Changeset 718 for trunk/platforms/tsar_generic_iob/tsar_iob_cluster
- Timestamp:
- Jun 24, 2014, 10:15:26 AM (10 years ago)
- Location:
- trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd
r693 r718 59 59 flit_width = parameter.Reference('dspin_int_rsp_width')), 60 60 61 Uses('caba:dspin_local_crossbar', 62 flit_width = parameter.Reference('dspin_ram_cmd_width')), 63 64 Uses('caba:dspin_local_crossbar', 65 flit_width = parameter.Reference('dspin_ram_rsp_width')), 66 61 67 Uses('caba:vci_dspin_initiator_wrapper', 62 68 cell_size = parameter.Reference('vci_data_width_int'), … … 86 92 dspin_rsp_width = parameter.Reference('dspin_ram_rsp_width')), 87 93 88 Uses('caba:dspin_router _tsar',94 Uses('caba:dspin_router', 89 95 flit_width = parameter.Reference('dspin_ram_cmd_width')), 90 96 91 Uses('caba:dspin_router _tsar',97 Uses('caba:dspin_router', 92 98 flit_width = parameter.Reference('dspin_ram_rsp_width')), 93 99 -
trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h
r714 r718 26 26 #include "vci_dspin_initiator_wrapper.h" 27 27 #include "vci_dspin_target_wrapper.h" 28 #include "dspin_router _tsar.h"28 #include "dspin_router.h" 29 29 #include "virtual_dspin_router.h" 30 30 #include "vci_multi_dma.h" … … 57 57 soclib::caba::VciTarget<vci_param_ext>* p_vci_iob_iox_tgt; 58 58 59 // These ports are used to connect IOB to RAM network in top cell60 soclib::caba::DspinOutput<dspin_ram_cmd_width>* p_dspin_iob_cmd_out;61 soclib::caba::DspinInput<dspin_ram_rsp_width>* p_dspin_iob_rsp_in;62 63 59 // These arrays of ports are used to connect the INT & RAM networks in top cell 64 60 soclib::caba::DspinOutput<dspin_int_cmd_width>** p_dspin_int_cmd_out; … … 116 112 VciSignals<vci_param_ext> signal_ram_vci_tgt_xram; 117 113 118 // RAM network DSPIN signals between VCI/DSPIN wrappers and routers 114 // RAM network DSPIN signals between VCI/DSPIN wrappers, RAM dspin crossbar 115 // and routers 119 116 DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_xram_t; 120 117 DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_xram_t; 121 118 DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_memc_i; 122 119 DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_memc_i; 120 DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_iob_i; 121 DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_iob_i; 122 DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_xbar; 123 DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_xbar; 124 DspinSignals<dspin_ram_cmd_width> signal_ram_dspin_cmd_false; 125 DspinSignals<dspin_ram_rsp_width> signal_ram_dspin_rsp_false; 123 126 124 127 ////////////////////////////////////// … … 166 169 dspin_ram_rsp_width>* xram_ram_wt; 167 170 168 DspinRouterTsar<dspin_ram_cmd_width>* ram_router_cmd; 169 DspinRouterTsar<dspin_ram_rsp_width>* ram_router_rsp; 171 DspinRouter<dspin_ram_cmd_width>* ram_router_cmd; 172 DspinRouter<dspin_ram_rsp_width>* ram_router_rsp; 173 174 DspinLocalCrossbar<dspin_ram_cmd_width>* ram_xbar_cmd; 175 DspinLocalCrossbar<dspin_ram_rsp_width>* ram_xbar_rsp; 176 170 177 171 178 // IO Network Components (not instanciated in all clusters) … … 177 184 dspin_ram_cmd_width, 178 185 dspin_ram_rsp_width>* iob_ram_wi; 179 186 180 187 // cluster constructor 181 188 TsarIobCluster( sc_module_name insname, … … 195 202 size_t l_width, // l field bits 196 203 197 size_t int_memc_tgtid, 198 size_t int_xicu_tgtid, 199 size_t int_mdma_tgtid, 200 size_t int_iobx_tgtid, 201 202 size_t int_proc_srcid, 203 size_t int_mdma_srcid, 204 size_t int_iobx_srcid, 205 206 size_t ext_xram_tgtid, 207 208 size_t ext_memc_srcid, 209 size_t ext_iobx_srcid, 204 size_t int_memc_tgt_id, 205 size_t int_xicu_tgt_id, 206 size_t int_mdma_tgt_id, 207 size_t int_iobx_tgt_id, 208 size_t int_proc_ini_id, 209 size_t int_mdma_ini_id, 210 size_t int_iobx_ini_id, 211 212 size_t ram_xram_tgt_id, 213 size_t ram_memc_ini_id, 214 size_t ram_iobx_ini_id, 215 216 bool is_io, 217 size_t iox_iobx_tgt_id, 218 size_t iox_iobx_ini_id, 210 219 211 220 size_t memc_ways, … … 226 235 bool iob0_debug_ok ); 227 236 237 protected: 238 239 SC_HAS_PROCESS(TsarIobCluster); 240 241 void init(); 242 243 228 244 }; 229 245 … … 231 247 232 248 #endif 249 250 // Local Variables: 251 // tab-width: 3 252 // c-basic-offset: 3 253 // c-file-offsets:((innamespace . 0)(inline-open . 0)) 254 // indent-tabs-mode: nil 255 // End: 256 257 // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 258 // -
trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp
r714 r718 15 15 #include "../include/tsar_iob_cluster.h" 16 16 17 #define tmpl(x) \ 18 template<typename vci_param_int , typename vci_param_ext,\ 19 size_t dspin_int_cmd_width, size_t dspin_int_rsp_width,\ 20 size_t dspin_ram_cmd_width, size_t dspin_ram_rsp_width>\ 21 x TsarIobCluster<\ 22 vci_param_int , vci_param_ext,\ 23 dspin_int_cmd_width, dspin_int_rsp_width,\ 24 dspin_ram_cmd_width, dspin_ram_rsp_width> 25 17 26 namespace soclib { namespace caba { 18 27 … … 20 29 // Constructor 21 30 ////////////////////////////////////////////////////////////////////////// 22 template<typename vci_param_int, 23 typename vci_param_ext, 24 size_t dspin_int_cmd_width, 25 size_t dspin_int_rsp_width, 26 size_t dspin_ram_cmd_width, 27 size_t dspin_ram_rsp_width> 28 TsarIobCluster<vci_param_int, 29 vci_param_ext, 30 dspin_int_cmd_width, 31 dspin_int_rsp_width, 32 dspin_ram_cmd_width, 33 dspin_ram_rsp_width>::TsarIobCluster( 31 tmpl(/**/)::TsarIobCluster( 34 32 ////////////////////////////////////////////////////////////////////////// 35 33 sc_module_name insname, … … 49 47 size_t l_width, 50 48 51 size_t memc_int_tgtid, // local index 52 size_t xicu_int_tgtid, // local index 53 size_t mdma_int_tgtid, // local index 54 size_t iobx_int_tgtid, // local index 55 56 size_t proc_int_srcid, // local index 57 size_t mdma_int_srcid, // local index 58 size_t iobx_int_srcid, // local index 59 60 size_t xram_ram_tgtid, // local index 61 62 size_t memc_ram_srcid, // local index 63 size_t iobx_ram_srcid, // local index 49 size_t int_memc_tgt_id, // local index 50 size_t int_xicu_tgt_id, // local index 51 size_t int_mdma_tgt_id, // local index 52 size_t int_iobx_tgt_id, // local index 53 54 size_t int_proc_ini_id, // local index 55 size_t int_mdma_ini_id, // local index 56 size_t int_iobx_ini_id, // local index 57 58 size_t ram_xram_tgt_id, // local index 59 size_t ram_memc_ini_id, // local index 60 size_t ram_iobx_ini_id, // local index 61 62 bool is_io, // is IO cluster (IOB)? 63 size_t iox_iobx_tgt_id, // local_index 64 size_t iox_iobx_ini_id, // local index 64 65 65 66 size_t memc_ways, … … 87 88 size_t cluster_id = (x_id<<4) + y_id; 88 89 89 size_t cluster_iob0 = 0; // South-West cluster90 size_t cluster_iob1 = ((xmax-1)<<4) + ymax-1; // North-East cluster91 92 90 // Vectors of DSPIN ports for inter-cluster communications 93 91 p_dspin_int_cmd_in = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3); … … 101 99 p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4); 102 100 103 // ports in cluster_iob0 and cluster_iob1 only 104 if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) 105 { 106 // VCI ports from IOB to IOX network 101 // VCI ports from IOB to IOX network (only in IO clusters) 102 if ( is_io ) 103 { 107 104 p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>; 108 105 p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>; 109 110 // DSPIN ports from IOB to RAM network111 p_dspin_iob_cmd_out = new soclib::caba::DspinOutput<dspin_ram_cmd_width>;112 p_dspin_iob_rsp_in = new soclib::caba::DspinInput<dspin_ram_rsp_width>;113 106 } 114 107 … … 135 128 8, // DTLB ways 136 129 8, // DTLB sets 137 l1_i_ways, l1_i_sets,16,// ICACHE size138 l1_d_ways, l1_d_sets,16,// DCACHE size130 l1_i_ways, l1_i_sets, 16, // ICACHE size 131 l1_d_ways, l1_d_sets, 16, // DCACHE size 139 132 4, // WBUF nlines 140 133 4, // WBUF nwords … … 154 147 dspin_int_cmd_width>( 155 148 s_memc.str().c_str(), 156 mt_int, // Mapping Table INT network157 mt_ram, // Mapping Table RAM network158 IntTab(cluster_id, memc_ram_srcid), // SRCID RAM network159 IntTab(cluster_id, memc_int_tgtid), // TGTID INT network160 x_width, // number of bits for x coordinate161 y_width, // number of bits for y coordinate162 memc_ways, memc_sets, 16, // CACHE SIZE163 3, // MAX NUMBER OF COPIES164 4096, // HEAP SIZE165 8, // TRANSACTION TABLE DEPTH166 8, // UPDATE TABLE DEPTH167 8, // INVALIDATE TABLE DEPTH149 mt_int, // Mapping Table INT network 150 mt_ram, // Mapping Table RAM network 151 IntTab(cluster_id, ram_memc_ini_id), // SRCID RAM network 152 IntTab(cluster_id, int_memc_tgt_id), // TGTID INT network 153 x_width, // number of bits for x coordinate 154 y_width, // number of bits for y coordinate 155 memc_ways, memc_sets, 16, // CACHE SIZE 156 3, // MAX NUMBER OF COPIES 157 4096, // HEAP SIZE 158 8, // TRANSACTION TABLE DEPTH 159 8, // UPDATE TABLE DEPTH 160 8, // INVALIDATE TABLE DEPTH 168 161 debug_start_cycle, 169 162 memc_debug_ok ); … … 182 175 xicu = new VciXicu<vci_param_int>( 183 176 s_xicu.str().c_str(), 184 mt_int, // mapping table INT network185 IntTab(cluster_id, xicu_int_tgtid), // TGTID direct space186 xcu_nb_inputs, // number of timer IRQs187 xcu_nb_inputs, // number of hard IRQs188 xcu_nb_inputs, // number of soft IRQs189 16); // number of output IRQs177 mt_int, // mapping table INT network 178 IntTab(cluster_id, int_xicu_tgt_id), // TGTID direct space 179 xcu_nb_inputs, // number of timer IRQs 180 xcu_nb_inputs, // number of hard IRQs 181 xcu_nb_inputs, // number of soft IRQs 182 16); // number of output IRQs 190 183 191 184 //////////// MDMA … … 196 189 mt_int, 197 190 IntTab(cluster_id, nb_procs), // SRCID 198 IntTab(cluster_id, mdma_int_tgtid),// TGTID191 IntTab(cluster_id, int_mdma_tgt_id), // TGTID 199 192 64, // burst size 200 193 nb_dmas); // number of IRQs 201 194 202 195 /////////// Direct LOCAL_XBAR(S) 203 size_t nb_direct_initiators = nb_procs + 1; 204 size_t nb_direct_targets = 3; 205 if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) ) 206 { 207 nb_direct_initiators = nb_procs + 2; 208 nb_direct_targets = 4; 209 } 196 size_t nb_direct_initiators = is_io ? nb_procs + 2 : nb_procs + 1; 197 size_t nb_direct_targets = is_io ? 4 : 3; 210 198 211 199 std::ostringstream s_int_xbar_d; … … 304 292 xram = new VciSimpleRam<vci_param_ext>( 305 293 s_xram.str().c_str(), 306 IntTab(cluster_id, xram_ram_tgtid),294 IntTab(cluster_id, ram_xram_tgt_id), 307 295 mt_ram, 308 296 loader, … … 320 308 std::ostringstream s_ram_router_cmd; 321 309 s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id; 322 size_t is_iob0 = (x_id == 0) and (y_id == 0); 323 size_t is_iob1 = (x_id == (xmax-1)) and (y_id == (ymax-1)); 324 ram_router_cmd = new DspinRouterTsar<dspin_ram_cmd_width>( 310 ram_router_cmd = new DspinRouter<dspin_ram_cmd_width>( 325 311 s_ram_router_cmd.str().c_str(), 326 312 x_id, y_id, // router coordinates in mesh 327 313 x_width, // x field width in first flit 328 314 y_width, // y field width in first flit 329 4, 4, // input & output fifo depths 330 is_iob0, // cluster contains IOB0 331 is_iob1, // cluster contains IOB1 332 false, // not a response router 333 l_width); // local field width in first flit 315 4, 4); // input & output fifo depths 334 316 335 317 std::ostringstream s_ram_router_rsp; 336 318 s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id; 337 ram_router_rsp = new DspinRouter Tsar<dspin_ram_rsp_width>(319 ram_router_rsp = new DspinRouter<dspin_ram_rsp_width>( 338 320 s_ram_router_rsp.str().c_str(), 339 321 x_id, y_id, // coordinates in mesh 340 322 x_width, // x field width in first flit 341 323 y_width, // y field width in first flit 342 4, 4, // input & output fifo depths 343 is_iob0, // cluster contains IOB0 344 is_iob1, // cluster contains IOB1 345 true, // response router 346 l_width); // local field width in first flit 324 4, 4); // input & output fifo depths 347 325 348 326 349 327 ////////////////////// I/O CLUSTER ONLY /////////////////////// 350 if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1))328 if ( is_io ) 351 329 { 352 330 /////////// IO_BRIDGE 353 size_t iox_local_id;354 size_t global_id;355 if ( cluster_id == cluster_iob0 )356 {357 iox_local_id = 0;358 global_id = cluster_iob0;359 }360 else361 {362 iox_local_id = 1;363 global_id = cluster_iob1;364 }365 366 331 std::ostringstream s_iob; 367 332 s_iob << "iob_" << x_id << "_" << y_id; … … 369 334 vci_param_ext>( 370 335 s_iob.str().c_str(), 371 mt_ram, // EXT network maptab 372 mt_int, // INT network maptab 373 mt_iox, // IOX network maptab 374 IntTab( global_id, iobx_int_tgtid ), // INT TGTID 375 IntTab( global_id, iobx_int_srcid ), // INT SRCID 376 IntTab( global_id, iox_local_id ), // IOX TGTID 377 16, // cache line words 378 8, // IOTLB ways 379 8, // IOTLB sets 336 mt_ram, // EXT network maptab 337 mt_int, // INT network maptab 338 mt_iox, // IOX network maptab 339 IntTab( cluster_id, int_iobx_tgt_id ), // INT TGTID 340 IntTab( cluster_id, int_iobx_ini_id ), // INT SRCID 341 IntTab( 0 , iox_iobx_tgt_id ), // IOX TGTID 342 IntTab( 0 , iox_iobx_ini_id ), // IOX SRCID 343 16, // cache line words 344 8, // IOTLB ways 345 8, // IOTLB sets 380 346 debug_start_cycle, 381 347 iob_debug_ok ); … … 387 353 dspin_ram_rsp_width>( 388 354 s_iob_ram_wi.str().c_str(), 389 x_width + y_width + l_width); 355 vci_param_int::S); 356 357 std::ostringstream s_ram_xbar_cmd; 358 s_ram_xbar_cmd << "s_ram_xbar_cmd_" << x_id << "_" << y_id; 359 ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>( 360 s_ram_xbar_cmd.str().c_str(), // name 361 mt_ram, // mapping table 362 x_id, y_id, // x, y 363 x_width, y_width, l_width, // x_width, y_width, l_width 364 2, 0, // local inputs, local outputs 365 2, 2, // in fifo, out fifo depths 366 true, // is cmd ? 367 false, // use routing table ? 368 false); // support broadcast ? 369 370 std::ostringstream s_ram_xbar_rsp; 371 s_ram_xbar_rsp << "s_ram_xbar_rsp_" << x_id << "_" << y_id; 372 ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>( 373 s_ram_xbar_rsp.str().c_str(), // name 374 mt_ram, // mapping table 375 x_id, y_id, // x, y 376 x_width, y_width, l_width, // x_width, y_width, l_width 377 0, 2, // local inputs, local outputs 378 2, 2, // in fifo, out fifo depths 379 false, // is cmd ? 380 true, // use routing table ? 381 false); // support broadcast ? 390 382 } // end if IO 391 383 … … 396 388 // on coherence network : local srcid[proc] in [0...nb_procs-1] 397 389 // : local srcid[memc] = nb_procs 398 // In cluster_iob0, 32 HWI interrupts from external peripherals399 // are connected to the XICU ports p_hwi[0:31]400 // In other clusters, no HWI interrupts are connected to XICU401 390 402 391 //////////////////////// internal CMD & RSP routers … … 440 429 int_xbar_d->p_target_to_up (signal_int_vci_g2l); 441 430 442 int_xbar_d->p_to_target[ memc_int_tgtid](signal_int_vci_tgt_memc);443 int_xbar_d->p_to_target[ xicu_int_tgtid](signal_int_vci_tgt_xicu);444 int_xbar_d->p_to_target[ mdma_int_tgtid](signal_int_vci_tgt_mdma);445 int_xbar_d->p_to_initiator[ mdma_int_srcid](signal_int_vci_ini_mdma);431 int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc); 432 int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu); 433 int_xbar_d->p_to_target[int_mdma_tgt_id] (signal_int_vci_tgt_mdma); 434 int_xbar_d->p_to_initiator[int_mdma_ini_id] (signal_int_vci_ini_mdma); 446 435 for (size_t p = 0; p < nb_procs; p++) 447 int_xbar_d->p_to_initiator[ proc_int_srcid + p] (signal_int_vci_ini_proc[p]);448 449 if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1))450 { 451 int_xbar_d->p_to_target[i obx_int_tgtid] (signal_int_vci_tgt_iobx);452 int_xbar_d->p_to_initiator[i obx_int_srcid] (signal_int_vci_ini_iobx);436 int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]); 437 438 if ( is_io ) 439 { 440 int_xbar_d->p_to_target[int_iobx_tgt_id] (signal_int_vci_tgt_iobx); 441 int_xbar_d->p_to_initiator[int_iobx_ini_id] (signal_int_vci_ini_iobx); 453 442 } 454 443 … … 573 562 ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]); 574 563 } 564 575 565 ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t); 576 ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i);577 ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i);578 566 ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t); 567 568 if ( is_io ) 569 { 570 ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_xbar); 571 ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_xbar); 572 } 573 else 574 { 575 ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i); 576 ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i); 577 } 579 578 580 579 ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. 581 if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1))580 if ( is_io ) 582 581 { 583 582 // IO bridge 584 iob->p_clk (this->p_clk);585 iob->p_resetn (this->p_resetn);586 iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini));587 iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt));588 iob->p_vci_tgt_int (signal_int_vci_tgt_iobx);589 iob->p_vci_ini_int (signal_int_vci_ini_iobx);590 iob->p_vci_ini_ram (signal_ram_vci_ini_iobx);583 iob->p_clk (this->p_clk); 584 iob->p_resetn (this->p_resetn); 585 iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini)); 586 iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt)); 587 iob->p_vci_tgt_int (signal_int_vci_tgt_iobx); 588 iob->p_vci_ini_int (signal_int_vci_ini_iobx); 589 iob->p_vci_ini_ram (signal_ram_vci_ini_iobx); 591 590 592 591 // initiator wrapper to RAM network 593 iob_ram_wi->p_clk (this->p_clk); 594 iob_ram_wi->p_resetn (this->p_resetn); 595 iob_ram_wi->p_dspin_cmd (*(this->p_dspin_iob_cmd_out)); 596 iob_ram_wi->p_dspin_rsp (*(this->p_dspin_iob_rsp_in)); 597 iob_ram_wi->p_vci (signal_ram_vci_ini_iobx); 598 } 599 592 iob_ram_wi->p_clk (this->p_clk); 593 iob_ram_wi->p_resetn (this->p_resetn); 594 iob_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_iob_i); 595 iob_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_iob_i); 596 iob_ram_wi->p_vci (signal_ram_vci_ini_iobx); 597 598 // crossbar between MEMC and IOB to RAM network 599 ram_xbar_cmd->p_clk (this->p_clk); 600 ram_xbar_cmd->p_resetn (this->p_resetn); 601 ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_xbar); 602 ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_false); 603 ram_xbar_cmd->p_local_in[ram_memc_ini_id] (signal_ram_dspin_cmd_memc_i); 604 ram_xbar_cmd->p_local_in[ram_iobx_ini_id] (signal_ram_dspin_cmd_iob_i); 605 606 ram_xbar_rsp->p_clk (this->p_clk); 607 ram_xbar_rsp->p_resetn (this->p_resetn); 608 ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_false); 609 ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_xbar); 610 ram_xbar_rsp->p_local_out[ram_memc_ini_id] (signal_ram_dspin_rsp_memc_i); 611 ram_xbar_rsp->p_local_out[ram_iobx_ini_id] (signal_ram_dspin_rsp_iob_i); 612 } 613 614 SC_METHOD(init); 600 615 } // end constructor 616 617 tmpl(void)::init() 618 { 619 signal_ram_dspin_cmd_false.write = false; 620 signal_ram_dspin_cmd_false.read = true; 621 signal_ram_dspin_rsp_false.write = false; 622 signal_ram_dspin_rsp_false.read = true; 623 } // end init 601 624 602 625 }} … … 612 635 // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 613 636 614 615
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