Index: trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd
===================================================================
--- trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd	(revision 714)
+++ trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd	(revision 718)
@@ -59,4 +59,10 @@
               flit_width         = parameter.Reference('dspin_int_rsp_width')),
 
+        Uses('caba:dspin_local_crossbar', 
+              flit_width         = parameter.Reference('dspin_ram_cmd_width')),
+
+        Uses('caba:dspin_local_crossbar', 
+              flit_width         = parameter.Reference('dspin_ram_rsp_width')),
+
         Uses('caba:vci_dspin_initiator_wrapper', 
               cell_size          = parameter.Reference('vci_data_width_int'),
@@ -86,8 +92,8 @@
               dspin_rsp_width    = parameter.Reference('dspin_ram_rsp_width')),
 
-        Uses('caba:dspin_router_tsar', 
+        Uses('caba:dspin_router', 
               flit_width         = parameter.Reference('dspin_ram_cmd_width')),
 
-        Uses('caba:dspin_router_tsar', 
+        Uses('caba:dspin_router', 
               flit_width         = parameter.Reference('dspin_ram_rsp_width')),
 
Index: trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h
===================================================================
--- trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h	(revision 714)
+++ trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h	(revision 718)
@@ -26,5 +26,5 @@
 #include "vci_dspin_initiator_wrapper.h"
 #include "vci_dspin_target_wrapper.h"
-#include "dspin_router_tsar.h"
+#include "dspin_router.h"
 #include "virtual_dspin_router.h"
 #include "vci_multi_dma.h"
@@ -57,8 +57,4 @@
     soclib::caba::VciTarget<vci_param_ext>*            p_vci_iob_iox_tgt; 
 
-    // These ports are used to connect IOB to RAM network in top cell
-    soclib::caba::DspinOutput<dspin_ram_cmd_width>*    p_dspin_iob_cmd_out;  
-    soclib::caba::DspinInput<dspin_ram_rsp_width>*     p_dspin_iob_rsp_in;  
-
     // These arrays of ports are used to connect the INT & RAM networks in top cell
     soclib::caba::DspinOutput<dspin_int_cmd_width>**   p_dspin_int_cmd_out;
@@ -116,9 +112,16 @@
     VciSignals<vci_param_ext>             signal_ram_vci_tgt_xram;
 
-    // RAM network DSPIN signals between VCI/DSPIN wrappers and routers 
+    // RAM network DSPIN signals between VCI/DSPIN wrappers, RAM dspin crossbar
+    // and routers 
     DspinSignals<dspin_ram_cmd_width>     signal_ram_dspin_cmd_xram_t;
     DspinSignals<dspin_ram_rsp_width>     signal_ram_dspin_rsp_xram_t;
     DspinSignals<dspin_ram_cmd_width>     signal_ram_dspin_cmd_memc_i;
     DspinSignals<dspin_ram_rsp_width>     signal_ram_dspin_rsp_memc_i;
+    DspinSignals<dspin_ram_cmd_width>     signal_ram_dspin_cmd_iob_i;
+    DspinSignals<dspin_ram_rsp_width>     signal_ram_dspin_rsp_iob_i;
+    DspinSignals<dspin_ram_cmd_width>     signal_ram_dspin_cmd_xbar;
+    DspinSignals<dspin_ram_rsp_width>     signal_ram_dspin_rsp_xbar;
+    DspinSignals<dspin_ram_cmd_width>     signal_ram_dspin_cmd_false;
+    DspinSignals<dspin_ram_rsp_width>     signal_ram_dspin_rsp_false;
   
     //////////////////////////////////////
@@ -166,6 +169,10 @@
                           dspin_ram_rsp_width>*       xram_ram_wt;
     
-    DspinRouterTsar<dspin_ram_cmd_width>*             ram_router_cmd;
-    DspinRouterTsar<dspin_ram_rsp_width>*             ram_router_rsp;
+    DspinRouter<dspin_ram_cmd_width>*                 ram_router_cmd;
+    DspinRouter<dspin_ram_rsp_width>*                 ram_router_rsp;
+
+    DspinLocalCrossbar<dspin_ram_cmd_width>*          ram_xbar_cmd;
+    DspinLocalCrossbar<dspin_ram_rsp_width>*          ram_xbar_rsp;
+    
 
     // IO Network Components (not instanciated in all clusters)
@@ -177,5 +184,5 @@
                              dspin_ram_cmd_width,
                              dspin_ram_rsp_width>*    iob_ram_wi;
-    
+
     // cluster constructor
     TsarIobCluster( sc_module_name                     insname,
@@ -195,17 +202,19 @@
                     size_t                             l_width,       // l field  bits
 
-                    size_t                             int_memc_tgtid,
-                    size_t                             int_xicu_tgtid,
-                    size_t                             int_mdma_tgtid,
-                    size_t                             int_iobx_tgtid,
-
-                    size_t                             int_proc_srcid,
-                    size_t                             int_mdma_srcid,
-                    size_t                             int_iobx_srcid,
-
-                    size_t                             ext_xram_tgtid,
-
-                    size_t                             ext_memc_srcid,
-                    size_t                             ext_iobx_srcid,
+                    size_t                             int_memc_tgt_id,
+                    size_t                             int_xicu_tgt_id,
+                    size_t                             int_mdma_tgt_id,
+                    size_t                             int_iobx_tgt_id,
+                    size_t                             int_proc_ini_id,
+                    size_t                             int_mdma_ini_id,
+                    size_t                             int_iobx_ini_id,
+
+                    size_t                             ram_xram_tgt_id,
+                    size_t                             ram_memc_ini_id,
+                    size_t                             ram_iobx_ini_id,
+
+                    bool                               is_io,
+                    size_t                             iox_iobx_tgt_id,
+                    size_t                             iox_iobx_ini_id,
 
                     size_t                             memc_ways,
@@ -226,4 +235,11 @@
                     bool                               iob0_debug_ok ); 
 
+  protected:
+
+    SC_HAS_PROCESS(TsarIobCluster);
+
+    void init();
+ 
+
 };
 
@@ -231,2 +247,12 @@
 
 #endif
+
+// Local Variables:
+// tab-width: 3
+// c-basic-offset: 3
+// c-file-offsets:((innamespace . 0)(inline-open . 0))
+// indent-tabs-mode: nil
+// End:
+
+// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
+//
Index: trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp
===================================================================
--- trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp	(revision 714)
+++ trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp	(revision 718)
@@ -15,4 +15,13 @@
 #include "../include/tsar_iob_cluster.h"
 
+#define tmpl(x) \
+   template<typename vci_param_int      , typename vci_param_ext,\
+            size_t   dspin_int_cmd_width, size_t   dspin_int_rsp_width,\
+            size_t   dspin_ram_cmd_width, size_t   dspin_ram_rsp_width>\
+            x TsarIobCluster<\
+                  vci_param_int      , vci_param_ext,\
+                  dspin_int_cmd_width, dspin_int_rsp_width,\
+                  dspin_ram_cmd_width, dspin_ram_rsp_width>
+
 namespace soclib { namespace caba  {
 
@@ -20,16 +29,5 @@
 //                 Constructor
 //////////////////////////////////////////////////////////////////////////
-template<typename vci_param_int, 
-         typename vci_param_ext,
-         size_t   dspin_int_cmd_width, 
-         size_t   dspin_int_rsp_width,
-         size_t   dspin_ram_cmd_width, 
-         size_t   dspin_ram_rsp_width>
-TsarIobCluster<vci_param_int, 
-               vci_param_ext,
-               dspin_int_cmd_width, 
-               dspin_int_rsp_width,
-               dspin_ram_cmd_width, 
-               dspin_ram_rsp_width>::TsarIobCluster(
+tmpl(/**/)::TsarIobCluster(
 //////////////////////////////////////////////////////////////////////////
                     sc_module_name                     insname,
@@ -49,17 +47,20 @@
                     size_t                             l_width,
 
-                    size_t                             memc_int_tgtid,  // local index
-                    size_t                             xicu_int_tgtid,  // local index
-                    size_t                             mdma_int_tgtid,  // local index
-                    size_t                             iobx_int_tgtid,  // local index
-
-                    size_t                             proc_int_srcid,  // local index
-                    size_t                             mdma_int_srcid,  // local index
-                    size_t                             iobx_int_srcid,  // local index
-
-                    size_t                             xram_ram_tgtid,  // local index
-
-                    size_t                             memc_ram_srcid,  // local index
-                    size_t                             iobx_ram_srcid,  // local index
+                    size_t                             int_memc_tgt_id, // local index
+                    size_t                             int_xicu_tgt_id, // local index
+                    size_t                             int_mdma_tgt_id, // local index
+                    size_t                             int_iobx_tgt_id, // local index
+
+                    size_t                             int_proc_ini_id, // local index
+                    size_t                             int_mdma_ini_id, // local index
+                    size_t                             int_iobx_ini_id, // local index
+
+                    size_t                             ram_xram_tgt_id, // local index
+                    size_t                             ram_memc_ini_id, // local index
+                    size_t                             ram_iobx_ini_id, // local index
+
+                    bool                               is_io,           // is IO cluster (IOB)?
+                    size_t                             iox_iobx_tgt_id, // local_index
+                    size_t                             iox_iobx_ini_id, // local index
 
                     size_t                             memc_ways,
@@ -87,7 +88,4 @@
     size_t cluster_id = (x_id<<4) + y_id;
 
-    size_t cluster_iob0 = 0;                            // South-West cluster
-    size_t cluster_iob1 = ((xmax-1)<<4) + ymax-1;       // North-East cluster
-
     // Vectors of DSPIN ports for inter-cluster communications
     p_dspin_int_cmd_in  = alloc_elems<DspinInput<dspin_int_cmd_width> >("p_int_cmd_in", 4, 3);
@@ -101,14 +99,9 @@
     p_dspin_ram_rsp_out = alloc_elems<DspinOutput<dspin_ram_rsp_width> >("p_ext_rsp_out", 4);
 
-    // ports in cluster_iob0 and cluster_iob1 only
-    if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) )
-    {
-        // VCI ports from IOB to IOX network
+    // VCI ports from IOB to IOX network (only in IO clusters)
+    if ( is_io )
+    {
         p_vci_iob_iox_ini = new soclib::caba::VciInitiator<vci_param_ext>;
         p_vci_iob_iox_tgt = new soclib::caba::VciTarget<vci_param_ext>; 
-
-        // DSPIN ports from IOB to RAM network
-        p_dspin_iob_cmd_out = new soclib::caba::DspinOutput<dspin_ram_cmd_width>;
-        p_dspin_iob_rsp_in  = new soclib::caba::DspinInput<dspin_ram_rsp_width>;
     }
 
@@ -135,6 +128,6 @@
                       8,                              // DTLB ways
                       8,                              // DTLB sets
-                      l1_i_ways,l1_i_sets,16,         // ICACHE size
-                      l1_d_ways,l1_d_sets,16,         // DCACHE size
+                      l1_i_ways, l1_i_sets, 16,       // ICACHE size
+                      l1_d_ways, l1_d_sets, 16,       // DCACHE size
                       4,                              // WBUF nlines
                       4,                              // WBUF nwords
@@ -154,16 +147,16 @@
                            dspin_int_cmd_width>(
                      s_memc.str().c_str(),
-                     mt_int,                             // Mapping Table INT network
-                     mt_ram,                             // Mapping Table RAM network
-                     IntTab(cluster_id, memc_ram_srcid), // SRCID RAM network
-                     IntTab(cluster_id, memc_int_tgtid), // TGTID INT network
-                     x_width,                            // number of bits for x coordinate
-                     y_width,                            // number of bits for y coordinate
-                     memc_ways, memc_sets, 16,           // CACHE SIZE
-                     3,                                  // MAX NUMBER OF COPIES
-                     4096,                               // HEAP SIZE
-                     8,                                  // TRANSACTION TABLE DEPTH
-                     8,                                  // UPDATE TABLE DEPTH
-                     8,                                  // INVALIDATE TABLE DEPTH
+                     mt_int,                              // Mapping Table INT network
+                     mt_ram,                              // Mapping Table RAM network
+                     IntTab(cluster_id, ram_memc_ini_id), // SRCID RAM network
+                     IntTab(cluster_id, int_memc_tgt_id), // TGTID INT network
+                     x_width,                             // number of bits for x coordinate
+                     y_width,                             // number of bits for y coordinate
+                     memc_ways, memc_sets, 16,            // CACHE SIZE
+                     3,                                   // MAX NUMBER OF COPIES
+                     4096,                                // HEAP SIZE
+                     8,                                   // TRANSACTION TABLE DEPTH
+                     8,                                   // UPDATE TABLE DEPTH
+                     8,                                   // INVALIDATE TABLE DEPTH
                      debug_start_cycle,
                      memc_debug_ok );
@@ -182,10 +175,10 @@
     xicu = new VciXicu<vci_param_int>(
                      s_xicu.str().c_str(),
-                     mt_int,                            // mapping table INT network
-                     IntTab(cluster_id,xicu_int_tgtid), // TGTID direct space
-                     xcu_nb_inputs,                     // number of timer IRQs
-                     xcu_nb_inputs,                     // number of hard IRQs
-                     xcu_nb_inputs,                     // number of soft IRQs
-                     16);                               // number of output IRQs
+                     mt_int,                              // mapping table INT network
+                     IntTab(cluster_id, int_xicu_tgt_id), // TGTID direct space
+                     xcu_nb_inputs,                       // number of timer IRQs
+                     xcu_nb_inputs,                       // number of hard IRQs
+                     xcu_nb_inputs,                       // number of soft IRQs
+                     16);                                 // number of output IRQs
 
     ////////////  MDMA
@@ -196,16 +189,11 @@
                      mt_int,
                      IntTab(cluster_id, nb_procs),        // SRCID
-                     IntTab(cluster_id, mdma_int_tgtid),  // TGTID
+                     IntTab(cluster_id, int_mdma_tgt_id), // TGTID
                      64,                                  // burst size
                      nb_dmas);                            // number of IRQs
 
     ///////////  Direct LOCAL_XBAR(S)
-    size_t nb_direct_initiators      = nb_procs + 1;
-    size_t nb_direct_targets         = 3;
-    if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) )
-    {
-        nb_direct_initiators         = nb_procs + 2;
-        nb_direct_targets            = 4;
-    }
+    size_t nb_direct_initiators = is_io ? nb_procs + 2 : nb_procs + 1;
+    size_t nb_direct_targets    = is_io ? 4 : 3;
 
     std::ostringstream s_int_xbar_d;
@@ -304,5 +292,5 @@
     xram = new VciSimpleRam<vci_param_ext>(
                      s_xram.str().c_str(),
-                     IntTab(cluster_id, xram_ram_tgtid ),
+                     IntTab(cluster_id, ram_xram_tgt_id),
                      mt_ram,
                      loader,
@@ -320,48 +308,25 @@
     std::ostringstream s_ram_router_cmd;
     s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id;
-    size_t is_iob0 = (x_id == 0) and (y_id == 0);
-    size_t is_iob1 = (x_id == (xmax-1)) and (y_id == (ymax-1));
-    ram_router_cmd = new DspinRouterTsar<dspin_ram_cmd_width>(
+    ram_router_cmd = new DspinRouter<dspin_ram_cmd_width>(
                      s_ram_router_cmd.str().c_str(),
                      x_id, y_id,                     // router coordinates in mesh
                      x_width,                        // x field width in first flit
                      y_width,                        // y field width in first flit
-                     4, 4,                           // input & output fifo depths
-                     is_iob0,                        // cluster contains IOB0
-                     is_iob1,                        // cluster contains IOB1
-                     false,                          // not a response router
-                     l_width);                       // local field width in first flit
+                     4, 4);                          // input & output fifo depths
 
     std::ostringstream s_ram_router_rsp;
     s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id;
-    ram_router_rsp = new DspinRouterTsar<dspin_ram_rsp_width>(
+    ram_router_rsp = new DspinRouter<dspin_ram_rsp_width>(
                      s_ram_router_rsp.str().c_str(),
                      x_id, y_id,                     // coordinates in mesh
                      x_width,                        // x field width in first flit
                      y_width,                        // y field width in first flit
-                     4, 4,                           // input & output fifo depths
-                     is_iob0,                        // cluster contains IOB0
-                     is_iob1,                        // cluster contains IOB1
-                     true,                           // response router
-                     l_width);                       // local field width in first flit
+                     4, 4);                          // input & output fifo depths
 
 
     ////////////////////// I/O  CLUSTER ONLY    ///////////////////////
-    if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) )
+    if ( is_io )
     {
         ///////////  IO_BRIDGE
-        size_t iox_local_id;
-        size_t global_id;
-        if ( cluster_id == cluster_iob0 ) 
-        {
-            iox_local_id = 0;
-            global_id    = cluster_iob0;
-        }
-        else
-        {
-            iox_local_id = 1;
-            global_id    = cluster_iob1;
-        }
-
         std::ostringstream s_iob;
         s_iob << "iob_" << x_id << "_" << y_id;   
@@ -369,13 +334,14 @@
                               vci_param_ext>(  
                      s_iob.str().c_str(),
-                     mt_ram,                               // EXT network maptab
-                     mt_int,                               // INT network maptab
-                     mt_iox,                               // IOX network maptab
-                     IntTab( global_id, iobx_int_tgtid ),  // INT TGTID
-                     IntTab( global_id, iobx_int_srcid ),  // INT SRCID
-                     IntTab( global_id, iox_local_id   ),  // IOX TGTID
-                     16,                                   // cache line words
-                     8,                                    // IOTLB ways
-                     8,                                    // IOTLB sets
+                     mt_ram,                                // EXT network maptab
+                     mt_int,                                // INT network maptab
+                     mt_iox,                                // IOX network maptab
+                     IntTab( cluster_id, int_iobx_tgt_id ), // INT TGTID
+                     IntTab( cluster_id, int_iobx_ini_id ), // INT SRCID
+                     IntTab( 0         , iox_iobx_tgt_id ), // IOX TGTID
+                     IntTab( 0         , iox_iobx_ini_id ), // IOX SRCID
+                     16,                                    // cache line words
+                     8,                                     // IOTLB ways
+                     8,                                     // IOTLB sets
                      debug_start_cycle,
                      iob_debug_ok );
@@ -387,5 +353,31 @@
                                                   dspin_ram_rsp_width>(
                      s_iob_ram_wi.str().c_str(),
-                     x_width + y_width + l_width);
+                     vci_param_int::S);
+
+        std::ostringstream s_ram_xbar_cmd;
+        s_ram_xbar_cmd << "s_ram_xbar_cmd_" << x_id << "_" << y_id;
+        ram_xbar_cmd = new DspinLocalCrossbar<dspin_ram_cmd_width>(
+              s_ram_xbar_cmd.str().c_str(), // name
+              mt_ram,                       // mapping table
+              x_id, y_id,                   // x, y
+              x_width, y_width, l_width,    // x_width, y_width, l_width
+              2, 0,                         // local inputs, local outputs
+              2, 2,                         // in fifo, out fifo depths
+              true,                         // is cmd ?
+              false,                        // use routing table ?
+              false);                       // support broadcast ?
+
+        std::ostringstream s_ram_xbar_rsp;
+        s_ram_xbar_rsp << "s_ram_xbar_rsp_" << x_id << "_" << y_id;
+        ram_xbar_rsp = new DspinLocalCrossbar<dspin_ram_rsp_width>(
+              s_ram_xbar_rsp.str().c_str(), // name
+              mt_ram,                       // mapping table
+              x_id, y_id,                   // x, y
+              x_width, y_width, l_width,    // x_width, y_width, l_width
+              0, 2,                         // local inputs, local outputs
+              2, 2,                         // in fifo, out fifo depths
+              false,                        // is cmd ?
+              true,                         // use routing table ?
+              false);                       // support broadcast ?
     } // end if IO
 
@@ -396,7 +388,4 @@
     // on coherence network : local srcid[proc] in [0...nb_procs-1]
     //                      : local srcid[memc] = nb_procs
-    // In cluster_iob0, 32 HWI interrupts from external peripherals
-    // are connected to the XICU ports p_hwi[0:31] 
-    // In other clusters, no HWI interrupts are connected to XICU
  
     //////////////////////// internal CMD & RSP routers
@@ -440,15 +429,15 @@
     int_xbar_d->p_target_to_up                        (signal_int_vci_g2l);
 
-    int_xbar_d->p_to_target[memc_int_tgtid]           (signal_int_vci_tgt_memc);
-    int_xbar_d->p_to_target[xicu_int_tgtid]           (signal_int_vci_tgt_xicu);
-    int_xbar_d->p_to_target[mdma_int_tgtid]           (signal_int_vci_tgt_mdma);
-    int_xbar_d->p_to_initiator[mdma_int_srcid]        (signal_int_vci_ini_mdma);
+    int_xbar_d->p_to_target[int_memc_tgt_id]          (signal_int_vci_tgt_memc);
+    int_xbar_d->p_to_target[int_xicu_tgt_id]          (signal_int_vci_tgt_xicu);
+    int_xbar_d->p_to_target[int_mdma_tgt_id]          (signal_int_vci_tgt_mdma);
+    int_xbar_d->p_to_initiator[int_mdma_ini_id]       (signal_int_vci_ini_mdma);
     for (size_t p = 0; p < nb_procs; p++)
-       int_xbar_d->p_to_initiator[proc_int_srcid + p] (signal_int_vci_ini_proc[p]);
-
-    if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) )
-    {
-       int_xbar_d->p_to_target[iobx_int_tgtid]        (signal_int_vci_tgt_iobx);
-       int_xbar_d->p_to_initiator[iobx_int_srcid]     (signal_int_vci_ini_iobx);
+       int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]);
+
+    if ( is_io )
+    {
+       int_xbar_d->p_to_target[int_iobx_tgt_id]        (signal_int_vci_tgt_iobx);
+       int_xbar_d->p_to_initiator[int_iobx_ini_id]     (signal_int_vci_ini_iobx);
     }
 
@@ -573,30 +562,64 @@
         ram_router_rsp->p_in[n]                  (this->p_dspin_ram_rsp_in[n]);
     }
+
     ram_router_cmd->p_out[4]                     (signal_ram_dspin_cmd_xram_t);
-    ram_router_cmd->p_in[4]                      (signal_ram_dspin_cmd_memc_i);
-    ram_router_rsp->p_out[4]                     (signal_ram_dspin_rsp_memc_i);
     ram_router_rsp->p_in[4]                      (signal_ram_dspin_rsp_xram_t);
+
+    if ( is_io )
+    {
+       ram_router_cmd->p_in[4]                   (signal_ram_dspin_cmd_xbar);
+       ram_router_rsp->p_out[4]                  (signal_ram_dspin_rsp_xbar);
+    }
+    else
+    {
+       ram_router_cmd->p_in[4]                   (signal_ram_dspin_cmd_memc_i);
+       ram_router_rsp->p_out[4]                  (signal_ram_dspin_rsp_memc_i);
+    }
    
     ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. 
-    if ( (cluster_id == cluster_iob0) or (cluster_id == cluster_iob1) )
+    if ( is_io )
     {
         // IO bridge
-        iob->p_clk                               (this->p_clk);
-        iob->p_resetn                            (this->p_resetn);
-        iob->p_vci_ini_iox                       (*(this->p_vci_iob_iox_ini));
-        iob->p_vci_tgt_iox                       (*(this->p_vci_iob_iox_tgt));
-        iob->p_vci_tgt_int                       (signal_int_vci_tgt_iobx);
-        iob->p_vci_ini_int                       (signal_int_vci_ini_iobx);
-        iob->p_vci_ini_ram                       (signal_ram_vci_ini_iobx);
+        iob->p_clk                                 (this->p_clk);
+        iob->p_resetn                              (this->p_resetn);
+        iob->p_vci_ini_iox                         (*(this->p_vci_iob_iox_ini));
+        iob->p_vci_tgt_iox                         (*(this->p_vci_iob_iox_tgt));
+        iob->p_vci_tgt_int                         (signal_int_vci_tgt_iobx);
+        iob->p_vci_ini_int                         (signal_int_vci_ini_iobx);
+        iob->p_vci_ini_ram                         (signal_ram_vci_ini_iobx);
 
         // initiator wrapper to RAM network
-        iob_ram_wi->p_clk                        (this->p_clk);
-        iob_ram_wi->p_resetn                     (this->p_resetn);
-        iob_ram_wi->p_dspin_cmd                  (*(this->p_dspin_iob_cmd_out));
-        iob_ram_wi->p_dspin_rsp                  (*(this->p_dspin_iob_rsp_in));
-        iob_ram_wi->p_vci                        (signal_ram_vci_ini_iobx);
-    }
-
+        iob_ram_wi->p_clk                          (this->p_clk);
+        iob_ram_wi->p_resetn                       (this->p_resetn);
+        iob_ram_wi->p_dspin_cmd                    (signal_ram_dspin_cmd_iob_i);
+        iob_ram_wi->p_dspin_rsp                    (signal_ram_dspin_rsp_iob_i);
+        iob_ram_wi->p_vci                          (signal_ram_vci_ini_iobx);
+
+        // crossbar between MEMC and IOB to RAM network
+        ram_xbar_cmd->p_clk                        (this->p_clk);
+        ram_xbar_cmd->p_resetn                     (this->p_resetn);
+        ram_xbar_cmd->p_global_out                 (signal_ram_dspin_cmd_xbar);
+        ram_xbar_cmd->p_global_in                  (signal_ram_dspin_cmd_false);
+        ram_xbar_cmd->p_local_in[ram_memc_ini_id]  (signal_ram_dspin_cmd_memc_i);
+        ram_xbar_cmd->p_local_in[ram_iobx_ini_id]  (signal_ram_dspin_cmd_iob_i);
+
+        ram_xbar_rsp->p_clk                        (this->p_clk);
+        ram_xbar_rsp->p_resetn                     (this->p_resetn);
+        ram_xbar_rsp->p_global_out                 (signal_ram_dspin_rsp_false);
+        ram_xbar_rsp->p_global_in                  (signal_ram_dspin_rsp_xbar);
+        ram_xbar_rsp->p_local_out[ram_memc_ini_id] (signal_ram_dspin_rsp_memc_i);
+        ram_xbar_rsp->p_local_out[ram_iobx_ini_id] (signal_ram_dspin_rsp_iob_i);
+    }
+
+   SC_METHOD(init);
 } // end constructor
+
+tmpl(void)::init()
+{
+   signal_ram_dspin_cmd_false.write = false;
+   signal_ram_dspin_cmd_false.read = true;
+   signal_ram_dspin_rsp_false.write = false;
+   signal_ram_dspin_rsp_false.read = true;
+} // end init
 
 }}
@@ -612,4 +635,2 @@
 // vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3
 
-
-
