Ignore:
Timestamp:
Jun 24, 2014, 5:30:03 PM (11 years ago)
Author:
haoliu
Message:

MESI: some modifications have been done for the MESI protocol in MAY for

some counters have been updated in component memcache and cc_vcache
fixed a bug in memcache (in WRITE FSM)

Location:
branches/MESI/modules/vci_cc_vcache_wrapper/caba/source
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h

    r700 r719  
    774774    uint32_t m_cpt_data_tlb_inval;             // number of data tlb invalidate
    775775
     776    uint32_t m_cpt_data_miss_clean;
     777    uint32_t m_cpt_data_miss_clean_pte;
     778    uint32_t m_cpt_data_miss_clean_ptd;
     779    uint32_t m_cpt_miss_tlb;
     780    uint32_t m_cpt_dcache_miss_pte;
     781
    776782    // FSM activity counters
    777783    uint32_t m_cpt_fsm_icache     [64];

  • branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

    r700 r719  
    597597////////////////////////
    598598{
    599     float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
     599    //float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
    600600    std::cout << name() << std::endl
    601         << "- CPI                     = " << std::dec <<(float)m_cpt_total_cycles/run_cycles << std::endl
    602         << "- READ RATE               = " << (float)m_cpt_data_read/run_cycles << std::endl
    603         << "- WRITE RATE              = " << (float)m_cpt_data_write/run_cycles << std::endl
    604         << "- IMISS_RATE              = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
    605         << "- DMISS RATE              = " << (float)m_cpt_data_miss/(m_cpt_data_read-m_cpt_unc_read) << std::endl
    606         << "- INS MISS COST           = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
    607         << "- DATA MISS COST          = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
    608         << "- WRITE COST              = " << (float)m_cost_write_frz/m_cpt_data_write << std::endl
    609         << "- UNC COST                = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
    610         << "- UNCACHED READ RATE      = " << (float)m_cpt_unc_read/m_cpt_data_read << std::endl
    611         << "- CACHED WRITE RATE       = " << (float)m_cpt_write_cached/m_cpt_data_write << std::endl
    612         << "- INS TLB MISS RATE       = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
    613         << "- DATA TLB MISS RATE      = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
    614         << "- ITLB MISS COST          = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
    615         << "- DTLB MISS COST          = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
    616         << "- ITLB UPDATE ACC COST    = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
    617         << "- DTLB UPDATE ACC COST    = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
    618         << "- DTLB UPDATE DIRTY COST  = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
    619         << "- ITLB HIT IN DCACHE RATE = " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
    620         << "- DTLB HIT IN DCACHE RATE = " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
    621         //<< "- DCACHE FROZEN BY ITLB   = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
    622         << "- DCACHE FOR TLB %        = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
    623         << "- NB CC BROADCAST         = " << m_cpt_cc_broadcast << std::endl
    624         << "- NB CC UPDATE DATA       = " << m_cpt_cc_update_dcache << std::endl
    625         << "- NB CC INVAL DATA        = " << m_cpt_cc_inval_dcache << std::endl
    626         << "- NB CC INVAL INS         = " << m_cpt_cc_inval_icache << std::endl
    627         << "- CC BROADCAST COST       = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
    628         << "- CC UPDATE DATA COST     = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_dcache << std::endl
    629         << "- CC INVAL DATA COST      = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_dcache << std::endl
    630         << "- CC INVAL INS COST       = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_icache << std::endl
    631         << "- NB CC CLEANUP DATA      = " << m_cpt_cc_cleanup_data << std::endl
    632         << "- NB CC CLEANUP INS       = " << m_cpt_cc_cleanup_ins << std::endl
    633         << "- IMISS TRANSACTION       = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
    634         << "- DMISS TRANSACTION       = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
    635         << "- UNC TRANSACTION         = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
    636         << "- WRITE TRANSACTION       = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
    637         << "- NB WRITE TRANSACTION    = " << m_cpt_write_transaction << std::endl
    638         << "- NB WRITE WORDS VCI      = " << m_length_write_transaction << std::endl
    639         << "- NB WRITE PROC           = " << m_cpt_data_write << std::endl
    640         << "- NB WRITE BACK           = " << m_cpt_data_write_back << std::endl
    641         << "- NB WRITE BACK COHERENCE = " << m_cpt_data_cleanup << std::endl
    642         << "- NB DATA SC              = " << m_cpt_data_sc << std::endl
    643         << "- WRITE LENGTH            = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
    644         << "- ITLB MISS TRANSACTION   = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
    645         << "- DTLB MISS TRANSACTION   = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl
    646 
    647         << "- DMISS TRANSACTION       = " << m_cpt_dmiss_transaction << std::endl
    648         << "- DUNC TRANSACTION        = " << m_cpt_dunc_transaction << std::endl
    649         << "- LL TRANSACTION          = " << m_cpt_ll_transaction << std::endl
    650         << "- WRITE DATA MISS         = " << m_cpt_data_write_miss << std::endl
    651         << "- WRITE DATA ON ZOMBI     = " << m_cpt_data_write_on_zombi << std::endl
    652         << "- WRITE DATA ON ZOMBI NCC = " << m_cpt_data_write_on_zombi_ncc << std::endl
    653         << "- CLEANUP DATA NOT DIRTY  = " << m_cpt_cleanup_data_not_dirty << std::endl
    654         << "- CLEANUP DATA DIRTY WORD = " << m_cpt_cleanup_data_dirty_word << std::endl;
     601      //  << "- CPI                     = " << std::dec <<(float)m_cpt_total_cycles/run_cycles << std::endl
     602        << "- NB_MISS_CLEAN           = " << std::dec <<m_cpt_data_miss_clean << std::endl
     603        << "- NB_MISS_CLEAN_PTE       = " << std::dec <<m_cpt_data_miss_clean_pte << std::endl
     604        << "- NB_MISS_CLEAN_PTD       = " << std::dec <<m_cpt_data_miss_clean_ptd << std::endl
     605        << "- NB_MISS_TLB             = " << std::dec <<m_cpt_miss_tlb  << std::endl
     606        << "- NB_MISS_PTE             = " << std::dec <<m_cpt_dcache_miss_pte  << std::endl;
     607
     608     //   << "- READ RATE               = " << (float)m_cpt_data_read/run_cycles << std::endl
     609     //   << "- WRITE RATE              = " << (float)m_cpt_data_write/run_cycles << std::endl
     610     //   << "- IMISS_RATE              = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
     611     //   << "- DMISS RATE              = " << (float)m_cpt_data_miss/(m_cpt_data_read-m_cpt_unc_read) << std::endl
     612     //   << "- INS MISS COST           = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
     613     //   << "- DATA MISS COST          = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
     614     //   << "- WRITE COST              = " << (float)m_cost_write_frz/m_cpt_data_write << std::endl
     615     //   << "- UNC COST                = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
     616     //   << "- UNCACHED READ RATE      = " << (float)m_cpt_unc_read/m_cpt_data_read << std::endl
     617     //   << "- CACHED WRITE RATE       = " << (float)m_cpt_write_cached/m_cpt_data_write << std::endl
     618     //   << "- INS TLB MISS RATE       = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
     619     //   << "- DATA TLB MISS RATE      = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
     620     //   << "- ITLB MISS COST          = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
     621     //   << "- DTLB MISS COST          = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
     622     //   << "- ITLB UPDATE ACC COST    = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
     623     //   << "- DTLB UPDATE ACC COST    = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
     624     //   << "- DTLB UPDATE DIRTY COST  = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
     625     //   << "- ITLB HIT IN DCACHE RATE = " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
     626     //   << "- DTLB HIT IN DCACHE RATE = " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
     627     //   //<< "- DCACHE FROZEN BY ITLB   = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
     628     //   << "- DCACHE FOR TLB %        = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
     629     //   << "- NB CC BROADCAST         = " << m_cpt_cc_broadcast << std::endl
     630     //   << "- NB CC UPDATE DATA       = " << m_cpt_cc_update_dcache << std::endl
     631     //   << "- NB CC INVAL DATA        = " << m_cpt_cc_inval_dcache << std::endl
     632     //   << "- NB CC INVAL INS         = " << m_cpt_cc_inval_icache << std::endl
     633     //   << "- CC BROADCAST COST       = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
     634     //   << "- CC UPDATE DATA COST     = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_dcache << std::endl
     635     //   << "- CC INVAL DATA COST      = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_dcache << std::endl
     636     //   << "- CC INVAL INS COST       = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_icache << std::endl
     637     //   << "- NB CC CLEANUP DATA      = " << m_cpt_cc_cleanup_data << std::endl
     638     //   << "- NB CC CLEANUP INS       = " << m_cpt_cc_cleanup_ins << std::endl
     639     //   << "- IMISS TRANSACTION       = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
     640     //   << "- DMISS TRANSACTION       = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
     641     //   << "- UNC TRANSACTION         = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
     642     //   << "- WRITE TRANSACTION       = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
     643     //   << "- NB WRITE TRANSACTION    = " << m_cpt_write_transaction << std::endl
     644     //   << "- NB WRITE WORDS VCI      = " << m_length_write_transaction << std::endl
     645     //   << "- NB WRITE PROC           = " << m_cpt_data_write << std::endl
     646     //   << "- NB WRITE BACK           = " << m_cpt_data_write_back << std::endl
     647     //   << "- NB WRITE BACK COHERENCE = " << m_cpt_data_cleanup << std::endl
     648     //   << "- NB DATA SC              = " << m_cpt_data_sc << std::endl
     649     //   << "- WRITE LENGTH            = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
     650     //   << "- ITLB MISS TRANSACTION   = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
     651     //   << "- DTLB MISS TRANSACTION   = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl
     652
     653     //   << "- DMISS TRANSACTION       = " << m_cpt_dmiss_transaction << std::endl
     654     //   << "- DUNC TRANSACTION        = " << m_cpt_dunc_transaction << std::endl
     655     //   << "- LL TRANSACTION          = " << m_cpt_ll_transaction << std::endl
     656     //   << "- WRITE DATA MISS         = " << m_cpt_data_write_miss << std::endl
     657     //   << "- WRITE DATA ON ZOMBI     = " << m_cpt_data_write_on_zombi << std::endl
     658     //   << "- WRITE DATA ON ZOMBI NCC = " << m_cpt_data_write_on_zombi_ncc << std::endl
     659     //   << "- CLEANUP DATA NOT DIRTY  = " << m_cpt_cleanup_data_not_dirty << std::endl
     660     //   << "- CLEANUP DATA DIRTY WORD = " << m_cpt_cleanup_data_dirty_word << std::endl;
    655661}
    656662
    … …  
    755761    m_cpt_data_write_on_zombi = 0;
    756762    m_cpt_data_write_on_zombi_ncc = 0;
     763   
     764    m_cpt_data_miss_clean = 0;
     765    m_cpt_data_miss_clean_pte = 0;
     766    m_cpt_data_miss_clean_ptd = 0;
     767    m_cpt_miss_tlb = 0;
    757768
    758769}
    … …  
    13001311                    m_irsp.instruction = cache_inst;
    13011312                    r_icache_fsm       = ICACHE_IDLE;
    1302 #if DEBUG_ICACHE
     1313#if DEBUG_ICACHE 
    13031314if ( m_debug_activated )
    13041315std::cout << "  <PROC " << name() << " ICACHE_IDLE> READ HIT in icache"
    … …  
    22802291            if (m_dreq.addr == 0x0 && m_dreq.wdata == 0xDEADDEAD) {
    22812292                std::cout << "*** Ecriture à l'adresse 0 pour fin de simulation ***" << std::endl;
     2293                print_stats();
    22822294                raise(SIGINT);
    22832295            }
    … …  
    30573069        paddr_t         pte_paddr;
    30583070
     3071
     3072        m_cpt_miss_tlb ++;
    30593073        // evaluate bypass in order to skip first level page table access
    30603074        if ( r_dcache_tlb_ins.read() )                          // itlb miss
    … …  
    32473261            r_dcache_miss_type     = PTE1_MISS;
    32483262            r_dcache_fsm           = DCACHE_MISS_SELECT;
     3263           
     3264            m_cpt_dcache_miss_pte ++;
    32493265
    32503266#if DEBUG_DCACHE
    … …  
    35313547            r_dcache_miss_type    = PTE2_MISS;
    35323548
     3549            m_cpt_dcache_miss_pte ++;
    35333550#if DEBUG_DCACHE
    35343551if ( m_debug_activated )
    … …  
    45114528        size_t  set   = r_dcache_miss_set.read();
    45124529
     4530        m_cpt_data_miss_clean ++;
    45134531#ifdef INSTRUMENTATION
    45144532m_cpt_dcache_dir_read++;
    … …  
    45354553            //MODIFIED
    45364554            //r_dcache_in_tlb[way*m_dcache_sets+set] = false;
     4555            m_cpt_data_miss_clean_pte ++;
    45374556            r_dcache_content_state[way*m_dcache_sets+set] = LINE_EMPTY;
    45384557            if( not r_dcache_cleanup_victim_req.read() )
    … …  
    45534572        else if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD )
    45544573        {
     4574            m_cpt_data_miss_clean_ptd ++;
    45554575            r_itlb.reset();
    45564576            r_dtlb.reset();
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