Index: branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
===================================================================
--- branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 700)
+++ branches/MESI/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 719)
@@ -597,60 +597,66 @@
 ////////////////////////
 {
-    float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
+    //float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles);
     std::cout << name() << std::endl
-        << "- CPI                     = " << std::dec <<(float)m_cpt_total_cycles/run_cycles << std::endl
-        << "- READ RATE               = " << (float)m_cpt_data_read/run_cycles << std::endl
-        << "- WRITE RATE              = " << (float)m_cpt_data_write/run_cycles << std::endl
-        << "- IMISS_RATE              = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
-        << "- DMISS RATE              = " << (float)m_cpt_data_miss/(m_cpt_data_read-m_cpt_unc_read) << std::endl
-        << "- INS MISS COST           = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
-        << "- DATA MISS COST          = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
-        << "- WRITE COST              = " << (float)m_cost_write_frz/m_cpt_data_write << std::endl
-        << "- UNC COST                = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
-        << "- UNCACHED READ RATE      = " << (float)m_cpt_unc_read/m_cpt_data_read << std::endl
-        << "- CACHED WRITE RATE       = " << (float)m_cpt_write_cached/m_cpt_data_write << std::endl
-        << "- INS TLB MISS RATE       = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
-        << "- DATA TLB MISS RATE      = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
-        << "- ITLB MISS COST          = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
-        << "- DTLB MISS COST          = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
-        << "- ITLB UPDATE ACC COST    = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
-        << "- DTLB UPDATE ACC COST    = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
-        << "- DTLB UPDATE DIRTY COST  = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
-        << "- ITLB HIT IN DCACHE RATE = " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
-        << "- DTLB HIT IN DCACHE RATE = " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
-        //<< "- DCACHE FROZEN BY ITLB   = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
-        << "- DCACHE FOR TLB %        = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
-        << "- NB CC BROADCAST         = " << m_cpt_cc_broadcast << std::endl
-        << "- NB CC UPDATE DATA       = " << m_cpt_cc_update_dcache << std::endl
-        << "- NB CC INVAL DATA        = " << m_cpt_cc_inval_dcache << std::endl
-        << "- NB CC INVAL INS         = " << m_cpt_cc_inval_icache << std::endl
-        << "- CC BROADCAST COST       = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
-        << "- CC UPDATE DATA COST     = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_dcache << std::endl
-        << "- CC INVAL DATA COST      = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_dcache << std::endl
-        << "- CC INVAL INS COST       = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_icache << std::endl
-        << "- NB CC CLEANUP DATA      = " << m_cpt_cc_cleanup_data << std::endl
-        << "- NB CC CLEANUP INS       = " << m_cpt_cc_cleanup_ins << std::endl
-        << "- IMISS TRANSACTION       = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
-        << "- DMISS TRANSACTION       = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
-        << "- UNC TRANSACTION         = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
-        << "- WRITE TRANSACTION       = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
-        << "- NB WRITE TRANSACTION    = " << m_cpt_write_transaction << std::endl
-        << "- NB WRITE WORDS VCI      = " << m_length_write_transaction << std::endl
-        << "- NB WRITE PROC           = " << m_cpt_data_write << std::endl
-        << "- NB WRITE BACK           = " << m_cpt_data_write_back << std::endl
-        << "- NB WRITE BACK COHERENCE = " << m_cpt_data_cleanup << std::endl
-        << "- NB DATA SC              = " << m_cpt_data_sc << std::endl
-        << "- WRITE LENGTH            = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
-        << "- ITLB MISS TRANSACTION   = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
-        << "- DTLB MISS TRANSACTION   = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl
-
-        << "- DMISS TRANSACTION       = " << m_cpt_dmiss_transaction << std::endl
-        << "- DUNC TRANSACTION        = " << m_cpt_dunc_transaction << std::endl
-        << "- LL TRANSACTION          = " << m_cpt_ll_transaction << std::endl
-        << "- WRITE DATA MISS         = " << m_cpt_data_write_miss << std::endl
-        << "- WRITE DATA ON ZOMBI     = " << m_cpt_data_write_on_zombi << std::endl
-        << "- WRITE DATA ON ZOMBI NCC = " << m_cpt_data_write_on_zombi_ncc << std::endl
-        << "- CLEANUP DATA NOT DIRTY  = " << m_cpt_cleanup_data_not_dirty << std::endl
-        << "- CLEANUP DATA DIRTY WORD = " << m_cpt_cleanup_data_dirty_word << std::endl;
+      //  << "- CPI                     = " << std::dec <<(float)m_cpt_total_cycles/run_cycles << std::endl
+        << "- NB_MISS_CLEAN           = " << std::dec <<m_cpt_data_miss_clean << std::endl
+        << "- NB_MISS_CLEAN_PTE       = " << std::dec <<m_cpt_data_miss_clean_pte << std::endl
+        << "- NB_MISS_CLEAN_PTD       = " << std::dec <<m_cpt_data_miss_clean_ptd << std::endl
+        << "- NB_MISS_TLB             = " << std::dec <<m_cpt_miss_tlb  << std::endl
+        << "- NB_MISS_PTE             = " << std::dec <<m_cpt_dcache_miss_pte  << std::endl;
+
+     //   << "- READ RATE               = " << (float)m_cpt_data_read/run_cycles << std::endl
+     //   << "- WRITE RATE              = " << (float)m_cpt_data_write/run_cycles << std::endl
+     //   << "- IMISS_RATE              = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
+     //   << "- DMISS RATE              = " << (float)m_cpt_data_miss/(m_cpt_data_read-m_cpt_unc_read) << std::endl
+     //   << "- INS MISS COST           = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
+     //   << "- DATA MISS COST          = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
+     //   << "- WRITE COST              = " << (float)m_cost_write_frz/m_cpt_data_write << std::endl
+     //   << "- UNC COST                = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
+     //   << "- UNCACHED READ RATE      = " << (float)m_cpt_unc_read/m_cpt_data_read << std::endl
+     //   << "- CACHED WRITE RATE       = " << (float)m_cpt_write_cached/m_cpt_data_write << std::endl
+     //   << "- INS TLB MISS RATE       = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
+     //   << "- DATA TLB MISS RATE      = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
+     //   << "- ITLB MISS COST          = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
+     //   << "- DTLB MISS COST          = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
+     //   << "- ITLB UPDATE ACC COST    = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
+     //   << "- DTLB UPDATE ACC COST    = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
+     //   << "- DTLB UPDATE DIRTY COST  = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
+     //   << "- ITLB HIT IN DCACHE RATE = " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
+     //   << "- DTLB HIT IN DCACHE RATE = " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
+     //   //<< "- DCACHE FROZEN BY ITLB   = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
+     //   << "- DCACHE FOR TLB %        = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
+     //   << "- NB CC BROADCAST         = " << m_cpt_cc_broadcast << std::endl
+     //   << "- NB CC UPDATE DATA       = " << m_cpt_cc_update_dcache << std::endl
+     //   << "- NB CC INVAL DATA        = " << m_cpt_cc_inval_dcache << std::endl
+     //   << "- NB CC INVAL INS         = " << m_cpt_cc_inval_icache << std::endl
+     //   << "- CC BROADCAST COST       = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl
+     //   << "- CC UPDATE DATA COST     = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_dcache << std::endl
+     //   << "- CC INVAL DATA COST      = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_dcache << std::endl
+     //   << "- CC INVAL INS COST       = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_icache << std::endl
+     //   << "- NB CC CLEANUP DATA      = " << m_cpt_cc_cleanup_data << std::endl
+     //   << "- NB CC CLEANUP INS       = " << m_cpt_cc_cleanup_ins << std::endl
+     //   << "- IMISS TRANSACTION       = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl
+     //   << "- DMISS TRANSACTION       = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl
+     //   << "- UNC TRANSACTION         = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl
+     //   << "- WRITE TRANSACTION       = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl
+     //   << "- NB WRITE TRANSACTION    = " << m_cpt_write_transaction << std::endl
+     //   << "- NB WRITE WORDS VCI      = " << m_length_write_transaction << std::endl
+     //   << "- NB WRITE PROC           = " << m_cpt_data_write << std::endl
+     //   << "- NB WRITE BACK           = " << m_cpt_data_write_back << std::endl
+     //   << "- NB WRITE BACK COHERENCE = " << m_cpt_data_cleanup << std::endl
+     //   << "- NB DATA SC              = " << m_cpt_data_sc << std::endl
+     //   << "- WRITE LENGTH            = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl
+     //   << "- ITLB MISS TRANSACTION   = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl
+     //   << "- DTLB MISS TRANSACTION   = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl
+
+     //   << "- DMISS TRANSACTION       = " << m_cpt_dmiss_transaction << std::endl
+     //   << "- DUNC TRANSACTION        = " << m_cpt_dunc_transaction << std::endl
+     //   << "- LL TRANSACTION          = " << m_cpt_ll_transaction << std::endl
+     //   << "- WRITE DATA MISS         = " << m_cpt_data_write_miss << std::endl
+     //   << "- WRITE DATA ON ZOMBI     = " << m_cpt_data_write_on_zombi << std::endl
+     //   << "- WRITE DATA ON ZOMBI NCC = " << m_cpt_data_write_on_zombi_ncc << std::endl
+     //   << "- CLEANUP DATA NOT DIRTY  = " << m_cpt_cleanup_data_not_dirty << std::endl
+     //   << "- CLEANUP DATA DIRTY WORD = " << m_cpt_cleanup_data_dirty_word << std::endl;
 }
 
@@ -755,4 +761,9 @@
     m_cpt_data_write_on_zombi = 0;
     m_cpt_data_write_on_zombi_ncc = 0;
+    
+    m_cpt_data_miss_clean = 0;
+    m_cpt_data_miss_clean_pte = 0;
+    m_cpt_data_miss_clean_ptd = 0;
+    m_cpt_miss_tlb = 0;
 
 }
@@ -1300,5 +1311,5 @@
                     m_irsp.instruction = cache_inst;
                     r_icache_fsm       = ICACHE_IDLE;
-#if DEBUG_ICACHE
+#if DEBUG_ICACHE 
 if ( m_debug_activated )
 std::cout << "  <PROC " << name() << " ICACHE_IDLE> READ HIT in icache" 
@@ -2280,4 +2291,5 @@
             if (m_dreq.addr == 0x0 && m_dreq.wdata == 0xDEADDEAD) {
                 std::cout << "*** Ecriture Ã  l'adresse 0 pour fin de simulation ***" << std::endl;
+                print_stats();
                 raise(SIGINT);
             }
@@ -3057,4 +3069,6 @@
         paddr_t		pte_paddr;
 
+
+        m_cpt_miss_tlb ++;
         // evaluate bypass in order to skip first level page table access
         if ( r_dcache_tlb_ins.read() )				// itlb miss
@@ -3247,4 +3261,6 @@
             r_dcache_miss_type     = PTE1_MISS;
             r_dcache_fsm           = DCACHE_MISS_SELECT;
+            
+            m_cpt_dcache_miss_pte ++;
 
 #if DEBUG_DCACHE
@@ -3531,4 +3547,5 @@
             r_dcache_miss_type    = PTE2_MISS;
 
+            m_cpt_dcache_miss_pte ++;
 #if DEBUG_DCACHE
 if ( m_debug_activated )
@@ -4511,4 +4528,5 @@
         size_t  set   = r_dcache_miss_set.read();
 
+        m_cpt_data_miss_clean ++;
 #ifdef INSTRUMENTATION
 m_cpt_dcache_dir_read++;
@@ -4535,4 +4553,5 @@
             //MODIFIED
             //r_dcache_in_tlb[way*m_dcache_sets+set] = false;
+            m_cpt_data_miss_clean_pte ++;
             r_dcache_content_state[way*m_dcache_sets+set] = LINE_EMPTY;
             if( not r_dcache_cleanup_victim_req.read() )
@@ -4553,4 +4572,5 @@
         else if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD )
         {
+            m_cpt_data_miss_clean_ptd ++;
             r_itlb.reset();
             r_dtlb.reset();
