Index: trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h =================================================================== --- trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (revision 720) +++ trunk/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (revision 721) @@ -113,4 +113,5 @@ DCACHE_XTN_IC_FLUSH, DCACHE_XTN_IC_INVAL_PA, + DCACHE_XTN_IC_PADDR_EXT, DCACHE_XTN_IT_INVAL, DCACHE_XTN_DC_FLUSH, @@ -322,4 +323,7 @@ bool m_debug_ok; + uint32_t m_dcache_paddr_ext_reset; + uint32_t m_icache_paddr_ext_reset; + //////////////////////////////////////// // Communication with processor ISS @@ -401,4 +405,7 @@ sc_signal r_icache_cc_send_way; // ICACHE cc_send way sc_signal r_icache_cc_send_updt_tab_idx; // ICACHE cc_send update table index + + // Physical address extension for data access + sc_signal r_icache_paddr_ext; // CP2 register (if vci_address > 32) /////////////////////////////// @@ -749,4 +756,26 @@ } + ///////////////////////////////////////////////////////////// + // Set the m_dcache_paddr_ext_reset attribute + // + // The r_dcache_paddr_ext register will be initialized after + // reset with the m_dcache_paddr_ext_reset value + ///////////////////////////////////////////////////////////// + inline void set_dcache_paddr_ext_reset(uint32_t v) + { + m_dcache_paddr_ext_reset = v; + } + + ///////////////////////////////////////////////////////////// + // Set the m_icache_paddr_ext_reset attribute + // + // The r_icache_paddr_ext register will be initialized after + // reset with the m_icache_paddr_ext_reset value + ///////////////////////////////////////////////////////////// + inline void set_icache_paddr_ext_reset(uint32_t v) + { + m_icache_paddr_ext_reset = v; + } + private: void transition(); Index: trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp =================================================================== --- trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 720) +++ trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 721) @@ -85,4 +85,5 @@ "DCACHE_XTN_IC_FLUSH", "DCACHE_XTN_IC_INVAL_PA", + "DCACHE_XTN_IC_PADDR_EXT", "DCACHE_XTN_IT_INVAL", "DCACHE_XTN_DC_FLUSH", @@ -244,4 +245,6 @@ m_debug_start_cycle( debug_start_cycle ), m_debug_ok( debug_ok ), + m_dcache_paddr_ext_reset(0), + m_icache_paddr_ext_reset(0), r_mmu_ptpr("r_mmu_ptpr"), @@ -740,5 +743,8 @@ // reset data physical address extension - r_dcache_paddr_ext = 0; + r_dcache_paddr_ext = m_dcache_paddr_ext_reset; + + // reset inst physical address extension + r_icache_paddr_ext = m_icache_paddr_ext_reset; // reset dcache directory extension @@ -1055,6 +1061,6 @@ // XTN requests sent by DCACHE FSM - // These request are not executed in this IDLE state, because - // they require access to icache or itlb, that are already accessed + // These request are not executed in this IDLE state (except XTN_INST_PADDR_EXT), + // because they require access to icache or itlb, that are already accessed if ( r_dcache_xtn_req.read() ) { @@ -1078,16 +1084,21 @@ else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV) { - if (sizeof(paddr_t) <= 32) + if (sizeof(paddr_t) <= 32) { - assert(r_mmu_word_hi.read() == 0 && - "illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr"); - r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read(); + assert(r_mmu_word_hi.read() == 0 && + "illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr"); + r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read(); } else { - r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 | - (paddr_t)r_mmu_word_lo.read(); - } - r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA; + r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 | + (paddr_t)r_mmu_word_lo.read(); + } + r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA; + } + else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_INST_PADDR_EXT) + { + r_icache_paddr_ext = r_dcache_save_wdata.read(); + r_dcache_xtn_req = false; } else @@ -1128,11 +1139,19 @@ &paddr, &tlb_flags, - &tlb_nline, // unused - &tlb_way, // unused - &tlb_set ); // unused + &tlb_nline, // unused + &tlb_way, // unused + &tlb_set ); // unused } else { - paddr = (paddr_t)m_ireq.addr; + if (vci_param::N > 32) + { + paddr = (paddr_t)m_ireq.addr | + ((paddr_t)r_icache_paddr_ext.read() << 32); + } + else + { + paddr = (paddr_t)m_ireq.addr; + } } @@ -2480,4 +2499,10 @@ break; + case iss_t::XTN_INST_PADDR_EXT: + m_drsp.rdata = r_icache_paddr_ext.read(); + m_drsp.valid = true; + m_drsp.error = false; + break; + default: r_mmu_detr = MMU_READ_UNDEFINED_XTN; @@ -2608,9 +2633,14 @@ break; - case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action - case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action + case iss_t::XTN_INST_PADDR_EXT: // no cache or tlb access + r_dcache_xtn_req = true; + r_dcache_fsm = DCACHE_XTN_IC_PADDR_EXT; + break; + + case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action + case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action m_drsp.valid = true; r_dcache_fsm = DCACHE_IDLE; - break; + break; case iss_t::XTN_DEBUG_MASK: // debug mask @@ -3726,9 +3756,10 @@ } //////////////////////// - case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM - case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken - case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache - case DCACHE_XTN_IT_INVAL: // can generate an itlb miss, - // and because it can exist a simultaneous ITLB miss + case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM + case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken + case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache + case DCACHE_XTN_IC_PADDR_EXT: // can generate an itlb miss, + case DCACHE_XTN_IT_INVAL: // and because it can exist a simultaneous ITLB miss + { // coherence clack request (from DSPIN CLACK)