Index: /branches/fault_tolerance/communication/dspin_dhccp_param/caba/metadata/dspin_dhccp_param.sd =================================================================== --- /branches/fault_tolerance/communication/dspin_dhccp_param/caba/metadata/dspin_dhccp_param.sd (revision 724) +++ /branches/fault_tolerance/communication/dspin_dhccp_param/caba/metadata/dspin_dhccp_param.sd (revision 724) @@ -0,0 +1,4 @@ +Module('caba:dspin_dhccp_param', + classname = 'soclib::caba::DspinDhccpParam', + header_files = ['../source/include/dspin_dhccp_param.h',] +) Index: /branches/fault_tolerance/communication/dspin_dhccp_param/caba/source/include/dspin_dhccp_param.h =================================================================== --- /branches/fault_tolerance/communication/dspin_dhccp_param/caba/source/include/dspin_dhccp_param.h (revision 724) +++ /branches/fault_tolerance/communication/dspin_dhccp_param/caba/source/include/dspin_dhccp_param.h (revision 724) @@ -0,0 +1,405 @@ +/* -*- c++ -*- + * File : dspin_dhccp_param.h + * Date : 01/03/2013 + * Copyright : UPMC / LIP6 + * Authors : Cesar Fuguet + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + */ + + +#ifndef DSPIN_DHCCP_PARAMS_H +#define DSPIN_DHCCP_PARAMS_H + +#include +#include + +namespace soclib { namespace caba { + +/* + * L1 cache to Memory Cache command packets + * + * CLEANUP + * + * flit 1 + * ---------------------------------------------------------------------------------------------- + * EOP:0 | DEST | SRCID | NLINE MSB(2 bits)| X | WAY_INDEX(2 bits) | TYPE:0b1X | BC:0 + * | (10 bits) | (14 bits) | | | | | + * ---------------------------------------------------------------------------------------------- + * | X: 0 DATA | + * | 1 INST | + * flit 2 + * ---------------------------------------------------------------------------------------------- + * EOP:1 | NLINE(32 bits) + * ---------------------------------------------------------------------------------------------- + * + * MULTICAST ACKNOWLEDGEMENT + * + * flit 1 + * ---------------------------------------------------------------------------------------------- + * EOP:1 | DEST(10 bits) | X(15 bits) | UPDT_INDEX(4 bits) | TYPE:0b00 | BC:0 + * ---------------------------------------------------------------------------------------------- + */ + +/* + * M2P command packets + * + * MULTICAST UPDATE + * + * flit 1 + * ---------------------------------------------------------------------------------------------- + * EOP:0 | DEST(14 bits) | X(4 bits) | MEMC_ID(14 bits) | UPDT_INDEX(4 bits) | TYPE:0b0X | BC:0 + * ---------------------------------------------------------------------------------------------- + * | X: 0 DATA | + * | 1 INST | + * flit 2 + * ---------------------------------------------------------------------------------------------- + * EOP:0 | X | WORD_INDEX(4 bits) | NLINE (34 bits) + * ---------------------------------------------------------------------------------------------- + * + * flit 3 + * ---------------------------------------------------------------------------------------------- + * EOP:0 | X(3 bits) | BE(4 bits) | WDATA(32 bits) + * ---------------------------------------------------------------------------------------------- + * + * flit N + * ---------------------------------------------------------------------------------------------- + * EOP:1 | X(3 bits) | BE(4 bits) | WDATA(32 bits) + * ---------------------------------------------------------------------------------------------- + * + * MULTICAST INVALIDATE + * + * flit 1 + * ---------------------------------------------------------------------------------------------- + * EOP:0 | DEST(14 bits) | X(4 bits) | MEMC_ID(14 bits) | UPDT_INDEX(4 bits) | TYPE:0b1X | BC:0 + * ---------------------------------------------------------------------------------------------- + * | X: 0 DATA | + * | 1 INST | + * flit 2 + * ---------------------------------------------------------------------------------------------- + * EOP:1 | X(5 bits) | NLINE (34 bits) + * ---------------------------------------------------------------------------------------------- + * + * BROADCAST INVALIDATE + * + * flit 1 + * | BOUNDING BOX(20 bits) | + * ---------------------------------------------------------------------------------------------- + * EOP:0 | XMIN | XMAX | YMIN | YMAX | MEMC_ID(14 bits) | NETWORK_RESERVED(4 bits) | BC:1 + * ---------------------------------------------------------------------------------------------- + * + * flit 2 + * ---------------------------------------------------------------------------------------------- + * EOP:1 | X(5 bits) | NLINE (34 bits) + * ---------------------------------------------------------------------------------------------- + * + * M2P clack commands + * + * CLEANUP ACKNOWLEDGEMENT + * + * flit 1 + * ---------------------------------------------------------------------------------------------- + * EOP:1 | DEST(14 bits) | X(5 bits) | SET_INDEX(16 bits) | WAY_INDEX(2 bits) | TYPE:0bX | BC:0 + * ---------------------------------------------------------------------------------------------- + * | X: 0 CLACK | + * | DATA | + * | 1 CLACK | + * | INST | + * + */ + +/* + * Utility MACROS + */ +#define GET_FIELD(x,y)\ + case y: return ((x >> y##_SHIFT) & y##_MASK) + +#define SET_FIELD(x,y,z)\ + case z: x |= ((y & z##_MASK) << z##_SHIFT);break + +class DspinDhccpParam +{ + public: + + static const uint8_t m2p_flit_width = 40; + static const uint8_t p2m_flit_width = 33; + static const uint8_t clack_flit_width = 40; + + static const uint8_t UPDT_INDEX_WIDTH = 4; + static const uint8_t NLINE_WIDTH = 34; + static const uint8_t SRCID_WIDTH = 14; + static const uint8_t GLOBALID_WIDTH = 10; + static const uint8_t WORD_INDEX_WIDTH = 4; + static const uint8_t BE_WIDTH = 4; + static const uint8_t DATA_WIDTH = 32; + static const uint8_t SET_INDEX_WIDTH = 6; + static const uint8_t WAY_INDEX_WIDTH = 2; + static const uint8_t BROADCAST_BOX_WIDTH = 20; + static const uint8_t M2P_TYPE_WIDTH = 2; + static const uint8_t P2M_TYPE_WIDTH = 2; + static const uint8_t CLACK_TYPE_WIDTH = 1; + + static const uint8_t P2M_TYPE_SHIFT = 1; + static const uint64_t P2M_TYPE_MASK = ((1ULL< July 2008 + * + * Maintainers: alain + */ + +//////////////////////////////////////////////////////////////////////////////// +// File : generic_cache.h +// Date : 07/01/2012 +// Authors : Alain Greiner +///////////////////////////////////////////////////////////////////////////////// +// This object is a generic, set associative, cache. +// Each slot can be in three states: VALID, EMPTY or ZOMBI. +// The ZOMBI state is used by cache coherence protocols to indicate +// a pending cleanup request. +// Hit if ( (matching tag) and (state == VALID). +// The replacement policy is pseudo-LRU. The victim selection process cannot +// fail if the ZOMBI state is not used. +// But it can fail if all ways are in ZOMBI state. +///////////////////////////////////////////////////////////////////////////////// +// Implementation note +// The DATA part is implemented as an uint32_t array[nways*nsets*nwords]. +// The DIRECTORY part is implemented as an uint32_t array[nways*nsets]. +// All methods requiring a dual port RAM or cache modification using +// an associative search have been deprecated. +///////////////////////////////////////////////////////////////////////////////// +// Constructor parameters are : +// - std::string &name +// - size_t nways : number of associativity levels +// - size_t nsets : number of sets +// - size_t nwords : number of words in a cache line +// The nways, nsets, nwords parameters must be power of 2 +// The nsets parameter cannot be larger than 1024 +// The nways parameter cannot be larger than 16 +// The nwords parameter cannot be larger than 64 +///////////////////////////////////////////////////////////////////////////////// +// Template parameter is : +// - addr_t : address format to access the cache +///////////////////////////////////////////////////////////////////////////////// + +#ifndef SOCLIB_GENERIC_CACHE_H +#define SOCLIB_GENERIC_CACHE_H + +#include +#include +#include "arithmetics.h" +#include "static_assert.h" +#include "mapping_table.h" +#include + +namespace soclib { + +enum cache_slot_state_e +{ + CACHE_SLOT_STATE_EMPTY, + CACHE_SLOT_STATE_VALID, + CACHE_SLOT_STATE_ZOMBI, +}; + +////////////////////////// +template +class GenericCache +////////////////////////// +{ + typedef uint32_t data_t; + typedef uint32_t be_t; + + data_t *r_data ; + addr_t *r_tag ; + int *r_state; + bool *r_lru ; + + size_t m_ways; + size_t m_sets; + size_t m_words; + + const soclib::common::AddressMaskingTable m_x ; + const soclib::common::AddressMaskingTable m_y ; + const soclib::common::AddressMaskingTable m_z ; + + ////////////////////////////////////////////////////////////// + inline data_t &cache_data(size_t way, size_t set, size_t word) + { + return r_data[(way*m_sets*m_words)+(set*m_words)+word]; + } + + ////////////////////////////////////////////// + inline addr_t &cache_tag(size_t way, size_t set) + { + return r_tag[(way*m_sets)+set]; + } + + ////////////////////////////////////////////// + inline bool &cache_lru(size_t way, size_t set) + { + return r_lru[(way*m_sets)+set]; + } + + ////////////////////////////////////////////// + inline int &cache_state(size_t way, size_t set) + { + return r_state[(way*m_sets)+set]; + } + + ///////////////////////////////////////////////// + inline void cache_set_lru(size_t way, size_t set) + { + size_t way2; + + cache_lru(way, set) = true; + + for (way2 = 0; way2 < m_ways; way2++ ) + { + if (cache_lru(way2, set) == false) return; + } + // all lines are new -> they all become old + for (way2 = 0; way2 < m_ways; way2++ ) + { + cache_lru(way2, set) = false; + } + } + + //////////////////////////////// + inline data_t be2mask( be_t be ) + { + data_t mask = 0; + if ( (be & 0x1) == 0x1 ) mask = mask | 0x000000FF; + if ( (be & 0x2) == 0x2 ) mask = mask | 0x0000FF00; + if ( (be & 0x4) == 0x4 ) mask = mask | 0x00FF0000; + if ( (be & 0x8) == 0x8 ) mask = mask | 0xFF000000; + return mask; + } + +public: + + ////////////////////////////////////////// + GenericCache( const std::string &name, + size_t nways, + size_t nsets, + size_t nwords) + : m_ways(nways), + m_sets(nsets), + m_words(nwords), + +#define l2 soclib::common::uint32_log2 + + m_x( l2(nwords), l2(sizeof(data_t))), + m_y( l2(nsets), l2(nwords) + l2(sizeof(data_t))), + m_z( 8*sizeof(addr_t) - l2(nsets) - l2(nwords) - l2(sizeof(data_t)), + l2(nsets) + l2(nwords) + l2(sizeof(data_t))) +#undef l2 + { + assert(IS_POW_OF_2(nways)); + assert(IS_POW_OF_2(nsets)); + assert(IS_POW_OF_2(nwords)); + assert(nwords); + assert(nsets); + assert(nways); + assert(nwords <= 64); + assert(nsets <= 1024); + assert(nways <= 16); + +#ifdef GENERIC_CACHE_DEBUG +std::cout << "constructing " << name << std::endl + << "- nways = " << nways << std::endl + << "- nsets = " << nsets << std::endl + << "- nwords = " << nwords << std::endl + << " m_x: " << m_x + << " m_y: " << m_y + << " m_z: " << m_z + << std::endl; +#endif + + r_data = new data_t[nways*nsets*nwords]; + r_tag = new addr_t[nways*nsets]; + r_state = new int[nways*nsets]; + r_lru = new bool[nways*nsets]; + } + + //////////////// + ~GenericCache() + { + delete [] r_data; + delete [] r_tag; + delete [] r_state; + delete [] r_lru; + } + + //////////////////// + inline void reset( ) + { + std::memset(r_data, 0, sizeof(*r_data)*m_ways*m_sets*m_words); + std::memset(r_tag, 0, sizeof(*r_tag)*m_ways*m_sets); + std::memset(r_state, CACHE_SLOT_STATE_EMPTY, sizeof(*r_state)*m_ways*m_sets); + std::memset(r_lru, 0, sizeof(*r_lru)*m_ways*m_sets); + } + + ///////////////////////////////////////////////////////////////////// + // Read a single 32 bits word. + // returns true if (matching tag) and (state == VALID) + // Both data & directory are accessed. + ///////////////////////////////////////////////////////////////////// + inline bool read( addr_t ad, + data_t* dt) + { + const addr_t tag = m_z[ad]; + const size_t set = m_y[ad]; + const size_t word = m_x[ad]; + + for ( size_t way = 0; way < m_ways; way++ ) + { + if ( (tag == cache_tag(way, set)) + && (cache_state(way, set) == CACHE_SLOT_STATE_VALID) ) + { + *dt = cache_data(way, set, word); + cache_set_lru(way, set); + return true; + } + } + return false; + } + + //////////////////////////////////////////////////////////////////// + // Read a single 32 bits word. + // returns true if (matching tag) and (state == VALID) + // Both data & directory are accessed. + // The selected way, set and word index are returned in case of hit. + ///////////////////////////////////////////////////////////////////// + inline bool read( addr_t ad, + data_t* dt, + size_t* selway, + size_t* selset, + size_t* selword) + { + const addr_t tag = m_z[ad]; + const size_t set = m_y[ad]; + const size_t word = m_x[ad]; + + for ( size_t way = 0; way < m_ways; way++ ) + { + if ( (tag == cache_tag(way, set)) and + (cache_state(way, set) == CACHE_SLOT_STATE_VALID) ) + { + *selway = way; + *selset = set; + *selword = word; + *dt = cache_data(way, set, word); + cache_set_lru(way, set); + return true; + } + } + return false; + } + + //////////////////////////////////////////////////////////////////// + // Read a single 32 bits word when the ZOMBI state is used. + // Both data and directory are accessed. + // returns the access status in the state argument: + // - VALID : (matching tag) and (state == VALID) + // - ZOMBI : (matching tag) and (state == ZOMBI) + // - MISS : no matching tag or EMPTY state + // If VALID or ZOMBI, the data, the way, set and word index are + // returned in the other arguments. + //////////////////////////////////////////////////////////////////// + inline void read( addr_t ad, + data_t* dt, + size_t* selway, + size_t* selset, + size_t* selword, + int* state ) + { + const addr_t tag = m_z[ad]; + const size_t set = m_y[ad]; + const size_t word = m_x[ad]; + + // default return values + *state = CACHE_SLOT_STATE_EMPTY; + *selway = 0; + *selset = 0; + *selword = 0; + *dt = 0; + + for ( size_t way = 0; way < m_ways; way++ ) + { + if ( tag == cache_tag(way, set) ) // matching tag + { + + if ( cache_state(way, set) == CACHE_SLOT_STATE_VALID ) + { + *state = CACHE_SLOT_STATE_VALID; + *selway = way; + *selset = set; + *selword = word; + *dt = cache_data(way, set, word); + cache_set_lru(way, set); + } + else if ( cache_state(way, set) == CACHE_SLOT_STATE_ZOMBI ) + { + *state = CACHE_SLOT_STATE_ZOMBI; + *selway = way; + *selset = set; + *selword = word; + } + } + } + } + + //////////////////////////////////////////////////////////////////// + // Read a single 32 bits word, without LRU update. + // returns true if (matching tag) and (state == VALID) + // Both data & directory are accessed. + // The selected way, set and word index are returned in case of hit. + ///////////////////////////////////////////////////////////////////// + inline bool read_neutral( addr_t ad, + data_t* dt, + size_t* selway, + size_t* selset, + size_t* selword) + { + const addr_t tag = m_z[ad]; + const size_t set = m_y[ad]; + const size_t word = m_x[ad]; + + for ( size_t way = 0; way < m_ways; way++ ) + { + if ( (tag == cache_tag(way, set)) + && (cache_state(way, set) == CACHE_SLOT_STATE_VALID) ) + { + *selway = way; + *selset = set; + *selword = word; + *dt = cache_data(way, set, word); + return true; + } + } + return false; + } + + ///////////////////////////////////////////////////////////////////////////// + // Read one or two 32 bits word. + // Both data & directory are accessed. + // Hit if (matching tag) and (valid == true) and (zombi == false) + // If the addressed word is not the last in the cache line, + // two successive words are returned. + // The selected way, set and first word index are returned in case of hit. + // This function is used by the cc_vcache to get a 64 bits page table entry. + ///////////////////////////////////////////////////////////////////////////// + inline bool read( addr_t ad, + data_t* dt, + data_t* dt_next, + size_t* selway, + size_t* selset, + size_t* selword) + { + const addr_t tag = m_z[ad]; + const size_t set = m_y[ad]; + const size_t word = m_x[ad]; + + for ( size_t way = 0; way < m_ways; way++ ) + { + if ( (tag == cache_tag(way, set)) + && (cache_state(way, set) == CACHE_SLOT_STATE_VALID) ) + { + *dt = cache_data(way, set, word); + if ( word+1 < m_words) + { + *dt_next = cache_data(way, set, word+1); + } + *selway = way; + *selset = set; + *selword = word; + cache_set_lru(way, set); + return true; + } + } + return false; + } + + //////////////////////////////////////////////////////////////////// + // Read one or two 32 bits word. + // Both data and directory are accessed. + // returns the access status in the state argument: + // - VALID : (matching tag) and (state == VALID) + // - ZOMBI : (matching tag) and (state == ZOMBI) + // - MISS : no matching tag or EMPTY state + // If VALID or ZOMBI, the data, the way, set and word index are + // returned in the other arguments. + //////////////////////////////////////////////////////////////////// + inline void read( addr_t ad, + data_t* dt, + data_t* dt_next, + size_t* selway, + size_t* selset, + size_t* selword, + int* state ) + { + const addr_t tag = m_z[ad]; + const size_t set = m_y[ad]; + const size_t word = m_x[ad]; + + // default return values + *state = CACHE_SLOT_STATE_EMPTY; + *selway = 0; + *selset = 0; + *selword = 0; + *dt = 0; + + for ( size_t way = 0; way < m_ways; way++ ) + { + if ( tag == cache_tag(way, set) ) // matching tag + { + + if ( cache_state(way, set) == CACHE_SLOT_STATE_VALID ) + { + *state = CACHE_SLOT_STATE_VALID; + *selway = way; + *selset = set; + *selword = word; + *dt = cache_data(way, set, word); + if ( word+1 < m_words) + { + *dt_next = cache_data(way, set, word+1); + } else { + assert(false && "can't request 2 words at end of line"); + } + cache_set_lru(way, set); + } + else if ( cache_state(way, set) == CACHE_SLOT_STATE_ZOMBI ) + { + *state = CACHE_SLOT_STATE_ZOMBI; + *selway = way; + *selset = set; + *selword = word; + } + } + } + } + + /////////////////////////////////////////////////////////////////////////////// + // Checks the cache state for a given address. + // Only the directory is accessed. + // returns true if (matching tag) and (state == VALID) + // The selected way, set and first word index are returned in case of hit. + // This function can be used when we need to access the directory + // while we write in the data part with a different address in the same cycle. + /////////////////////////////////////////////////////////////////////////////// + inline bool hit( addr_t ad, + size_t* selway, + size_t* selset, + size_t* selword) + { + const addr_t tag = m_z[ad]; + const size_t set = m_y[ad]; + const size_t word = m_x[ad]; + + for ( size_t way = 0; way < m_ways; way++ ) + { + if ( (tag == cache_tag(way, set)) + && (cache_state(way, set) == CACHE_SLOT_STATE_VALID) ) + { + *selway = way; + *selset = set; + *selword = word; + cache_set_lru(way, set); + return true; + } + } + return false; + } + + /////////////////////////////////////////////////////////////////////////////// + // Checks the cache state for a given address, when the ZOMBI state is used. + // Only the directory is accessed. + // Returns the access status in the state argument: + // - VALID if (matching tag) and (state == VALID) + // - ZOMBI if (matching tag) and (state == ZOMBI) + // - EMPTY if no match or (state == EMPTY) + // The selected way, set and first word index are returned if not empty. + // This function can be used when we need to access the directory + // while we write in the data part with a different address in the same cycle. + /////////////////////////////////////////////////////////////////////////////// + inline void read_dir( addr_t ad, + int* state, + size_t* way, + size_t* set, + size_t* word) + { + const addr_t ad_tag = m_z[ad]; + const size_t ad_set = m_y[ad]; + const size_t ad_word = m_x[ad]; + + for ( size_t _way = 0; _way < m_ways; _way++ ) + { + if ( (ad_tag == cache_tag(_way, ad_set) ) and + (cache_state(_way, ad_set) != CACHE_SLOT_STATE_EMPTY) ) + { + *state = cache_state(_way, ad_set); + *way = _way; + *set = ad_set; + *word = ad_word; + return; + } + } + + // return value if not (VALID or ZOMBI) + *state = CACHE_SLOT_STATE_EMPTY; + } + + /////////////////////////////////////////////////////////////////////////////// + // Checks the cache state for a slot (set,way), when the ZOMBI state is used. + // Only the directory is accessed. + // Returns the access status and the tag value in the state and tag argument. + /////////////////////////////////////////////////////////////////////////////// + inline void read_dir( size_t way, + size_t set, + addr_t* tag, + int* state ) + { + *state = cache_state(way, set); + *tag = cache_tag(way, set); + } + + //////////////////////////////////////////// + inline addr_t get_tag(size_t way, size_t set) + { + return cache_tag(way, set); + } + + /////////////////////////////////////////////////////////////////// + // This function writes a complete 32 bits word + // It does not use the directory and cannot miss. + ////////////////////////////////////////////////////////////////// + inline void write(size_t way, + size_t set, + size_t word, + data_t data) + { + cache_data(way, set, word) = data; + cache_set_lru(way, set); + } + + //////////////////////////////////////////////////////////////////////////// + // this function writes up to 4 bytes, taking into account the byte enable. + // It does not use the directory and cannot miss. + //////////////////////////////////////////////////////////////////////////// + inline void write(size_t way, + size_t set, + size_t word, + data_t data, + be_t be) + { + data_t mask = be2mask(be); + data_t prev = cache_data(way, set, word); + cache_data(way, set, word) = (mask & data) | (~mask & prev); + cache_set_lru(way, set); + } + + ////////////////////////////////////////////////////////////////////////// + // This function invalidates a cache line identified by the set and way. + // It returns true if the line was valid, and returns the line index. + ////////////////////////////////////////////////////////////////////////// + inline bool inval(size_t way, + size_t set, + addr_t* nline) + { + if ( cache_state(way,set) == CACHE_SLOT_STATE_VALID ) + { + cache_state(way,set) = CACHE_SLOT_STATE_EMPTY; + *nline = (data_t)cache_tag(way,set)* m_sets + set; + return true; + } + return false; + } + + ////////////////////////////////////////////////////////////////////////////////// + // This function selects a victim slot in an associative set. + // It cannot fail, as a slot in ZOMBI state is considered EMPTY. + // - we search first an EMPTY slot + // - if no EMPTY slot, we search an OLD slot, using lru + // It returns the line index (Z + Y fields), the selected slot way and set, + // and a Boolean indicating that a cleanup is requested. + ////////////////////////////////////////////////////////////////////////////////// + inline bool victim_select(addr_t ad, + addr_t* victim, + size_t* way, + size_t* set) + { + bool found = false; + bool cleanup = false; + + *set = m_y[ad]; + *way = 0; + + // Search first empty slot + for ( size_t _way = 0 ; _way < m_ways && !found ; _way++ ) + { + if ( cache_state(_way, *set) != CACHE_SLOT_STATE_VALID ) // empty + { + found = true; + cleanup = false; + *way = _way; + } + } + + // If no empty slot, search first old slot (lru == false) + if ( !found ) + { + for ( size_t _way = 0 ; _way < m_ways && !found ; _way++ ) + { + if ( not cache_lru(_way, *set) ) + { + found = true; + cleanup = true; + *way = _way; + } + } + } + + assert(found && "all ways can't be new at the same time"); + *victim = (addr_t)((cache_tag(*way,*set) * m_sets) + *set); + return cleanup; + } + + ////////////////////////////////////////////////////////////////////////////////// + // This function selects a victim slot in an associative set. + // It can fail if all ways are in ZOMBI state. + // - we search first an EMPTY slot + // - if no empty slot, we search an OLD slot not in ZOMBI state, + // - if not found, we take the first not ZOMBI slot. + // It returns the line index (Z + Y fields), the selected slot way and set, + // and two Boolean indicating success and a required cleanup. + ////////////////////////////////////////////////////////////////////////////////// + inline void read_select(addr_t ad, + addr_t* victim, + size_t* way, + size_t* set, + bool* found, + bool* cleanup ) + { + size_t _set = m_y[ad]; + + *found = false; + + // Search first empty slot + for ( size_t _way = 0 ; _way < m_ways && !(*found) ; _way++ ) + { + if ( cache_state(_way, _set) == CACHE_SLOT_STATE_EMPTY ) + { + *found = true; + *cleanup = false; + *way = _way; + *set = m_y[ad]; + return; + } + } + // Search first not zombi old slot + for ( size_t _way = 0 ; _way < m_ways && !(*found) ; _way++ ) + { + if ( not cache_lru(_way, _set) and + (cache_state(_way, _set) != CACHE_SLOT_STATE_ZOMBI) ) + { + *found = true; + *cleanup = true; + *way = _way; + *set = m_y[ad]; + *victim = cache_tag(*way,_set) * m_sets + _set; + return; + } + } + // Search first not zombi slot + for ( size_t _way = 0 ; _way < m_ways && !(*found) ; _way++ ) + { + if ( cache_state(_way, _set) != CACHE_SLOT_STATE_ZOMBI) + { + *found = true; + *cleanup = true; + *way = _way; + *set = m_y[ad]; + *victim = cache_tag(*way,_set) * m_sets + _set; + return; + } + } + + // no slot found... + *found = false; + *cleanup = false; + } + + ////////////////////////////////////////////////////////////////// + // This function update the directory part of a slot + // identified by the way & set. + ////////////////////////////////////////////////////////////////// + inline void victim_update_tag( addr_t ad, + size_t way, + size_t set ) + { + addr_t tag = m_z[ad]; + + cache_tag(way, set) = tag; + cache_state(way, set) = CACHE_SLOT_STATE_VALID; + cache_set_lru(way, set); + } + + ////////////////////////////////////////////////////////////////// + // This function write the directory part of a slot + // identified by the way & set, when using the ZOMBI state. + ////////////////////////////////////////////////////////////////// + inline void write_dir( addr_t ad, + size_t way, + size_t set, + int state) + { + addr_t tag = m_z[ad]; + + assert( ( (state == CACHE_SLOT_STATE_VALID) or + (state == CACHE_SLOT_STATE_ZOMBI) or + (state == CACHE_SLOT_STATE_EMPTY) ) and + "illegal slot state argument in Generic Cache write_dir()"); + + assert( (way < m_ways) and + "too large way index argument in Generic Cache write_dir()"); + + assert( (set < m_sets) and + "too large set index argument in Generic Cache write_dir()"); + + cache_tag(way, set) = tag; + cache_state(way, set) = state; + + if ( state == CACHE_SLOT_STATE_VALID ) cache_set_lru(way, set); + } + + ////////////////////////////////////////////////////////////////// + // This function change the state of a slot + // identified by the way & set, when using the ZOMBI state. + // It does not affect the tag + ////////////////////////////////////////////////////////////////// + inline void write_dir( size_t way, + size_t set, + int state) + { + assert( ( (state == CACHE_SLOT_STATE_VALID) or + (state == CACHE_SLOT_STATE_ZOMBI) or + (state == CACHE_SLOT_STATE_EMPTY) ) and + "illegal slot state argument in Generic Cache write_dir()"); + + assert( (way < m_ways) and + "too large way index argument in Generic Cache write_dir()"); + + assert( (set < m_sets) and + "too large set index argument in Generic Cache write_dir()"); + + cache_state(way, set) = state; + + if ( state == CACHE_SLOT_STATE_VALID ) cache_set_lru(way, set); + } + + /////////////////////////////////////////////////////////////////// + // This function writes a full cache line in one single cycle. + // The target slot is identified by the way & set arguments. + // Both DATA and DIRECTORY are written + /////////////////////////////////////////////////////////////////// + inline void update(addr_t ad, + size_t way, + size_t set, + data_t* buf) + { + addr_t tag = m_z[ad]; + + cache_tag(way, set) = tag; + cache_state(way, set) = CACHE_SLOT_STATE_VALID; + cache_set_lru(way, set); + for ( size_t word = 0 ; word < m_words ; word++ ) + { + cache_data(way, set, word) = buf[word] ; + } + } + + /////////////////////////// + void fileTrace(FILE* file) + { + for( size_t nway = 0 ; nway < m_ways ; nway++) + { + for( size_t nset = 0 ; nset < m_sets ; nset++) + { + fprintf(file, "%d / ", (int)cache_state(nway, nset)); + fprintf(file, "way %d / ", (int)nway); + fprintf(file, "set %d / ", (int)nset); + fprintf(file, "@ = %08zX / ", + ((cache_tag(nway, nset)*m_sets+nset)*m_words*4)); + for( size_t nword = m_words ; nword > 0 ; nword--) + { + unsigned int data = cache_data(nway, nset, nword-1); + fprintf(file, "%08X ", data ); + } + fprintf(file, "\n"); + } + } + } + + //////////////////////// + inline void printTrace() + { + for ( size_t way = 0; way < m_ways ; way++ ) + { + for ( size_t set = 0 ; set < m_sets ; set++ ) + { + addr_t addr = (((addr_t)cache_tag(way,set))*m_words*m_sets+m_words*set)*4; + std::cout << std::dec << cache_state(way, set) + << " | way " << way + << " | set " << set + << std::hex << " | @ " << addr; + + for ( size_t word = 0 ; word < m_words ; word++ ) + { + std::cout << " | " << cache_data(way,set,word) ; + } + std::cout << std::endl ; + } + } + } + + /////////////////////////////////////////////////////////////////////////// + // This function is deprecated as it is difficult to implement in 1 cycle. + /////////////////////////////////////////////////////////////////////////// + __attribute__((deprecated)) + inline bool inval(addr_t ad) + { + bool hit = false; + const addr_t tag = m_z[ad]; + const size_t set = m_y[ad]; + + for ( size_t way = 0 ; way < m_ways && !hit ; way++ ) + { + if ( (tag == cache_tag(way, set)) and + (cache_state(way, set) == CACHE_SLOT_STATE_VALID) ) + { + hit = true; + cache_state(way, set) = CACHE_SLOT_STATE_EMPTY; + cache_lru(way, set) = false; + } + } + return hit; + } + + //////////////////////////////////////////////////////////////////////////////// + // This function is deprecated as it is difficult to implement in 1 cycle. + //////////////////////////////////////////////////////////////////////////////// + __attribute__((deprecated)) + inline bool inval( addr_t ad, + size_t* selway, + size_t* selset ) + { + bool hit = false; + const addr_t tag = m_z[ad]; + const size_t set = m_y[ad]; + + for ( size_t way = 0 ; way < m_ways && !hit ; way++ ) + { + if ( (tag == cache_tag(way, set)) and + (cache_state(way, set) == CACHE_SLOT_STATE_VALID) ) + { + hit = true; + cache_state(way, set) = CACHE_SLOT_STATE_EMPTY; + cache_lru(way, set) = false; + *selway = way; + *selset = set; + } + } + return hit; + } + + //////////////////////////////////////////////////////////////////////////////// + // This function is deprecated as the directory must be a dual port RAM... + //////////////////////////////////////////////////////////////////////////////// + __attribute__((deprecated)) + inline bool update( addr_t ad, + data_t* buf, + addr_t* victim ) + { + size_t set, way; + bool cleanup = victim_select(ad, victim, &way, &set); + victim_update_tag (ad, way, set); + + for ( size_t word = 0 ; word < m_words ; word++ ) { + cache_data(way, set, word) = buf[word] ; + } + + return cleanup; + } + + //////////////////////////////////////////////////////////////////////////// + // this function is deprecated, as it is difficult to implement in 1 cycle. + //////////////////////////////////////////////////////////////////////////// + __attribute__((deprecated)) + inline bool write(addr_t ad, + data_t dt) + { + const addr_t tag = m_z[ad]; + const size_t set = m_y[ad]; + const size_t word = m_x[ad]; + + for ( size_t way = 0; way < m_ways; way++ ) + { + if ( (tag == cache_tag(way, set)) and + (cache_state(way, set) == CACHE_SLOT_STATE_VALID) ) + { + cache_data(way, set, word) = dt; + cache_set_lru(way, set); + return true; + } + } + return false; + } + + //////////////////////////////////////////////////////////////////////////// + // this function is deprecated, as it is difficult to implement in 1 cycle. + //////////////////////////////////////////////////////////////////////////// + __attribute__((deprecated)) + inline bool write(addr_t ad, + data_t dt, + be_t be) + { + const addr_t tag = m_z[ad]; + const size_t set = m_y[ad]; + const size_t word = m_x[ad]; + + for ( size_t way = 0; way < m_ways; way++ ) + { + if ( (tag == cache_tag(way, set)) and + (cache_state(way, set) == CACHE_SLOT_STATE_VALID) ) + { + data_t mask = be2mask(be); + data_t prev = cache_data(way, set, word); + cache_data(way, set, word) = (mask & dt) | (~mask & prev); + cache_set_lru(way, set); + return true; + } + } + return false; + } + + ///////////////////////////////////////////////////////////////////////////// + // this function is deprecated, as it is difficult to implement in 1 cycle. + ///////////////////////////////////////////////////////////////////////////// + __attribute__((deprecated)) + inline bool write(addr_t ad, + data_t dt, + size_t* nway) + { + const addr_t tag = m_z[ad]; + const size_t set = m_y[ad]; + const size_t word = m_x[ad]; + + for ( size_t way = 0; way < m_ways; way++ ) + { + if ( (tag == cache_tag(way, set)) and + (cache_state(way, set) == CACHE_SLOT_STATE_VALID) ) + { + cache_data(way, set, word) = dt; + cache_set_lru(way, set); + *nway = way; + return true; + } + } + return false; + } + + ///////////////////////////////////////////////////////////////////////////// + // this function is deprecated, as it is difficult to implement in 1 cycle. + ///////////////////////////////////////////////////////////////////////////// + __attribute__((deprecated)) + inline bool write(addr_t ad, + data_t dt, + size_t* nway, + be_t be) + { + const addr_t tag = m_z[ad]; + const size_t set = m_y[ad]; + const size_t word = m_x[ad]; + + for ( size_t way = 0; way < m_ways; way++ ) + { + if ( (tag == cache_tag(way, set)) and + (cache_state(way, set) == CACHE_SLOT_STATE_VALID) ) + { + data_t mask = be2mask(be); + data_t prev = cache_data(way, set, word); + cache_data(way, set, word) = (mask & dt) | (~mask & prev); + cache_set_lru(way, set); + *nway = way; + return true; + } + } + return false; + } + +}; + +} // namespace soclib + +#endif + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: /branches/fault_tolerance/lib/generic_cache_tsar/metadata/generic_cache.sd =================================================================== --- /branches/fault_tolerance/lib/generic_cache_tsar/metadata/generic_cache.sd (revision 724) +++ /branches/fault_tolerance/lib/generic_cache_tsar/metadata/generic_cache.sd (revision 724) @@ -0,0 +1,15 @@ + +# -*- python -*- + +__version__ = "$Revision: 917 $" + +Module('caba:generic_cache_tsar', + classname = 'soclib::GenericCache', + header_files = ['../include/generic_cache.h',], + tmpl_parameters = [ + parameter.Type('addr_t'), + ], + uses = [Uses('common:mapping_table'), + Uses('common:address_masking_table', + data_t = parameter.Reference('addr_t')),], +) Index: /branches/fault_tolerance/lib/generic_llsc_global_table/include/generic_llsc_global_table.h =================================================================== --- /branches/fault_tolerance/lib/generic_llsc_global_table/include/generic_llsc_global_table.h (revision 724) +++ /branches/fault_tolerance/lib/generic_llsc_global_table/include/generic_llsc_global_table.h (revision 724) @@ -0,0 +1,533 @@ +/* -*- c++ -*- + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Alexandre JOANNOU + * + */ + +#ifndef SOCLIB_GENERIC_LLSC_GLOBAL_TABLE_H +#define SOCLIB_GENERIC_LLSC_GLOBAL_TABLE_H + +#include +#include +#include +#include +#include +#include + +#define RESERVATION_LIFE_SPAN 1 + +namespace soclib +{ + +////////////////////////// +//TODO switch to this +/* +template +< +size_t nb_slots, // max number of concerned shared resources +typename key_t, // key type => max number of key; TODO wich one ? +unsigned int t_network, // max number of cycle spent in the network when responding to a client (or more) +unsigned int t_inter_op, // min number of cycle between 2 reservation operation (or less but > 0) +typename addr_t // ressource identifier type +> +*/ +template +< +size_t nb_slots, // desired number of slots +unsigned int nb_procs, // number of processors in the system +unsigned int life_span, // registratioçn life span (in # of LL operations) +typename addr_t // address type +> +class GenericLLSCGlobalTable +//////////////////////////// +{ + private : + + const std::string name ; // component name + + uint32_t r_key [nb_slots] ; // array of key + addr_t r_addr [nb_slots] ; // array of addresses + bool r_val [nb_slots] ; // array of valid bits + + uint32_t r_next_key ; // value of the next key + uint64_t r_block_mask ; // mask for the slots blocks + uint64_t r_last_counter ; // mask for the slots blocks + size_t r_write_ptr ; // index of next slot to replace + size_t r_last_empty ; // index of last empty slot used + + mutable uint32_t m_cpt_evic ; // number of eviction in the table + mutable uint32_t m_cpt_ll ; // number of ll accesses to the table + mutable uint32_t m_cpt_ll_update ; // number of ll accesses to the table that trigger an update TODO check that + mutable uint32_t m_cpt_sc ; // number of sc accesses to the table + mutable uint32_t m_cpt_sc_success ; // number of sc accesses to the table that are successful + mutable uint32_t m_cpt_check ; // number of check accesses to the table + mutable uint32_t m_cpt_sw ; // number of sw accesses to the table + + //////////////////////////////////////////////////////////////////////////// + inline void upNextKey() + // This function generates a new value for the next key + { + // generating a new key in r_next_key + r_next_key++; + } + + //////////////////////////////////////////////////////////////////////////// + /* + inline void updateVictimSlot() + // This function selects the next slot to be evicted + // This is done by updating the value of r_write_ptr + { + // updates the position of the next slot to be replaced + + static unsigned int count = 0; + + + // for each slot, check if it actually is the slot to replace + // this is done by checking count % 2^(i+1) == (2^i)-1 + // 2^(i+1) being the period + // (2^i)-1 being the first apparition + // NB : the -1 in (2^i)-1 is here because of the 0 indexed array + + for (size_t i = 0 ; i < nb_slots; i++) + if (count % (int)pow(2,i+1) == pow(2,i)-1) + r_write_ptr = i; + + count = (count + 1) % (int) pow(2,nb_slots); // mustn't go further than 2^nb_slots + // or (2^nb_slots)+1 for a 1 indexed array + // 2^32 = periodicity of slot #31 + } + */ + //////////////////////////////////////////////////////////////////////////// + inline void updateVictimSlot() + // This function selects the next slot to be evicted + // This is done by updating the value of r_write_ptr + { + uint64_t new_counter; + uint64_t xor_counter; + + new_counter = newCounter(r_block_mask, r_last_counter); + xor_counter = new_counter ^ r_last_counter; + + for (size_t i = nb_slots - 1; i >= 0; --i) + { + if(xor_counter & (1 << i)) + { + r_write_ptr = i; + break; + } + } + + r_last_counter = new_counter; + } + + //////////////////////////////////////////////////////////////////////////// + inline uint64_t newCounter(const uint64_t& mask, + const uint64_t& counter) const + // This function generates the new counter //TODO comment more + { + return ((((~counter) & (counter << 1)) & mask) | (counter + 1)); + } + + //////////////////////////////////////////////////////////////////////////// + inline void init_block_mask() + //TODO + //This function selects the block mask to be used + //Need to provide another way to do that ? + { + /* + //try to dynamically compute the block mask ... + #define L2 soclib::common::uint32_log2 + unsigned int budget = nb_slots - (L2(nb_procs) + 1); //TODO +1? + #undef L2 + */ + + switch(nb_slots) + { + case 12: + r_block_mask = (uint64_t)0x000ULL; + break; + case 16 : + r_block_mask = (uint64_t)0xA800ULL; + break; + case 20 : + r_block_mask = (uint64_t)0xD5500ULL; + break; + case 24 : + r_block_mask = (uint64_t)0xDB5540ULL; + break; + case 28 : + r_block_mask = (uint64_t)0xEEDAAA0ULL; + break; + case 32 : + r_block_mask = (uint64_t)0xF776D550ULL; + break; + case 36 : + r_block_mask = (uint64_t)0xFBDDDB550ULL; + break; + case 40 : + r_block_mask = (uint64_t)0xFDF7BB6D50ULL; + break; + case 44 : + r_block_mask = (uint64_t)0xFEFBDEEDAA8ULL; + break; + case 48 : + r_block_mask = (uint64_t)0xFF7EFBDDDAA8ULL; + break; + case 52 : + r_block_mask = (uint64_t)0xFFBFBF7BBB6A8ULL; + break; + case 56 : + r_block_mask = (uint64_t)0xFFDFEFDF7BB6A8ULL; + break; + case 60 : + r_block_mask = (uint64_t)0xFFF7FDFDF7BB6A8ULL; + break; + case 64 : + r_block_mask = (uint64_t)0xFFFBFF7FBF7BB6A8ULL; + break; + default: + assert(false && "nb_slots must be either 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60 or 64"); + } + } + + //////////////////////////////////////////////////////////////////////////// + inline int nextEmptySlot() const + // This function returns : + // - the position of the first next empty slot in the table + // (starting from the last empty slot used) + // and updates the r_last_empty_slot register + // - -1 if the table is full + { + uint64_t i; + for(i = 0; i < nb_slots; i++) + { + if (!r_val[i]) return i; + } + + return -1; + } + + //////////////////////////////////////////////////////////////////////////// + inline int hitAddr(const addr_t ad) const + // HIT on the address only + // This function takes an addr_t ad + // It returns : + // - the position of the first HIT in the table + // - -1 in case of MISS + // NB : HIT = (slot addr == ad) AND (slot is valid) + { + // checking all slots + for (size_t i = 0; i < nb_slots; i++) + { + // if HIT, returning its position + if(ad == r_addr[i] && r_val[i]) return i; + } + + // MISS + return -1; + } + + //////////////////////////////////////////////////////////////////////////// + inline int hitAddrKey(const addr_t ad, const uint32_t key) const + // HIT on the address AND the on the signature + // This function takes an addr_t ad and a uint32_t key + // It returns : + // - the position of the first HIT in the table + // - -1 in case of MISS + // NB : HIT = (slot addr == ad) AND (slot key == key) + // AND (slot is valid) + { + // checking all slots + for (size_t i = 0; i < nb_slots; i++) + { + // if HIT, returning its position + if(ad == r_addr[i] && key == r_key[i] && r_val[i]) return i; + } + + // MISS + return -1; + } + + //////////////////////////////////////////////////////////////////////////// + inline void reset() + { + // init the table + init(); + + // init stat counters + m_cpt_evic = 0; + m_cpt_ll = 0; + m_cpt_ll_update = 0; + m_cpt_sc = 0; + m_cpt_sc_success = 0; + m_cpt_check = 0; + m_cpt_sw = 0; + } + + + public: + + //////////////////////////////////////////////////////////////////////////// + GenericLLSCGlobalTable( const std::string &n = "llsc_global_table" ) + : name(n) + { + assert(nb_procs > 1); + init(); + init_block_mask(); + } + + //////////////////////////////////////////////////////////////////////////// + ~GenericLLSCGlobalTable() + { + } + + //////////////////////////////////////////////////////////////////////////// + // This function initializes the table (all slots empty) + inline void init() + { + // making all slots available by reseting all valid bits + std::memset(r_val, 0, sizeof(*r_val) * nb_slots); + std::memset(r_addr, 0, sizeof(*r_addr) * nb_slots); + std::memset(r_key, 0, sizeof(*r_key) * nb_slots); + + // init registers + r_next_key = 0; + r_last_counter = 0; //TODO static in updateVictimSlot() ? + r_write_ptr = 0; + r_last_empty = 0; + } + + //////////////////////////////////////////////////////////////////////////// + inline uint32_t ll(const addr_t ad) + // This method registers an LL in the table and returns the key associated + // with the registration + { + // increment the ll access counter (for stats) + m_cpt_ll++; + + // hit addr ? + // YES + // enough time left ? + // YES + // use this registration, return key + // NO + // update this registration with a new key, return new key + // NO + // table has an empty slot ? + // YES + // select empty slot + // NO + // select victim slot (r_write_ptr) + // update next victim + // open registration on selected slot + // update next key + // return the registration key + + // Is the address found in the table ? + int pos = hitAddr(ad); + + // Yes, then return the associated key + if (pos >= 0) + { +#if RESERVATION_LIFE_SPAN == 0 + return r_key[pos]; +#else + uint32_t absdiff = ( r_key[pos] > r_next_key) ? + r_key[pos] - r_next_key : + r_next_key - r_key[pos]; + + if(absdiff < life_span) return r_key[pos]; + + r_key[pos] = r_next_key; + upNextKey(); + m_cpt_ll_update++; + + return r_key[pos]; +#endif + } + + // No, then try to find an empty slot + pos = nextEmptySlot(); + + // If there is no empty slot, + // evict an existing registration + if (pos == -1) + { + // update the victim slot for the next eviction + updateVictimSlot(); + + // get the position of the evicted registration + pos = r_write_ptr; + + // increment the eviction counter (for stats) + m_cpt_evic++; + } + + // get the key for the new registration + uint32_t key = r_next_key; + // update the registration slot + r_key[pos] = key ; + r_addr[pos] = ad ; + r_val[pos] = true ; + // compute the next key + upNextKey(); + + // return the key of the new registration + return key; + + } + + //////////////////////////////////////////////////////////////////////////// + inline bool sc(const addr_t ad, const uint32_t key) + // This method checks if there is a valid registration for the SC (ad && + // key) and, in case of hit,invalidates the registration and returns true + // (returns false otherwise) + // + // The return value can be used to tell if the SC is atomic + { + // increment the sc access counter (for stats) + m_cpt_sc++; + // hit addr && hit key ? + // NO + // return miss + // YES + // inval registration and return hit + + // Is there a valid registration in the table ? + int pos = hitAddrKey(ad, key); + if(pos >= 0) + { + // increment the sc success counter (for stats) + m_cpt_sc_success++; + // invalidate the registration + r_val[pos] = false; + // return the success of the sc operation + return true; + } + else + { + // return the failure of the sc operation + return false; + } + } + + //////////////////////////////////////////////////////////////////////////// + inline bool check(const addr_t ad, const uint32_t key) const + // This method checks if there is a valid registration for the SC (ad && + // key) + // The return value can be used to tell if the SC is atomic + { + // increment the check access counter (for stats) + m_cpt_check++; + + return (hitAddrKey(ad, key) >= 0); + } + + //////////////////////////////////////////////////////////////////////////// + /* + inline void sw(const addr_t ad) + // This method checks if there is a valid registration for the given + // address and, in case of hit, invalidates the registration + { + // increment the sw access counter (for stats) + m_cpt_sw++; + // hit addr ? + // YES + // inval registration + // NO + // nothing + + // Is there a registration for the given address ? + int pos = hitAddr(ad); + // If there is one, invalidate it + if(pos >= 0) r_val[pos] = false; + } + */ + inline void sw(const addr_t ad_min, const addr_t ad_max) + // This method checks if there is / are valid registration(s) for the given + // range and, in case of hit(s), invalidates the registration(s) + { + // increment the sw access counter (for stats) + m_cpt_sw++; + // hit range ? + // YES + // inval registration(s) + // NO + // nothing + + // for every address in the given range ... + for (addr_t i = ad_min; i <= ad_max; i+=4) + { + // Is there a registration for the given address ? + int pos = hitAddr(i); + + // If there is one, invalidate it + if (pos >= 0) + { + r_val[pos] = false; + } + } + } + + //////////////////////////////////////////////////////////////////////////// + /* + void fileTrace(FILE* file) + { + } + */ + + //////////////////////////////////////////////////////////////////////////// + inline void print_trace(std::ostream& out = std::cout) + { + for ( size_t i = 0; i < nb_slots ; i++ ) + { + out << std::setw(3) << std::setfill(' ') << std::dec << i + << std::noshowbase + << " VLD_RX = " << r_val[i] + << std::uppercase + << " ADR_RX = 0x" << std::setw(8) << std::setfill('0') << std::hex << (r_addr[i] >> 2) + << " SGN_RX = 0x" << std::setw(8) << std::setfill('0') << std::hex << r_key[i] + << std::endl; + } + out << "NEXT_SGN_RX = 0x" << std::setw(8) << std::setfill('0') << std::hex << r_next_key << std::endl + << "CNT_RX = 0x" << std::setw(8) << std::setfill('0') << std::hex << r_last_counter << std::endl; + } + + //////////////////////////////////////////////////////////////////////////// + inline void print_stats(std::ostream& out = std::cout) + { + out << "# of ll accesses : " << m_cpt_ll << std::endl + << "# of ll updates : " << m_cpt_ll_update << std::endl + << "# of sc accesses : " << m_cpt_sc << std::endl + << "# of sc success : " << m_cpt_sc_success << std::endl + << "# of sw accesses : " << m_cpt_sw << std::endl + << "# of evictions : " << m_cpt_evic << std::endl ; + } + +}; + +} // end namespace soclib + +#endif + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 Index: /branches/fault_tolerance/lib/generic_llsc_global_table/metadata/generic_llsc_global_table.sd =================================================================== --- /branches/fault_tolerance/lib/generic_llsc_global_table/metadata/generic_llsc_global_table.sd (revision 724) +++ /branches/fault_tolerance/lib/generic_llsc_global_table/metadata/generic_llsc_global_table.sd (revision 724) @@ -0,0 +1,13 @@ +# -*- python -*- + +Module( + 'caba:generic_llsc_global_table', + classname = 'soclib::GenericLLSCGlobalTable', + header_files = ['../include/generic_llsc_global_table.h'], + tmpl_parameters = + [ + parameter.Int('nb_slots', min = 2, max = 64, default = 32), + parameter.Int('nb_procs', min = 2, max = 4096, default = 4095), # default should be 4096, but soclib-cc problem + parameter.Type('addr_t', default = 'sc_dt::sc_uint<40>') + ] +) Index: /branches/fault_tolerance/modules/dspin_router_tsar/caba/metadata/dspin_router_tsar.sd =================================================================== --- /branches/fault_tolerance/modules/dspin_router_tsar/caba/metadata/dspin_router_tsar.sd (revision 724) +++ /branches/fault_tolerance/modules/dspin_router_tsar/caba/metadata/dspin_router_tsar.sd (revision 724) @@ -0,0 +1,30 @@ +# -*- python -*- + +Module('caba:dspin_router_tsar', + classname = 'soclib::caba::DspinRouterTsar', + tmpl_parameters = [ parameter.Int('flit_width'), ], + header_files = ['../source/include/dspin_router_tsar.h',], + implementation_files = ['../source/src/dspin_router_tsar.cpp',], + ports = [ + Port('caba:bit_in', 'p_resetn', auto = 'resetn'), + Port('caba:clock_in', 'p_clk', auto = 'clock'), + Port('caba:dspin_output', 'p_out', 5, dspin_data_size = parameter.Reference('flit_width')), + Port('caba:dspin_input', 'p_in', 5, dspin_data_size = parameter.Reference('flit_width')), + ], + instance_parameters = [ + parameter.Int('x'), + parameter.Int('y'), + parameter.Int('x_width'), + parameter.Int('y_width'), + parameter.Int('in_fifo_depth'), + parameter.Int('out_fifo_depth'), + parameter.Int('cluster_iob0'), + parameter.Int('cluster_iob1'), + parameter.Int('l_width'), + parameter.Int('iob_local_id'), + ], + uses = [ + Uses('caba:base_module'), + Uses('caba:generic_fifo'), + ], +) Index: /branches/fault_tolerance/modules/dspin_router_tsar/caba/source/include/dspin_router_tsar.h =================================================================== --- /branches/fault_tolerance/modules/dspin_router_tsar/caba/source/include/dspin_router_tsar.h (revision 724) +++ /branches/fault_tolerance/modules/dspin_router_tsar/caba/source/include/dspin_router_tsar.h (revision 724) @@ -0,0 +1,157 @@ +/* -*- c++ -*- + * + * File : dspin_router_tsar.h + * Copyright (c) UPMC, Lip6 + * Authors : Alain Greiner + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + */ + +//////////////////////////////////////////////////////////////////////////////// +// This component implements a variant of the standard (SocLib) DSPIN router: +// The routing function has been modified to handle the special case of +// cluster_iob0 (containing component IOB0) and cluster_iob1 (containing +// component IOB1). In those two cluster, the response router must decode +// both the SRCID global bits AND the SRCID local bits to distinguish +// between the IOB and MEMC initiators. +// This component contains the following modifications: +// - 4 extra constructor arguments, +// - 6 new member variables +// - a modified routing function +//////////////////////////////////////////////////////////////////////////////// + +#ifndef DSPIN_ROUTER_TSAR_H_ +#define DSPIN_ROUTER_TSAR_H_ + +#include +#include "caba_base_module.h" +#include "generic_fifo.h" +#include "dspin_interface.h" +#include "alloc_elems.h" + +namespace soclib { namespace caba { + +using namespace sc_core; + +template +class DspinRouterTsar +: public soclib::caba::BaseModule +{ + // Port indexing + enum + { + DSPIN_NORTH = 0, + DSPIN_SOUTH = 1, + DSPIN_EAST = 2, + DSPIN_WEST = 3, + DSPIN_LOCAL = 4, + }; + + // Input Port FSM + enum + { + INFSM_IDLE, + INFSM_REQ, + INFSM_ALLOC, + }; + + protected: + SC_HAS_PROCESS(DspinRouterTsar); + + public: + + // ports + sc_in p_clk; + sc_in p_resetn; + DspinInput *p_in; + DspinOutput *p_out; + + // constructor + DspinRouterTsar( + sc_module_name name, + const size_t x, // x coordinate + const size_t y, // y cordinate + const size_t x_width, // x field width in first flit + const size_t y_width, // y field width in first flit + const size_t in_fifo_depth, // input fifo depth + const size_t out_fifo_depth, // output fifo depth + const bool is_iob0, // cluster containing IOB0 + const bool is_iob1, // cluster containing IOB0 + const bool is_rsp, // only response router is modified + const size_t l_width); // local srcid width + private: + + // define the FIFO flit + typedef struct internal_flit_s + { + sc_uint data; + bool eop; + } internal_flit_t; + + // registers + sc_signal *r_alloc_out; + sc_signal *r_index_out; + sc_signal *r_fsm_in; + sc_signal *r_index_in; + + // fifos + soclib::caba::GenericFifo* r_fifo_in; + soclib::caba::GenericFifo* r_fifo_out; + + // structural parameters + size_t m_local_x; + size_t m_local_y; + size_t m_x_width; + size_t m_x_shift; + size_t m_x_mask; + size_t m_y_width; + size_t m_y_shift; + size_t m_y_mask; + size_t m_l_width; + size_t m_l_shift; + size_t m_l_mask; + bool m_is_iob0; + bool m_is_iob1; + bool m_is_rsp; + + // methods + void transition(); + void genMoore(); + size_t route( sc_uint data ); + + public: + + void print_trace(); +}; + +}} // end namespace + +#endif // DSPIN_ROUTER_TSAR_H_ + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 Index: /branches/fault_tolerance/modules/dspin_router_tsar/caba/source/src/dspin_router_tsar.cpp =================================================================== --- /branches/fault_tolerance/modules/dspin_router_tsar/caba/source/src/dspin_router_tsar.cpp (revision 724) +++ /branches/fault_tolerance/modules/dspin_router_tsar/caba/source/src/dspin_router_tsar.cpp (revision 724) @@ -0,0 +1,373 @@ +/* -*- c++ -*- + * + * File : dspin_router_tsar.cpp + * Copyright (c) UPMC, Lip6 + * Authors : Alain Greiner, Abbas Sheibanyrad, Ivan Miro, Zhen Zhang + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + */ + +//////////////////////////////////////////////////////////////////////////////// +// This component implements a variant of the standard (SocLib) DSPIN router: +// The routing function has been modified to handle the special case of +// cluster_iob0 (containing component IOB0) and cluster_iob1 (containing +// component IOB1). In those two cluster, the response router must decode +// both the SRCID global bits AND the SRCID local bits to distinguish +// between the IOB and MEMC initiators. +// This component contains the following modifications: +// - 4 new constructor arguments +// - 6 new member variables +// - a modified routing function +//////////////////////////////////////////////////////////////////////////////// + +#include "../include/dspin_router_tsar.h" + +namespace soclib { namespace caba { + +using namespace soclib::common; +using namespace soclib::caba; + +#define tmpl(x) template x DspinRouterTsar + + //////////////////////////////////////////////// + // constructor + //////////////////////////////////////////////// + tmpl(/**/)::DspinRouterTsar( + sc_module_name name, + const size_t x, // x coordinate + const size_t y, // y cordinate + const size_t x_width, // x field width in first flit + const size_t y_width, // y field width in first flit + const size_t in_fifo_depth, // input fifo depth + const size_t out_fifo_depth, // output fifo depth + + const bool is_iob0, // cluster contains iob0 + const bool is_iob1, // cluster contains iob1 + const bool is_rsp, // only response router is modified + const size_t l_width) // local field srcid width + : soclib::caba::BaseModule(name), + + p_clk( "p_clk" ), + p_resetn( "p_resetn" ), + p_in( alloc_elems >("p_in", 5) ), + p_out( alloc_elems >("p_out", 5) ), + + r_alloc_out( alloc_elems >("r_alloc_out", 5)), + r_index_out( soclib::common::alloc_elems >("r_index_out", 5)), + r_fsm_in( alloc_elems >("r_fsm_in", 5)), + r_index_in( alloc_elems >("r_index_in", 5)), + + m_local_x( x ), + m_local_y( y ), + + m_x_width( x_width ), + m_x_shift( flit_width - x_width ), + m_x_mask( (0x1 << x_width) - 1 ), + + m_y_width( y_width ), + m_y_shift( flit_width - x_width - y_width ), + m_y_mask( (0x1 << y_width) - 1 ), + + m_l_width( l_width ), + m_l_shift( flit_width - x_width - y_width - l_width ), + m_l_mask( (0x1 << l_width) - 1 ), + + m_is_iob0( is_iob0 ), + m_is_iob1( is_iob1 ), + m_is_rsp( is_rsp ) + + { + std::cout << " - Building DspinRouterTsar : " << name << std::endl; + + SC_METHOD (transition); + dont_initialize(); + sensitive << p_clk.pos(); + + SC_METHOD (genMoore); + dont_initialize(); + sensitive << p_clk.neg(); + + r_fifo_in = (GenericFifo*) + malloc(sizeof(GenericFifo)*5); + r_fifo_out = (GenericFifo*) + malloc(sizeof(GenericFifo)*5); + + for( size_t i = 0 ; i < 5 ; i++ ) + { + std::ostringstream stri; + stri << "r_in_fifo_" << i; + new(&r_fifo_in[i]) + GenericFifo(stri.str(), in_fifo_depth); + + std::ostringstream stro; + stro << "r_out_fifo_" << i; + new(&r_fifo_out[i]) + GenericFifo(stro.str(), out_fifo_depth); + } + } // end constructor + + ////////////////////////////////////////////////// + tmpl(size_t)::route( sc_uint data ) + { + size_t xdest = (size_t)(data >> m_x_shift) & m_x_mask; + size_t ydest = (size_t)(data >> m_y_shift) & m_y_mask; + size_t ldest = (size_t)(data >> m_l_shift) & m_l_mask; + + if (xdest < m_local_x ) return DSPIN_WEST; + else if (xdest > m_local_x ) return DSPIN_EAST; + else if (ydest < m_local_y ) return DSPIN_SOUTH; + else if (ydest > m_local_y ) return DSPIN_NORTH; + else // handling IOB0 & IOB1 special cases + { + if (m_is_rsp and m_is_iob0 and (ldest > 0xA)) return DSPIN_WEST; + else if (m_is_rsp and m_is_iob1 and (ldest > 0xA)) return DSPIN_EAST; + else return DSPIN_LOCAL; + } + } // end route() + + ///////////////////////// + tmpl(void)::print_trace() + { + const char* port_name[] = {"NORTH","SOUTH","EAST ","WEST ","LOCAL"}; + + std::cout << "DSPIN_ROUTER " << name() << std::hex; + for ( size_t out=0 ; out<5 ; out++) // loop on output ports + { + if ( r_alloc_out[out].read() ) + { + int in = r_index_out[out]; + std::cout << " / " << port_name[in] << " -> " << port_name[out] ; + } + } + std::cout << std::endl; + } + + //////////////////////// + tmpl(void)::transition() + { + // Long wires connecting input and output ports + size_t req_in[5]; // input ports -> output ports + size_t get_out[5]; // output ports -> input ports + bool put_in[5]; // input ports -> output ports + internal_flit_t flit_in[5]; // input ports -> output ports + + // control signals for the input fifos + bool fifo_in_write[5]; + bool fifo_in_read[5]; + internal_flit_t fifo_in_wdata[5]; + + // control signals for the output fifos + bool fifo_out_write[5]; + bool fifo_out_read[5]; + internal_flit_t fifo_out_wdata[5]; + + // Reset + if ( p_resetn == false ) + { + for(size_t i = 0 ; i < 5 ; i++) + { + r_alloc_out[i] = false; + r_index_out[i] = 0; + r_index_in[i] = 0; + r_fsm_in[i] = INFSM_IDLE; + r_fifo_in[i].init(); + r_fifo_out[i].init(); + } + return; + } + + // fifos signals default values + for(size_t i = 0 ; i < 5 ; i++) + { + fifo_in_read[i] = false; + fifo_in_write[i] = p_in[i].write.read(); + fifo_in_wdata[i].data = p_in[i].data.read(); + fifo_in_wdata[i].eop = p_in[i].eop.read(); + + fifo_out_read[i] = p_out[i].read.read(); + fifo_out_write[i] = false; + } + + // loop on the output ports: + // compute get_out[j] depending on the output port state + // and combining fifo_out[j].wok and r_alloc_out[j] + for ( size_t j = 0 ; j < 5 ; j++ ) + { + if( r_alloc_out[j].read() and (r_fifo_out[j].wok()) ) + { + get_out[j] = r_index_out[j].read(); + } + else + { + get_out[j] = 0xFFFFFFFF; + } + } + + // loop on the input ports : + // The port state is defined by r_fsm_in[i], r_index_in[i] + // The req_in[i] computation implements the X-FIRST algorithm. + // Both put_in[i] and req_in[i] depend on the input port state. + + for ( size_t i = 0 ; i < 5 ; i++ ) + { + switch ( r_fsm_in[i].read() ) + { + case INFSM_IDLE: // no output port allocated + { + put_in[i] = false; + if ( r_fifo_in[i].rok() ) // packet available in input fifo + { + req_in[i] = route( r_fifo_in[i].read().data ); + r_index_in[i] = req_in[i]; + r_fsm_in[i] = INFSM_REQ; + } + else + { + req_in[i] = 0xFFFFFFFF; // no request + } + break; + } + case INFSM_REQ: // waiting output port allocation + { + flit_in[i] = r_fifo_in[i].read(); + put_in[i] = r_fifo_in[i].rok(); + req_in[i] = r_index_in[i]; + if ( get_out[r_index_in[i].read()] == i ) // first flit transfered + { + if ( r_fifo_in[i].read().eop ) r_fsm_in[i] = INFSM_IDLE; + else r_fsm_in[i] = INFSM_ALLOC; + } + break; + } + case INFSM_ALLOC: // output port allocated + { + flit_in[i] = r_fifo_in[i].read(); + put_in[i] = r_fifo_in[i].rok(); + req_in[i] = 0xFFFFFFFF; // no request + if ( r_fifo_in[i].read().eop and r_fifo_in[i].rok() and + (get_out[r_index_in[i].read()] == i) ) // last flit transfered + { + r_fsm_in[i] = INFSM_IDLE; + } + break; + } + } // end switch + } // end for input ports + + // loop on the output ports : + // The r_alloc_out[j] and r_index_out[j] computation + // implements the round-robin allocation policy. + // These two registers implement a 10 states FSM. + for( size_t j = 0 ; j < 5 ; j++ ) + { + if( not r_alloc_out[j].read() ) // not allocated: possible new allocation + { + for( size_t k = r_index_out[j].read() + 1 ; + k < (r_index_out[j] + 6) ; k++) + { + size_t i = k % 5; + + if( req_in[i] == j ) + { + r_alloc_out[j] = true; + r_index_out[j] = i; + break; + } + } // end loop on input ports + } + else // allocated: possible desallocation + { + if ( flit_in[r_index_out[j]].eop and + r_fifo_out[j].wok() and + put_in[r_index_out[j]] ) + { + r_alloc_out[j] = false; + } + } + } // end loop on output ports + + // loop on input ports : + // fifo_in_read[i] computation (get data from fifo_in[i] + // (computed here because it depends on get_out[]) + for( size_t i = 0 ; i < 5 ; i++ ) + { + if ( r_fsm_in[i].read() != INFSM_IDLE ) + { + fifo_in_read[i] = (get_out[r_index_in[i].read()] == i); + } + else + { + fifo_in_read[i] = false; + } + } // end loop on input ports + + // loop on the output ports : + // The fifo_out_write[j] and fifo_out_wdata[j] computation + // implements the output port mux. + for( size_t j = 0 ; j < 5 ; j++ ) + { + if( r_alloc_out[j] ) // output port allocated + { + fifo_out_write[j] = put_in[r_index_out[j]]; + fifo_out_wdata[j] = flit_in[r_index_out[j]]; + } + } // end loop on the output ports + + // FIFOS update + for(size_t i = 0 ; i < 5 ; i++) + { + r_fifo_in[i].update(fifo_in_read[i], + fifo_in_write[i], + fifo_in_wdata[i]); + r_fifo_out[i].update(fifo_out_read[i], + fifo_out_write[i], + fifo_out_wdata[i]); + } + } // end transition + + //////////////////////////////// + // genMoore + //////////////////////////////// + tmpl(void)::genMoore() + { + for(size_t i = 0 ; i < 5 ; i++) + { + // input ports : READ signals + p_in[i].read = r_fifo_in[i].wok(); + + // output ports : DATA & WRITE signals + p_out[i].data = r_fifo_out[i].read().data; + p_out[i].eop = r_fifo_out[i].read().eop; + p_out[i].write = r_fifo_out[i].rok(); + } + } // end genMoore + +}} // end namespace + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 Index: /branches/fault_tolerance/modules/sdmmc/caba/metadata/sdmmc.sd =================================================================== --- /branches/fault_tolerance/modules/sdmmc/caba/metadata/sdmmc.sd (revision 724) +++ /branches/fault_tolerance/modules/sdmmc/caba/metadata/sdmmc.sd (revision 724) @@ -0,0 +1,33 @@ + +# -*- python -*- + +Module('caba:sdmmc', + classname = 'soclib::caba::SdMMC', + + header_files = [ + '../source/include/sdmmc.h', + ], + + implementation_files = [ + '../source/src/sdmmc.cpp', + ], + + ports = [ + Port('caba:bit_in', 'p_spi_clk'), + Port('caba:bit_in', 'p_spi_ss'), + Port('caba:bit_in', 'p_spi_mosi'), + Port('caba:bit_out', 'p_spi_miso'), + Port('caba:bit_in', 'p_resetn', auto = 'resetn'), + Port('caba:clock_in', 'p_clk', auto = 'clock'), + ], + + uses = [ + Uses('caba:base_module'), + ], + + instance_parameters = [ + parameter.String('filename'), + parameter.Int('latency'), + ], + +) Index: /branches/fault_tolerance/modules/sdmmc/caba/source/include/sdmmc.h =================================================================== --- /branches/fault_tolerance/modules/sdmmc/caba/source/include/sdmmc.h (revision 724) +++ /branches/fault_tolerance/modules/sdmmc/caba/source/include/sdmmc.h (revision 724) @@ -0,0 +1,138 @@ + +/* -*- c++ -*- + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * manuel.bouyer@lip6.fr october 2013 + * + * Maintainers: bouyer + */ + +////////////////////////////////////////////////////////////////////////////////////// +// This component is a SD/MMC block device. +// +// This component can perform data transfers between one single file belonging +// to the host system and a SPI controller. +// The file name is an argument of the constructor. +// + +#ifndef SOCLIB_SDMMC_H +#define SOCLIB_SDMMC_H + +#include +#include +#include +#include "caba_base_module.h" + +namespace soclib { +namespace caba { + +using namespace sc_core; + +class SdMMC + : public caba::BaseModule +{ +private: + + // Registers + int spi_fsm; // SPI state register + int spi_shiftreg; // data shift in/out + int spi_bitcount; + int spi_clk; + int spi_mosi_previous; // sampled MOSI value + + uint8_t command; + uint32_t args; + uint8_t cmdcrc; + int m_fd; // File descriptor + uint64_t m_device_size; // Total number of blocks + const uint32_t m_latency; // device latency + + uint8_t m_databuf[1 /* reponse */ + 1 /* data tocken */ + 512 /* data block */ + 2 /* CRC */ ]; + uint32_t m_datalen_snd; // data size to be sent to host + uint32_t m_datalen_rcv; // data size expected from host + uint32_t m_data_idx; + bool m_acmd; // next command will be acmd + int m_sdstate; // sdcard internal state + + // sd states + enum { + SD_IDLE = 0, + SD_READY = 1, + }; + + // methods + void genMealy(); + + void handle_sdmmc_cmd(uint8_t, uint32_t); + void handle_sdmmc_write(uint8_t, uint32_t); + + // Master FSM states + enum { + S_IDLE = 0, + S_RECEIVE_CMD = 1, + S_RECEIVE_ARGS_START = 2, + S_RECEIVE_ARGS = 3, + S_RECEIVE_CRC = 4, + S_RECEIVE_DATA_WAIT = 5, + S_RECEIVE_DATA = 6, + S_SEND_DATA = 7, + }; + +protected: + + SC_HAS_PROCESS(SdMMC); + +public: + + // ports + sc_in p_clk; + sc_in p_resetn; + sc_in p_spi_ss; + sc_in p_spi_clk; + sc_in p_spi_mosi; + sc_out p_spi_miso; + + void print_trace(); + + // Constructor + SdMMC( + sc_module_name name, + const std::string &filename, + const uint32_t latency = 0); + + ~SdMMC(); + +}; + +}} + +#endif /* SOCLIB_SDMMC_H */ + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 Index: /branches/fault_tolerance/modules/sdmmc/caba/source/src/sdmmc.cpp =================================================================== --- /branches/fault_tolerance/modules/sdmmc/caba/source/src/sdmmc.cpp (revision 724) +++ /branches/fault_tolerance/modules/sdmmc/caba/source/src/sdmmc.cpp (revision 724) @@ -0,0 +1,549 @@ +/* + -*- c++ -*- + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * manuel.bouyer@lip6.fr october 2013 + * + * Maintainers: bouyer + */ + +#include +#include +#include +#include +#include +#include +#include "sdmmc.h" + +namespace soclib { namespace caba { + +using namespace soclib::caba; + +//////////////////////// +void SdMMC::genMealy() +{ + if(p_resetn.read() == false) + { + spi_fsm = S_IDLE; + m_acmd = false; + m_sdstate = SD_IDLE; + return; + } + if (p_spi_ss.read()) { + if (spi_fsm != S_IDLE) { + std::cerr << name() << " deselect but not idle, state " + << std::dec << spi_fsm << " last cmd " << (int)command + << " args " << std::hex << args << std::dec + << " bitcount " << (int)spi_bitcount + << " idx " << m_data_idx << " len_snd " << m_datalen_snd + << " len_rcv " << m_datalen_rcv << std::endl; + } + spi_fsm = S_IDLE; + spi_clk = p_spi_clk; + spi_mosi_previous = p_spi_mosi; + return; + } + + switch(spi_fsm) { + case S_IDLE: + if (p_spi_clk.read() == 1 && spi_clk == 0) { + // rising edge + command = (command << 1) | spi_mosi_previous; + spi_bitcount = 6; + spi_fsm = S_RECEIVE_CMD; + } + break; + case S_RECEIVE_CMD: + if (p_spi_clk.read() == 1 && spi_clk == 0) { + // rising edge + command = (command << 1) | spi_mosi_previous; + if (spi_bitcount == 0) { + if ((command & 0x80) == 0) { + spi_fsm = S_RECEIVE_ARGS_START; + } else { +#ifdef SOCLIB_MODULE_DEBUG0 + std::cout << name() << " S_RECEIVE_CMD " << std::hex << (int)command << std::endl; +#endif + spi_fsm = S_IDLE; + } + } else { + spi_bitcount = spi_bitcount - 1; + } + } + break; + case S_RECEIVE_ARGS_START: + if (p_spi_clk.read() == 1 && spi_clk == 0) { + // rising edge + args = (args << 1) | spi_mosi_previous; + spi_bitcount = 30; + spi_fsm = S_RECEIVE_ARGS; + } + break; + case S_RECEIVE_ARGS: + if (p_spi_clk.read() == 1 && spi_clk == 0) { + // rising edge + args = (args << 1) | spi_mosi_previous; + if (spi_bitcount == 0) { + spi_bitcount = 7; + spi_fsm = S_RECEIVE_CRC; + } else { + spi_bitcount = spi_bitcount - 1; + } + } + break; + case S_RECEIVE_CRC: + if (p_spi_clk.read() == 1 && spi_clk == 0) { + // rising edge + cmdcrc = (cmdcrc << 1) | spi_mosi_previous; + if (spi_bitcount == 0) { + handle_sdmmc_cmd(command, args); + spi_bitcount = 0; // SEND_DATA will reset it + spi_fsm = S_SEND_DATA; + m_data_idx = 0; + } else { + spi_bitcount = spi_bitcount - 1; + } + } + break; + + case S_SEND_DATA: + if (p_spi_clk.read() == 0 && spi_clk == 1) { + // falling edge + if (spi_bitcount == 0) { + if (m_data_idx != m_datalen_snd) { + spi_shiftreg = m_databuf[m_data_idx]; + spi_bitcount = 7; + spi_fsm = S_SEND_DATA; + m_data_idx++; +#ifdef SOCLIB_MODULE_DEBUG0 + std::cout << name() << " S_SEND_DATA " << std::dec << m_datalen_snd << " idx " << m_data_idx << " " << std::hex << (uint32_t)m_databuf[m_data_idx] << std::endl; +#endif + } else if (m_datalen_rcv != 0) { + spi_fsm = S_RECEIVE_DATA_WAIT; + spi_bitcount = 7; + m_data_idx = 0; + } else { + spi_fsm = S_IDLE; + } + } else { + spi_bitcount = spi_bitcount - 1; + spi_shiftreg = spi_shiftreg << 1; + } + } + break; + case S_RECEIVE_DATA_WAIT: + if (p_spi_clk.read() == 1 && spi_clk == 0) { + // rising edge + uint8_t s_data; + s_data = (m_databuf[0] << 1) | spi_mosi_previous; + m_databuf[0] = s_data; + if (spi_bitcount == 0) { +#ifdef SOCLIB_MODULE_DEBUG + std::cout << name() << " S_RECEIVE_DATA_WAIT " << std::dec << (int)s_data << std::endl; +#endif + spi_bitcount = 7; + if (s_data == 0xfe) { // data start token + spi_fsm = S_RECEIVE_DATA; + m_data_idx = 1; + } else { +#ifdef SOCLIB_MODULE_DEBUG + std::cout << name() << " S_RECEIVE_DATA_WAIT " << std::hex << (int)s_data << std::endl; +#endif + spi_fsm = S_RECEIVE_DATA_WAIT; + } + } else { + spi_bitcount = spi_bitcount - 1; + } + } + break; + case S_RECEIVE_DATA: + if (p_spi_clk.read() == 1 && spi_clk == 0) { + // rising edge + m_databuf[m_data_idx] = (m_databuf[m_data_idx] << 1) | spi_mosi_previous; + if (spi_bitcount == 0) { + m_data_idx++; + if (m_data_idx != m_datalen_rcv) { + spi_fsm = S_RECEIVE_DATA; + spi_bitcount = 7; + } else { + handle_sdmmc_write(command, args); + if (m_datalen_snd > 0) { + spi_bitcount = 0; // SEND_DATA will reset it + spi_fsm = S_SEND_DATA; + m_data_idx = 0; + } else { + spi_fsm = S_IDLE; + } + } + } else { + spi_bitcount = spi_bitcount - 1; + } + } + break; + } + +//// now genrate output signal + + switch(spi_fsm) { + case S_IDLE: + p_spi_miso = !p_spi_ss.read(); + break; + case S_SEND_DATA: + p_spi_miso = (spi_shiftreg & 0x80) != 0; + break; + default: + p_spi_miso = !p_spi_ss.read(); + break; + } + spi_clk = p_spi_clk.read(); + spi_mosi_previous = p_spi_mosi; +} // end GenMealy() + + +////////////////////// +void SdMMC::handle_sdmmc_cmd(uint8_t cmd, uint32_t data) +{ + m_datalen_rcv = 0; + m_databuf[0] = 0x04; // illegal command + m_datalen_snd = 1; + + if (m_sdstate == SD_IDLE) + m_databuf[0] |= 0x01; // idle + + if ((cmd & 0x40) == 0) { + //illegal command + return; + } + cmd &= 0x3f; + if (m_acmd) { +#ifdef SOCLIB_MODULE_DEBUG0 + std::cout << name() << " new acmd " << std::dec << (int)cmd << " args " << std::hex << data << " crc " << (int)cmdcrc << std::endl; +#endif + m_acmd = false; + switch (cmd) { + case 41: + m_databuf[0] = 0x0; // card ready + m_datalen_snd = 1; + m_sdstate = SD_READY; + break; + case 51: + // send SCR + m_databuf[ 0] = (m_sdstate == SD_IDLE) ? 0x1 : 0x0; // R1 + m_databuf[ 1] = 0xfe; // data token + m_databuf[ 2] = 0x00; // SCR_STRUCTURE / SD_SPEC + m_databuf[ 3] = 0x05; // DATA_STAT_AFTER_ERASE, SD_SECURITY, SD_BUS_WIDTHS + m_databuf[ 4] = 0; // SD_SPEC3, EX_SECURITY, SD_SPEC4 + m_databuf[ 5] = 0; // CMD_SUPPORT + m_databuf[ 6] = 0; // vendor specific + m_databuf[ 7] = 0; // vendor specific + m_databuf[ 8] = 0; // vendor specific + m_databuf[ 9] = 0; // vendor specific + m_databuf[10] = 0x0; // CRC16 + m_databuf[11] = 0x0; // CRC16 + m_datalen_snd = 12; + break; + default: + std::cout << name() << " unknown acmd " << std::dec + << (int)cmd << std::endl; + break; // return illegal command + } + } else { +#ifdef SOCLIB_MODULE_DEBUG0 + std::cout << name() << " new cmd " << std::dec << (int)cmd << " args " << std::hex << data << " crc " << (int)cmdcrc << std::endl; +#endif + switch (cmd) { + case 0: + m_databuf[0] = 0x1; + m_datalen_snd = 1; + m_sdstate = SD_IDLE; + break; + case 8: + // reply with illegal command for now + break; + case 9: + { + // send CSD + // we use a block len of 1024 + uint32_t csize = ((m_device_size + (512 * 1024) - 1) / (512 * 1024)) - 1; + m_databuf[ 0] = (m_sdstate == SD_IDLE) ? 0x1 : 0x0; // R1 + m_databuf[ 1] = 0xfe; // data token + m_databuf[ 2] = 0x00; // CSD_STRUCTURE + m_databuf[ 3] = 0xe; // TAAC + m_databuf[ 4] = 0; // NSAC + m_databuf[ 5] = 0x32; // TRAN_SPEED + m_databuf[ 6] = 0x5b; // CCC_H + m_databuf[ 7] = 0x5a; // CCC_L + READ_BL_LEN + m_databuf[ 8] = 0x80; // READ_BL_PARTIAL, R/W_BLK_MISALIGN, DSR_IMP + m_databuf[ 8] |= (csize >> 10) & 0x03; // CSIZE[12-11] + m_databuf[ 9] = (csize >> 2) & 0xff; // CSIZE[10-2] + m_databuf[10] = (csize << 6) & 0xc0; // CSIZE[1-0] + m_databuf[10] |= 0; // R_CURR_MIN, R_CURR_MAX + m_databuf[11] = 0x3; // W_CURR_MIN, W_CURR_MAX, CSIZE_MULT[2-1]; + m_databuf[12] = 0xff; // CSIZE_MULT[1], ERASE_BLK_EN, ERASE_SECTOR_SIZE[6-1] + m_databuf[13] = 0x80; // ERASE_SECTOR_SIZE[0]. WP_GRP_SIZE + m_databuf[14] = 0x0a; // WP_GRP_ENABLE, R2W_FACTOR, WRITE_BL_LEN[2-3] + m_databuf[15] = 0x40; // WRITE_BL_LEN[0-1], WR_BL_PARTIAL + m_databuf[16] = 0; // FILE_FORMAT + m_databuf[17] = 0x1; // CRC7 + m_databuf[18] = 0x0; // CRC16 + m_databuf[19] = 0x0; // CRC16 + m_datalen_snd = 20; + break; + } + case 10: + // send CID + m_databuf[ 0] = (m_sdstate == SD_IDLE) ? 0x1 : 0x0; // R1 + m_databuf[ 1] = 0xfe; // data token + m_databuf[ 2] = 0xda; // MID + m_databuf[ 3] = 'P'; // OID + m_databuf[ 4] = '6'; // OID + m_databuf[ 5] = 's'; // PNM + m_databuf[ 6] = 'o'; // PNM + m_databuf[ 7] = 'c'; // PNM + m_databuf[ 8] = 's'; // PNM + m_databuf[ 9] = 'd'; // PNM + m_databuf[10] = 0x01; // PRV + m_databuf[11] = 0xde; // PSN + m_databuf[12] = 0xad; // PSN + m_databuf[13] = 0xbe; // PSN + m_databuf[14] = 0xef; // PSN + m_databuf[15] = 10; // MDT + m_databuf[16] = 13; // MDT + m_databuf[17] = 0x1; // CRC7 + m_databuf[18] = 0x0; // CRC16 + m_databuf[19] = 0x0; // CRC16 + m_datalen_snd = 20; + break; + case 16: + // set block size + if (m_sdstate != SD_IDLE && data == 512) { + m_databuf[0] = 0x00; + m_datalen_snd = 1; + } // else illegal command + break; + case 17: + { + int ret; + // read data block + if (m_sdstate == SD_IDLE) { + // return illegal command + return; + } + if (data >= m_device_size) { + std::cerr << name() << " read: request " << data + << " past end of file " << m_device_size << std::endl; + m_databuf[0] = 0x00; // R1 OK + m_databuf[1] = 0x08; // error tocken "out of range" + m_datalen_snd = 2; + return; + } + do { + if (lseek(m_fd, data, SEEK_SET) < 0) { + std::cerr << name() << " lseek: " << + strerror(errno) << std::endl; + m_databuf[0] = 0x00; // R1 OK + m_databuf[1] = 0x02; // error tocken "CC err" + m_datalen_snd = 2; + return; + } + ret = read(m_fd, &m_databuf[2], 512); + } while (ret < 0 && errno == EINTR); + if (ret < 0) { + std::cerr << name() << " read: " << + strerror(errno) << std::endl; + m_databuf[0] = 0x00; // R1 OK + m_databuf[1] = 0x04; // error tocken "card ECC failed" + m_datalen_snd = 2; + return; + } + m_databuf[514] = m_databuf[515] = 0; // XXX CRC + m_databuf[0] = 0x0; // R1 + m_databuf[1] = 0xfe; // start block tocken + m_datalen_snd = 516; + break; + } + case 24: + { + // write data block + if (m_sdstate == SD_IDLE) { + // return illegal command + return; + } +#ifdef SOCLIB_MODULE_DEBUG + std::cout << name() << " new cmd write " << std::dec << (int)cmd << " args " << std::hex << data << std::endl; +#endif + m_databuf[0] = 0x0; // R1 + m_datalen_snd = 1; + m_datalen_rcv = 512 + 2 + 1; // data + tocken + CRC + break; + } + case 55: + // app-specific command follow + m_acmd = true; + m_databuf[0] = (m_sdstate == SD_IDLE) ? 0x1 : 0x0; + m_datalen_snd = 1; + break; + case 58: + // send OCR + m_databuf[4] = (m_sdstate == SD_IDLE) ? 0x1 : 0x0; // R1 + m_databuf[3] = 0x80; // power up complete, SDSC + m_databuf[2] = 0xff; // all voltages supported + m_databuf[1] = 0x00; + m_databuf[0] = 0x00; + m_datalen_snd = 5; + break; + default: + std::cout << name() << " unknown cmd " << std::dec + << (int)cmd << std::endl; + break; // return illegal command + } + } +} + +void SdMMC::handle_sdmmc_write(uint8_t cmd, uint32_t data) +{ + m_datalen_rcv = 0; + cmd &= 0x3f; +#ifdef SOCLIB_MODULE_DEBUG + std::cout << name() << " cmd write " << std::dec << (int)cmd << " args " << std::hex << data << std::endl; +#endif + switch(cmd) { + case 24: + { + int ret; + // write data block + assert(m_sdstate != SD_IDLE && "can't write in idle state"); + if (data >= m_device_size) { + std::cerr << name() << " write: request " << data + << " past end of file " << m_device_size << std::endl; + m_databuf[0] = 0xd; // write error + m_datalen_snd = 1; + return; + } + do { + if (lseek(m_fd, data, SEEK_SET) < 0) { + std::cerr << name() << " lseek: " << + strerror(errno) << std::endl; + m_databuf[0] = 0xd; // write error + m_datalen_snd = 1; + return; + } + ret = write(m_fd, &m_databuf[1], 512); + } while (ret < 0 && errno == EINTR); + if (ret < 0) { + std::cerr << name() << " write: " << + strerror(errno) << std::endl; + m_databuf[0] = 0xd; // write error + m_datalen_snd = 1; + return; + } + m_databuf[0] = 0x5; // write complete + m_databuf[1] = 0x0; // busy + m_datalen_snd = 2; + break; + } + default: + std::cerr << name() << " unkown write cmd " << std::dec << + (int)cmd << std::endl; + m_databuf[0] = 0xd; // write error; + m_datalen_snd = 1; + } + return; +} + +////////////////////////////////////////////////////////////////////////////// +SdMMC::SdMMC( sc_core::sc_module_name name, + const std::string &filename, + const uint32_t latency) + +: caba::BaseModule(name), + m_latency(latency), + p_clk("p_clk"), + p_resetn("p_resetn"), + p_spi_ss("p_spi_ss"), + p_spi_clk("p_spi_clk"), + p_spi_mosi("p_spi_mosi"), + p_spi_miso("p_spi_miso") +{ + std::cout << " - Building SdMMC " << name << std::endl; + + SC_METHOD(genMealy); + dont_initialize(); + sensitive << p_clk.neg(); + sensitive << p_resetn; + sensitive << p_spi_ss; + sensitive << p_spi_clk; + + m_fd = ::open(filename.c_str(), O_RDWR); + if ( m_fd < 0 ) + { + std::cout << "Error in component SdMMC : " << name + << " Unable to open file " << filename << std::endl; + exit(1); + } + m_device_size = lseek(m_fd, 0, SEEK_END); + +} // end constructor + +SdMMC::~SdMMC() +{ +} + + +////////////////////////// +void SdMMC::print_trace() +{ + const char* spi_str[] = + { + "S_IDLE", + "S_RECEIVE_CMD", + "S_RECEIVE_ARGS_START", + "S_RECEIVE_ARGS", + "S_RECEIVE_CRC", + "S_RECEIVE_DATA_START", + "S_RECEIVE_DATA", + "S_SEND_DATA", + "S_NOP", + }; + if (spi_clk != p_spi_clk.read()) { + std::cout << name() << " SPI_FSM : " << spi_str[spi_fsm] + << std::dec + << " clk " << spi_clk << "->" << p_spi_clk << " ss " << p_spi_ss + << " mosi " << p_spi_mosi << " miso " << p_spi_miso + << std::endl; + std::cout << " spi_shiftreg: " << std::hex << (int)spi_shiftreg + << " spi_bitcount: " << (int)spi_bitcount + << std::endl; + } +} +}} // end namespace + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: /branches/fault_tolerance/modules/vci_block_device_tsar/caba/metadata/vci_block_device_tsar.sd =================================================================== --- /branches/fault_tolerance/modules/vci_block_device_tsar/caba/metadata/vci_block_device_tsar.sd (revision 724) +++ /branches/fault_tolerance/modules/vci_block_device_tsar/caba/metadata/vci_block_device_tsar.sd (revision 724) @@ -0,0 +1,51 @@ + +# -*- python -*- + +Module('caba:vci_block_device_tsar', + classname = 'soclib::caba::VciBlockDeviceTsar', + + tmpl_parameters = [ + parameter.Module('vci_param', default = 'caba:vci_param'), + ], + + header_files = [ + '../source/include/vci_block_device_tsar.h', + ], + + interface_files = [ + '../../include/soclib/block_device_tsar.h', + ], + + implementation_files = [ + '../source/src/vci_block_device_tsar.cpp', + ], + + ports = [ + Port('caba:vci_target', 'p_vci_target'), + Port('caba:vci_initiator', 'p_vci_initiator'), + Port('caba:bit_out', 'p_irq'), + Port('caba:bit_in', 'p_resetn', auto = 'resetn'), + Port('caba:clock_in', 'p_clk', auto = 'clock'), + ], + + uses = [ + Uses('caba:base_module'), + Uses('common:mapping_table'), + ], + + instance_parameters = [ + parameter.Module('mt', typename = 'common:mapping_table', auto = 'env:mapping_table'), + parameter.IntTab('srcid'), + parameter.IntTab('tgtid'), + parameter.String('filename'), + parameter.Int('block_size', default=512), + parameter.Int('burst_size', default=64), + parameter.Int('latency', default=0), + ], + + extensions = [ + 'dsx:addressable=tgtid', + 'dsx:max_segments=1', + 'dsx:get_ident=tgtid:p_vci_target:mt,srcid:p_vci_initiator:mt', + ], +) Index: /branches/fault_tolerance/modules/vci_block_device_tsar/caba/source/include/vci_block_device_tsar.h =================================================================== --- /branches/fault_tolerance/modules/vci_block_device_tsar/caba/source/include/vci_block_device_tsar.h (revision 724) +++ /branches/fault_tolerance/modules/vci_block_device_tsar/caba/source/include/vci_block_device_tsar.h (revision 724) @@ -0,0 +1,251 @@ + +/* -*- c++ -*- + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, Asim + * alain.greiner@lip6.fr april 2011 + * + * Maintainers: alain + */ + +////////////////////////////////////////////////////////////////////////////////////// +// This component is a simplified disk controller with a VCI interface. +// It supports only 32 or 64 bits VCI DATA width, but all addressable registers +// contain 32 bits words. It supports VCI addresss lartger than 32 bits. +// +// This component can perform data transfers between one single file belonging +// to the host system and a buffer in the memory of the virtual prototype. +// The file name is an argument of the constructor. +// This component has a DMA capability, and is both a target and an initiator. +// The block size (bytes), and the burst size (bytes) must be power of 2. +// The burst size is typically a cache line. +// The memory buffer is not constrained to be aligned on a burst boundary, +// but must be aligned on a 32 bits word boundary. +// Both read and write transfers are supported. An IRQ is optionally +// asserted when the transfer is completed. +// +// As a target this block device controler contains 9 32 bits memory mapped registers, +// taking 36 bytes in the address space. +// - BLOCK_DEVICE_BUFFER 0x00 (read/write) Memory buffer base address (LSB bits) +// - BLOCK_DEVICE_COUNT 0x04 (read/write) Number of blocks to be transfered. +// - BLOCK_DEVICE_LBA 0x08 (read/write) Index of first block in the file. +// - BLOCK_DEVICE_OP 0x0C (write-only) Writing here starts the operation. +// - BLOCK_DEVICE_STATUS 0x10 (read-only) Block Device status. +// - BLOCK_DEVICE_IRQ_ENABLE 0x14 (read/write) IRQ enabled if non zero. +// - BLOCK_DEVICE_SIZE 0x18 (read-only) Number of addressable blocks. +// - BLOCK_DEVICE_BLOCK_SIZE 0x1C (read_only) Block size in bytes. +// - BLOCK_DEVICE_BUFFER_EXT 0x20 (read_only) Memory buffer base address (MSB bits) +// +// The following operations codes are supported: +// - BLOCK_DEVICE_NOOP No operation +// - BLOCK_DEVICE_READ From block device to memory +// - BLOCK_DEVICE_WRITE From memory to block device +// +// The BLOCK_DEVICE_STATUS is actually defined by the initiator FSM state. +// The following values are defined for device status: +// -BLOCK_DEVICE_IDLE 0 +// -BLOCK_DEVICE_BUSY 1 +// -BLOCK_DEVICE_READ_SUCCESS 2 +// -BLOCK_DEVICE_WRITE_SUCCESS 3 +// -BLOCK_DEVICE_READ_ERROR 4 +// -BLOCK_DEVICE_WRITE_ERROR 5 +// +// In the 4 states READ_ERROR, READ_SUCCESS, WRITE_ERROR, WRITE_SUCCESS, +// the IRQ is asserted (if it is enabled). +// A read access to the BLOCK_DEVICE_STATUS in these 4 states reset +// the initiator FSM state to IDLE, and acknowledge the IRQ. +// Any write access to registers BUFFER, COUNT, LBA, OP is ignored +// if the device is not IDLE. +/////////////////////////////////////////////////////////////////////////// + +#ifndef SOCLIB_VCI_BLOCK_DEVICE_TSAR_H +#define SOCLIB_VCI_BLOCK_DEVICE_TSAR_H + +#include +#include +#include +#include "caba_base_module.h" +#include "mapping_table.h" +#include "vci_initiator.h" +#include "vci_target.h" + +namespace soclib { +namespace caba { + +using namespace sc_core; + +template +class VciBlockDeviceTsar + : public caba::BaseModule +{ +private: + + // Registers + sc_signal r_target_fsm; // target fsm state register + sc_signal r_initiator_fsm; // initiator fsm state register + sc_signal r_irq_enable; // default value is true + sc_signal r_nblocks; // number of blocks in transfer + sc_signal r_buf_address; // memory buffer address + sc_signal r_lba; // first block index + sc_signal r_read; // requested operation + sc_signal r_index; // word index in local buffer + sc_signal r_latency_count; // latency counter + sc_signal r_words_count; // word counter (in a burst) + sc_signal r_burst_count; // burst counter (in a block) + sc_signal r_block_count; // block counter (in a transfer) + sc_signal r_burst_offset; // number of non aligned words + sc_signal r_burst_nwords; // number of words in a burst + sc_signal r_go; // command from T_FSM to M_FSM + + sc_signal r_srcid; // save srcid + sc_signal r_trdid; // save trdid + sc_signal r_pktid; // save pktid + sc_signal r_tdata; // save wdata + + uint32_t* r_local_buffer; // capacity is one block + + // structural parameters + std::list m_seglist; + uint32_t m_srcid; // initiator index + int m_fd; // File descriptor + uint64_t m_device_size; // Total number of blocks + const uint32_t m_words_per_block; // number of words in a block + const uint32_t m_words_per_burst; // number of words in a burst + const uint32_t m_bursts_per_block; // number of bursts in a block + const uint32_t m_latency; // device latency + + // methods + void transition(); + void genMoore(); + + // Master FSM states + enum { + M_IDLE = 0, + + M_READ_BLOCK = 1, + M_READ_BURST = 2, + M_READ_CMD = 3, + M_READ_RSP = 4, + M_READ_SUCCESS = 5, + M_READ_ERROR = 6, + + M_WRITE_BURST = 7, + M_WRITE_CMD = 8, + M_WRITE_RSP = 9, + M_WRITE_BLOCK = 10, + M_WRITE_SUCCESS = 11, + M_WRITE_ERROR = 12, + }; + + // Target FSM states + enum { + T_IDLE = 0, + T_WRITE_BUFFER = 1, + T_READ_BUFFER = 2, + T_WRITE_BUFFER_EXT = 3, + T_READ_BUFFER_EXT = 4, + T_WRITE_COUNT = 5, + T_READ_COUNT = 6, + T_WRITE_LBA = 7, + T_READ_LBA = 8, + T_WRITE_OP = 9, + T_READ_STATUS = 10, + T_WRITE_IRQEN = 11, + T_READ_IRQEN = 12, + T_READ_SIZE = 13, + T_READ_BLOCK = 14, + T_READ_ERROR = 15, + T_WRITE_ERROR = 16, + }; + + // Error codes values + enum { + VCI_READ_OK = 0, + VCI_READ_ERROR = 1, + VCI_WRITE_OK = 2, + VCI_WRITE_ERROR = 3, + }; + + /* transaction type, pktid field */ + enum transaction_type_e + { + // b3 unused + // b2 READ / NOT READ + // Si READ + // b1 DATA / INS + // b0 UNC / MISS + // Si NOT READ + // b1 accÚs table llsc type SW / other + // b2 WRITE/CAS/LL/SC + TYPE_READ_DATA_UNC = 0x0, + TYPE_READ_DATA_MISS = 0x1, + TYPE_READ_INS_UNC = 0x2, + TYPE_READ_INS_MISS = 0x3, + TYPE_WRITE = 0x4, + TYPE_CAS = 0x5, + TYPE_LL = 0x6, + TYPE_SC = 0x7 + }; + +protected: + + SC_HAS_PROCESS(VciBlockDeviceTsar); + +public: + + // ports + sc_in p_clk; + sc_in p_resetn; + soclib::caba::VciInitiator p_vci_initiator; + soclib::caba::VciTarget p_vci_target; + sc_out p_irq; + + void print_trace(); + + // Constructor + VciBlockDeviceTsar( + sc_module_name name, + const soclib::common::MappingTable &mt, + const soclib::common::IntTab &srcid, + const soclib::common::IntTab &tgtid, + const std::string &filename, + const uint32_t block_size = 512, + const uint32_t burst_size = 64, + const uint32_t latency = 0); + + ~VciBlockDeviceTsar(); + +}; + +}} + +#endif /* SOCLIB_VCI_BLOCK_DEVICE_TSAR_H */ + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: /branches/fault_tolerance/modules/vci_block_device_tsar/caba/source/src/vci_block_device_tsar.cpp =================================================================== --- /branches/fault_tolerance/modules/vci_block_device_tsar/caba/source/src/vci_block_device_tsar.cpp (revision 724) +++ /branches/fault_tolerance/modules/vci_block_device_tsar/caba/source/src/vci_block_device_tsar.cpp (revision 724) @@ -0,0 +1,917 @@ +/* -*- c++ -*- + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, Asim + * alain.greiner@lip6.fr april 2011 + * + * Maintainers: alain + */ + +#include +#include +#include +#include "vci_block_device_tsar.h" +#include "block_device_tsar.h" + +#define DEBUG_BDEV 0 + +namespace soclib { namespace caba { + +#define tmpl(t) template t VciBlockDeviceTsar + +using namespace soclib::caba; +using namespace soclib::common; + +//////////////////////// +tmpl(void)::transition() +{ + if(p_resetn.read() == false) + { + r_initiator_fsm = M_IDLE; + r_target_fsm = T_IDLE; + r_irq_enable = true; + r_go = false; + return; + } + + ////////////////////////////////////////////////////////////////////////////// + // The Target FSM controls the following registers: + // r_target_fsm, r_irq_enable, r_nblocks, r_buf adress, r_lba, r_go, r_read + ////////////////////////////////////////////////////////////////////////////// + + switch(r_target_fsm) { + //////////// + case T_IDLE: + { + if ( p_vci_target.cmdval.read() ) + { + r_srcid = p_vci_target.srcid.read(); + r_trdid = p_vci_target.trdid.read(); + r_pktid = p_vci_target.pktid.read(); + sc_dt::sc_uint address = p_vci_target.address.read(); + + bool found = false; + std::list::iterator seg; + for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) + { + if ( seg->contains(address) ) found = true; + } + + bool read = (p_vci_target.cmd.read() == vci_param::CMD_READ); + uint32_t cell = (uint32_t)((address & 0x3F)>>2); + + if ( !read && not found ) r_target_fsm = T_WRITE_ERROR; + else if( read && not found ) r_target_fsm = T_READ_ERROR; + else if( !read && not p_vci_target.eop.read() ) r_target_fsm = T_WRITE_ERROR; + else if( read && not p_vci_target.eop.read() ) r_target_fsm = T_READ_ERROR; + else if( !read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_WRITE_BUFFER; + else if( read && (cell == BLOCK_DEVICE_BUFFER) ) r_target_fsm = T_READ_BUFFER; + else if( !read && (cell == BLOCK_DEVICE_BUFFER_EXT) ) r_target_fsm = T_WRITE_BUFFER_EXT; + else if( read && (cell == BLOCK_DEVICE_BUFFER_EXT) ) r_target_fsm = T_READ_BUFFER_EXT; + else if( !read && (cell == BLOCK_DEVICE_COUNT) ) r_target_fsm = T_WRITE_COUNT; + else if( read && (cell == BLOCK_DEVICE_COUNT) ) r_target_fsm = T_READ_COUNT; + else if( !read && (cell == BLOCK_DEVICE_LBA) ) r_target_fsm = T_WRITE_LBA; + else if( read && (cell == BLOCK_DEVICE_LBA) ) r_target_fsm = T_READ_LBA; + else if( !read && (cell == BLOCK_DEVICE_OP) ) r_target_fsm = T_WRITE_OP; + else if( read && (cell == BLOCK_DEVICE_STATUS) ) r_target_fsm = T_READ_STATUS; + else if( !read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_WRITE_IRQEN; + else if( read && (cell == BLOCK_DEVICE_IRQ_ENABLE) ) r_target_fsm = T_READ_IRQEN; + else if( read && (cell == BLOCK_DEVICE_SIZE) ) r_target_fsm = T_READ_SIZE; + else if( read && (cell == BLOCK_DEVICE_BLOCK_SIZE) ) r_target_fsm = T_READ_BLOCK; + + // get write data value for both 32 bits and 64 bits data width + if( (vci_param::B == 8) and (p_vci_target.be.read() == 0xF0) ) + r_tdata = (uint32_t)(p_vci_target.wdata.read()>>32); + else + r_tdata = p_vci_target.wdata.read(); + } + break; + } + //////////////////// + case T_WRITE_BUFFER: + { + if (p_vci_target.rspack.read() ) + { + if (r_initiator_fsm.read() == M_IDLE) + { + +#if DEBUG_BDEV +std::cout << " value = " << r_tdata.read() << std::endl; +#endif + r_buf_address = (uint64_t)r_tdata.read(); + r_target_fsm = T_IDLE; + } + } + break; + } + //////////////////////// + case T_WRITE_BUFFER_EXT: + { + if (p_vci_target.rspack.read() ) + { + if (r_initiator_fsm.read() == M_IDLE) + { + +#if DEBUG_BDEV +std::cout << " value = " << r_tdata.read() << std::endl; +#endif + r_buf_address = r_buf_address.read() + (((uint64_t)r_tdata.read())<<32); + r_target_fsm = T_IDLE; + } + } + break; + } + /////////////////// + case T_WRITE_COUNT: + { + if (p_vci_target.rspack.read() ) + { + if (r_initiator_fsm.read() == M_IDLE) + { + +#if DEBUG_BDEV +std::cout << " value = " << r_tdata.read() << std::endl; +#endif + r_nblocks = (uint32_t)r_tdata.read(); + r_target_fsm = T_IDLE; + } + } + break; + } + ///////////////// + case T_WRITE_LBA: + { + if (p_vci_target.rspack.read() ) + { + if (r_initiator_fsm.read() == M_IDLE) + { + +#if DEBUG_BDEV +std::cout << " value = " << r_tdata.read() << std::endl; +#endif + r_lba = (uint32_t)r_tdata.read(); + r_target_fsm = T_IDLE; + } + } + break; + } + //////////////// + case T_WRITE_OP: + { + if ( p_vci_target.rspack.read() ) + { + if ( ((uint32_t)r_tdata.read() == BLOCK_DEVICE_READ) and + (r_initiator_fsm.read() == M_IDLE) ) + { + +#if DEBUG_BDEV +std::cout << " value = READ" << std::endl; +#endif + r_read = true; + r_go = true; + } + else if ( ((uint32_t)r_tdata.read() == BLOCK_DEVICE_WRITE) and + (r_initiator_fsm.read() == M_IDLE) ) + { + +#if DEBUG_BDEV +std::cout << " value = WRITE" << std::endl; +#endif + r_read = false; + r_go = true; + } + else + { + +#if DEBUG_BDEV +std::cout << " value = SOFT RESET" << std::endl; +#endif + r_go = false; + } + r_target_fsm = T_IDLE; + } + break; + } + /////////////////// + case T_WRITE_IRQEN: + { + if ( p_vci_target.rspack.read() ) + { + +#if DEBUG_BDEV +std::cout << " value = " << r_tdata.read() << std::endl; +#endif + r_target_fsm = T_IDLE; + r_irq_enable = (r_tdata.read() != 0); + } + break; + } + /////////////////// + case T_READ_BUFFER: + case T_READ_BUFFER_EXT: + case T_READ_COUNT: + case T_READ_LBA: + case T_READ_IRQEN: + case T_READ_SIZE: + case T_READ_BLOCK: + case T_READ_ERROR: + case T_WRITE_ERROR: + { + if ( p_vci_target.rspack.read() ) r_target_fsm = T_IDLE; + break; + } + /////////////////// + case T_READ_STATUS: + { + if ( p_vci_target.rspack.read() ) + { + r_target_fsm = T_IDLE; + if( (r_initiator_fsm == M_READ_SUCCESS ) || + (r_initiator_fsm == M_READ_ERROR ) || + (r_initiator_fsm == M_WRITE_SUCCESS) || + (r_initiator_fsm == M_WRITE_ERROR ) ) r_go = false; + } + break; + } + } // end switch target fsm + + ////////////////////////////////////////////////////////////////////////////// + // The initiator FSM executes a loop, transfering one block per iteration. + // Each block is split in bursts, and the number of bursts depends + // on the memory buffer alignment on a burst boundary: + // - If buffer aligned, all burst have the same length (m_words_per burst) + // and the number of bursts is (m_bursts_per_block). + // - If buffer not aligned, the number of bursts is (m_bursts_per_block + 1) + // and first and last burst are shorter, because all words in a burst + // must be contained in a single cache line. + // first burst => nwords = m_words_per_burst - offset + // last burst => nwords = offset + // other burst => nwords = m_words_per_burst + ////////////////////////////////////////////////////////////////////////////// + + switch( r_initiator_fsm.read() ) { + //////////// + case M_IDLE: // check buffer alignment to compute the number of bursts + { + if ( r_go.read() ) + { + r_index = 0; + r_block_count = 0; + r_burst_count = 0; + r_words_count = 0; + r_latency_count = m_latency; + + // compute r_burst_offset (zero when buffer aligned) + r_burst_offset = (uint32_t)((r_buf_address.read()>>2) % m_words_per_burst); + + // start tranfer + if ( r_read.read() ) r_initiator_fsm = M_READ_BLOCK; + else r_initiator_fsm = M_WRITE_BURST; + } + break; + } + ////////////////// + case M_READ_BLOCK: // read one block from disk after waiting m_latency cycles + { + if ( r_latency_count.read() == 0 ) + { + r_latency_count = m_latency; + ::lseek(m_fd, (r_lba + r_block_count)*m_words_per_block*4, SEEK_SET); + if( ::read(m_fd, r_local_buffer, m_words_per_block*4) < 0 ) + { + r_initiator_fsm = M_READ_ERROR; + } + else + { + r_burst_count = 0; + r_words_count = 0; + r_initiator_fsm = M_READ_BURST; + } + +//////////////////////////////////////////////////////////////////////////////////////// +//std::cout << "***** Block content after read for lba " +// << std::hex << r_lba.read() << " **************" << std::endl; +//for ( size_t line=0 ; line<16 ; line++ ) +//{ +// for ( size_t word=0 ; word<8 ; word++ ) +// { +// std::cout << std::hex << r_local_buffer[line*8 + word] << " "; +// } +// std::cout << std::endl; +//} +//std::cout << "**********************************************************" << std::endl; +//////////////////////////////////////////////////////////////////////////////////////// + + } + else + { + r_latency_count = r_latency_count.read() - 1; + } + break; + } + ////////////////// + case M_READ_BURST: // Compute the number of words and the number of flits in the burst + // The number of flits can be smaller than the number of words + // in case of 8 bytes flits... + { + uint32_t nwords; + uint32_t offset = r_burst_offset.read(); + + if ( offset ) // buffer not aligned + { + if ( r_burst_count.read() == 0 ) nwords = m_words_per_burst - offset; + else if ( r_burst_count.read() == m_bursts_per_block ) nwords = offset; + else nwords = m_words_per_burst; + } + else // buffer aligned + { + nwords = m_words_per_burst; + } + + r_burst_nwords = nwords; + r_initiator_fsm = M_READ_CMD; + break; + } + //////////////// + case M_READ_CMD: // Send a multi-flits VCI WRITE command + { + if ( p_vci_initiator.cmdack.read() ) + { + uint32_t nwords = r_burst_nwords.read() - r_words_count.read(); + + if ( vci_param::B == 4 ) // one word per flit + { + if ( nwords <= 1 ) // last flit + { + r_initiator_fsm = M_READ_RSP; + r_words_count = 0; + } + else // not the last flit + { + r_words_count = r_words_count.read() + 1; + } + + // compute next word address and next local buffer index + r_buf_address = r_buf_address.read() + 4; + r_index = r_index.read() + 1; + } + else // 2 words per flit + { + if ( nwords <= 2 ) // last flit + { + r_initiator_fsm = M_READ_RSP; + r_words_count = 0; + } + else // not the last flit + { + r_words_count = r_words_count.read() + 2; + } + + // compute next word address and next local buffer index + if ( nwords == 1 ) + { + r_buf_address = r_buf_address.read() + 4; + r_index = r_index.read() + 1; + } + else + { + r_buf_address = r_buf_address.read() + 8; + r_index = r_index.read() + 2; + } + } + } + break; + } + //////////////// + case M_READ_RSP: // Wait a single flit VCI WRITE response + { + if ( p_vci_initiator.rspval.read() ) + { + bool aligned = (r_burst_offset.read() == 0); + + if ( (p_vci_initiator.rerror.read()&0x1) != 0 ) + { + r_initiator_fsm = M_READ_ERROR; + } + else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or + (aligned and (r_burst_count.read() == (m_bursts_per_block-1))) ) + { + if ( r_block_count.read() == (r_nblocks.read()-1) ) // last burst of last block + { + r_initiator_fsm = M_READ_SUCCESS; + } + else // last burst not last block + { + r_index = 0; + r_burst_count = 0; + r_block_count = r_block_count.read() + 1; + r_initiator_fsm = M_READ_BLOCK; + } + } + else // not the last burst + { + r_burst_count = r_burst_count.read() + 1; + r_initiator_fsm = M_READ_BURST; + } + } + break; + } + /////////////////// + case M_READ_SUCCESS: + case M_READ_ERROR: + { + if( !r_go ) r_initiator_fsm = M_IDLE; + break; + } + /////////////////// + case M_WRITE_BURST: // Compute the number of words in the burst + { + uint32_t nwords; + uint32_t offset = r_burst_offset.read(); + + if ( offset ) // buffer not aligned + { + if ( r_burst_count.read() == 0 ) nwords = m_words_per_burst - offset; + else if ( r_burst_count.read() == m_bursts_per_block ) nwords = offset; + else nwords = m_words_per_burst; + } + else // buffer aligned + { + nwords = m_words_per_burst; + } + + r_burst_nwords = nwords; + r_initiator_fsm = M_WRITE_CMD; + break; + } + ///////////////// + case M_WRITE_CMD: // This is actually a single flit VCI READ command + { + if ( p_vci_initiator.cmdack.read() ) r_initiator_fsm = M_WRITE_RSP; + break; + } + ///////////////// + case M_WRITE_RSP: // This is actually a multi-words VCI READ response + { + if ( p_vci_initiator.rspval.read() ) + { + bool aligned = (r_burst_offset.read() == 0); + + if ( (vci_param::B == 8) and (r_burst_nwords.read() > 1) ) + { + r_local_buffer[r_index.read()] = (uint32_t)p_vci_initiator.rdata.read(); + r_local_buffer[r_index.read()+1] = (uint32_t)(p_vci_initiator.rdata.read()>>32); + r_index = r_index.read() + 2; + } + else + { + r_local_buffer[r_index.read()] = (uint32_t)p_vci_initiator.rdata.read(); + r_index = r_index.read() + 1; + } + + if ( p_vci_initiator.reop.read() ) // last flit of the burst + { + r_words_count = 0; + r_buf_address = r_buf_address.read() + (r_burst_nwords.read()<<2); + + if( (p_vci_initiator.rerror.read()&0x1) != 0 ) + { + r_initiator_fsm = M_WRITE_ERROR; + } + else if ( (not aligned and (r_burst_count.read() == m_bursts_per_block)) or + (aligned and (r_burst_count.read() == (m_bursts_per_block-1))) ) // last burst + { + r_initiator_fsm = M_WRITE_BLOCK; + } + else // not the last burst + { + r_burst_count = r_burst_count.read() + 1; + r_initiator_fsm = M_WRITE_BURST; + } + } + else + { + r_words_count = r_words_count.read() + 1; + } + } + break; + } + /////////////////// + case M_WRITE_BLOCK: // write a block to disk after waiting m_latency cycles + { + if ( r_latency_count == 0 ) + { + +//////////////////////////////////////////////////////////////////////////////////////// +//std::cout << "***** Block content before write for lba " +// << std::hex << r_lba.read() << " ***********" << std::endl; +//for ( size_t line=0 ; line<16 ; line++ ) +//{ +// for ( size_t word=0 ; word<8 ; word++ ) +// { +// std::cout << std::hex << r_local_buffer[line*8 + word] << " "; +// } +// std::cout << std::endl; +//} +//std::cout << "**********************************************************" << std::endl; +//////////////////////////////////////////////////////////////////////////////////////// + + r_latency_count = m_latency; + ::lseek(m_fd, (r_lba + r_block_count)*m_words_per_block*4, SEEK_SET); + if( ::write(m_fd, r_local_buffer, m_words_per_block*4) < 0 ) + { + r_initiator_fsm = M_WRITE_ERROR; + } + else if ( r_block_count.read() == r_nblocks.read() - 1 ) + { + r_initiator_fsm = M_WRITE_SUCCESS; + } + else + { + r_burst_count = 0; + r_index = 0; + r_block_count = r_block_count.read() + 1; + r_initiator_fsm = M_WRITE_BURST; + } + } + else + { + r_latency_count = r_latency_count - 1; + } + break; + } + ///////////////////// + case M_WRITE_SUCCESS: + case M_WRITE_ERROR: + { + if( !r_go ) r_initiator_fsm = M_IDLE; + break; + } + } // end switch r_initiator_fsm +} // end transition + +////////////////////// +tmpl(void)::genMoore() +{ + // p_vci_target port + p_vci_target.rsrcid = (sc_dt::sc_uint)r_srcid.read(); + p_vci_target.rtrdid = (sc_dt::sc_uint)r_trdid.read(); + p_vci_target.rpktid = (sc_dt::sc_uint)r_pktid.read(); + p_vci_target.reop = true; + + switch(r_target_fsm) { + case T_IDLE: + p_vci_target.cmdack = true; + p_vci_target.rspval = false; + p_vci_target.rdata = 0; + break; + case T_READ_STATUS: + p_vci_target.cmdack = false; + p_vci_target.rspval = true; + if (r_initiator_fsm == M_IDLE) p_vci_target.rdata = BLOCK_DEVICE_IDLE; + else if(r_initiator_fsm == M_READ_SUCCESS) p_vci_target.rdata = BLOCK_DEVICE_READ_SUCCESS; + else if(r_initiator_fsm == M_WRITE_SUCCESS) p_vci_target.rdata = BLOCK_DEVICE_WRITE_SUCCESS; + else if(r_initiator_fsm == M_READ_ERROR) p_vci_target.rdata = BLOCK_DEVICE_READ_ERROR; + else if(r_initiator_fsm == M_WRITE_ERROR) p_vci_target.rdata = BLOCK_DEVICE_WRITE_ERROR; + else p_vci_target.rdata = BLOCK_DEVICE_BUSY; + p_vci_target.rerror = VCI_READ_OK; + break; + case T_READ_BUFFER: + p_vci_target.cmdack = false; + p_vci_target.rspval = true; + p_vci_target.rdata = (uint32_t)r_buf_address.read(); + p_vci_target.rerror = VCI_READ_OK; + break; + case T_READ_BUFFER_EXT: + p_vci_target.cmdack = false; + p_vci_target.rspval = true; + p_vci_target.rdata = (uint32_t)(r_buf_address.read()>>32); + p_vci_target.rerror = VCI_READ_OK; + break; + case T_READ_COUNT: + p_vci_target.cmdack = false; + p_vci_target.rspval = true; + p_vci_target.rdata = r_nblocks.read(); + p_vci_target.rerror = VCI_READ_OK; + break; + case T_READ_LBA: + p_vci_target.cmdack = false; + p_vci_target.rspval = true; + p_vci_target.rdata = r_lba.read(); + p_vci_target.rerror = VCI_READ_OK; + break; + case T_READ_IRQEN: + p_vci_target.cmdack = false; + p_vci_target.rspval = true; + p_vci_target.rdata = r_irq_enable.read(); + p_vci_target.rerror = VCI_READ_OK; + break; + case T_READ_SIZE: + p_vci_target.cmdack = false; + p_vci_target.rspval = true; + p_vci_target.rdata = m_device_size; + p_vci_target.rerror = VCI_READ_OK; + break; + case T_READ_BLOCK: + p_vci_target.cmdack = false; + p_vci_target.rspval = true; + p_vci_target.rdata = m_words_per_block*4; + p_vci_target.rerror = VCI_READ_OK; + break; + case T_READ_ERROR: + p_vci_target.cmdack = false; + p_vci_target.rspval = true; + p_vci_target.rdata = 0; + p_vci_target.rerror = VCI_READ_ERROR; + break; + case T_WRITE_ERROR: + p_vci_target.cmdack = false; + p_vci_target.rspval = true; + p_vci_target.rdata = 0; + p_vci_target.rerror = VCI_WRITE_ERROR; + break; + default: + p_vci_target.cmdack = false; + p_vci_target.rspval = true; + p_vci_target.rdata = 0; + p_vci_target.rerror = VCI_WRITE_OK; + break; + } // end switch target fsm + + // p_vci_initiator port + p_vci_initiator.srcid = (sc_dt::sc_uint)m_srcid; + p_vci_initiator.trdid = 0; + p_vci_initiator.contig = true; + p_vci_initiator.cons = false; + p_vci_initiator.wrap = false; + p_vci_initiator.cfixed = false; + p_vci_initiator.clen = 0; + + switch (r_initiator_fsm) { + case M_WRITE_CMD: // It is actually a single flit VCI read command + p_vci_initiator.rspack = false; + p_vci_initiator.cmdval = true; + p_vci_initiator.address = (sc_dt::sc_uint)r_buf_address.read(); + p_vci_initiator.cmd = vci_param::CMD_READ; + p_vci_initiator.pktid = TYPE_READ_DATA_UNC; + p_vci_initiator.wdata = 0; + p_vci_initiator.be = 0; + p_vci_initiator.plen = (sc_dt::sc_uint)(r_burst_nwords.read()<<2); + p_vci_initiator.eop = true; + break; + case M_READ_CMD: // It is actually a multi-words VCI WRITE command + p_vci_initiator.rspack = false; + p_vci_initiator.cmdval = true; + p_vci_initiator.address = (sc_dt::sc_uint)r_buf_address.read(); + p_vci_initiator.cmd = vci_param::CMD_WRITE; + p_vci_initiator.pktid = TYPE_WRITE; + p_vci_initiator.plen = (sc_dt::sc_uint)(r_burst_nwords.read()<<2); + if ( (vci_param::B == 8) and ((r_burst_nwords.read() - r_words_count.read()) > 1) ) + { + p_vci_initiator.wdata = ((uint64_t)r_local_buffer[r_index.read() ]) + + (((uint64_t)r_local_buffer[r_index.read()+1]) << 32); + p_vci_initiator.be = 0xFF; + p_vci_initiator.eop = ( (r_burst_nwords.read() - r_words_count.read()) <= 2 ); + } + else + { + p_vci_initiator.wdata = r_local_buffer[r_index.read()]; + p_vci_initiator.be = 0xF; + p_vci_initiator.eop = ( r_words_count.read() == (r_burst_nwords.read() - 1) ); + } + break; + case M_READ_RSP: + case M_WRITE_RSP: + p_vci_initiator.rspack = true; + p_vci_initiator.cmdval = false; + break; + default: + p_vci_initiator.rspack = false; + p_vci_initiator.cmdval = false; + break; + } + + // IRQ signal + if ( ((r_initiator_fsm == M_READ_SUCCESS) || + (r_initiator_fsm == M_WRITE_SUCCESS) || + (r_initiator_fsm == M_READ_ERROR) || + (r_initiator_fsm == M_WRITE_ERROR) ) && + r_irq_enable.read() ) + { + +#if DEBUG_BDEV +std::cout << " " << std::endl; +#endif + p_irq = true; + } + else + { + p_irq = false; + } +} // end GenMoore() + +////////////////////////////////////////////////////////////////////////////// +tmpl(/**/)::VciBlockDeviceTsar( sc_core::sc_module_name name, + const soclib::common::MappingTable &mt, + const soclib::common::IntTab &srcid, + const soclib::common::IntTab &tgtid, + const std::string &filename, + const uint32_t block_size, + const uint32_t burst_size, + const uint32_t latency) + +: caba::BaseModule(name), + m_seglist(mt.getSegmentList(tgtid)), + m_srcid(mt.indexForId(srcid)), + m_words_per_block(block_size/4), + m_words_per_burst(burst_size/4), + m_bursts_per_block(block_size/burst_size), + m_latency(latency), + p_clk("p_clk"), + p_resetn("p_resetn"), + p_vci_initiator("p_vci_initiator"), + p_vci_target("p_vci_target"), + p_irq("p_irq") +{ + std::cout << " - Building VciBlockDeviceTsar " << name << std::endl; + + SC_METHOD(transition); + dont_initialize(); + sensitive << p_clk.pos(); + + SC_METHOD(genMoore); + dont_initialize(); + sensitive << p_clk.neg(); + + size_t nbsegs = 0; + std::list::iterator seg; + for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) + { + nbsegs++; + + if ( (seg->baseAddress() & 0x0000003F) != 0 ) + { + std::cout << "Error in component VciBlockDeviceTsar : " << name + << "The base address of segment " << seg->name() + << " must be multiple of 64 bytes" << std::endl; + exit(1); + } + if ( seg->size() < 64 ) + { + std::cout << "Error in component VciBlockDeviceTsar : " << name + << "The size of segment " << seg->name() + << " cannot be smaller than 64 bytes" << std::endl; + exit(1); + } + std::cout << " => segment " << seg->name() + << " / base = " << std::hex << seg->baseAddress() + << " / size = " << seg->size() << std::endl; + } + + if( nbsegs == 0 ) + { + std::cout << "Error in component VciBlockDeviceTsar : " << name + << " No segment allocated" << std::endl; + exit(1); + } + + if( (block_size != 128) && + (block_size != 256) && + (block_size != 512) && + (block_size != 1024) && + (block_size != 2048) && + (block_size != 4096) ) + { + std::cout << "Error in component VciBlockDeviceTsar : " << name + << " The block size must be 128, 256, 512, 1024, 2048 or 4096 bytes" + << std::endl; + exit(1); + } + + if( (burst_size != 8 ) && + (burst_size != 16) && + (burst_size != 32) && + (burst_size != 64) ) + { + std::cout << "Error in component VciBlockDeviceTsar : " << name + << " The burst size must be 8, 16, 32 or 64 bytes" << std::endl; + exit(1); + } + + if ( (vci_param::B != 4) and (vci_param::B != 8) ) + { + std::cout << "Error in component VciBlockDeviceTsar : " << name + << " The VCI data fields must have 32 bits or 64 bits" << std::endl; + exit(1); + } + + m_fd = ::open(filename.c_str(), O_RDWR); + if ( m_fd < 0 ) + { + std::cout << "Error in component VciBlockDeviceTsar : " << name + << " Unable to open file " << filename << std::endl; + exit(1); + } + m_device_size = lseek(m_fd, 0, SEEK_END) / block_size; + + if ( m_device_size > ((uint64_t)1< +class VciCcVCacheWrapper +//////////////////////////////////////////// + : public soclib::caba::BaseModule +{ + + typedef typename vci_param::fast_addr_t paddr_t; + + enum icache_fsm_state_e + { + ICACHE_IDLE, + // handling XTN processor requests + ICACHE_XTN_TLB_FLUSH, + ICACHE_XTN_CACHE_FLUSH, + ICACHE_XTN_CACHE_FLUSH_GO, + ICACHE_XTN_TLB_INVAL, + ICACHE_XTN_CACHE_INVAL_VA, + ICACHE_XTN_CACHE_INVAL_PA, + ICACHE_XTN_CACHE_INVAL_GO, + // handling tlb miss + ICACHE_TLB_WAIT, + // handling cache miss + ICACHE_MISS_SELECT, + ICACHE_MISS_CLEAN, + ICACHE_MISS_WAIT, + ICACHE_MISS_DATA_UPDT, + ICACHE_MISS_DIR_UPDT, + // handling unc read + ICACHE_UNC_WAIT, + // handling coherence requests + ICACHE_CC_CHECK, + ICACHE_CC_UPDT, + ICACHE_CC_INVAL, + }; + + enum dcache_fsm_state_e + { + DCACHE_IDLE, + // handling itlb & dtlb miss + DCACHE_TLB_MISS, + DCACHE_TLB_PTE1_GET, + DCACHE_TLB_PTE1_SELECT, + DCACHE_TLB_PTE1_UPDT, + DCACHE_TLB_PTE2_GET, + DCACHE_TLB_PTE2_SELECT, + DCACHE_TLB_PTE2_UPDT, + DCACHE_TLB_LR_UPDT, + DCACHE_TLB_LR_WAIT, + DCACHE_TLB_RETURN, + // handling processor XTN requests + DCACHE_XTN_SWITCH, + DCACHE_XTN_SYNC, + DCACHE_XTN_IC_INVAL_VA, + DCACHE_XTN_IC_FLUSH, + DCACHE_XTN_IC_INVAL_PA, + DCACHE_XTN_IC_PADDR_EXT, + DCACHE_XTN_IT_INVAL, + DCACHE_XTN_DC_FLUSH, + DCACHE_XTN_DC_FLUSH_GO, + DCACHE_XTN_DC_INVAL_VA, + DCACHE_XTN_DC_INVAL_PA, + DCACHE_XTN_DC_INVAL_END, + DCACHE_XTN_DC_INVAL_GO, + DCACHE_XTN_DT_INVAL, + //handling dirty bit update + DCACHE_DIRTY_GET_PTE, + DCACHE_DIRTY_WAIT, + // handling processor miss requests + DCACHE_MISS_SELECT, + DCACHE_MISS_CLEAN, + DCACHE_MISS_WAIT, + DCACHE_MISS_DATA_UPDT, + DCACHE_MISS_DIR_UPDT, + // handling processor unc, ll and sc requests + DCACHE_UNC_WAIT, + DCACHE_LL_WAIT, + DCACHE_SC_WAIT, + // handling coherence requests + DCACHE_CC_CHECK, + DCACHE_CC_UPDT, + DCACHE_CC_INVAL, + // handling TLB inval (after a coherence or XTN request) + DCACHE_INVAL_TLB_SCAN, + }; + + enum cmd_fsm_state_e + { + CMD_IDLE, + CMD_INS_MISS, + CMD_INS_UNC, + CMD_DATA_MISS, + CMD_DATA_UNC_READ, + CMD_DATA_UNC_WRITE, + CMD_DATA_WRITE, + CMD_DATA_LL, + CMD_DATA_SC, + CMD_DATA_CAS, + }; + + enum rsp_fsm_state_e + { + RSP_IDLE, + RSP_INS_MISS, + RSP_INS_UNC, + RSP_DATA_MISS, + RSP_DATA_UNC, + RSP_DATA_LL, + RSP_DATA_WRITE, + }; + + enum cc_receive_fsm_state_e + { + CC_RECEIVE_IDLE, + CC_RECEIVE_BRDCAST_HEADER, + CC_RECEIVE_BRDCAST_NLINE, + CC_RECEIVE_INS_INVAL_HEADER, + CC_RECEIVE_INS_INVAL_NLINE, + CC_RECEIVE_INS_UPDT_HEADER, + CC_RECEIVE_INS_UPDT_NLINE, + CC_RECEIVE_DATA_INVAL_HEADER, + CC_RECEIVE_DATA_INVAL_NLINE, + CC_RECEIVE_DATA_UPDT_HEADER, + CC_RECEIVE_DATA_UPDT_NLINE, + CC_RECEIVE_INS_UPDT_DATA, + CC_RECEIVE_DATA_UPDT_DATA, + }; + + enum cc_send_fsm_state_e + { + CC_SEND_IDLE, + CC_SEND_CLEANUP_1, + CC_SEND_CLEANUP_2, + CC_SEND_MULTI_ACK, + }; + + /* transaction type, pktid field */ + enum transaction_type_e + { + // b3 unused + // b2 READ / NOT READ + // if READ + // b1 DATA / INS + // b0 UNC / MISS + // else + // b1 accÚs table llsc type SW / other + // b2 WRITE/CAS/LL/SC + TYPE_DATA_UNC = 0x0, + TYPE_READ_DATA_MISS = 0x1, + TYPE_READ_INS_UNC = 0x2, + TYPE_READ_INS_MISS = 0x3, + TYPE_WRITE = 0x4, + TYPE_CAS = 0x5, + TYPE_LL = 0x6, + TYPE_SC = 0x7 + }; + + /* SC return values */ + enum sc_status_type_e + { + SC_SUCCESS = 0x00000000, + SC_FAIL = 0x00000001 + }; + + // cc_send_type + typedef enum + { + CC_TYPE_CLEANUP, + CC_TYPE_MULTI_ACK, + } cc_send_t; + + // cc_receive_type + typedef enum + { + CC_TYPE_CLACK, + CC_TYPE_BRDCAST, + CC_TYPE_INVAL, + CC_TYPE_UPDT, + } cc_receive_t; + + // TLB Mode : ITLB / DTLB / ICACHE / DCACHE + enum + { + INS_TLB_MASK = 0x8, + DATA_TLB_MASK = 0x4, + INS_CACHE_MASK = 0x2, + DATA_CACHE_MASK = 0x1, + }; + + // Error Type + enum mmu_error_type_e + { + MMU_NONE = 0x0000, // None + MMU_WRITE_PT1_UNMAPPED = 0x0001, // Write & Page fault on PT1 + MMU_WRITE_PT2_UNMAPPED = 0x0002, // Write & Page fault on PT2 + MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write & Protected access in user mode + MMU_WRITE_ACCES_VIOLATION = 0x0008, // Write to non writable page + MMU_WRITE_UNDEFINED_XTN = 0x0020, // Write & undefined external access + MMU_WRITE_PT1_ILLEGAL_ACCESS = 0x0040, // Write & Bus Error accessing PT1 + MMU_WRITE_PT2_ILLEGAL_ACCESS = 0x0080, // Write & Bus Error accessing PT2 + MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write & Bus Error in cache access + MMU_READ_PT1_UNMAPPED = 0x1001, // Read & Page fault on PT1 + MMU_READ_PT2_UNMAPPED = 0x1002, // Read & Page fault on PT2 + MMU_READ_PRIVILEGE_VIOLATION = 0x1004, // Read & Protected access in user mode + MMU_READ_EXEC_VIOLATION = 0x1010, // Read & Exec access to a non exec page + MMU_READ_UNDEFINED_XTN = 0x1020, // Read & Undefined external access + MMU_READ_PT1_ILLEGAL_ACCESS = 0x1040, // Read & Bus Error accessing PT1 + MMU_READ_PT2_ILLEGAL_ACCESS = 0x1080, // Read & Bus Error accessing PT2 + MMU_READ_DATA_ILLEGAL_ACCESS = 0x1100, // Read & Bus Error in cache access + }; + + // miss types for data cache + enum dcache_miss_type_e + { + PTE1_MISS, + PTE2_MISS, + PROC_MISS, + }; + +// enum transaction_type_d_e +// { +// // b0 : 1 if cached +// // b1 : 1 if instruction +// TYPE_DATA_UNC = 0x0, +// TYPE_DATA_MISS = 0x1, +// TYPE_INS_UNC = 0x2, +// TYPE_INS_MISS = 0x3, +// }; + +public: + sc_in p_clk; + sc_in p_resetn; + sc_in p_irq[iss_t::n_irq]; + soclib::caba::VciInitiator p_vci; + soclib::caba::DspinInput p_dspin_m2p; + soclib::caba::DspinOutput p_dspin_p2m; + soclib::caba::DspinInput p_dspin_clack; + +private: + + // STRUCTURAL PARAMETERS + soclib::common::AddressDecodingTable m_cacheability_table; + + const size_t m_srcid; + const size_t m_cc_global_id; + const size_t m_nline_width; + const size_t m_itlb_ways; + const size_t m_itlb_sets; + const size_t m_dtlb_ways; + const size_t m_dtlb_sets; + const size_t m_icache_ways; + const size_t m_icache_sets; + const paddr_t m_icache_yzmask; + const size_t m_icache_words; + const size_t m_dcache_ways; + const size_t m_dcache_sets; + const paddr_t m_dcache_yzmask; + const size_t m_dcache_words; + const size_t m_x_width; + const size_t m_y_width; + const size_t m_proc_id; + const uint32_t m_max_frozen_cycles; + const size_t m_paddr_nbits; + uint32_t m_debug_start_cycle; + bool m_debug_ok; + + uint32_t m_dcache_paddr_ext_reset; + uint32_t m_icache_paddr_ext_reset; + + //////////////////////////////////////// + // Communication with processor ISS + //////////////////////////////////////// + typename iss_t::InstructionRequest m_ireq; + typename iss_t::InstructionResponse m_irsp; + typename iss_t::DataRequest m_dreq; + typename iss_t::DataResponse m_drsp; + + ///////////////////////////////////////////// + // debug variables + ///////////////////////////////////////////// + bool m_debug_previous_i_hit; + bool m_debug_previous_d_hit; + bool m_debug_icache_fsm; + bool m_debug_dcache_fsm; + bool m_debug_cmd_fsm; + + /////////////////////////////// + // Software visible REGISTERS + /////////////////////////////// + sc_signal r_mmu_ptpr; // page table pointer register + sc_signal r_mmu_mode; // mmu mode register + sc_signal r_mmu_word_lo; // mmu misc data low + sc_signal r_mmu_word_hi; // mmu misc data hight + sc_signal r_mmu_ibvar; // mmu bad instruction address + sc_signal r_mmu_dbvar; // mmu bad data address + sc_signal r_mmu_ietr; // mmu instruction error type + sc_signal r_mmu_detr; // mmu data error type + uint32_t r_mmu_params; // read-only + uint32_t r_mmu_release; // read_only + + + ////////////////////////////// + // ICACHE FSM REGISTERS + ////////////////////////////// + sc_signal r_icache_fsm; // state register + sc_signal r_icache_fsm_save; // return state for coherence op + sc_signal r_icache_vci_paddr; // physical address + sc_signal r_icache_vaddr_save; // virtual address from processor + + // icache miss handling + sc_signal r_icache_miss_way; // selected way for cache update + sc_signal r_icache_miss_set; // selected set for cache update + sc_signal r_icache_miss_word; // word index ( cache update) + sc_signal r_icache_miss_inval; // coherence request matching a miss + sc_signal r_icache_miss_clack; // waiting for a cleanup acknowledge + + // coherence request handling + sc_signal r_icache_cc_way; // selected way for cc update/inval + sc_signal r_icache_cc_set; // selected set for cc update/inval + sc_signal r_icache_cc_word; // word counter for cc update + sc_signal r_icache_cc_need_write; // activate the cache for writing + + // coherence clack handling + sc_signal r_icache_clack_req; // clack request + sc_signal r_icache_clack_way; // clack way + sc_signal r_icache_clack_set; // clack set + + // icache flush handling + sc_signal r_icache_flush_count; // slot counter used for cache flush + + // communication between ICACHE FSM and VCI_CMD FSM + sc_signal r_icache_miss_req; // cached read miss + sc_signal r_icache_unc_req; // uncached read miss + + // communication between ICACHE FSM and DCACHE FSM + sc_signal r_icache_tlb_miss_req; // (set icache/reset dcache) + sc_signal r_icache_tlb_rsp_error; // tlb miss response error + + // Filp-Flop in ICACHE FSM for saving the cleanup victim request + sc_signal r_icache_cleanup_victim_req; + sc_signal r_icache_cleanup_victim_nline; + + // communication between ICACHE FSM and CC_SEND FSM + sc_signal r_icache_cc_send_req; // ICACHE cc_send request + sc_signal r_icache_cc_send_type; // ICACHE cc_send request type + sc_signal r_icache_cc_send_nline; // ICACHE cc_send nline + sc_signal r_icache_cc_send_way; // ICACHE cc_send way + sc_signal r_icache_cc_send_updt_tab_idx; // ICACHE cc_send update table index + + // Physical address extension for data access + sc_signal r_icache_paddr_ext; // CP2 register (if vci_address > 32) + + /////////////////////////////// + // DCACHE FSM REGISTERS + /////////////////////////////// + sc_signal r_dcache_fsm; // state register + sc_signal r_dcache_fsm_cc_save; // return state for coherence op + sc_signal r_dcache_fsm_scan_save; // return state for tlb scan op + // registers written in P0 stage (used in P1 stage) + sc_signal r_dcache_wbuf_req; // WBUF must be written in P1 stage + sc_signal r_dcache_updt_req; // DCACHE must be updated in P1 stage + sc_signal r_dcache_save_vaddr; // virtual address (from proc) + sc_signal r_dcache_save_wdata; // write data (from proc) + sc_signal r_dcache_save_be; // byte enable (from proc) + sc_signal r_dcache_save_paddr; // physical address + sc_signal r_dcache_save_cache_way; // selected way (from dcache) + sc_signal r_dcache_save_cache_set; // selected set (from dcache) + sc_signal r_dcache_save_cache_word; // selected word (from dcache) + // registers used by the Dirty bit sub-fsm + sc_signal r_dcache_dirty_paddr; // PTE physical address + sc_signal r_dcache_dirty_way; // way to invalidate in dcache + sc_signal r_dcache_dirty_set; // set to invalidate in dcache + + // communication between DCACHE FSM and VCI_CMD FSM + sc_signal r_dcache_vci_paddr; // physical address for VCI command + sc_signal r_dcache_vci_wdata; // write unc data for VCI command + sc_signal r_dcache_vci_miss_req; // read miss request + sc_signal r_dcache_vci_unc_req; // uncacheable request (read/write) + sc_signal r_dcache_vci_unc_be; // uncacheable byte enable + sc_signal r_dcache_vci_unc_write; // uncacheable data write request + sc_signal r_dcache_vci_cas_req; // atomic write request CAS + sc_signal r_dcache_vci_cas_old; // previous data value for a CAS + sc_signal r_dcache_vci_cas_new; // new data value for a CAS + sc_signal r_dcache_vci_ll_req; // atomic read request LL + sc_signal r_dcache_vci_sc_req; // atomic write request SC + sc_signal r_dcache_vci_sc_data; // SC data (command) + + // register used for XTN inval + sc_signal r_dcache_xtn_way; // selected way (from dcache) + sc_signal r_dcache_xtn_set; // selected set (from dcache) + + // handling dcache miss + sc_signal r_dcache_miss_type; // depending on the requester + sc_signal r_dcache_miss_word; // word index for cache update + sc_signal r_dcache_miss_way; // selected way for cache update + sc_signal r_dcache_miss_set; // selected set for cache update + sc_signal r_dcache_miss_inval; // coherence request matching a miss + sc_signal r_dcache_miss_clack; // waiting for a cleanup acknowledge + + // handling coherence requests + sc_signal r_dcache_cc_way; // selected way for cc update/inval + sc_signal r_dcache_cc_set; // selected set for cc update/inval + sc_signal r_dcache_cc_word; // word counter for cc update + sc_signal r_dcache_cc_need_write; // activate the cache for writing + + // coherence clack handling + sc_signal r_dcache_clack_req; // clack request + sc_signal r_dcache_clack_way; // clack way + sc_signal r_dcache_clack_set; // clack set + + // dcache flush handling + sc_signal r_dcache_flush_count; // slot counter used for cache flush + + // ll response handling + sc_signal r_dcache_ll_rsp_count; // flit counter used for ll rsp + + // used by the TLB miss sub-fsm + sc_signal r_dcache_tlb_vaddr; // virtual address for a tlb miss + sc_signal r_dcache_tlb_ins; // target tlb (itlb if true) + sc_signal r_dcache_tlb_paddr; // physical address of pte + sc_signal r_dcache_tlb_pte_flags; // pte1 or first word of pte2 + sc_signal r_dcache_tlb_pte_ppn; // second word of pte2 + sc_signal r_dcache_tlb_cache_way; // selected way in dcache + sc_signal r_dcache_tlb_cache_set; // selected set in dcache + sc_signal r_dcache_tlb_cache_word; // selected word in dcache + sc_signal r_dcache_tlb_way; // selected way in tlb + sc_signal r_dcache_tlb_set; // selected set in tlb + + // ITLB and DTLB invalidation + sc_signal r_dcache_tlb_inval_line; // line index + sc_signal r_dcache_tlb_inval_set; // tlb set counter + + // communication between DCACHE FSM and ICACHE FSM + sc_signal r_dcache_xtn_req; // xtn request (caused by processor) + sc_signal r_dcache_xtn_opcode; // xtn request type + + // Filp-Flop in DCACHE FSM for saving the cleanup victim request + sc_signal r_dcache_cleanup_victim_req; + sc_signal r_dcache_cleanup_victim_nline; + + // communication between DCACHE FSM and CC_SEND FSM + sc_signal r_dcache_cc_send_req; // DCACHE cc_send request + sc_signal r_dcache_cc_send_type; // DCACHE cc_send request type + sc_signal r_dcache_cc_send_nline; // DCACHE cc_send nline + sc_signal r_dcache_cc_send_way; // DCACHE cc_send way + sc_signal r_dcache_cc_send_updt_tab_idx; // DCACHE cc_send update table index + + // dcache directory extension + bool *r_dcache_in_tlb; // copy exist in dtlb or itlb + bool *r_dcache_contains_ptd; // cache line contains a PTD + + // Physical address extension for data access + sc_signal r_dcache_paddr_ext; // CP2 register (if vci_address > 32) + + /////////////////////////////////// + // VCI_CMD FSM REGISTERS + /////////////////////////////////// + sc_signal r_vci_cmd_fsm; + sc_signal r_vci_cmd_min; // used for write bursts + sc_signal r_vci_cmd_max; // used for write bursts + sc_signal r_vci_cmd_cpt; // used for write bursts + sc_signal r_vci_cmd_imiss_prio; // round-robin between imiss & dmiss + + /////////////////////////////////// + // VCI_RSP FSM REGISTERS + /////////////////////////////////// + sc_signal r_vci_rsp_fsm; + sc_signal r_vci_rsp_cpt; + sc_signal r_vci_rsp_ins_error; + sc_signal r_vci_rsp_data_error; + GenericFifo r_vci_rsp_fifo_icache; // response FIFO to ICACHE FSM + GenericFifo r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM + + /////////////////////////////////// + // CC_SEND FSM REGISTER + /////////////////////////////////// + sc_signal r_cc_send_fsm; // state register + sc_signal r_cc_send_last_client; // 0 dcache / 1 icache + + /////////////////////////////////// + // CC_RECEIVE FSM REGISTER + /////////////////////////////////// + sc_signal r_cc_receive_fsm; // state register + sc_signal r_cc_receive_data_ins; // request to : 0 dcache / 1 icache + + // communication between CC_RECEIVE FSM and ICACHE/DCACHE FSM + sc_signal r_cc_receive_word_idx; // word index + GenericFifo r_cc_receive_updt_fifo_be; + GenericFifo r_cc_receive_updt_fifo_data; + GenericFifo r_cc_receive_updt_fifo_eop; + + // communication between CC_RECEIVE FSM and ICACHE FSM + sc_signal r_cc_receive_icache_req; // cc_receive to icache request + sc_signal r_cc_receive_icache_type; // cc_receive type of request + sc_signal r_cc_receive_icache_way; // cc_receive to icache way + sc_signal r_cc_receive_icache_set; // cc_receive to icache set + sc_signal r_cc_receive_icache_updt_tab_idx; // cc_receive update table index + sc_signal r_cc_receive_icache_nline; // cache line physical address + + // communication between CC_RECEIVE FSM and DCACHE FSM + sc_signal r_cc_receive_dcache_req; // cc_receive to dcache request + sc_signal r_cc_receive_dcache_type; // cc_receive type of request + sc_signal r_cc_receive_dcache_way; // cc_receive to dcache way + sc_signal r_cc_receive_dcache_set; // cc_receive to dcache set + sc_signal r_cc_receive_dcache_updt_tab_idx; // cc_receive update table index + sc_signal r_cc_receive_dcache_nline; // cache line physical address + + /////////////////////////////////// + // DSPIN CLACK INTERFACE REGISTER + /////////////////////////////////// + sc_signal r_dspin_clack_req; + sc_signal r_dspin_clack_flit; + + ////////////////////////////////////////////////////////////////// + // processor, write buffer, caches , TLBs + ////////////////////////////////////////////////////////////////// + + iss_t r_iss; + MultiWriteBuffer r_wbuf; + GenericCache r_icache; + GenericCache r_dcache; + GenericTlb r_itlb; + GenericTlb r_dtlb; + + ////////////////////////////////////////////////////////////////// + // llsc registration buffer + ////////////////////////////////////////////////////////////////// + + sc_signal r_dcache_llsc_paddr; + sc_signal r_dcache_llsc_key; + sc_signal r_dcache_llsc_count; + sc_signal r_dcache_llsc_valid; + + //////////////////////////////// + // Activity counters + //////////////////////////////// + uint32_t m_cpt_dcache_data_read; // DCACHE DATA READ + uint32_t m_cpt_dcache_data_write; // DCACHE DATA WRITE + uint32_t m_cpt_dcache_dir_read; // DCACHE DIR READ + uint32_t m_cpt_dcache_dir_write; // DCACHE DIR WRITE + + uint32_t m_cpt_icache_data_read; // ICACHE DATA READ + uint32_t m_cpt_icache_data_write; // ICACHE DATA WRITE + uint32_t m_cpt_icache_dir_read; // ICACHE DIR READ + uint32_t m_cpt_icache_dir_write; // ICACHE DIR WRITE + + uint32_t m_cpt_frz_cycles; // number of cycles where the cpu is frozen + uint32_t m_cpt_total_cycles; // total number of cycles + + // Cache activity counters + uint32_t m_cpt_data_read; // total number of read data + uint32_t m_cpt_data_write; // total number of write data + uint32_t m_cpt_data_miss; // number of read miss + uint32_t m_cpt_ins_miss; // number of instruction miss + uint32_t m_cpt_unc_read; // number of read uncached + uint32_t m_cpt_write_cached; // number of cached write + uint32_t m_cpt_ins_read; // number of instruction read + uint32_t m_cpt_ins_spc_miss; // number of speculative instruction miss + + uint32_t m_cost_write_frz; // number of frozen cycles related to write buffer + uint32_t m_cost_data_miss_frz; // number of frozen cycles related to data miss + uint32_t m_cost_unc_read_frz; // number of frozen cycles related to uncached read + uint32_t m_cost_ins_miss_frz; // number of frozen cycles related to ins miss + + uint32_t m_cpt_imiss_transaction; // number of VCI instruction miss transactions + uint32_t m_cpt_dmiss_transaction; // number of VCI data miss transactions + uint32_t m_cpt_unc_transaction; // number of VCI uncached read transactions + uint32_t m_cpt_write_transaction; // number of VCI write transactions + uint32_t m_cpt_icache_unc_transaction; + + uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions + uint32_t m_cost_dmiss_transaction; // cumulated duration for VCI DMISS transactions + uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions + uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions + uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions + uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions + + // TLB activity counters + uint32_t m_cpt_ins_tlb_read; // number of instruction tlb read + uint32_t m_cpt_ins_tlb_miss; // number of instruction tlb miss + uint32_t m_cpt_ins_tlb_update_acc; // number of instruction tlb update + uint32_t m_cpt_ins_tlb_occup_cache; // number of instruction tlb occupy data cache line + uint32_t m_cpt_ins_tlb_hit_dcache; // number of instruction tlb hit in data cache + + uint32_t m_cpt_data_tlb_read; // number of data tlb read + uint32_t m_cpt_data_tlb_miss; // number of data tlb miss + uint32_t m_cpt_data_tlb_update_acc; // number of data tlb update + uint32_t m_cpt_data_tlb_update_dirty; // number of data tlb update dirty + uint32_t m_cpt_data_tlb_hit_dcache; // number of data tlb hit in data cache + uint32_t m_cpt_data_tlb_occup_cache; // number of data tlb occupy data cache line + uint32_t m_cpt_tlb_occup_dcache; + + uint32_t m_cost_ins_tlb_miss_frz; // number of frozen cycles related to instruction tlb miss + uint32_t m_cost_data_tlb_miss_frz; // number of frozen cycles related to data tlb miss + uint32_t m_cost_ins_tlb_update_acc_frz; // number of frozen cycles related to instruction tlb update acc + uint32_t m_cost_data_tlb_update_acc_frz; // number of frozen cycles related to data tlb update acc + uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty + uint32_t m_cost_ins_tlb_occup_cache_frz; // number of frozen cycles related to instruction tlb miss operate in dcache + uint32_t m_cost_data_tlb_occup_cache_frz; // number of frozen cycles related to data tlb miss operate in dcache + + uint32_t m_cpt_itlbmiss_transaction; // number of itlb miss transactions + uint32_t m_cpt_itlb_ll_transaction; // number of itlb ll acc transactions + uint32_t m_cpt_itlb_sc_transaction; // number of itlb sc acc transactions + uint32_t m_cpt_dtlbmiss_transaction; // number of dtlb miss transactions + uint32_t m_cpt_dtlb_ll_transaction; // number of dtlb ll acc transactions + uint32_t m_cpt_dtlb_sc_transaction; // number of dtlb sc acc transactions + uint32_t m_cpt_dtlb_ll_dirty_transaction; // number of dtlb ll dirty transactions + uint32_t m_cpt_dtlb_sc_dirty_transaction; // number of dtlb sc dirty transactions + + uint32_t m_cost_itlbmiss_transaction; // cumulated duration for VCI instruction TLB miss transactions + uint32_t m_cost_itlb_ll_transaction; // cumulated duration for VCI instruction TLB ll acc transactions + uint32_t m_cost_itlb_sc_transaction; // cumulated duration for VCI instruction TLB sc acc transactions + uint32_t m_cost_dtlbmiss_transaction; // cumulated duration for VCI data TLB miss transactions + uint32_t m_cost_dtlb_ll_transaction; // cumulated duration for VCI data TLB ll acc transactions + uint32_t m_cost_dtlb_sc_transaction; // cumulated duration for VCI data TLB sc acc transactions + uint32_t m_cost_dtlb_ll_dirty_transaction; // cumulated duration for VCI data TLB ll dirty transactions + uint32_t m_cost_dtlb_sc_dirty_transaction; // cumulated duration for VCI data TLB sc dirty transactions + + // coherence activity counters + uint32_t m_cpt_cc_update_icache; // number of coherence update instruction commands + uint32_t m_cpt_cc_update_dcache; // number of coherence update data commands + uint32_t m_cpt_cc_inval_icache; // number of coherence inval instruction commands + uint32_t m_cpt_cc_inval_dcache; // number of coherence inval data commands + uint32_t m_cpt_cc_broadcast; // number of coherence broadcast commands + + uint32_t m_cost_updt_data_frz; // number of frozen cycles related to coherence update data packets + uint32_t m_cost_inval_ins_frz; // number of frozen cycles related to coherence inval instruction packets + uint32_t m_cost_inval_data_frz; // number of frozen cycles related to coherence inval data packets + uint32_t m_cost_broadcast_frz; // number of frozen cycles related to coherence broadcast packets + + uint32_t m_cpt_cc_cleanup_ins; // number of coherence cleanup packets + uint32_t m_cpt_cc_cleanup_data; // number of coherence cleanup packets + + uint32_t m_cpt_icleanup_transaction; // number of instruction cleanup transactions + uint32_t m_cpt_dcleanup_transaction; // number of instructinumber of data cleanup transactions + uint32_t m_cost_icleanup_transaction; // cumulated duration for VCI instruction cleanup transactions + uint32_t m_cost_dcleanup_transaction; // cumulated duration for VCI data cleanup transactions + + uint32_t m_cost_ins_tlb_inval_frz; // number of frozen cycles related to checking ins tlb invalidate + uint32_t m_cpt_ins_tlb_inval; // number of ins tlb invalidate + + uint32_t m_cost_data_tlb_inval_frz; // number of frozen cycles related to checking data tlb invalidate + uint32_t m_cpt_data_tlb_inval; // number of data tlb invalidate + + // FSM activity counters + uint32_t m_cpt_fsm_icache [64]; + uint32_t m_cpt_fsm_dcache [64]; + uint32_t m_cpt_fsm_cmd [64]; + uint32_t m_cpt_fsm_rsp [64]; + uint32_t m_cpt_fsm_cc_receive [64]; + uint32_t m_cpt_fsm_cc_send [64]; + + uint32_t m_cpt_stop_simulation; // used to stop simulation if frozen + bool m_monitor_ok; // used to debug cache output + uint32_t m_monitor_base; + uint32_t m_monitor_length; + +protected: + SC_HAS_PROCESS(VciCcVCacheWrapper); + +public: + VciCcVCacheWrapper( + sc_module_name name, + const int proc_id, + const soclib::common::MappingTable &mtd, + const soclib::common::IntTab &srcid, + const size_t cc_global_id, + const size_t itlb_ways, + const size_t itlb_sets, + const size_t dtlb_ways, + const size_t dtlb_sets, + const size_t icache_ways, + const size_t icache_sets, + const size_t icache_words, + const size_t dcache_ways, + const size_t dcache_sets, + const size_t dcache_words, + const size_t wbuf_nlines, + const size_t wbuf_nwords, + const size_t x_width, + const size_t y_width, + const uint32_t max_frozen_cycles, + const uint32_t debug_start_cycle, + const bool debug_ok ); + + ~VciCcVCacheWrapper(); + + void print_cpi(); + void print_stats(); + void clear_stats(); + void print_trace(size_t mode = 0); + void cache_monitor(paddr_t addr); + void start_monitor(paddr_t,paddr_t); + void stop_monitor(); + inline void iss_set_debug_mask(uint v) + { + r_iss.set_debug_mask(v); + } + + ///////////////////////////////////////////////////////////// + // Set the m_dcache_paddr_ext_reset attribute + // + // The r_dcache_paddr_ext register will be initialized after + // reset with the m_dcache_paddr_ext_reset value + ///////////////////////////////////////////////////////////// + inline void set_dcache_paddr_ext_reset(uint32_t v) + { + m_dcache_paddr_ext_reset = v; + } + + ///////////////////////////////////////////////////////////// + // Set the m_icache_paddr_ext_reset attribute + // + // The r_icache_paddr_ext register will be initialized after + // reset with the m_icache_paddr_ext_reset value + ///////////////////////////////////////////////////////////// + inline void set_icache_paddr_ext_reset(uint32_t v) + { + m_icache_paddr_ext_reset = v; + } + +private: + void transition(); + void genMoore(); + + soclib_static_assert((int)iss_t::SC_ATOMIC == (int)vci_param::STORE_COND_ATOMIC); + soclib_static_assert((int)iss_t::SC_NOT_ATOMIC == (int)vci_param::STORE_COND_NOT_ATOMIC); +}; + +}} + +#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_H */ + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 Index: /branches/fault_tolerance/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp =================================================================== --- /branches/fault_tolerance/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 724) +++ /branches/fault_tolerance/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 724) @@ -0,0 +1,6422 @@ +/* -*- c++ -*- + * File : vci_cc_vcache_wrapper.cpp + * Copyright (c) UPMC, Lip6, SoC + * Authors : Alain GREINER, Yang GAO + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Maintainers: cesar.fuguet-tortolero@lip6.fr + * alexandre.joannou@lip6.fr + */ + +#include +#include "arithmetics.h" +#include "../include/vci_cc_vcache_wrapper.h" + +#define DEBUG_DCACHE 1 +#define DEBUG_ICACHE 1 +#define DEBUG_CMD 0 + +namespace soclib { +namespace caba { + +namespace { +const char *icache_fsm_state_str[] = { + "ICACHE_IDLE", + + "ICACHE_XTN_TLB_FLUSH", + "ICACHE_XTN_CACHE_FLUSH", + "ICACHE_XTN_CACHE_FLUSH_GO", + "ICACHE_XTN_TLB_INVAL", + "ICACHE_XTN_CACHE_INVAL_VA", + "ICACHE_XTN_CACHE_INVAL_PA", + "ICACHE_XTN_CACHE_INVAL_GO", + + "ICACHE_TLB_WAIT", + + "ICACHE_MISS_SELECT", + "ICACHE_MISS_CLEAN", + "ICACHE_MISS_WAIT", + "ICACHE_MISS_DATA_UPDT", + "ICACHE_MISS_DIR_UPDT", + + "ICACHE_UNC_WAIT", + + "ICACHE_CC_CHECK", + "ICACHE_CC_UPDT", + "ICACHE_CC_INVAL", + }; + +const char *dcache_fsm_state_str[] = { + "DCACHE_IDLE", + + "DCACHE_TLB_MISS", + "DCACHE_TLB_PTE1_GET", + "DCACHE_TLB_PTE1_SELECT", + "DCACHE_TLB_PTE1_UPDT", + "DCACHE_TLB_PTE2_GET", + "DCACHE_TLB_PTE2_SELECT", + "DCACHE_TLB_PTE2_UPDT", + "DCACHE_TLB_LR_UPDT", + "DCACHE_TLB_LR_WAIT", + "DCACHE_TLB_RETURN", + + "DCACHE_XTN_SWITCH", + "DCACHE_XTN_SYNC", + "DCACHE_XTN_IC_INVAL_VA", + "DCACHE_XTN_IC_FLUSH", + "DCACHE_XTN_IC_INVAL_PA", + "DCACHE_XTN_IC_PADDR_EXT", + "DCACHE_XTN_IT_INVAL", + "DCACHE_XTN_DC_FLUSH", + "DCACHE_XTN_DC_FLUSH_GO", + "DCACHE_XTN_DC_INVAL_VA", + "DCACHE_XTN_DC_INVAL_PA", + "DCACHE_XTN_DC_INVAL_END", + "DCACHE_XTN_DC_INVAL_GO", + "DCACHE_XTN_DT_INVAL", + + "DCACHE_DIRTY_GET_PTE", + "DCACHE_DIRTY_WAIT", + + "DCACHE_MISS_SELECT", + "DCACHE_MISS_CLEAN", + "DCACHE_MISS_WAIT", + "DCACHE_MISS_DATA_UPDT", + "DCACHE_MISS_DIR_UPDT", + + "DCACHE_UNC_WAIT", + "DCACHE_LL_WAIT", + "DCACHE_SC_WAIT", + + "DCACHE_CC_CHECK", + "DCACHE_CC_UPDT", + "DCACHE_CC_INVAL", + + "DCACHE_INVAL_TLB_SCAN", + }; + +const char *cmd_fsm_state_str[] = { + "CMD_IDLE", + "CMD_INS_MISS", + "CMD_INS_UNC", + "CMD_DATA_MISS", + "CMD_DATA_UNC_READ", + "CMD_DATA_UNC_WRITE", + "CMD_DATA_WRITE", + "CMD_DATA_LL", + "CMD_DATA_SC", + "CMD_DATA_CAS", + }; + +const char *vci_pktid_type_str[] = { + "TYPE_DATA_UNC", + "TYPE_READ_DATA_MISS", + "TYPE_READ_INS_UNC", + "TYPE_READ_INS_MISS", + "TYPE_WRITE", + "TYPE_CAS", + "TYPE_LL", + "TYPE_SC", + }; + +const char *vci_cmd_type_str[] = { + "NOP or STORE_COND", + "READ", + "WRITE", + "LOCKED_READ" + }; + +const char *rsp_fsm_state_str[] = { + "RSP_IDLE", + "RSP_INS_MISS", + "RSP_INS_UNC", + "RSP_DATA_MISS", + "RSP_DATA_UNC", + "RSP_DATA_LL", + "RSP_DATA_WRITE", + }; + +const char *cc_receive_fsm_state_str[] = { + "CC_RECEIVE_IDLE", + "CC_RECEIVE_BRDCAST_HEADER", + "CC_RECEIVE_BRDCAST_NLINE", + "CC_RECEIVE_INS_INVAL_HEADER", + "CC_RECEIVE_INS_INVAL_NLINE", + "CC_RECEIVE_INS_UPDT_HEADER", + "CC_RECEIVE_INS_UPDT_NLINE", + "CC_RECEIVE_INS_UPDT_DATA", + "CC_RECEIVE_DATA_INVAL_HEADER", + "CC_RECEIVE_DATA_INVAL_NLINE", + "CC_RECEIVE_DATA_UPDT_HEADER", + "CC_RECEIVE_DATA_UPDT_NLINE", + "CC_RECEIVE_DATA_UPDT_DATA", + }; + +const char *cc_send_fsm_state_str[] = { + "CC_SEND_IDLE", + "CC_SEND_CLEANUP_1", + "CC_SEND_CLEANUP_2", + "CC_SEND_MULTI_ACK", + }; +} + +#define tmpl(...) \ + template __VA_ARGS__ \ + VciCcVCacheWrapper + +using namespace soclib::common; + +///////////////////////////////// +tmpl(/**/)::VciCcVCacheWrapper( + sc_module_name name, + const int proc_id, + const MappingTable &mtd, + const IntTab &srcid, + const size_t cc_global_id, + const size_t itlb_ways, + const size_t itlb_sets, + const size_t dtlb_ways, + const size_t dtlb_sets, + const size_t icache_ways, + const size_t icache_sets, + const size_t icache_words, + const size_t dcache_ways, + const size_t dcache_sets, + const size_t dcache_words, + const size_t wbuf_nlines, + const size_t wbuf_nwords, + const size_t x_width, + const size_t y_width, + const uint32_t max_frozen_cycles, + const uint32_t debug_start_cycle, + const bool debug_ok ) + : soclib::caba::BaseModule(name), + + p_clk("p_clk"), + p_resetn("p_resetn"), + p_vci("p_vci"), + p_dspin_m2p("p_dspin_m2p"), + p_dspin_p2m("p_dspin_p2m"), + p_dspin_clack("p_dspin_clack"), + + m_cacheability_table( mtd.getCacheabilityTable() ), + m_srcid( mtd.indexForId(srcid) ), + m_cc_global_id( cc_global_id ), + m_nline_width( vci_param::N - (uint32_log2(dcache_words)) - 2 ), + m_itlb_ways( itlb_ways ), + m_itlb_sets( itlb_sets ), + m_dtlb_ways( dtlb_ways ), + m_dtlb_sets( dtlb_sets ), + m_icache_ways( icache_ways ), + m_icache_sets( icache_sets ), + m_icache_yzmask( (~0)<<(uint32_log2(icache_words) + 2) ), + m_icache_words( icache_words ), + m_dcache_ways( dcache_ways ), + m_dcache_sets( dcache_sets ), + m_dcache_yzmask( (~0)<<(uint32_log2(dcache_words) + 2) ), + m_dcache_words( dcache_words ), + m_x_width( x_width ), + m_y_width( y_width ), + m_proc_id( proc_id ), + m_max_frozen_cycles( max_frozen_cycles ), + m_paddr_nbits( vci_param::N ), + m_debug_start_cycle( debug_start_cycle ), + m_debug_ok( debug_ok ), + m_dcache_paddr_ext_reset(0), + m_icache_paddr_ext_reset(0), + + r_mmu_ptpr("r_mmu_ptpr"), + r_mmu_mode("r_mmu_mode"), + r_mmu_word_lo("r_mmu_word_lo"), + r_mmu_word_hi("r_mmu_word_hi"), + r_mmu_ibvar("r_mmu_ibvar"), + r_mmu_dbvar("r_mmu_dbvar"), + r_mmu_ietr("r_mmu_ietr"), + r_mmu_detr("r_mmu_detr"), + + r_icache_fsm("r_icache_fsm"), + r_icache_fsm_save("r_icache_fsm_save"), + r_icache_vci_paddr("r_icache_vci_paddr"), + r_icache_vaddr_save("r_icache_vaddr_save"), + + r_icache_miss_way("r_icache_miss_way"), + r_icache_miss_set("r_icache_miss_set"), + r_icache_miss_word("r_icache_miss_word"), + r_icache_miss_inval("r_icache_miss_inval"), + r_icache_miss_clack("r_icache_miss_clack"), + + r_icache_cc_way("r_icache_cc_way"), + r_icache_cc_set("r_icache_cc_set"), + r_icache_cc_word("r_icache_cc_word"), + r_icache_cc_need_write("r_icache_cc_need_write"), + + r_icache_flush_count("r_icache_flush_count"), + + r_icache_miss_req("r_icache_miss_req"), + r_icache_unc_req("r_icache_unc_req"), + + r_icache_tlb_miss_req("r_icache_tlb_read_req"), + r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"), + + r_icache_cleanup_victim_req("r_icache_cleanup_victim_req"), + r_icache_cleanup_victim_nline("r_icache_cleanup_victim_nline"), + + r_icache_cc_send_req("r_icache_cc_send_req"), + r_icache_cc_send_type("r_icache_cc_send_type"), + r_icache_cc_send_nline("r_icache_cc_send_nline"), + r_icache_cc_send_way("r_icache_cc_send_way"), + r_icache_cc_send_updt_tab_idx("r_icache_cc_send_updt_tab_idx"), + + r_dcache_fsm("r_dcache_fsm"), + r_dcache_fsm_cc_save("r_dcache_fsm_cc_save"), + r_dcache_fsm_scan_save("r_dcache_fsm_scan_save"), + + r_dcache_wbuf_req("r_dcache_wbuf_req"), + r_dcache_updt_req("r_dcache_updt_req"), + r_dcache_save_vaddr("r_dcache_save_vaddr"), + r_dcache_save_wdata("r_dcache_save_wdata"), + r_dcache_save_be("r_dcache_save_be"), + r_dcache_save_paddr("r_dcache_save_paddr"), + r_dcache_save_cache_way("r_dcache_save_cache_way"), + r_dcache_save_cache_set("r_dcache_save_cache_set"), + r_dcache_save_cache_word("r_dcache_save_cache_word"), + + r_dcache_dirty_paddr("r_dcache_dirty_paddr"), + r_dcache_dirty_way("r_dcache_dirty_way"), + r_dcache_dirty_set("r_dcache_dirty_set"), + + r_dcache_vci_paddr("r_dcache_vci_paddr"), + r_dcache_vci_wdata("r_dcache_vci_wdata"), + r_dcache_vci_miss_req("r_dcache_vci_miss_req"), + r_dcache_vci_unc_req("r_dcache_vci_unc_req"), + r_dcache_vci_unc_be("r_dcache_vci_unc_be"), + r_dcache_vci_unc_write("r_dcache_vci_unc_write"), + r_dcache_vci_cas_req("r_dcache_vci_cas_req"), + r_dcache_vci_cas_old("r_dcache_vci_cas_old"), + r_dcache_vci_cas_new("r_dcache_vci_cas_new"), + r_dcache_vci_ll_req("r_dcache_vci_ll_req"), + r_dcache_vci_sc_req("r_dcache_vci_sc_req"), + r_dcache_vci_sc_data("r_dcache_vci_sc_data"), + + r_dcache_xtn_way("r_dcache_xtn_way"), + r_dcache_xtn_set("r_dcache_xtn_set"), + + r_dcache_miss_type("r_dcache_miss_type"), + r_dcache_miss_word("r_dcache_miss_word"), + r_dcache_miss_way("r_dcache_miss_way"), + r_dcache_miss_set("r_dcache_miss_set"), + r_dcache_miss_inval("r_dcache_miss_inval"), + + r_dcache_cc_way("r_dcache_cc_way"), + r_dcache_cc_set("r_dcache_cc_set"), + r_dcache_cc_word("r_dcache_cc_word"), + r_dcache_cc_need_write("r_dcache_cc_need_write"), + + r_dcache_flush_count("r_dcache_flush_count"), + + r_dcache_ll_rsp_count("r_dcache_ll_rsp_count"), + + r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"), + r_dcache_tlb_ins("r_dcache_tlb_ins"), + r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"), + r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"), + r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"), + r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"), + r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"), + r_dcache_tlb_way("r_dcache_tlb_way"), + r_dcache_tlb_set("r_dcache_tlb_set"), + + r_dcache_tlb_inval_line("r_dcache_tlb_inval_line"), + r_dcache_tlb_inval_set("r_dcache_tlb_inval_set"), + + r_dcache_xtn_req("r_dcache_xtn_req"), + r_dcache_xtn_opcode("r_dcache_xtn_opcode"), + + r_dcache_cleanup_victim_req("r_dcache_cleanup_victim_req"), + r_dcache_cleanup_victim_nline("r_dcache_cleanup_victim_nline"), + + r_dcache_cc_send_req("r_dcache_cc_send_req"), + r_dcache_cc_send_type("r_dcache_cc_send_type"), + r_dcache_cc_send_nline("r_dcache_cc_send_nline"), + r_dcache_cc_send_way("r_dcache_cc_send_way"), + r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"), + + r_vci_cmd_fsm("r_vci_cmd_fsm"), + r_vci_cmd_min("r_vci_cmd_min"), + r_vci_cmd_max("r_vci_cmd_max"), + r_vci_cmd_cpt("r_vci_cmd_cpt"), + r_vci_cmd_imiss_prio("r_vci_cmd_imiss_prio"), + + r_vci_rsp_fsm("r_vci_rsp_fsm"), + r_vci_rsp_cpt("r_vci_rsp_cpt"), + r_vci_rsp_ins_error("r_vci_rsp_ins_error"), + r_vci_rsp_data_error("r_vci_rsp_data_error"), + r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth + r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth + + r_cc_send_fsm("r_cc_send_fsm"), + r_cc_send_last_client("r_cc_send_last_client"), + + r_cc_receive_fsm("r_cc_receive_fsm"), + r_cc_receive_data_ins("r_cc_receive_data_ins"), + r_cc_receive_word_idx("r_cc_receive_word_idx"), + r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2), // 2 words depth + r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2), // 2 words depth + r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2), // 2 words depth + + r_cc_receive_icache_req("r_cc_receive_icache_req"), + r_cc_receive_icache_type("r_cc_receive_icache_type"), + r_cc_receive_icache_way("r_cc_receive_icache_way"), + r_cc_receive_icache_set("r_cc_receive_icache_set"), + r_cc_receive_icache_updt_tab_idx("r_cc_receive_icache_updt_tab_idx"), + r_cc_receive_icache_nline("r_cc_receive_icache_nline"), + + r_cc_receive_dcache_req("r_cc_receive_dcache_req"), + r_cc_receive_dcache_type("r_cc_receive_dcache_type"), + r_cc_receive_dcache_way("r_cc_receive_dcache_way"), + r_cc_receive_dcache_set("r_cc_receive_dcache_set"), + r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"), + r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"), + + r_iss(this->name(), proc_id), + r_wbuf("wbuf", wbuf_nwords, wbuf_nlines, dcache_words ), + r_icache("icache", icache_ways, icache_sets, icache_words), + r_dcache("dcache", dcache_ways, dcache_sets, dcache_words), + r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N), + r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N) +{ + std::cout << " - Building VciCcVcacheWrapper : " << name << std::endl; + + assert( ((icache_words*vci_param::B) < (1< 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and + "Need more TRDID bits."); + + assert( (icache_words == dcache_words) and + "icache_words and dcache_words parameters must be equal"); + + assert( (itlb_sets == dtlb_sets) and + "itlb_sets and dtlb_sets parameters must be etqual"); + + assert( (itlb_ways == dtlb_ways) and + "itlb_ways and dtlb_ways parameters must be etqual"); + + r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) | (uint32_log2(m_dtlb_sets) << 25) | + (uint32_log2(m_dcache_ways) << 22) | (uint32_log2(m_dcache_sets) << 18) | + (uint32_log2(m_itlb_ways) << 15) | (uint32_log2(m_itlb_sets) << 11) | + (uint32_log2(m_icache_ways) << 8) | (uint32_log2(m_icache_sets) << 4) | + (uint32_log2(m_icache_words<<2)); + + r_mmu_release = (uint32_t)(1 << 16) | 0x1; + + r_dcache_in_tlb = new bool[dcache_ways*dcache_sets]; + r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets]; + + SC_METHOD(transition); + dont_initialize(); + sensitive << p_clk.pos(); + + SC_METHOD(genMoore); + dont_initialize(); + sensitive << p_clk.neg(); + + typename iss_t::CacheInfo cache_info; + cache_info.has_mmu = true; + cache_info.icache_line_size = icache_words*sizeof(uint32_t); + cache_info.icache_assoc = icache_ways; + cache_info.icache_n_lines = icache_sets; + cache_info.dcache_line_size = dcache_words*sizeof(uint32_t); + cache_info.dcache_assoc = dcache_ways; + cache_info.dcache_n_lines = dcache_sets; + r_iss.setCacheInfo(cache_info); +} + +///////////////////////////////////// +tmpl(/**/)::~VciCcVCacheWrapper() +///////////////////////////////////// +{ + delete [] r_dcache_in_tlb; + delete [] r_dcache_contains_ptd; +} + +//////////////////////// +tmpl(void)::print_cpi() +//////////////////////// +{ + std::cout << name() << " CPI = " + << (float)m_cpt_total_cycles/(m_cpt_total_cycles - m_cpt_frz_cycles) << std::endl ; +} + +//////////////////////////////////// +tmpl(void)::print_trace(size_t mode) +//////////////////////////////////// +{ + // b0 : write buffer trace + // b2 : dcache trace + // b3 : icache trace + // b4 : dtlb trace + // b5 : itlb trace + + std::cout << std::dec << "PROC " << name() << std::endl; + + std::cout << " " << m_ireq << std::endl; + std::cout << " " << m_irsp << std::endl; + std::cout << " " << m_dreq << std::endl; + std::cout << " " << m_drsp << std::endl; + + std::cout << " " << icache_fsm_state_str[r_icache_fsm.read()] + << " | " << dcache_fsm_state_str[r_dcache_fsm.read()] + << " | " << cmd_fsm_state_str[r_vci_cmd_fsm.read()] + << " | " << rsp_fsm_state_str[r_vci_rsp_fsm.read()] + << " | " << cc_receive_fsm_state_str[r_cc_receive_fsm.read()] + << " | " << cc_send_fsm_state_str[r_cc_send_fsm.read()] + << " | MMU = " << r_mmu_mode.read(); + + if (r_dcache_updt_req.read() ) std::cout << " | P1_UPDT"; + if (r_dcache_wbuf_req.read() ) std::cout << " | P1_WBUF"; + std::cout << std::endl; + + if(mode & 0x01) + { + if ( r_icache_miss_req.read() ) std::cout << " IMISS_REQ" << std::endl; + if ( r_icache_unc_req.read() ) std::cout << " IUNC_REQ" << std::endl; + if ( r_dcache_vci_miss_req.read() ) std::cout << " DMISS_REQ" << std::endl; + if ( r_dcache_vci_unc_req.read() ) std::cout << " DUNC_REQ" << std::endl; + + r_wbuf.printTrace((mode>>1)&1); + } + if(mode & 0x04) + { + std::cout << " Data Cache" << std::endl; + r_dcache.printTrace(); + } + if(mode & 0x08) + { + std::cout << " Instruction Cache" << std::endl; + r_icache.printTrace(); + } + if(mode & 0x10) + { + std::cout << " Data TLB" << std::endl; + r_dtlb.printTrace(); + } + if(mode & 0x20) + { + std::cout << " Instruction TLB" << std::endl; + r_itlb.printTrace(); + } +} + +////////////////////////////////////////// +tmpl(void)::cache_monitor( paddr_t addr ) +////////////////////////////////////////// +{ + bool cache_hit; + size_t cache_way = 0; + size_t cache_set = 0; + size_t cache_word = 0; + uint32_t cache_rdata = 0; + + cache_hit = r_dcache.read_neutral( addr, + &cache_rdata, + &cache_way, + &cache_set, + &cache_word ); + + if ( cache_hit != m_debug_previous_d_hit ) + { + std::cout << "Monitor PROC " << name() + << " DCACHE at cycle " << std::dec << m_cpt_total_cycles + << " / HIT = " << cache_hit + << " / PADDR = " << std::hex << addr + << " / DATA = " << cache_rdata + << " / WAY = " << cache_way << std::endl; + m_debug_previous_d_hit = cache_hit; + } + + cache_hit = r_icache.read_neutral( addr, + &cache_rdata, + &cache_way, + &cache_set, + &cache_word ); + + if ( cache_hit != m_debug_previous_i_hit ) + { + std::cout << "Monitor PROC " << name() + << " ICACHE at cycle " << std::dec << m_cpt_total_cycles + << " / HIT = " << cache_hit + << " / PADDR = " << std::hex << addr + << " / DATA = " << cache_rdata + << " / WAY = " << cache_way << std::endl; + m_debug_previous_i_hit = cache_hit; + } +} + +/* +//////////////////////// +tmpl(void)::print_stats() +//////////////////////// +{ + float run_cycles = (float)(m_cpt_total_cycles - m_cpt_frz_cycles); + std::cout << name() << std::endl + << "- CPI = " << (float)m_cpt_total_cycles/run_cycles << std::endl + << "- READ RATE = " << (float)m_cpt_read/run_cycles << std::endl + << "- WRITE RATE = " << (float)m_cpt_write/run_cycles << std::endl + << "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl + << "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_read-m_cpt_unc_read) << std::endl + << "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl + << "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl + << "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_write << std::endl + << "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl + << "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_read << std::endl + << "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_write << std::endl + << "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl + << "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl + << "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl + << "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl + << "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl + << "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl + << "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl + << "- ITLB HIT IN DCACHE RATE= " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl + << "- DTLB HIT IN DCACHE RATE= " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl + << "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl + << "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl + << "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl + << "- NB CC UPDATE DATA = " << m_cpt_cc_update_data << std::endl + << "- NB CC INVAL DATA = " << m_cpt_cc_inval_data << std::endl + << "- NB CC INVAL INS = " << m_cpt_cc_inval_ins << std::endl + << "- CC BROADCAST COST = " << (float)m_cost_broadcast_frz/m_cpt_cc_broadcast << std::endl + << "- CC UPDATE DATA COST = " << (float)m_cost_updt_data_frz/m_cpt_cc_update_data << std::endl + << "- CC INVAL DATA COST = " << (float)m_cost_inval_data_frz/m_cpt_cc_inval_data << std::endl + << "- CC INVAL INS COST = " << (float)m_cost_inval_ins_frz/m_cpt_cc_inval_ins << std::endl + << "- NB CC CLEANUP DATA = " << m_cpt_cc_cleanup_data << std::endl + << "- NB CC CLEANUP INS = " << m_cpt_cc_cleanup_ins << std::endl + << "- IMISS TRANSACTION = " << (float)m_cost_imiss_transaction/m_cpt_imiss_transaction << std::endl + << "- DMISS TRANSACTION = " << (float)m_cost_dmiss_transaction/m_cpt_dmiss_transaction << std::endl + << "- UNC TRANSACTION = " << (float)m_cost_unc_transaction/m_cpt_unc_transaction << std::endl + << "- WRITE TRANSACTION = " << (float)m_cost_write_transaction/m_cpt_write_transaction << std::endl + << "- WRITE LENGTH = " << (float)m_length_write_transaction/m_cpt_write_transaction << std::endl + << "- ITLB MISS TRANSACTION = " << (float)m_cost_itlbmiss_transaction/m_cpt_itlbmiss_transaction << std::endl + << "- DTLB MISS TRANSACTION = " << (float)m_cost_dtlbmiss_transaction/m_cpt_dtlbmiss_transaction << std::endl; +} + +//////////////////////// +tmpl(void)::clear_stats() +//////////////////////// +{ + m_cpt_dcache_data_read = 0; + m_cpt_dcache_data_write = 0; + m_cpt_dcache_dir_read = 0; + m_cpt_dcache_dir_write = 0; + m_cpt_icache_data_read = 0; + m_cpt_icache_data_write = 0; + m_cpt_icache_dir_read = 0; + m_cpt_icache_dir_write = 0; + + m_cpt_frz_cycles = 0; + m_cpt_dcache_frz_cycles = 0; + m_cpt_total_cycles = 0; + + m_cpt_read = 0; + m_cpt_write = 0; + m_cpt_data_miss = 0; + m_cpt_ins_miss = 0; + m_cpt_unc_read = 0; + m_cpt_write_cached = 0; + m_cpt_ins_read = 0; + + m_cost_write_frz = 0; + m_cost_data_miss_frz = 0; + m_cost_unc_read_frz = 0; + m_cost_ins_miss_frz = 0; + + m_cpt_imiss_transaction = 0; + m_cpt_dmiss_transaction = 0; + m_cpt_unc_transaction = 0; + m_cpt_write_transaction = 0; + m_cpt_icache_unc_transaction = 0; + + m_cost_imiss_transaction = 0; + m_cost_dmiss_transaction = 0; + m_cost_unc_transaction = 0; + m_cost_write_transaction = 0; + m_cost_icache_unc_transaction = 0; + m_length_write_transaction = 0; + + m_cpt_ins_tlb_read = 0; + m_cpt_ins_tlb_miss = 0; + m_cpt_ins_tlb_update_acc = 0; + + m_cpt_data_tlb_read = 0; + m_cpt_data_tlb_miss = 0; + m_cpt_data_tlb_update_acc = 0; + m_cpt_data_tlb_update_dirty = 0; + m_cpt_ins_tlb_hit_dcache = 0; + m_cpt_data_tlb_hit_dcache = 0; + m_cpt_ins_tlb_occup_cache = 0; + m_cpt_data_tlb_occup_cache = 0; + + m_cost_ins_tlb_miss_frz = 0; + m_cost_data_tlb_miss_frz = 0; + m_cost_ins_tlb_update_acc_frz = 0; + m_cost_data_tlb_update_acc_frz = 0; + m_cost_data_tlb_update_dirty_frz = 0; + m_cost_ins_tlb_occup_cache_frz = 0; + m_cost_data_tlb_occup_cache_frz = 0; + + m_cpt_itlbmiss_transaction = 0; + m_cpt_itlb_ll_transaction = 0; + m_cpt_itlb_sc_transaction = 0; + m_cpt_dtlbmiss_transaction = 0; + m_cpt_dtlb_ll_transaction = 0; + m_cpt_dtlb_sc_transaction = 0; + m_cpt_dtlb_ll_dirty_transaction = 0; + m_cpt_dtlb_sc_dirty_transaction = 0; + + m_cost_itlbmiss_transaction = 0; + m_cost_itlb_ll_transaction = 0; + m_cost_itlb_sc_transaction = 0; + m_cost_dtlbmiss_transaction = 0; + m_cost_dtlb_ll_transaction = 0; + m_cost_dtlb_sc_transaction = 0; + m_cost_dtlb_ll_dirty_transaction = 0; + m_cost_dtlb_sc_dirty_transaction = 0; + + m_cpt_cc_update_data = 0; + m_cpt_cc_inval_ins = 0; + m_cpt_cc_inval_data = 0; + m_cpt_cc_broadcast = 0; + + m_cost_updt_data_frz = 0; + m_cost_inval_ins_frz = 0; + m_cost_inval_data_frz = 0; + m_cost_broadcast_frz = 0; + + m_cpt_cc_cleanup_data = 0; + m_cpt_cc_cleanup_ins = 0; +} + +*/ + +///////////////////////// +tmpl(void)::transition() +///////////////////////// +{ + if ( not p_resetn.read() ) + { + r_iss.reset(); + r_wbuf.reset(); + r_icache.reset(); + r_dcache.reset(); + r_itlb.reset(); + r_dtlb.reset(); + + r_dcache_fsm = DCACHE_IDLE; + r_icache_fsm = ICACHE_IDLE; + r_vci_cmd_fsm = CMD_IDLE; + r_vci_rsp_fsm = RSP_IDLE; + r_cc_receive_fsm = CC_RECEIVE_IDLE; + r_cc_send_fsm = CC_SEND_IDLE; + + // reset data physical address extension + r_dcache_paddr_ext = m_dcache_paddr_ext_reset; + + // reset inst physical address extension + r_icache_paddr_ext = m_icache_paddr_ext_reset; + + // reset dcache directory extension + for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++) + { + r_dcache_in_tlb[i] = false; + r_dcache_contains_ptd[i] = false; + } + + // Response FIFOs and cleanup buffer + r_vci_rsp_fifo_icache.init(); + r_vci_rsp_fifo_dcache.init(); + + // ICACHE & DCACHE activated + // ITLB & DTLB desactivated + r_mmu_mode = 0x3; + + // No request from ICACHE FSM to CMD FSM + r_icache_miss_req = false; + r_icache_unc_req = false; + + // No request from ICACHE_FSM to DCACHE FSM + r_icache_tlb_miss_req = false; + + // No request from ICACHE_FSM to CC_SEND FSM + r_icache_cc_send_req = false; + r_icache_cleanup_victim_req = false; + + r_icache_clack_req = false; + + // No pending write in pipeline + r_dcache_wbuf_req = false; + r_dcache_updt_req = false; + + // No request from DCACHE_FSM to CMD_FSM + r_dcache_vci_miss_req = false; + r_dcache_vci_unc_req = false; + r_dcache_vci_cas_req = false; + r_dcache_vci_ll_req = false; + r_dcache_vci_sc_req = false; + + // No processor XTN request pending + r_dcache_xtn_req = false; + + // No request from DCACHE FSM to CC_SEND FSM + r_dcache_cc_send_req = false; + r_dcache_cleanup_victim_req = false; + + r_dcache_clack_req = false; + + // No request from CC_RECEIVE FSM to ICACHE/DCACHE FSMs + r_cc_receive_icache_req = false; + r_cc_receive_dcache_req = false; + + // last cc_send client was dcache + r_cc_send_last_client = false; + + // No pending cleanup after a replacement + r_icache_miss_clack = false; + r_dcache_miss_clack = false; + + // No signalisation of a coherence request matching a pending miss + r_icache_miss_inval = false; + r_dcache_miss_inval = false; + + r_dspin_clack_req = false; + + // No signalisation of errors + r_vci_rsp_ins_error = false; + r_vci_rsp_data_error = false; + + // Debug variables + m_debug_previous_i_hit = false; + m_debug_previous_d_hit = false; + m_debug_icache_fsm = false; + m_debug_dcache_fsm = false; + m_debug_cmd_fsm = false; + + // activity counters + m_cpt_dcache_data_read = 0; + m_cpt_dcache_data_write = 0; + m_cpt_dcache_dir_read = 0; + m_cpt_dcache_dir_write = 0; + m_cpt_icache_data_read = 0; + m_cpt_icache_data_write = 0; + m_cpt_icache_dir_read = 0; + m_cpt_icache_dir_write = 0; + + m_cpt_frz_cycles = 0; + m_cpt_total_cycles = 0; + m_cpt_stop_simulation = 0; + + m_cpt_data_miss = 0; + m_cpt_ins_miss = 0; + m_cpt_unc_read = 0; + m_cpt_write_cached = 0; + m_cpt_ins_read = 0; + + m_cost_write_frz = 0; + m_cost_data_miss_frz = 0; + m_cost_unc_read_frz = 0; + m_cost_ins_miss_frz = 0; + + m_cpt_imiss_transaction = 0; + m_cpt_dmiss_transaction = 0; + m_cpt_unc_transaction = 0; + m_cpt_write_transaction = 0; + m_cpt_icache_unc_transaction = 0; + + m_cost_imiss_transaction = 0; + m_cost_dmiss_transaction = 0; + m_cost_unc_transaction = 0; + m_cost_write_transaction = 0; + m_cost_icache_unc_transaction = 0; + m_length_write_transaction = 0; + + m_cpt_ins_tlb_read = 0; + m_cpt_ins_tlb_miss = 0; + m_cpt_ins_tlb_update_acc = 0; + + m_cpt_data_tlb_read = 0; + m_cpt_data_tlb_miss = 0; + m_cpt_data_tlb_update_acc = 0; + m_cpt_data_tlb_update_dirty = 0; + m_cpt_ins_tlb_hit_dcache = 0; + m_cpt_data_tlb_hit_dcache = 0; + m_cpt_ins_tlb_occup_cache = 0; + m_cpt_data_tlb_occup_cache = 0; + + m_cost_ins_tlb_miss_frz = 0; + m_cost_data_tlb_miss_frz = 0; + m_cost_ins_tlb_update_acc_frz = 0; + m_cost_data_tlb_update_acc_frz = 0; + m_cost_data_tlb_update_dirty_frz = 0; + m_cost_ins_tlb_occup_cache_frz = 0; + m_cost_data_tlb_occup_cache_frz = 0; + + m_cpt_ins_tlb_inval = 0; + m_cpt_data_tlb_inval = 0; + m_cost_ins_tlb_inval_frz = 0; + m_cost_data_tlb_inval_frz = 0; + + m_cpt_cc_broadcast = 0; + + m_cost_updt_data_frz = 0; + m_cost_inval_ins_frz = 0; + m_cost_inval_data_frz = 0; + m_cost_broadcast_frz = 0; + + m_cpt_cc_cleanup_data = 0; + m_cpt_cc_cleanup_ins = 0; + + m_cpt_itlbmiss_transaction = 0; + m_cpt_itlb_ll_transaction = 0; + m_cpt_itlb_sc_transaction = 0; + m_cpt_dtlbmiss_transaction = 0; + m_cpt_dtlb_ll_transaction = 0; + m_cpt_dtlb_sc_transaction = 0; + m_cpt_dtlb_ll_dirty_transaction = 0; + m_cpt_dtlb_sc_dirty_transaction = 0; + + m_cost_itlbmiss_transaction = 0; + m_cost_itlb_ll_transaction = 0; + m_cost_itlb_sc_transaction = 0; + m_cost_dtlbmiss_transaction = 0; + m_cost_dtlb_ll_transaction = 0; + m_cost_dtlb_sc_transaction = 0; + m_cost_dtlb_ll_dirty_transaction = 0; + m_cost_dtlb_sc_dirty_transaction = 0; +/* + m_cpt_dcache_frz_cycles = 0; + m_cpt_read = 0; + m_cpt_write = 0; + m_cpt_cc_update_data = 0; + m_cpt_cc_inval_ins = 0; + m_cpt_cc_inval_data = 0; +*/ + + for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0; + for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0; + for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0; + for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0; + + // init the llsc reservation buffer + r_dcache_llsc_valid = false; + m_monitor_ok = false; + + return; + } + + // Response FIFOs default values + bool vci_rsp_fifo_icache_get = false; + bool vci_rsp_fifo_icache_put = false; + uint32_t vci_rsp_fifo_icache_data = 0; + + bool vci_rsp_fifo_dcache_get = false; + bool vci_rsp_fifo_dcache_put = false; + uint32_t vci_rsp_fifo_dcache_data = 0; + + // updt fifo + bool cc_receive_updt_fifo_get = false; + bool cc_receive_updt_fifo_put = false; + uint32_t cc_receive_updt_fifo_be = 0; + uint32_t cc_receive_updt_fifo_data = 0; + bool cc_receive_updt_fifo_eop = false; + +#ifdef INSTRUMENTATION + m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++; + m_cpt_fsm_icache [r_icache_fsm.read() ] ++; + m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++; + m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++; + m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++; + m_cpt_fsm_cleanup [r_cleanup_cmd_fsm.read()] ++; +#endif + + m_cpt_total_cycles++; + + m_debug_icache_fsm = m_debug_icache_fsm || + ((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok); + m_debug_dcache_fsm = m_debug_dcache_fsm || + ((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok); + m_debug_cmd_fsm = m_debug_cmd_fsm || + ((m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok); + + ///////////////////////////////////////////////////////////////////// + // Get data and instruction requests from processor + /////////////////////////////////////////////////////////////////////// + + r_iss.getRequests(m_ireq, m_dreq); + + //////////////////////////////////////////////////////////////////////////////////// + // ICACHE_FSM + // + // 1/ Coherence operations + // They are handled as interrupts generated by the CC_RECEIVE FSM. + // - There is a coherence request when r_tgt_icache_req is set. + // They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, states. + // - There is a cleanup ack request when r_cleanup_icache_req is set. + // They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, + // MISS_DATA_UPDT, MISS_DIR_UPDT and UNC_WAIT states. + // - For both types of requests, actions associated to the pre-empted state + // are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK + // or CC_CLACK) to execute the requested coherence operation, and returns + // to the pre-empted state. + // + // 2/ Processor requests + // They are taken in IDLE state only. In case of cache miss, or uncacheable + // instruction, the ICACHE FSM request a VCI transaction to CMD FSM, + // using the r_icache_miss_req or r_icache_unc_req flip-flops. These + // flip-flops are reset when the transaction starts. + // - In case of miss the ICACHE FSM goes to the ICACHE_MISS_SELECT state + // to select a slot and possibly request a cleanup transaction to the CC_SEND FSM. + // It goes next to the ICACHE_MISS_WAIT state waiting a response from RSP FSM, + // The availability of the missing cache line is signaled by the response fifo, + // and the cache update is done (one word per cycle) in the ICACHE_MISS_DATA_UPDT + // and ICACHE_MISS_DIR_UPDT states. + // - In case of uncacheable instruction, the ICACHE FSM goes to ICACHE_UNC_WAIT + // to wait the response from the RSP FSM, through the response fifo. + // The missing instruction is directly returned to processor in this state. + // + // 3/ TLB miss + // In case of tlb miss, the ICACHE FSM request to the DCACHE FSM to update the + // ITLB using the r_icache_tlb_miss_req flip-flop and the r_icache_tlb_miss_vaddr + // register, and goes to the ICACHE_TLB_WAIT state. + // The tlb update is entirely done by the DCACHE FSM (who becomes the owner + // of ITLB until the update is completed, and reset r_icache_tlb_miss_req + // to signal the completion. + // + // 4/ XTN requests + // The DCACHE FSM signals XTN processor requests to ICACHE_FSM + // using the r_dcache_xtn_req flip-flop. + // The request opcode and the address to be invalidated are transmitted + // in the r_dcache_xtn_opcode and r_dcache_save_wdata registers respectively. + // The r_dcache_xtn_req flip-flop is reset by the ICACHE_FSM when the operation + // is completed. + // + // 5/ Error Handling + // The r_vci_rsp_ins_error flip-flop is set by the RSP FSM in case of bus error + // in a cache miss or uncacheable read VCI transaction. Nothing is written + // in the response fifo. This flip-flop is reset by the ICACHE-FSM. + //////////////////////////////////////////////////////////////////////////////////////// + + // default value for m_irsp + m_irsp.valid = false; + m_irsp.error = false; + m_irsp.instruction = 0; + + switch( r_icache_fsm.read() ) + { + ///////////////// + case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests, + // and coherence requests with a fixed priority: + // 1/ Coherence requests => ICACHE_CC_CHECK + // 2/ XTN processor requests (from DCACHE FSM) => ICACHE_XTN_* + // 3/ tlb miss => ICACHE_TLB_WAIT + // 4/ cacheable read miss => ICACHE_MISS_SELECT + // 5/ uncacheable read miss => ICACHE_UNC_REQ + { + // coherence clack interrupt + if ( r_icache_clack_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + // coherence interrupt + if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + // XTN requests sent by DCACHE FSM + // These request are not executed in this IDLE state (except XTN_INST_PADDR_EXT), + // because they require access to icache or itlb, that are already accessed + if ( r_dcache_xtn_req.read() ) + { + if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR ) + { + r_icache_fsm = ICACHE_XTN_TLB_FLUSH; + } + else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH) + { + r_icache_flush_count = 0; + r_icache_fsm = ICACHE_XTN_CACHE_FLUSH; + } + else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL) + { + r_icache_fsm = ICACHE_XTN_TLB_INVAL; + } + else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL) + { + r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA; + } + else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV) + { + if (sizeof(paddr_t) <= 32) + { + assert(r_mmu_word_hi.read() == 0 && + "illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr"); + r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read(); + } + else + { + r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 | + (paddr_t)r_mmu_word_lo.read(); + } + r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA; + } + else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_INST_PADDR_EXT) + { + r_icache_paddr_ext = r_dcache_save_wdata.read(); + r_dcache_xtn_req = false; + } + else + { + assert( false and + "undefined XTN request received by ICACHE FSM"); + } + break; + } // end if xtn_req + + // processor request + if ( m_ireq.valid ) + { + bool cacheable; + paddr_t paddr; + bool tlb_hit = false; + pte_info_t tlb_flags; + size_t tlb_way; + size_t tlb_set; + paddr_t tlb_nline; + uint32_t cache_inst = 0; + size_t cache_way; + size_t cache_set; + size_t cache_word; + int cache_state = CACHE_SLOT_STATE_EMPTY; + + // We register processor request + r_icache_vaddr_save = m_ireq.addr; + + // sytematic itlb access (if activated) + if ( r_mmu_mode.read() & INS_TLB_MASK ) + { + +#ifdef INSTRUMENTATION +m_cpt_itlb_read++; +#endif + tlb_hit = r_itlb.translate( m_ireq.addr, + &paddr, + &tlb_flags, + &tlb_nline, // unused + &tlb_way, // unused + &tlb_set ); // unused + } + else + { + if (vci_param::N > 32) + { + paddr = (paddr_t)m_ireq.addr | + ((paddr_t)r_icache_paddr_ext.read() << 32); + } + else + { + paddr = (paddr_t)m_ireq.addr; + } + } + + // systematic icache access (if activated) + if ( r_mmu_mode.read() & INS_CACHE_MASK ) + { + + +#ifdef INSTRUMENTATION +m_cpt_icache_data_read++; +m_cpt_icache_dir_read++; +#endif + r_icache.read( paddr, + &cache_inst, + &cache_way, + &cache_set, + &cache_word, + &cache_state ); + } + + // We compute cacheability and check access rights: + // - If MMU activated : cacheability is defined by the C bit in the PTE, + // and the access rights are defined by the U and X bits in the PTE. + // - If MMU not activated : cacheability is defined by the segment table, + // and there is no access rights checking + + if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated: + { + // cacheability + if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false; + else cacheable = m_cacheability_table[(uint64_t)m_ireq.addr]; + } + else // itlb activated + { + if ( tlb_hit ) // ITLB hit + { + // cacheability + if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false; + else cacheable = tlb_flags.c; + + // access rights checking + if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) ) + { + r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION; + r_mmu_ibvar = m_ireq.addr; + m_irsp.valid = true; + m_irsp.error = true; + m_irsp.instruction = 0; + break; + } + else if ( not tlb_flags.x ) + { + r_mmu_ietr = MMU_READ_EXEC_VIOLATION; + r_mmu_ibvar = m_ireq.addr; + m_irsp.valid = true; + m_irsp.error = true; + m_irsp.instruction = 0; + break; + } + } + else // ITLB miss + { + +#ifdef INSTRUMENTATION +m_cpt_itlb_miss++; +#endif + r_icache_fsm = ICACHE_TLB_WAIT; + r_icache_tlb_miss_req = true; + break; + } + } // end if itlb activated + + // physical address registration + r_icache_vci_paddr = paddr; + + // Finally, we send the response to processor, and compute next state + if ( cacheable ) + { + if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss + { + +#ifdef INSTRUMENTATION +m_cpt_icache_miss++; +#endif + // we request a VCI transaction + r_icache_fsm = ICACHE_MISS_SELECT; +#if DEBUG_ICACHE +if ( m_debug_icache_fsm ) +std::cout << " READ MISS in icache" + << " : PADDR = " << std::hex << paddr << std::endl; +#endif + r_icache_miss_req = true; + } + else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup + { + // stalled until cleanup is acknowledged + r_icache_fsm = ICACHE_IDLE; + } + else // cache hit + { + +#ifdef INSTRUMENTATION +m_cpt_ins_read++; +#endif + // return instruction to processor + m_irsp.valid = true; + m_irsp.instruction = cache_inst; + r_icache_fsm = ICACHE_IDLE; +#if DEBUG_ICACHE +if ( m_debug_icache_fsm ) +std::cout << " READ HIT in icache" + << " : PADDR = " << std::hex << paddr + << " / INST = " << cache_inst << std::endl; +#endif + } + } + else // non cacheable read + { + r_icache_unc_req = true; + r_icache_fsm = ICACHE_UNC_WAIT; + +#if DEBUG_ICACHE +if ( m_debug_icache_fsm ) +{ + std::cout << " READ UNCACHEABLE in icache" + << " : PADDR = " << std::hex << paddr << std::endl; +} +#endif + } + } // end if m_ireq.valid + break; + } + ///////////////////// + case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss + // the itlb is udated by the DCACHE FSM, as well as the + // r_mmu_ietr and r_mmu_ibvar registers in case of error. + // the itlb is not accessed by ICACHE FSM until DCACHE FSM + // reset the r_icache_tlb_miss_req flip-flop + // external coherence request are accepted in this state. + { + // coherence clack interrupt + if ( r_icache_clack_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + // coherence interrupt + if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++; + + // DCACHE FSM signals response by reseting the request flip-flop + if ( not r_icache_tlb_miss_req.read() ) + { + if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated + { + r_icache_tlb_rsp_error = false; + m_irsp.error = true; + m_irsp.valid = true; + r_icache_fsm = ICACHE_IDLE; + } + else // tlb updated : return to IDLE state + { + r_icache_fsm = ICACHE_IDLE; + } + } + break; + } + ////////////////////////// + case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries + { + r_itlb.flush(); + r_dcache_xtn_req = false; + r_icache_fsm = ICACHE_IDLE; + break; + } + //////////////////////////// + case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using + // r_icache_flush_count as a slot counter, + // looping in this state until all slots are visited. + // It can require two cycles per slot: + // We test here the slot state, and make the actual inval + // (if line is valid) in ICACHE_XTN_CACHE_FLUSH_GO state. + // A cleanup request is generated for each valid line + { + // coherence clack interrupt + if ( r_icache_clack_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request is sent + { + int state; + paddr_t tag; + size_t way = r_icache_flush_count.read()/m_icache_sets; + size_t set = r_icache_flush_count.read()%m_icache_sets; + +#ifdef INSTRUMENTATION +m_cpt_icache_dir_read++; +#endif + r_icache.read_dir( way, + set, + &tag, + &state ); + + if ( state == CACHE_SLOT_STATE_VALID ) // inval required + { + // request cleanup + r_icache_cc_send_req = true; + r_icache_cc_send_nline = tag * m_icache_sets + set; + r_icache_cc_send_way = way; + r_icache_cc_send_type = CC_TYPE_CLEANUP; + + // goes to ICACHE_XTN_CACHE_FLUSH_GO to make inval + r_icache_miss_way = way; + r_icache_miss_set = set; + r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO; + } + else if ( r_icache_flush_count.read() == + (m_icache_sets*m_icache_ways - 1) ) // last slot + { + r_dcache_xtn_req = false; + m_drsp.valid = true; + r_icache_fsm = ICACHE_IDLE; + } + + // saturation counter, to have the same last slot condition + // in ICACHE_XTN_CACHE_FLUSH and ICACHE_XTN_CACHE_FLUSH_GO states + if ( r_icache_flush_count.read() < (m_icache_sets*m_icache_ways - 1) ) + { + r_icache_flush_count = r_icache_flush_count.read() + 1; + } + } + break; + } + /////////////////////////////// + case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush + { + size_t way = r_icache_miss_way.read(); + size_t set = r_icache_miss_set.read(); + +#ifdef INSTRUMENTATION +m_cpt_icache_dir_write++; +#endif + + r_icache.write_dir( way, + set, + CACHE_SLOT_STATE_ZOMBI ); + + if ( r_icache_flush_count.read() == + (m_icache_sets*m_icache_ways - 1) ) // last slot + { + r_dcache_xtn_req = false; + m_drsp.valid = true; + r_icache_fsm = ICACHE_IDLE; + } + else + { + r_icache_fsm = ICACHE_XTN_CACHE_FLUSH; + } + break; + } + + ////////////////////////// + case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address + // stored in the r_dcache_save_wdata register + { + r_itlb.inval(r_dcache_save_wdata.read()); + r_dcache_xtn_req = false; + r_icache_fsm = ICACHE_IDLE; + break; + } + /////////////////////////////// + case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address + // requires 3 cycles (in case of hit on itlb and icache). + // In this state, access TLB to translate virtual address + // stored in the r_dcache_save_wdata register. + { + paddr_t paddr; + bool hit; + + // read physical address in TLB when MMU activated + if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated + { + +#ifdef INSTRUMENTATION +m_cpt_itlb_read++; +#endif + hit = r_itlb.translate(r_dcache_save_wdata.read(), + &paddr); + } + else // itlb not activated + { + paddr = (paddr_t)r_dcache_save_wdata.read(); + hit = true; + } + + if ( hit ) // continue the selective inval process + { + r_icache_vci_paddr = paddr; + r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA; + } + else // miss : send a request to DCACHE FSM + { + +#ifdef INSTRUMENTATION +m_cpt_itlb_miss++; +#endif + r_icache_tlb_miss_req = true; + r_icache_vaddr_save = r_dcache_save_wdata.read(); + r_icache_fsm = ICACHE_TLB_WAIT; + } + break; + } + /////////////////////////////// + case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address + // require 2 cycles. In this state, we read directory + // with address stored in r_icache_vci_paddr register. + { + int state; + size_t way; + size_t set; + size_t word; + +#ifdef INSTRUMENTATION +m_cpt_icache_dir_read++; +#endif + r_icache.read_dir(r_icache_vci_paddr.read(), + &state, + &way, + &set, + &word); + + if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done + { + r_icache_miss_way = way; + r_icache_miss_set = set; + r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO; + } + else // miss : acknowlege the XTN request and return + { + r_dcache_xtn_req = false; + r_icache_fsm = ICACHE_IDLE; + } + break; + } + /////////////////////////////// + case ICACHE_XTN_CACHE_INVAL_GO: // Switch slot to ZOMBI state for an XTN inval + { + if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request not sent + { + +#ifdef INSTRUMENTATION +m_cpt_icache_dir_write++; +#endif + r_icache.write_dir( r_icache_miss_way.read(), + r_icache_miss_set.read(), + CACHE_SLOT_STATE_ZOMBI ); + + // request cleanup + r_icache_cc_send_req = true; + r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2); + r_icache_cc_send_way = r_icache_miss_way.read(); + r_icache_cc_send_type = CC_TYPE_CLEANUP; + + // acknowledge the XTN request and return + r_dcache_xtn_req = false; + r_icache_fsm = ICACHE_IDLE; + } + break; + } + //////////////////////// + case ICACHE_MISS_SELECT: // Try to select a slot in associative set, + // Waiting in this state if no slot available. + // If a victim slot has been choosen and the r_icache_cc_send_req is false, + // we send the cleanup request in this state. + // If not, a r_icache_cleanup_victim_req flip-flop is + // utilized for saving this cleanup request, and it will be sent later + // in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR. + // The r_icache_miss_clack flip-flop is set + // when a cleanup is required + { + if (m_ireq.valid) m_cost_ins_miss_frz++; + + // coherence clack interrupt + if ( r_icache_clack_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + // coherence interrupt + if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + + bool found; + bool cleanup; + size_t way; + size_t set; + paddr_t victim; + +#ifdef INSTRUMENTATION +m_cpt_icache_dir_read++; +#endif + r_icache.read_select(r_icache_vci_paddr.read(), + &victim, + &way, + &set, + &found, + &cleanup ); + if ( not found ) + { + break; + } + else + { + r_icache_miss_way = way; + r_icache_miss_set = set; + + if ( cleanup ) + { + if ( not r_icache_cc_send_req.read() ) + { + r_icache_cc_send_req = true; + r_icache_cc_send_nline = victim; + r_icache_cc_send_way = way; + r_icache_cc_send_type = CC_TYPE_CLEANUP; + } + else + { + r_icache_cleanup_victim_req = true; + r_icache_cleanup_victim_nline = victim; + } + + r_icache_miss_clack = true; + r_icache_fsm = ICACHE_MISS_CLEAN; + } + else + { + r_icache_fsm = ICACHE_MISS_WAIT; + } + +#if DEBUG_ICACHE +if ( m_debug_icache_fsm ) +{ + std::cout << " Select a slot:" << std::dec + << " / WAY = " << way + << " / SET = " << set; + if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl; + else std::cout << std::endl; +} +#endif + } + break; + } + /////////////////////// + case ICACHE_MISS_CLEAN: // switch the slot to zombi state + { + if (m_ireq.valid) m_cost_ins_miss_frz++; + +#ifdef INSTRUMENTATION +m_cpt_icache_dir_write++; +#endif + r_icache.write_dir( r_icache_miss_way.read(), + r_icache_miss_set.read(), + CACHE_SLOT_STATE_ZOMBI); +#if DEBUG_ICACHE +if ( m_debug_icache_fsm ) +{ + std::cout << " Switch to ZOMBI state" << std::dec + << " / WAY = " << r_icache_miss_way.read() + << " / SET = " << r_icache_miss_set.read() << std::endl; +} +#endif + + r_icache_fsm = ICACHE_MISS_WAIT; + break; + } + ////////////////////// + case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM + { + if (m_ireq.valid) m_cost_ins_miss_frz++; + + // send cleanup victim request + if ( r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read() ) + { + r_icache_cc_send_req = true; + r_icache_cc_send_nline = r_icache_cleanup_victim_nline; + r_icache_cc_send_way = r_icache_miss_way; + r_icache_cc_send_type = CC_TYPE_CLEANUP; + r_icache_cleanup_victim_req = false; + } + + // coherence clack interrupt + if ( r_icache_clack_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + // coherence interrupt + if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + if ( r_vci_rsp_ins_error.read() ) // bus error + { + r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS; + r_mmu_ibvar = r_icache_vaddr_save.read(); + m_irsp.valid = true; + m_irsp.error = true; + r_vci_rsp_ins_error = false; + r_icache_fsm = ICACHE_IDLE; + } + else if ( r_vci_rsp_fifo_icache.rok() ) // response available + { + r_icache_miss_word = 0; + r_icache_fsm = ICACHE_MISS_DATA_UPDT; + } + break; + } + /////////////////////////// + case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle) + { + if ( m_ireq.valid ) m_cost_ins_miss_frz++; + + if ( r_vci_rsp_fifo_icache.rok() ) // response available + { + +#ifdef INSTRUMENTATION +m_cpt_icache_data_write++; +#endif + r_icache.write( r_icache_miss_way.read(), + r_icache_miss_set.read(), + r_icache_miss_word.read(), + r_vci_rsp_fifo_icache.read() ); +#if DEBUG_ICACHE +if ( m_debug_icache_fsm ) +{ + std::cout << " Write one word:" + << " WDATA = " << std::hex << r_vci_rsp_fifo_icache.read() + << " WAY = " << r_icache_miss_way.read() + << " SET = " << r_icache_miss_set.read() + << " WORD = " << r_icache_miss_word.read() << std::endl; +} +#endif + vci_rsp_fifo_icache_get = true; + r_icache_miss_word = r_icache_miss_word.read() + 1; + + if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word + { + r_icache_fsm = ICACHE_MISS_DIR_UPDT; + } + } + break; + } + ////////////////////////// + case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted, + // and the cleanup ack has not been received, + // as indicated by r_icache_miss_clack. + // - If no matching coherence request (r_icache_miss_inval) + // switch directory slot to VALID state. + // - If matching coherence request, switch directory slot + // to ZOMBI state, and send a cleanup request. + { + if ( m_ireq.valid ) m_cost_ins_miss_frz++; + + // send cleanup victim request + if ( r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read() ) + { + r_icache_cc_send_req = true; + r_icache_cc_send_nline = r_icache_cleanup_victim_nline; + r_icache_cc_send_way = r_icache_miss_way; + r_icache_cc_send_type = CC_TYPE_CLEANUP; + r_icache_cleanup_victim_req = false; + } + + // coherence clack interrupt + if ( r_icache_clack_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + // coherence interrupt + if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + if ( not r_icache_miss_clack.read() ) // waiting cleanup acknowledge for victim line + { + if ( r_icache_miss_inval ) // Switch slot to ZOMBI state, and new cleanup + { + if ( not r_icache_cc_send_req.read() ) + { + r_icache_miss_inval = false; + // request cleanup + r_icache_cc_send_req = true; + r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2); + r_icache_cc_send_way = r_icache_miss_way.read(); + r_icache_cc_send_type = CC_TYPE_CLEANUP; + +#ifdef INSTRUMENTATION +m_cpt_icache_dir_write++; +#endif + r_icache.write_dir( r_icache_vci_paddr.read(), + r_icache_miss_way.read(), + r_icache_miss_set.read(), + CACHE_SLOT_STATE_ZOMBI ); +#if DEBUG_ICACHE +if ( m_debug_icache_fsm ) +{ + std::cout << " Switch cache slot to ZOMBI state" + << " PADDR = " << std::hex << r_icache_vci_paddr.read() + << " WAY = " << std::dec << r_icache_miss_way.read() + << " SET = " << r_icache_miss_set.read() << std::endl; +} +#endif + } + else + break; + } + else // Switch slot to VALID state + { + +#ifdef INSTRUMENTATION +m_cpt_icache_dir_write++; +#endif + r_icache.write_dir( r_icache_vci_paddr.read(), + r_icache_miss_way.read(), + r_icache_miss_set.read(), + CACHE_SLOT_STATE_VALID ); +#if DEBUG_ICACHE +if ( m_debug_icache_fsm ) +{ + std::cout << " Switch cache slot to VALID state" + << " PADDR = " << std::hex << r_icache_vci_paddr.read() + << " WAY = " << std::dec << r_icache_miss_way.read() + << " SET = " << r_icache_miss_set.read() << std::endl; +} +#endif + } + + r_icache_fsm = ICACHE_IDLE; + } + break; + } + //////////////////// + case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM + { + // coherence clack interrupt + if ( r_icache_clack_req.read() ) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + // coherence interrupt + if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) + { + r_icache_fsm = ICACHE_CC_CHECK; + r_icache_fsm_save = r_icache_fsm.read(); + break; + } + + if ( r_vci_rsp_ins_error.read() ) // bus error + { + r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS; + r_mmu_ibvar = m_ireq.addr; + r_vci_rsp_ins_error = false; + m_irsp.valid = true; + m_irsp.error = true; + r_icache_fsm = ICACHE_IDLE; + } + else if (r_vci_rsp_fifo_icache.rok() ) // instruction available + { + vci_rsp_fifo_icache_get = true; + r_icache_fsm = ICACHE_IDLE; + if ( m_ireq.valid and + (m_ireq.addr == r_icache_vaddr_save.read()) ) // request unmodified + { + m_irsp.valid = true; + m_irsp.instruction = r_vci_rsp_fifo_icache.read(); + } + } + break; + } + ///////////////////// + case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm + // handling coherence requests. + // if there is a matching pending miss, it is + // signaled in the r_icache_miss_inval flip-flop. + // The return state is defined in r_icache_fsm_save. + { + paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4; + paddr_t mask = ~((m_icache_words<<2)-1); + + // CLACK handler + // We switch the directory slot to EMPTY state + // and reset r_icache_miss_clack if the cleanup ack + // is matching a pending miss. + if ( r_icache_clack_req.read() ) + { + + if ( m_ireq.valid ) m_cost_ins_miss_frz++; + +#ifdef INSTRUMENTATION +m_cpt_icache_dir_write++; +#endif + r_icache.write_dir( 0, + r_icache_clack_way.read(), + r_icache_clack_set.read(), + CACHE_SLOT_STATE_EMPTY); + + if ( (r_icache_miss_set.read() == r_icache_clack_set.read()) and + (r_icache_miss_way.read() == r_icache_clack_way.read()) ) + { + r_icache_miss_clack = false; + } + + r_icache_clack_req = false; + + // return to cc_save state + r_icache_fsm = r_icache_fsm_save.read(); + +#if DEBUG_ICACHE +if ( m_debug_icache_fsm ) +{ + std::cout << " CC_TYPE_CLACK slot returns to empty state" + << " set = " << r_icache_clack_set.read() + << " / way = " << r_icache_clack_way.read() << std::endl; +} +#endif + + break; + } + + assert ( not r_icache_cc_send_req.read() and "CC_SEND must be available in ICACHE_CC_CHECK"); + + // Match between MISS address and CC address + if (r_cc_receive_icache_req.read() and + ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT ) or + (r_icache_fsm_save.read() == ICACHE_MISS_WAIT ) or + (r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and + ((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching + { + // signaling the matching + r_icache_miss_inval = true; + + // in case of update, go to CC_UPDT + // JUST TO POP THE FIFO + if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) + { + r_icache_fsm = ICACHE_CC_UPDT; + r_icache_cc_word = r_cc_receive_word_idx.read(); + + // just pop the fifo , don't write in icache + r_icache_cc_need_write = false; + } + // the request is dealt with + else + { + r_cc_receive_icache_req = false; + r_icache_fsm = r_icache_fsm_save.read(); + } +#if DEBUG_ICACHE +if ( m_debug_icache_fsm ) +{ + std::cout << " Coherence request matching a pending miss:" + << " PADDR = " << std::hex << paddr << std::endl; +} +#endif + } + + // CC request handler + + int state = 0; + size_t way = 0; + size_t set = 0; + size_t word = 0; + +#ifdef INSTRUMENTATION +m_cpt_icache_dir_read++; +#endif + r_icache.read_dir(paddr, + &state, + &way, + &set, + &word); + + r_icache_cc_way = way; + r_icache_cc_set = set; + + if ( state == CACHE_SLOT_STATE_VALID) // hit + { + // need to update the cache state + if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) // hit update + { + r_icache_cc_need_write = true; + r_icache_fsm = ICACHE_CC_UPDT; + r_icache_cc_word = r_cc_receive_word_idx.read(); + } + else if ( r_cc_receive_icache_type.read() == CC_TYPE_INVAL ) // hit inval + { + r_icache_fsm = ICACHE_CC_INVAL; + } + } + else // miss + { + // multicast acknowledgement required in case of update + if(r_cc_receive_icache_type.read() == CC_TYPE_UPDT) + { + r_icache_fsm = ICACHE_CC_UPDT; + r_icache_cc_word = r_cc_receive_word_idx.read(); + + // just pop the fifo , don't write in icache + r_icache_cc_need_write = false; + } + else // No response needed + { + r_cc_receive_icache_req = false; + r_icache_fsm = r_icache_fsm_save.read(); + } + } + break; + } + ///////////////////// + case ICACHE_CC_INVAL: // hit inval : switch slot to ZOMBI state + { + assert (not r_icache_cc_send_req.read() && + "ERROR in ICACHE_CC_INVAL: the r_icache_cc_send_req " + "must not be set"); + +#ifdef INSTRUMENTATION +m_cpt_icache_dir_read++; +#endif + + // Switch slot state to ZOMBI and send CLEANUP command + r_icache.write_dir( r_icache_cc_way.read(), + r_icache_cc_set.read(), + CACHE_SLOT_STATE_ZOMBI ); + + // coherence request completed + r_icache_cc_send_req = true; + r_icache_cc_send_nline = r_cc_receive_icache_nline.read(); + r_icache_cc_send_way = r_icache_cc_way.read(); + r_icache_cc_send_type = CC_TYPE_CLEANUP; + + r_icache_fsm = r_icache_fsm_save.read(); + +#if DEBUG_ICACHE +if ( m_debug_icache_fsm ) +{ +std::cout << " slot returns to ZOMBI state" + << " set = " << r_icache_cc_set.read() + << " / way = " << r_icache_cc_way.read() << std::endl; +} +#endif + + break; + } + //////////////////// + case ICACHE_CC_UPDT: // hit update : write one word per cycle + { + assert (not r_icache_cc_send_req.read() && + "ERROR in ICACHE_CC_UPDT: the r_icache_cc_send_req " + "must not be set"); + + if ( not r_cc_receive_updt_fifo_be.rok() ) break; + + + size_t word = r_icache_cc_word.read(); + size_t way = r_icache_cc_way.read(); + size_t set = r_icache_cc_set.read(); + + if (r_icache_cc_need_write.read()) + { + r_icache.write( way, + set, + word, + r_cc_receive_updt_fifo_data.read(), + r_cc_receive_updt_fifo_be.read() ); + + r_icache_cc_word = word+1; + +#ifdef INSTRUMENTATION +m_cpt_icache_data_write++; +#endif + +#if DEBUG_ICACHE +if ( m_debug_icache_fsm ) +{ + std::cout << " Write one word " + << " set = " << r_icache_cc_set.read() + << " / way = " << r_icache_cc_way.read() + << " / word = " << r_icache_cc_word.read() << std::endl; +} +#endif + } + + if ( r_cc_receive_updt_fifo_eop.read() ) // last word + { + // no need to write in the cache anymore + r_icache_cc_need_write = false; + + // coherence request completed + r_cc_receive_icache_req = false; + + // request multicast acknowledgement + r_icache_cc_send_req = true; + r_icache_cc_send_nline = r_cc_receive_icache_nline.read(); + r_icache_cc_send_updt_tab_idx = r_cc_receive_icache_updt_tab_idx.read(); + r_icache_cc_send_type = CC_TYPE_MULTI_ACK; + + r_icache_fsm = r_icache_fsm_save.read(); + } + //consume fifo if not eop + cc_receive_updt_fifo_get = true; + + break; + } + + } // end switch r_icache_fsm + + //////////////////////////////////////////////////////////////////////////////////// + // DCACHE FSM + // + // 1/ Coherence operations + // They are handled as interrupts generated by the CC_RECEIVE FSM. + // - There is a coherence request when r_tgt_dcache_req is set. + // They are taken in IDLE, MISS_WAIT, MISS_DIR_UPDT, UNC_WAIT, LL_WAIT + // and SC_WAIT states. + // - There is a cleanup acknowledge request when r_cleanup_dcache_req is set. + // They are taken in IDLE, MISS_SELECT, MISS_CLEAN, MISS_WAIT, MISS_DATA_UPDT, + // MISS_DIR_UPDT, UNC_WAIT, LL_WAIT, SC_WAIT states. + // - For both types of requests, actions associated to the pre-empted state + // are not executed. The DCACHE FSM goes to the proper sub-FSM (CC_CHECK + // or CC_CLACK) to execute the requested coherence operation, and returns + // to the pre-empted state. + // + // 2/ TLB miss + // The page tables are generally cacheable. + // In case of miss in itlb or dtlb, the tlb miss is handled by a dedicated + // sub-fsm (DCACHE_TLB_MISS state), that handle possible miss in DCACHE, + // this sub-fsm implement the table-walk... + // + // 3/ processor requests + // Processor requests are taken in IDLE state only. + // The IDLE state implements a two stages pipe-line to handle write bursts: + // - Both DTLB and DCACHE are accessed in stage P0 (if processor request valid). + // - The registration in wbuf and the dcache update is done in stage P1 + // (if the processor request is a write). + // The two r_dcache_wbuf_req and r_dcache_updt_req flip-flops define + // the operations that must be done in P1 stage, and the access type + // (read or write) to the DATA part of DCACHE depends on r_dcache_updt_req. + // READ requests are delayed if a cache update is requested. + // WRITE or SC requests can require a PTE Dirty bit update (in memory), + // that is done (before handling the processor request) by a dedicated sub-fsm. + // If a PTE is modified, both the itlb and dtlb are selectively, but sequencially + // cleared by a dedicated sub_fsm (DCACHE_INVAL_TLB_SCAN state). + // + // 4/ Atomic instructions LL/SC + // The LL/SC address are non cacheable (systematic access to memory). + // The llsc buffer contains a registration for an active LL/SC operation + // (with an address, a registration key, an aging counter and a valid bit). + // - LL requests from the processor are transmitted as a one flit VCI command + // (CMD_LOCKED_READ as CMD, and TYPE_LL as PKTID value). PLEN must + // be 8 as the response is 2 flits long (data and registration key) + // - SC requests from the processor are systematically transmitted to the + // memory cache as 2 flits VCI command (CMD_STORE_COND as CMD, and TYPE_SC + // as PKTID value). The first flit contains the registration key, the second + // flit contains the data to write in case of success. + // The cache is not updated, as this is done in case of success by the + // coherence transaction. + // + // 5/ Non cacheable access: + // This component implement a strong order between non cacheable access + // (read or write) : A new non cacheable VCI transaction starts only when + // the previous non cacheable transaction is completed. After send the VCI + // transaction, the DCACHE FSM wait for the respone in the DCACHE_UNC_WAIT state. + // So the processor is blocked until the respone arrives in CACHE L1. + // + // 6/ Error handling: + // When the MMU is not activated, Read Bus Errors are synchronous events, + // Some Write Bus Errors are synchronous events when the request is a non cacheable access + // but some Write Bus Errors are asynchronous events when the request is cacheable access + // (processor is not frozen). + // - If a Read Bus Error or a Non Cacheable Write Bus Error is detected, the VCI_RSP FSM sets the + // r_vci_rsp_data_error flip-flop, without writing any data in the + // r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled + // by the DCACHE FSM. + // - If a Cacheable Write Bus Error is detected, the VCI_RSP_FSM signals + // the asynchronous error using the setWriteBerr() method. + // When the MMU is activated bus error are rare events, as the MMU + // checks the physical address before the VCI transaction starts. + //////////////////////////////////////////////////////////////////////////////////////// + + // default value for m_drsp + m_drsp.valid = false; + m_drsp.error = false; + m_drsp.rdata = 0; + + switch ( r_dcache_fsm.read() ) + { + case DCACHE_IDLE: // There are 10 conditions to exit the IDLE state : + // 1) ITLB/DTLB inval request (update) => DCACHE_INVAL_TLB_SCAN + // 2) Coherence request (TGT FSM) => DCACHE_CC_CHECK + // 3) ITLB miss request (ICACHE FSM) => DCACHE_TLB_MISS + // 4) XTN request (processor) => DCACHE_XTN_* + // 5) DTLB miss (processor) => DCACHE_TLB_MISS + // 6) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE + // 7) Cacheable read miss (processor) => DCACHE_MISS_SELECT + // 8) Uncacheable read (processor) => DCACHE_UNC_WAIT + // 9) LL access (processor) => DCACHE_LL_WAIT + // 10) SC access (processor) => DCACHE_SC_WAIT + // + // There is a fixed priority to handle requests to DCACHE: + // 1/ the ITLB/DTLB invalidate requests + // 2/ the coherence requests, + // 3/ the processor requests (including DTLB miss), + // 4/ the ITLB miss requests, + // The address space processor request are handled as follows: + // - WRITE request is blocked if the Dirty bit mus be set. + // If DTLB hit, the P1 stage is activated (writes WBUF, and + // updates DCACHE if DCACHE hit) & processor request acknowledged. + // - READ request generate a simultaneouss access to DCACHE.DATA + // and DCACHE.DIR, but is delayed if DCACHE update required. + // + // There is 4 configurations defining the access type to + // DTLB, DCACHE.DATA, and DCACHE.DIR, depending on the + // dreq.valid (dreq) and r_dcache_updt_req (updt) signals: + // dreq / updt / DTLB / DCACHE.DIR / DCACHE.DATA / + // 0 / 0 / NOP / NOP / NOP / + // 0 / 1 / NOP / NOP / WRITE / + // 1 / 0 / READ / READ / NOP / + // 1 / 1 / READ / READ / WRITE / + // Those two registers are set at each cycle from the 3 signals + // updt_request, wbuf_request, wbuf_write_miss. + { + paddr_t paddr; // physical address + pte_info_t tlb_flags; + size_t tlb_way; + size_t tlb_set; + paddr_t tlb_nline = 0; + size_t cache_way; + size_t cache_set; + size_t cache_word; + uint32_t cache_rdata = 0; + bool tlb_hit = false; + int cache_state = CACHE_SLOT_STATE_EMPTY; + + bool tlb_inval_required = false; // request TLB inval after cache update + bool wbuf_write_miss = false; // miss a WBUF write request + bool updt_request = false; // request DCACHE update in P1 stage + bool wbuf_request = false; // request WBUF write in P1 stage + + // physical address computation : systematic DTLB access if activated) + if ( m_dreq.valid ) + { + if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated + { + tlb_hit = r_dtlb.translate( m_dreq.addr, + &paddr, + &tlb_flags, + &tlb_nline, + &tlb_way, + &tlb_set ); +#ifdef INSTRUMENTATION +m_cpt_dtlb_read++; +#endif + } + else // identity mapping + { + paddr = (paddr_t)m_dreq.addr; + // we take into account the paddr extension + if (vci_param::N > 32) + paddr = paddr | ((paddr_t)(r_dcache_paddr_ext.read()) << 32); + } + } // end physical address computation + + // systematic DCACHE access depending on r_dcache_updt_req (if activated) + if ( r_mmu_mode.read() & DATA_CACHE_MASK) + { + if ( m_dreq.valid and r_dcache_updt_req.read() ) // read DIR and write DATA + { + r_dcache.read_dir( paddr, + &cache_state, + &cache_way, + &cache_set, + &cache_word ); + + r_dcache.write( r_dcache_save_cache_way.read(), + r_dcache_save_cache_set.read(), + r_dcache_save_cache_word.read(), + r_dcache_save_wdata.read(), + r_dcache_save_be.read() ); +#ifdef INSTRUMENTATION +m_cpt_dcache_dir_read++; +m_cpt_dcache_data_write++; +#endif + } + else if ( m_dreq.valid and not r_dcache_updt_req.read() ) // read DIR and DATA + { + r_dcache.read( paddr, + &cache_rdata, + &cache_way, + &cache_set, + &cache_word, + &cache_state ); + +#ifdef INSTRUMENTATION +m_cpt_dcache_dir_read++; +m_cpt_dcache_data_read++; +#endif + } + else if ( not m_dreq.valid and r_dcache_updt_req.read() ) // write DATA + { + r_dcache.write( r_dcache_save_cache_way.read(), + r_dcache_save_cache_set.read(), + r_dcache_save_cache_word.read(), + r_dcache_save_wdata.read(), + r_dcache_save_be.read() ); +#ifdef INSTRUMENTATION +m_cpt_dcache_data_write++; +#endif + } + } // end dcache access + + // DCACHE update in P1 stage can require ITLB / DTLB inval or flush + if ( r_dcache_updt_req.read() ) + { + size_t way = r_dcache_save_cache_way.read(); + size_t set = r_dcache_save_cache_set.read(); + + if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) + { + tlb_inval_required = true; + r_dcache_tlb_inval_set = 0; + r_dcache_tlb_inval_line = r_dcache_save_paddr.read()>> + (uint32_log2(m_dcache_words<<2)); + r_dcache_in_tlb[way*m_dcache_sets+set] = false; + } + else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) + { + r_itlb.reset(); + r_dtlb.reset(); + r_dcache_contains_ptd[way*m_dcache_sets+set] = false; + } + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +std::cout << " " + << " Cache update in P1 stage" << std::dec + << " / WAY = " << r_dcache_save_cache_way.read() + << " / SET = " << r_dcache_save_cache_set.read() + << " / WORD = " << r_dcache_save_cache_word.read() << std::hex + << " / WDATA = " << r_dcache_save_wdata.read() + << " / BE = " << r_dcache_save_be.read() << std::endl; +#endif + } // end test TLB inval + + // Try WBUF update in P1 stage + // Miss if the write request is non cacheable, and there is a pending + // non cacheable write, or if the write buffer is full. + if ( r_dcache_wbuf_req.read() ) + { + bool wok = r_wbuf.write( r_dcache_save_paddr.read(), + r_dcache_save_be.read(), + r_dcache_save_wdata.read(), + true); +#ifdef INSTRUMENTATION +m_cpt_wbuf_write++; +#endif + if ( not wok ) // miss if write buffer full + { + wbuf_write_miss = true; + } + } // end WBUF update + + // Computing the response to processor, + // and the next value for r_dcache_fsm + + // itlb/dtlb invalidation self-request + if ( tlb_inval_required ) + { + r_dcache_fsm_scan_save = r_dcache_fsm.read(); + r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; + } + + // coherence clack request (from DSPIN CLACK) + else if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + } + // coherence request (from CC_RECEIVE FSM) + else if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + } + + // processor request (READ, WRITE, LL, SC, XTN_READ, XTN_WRITE) + // we don't take the processor request, and registers + // are frozen in case of wbuf_write_miss + else if ( m_dreq.valid and not wbuf_write_miss ) + { + // register processor request and DCACHE response + r_dcache_save_vaddr = m_dreq.addr; + r_dcache_save_be = m_dreq.be; + r_dcache_save_wdata = m_dreq.wdata; + r_dcache_save_paddr = paddr; + r_dcache_save_cache_way = cache_way; + r_dcache_save_cache_set = cache_set; + r_dcache_save_cache_word = cache_word; + + // READ XTN requests from processor + // They are executed in this DCACHE_IDLE state. + // The processor must not be in user mode + if (m_dreq.type == iss_t::XTN_READ) + { + int xtn_opcode = (int)m_dreq.addr/4; + + // checking processor mode: + if (m_dreq.mode == iss_t::MODE_USER) + { + r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION; + r_mmu_dbvar = m_dreq.addr; + m_drsp.valid = true; + m_drsp.error = true; + m_drsp.rdata = 0; + r_dcache_fsm = DCACHE_IDLE; + } + else + { + switch( xtn_opcode ) + { + case iss_t::XTN_INS_ERROR_TYPE: + m_drsp.rdata = r_mmu_ietr.read(); + m_drsp.valid = true; + m_drsp.error = false; + break; + + case iss_t::XTN_DATA_ERROR_TYPE: + m_drsp.rdata = r_mmu_detr.read(); + m_drsp.valid = true; + m_drsp.error = false; + break; + + case iss_t::XTN_INS_BAD_VADDR: + m_drsp.rdata = r_mmu_ibvar.read(); + m_drsp.valid = true; + m_drsp.error = false; + break; + + case iss_t::XTN_DATA_BAD_VADDR: + m_drsp.rdata = r_mmu_dbvar.read(); + m_drsp.valid = true; + m_drsp.error = false; + break; + + case iss_t::XTN_PTPR: + m_drsp.rdata = r_mmu_ptpr.read(); + m_drsp.valid = true; + m_drsp.error = false; + break; + + case iss_t::XTN_TLB_MODE: + m_drsp.rdata = r_mmu_mode.read(); + m_drsp.valid = true; + m_drsp.error = false; + break; + + case iss_t::XTN_MMU_PARAMS: + m_drsp.rdata = r_mmu_params; + m_drsp.valid = true; + m_drsp.error = false; + break; + + case iss_t::XTN_MMU_RELEASE: + m_drsp.rdata = r_mmu_release; + m_drsp.valid = true; + m_drsp.error = false; + break; + + case iss_t::XTN_MMU_WORD_LO: + m_drsp.rdata = r_mmu_word_lo.read(); + m_drsp.valid = true; + m_drsp.error = false; + break; + + case iss_t::XTN_MMU_WORD_HI: + m_drsp.rdata = r_mmu_word_hi.read(); + m_drsp.valid = true; + m_drsp.error = false; + break; + + case iss_t::XTN_DATA_PADDR_EXT: + m_drsp.rdata = r_dcache_paddr_ext.read(); + m_drsp.valid = true; + m_drsp.error = false; + break; + + case iss_t::XTN_INST_PADDR_EXT: + m_drsp.rdata = r_icache_paddr_ext.read(); + m_drsp.valid = true; + m_drsp.error = false; + break; + + default: + r_mmu_detr = MMU_READ_UNDEFINED_XTN; + r_mmu_dbvar = m_dreq.addr; + m_drsp.valid = true; + m_drsp.error = true; + m_drsp.rdata = 0; + break; + } // end switch xtn_opcode + } // end else + } // end if XTN_READ + + // Handling WRITE XTN requests from processor. + // They are not executed in this DCACHE_IDLE state + // if they require access to the caches or the TLBs + // that are already accessed. + // Caches can be invalidated or flushed in user mode, + // and the sync instruction can be executed in user mode + else if (m_dreq.type == iss_t::XTN_WRITE) + { + int xtn_opcode = (int)m_dreq.addr/4; + r_dcache_xtn_opcode = xtn_opcode; + + // checking processor mode: + if ( (m_dreq.mode == iss_t::MODE_USER) && + (xtn_opcode != iss_t::XTN_SYNC) && + (xtn_opcode != iss_t::XTN_DCACHE_INVAL) && + (xtn_opcode != iss_t::XTN_DCACHE_FLUSH) && + (xtn_opcode != iss_t::XTN_ICACHE_INVAL) && + (xtn_opcode != iss_t::XTN_ICACHE_FLUSH) ) + { + r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION; + r_mmu_dbvar = m_dreq.addr; + m_drsp.valid = true; + m_drsp.error = true; + m_drsp.rdata = 0; + r_dcache_fsm = DCACHE_IDLE; + } + else + { + switch( xtn_opcode ) + { + case iss_t::XTN_PTPR: // itlb & dtlb must be flushed + r_dcache_xtn_req = true; + r_dcache_fsm = DCACHE_XTN_SWITCH; + break; + + case iss_t::XTN_TLB_MODE: // no cache or tlb access + r_mmu_mode = m_dreq.wdata; + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; + break; + + case iss_t::XTN_DTLB_INVAL: // dtlb access + r_dcache_fsm = DCACHE_XTN_DT_INVAL; + break; + + case iss_t::XTN_ITLB_INVAL: // itlb access + r_dcache_xtn_req = true; + r_dcache_fsm = DCACHE_XTN_IT_INVAL; + break; + + case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access + r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA; + break; + + case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access + r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA; + if (sizeof(paddr_t) <= 32) + { + assert(r_mmu_word_hi.read() == 0 && + "high bits should be 0 for 32bit paddr"); + r_dcache_save_paddr = (paddr_t)r_mmu_word_lo.read(); + } + else + { + r_dcache_save_paddr = (paddr_t)r_mmu_word_hi.read() << 32 | + (paddr_t)r_mmu_word_lo.read(); + } + break; + + case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset + r_dcache_flush_count = 0; + r_dcache_fsm = DCACHE_XTN_DC_FLUSH; + break; + + case iss_t::XTN_ICACHE_INVAL: // icache and itlb access + r_dcache_xtn_req = true; + r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA; + break; + + case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access + r_dcache_xtn_req = true; + r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA; + break; + + case iss_t::XTN_ICACHE_FLUSH: // icache access + r_dcache_xtn_req = true; + r_dcache_fsm = DCACHE_XTN_IC_FLUSH; + break; + + case iss_t::XTN_SYNC: // wait until write buffer empty + r_dcache_fsm = DCACHE_XTN_SYNC; + break; + + case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access + r_mmu_word_lo = m_dreq.wdata; + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; + break; + + case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access + r_mmu_word_hi = m_dreq.wdata; + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; + break; + + case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access + r_dcache_llsc_valid = false; + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; + break; + + case iss_t::XTN_DATA_PADDR_EXT: // no cache or tlb access + r_dcache_paddr_ext = m_dreq.wdata; + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; + break; + + case iss_t::XTN_INST_PADDR_EXT: // no cache or tlb access + r_dcache_xtn_req = true; + r_dcache_fsm = DCACHE_XTN_IC_PADDR_EXT; + break; + + case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action + case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; + break; + + case iss_t::XTN_DEBUG_MASK: // debug mask + m_debug_dcache_fsm = ((m_dreq.wdata & 0x1) != 0); + m_debug_icache_fsm = ((m_dreq.wdata & 0x2) != 0); + m_debug_cmd_fsm = ((m_dreq.wdata & 0x4) != 0); + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; + break; + + default: + r_mmu_detr = MMU_WRITE_UNDEFINED_XTN; + r_mmu_dbvar = m_dreq.addr; + m_drsp.valid = true; + m_drsp.error = true; + r_dcache_fsm = DCACHE_IDLE; + break; + } // end switch xtn_opcode + } // end else + } // end if XTN_WRITE + + // Handling processor requests to address space (READ/WRITE/LL/SC) + // The dtlb and dcache can be activated or not. + // We compute the cacheability, and check processor request validity: + // - If DTLB not activated : cacheability is defined by the segment table, + // and there is no access rights checking. + // - If DTLB activated : cacheability is defined by the C bit in the PTE, + // and the U & W bits of the PTE are checked, as well as the DTLB hit. + // Jumps to the TLB_MISS sub-fsm in case of dtlb miss. + else + { + bool valid_req; + bool cacheable; + + if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated + { + valid_req = true; + + if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false; + else cacheable = m_cacheability_table[(uint64_t)m_dreq.addr]; + } + else // dtlb activated + { + if ( tlb_hit ) // tlb hit + { + // cacheability + if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false; + else cacheable = tlb_flags.c; + + // access rights checking + if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER)) + { + if ( (m_dreq.type == iss_t::DATA_READ) or + (m_dreq.type == iss_t::DATA_LL) ) + { + r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION; + } + else + { + r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION; + } + valid_req = false; + r_mmu_dbvar = m_dreq.addr; + m_drsp.valid = true; + m_drsp.error = true; + m_drsp.rdata = 0; +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +std::cout << " " + << " HIT in dtlb, but privilege violation" << std::endl; +#endif + } + else if ( not tlb_flags.w and + ((m_dreq.type == iss_t::DATA_WRITE) or + (m_dreq.type == iss_t::DATA_SC)) ) + { + r_mmu_detr = MMU_WRITE_ACCES_VIOLATION; + valid_req = false; + r_mmu_dbvar = m_dreq.addr; + m_drsp.valid = true; + m_drsp.error = true; + m_drsp.rdata = 0; +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +std::cout << " " + << " HIT in dtlb, but writable violation" << std::endl; +#endif + } + else + { + valid_req = true; + } + } + else // tlb miss + { + valid_req = false; + r_dcache_tlb_vaddr = m_dreq.addr; + r_dcache_tlb_ins = false; + r_dcache_fsm = DCACHE_TLB_MISS; + } + } // end DTLB activated + + if ( valid_req ) // processor request is valid (after MMU check) + { + // READ request + // The read requests are taken only if there is no cache update. + // We request a VCI transaction to CMD FSM if miss or uncachable + + if ( ((m_dreq.type == iss_t::DATA_READ)) + and not r_dcache_updt_req.read() ) + { + if ( cacheable ) // cacheable read + { + if ( cache_state == CACHE_SLOT_STATE_EMPTY ) // cache miss + { +#ifdef INSTRUMENTATION +m_cpt_dcache_miss++; +#endif + // request a VCI DMISS transaction + r_dcache_vci_paddr = paddr; + r_dcache_vci_miss_req = true; + r_dcache_miss_type = PROC_MISS; + r_dcache_fsm = DCACHE_MISS_SELECT; +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +std::cout << " " + << " READ MISS in dcache" + << " / PADDR = " << std::hex << paddr << std::endl; +#endif + } + else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup + { + // stalled until cleanup is acknowledged + r_dcache_fsm = DCACHE_IDLE; +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +std::cout << " " + << " Pending cleanup, stalled until cleanup acknowledge" + << " / PADDR = " << std::hex << paddr << std::endl; +#endif + } + else // cache hit + { +#ifdef INSTRUMENTATION +m_cpt_data_read++; +#endif + // returns data to processor + m_drsp.valid = true; + m_drsp.error = false; + m_drsp.rdata = cache_rdata; +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +std::cout << " " + << " READ HIT in dcache" + << " : PADDR = " << std::hex << paddr + << " / DATA = " << std::hex << cache_rdata << std::endl; +#endif + } + } + else // uncacheable read + { + r_dcache_vci_paddr = paddr; + r_dcache_vci_unc_be = m_dreq.be; + r_dcache_vci_unc_write = false; + r_dcache_vci_unc_req = true; + r_dcache_fsm = DCACHE_UNC_WAIT; +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +std::cout << " " + << " READ UNCACHEABLE in dcache" + << " / PADDR = " << std::hex << paddr << std::endl; +#endif + } + } // end READ + + // LL request (non cachable) + // We request a VCI LL transaction to CMD FSM and register + // the LL/SC operation in llsc buffer. + else if (m_dreq.type == iss_t::DATA_LL) + { + // register paddr in LLSC buffer + r_dcache_llsc_paddr = paddr; + r_dcache_llsc_count = LLSC_TIMEOUT; + r_dcache_llsc_valid = true; + + // request an LL VCI transaction and go to DCACHE_LL_WAIT state + r_dcache_vci_ll_req = true; + r_dcache_vci_paddr = paddr; + r_dcache_ll_rsp_count = 0; + r_dcache_fsm = DCACHE_LL_WAIT; + + }// end LL + + // WRITE request: + // If the TLB is activated and the PTE Dirty bit is not set, we stall + // the processor and set the Dirty bit before handling the write request, + // going to the DCACHE_DIRTY_GT_PTE state. + // If we don't need to set the Dirty bit, we can acknowledge + // the processor request, as the write arguments (including the + // physical address) are registered in r_dcache_save registers, + // and the write will be done in the P1 pipeline stage. + else if ( m_dreq.type == iss_t::DATA_WRITE ) + { + if ( (r_mmu_mode.read() & DATA_TLB_MASK ) + and not tlb_flags.d ) // Dirty bit must be set + { + // The PTE physical address is obtained from the nline value (dtlb), + // and from the virtual address (word index) + if ( tlb_flags.b ) // PTE1 + { + r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) | + (paddr_t)((m_dreq.addr>>19) & 0x3c); + } + else // PTE2 + { + r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) | + (paddr_t)((m_dreq.addr>>9) & 0x38); + } + r_dcache_fsm = DCACHE_DIRTY_GET_PTE; + } + else // Write request accepted + { +#ifdef INSTRUMENTATION +m_cpt_data_write++; +#endif + // cleaning llsc buffer if address matching + if ( paddr == r_dcache_llsc_paddr.read() ) + r_dcache_llsc_valid = false; + + if (not cacheable) + { + r_dcache_vci_paddr = paddr; + r_dcache_vci_wdata = m_dreq.wdata; + r_dcache_vci_unc_write = true; + r_dcache_vci_unc_be = m_dreq.be; + r_dcache_vci_unc_req = true; + r_dcache_fsm = DCACHE_UNC_WAIT; + } + else + { + // response to processor + m_drsp.valid = true; + // activating P1 stage + wbuf_request = true; + updt_request = (cache_state == CACHE_SLOT_STATE_VALID); + } + } + } // end WRITE + + // SC request: + // If the TLB is activated and the PTE Dirty bit is not set, we stall + // the processor and set the Dirty bit before handling the write request, + // going to the DCACHE_DIRTY_GT_PTE state. + // If we don't need to set the Dirty bit, we test the llsc buffer: + // If failure, we send a negative response to processor. + // If success, we request a SC transaction to CMD FSM and go + // to DCACHE_SC_WAIT state. + // We don't check a possible write hit in dcache, as the cache update + // is done by the coherence transaction induced by the SC... + else if ( m_dreq.type == iss_t::DATA_SC ) + { + if ( (r_mmu_mode.read() & DATA_TLB_MASK ) + and not tlb_flags.d ) // Dirty bit must be set + { + // The PTE physical address is obtained from the nline value (dtlb), + // and the word index (virtual address) + if ( tlb_flags.b ) // PTE1 + { + r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) | + (paddr_t)((m_dreq.addr>>19) & 0x3c); + } + else // PTE2 + { + r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) | + (paddr_t)((m_dreq.addr>>9) & 0x38); + } + r_dcache_fsm = DCACHE_DIRTY_GET_PTE; + m_drsp.valid = false; + m_drsp.error = false; + m_drsp.rdata = 0; + } + else // SC request accepted + { +#ifdef INSTRUMENTATION +m_cpt_data_sc++; +#endif + // checking local success + if( r_dcache_llsc_valid.read() and + (r_dcache_llsc_paddr.read() == paddr) ) // local success + { + // request an SC CMD and go to DCACHE_SC_WAIT state + r_dcache_vci_paddr = paddr; + r_dcache_vci_sc_req = true; + r_dcache_vci_sc_data = m_dreq.wdata; + r_dcache_fsm = DCACHE_SC_WAIT; + } + else // local fail + { + m_drsp.valid = true; + m_drsp.error = false; + m_drsp.rdata = 0x1; + } + } + } // end SC + } // end valid_req + } // end if read/write/ll/sc request + } // end processor request + + // itlb miss request + else if ( r_icache_tlb_miss_req.read() and not wbuf_write_miss ) + { + r_dcache_tlb_ins = true; + r_dcache_tlb_vaddr = r_icache_vaddr_save.read(); + r_dcache_fsm = DCACHE_TLB_MISS; + } + + // Computing requests for P1 stage : r_dcache_wbuf_req & r_dcache_updt_req + r_dcache_updt_req = updt_request; + r_dcache_wbuf_req = wbuf_request or + (r_dcache_wbuf_req.read() and wbuf_write_miss); + break; + } + ///////////////////// + case DCACHE_TLB_MISS: // This is the entry point for the sub-fsm handling all tlb miss. + // Input arguments are: + // - r_dcache_tlb_vaddr + // - r_dcache_tlb_ins (true when itlb miss) + // The sub-fsm access the dcache to find the missing TLB entry, + // and activates the cache miss procedure in case of miss. + // It bypass the first level page table access if possible. + // It uses atomic access to update the R/L access bits + // in the page table if required. + // It directly updates the itlb or dtlb, and writes into the + // r_mmu_ins_* or r_mmu_data* error reporting registers. + { + uint32_t ptba = 0; + bool bypass; + paddr_t pte_paddr; + + // evaluate bypass in order to skip first level page table access + if ( r_dcache_tlb_ins.read() ) // itlb miss + { + bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba); + } + else // dtlb miss + { + bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba); + } + + if ( not bypass ) // Try to read PTE1/PTD1 in dcache + { + pte_paddr = (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2)) | + ((((paddr_t)r_dcache_tlb_vaddr.read()) >> PAGE_M_NBITS) << 2); + r_dcache_tlb_paddr = pte_paddr; + r_dcache_fsm = DCACHE_TLB_PTE1_GET; + } + else // Try to read PTE2 in dcache + { + pte_paddr = (paddr_t)ptba << PAGE_K_NBITS | + (paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3); + r_dcache_tlb_paddr = pte_paddr; + r_dcache_fsm = DCACHE_TLB_PTE2_GET; + } + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + if ( r_dcache_tlb_ins.read() ) + std::cout << " ITLB miss"; + else + std::cout << " DTLB miss"; + std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read() + << " / ptpr = " << (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2)) + << " / BYPASS = " << bypass + << " / PTE_ADR = " << pte_paddr << std::endl; +} +#endif + + break; + } + ///////////////////////// + case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache + { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + uint32_t entry; + size_t way; + size_t set; + size_t word; + int cache_state; + r_dcache.read( r_dcache_tlb_paddr.read(), + &entry, + &way, + &set, + &word, + &cache_state ); +#ifdef INSTRUMENTATION +m_cpt_dcache_data_read++; +m_cpt_dcache_dir_read++; +#endif + if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache + { + if ( not (entry & PTE_V_MASK) ) // unmapped + { + if ( r_dcache_tlb_ins.read() ) + { + r_mmu_ietr = MMU_READ_PT1_UNMAPPED; + r_mmu_ibvar = r_dcache_tlb_vaddr.read(); + r_icache_tlb_miss_req = false; + r_icache_tlb_rsp_error = true; + } + else + { + r_mmu_detr = MMU_READ_PT1_UNMAPPED; + r_mmu_dbvar = r_dcache_tlb_vaddr.read(); + m_drsp.valid = true; + m_drsp.error = true; + } + r_dcache_fsm = DCACHE_IDLE; + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " HIT in dcache, but unmapped" + << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() + << std::dec << " / way = " << way + << std::dec << " / set = " << set + << std::dec << " / word = " << word + << std::hex << " / PTE1 = " << entry << std::endl; +} +#endif + + } + else if( entry & PTE_T_MASK ) // PTD : me must access PT2 + { + // mark the cache line ac containing a PTD + r_dcache_contains_ptd[m_dcache_sets*way+set] = true; + + // register bypass + if ( r_dcache_tlb_ins.read() ) // itlb + { + r_itlb.set_bypass(r_dcache_tlb_vaddr.read(), + entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1), + r_dcache_tlb_paddr.read() / (m_icache_words<<2) ); + } + else // dtlb + { + r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(), + entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1), + r_dcache_tlb_paddr.read() / (m_dcache_words<<2) ); + } + r_dcache_tlb_paddr = + (paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS | + (paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); + r_dcache_fsm = DCACHE_TLB_PTE2_GET; + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " HIT in dcache" + << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() + << std::dec << " / way = " << way + << std::dec << " / set = " << set + << std::dec << " / word = " << word + << std::hex << " / PTD = " << entry << std::endl; +} +#endif + } + else // PTE1 : we must update the TLB + { + r_dcache_in_tlb[m_icache_sets*way+set] = true; + r_dcache_tlb_pte_flags = entry; + r_dcache_tlb_cache_way = way; + r_dcache_tlb_cache_set = set; + r_dcache_tlb_cache_word = word; + r_dcache_fsm = DCACHE_TLB_PTE1_SELECT; + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " HIT in dcache" + << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() + << std::dec << " / way = " << way + << std::dec << " / set = " << set + << std::dec << " / word = " << word + << std::hex << " / PTE1 = " << entry << std::endl; +} +#endif + } + } + else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup + { + // stalled until cleanup is acknowledged + r_dcache_fsm = DCACHE_TLB_PTE1_GET; + } + else // we must load the missing cache line in dcache + { + r_dcache_vci_miss_req = true; + r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); + r_dcache_save_paddr = r_dcache_tlb_paddr.read(); + r_dcache_miss_type = PTE1_MISS; + r_dcache_fsm = DCACHE_MISS_SELECT; + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " MISS in dcache:" + << " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl; +} +#endif + } + break; + } + //////////////////////////// + case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1 + { + size_t way; + size_t set; + + if ( r_dcache_tlb_ins.read() ) + { + r_itlb.select( r_dcache_tlb_vaddr.read(), + true, // PTE1 + &way, + &set ); +#ifdef INSTRUMENTATION +m_cpt_itlb_read++; +#endif + } + else + { + r_dtlb.select( r_dcache_tlb_vaddr.read(), + true, // PTE1 + &way, + &set ); +#ifdef INSTRUMENTATION +m_cpt_dtlb_read++; +#endif + } + r_dcache_tlb_way = way; + r_dcache_tlb_set = set; + r_dcache_fsm = DCACHE_TLB_PTE1_UPDT; + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + if ( r_dcache_tlb_ins.read() ) + std::cout << " Select a slot in ITLB:"; + else + std::cout << " Select a slot in DTLB:"; + std::cout << " way = " << std::dec << way + << " / set = " << set << std::endl; +} +#endif + break; + } + ////////////////////////// + case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit + // - if L/R bit already set, exit the sub-fsm. + // - if not, we update the page table but we dont write + // neither in DCACHE, nor in TLB, as this will be done by + // the coherence mechanism. + { + paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2); + uint32_t pte = r_dcache_tlb_pte_flags.read(); + bool pt_updt = false; + bool local = true; + + // We should compute the access locality: + // The PPN MSB bits define the destination cluster index. + // The m_srcid MSB bits define the source cluster index. + // The number of bits to compare depends on the number of clusters, + // and can be obtained in the mapping table. + // As long as this computation is not done, all access are local. + + if ( local ) // local access + { + if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit + { + pt_updt = true; + r_dcache_vci_cas_old = pte; + r_dcache_vci_cas_new = pte | PTE_L_MASK; + pte = pte | PTE_L_MASK; + r_dcache_tlb_pte_flags = pte; + } + } + else // remote access + { + if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit + { + pt_updt = true; + r_dcache_vci_cas_old = pte; + r_dcache_vci_cas_new = pte | PTE_R_MASK; + pte = pte | PTE_R_MASK; + r_dcache_tlb_pte_flags = pte; + } + } + + if ( not pt_updt ) // update TLB and return + { + if ( r_dcache_tlb_ins.read() ) + { + r_itlb.write( true, // 2M page + pte, + 0, // argument unused for a PTE1 + r_dcache_tlb_vaddr.read(), + r_dcache_tlb_way.read(), + r_dcache_tlb_set.read(), + nline ); +#ifdef INSTRUMENTATION +m_cpt_itlb_write++; +#endif + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " write PTE1 in ITLB" + << " / set = " << std::dec << r_dcache_tlb_set.read() + << " / way = " << r_dcache_tlb_way.read() << std::endl; + r_itlb.printTrace(); +} +#endif + } + else + { + r_dtlb.write( true, // 2M page + pte, + 0, // argument unused for a PTE1 + r_dcache_tlb_vaddr.read(), + r_dcache_tlb_way.read(), + r_dcache_tlb_set.read(), + nline ); +#ifdef INSTRUMENTATION +m_cpt_dtlb_write++; +#endif + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " write PTE1 in DTLB" + << " / set = " << std::dec << r_dcache_tlb_set.read() + << " / way = " << r_dcache_tlb_way.read() << std::endl; + r_dtlb.printTrace(); +} +#endif + } + r_dcache_fsm = DCACHE_TLB_RETURN; + } + else // update page table but not TLB + { + r_dcache_fsm = DCACHE_TLB_LR_UPDT; + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " L/R bit update required" + << std::endl; +} +#endif + } + break; + } + ///////////////////////// + case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache + { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + uint32_t pte_flags; + uint32_t pte_ppn; + size_t way; + size_t set; + size_t word; + int cache_state; + + r_dcache.read( r_dcache_tlb_paddr.read(), + &pte_flags, + &pte_ppn, + &way, + &set, + &word, + &cache_state ); +#ifdef INSTRUMENTATION +m_cpt_dcache_data_read++; +m_cpt_dcache_dir_read++; +#endif + if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache + { + if ( not (pte_flags & PTE_V_MASK) ) // unmapped + { + if ( r_dcache_tlb_ins.read() ) + { + r_mmu_ietr = MMU_READ_PT2_UNMAPPED; + r_mmu_ibvar = r_dcache_tlb_vaddr.read(); + r_icache_tlb_miss_req = false; + r_icache_tlb_rsp_error = true; + } + else + { + r_mmu_detr = MMU_READ_PT2_UNMAPPED; + r_mmu_dbvar = r_dcache_tlb_vaddr.read(); + m_drsp.valid = true; + m_drsp.error = true; + } + r_dcache_fsm = DCACHE_IDLE; + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " HIT in dcache, but PTE unmapped" + << " PTE_FLAGS = " << std::hex << pte_flags + << " PTE_PPN = " << std::hex << pte_ppn << std::endl; +} +#endif + } + else // mapped : we must update the TLB + { + r_dcache_in_tlb[m_dcache_sets*way+set] = true; + r_dcache_tlb_pte_flags = pte_flags; + r_dcache_tlb_pte_ppn = pte_ppn; + r_dcache_tlb_cache_way = way; + r_dcache_tlb_cache_set = set; + r_dcache_tlb_cache_word = word; + r_dcache_fsm = DCACHE_TLB_PTE2_SELECT; + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " HIT in dcache:" + << " PTE_FLAGS = " << std::hex << pte_flags + << " PTE_PPN = " << std::hex << pte_ppn << std::endl; +} +#endif + } + } + else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup + { + // stalled until cleanup is acknowledged + r_dcache_fsm = DCACHE_TLB_PTE2_GET; + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " ZOMBI in dcache: waiting cleanup ack" + << std::endl; +} +#endif + } + else // we must load the missing cache line in dcache + { + r_dcache_fsm = DCACHE_MISS_SELECT; + r_dcache_vci_miss_req = true; + r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); + r_dcache_save_paddr = r_dcache_tlb_paddr.read(); + r_dcache_miss_type = PTE2_MISS; + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " MISS in dcache:" + << " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl; +} +#endif + } + break; + } + //////////////////////////// + case DCACHE_TLB_PTE2_SELECT: // select a slot for PTE2 + { + size_t way; + size_t set; + + if ( r_dcache_tlb_ins.read() ) + { + r_itlb.select( r_dcache_tlb_vaddr.read(), + false, // PTE2 + &way, + &set ); +#ifdef INSTRUMENTATION +m_cpt_itlb_read++; +#endif + } + else + { + r_dtlb.select( r_dcache_tlb_vaddr.read(), + false, // PTE2 + &way, + &set ); +#ifdef INSTRUMENTATION +m_cpt_dtlb_read++; +#endif + } + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + if ( r_dcache_tlb_ins.read() ) + std::cout << " Select a slot in ITLB:"; + else + std::cout << " Select a slot in DTLB:"; + std::cout << " way = " << std::dec << way + << " / set = " << set << std::endl; +} +#endif + r_dcache_tlb_way = way; + r_dcache_tlb_set = set; + r_dcache_fsm = DCACHE_TLB_PTE2_UPDT; + break; + } + ////////////////////////// + case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit + // - if L/R bit already set, exit the sub-fsm. + // - if not, we update the page table but we dont write + // neither in DCACHE, nor in TLB, as this will be done by + // the coherence mechanism. + { + paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2); + uint32_t pte_flags = r_dcache_tlb_pte_flags.read(); + uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read(); + bool pt_updt = false; + bool local = true; + + // We should compute the access locality: + // The PPN MSB bits define the destination cluster index. + // The m_srcid MSB bits define the source cluster index. + // The number of bits to compare depends on the number of clusters, + // and can be obtained in the mapping table. + // As long as this computation is not done, all access are local. + + if ( local ) // local access + { + if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit + { + pt_updt = true; + r_dcache_vci_cas_old = pte_flags; + r_dcache_vci_cas_new = pte_flags | PTE_L_MASK; + pte_flags = pte_flags | PTE_L_MASK; + r_dcache_tlb_pte_flags = pte_flags; + } + } + else // remote access + { + if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit + { + pt_updt = true; + r_dcache_vci_cas_old = pte_flags; + r_dcache_vci_cas_new = pte_flags | PTE_R_MASK; + pte_flags = pte_flags | PTE_R_MASK; + r_dcache_tlb_pte_flags = pte_flags; + } + } + + if ( not pt_updt ) // update TLB + { + if ( r_dcache_tlb_ins.read() ) + { + r_itlb.write( false, // 4K page + pte_flags, + pte_ppn, + r_dcache_tlb_vaddr.read(), + r_dcache_tlb_way.read(), + r_dcache_tlb_set.read(), + nline ); +#ifdef INSTRUMENTATION +m_cpt_itlb_write++; +#endif + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " write PTE2 in ITLB" + << " / set = " << std::dec << r_dcache_tlb_set.read() + << " / way = " << r_dcache_tlb_way.read() << std::endl; + r_itlb.printTrace(); +} +#endif + } + else + { + r_dtlb.write( false, // 4K page + pte_flags, + pte_ppn, + r_dcache_tlb_vaddr.read(), + r_dcache_tlb_way.read(), + r_dcache_tlb_set.read(), + nline ); +#ifdef INSTRUMENTATION +m_cpt_dtlb_write++; +#endif + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " write PTE2 in DTLB" + << " / set = " << std::dec << r_dcache_tlb_set.read() + << " / way = " << r_dcache_tlb_way.read() << std::endl; + r_dtlb.printTrace(); +} +#endif + + } + r_dcache_fsm = DCACHE_TLB_RETURN; + } + else // update page table but not TLB + { + r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " L/R bit update required" << std::endl; +} +#endif + } + break; + } + //////////////////////// + case DCACHE_TLB_LR_UPDT: // request a CAS transaction to update L/R bit + { +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " Update dcache: (L/R) bit" << std::endl; +} +#endif + // r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set + r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); + + // checking llsc reservation buffer + if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() ) + r_dcache_llsc_valid = false; + + // request a CAS CMD and go to DCACHE_TLB_LR_WAIT state + r_dcache_vci_cas_req = true; + r_dcache_fsm = DCACHE_TLB_LR_WAIT; + break; + } + //////////////////////// + case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit. + // We consume the response in rsp FIFO, + // and exit the sub-fsm, but we don't + // analyse the response, because we don't + // care if the L/R bit update is not done. + // We must take the coherence requests because + // there is a risk of dead-lock + + { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + if ( r_vci_rsp_data_error.read() ) // bus error + { + std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl; + std::cout << "This should not happen in this state" << std::endl; + exit(0); + } + else if ( r_vci_rsp_fifo_dcache.rok() ) // response available + { +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " SC response received" << std::endl; +} +#endif + vci_rsp_fifo_dcache_get = true; + r_dcache_fsm = DCACHE_TLB_RETURN; + } + break; + } + /////////////////////// + case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type + { +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " TLB MISS completed" << std::endl; +} +#endif + if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false; + r_dcache_fsm = DCACHE_IDLE; + break; + } + /////////////////////// + case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written, + // and both itlb and dtlb must be flushed. + // Caution : the itlb miss requests must be taken + // to avoid dead-lock in case of simultaneous ITLB miss + // Caution : the clack and cc requests must be taken + // to avoid dead-lock + { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // itlb miss request + if ( r_icache_tlb_miss_req.read() ) + { + r_dcache_tlb_ins = true; + r_dcache_tlb_vaddr = r_icache_vaddr_save.read(); + r_dcache_fsm = DCACHE_TLB_MISS; + break; + } + + if ( not r_dcache_xtn_req.read() ) + { + r_dtlb.flush(); + r_mmu_ptpr = m_dreq.wdata; + r_dcache_fsm = DCACHE_IDLE; + m_drsp.valid = true; + } + break; + } + ///////////////////// + case DCACHE_XTN_SYNC: // waiting until write buffer empty + // The coherence request must be taken + // as there is a risk of dead-lock + { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + if ( r_wbuf.empty() ) + { + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; + } + break; + } + //////////////////////// + case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM + case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken + case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache + case DCACHE_XTN_IC_PADDR_EXT: // can generate an itlb miss, + case DCACHE_XTN_IT_INVAL: // and because it can exist a simultaneous ITLB miss + + { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // itlb miss request + if ( r_icache_tlb_miss_req.read() ) + { + r_dcache_tlb_ins = true; + r_dcache_tlb_vaddr = r_icache_vaddr_save.read(); + r_dcache_fsm = DCACHE_TLB_MISS; + break; + } + + // test if XTN request to icache completed + if ( not r_dcache_xtn_req.read() ) + { + r_dcache_fsm = DCACHE_IDLE; + m_drsp.valid = true; + } + break; + } + ///////////////////////// + case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using + // r_dcache_flush_count as a slot counter, + // looping in this state until all slots have been visited. + // It can require two cycles per slot: + // We test here the slot state, and make the actual inval + // (if line is valid) in DCACHE_XTN_DC_FLUSH_GO state. + // A cleanup request is generated for each valid line. + // returns to IDLE and flush TLBs when last slot + { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent + { + int state; + paddr_t tag; + size_t way = r_dcache_flush_count.read()/m_dcache_sets; + size_t set = r_dcache_flush_count.read()%m_dcache_sets; + +#ifdef INSTRUMENTATION +m_cpt_dcache_dir_read++; +#endif + r_dcache.read_dir( way, + set, + &tag, + &state ); + + if ( state == CACHE_SLOT_STATE_VALID ) // inval required + { + // request cleanup + r_dcache_cc_send_req = true; + r_dcache_cc_send_nline = tag * m_dcache_sets + set; + r_dcache_cc_send_way = way; + r_dcache_cc_send_type = CC_TYPE_CLEANUP; + + // goes to DCACHE_XTN_DC_FLUSH_GO to inval directory + r_dcache_miss_way = way; + r_dcache_miss_set = set; + r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO; + } + else if ( r_dcache_flush_count.read() == + (m_dcache_sets*m_dcache_ways - 1) ) // last slot + { + r_dtlb.reset(); + r_itlb.reset(); + r_dcache_fsm = DCACHE_IDLE; + m_drsp.valid = true; + } + + // saturation counter + if ( r_dcache_flush_count.read() < (m_dcache_sets*m_dcache_ways - 1) ) + r_dcache_flush_count = r_dcache_flush_count.read() + 1; + } + break; + } + //////////////////////////// + case DCACHE_XTN_DC_FLUSH_GO: // Switch the cache slot to ZOMBI state + // and reset directory extension. + // returns to IDLE and flush TLBs when last slot + { + size_t way = r_dcache_miss_way.read(); + size_t set = r_dcache_miss_set.read(); + + r_dcache_in_tlb[m_dcache_sets*way+set] = false; + r_dcache_contains_ptd[m_dcache_sets*way+set] = false; + +#ifdef INSTRUMENTATION +m_cpt_dcache_dir_write++; +#endif + r_dcache.write_dir( way, + set, + CACHE_SLOT_STATE_ZOMBI ); + + if ( r_dcache_flush_count.read() == + (m_dcache_sets*m_dcache_ways - 1) ) // last slot + { + r_dtlb.reset(); + r_itlb.reset(); + r_dcache_fsm = DCACHE_IDLE; + m_drsp.valid = true; + } + else + { + r_dcache_fsm = DCACHE_XTN_DC_FLUSH; + } + break; + } + ///////////////////////// + case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request + { + r_dtlb.inval(r_dcache_save_wdata.read()); + r_dcache_fsm = DCACHE_IDLE; + m_drsp.valid = true; + break; + } + //////////////////////////// + case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address + // requires 3 cycles: access tlb, read cache, inval cache + // we compute the physical address in this state + { + paddr_t paddr; + bool hit; + + if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated + { + +#ifdef INSTRUMENTATION +m_cpt_dtlb_read++; +#endif + hit = r_dtlb.translate( r_dcache_save_wdata.read(), + &paddr ); + } + else // dtlb not activated + { + paddr = (paddr_t)r_dcache_save_wdata.read(); + if (vci_param::N > 32) + paddr = paddr | ((paddr_t)(r_dcache_paddr_ext.read()) << 32); + hit = true; + } + + if ( hit ) // tlb hit + { + r_dcache_save_paddr = paddr; + r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA; + } + else // tlb miss + { + +#ifdef INSTRUMENTATION +m_cpt_dtlb_miss++; +#endif + r_dcache_tlb_ins = false; // dtlb + r_dcache_tlb_vaddr = r_dcache_save_wdata.read(); + r_dcache_fsm = DCACHE_TLB_MISS; + } + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " Compute physical address" << std::hex + << " / VADDR = " << r_dcache_save_wdata.read() + << " / PADDR = " << paddr << std::endl; +} +#endif + + break; + } + //////////////////////////// + case DCACHE_XTN_DC_INVAL_PA: // selective cache line invalidate with physical address + // requires 2 cycles: read cache / inval cache + // In this state we read dcache. + { + size_t way; + size_t set; + size_t word; + int state; + +#ifdef INSTRUMENTATION +m_cpt_dcache_dir_read++; +#endif + r_dcache.read_dir( r_dcache_save_paddr.read(), + &state, + &way, + &set, + &word ); + + if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done + { + r_dcache_xtn_way = way; + r_dcache_xtn_set = set; + r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO; + } + else // miss : nothing to do + { + r_dcache_fsm = DCACHE_IDLE; + m_drsp.valid = true; + } + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " Test hit in dcache" << std::hex + << " / PADDR = " << r_dcache_save_paddr.read() << std::dec + << " / HIT = " << (state == CACHE_SLOT_STATE_VALID) + << " / SET = " << set + << " / WAY = " << way << std::endl; +} +#endif + break; + } + //////////////////////////// + case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line + // Blocked if previous cleanup not completed + // Test if itlb or dtlb inval is required + { + if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent + { + size_t way = r_dcache_xtn_way.read(); + size_t set = r_dcache_xtn_set.read(); + paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2); + +#ifdef INSTRUMENTATION +m_cpt_dcache_dir_write++; +#endif + r_dcache.write_dir( way, + set, + CACHE_SLOT_STATE_ZOMBI ); + + // request cleanup + r_dcache_cc_send_req = true; + r_dcache_cc_send_nline = nline; + r_dcache_cc_send_way = way; + r_dcache_cc_send_type = CC_TYPE_CLEANUP; + + // possible itlb & dtlb invalidate + if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) + { + r_dcache_tlb_inval_line = nline; + r_dcache_tlb_inval_set = 0; + r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END; + r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; + r_dcache_in_tlb[way*m_dcache_sets+set] = false; + } + else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) + { + r_itlb.reset(); + r_dtlb.reset(); + r_dcache_contains_ptd[way*m_dcache_sets+set] = false; + r_dcache_fsm = DCACHE_IDLE; + m_drsp.valid = true; + } + else + { + r_dcache_fsm = DCACHE_IDLE; + m_drsp.valid = true; + } + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " Actual dcache inval" << std::hex + << " / PADDR = " << r_dcache_save_paddr.read() << std::endl; +} +#endif + } + break; + } + ////////////////////////////// + case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request + { + r_dcache_fsm = DCACHE_IDLE; + m_drsp.valid = true; + break; + } + //////////////////////// + case DCACHE_MISS_SELECT: // Try to select a slot in associative set, + // Waiting in this state if no slot available. + // If a victim slot has been choosen and the r_icache_cc_send_req is false, + // we send the cleanup request in this state. + // If not, a r_icache_cleanup_victim_req flip-flop is + // utilized for saving this cleanup request, and it will be sent later + // in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR. + // The r_icache_miss_clack flip-flop is set + // when a cleanup is required + { + if ( m_dreq.valid) m_cost_data_miss_frz++; + + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + bool found = false; + bool cleanup = false; + size_t way = 0; + size_t set = 0; + paddr_t victim = 0; + +#ifdef INSTRUMENTATION +m_cpt_dcache_dir_read++; +#endif + r_dcache.read_select( r_dcache_save_paddr.read(), + &victim, + &way, + &set, + &found, + &cleanup ); + + if ( not found ) + { + break; + } + else + { + r_dcache_miss_way = way; + r_dcache_miss_set = set; + + if ( cleanup ) + { + if ( not r_dcache_cc_send_req.read() ) + { + r_dcache_cc_send_req = true; + r_dcache_cc_send_nline = victim; + r_dcache_cc_send_way = way; + r_dcache_cc_send_type = CC_TYPE_CLEANUP; + + } + else + { + r_dcache_cleanup_victim_req = true; + r_dcache_cleanup_victim_nline = victim; + } + + r_dcache_miss_clack = true; + r_dcache_fsm = DCACHE_MISS_CLEAN; + } + else + { + r_dcache_fsm = DCACHE_MISS_WAIT; + } + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " Select a slot:" << std::dec + << " / WAY = " << way + << " / SET = " << set + << " / PADDR = " << std::hex << r_dcache_save_paddr.read(); + if(cleanup) std::cout << " / VICTIM = " << (victim*m_dcache_words*4) << std::endl; + else std::cout << std::endl; +} +#endif + } // end found + break; + } + /////////////////////// + case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state + // and possibly request itlb or dtlb invalidate + { + if ( m_dreq.valid) m_cost_data_miss_frz++; + + size_t way = r_dcache_miss_way.read(); + size_t set = r_dcache_miss_set.read(); + +#ifdef INSTRUMENTATION +m_cpt_dcache_dir_read++; +#endif + r_dcache.write_dir( way, + set, + CACHE_SLOT_STATE_ZOMBI ); +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " Switch to ZOMBI state" << std::dec + << " / way = " << way + << " / set = " << set << std::endl; +} +#endif + // if selective itlb & dtlb invalidate are required + // the miss response is not handled before invalidate completed + if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) + { + r_dcache_in_tlb[way*m_dcache_sets+set] = false; + + if( not r_dcache_cleanup_victim_req.read() ) + r_dcache_tlb_inval_line = r_dcache_cc_send_nline.read(); + else + r_dcache_tlb_inval_line = r_dcache_cleanup_victim_nline.read(); + + r_dcache_tlb_inval_set = 0; + r_dcache_fsm_scan_save = DCACHE_MISS_WAIT; + r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; + } + else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) + { + r_itlb.reset(); + r_dtlb.reset(); + r_dcache_contains_ptd[way*m_dcache_sets+set] = false; + r_dcache_fsm = DCACHE_MISS_WAIT; + } + else + { + r_dcache_fsm = DCACHE_MISS_WAIT; + } + break; + } + ////////////////////// + case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM + // This state is in charge of error signaling + // There is 5 types of error depending on the requester + { + if ( m_dreq.valid) m_cost_data_miss_frz++; + + // send cleanup victim request + if ( r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read() ) + { + r_dcache_cc_send_req = true; + r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline; + r_dcache_cc_send_way = r_dcache_miss_way; + r_dcache_cc_send_type = CC_TYPE_CLEANUP; + r_dcache_cleanup_victim_req = false; + } + + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_dcache_req.read() and + not r_dcache_cc_send_req.read() and + not r_dcache_cleanup_victim_req.read()) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + if ( r_vci_rsp_data_error.read() ) // bus error + { + switch ( r_dcache_miss_type.read() ) + { + case PROC_MISS: + { + r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; + r_mmu_dbvar = r_dcache_save_vaddr.read(); + m_drsp.valid = true; + m_drsp.error = true; + r_dcache_fsm = DCACHE_IDLE; + break; + } + case PTE1_MISS: + { + if ( r_dcache_tlb_ins.read() ) + { + r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS; + r_mmu_ibvar = r_dcache_tlb_vaddr.read(); + r_icache_tlb_miss_req = false; + r_icache_tlb_rsp_error = true; + } + else + { + r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS; + r_mmu_dbvar = r_dcache_tlb_vaddr.read(); + m_drsp.valid = true; + m_drsp.error = true; + } + r_dcache_fsm = DCACHE_IDLE; + break; + } + case PTE2_MISS: + { + if ( r_dcache_tlb_ins.read() ) + { + r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS; + r_mmu_ibvar = r_dcache_tlb_vaddr.read(); + r_icache_tlb_miss_req = false; + r_icache_tlb_rsp_error = true; + } + else + { + r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS; + r_mmu_dbvar = r_dcache_tlb_vaddr.read(); + m_drsp.valid = true; + m_drsp.error = true; + } + r_dcache_fsm = DCACHE_IDLE; + break; + } + } // end switch type + r_vci_rsp_data_error = false; + } + else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available + { + r_dcache_miss_word = 0; + r_dcache_fsm = DCACHE_MISS_DATA_UPDT; + } + break; + } + ////////////////////////// + case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle) + { + if ( m_dreq.valid) m_cost_data_miss_frz++; + + if ( r_vci_rsp_fifo_dcache.rok() ) // one word available + { +#ifdef INSTRUMENTATION +m_cpt_dcache_data_write++; +#endif + r_dcache.write( r_dcache_miss_way.read(), + r_dcache_miss_set.read(), + r_dcache_miss_word.read(), + r_vci_rsp_fifo_dcache.read() ); +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " Write one word:" + << " / DATA = " << std::hex << r_vci_rsp_fifo_dcache.read() + << " / WAY = " << std::dec << r_dcache_miss_way.read() + << " / SET = " << r_dcache_miss_set.read() + << " / WORD = " << r_dcache_miss_word.read() << std::endl; +} +#endif + vci_rsp_fifo_dcache_get = true; + r_dcache_miss_word = r_dcache_miss_word.read() + 1; + + if ( r_dcache_miss_word.read() == (m_dcache_words-1) ) // last word + { + r_dcache_fsm = DCACHE_MISS_DIR_UPDT; + } + } + break; + } + ////////////////////////// + case DCACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted + // and the cleanup ack has not been received, + // as indicated by the r_dcache_miss clack. + // - If no matching coherence request (r_dcache_inval_miss) + // switch directory slot to VALID state. + // - If matching coherence request, switch directory slot + // to ZOMBI state, and send a cleanup request. + { + if ( m_dreq.valid) m_cost_data_miss_frz++; + + // send cleanup victim request + if ( r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read() ) + { + r_dcache_cc_send_req = true; + r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline; + r_dcache_cc_send_way = r_dcache_miss_way; + r_dcache_cc_send_type = CC_TYPE_CLEANUP; + r_dcache_cleanup_victim_req = false; + } + + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_dcache_req.read() and + not r_dcache_cc_send_req.read() and + not r_dcache_cleanup_victim_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + if ( not r_dcache_miss_clack.read() ) // waiting cleanup acknowledge + { + if ( r_dcache_miss_inval.read() ) // switch slot to ZOMBI state, and new cleanup + { + if ( not r_dcache_cc_send_req.read() ) // blocked until previous request sent + { + r_dcache_miss_inval = false; + // request cleanup + r_dcache_cc_send_req = true; + r_dcache_cc_send_nline = r_dcache_save_paddr.read()/(m_dcache_words<<2); + r_dcache_cc_send_way = r_dcache_miss_way.read(); + r_dcache_cc_send_type = CC_TYPE_CLEANUP; + +#ifdef INSTRUMENTATION +m_cpt_dcache_dir_write++; +#endif + r_dcache.write_dir( r_dcache_save_paddr.read(), + r_dcache_miss_way.read(), + r_dcache_miss_set.read(), + CACHE_SLOT_STATE_ZOMBI ); +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +std::cout << " Switch slot to ZOMBI state" + << " PADDR = " << std::hex << r_dcache_save_paddr.read() + << " / WAY = " << std::dec << r_dcache_miss_way.read() + << " / SET = " << r_dcache_miss_set.read() << std::endl; +#endif + } + else + break; + } + else // switch slot to VALID state + { + +#ifdef INSTRUMENTATION +m_cpt_dcache_dir_write++; +#endif + r_dcache.write_dir( r_dcache_save_paddr.read(), + r_dcache_miss_way.read(), + r_dcache_miss_set.read(), + CACHE_SLOT_STATE_VALID ); + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +std::cout << " Switch slot to VALID state" + << " PADDR = " << std::hex << r_dcache_save_paddr.read() + << " / WAY = " << std::dec << r_dcache_miss_way.read() + << " / SET = " << r_dcache_miss_set.read() << std::endl; +#endif + // reset directory extension + size_t way = r_dcache_miss_way.read(); + size_t set = r_dcache_miss_set.read(); + r_dcache_in_tlb[way*m_dcache_sets+set] = false; + r_dcache_contains_ptd[way*m_dcache_sets+set] = false; + } + if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET; + else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET; + else r_dcache_fsm = DCACHE_IDLE; + } + break; + } + ///////////////////// + case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read + { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + if ( r_vci_rsp_data_error.read() ) // bus error + { + if(r_dcache_vci_unc_write.read()) + r_mmu_detr = MMU_WRITE_DATA_ILLEGAL_ACCESS; + else + r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; + + r_mmu_dbvar = m_dreq.addr; + r_vci_rsp_data_error = false; + m_drsp.error = true; + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; + break; + } + else if ( r_vci_rsp_fifo_dcache.rok() ) // data available + { + // consume data + vci_rsp_fifo_dcache_get = true; + r_dcache_fsm = DCACHE_IDLE; + + // acknowledge the processor request if it has not been modified + if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) ) + { + m_drsp.valid = true; + m_drsp.error = false; + m_drsp.rdata = r_vci_rsp_fifo_dcache.read(); + } + } + break; + } + ///////////////////// + case DCACHE_LL_WAIT: // waiting VCI response to a LL transaction + { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + if ( r_vci_rsp_data_error.read() ) // bus error + { + r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; + r_mmu_dbvar = m_dreq.addr; + r_vci_rsp_data_error = false; + m_drsp.error = true; + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; + break; + } + else if ( r_vci_rsp_fifo_dcache.rok() ) // data available + { + // consume data + vci_rsp_fifo_dcache_get = true; + + if(r_dcache_ll_rsp_count.read() == 0) // first flit + { + // set key value in llsc reservation buffer + r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read(); + r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1 ; + } + else // last flit + { + // acknowledge the processor request if it has not been modified + if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) ) + { + m_drsp.valid = true; + m_drsp.error = false; + m_drsp.rdata = r_vci_rsp_fifo_dcache.read(); + } + r_dcache_fsm = DCACHE_IDLE; + } + } + break; + } + //////////////////// + case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction + { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + if ( r_vci_rsp_data_error.read() ) // bus error + { + r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; + r_mmu_dbvar = m_dreq.addr; + r_vci_rsp_data_error = false; + m_drsp.error = true; + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; + break; + } + else if ( r_vci_rsp_fifo_dcache.rok() ) // response available + { + // consume response + vci_rsp_fifo_dcache_get = true; + m_drsp.valid = true; + m_drsp.rdata = r_vci_rsp_fifo_dcache.read(); + r_dcache_fsm = DCACHE_IDLE; + } + break; + } + ////////////////////////// + case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory + // before handling a processor WRITE or SC request + // Input argument is r_dcache_dirty_paddr + // In this first state, we get PTE value in dcache + // and post a CAS request to CMD FSM + { + // get PTE in dcache + uint32_t pte; + size_t way; + size_t set; + size_t word; // unused + int state; + +#ifdef INSTRUMENTATION +m_cpt_dcache_data_read++; +m_cpt_dcache_dir_read++; +#endif + r_dcache.read( r_dcache_dirty_paddr.read(), + &pte, + &way, + &set, + &word, + &state ); + + assert( (state == CACHE_SLOT_STATE_VALID) and + "error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" ); + + // request CAS transaction to CMD_FSM + r_dcache_dirty_way = way; + r_dcache_dirty_set = set; + + // check llsc reservation buffer + if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read() ) + r_dcache_llsc_valid = false; + + // request a CAS CMD and go to DCACHE_DIRTY_WAIT state + r_dcache_vci_cas_req = true; + r_dcache_vci_paddr = r_dcache_dirty_paddr.read(); + r_dcache_vci_cas_old = pte; + r_dcache_vci_cas_new = pte | PTE_D_MASK; + r_dcache_fsm = DCACHE_DIRTY_WAIT; + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " CAS request" << std::hex + << " / PTE_PADDR = " << r_dcache_dirty_paddr.read() + << " / PTE_VALUE = " << pte << std::dec + << " / SET = " << set + << " / WAY = " << way << std::endl; +} +#endif + break; + } + /////////////////////// + case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit, + // and return to IDLE state when response is received. + // we don't care if the CAS is a failure: + // - if the CAS is a success, the coherence mechanism + // updates the local copy. + // - if the CAS is a failure, we just retry the write. + { + // coherence clack request (from DSPIN CLACK) + if ( r_dcache_clack_req.read() ) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + // coherence request (from CC_RECEIVE FSM) + if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + { + r_dcache_fsm = DCACHE_CC_CHECK; + r_dcache_fsm_cc_save = r_dcache_fsm.read(); + break; + } + + if ( r_vci_rsp_data_error.read() ) // bus error + { + std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl; + std::cout << "This should not happen in this state" << std::endl; + exit(0); + } + else if ( r_vci_rsp_fifo_dcache.rok() ) // response available + { + vci_rsp_fifo_dcache_get = true; + r_dcache_fsm = DCACHE_IDLE; + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " CAS completed" << std::endl; +} +#endif + } + break; + } + ///////////////////// + case DCACHE_CC_CHECK: // This state is the entry point for the sub-FSM + // handling coherence requests for DCACHE. + // If there is a matching pending miss on the modified cache + // line this is signaled in the r_dcache_miss inval flip-flop. + // If the updated (or invalidated) cache line has copies in TLBs + // these TLB copies are invalidated. + // The return state is defined in r_dcache_fsm_cc_save + { + paddr_t paddr = r_cc_receive_dcache_nline.read() * m_dcache_words * 4; + paddr_t mask = ~((m_dcache_words<<2)-1); + + // CLACK handler + // We switch the directory slot to EMPTY state and reset + // r_dcache_miss_clack if the cleanup ack is matching a pending miss. + if ( r_dcache_clack_req.read() ) + { + if ( m_dreq.valid ) m_cost_data_miss_frz++; + +#ifdef INSTRUMENTATION +m_cpt_dcache_dir_write++; +#endif + r_dcache.write_dir( 0, + r_dcache_clack_way.read(), + r_dcache_clack_set.read(), + CACHE_SLOT_STATE_EMPTY); + + if ( (r_dcache_miss_set.read() == r_dcache_clack_set.read()) and + (r_dcache_miss_way.read() == r_dcache_clack_way.read()) ) + { + r_dcache_miss_clack = false; + } + + r_dcache_clack_req = false; + + // return to cc_save state + r_dcache_fsm = r_dcache_fsm_cc_save.read() ; + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " CLACK for PADDR " << paddr + << " Switch slot to EMPTY state : " + << " set = " << r_dcache_clack_set.read() + << " / way = " << r_dcache_clack_way.read() << std::endl; +} +#endif + break; + } + + assert ( not r_dcache_cc_send_req.read() and + "CC_SEND must be available in DCACHE_CC_CHECK" ); + + // Match between MISS address and CC address + if (r_cc_receive_dcache_req.read() and + ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT ) or + (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT ) or + (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and + ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))) // matching + { + // signaling matching + r_dcache_miss_inval = true; + + // in case of update, go to CC_UPDT + // JUST TO POP THE FIFO + if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) + { + r_dcache_fsm = DCACHE_CC_UPDT; + r_dcache_cc_word = r_cc_receive_word_idx.read(); + + // just pop the fifo , don't write in icache + r_dcache_cc_need_write = false; + } + // the request is dealt with + else + { + r_cc_receive_dcache_req = false; + r_dcache_fsm = r_dcache_fsm_cc_save.read(); + } + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " Coherence request matching a pending miss:" + << " PADDR = " << std::hex << paddr << std::endl; +} +#endif + } + + // CC request handler + + int state = 0; + size_t way = 0; + size_t set = 0; + size_t word = 0; + +#ifdef INSTRUMENTATION +m_cpt_dcache_dir_read++; +#endif + r_dcache.read_dir( paddr, + &state, + &way, + &set, + &word ); // unused + + r_dcache_cc_way = way; + r_dcache_cc_set = set; + + if ( state == CACHE_SLOT_STATE_VALID) // hit + { + // need to update the cache state + if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update + { + r_dcache_cc_need_write = true; + r_dcache_fsm = DCACHE_CC_UPDT; + r_dcache_cc_word = r_cc_receive_word_idx.read(); + } + else if ( r_cc_receive_dcache_type.read() == CC_TYPE_INVAL ) // hit inval + { + r_dcache_fsm = DCACHE_CC_INVAL; + } + } + else // miss + { + // multicast acknowledgement required in case of update + if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) + { + r_dcache_fsm = DCACHE_CC_UPDT; + r_dcache_cc_word = r_cc_receive_word_idx.read(); + + // just pop the fifo , don't write in icache + r_dcache_cc_need_write = false; + } + else // No response needed + { + r_cc_receive_dcache_req = false; + r_dcache_fsm = r_dcache_fsm_cc_save.read(); + } + } + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " Coherence request received:" + << " PADDR = " << std::hex << paddr + << " / TYPE = " << std::dec << r_cc_receive_dcache_type.read() + << " / HIT = " << (state == CACHE_SLOT_STATE_VALID) << std::endl; +} +#endif + + break; + } + ///////////////////// + case DCACHE_CC_INVAL: // hit inval: switch slot to ZOMBI state and send a + // CLEANUP after possible invalidation of copies in + // TLBs + { + size_t way = r_dcache_cc_way.read(); + size_t set = r_dcache_cc_set.read(); + + if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval + { + r_dcache_in_tlb[way*m_dcache_sets+set] = false; + r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); + r_dcache_tlb_inval_set = 0; + r_dcache_fsm_scan_save = r_dcache_fsm.read(); + r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; + break; + } + + if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush + { + r_itlb.reset(); + r_dtlb.reset(); + r_dcache_contains_ptd[way*m_dcache_sets+set] = false; + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " Flush DTLB & ITLB" << std::endl; +} +#endif + } + + assert (not r_dcache_cc_send_req.read() && + "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req " + "must not be set"); + + // Switch slot state to ZOMBI and send CLEANUP command + r_dcache.write_dir( way, + set, + CACHE_SLOT_STATE_ZOMBI ); + + // coherence request completed + r_cc_receive_dcache_req = false; + r_dcache_cc_send_req = true; + r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); + r_dcache_cc_send_way = r_dcache_cc_way.read(); + r_dcache_cc_send_type = CC_TYPE_CLEANUP; + r_dcache_fsm = r_dcache_fsm_cc_save.read(); + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " Switch slot to EMPTY state:" << std::dec + << " / WAY = " << way + << " / SET = " << set << std::endl; +} +#endif + break; + } + /////////////////// + case DCACHE_CC_UPDT: // hit update: write one word per cycle, + // after possible invalidation of copies in TLBs + { + size_t word = r_dcache_cc_word.read(); + size_t way = r_dcache_cc_way.read(); + size_t set = r_dcache_cc_set.read(); + + if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval + { + r_dcache_in_tlb[way*m_dcache_sets+set] = false; + r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); + r_dcache_tlb_inval_set = 0; + r_dcache_fsm_scan_save = r_dcache_fsm.read(); + r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; + + break; + } + + if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush + { + r_itlb.reset(); + r_dtlb.reset(); + r_dcache_contains_ptd[way*m_dcache_sets+set] = false; + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " Flush DTLB & ITLB" << std::endl; +} +#endif + } + + assert (not r_dcache_cc_send_req.read() && + "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req " + "must not be set"); + + if ( not r_cc_receive_updt_fifo_be.rok() ) break; + + if (r_dcache_cc_need_write.read()) + { + +#ifdef INSTRUMENTATION +m_cpt_dcache_data_write++; +#endif + r_dcache.write( way, + set, + word, + r_cc_receive_updt_fifo_data.read(), + r_cc_receive_updt_fifo_be.read() ); + + r_dcache_cc_word = word + 1; + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm ) +{ + std::cout << " Write one word" << std::dec + << " / WAY = " << way + << " / SET = " << set + << " / WORD = " << word + << " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl; +} +#endif + } + + if ( r_cc_receive_updt_fifo_eop.read() ) // last word + { + // no need to write in the cache anymore + r_dcache_cc_need_write = false; + + // coherence request completed + r_cc_receive_dcache_req = false; + + // request multicast acknowledgement + r_dcache_cc_send_req = true; + r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read(); + r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read(); + r_dcache_cc_send_type = CC_TYPE_MULTI_ACK; + + r_dcache_fsm = r_dcache_fsm_cc_save.read(); + } + + //consume fifo if not eop + cc_receive_updt_fifo_get = true; + + break; + } + /////////////////////////// + case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB + // It makes assumption: m_itlb_sets == m_dtlb_sets + // All ways are handled in parallel. + // We enter this state when a DCACHE line is modified, + // and there is a copy in itlb or dtlb. + // It can be caused by: + // - a coherence inval or updt transaction, + // - a line inval caused by a cache miss + // - a processor XTN inval request, + // - a WRITE hit, + // - a Dirty bit update + // Input arguments are: + // - r_dcache_tlb_inval_line + // - r_dcache_tlb_inval_set + // - r_dcache_fsm_scan_save + { + paddr_t line = r_dcache_tlb_inval_line.read(); + size_t set = r_dcache_tlb_inval_set.read(); + size_t way; + bool ok; + + for ( way = 0 ; way < m_itlb_ways ; way++ ) + { + ok = r_itlb.inval( line, way, set ); + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm and ok ) +{ + std::cout << " Invalidate ITLB entry:" << std::hex + << " line = " << line << std::dec + << " / set = " << set + << " / way = " << way << std::endl; +} +#endif + } + + for ( way = 0 ; way < m_dtlb_ways ; way++ ) + { + ok = r_dtlb.inval( line, way, set ); + +#if DEBUG_DCACHE +if ( m_debug_dcache_fsm and ok ) +std::cout << " " + << " Invalidate DTLB entry" << std::hex + << " / line = " << line << std::dec + << " / set = " << set + << " / way = " << way << std::endl; +#endif + } + + // return to the calling state when TLB inval completed + if ( r_dcache_tlb_inval_set.read() == (m_dtlb_sets-1) ) + { + r_dcache_fsm = r_dcache_fsm_scan_save.read(); + } + r_dcache_tlb_inval_set = r_dcache_tlb_inval_set.read() + 1; + break; + } + } // end switch r_dcache_fsm + + ///////////////// wbuf update /////////////////////////////////////////////////////// + r_wbuf.update(); + + ///////////////// llsc update /////////////////////////////////////////////////////// + if (r_dcache_llsc_valid.read()) r_dcache_llsc_count = r_dcache_llsc_count.read() - 1; + if (r_dcache_llsc_count.read() == 1) r_dcache_llsc_valid = false; + + //////////////// test processor frozen ////////////////////////////////////////////// + // The simulation exit if the number of consecutive frozen cycles + // is larger than the m_max_frozen_cycles (constructor parameter) + if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) ) + { + m_cpt_frz_cycles++; // used for instrumentation + m_cpt_stop_simulation++; // used for debug + if ( m_cpt_stop_simulation > m_max_frozen_cycles ) + { + std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl + << " stop at cycle " << m_cpt_total_cycles << std::endl + << " frozen since cycle " << m_cpt_total_cycles - m_max_frozen_cycles + << std::endl; + r_iss.dump(); + exit(1); + } + } + else + { + m_cpt_stop_simulation = 0; + } + + /////////// execute one iss cycle ///////////////////////////////// + { + uint32_t it = 0; + for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it |= (1<" + << " / dmiss_req = " << dcache_miss_req + << " / imiss_req = " << icache_miss_req + << std::endl; +} +#endif + break; + } + //////////////////// + case CMD_DATA_WRITE: + { + if ( p_vci.cmdack.read() ) + { + r_vci_cmd_cpt = r_vci_cmd_cpt + 1; + if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent + { + r_vci_cmd_fsm = CMD_IDLE ; + r_wbuf.sent() ; + } + } + break; + } + ///////////////// + case CMD_DATA_SC: + case CMD_DATA_CAS: + { + // The CAS and SC VCI commands contain two flits + if ( p_vci.cmdack.read() ) + { + r_vci_cmd_cpt = r_vci_cmd_cpt + 1; + if (r_vci_cmd_cpt == 1) r_vci_cmd_fsm = CMD_IDLE ; + } + break; + } + ////////////////// + case CMD_INS_MISS: + case CMD_INS_UNC: + case CMD_DATA_MISS: + case CMD_DATA_UNC_READ: + case CMD_DATA_UNC_WRITE: + case CMD_DATA_LL: + { + // all read VCI commands contain one single flit + if ( p_vci.cmdack.read() ) { + r_vci_cmd_fsm = CMD_IDLE; + } + break; + } + + } // end switch r_vci_cmd_fsm + + ////////////////////////////////////////////////////////////////////////// + // The VCI_RSP FSM controls the following ressources: + // - r_vci_rsp_fsm: + // - r_vci_rsp_fifo_icache (push) + // - r_vci_rsp_fifo_dcache (push) + // - r_vci_rsp_data_error (set) + // - r_vci_rsp_ins_error (set) + // - r_vci_rsp_cpt + // - r_dcache_vci_sc_req (reset when SC response recieved) + // + // As the VCI_RSP and VCI_CMD are fully desynchronized to support several + // simultaneous VCI transactions, this FSM uses the VCI RPKTID field + // to identify the transactions. + // + // VCI vormat: + // This component checks the response packet length and accepts only + // single word packets for write response packets. + // + // Error handling: + // This FSM analyzes the VCI error code and signals directly the Write Bus Error. + // In case of Read Data Error, the VCI_RSP FSM sets the r_vci_rsp_data_error + // flip_flop and the error is signaled by the DCACHE FSM. + // In case of Instruction Error, the VCI_RSP FSM sets the r_vci_rsp_ins_error + // flip_flop and the error is signaled by the ICACHE FSM. + // In case of Cleanup Error, the simulation stops with an error message... + ////////////////////////////////////////////////////////////////////////// + + switch ( r_vci_rsp_fsm.read() ) + { + ////////////// + case RSP_IDLE: + { + if ( p_vci.rspval.read() ) + { + r_vci_rsp_cpt = 0; + + if ( (p_vci.rpktid.read() & 0x7) == TYPE_DATA_UNC ) + { + r_vci_rsp_fsm = RSP_DATA_UNC; + } + else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS ) + { + r_vci_rsp_fsm = RSP_DATA_MISS; + } + else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC ) + { + r_vci_rsp_fsm = RSP_INS_UNC; + } + else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS ) + { + r_vci_rsp_fsm = RSP_INS_MISS; + } + else if ( (p_vci.rpktid.read() & 0x7) == TYPE_WRITE ) + { + r_vci_rsp_fsm = RSP_DATA_WRITE; + } + else if ( (p_vci.rpktid.read() & 0x7) == TYPE_CAS ) + { + r_vci_rsp_fsm = RSP_DATA_UNC; + } + else if ( (p_vci.rpktid.read() & 0x7) == TYPE_LL ) + { + r_vci_rsp_fsm = RSP_DATA_LL; + } + else if ( (p_vci.rpktid.read() & 0x7) == TYPE_SC ) + { + r_vci_rsp_fsm = RSP_DATA_UNC; + } + else + { + assert(false and "Unexpected VCI response"); + } + } + break; + } + ////////////////// + case RSP_INS_MISS: + { + if ( p_vci.rspval.read() ) + { + if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported + { + r_vci_rsp_ins_error = true; + if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE; + } + else // no error reported + { + if ( r_vci_rsp_fifo_icache.wok() ) + { + if ( r_vci_rsp_cpt.read() >= m_icache_words ) + { + std::cout << "ERROR in VCI_CC_VCACHE " << name() + << " VCI response packet too long " + << " for instruction miss" << std::endl; + exit(0); + } + r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; + vci_rsp_fifo_icache_put = true, + vci_rsp_fifo_icache_data = p_vci.rdata.read(); + if ( p_vci.reop.read() ) + { + if ( r_vci_rsp_cpt.read() != (m_icache_words - 1) ) + { + std::cout << "ERROR in VCI_CC_VCACHE " << name() + << " VCI response packet too short" + << " for instruction miss" << std::endl; + exit(0); + } + r_vci_rsp_fsm = RSP_IDLE; + } + } + } + } + break; + } + ///////////////// + case RSP_INS_UNC: + { + if (p_vci.rspval.read() ) + { + assert( p_vci.reop.read() and + "illegal VCI response packet for uncachable instruction"); + + if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported + { + r_vci_rsp_ins_error = true; + r_vci_rsp_fsm = RSP_IDLE; + } + else // no error reported + { + if ( r_vci_rsp_fifo_icache.wok()) + { + vci_rsp_fifo_icache_put = true; + vci_rsp_fifo_icache_data = p_vci.rdata.read(); + r_vci_rsp_fsm = RSP_IDLE; + } + } + } + break; + } + /////////////////// + case RSP_DATA_MISS: + { + if ( p_vci.rspval.read() ) + { + if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported + { + r_vci_rsp_data_error = true; + if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE; + } + else // no error reported + { + if ( r_vci_rsp_fifo_dcache.wok() ) + { + assert( (r_vci_rsp_cpt.read() < m_dcache_words) and + "The VCI response packet for data miss is too long"); + + r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; + vci_rsp_fifo_dcache_put = true, + vci_rsp_fifo_dcache_data = p_vci.rdata.read(); + if ( p_vci.reop.read() ) + { + assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and + "The VCI response packet for data miss is too short"); + + r_vci_rsp_fsm = RSP_IDLE; + } + } + } + } + break; + } + ////////////////// + case RSP_DATA_UNC: + { + if (p_vci.rspval.read() ) + { + assert( p_vci.reop.read() and + "illegal VCI response packet for uncachable read data"); + + if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported + { + r_vci_rsp_data_error = true; + r_vci_rsp_fsm = RSP_IDLE; + } + else // no error reported + { + if ( r_vci_rsp_fifo_dcache.wok()) + { + vci_rsp_fifo_dcache_put = true; + vci_rsp_fifo_dcache_data = p_vci.rdata.read(); + r_vci_rsp_fsm = RSP_IDLE; + } + } + } + break; + } + ///////////////// + case RSP_DATA_LL: + { + if ( p_vci.rspval.read() ) + { + if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported + { + r_vci_rsp_data_error = true; + r_vci_rsp_fsm = RSP_IDLE; + break; + } + if (r_vci_rsp_cpt.read() == 0) //first flit + { + if(r_vci_rsp_fifo_dcache.wok()) + { + assert(!p_vci.reop.read() && + "illegal VCI response packet for LL"); + vci_rsp_fifo_dcache_put = true; + vci_rsp_fifo_dcache_data = p_vci.rdata.read(); + r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; + } + break; + } + else // last flit + { + if(r_vci_rsp_fifo_dcache.wok()) + { + assert(p_vci.reop.read() && + "illegal VCI response packet for LL"); + vci_rsp_fifo_dcache_put = true; + vci_rsp_fifo_dcache_data = p_vci.rdata.read(); + r_vci_rsp_fsm = RSP_IDLE; + } + break; + } + } + break; + } + //////////////////// + case RSP_DATA_WRITE: + { + if (p_vci.rspval.read()) + { + assert( p_vci.reop.read() and + "a VCI response packet must contain one flit for a write transaction"); + + r_vci_rsp_fsm = RSP_IDLE; + uint32_t wbuf_index = p_vci.rtrdid.read(); + r_wbuf.completed(wbuf_index); + if ( (p_vci.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr(); + } + break; + } + } // end switch r_vci_rsp_fsm + + ///////////////////////////////////////////////////////////////////////////////////// + // The CC_SEND FSM is in charge of sending cleanups and the multicast + // acknowledgements on the coherence network. It has two clients (DCACHE FSM + // and ICACHE FSM) that are served with a round-robin priority. + // The CC_SEND FSM resets the r_*cache_cc_send_req request flip-flops as + // soon as the request has been sent. + ///////////////////////////////////////////////////////////////////////////////////// + switch ( r_cc_send_fsm.read() ) + { + /////////////////////////// + case CC_SEND_IDLE: + { + /////////////////////////////////////////////////////// + // handling round robin between icache and dcache : // + // we first check for the last client and listen for // + // a request of the other, then update the client // + // r_cc_send_last_client : 0 dcache / 1 icache + /////////////////////////////////////////////////////// + bool update_last_client = r_cc_send_last_client.read(); + if ( r_cc_send_last_client.read() == 0 ) // last client was dcache + { + if (r_icache_cc_send_req.read()) // request from icache + update_last_client = 1; // update last client to icache + } + else // last client was icache + { + if (r_dcache_cc_send_req.read()) // request from dcache + update_last_client = 0; // update last client to dcache + } + r_cc_send_last_client = update_last_client; + + // if there is an actual request + if (r_dcache_cc_send_req.read() or r_icache_cc_send_req.read()) + { + // the new client is dcache and has a cleanup request + if ( (update_last_client == 0) and + (r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP)) + r_cc_send_fsm = CC_SEND_CLEANUP_1; + // the new client is dcache and has a multi acknowledgement request + else if ( (update_last_client == 0) and + (r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK)) + r_cc_send_fsm = CC_SEND_MULTI_ACK; + // the new client is icache and has a cleanup request + else if ( (update_last_client == 1) and + (r_icache_cc_send_type.read() == CC_TYPE_CLEANUP)) + r_cc_send_fsm = CC_SEND_CLEANUP_1; + // the new client is icache and has a multi acknowledgement request + else if ( (update_last_client == 1) and + (r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK)) + r_cc_send_fsm = CC_SEND_MULTI_ACK; + } + break; + } + /////////////////////////// + case CC_SEND_CLEANUP_1: + { + // wait for the first flit to be consumed + if (p_dspin_p2m.read.read()) + r_cc_send_fsm = CC_SEND_CLEANUP_2; + + break; + } + /////////////////////////// + case CC_SEND_CLEANUP_2: + { + // wait for the second flit to be consumed + if (p_dspin_p2m.read.read()) + { + if (r_cc_send_last_client.read() == 0) // dcache active request + r_dcache_cc_send_req = false; // reset dcache request + else // icache active request + r_icache_cc_send_req = false; // reset icache request + + // go back to idle state + r_cc_send_fsm = CC_SEND_IDLE; + } + break; + } + /////////////////////////// + case CC_SEND_MULTI_ACK: + { + // wait for the flit to be consumed + if(p_dspin_p2m.read.read()) + { + if(r_cc_send_last_client.read() == 0) // dcache active request + r_dcache_cc_send_req = false; // reset dcache request + else // icache active request + r_icache_cc_send_req = false; // reset icache request + // go back to idle state + r_cc_send_fsm = CC_SEND_IDLE; + } + break; + } + } // end switch CC_SEND FSM + + /////////////////////////////////////////////////////////////////////////////// + // CC_RECEIVE FSM + // This FSM receive all coherence packets on a DSPIN40 port. + // There is 5 packet types: + // - CC_DATA_INVAL : DCACHE invalidate request + // - CC_DATA_UPDT : DCACHE update request (multi-words) + // - CC_INST_INVAL : ICACHE invalidate request + // - CC_INST_UPDT : ICACHE update request (multi-words) + // - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE) + ////////////////////////////////////////////////////////////////////////////// + switch( r_cc_receive_fsm.read() ) + { + ///////////////////// + case CC_RECEIVE_IDLE: + { + // a coherence request has arrived + if (p_dspin_m2p.write.read()) + { + // initialize dspin received data + uint64_t receive_data = p_dspin_m2p.data.read(); + // initialize coherence packet type + uint64_t receive_type = DspinDhccpParam::dspin_get(receive_data, + DspinDhccpParam::M2P_TYPE); + // test for a broadcast + if (DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::M2P_BC)) + { + r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER; + } + // test for a multi updt + else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA) + { + r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_HEADER; + } + else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_INST) + { + r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_HEADER; + } + // test for a multi inval + else if (receive_type == DspinDhccpParam::TYPE_MULTI_INVAL_DATA) + { + r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_HEADER; + } + else + { + r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_HEADER; + } + } + break; + } + /////////////////////////////// + case CC_RECEIVE_BRDCAST_HEADER: + { + // no actual data in the HEADER, just skip to second flit + r_cc_receive_fsm = CC_RECEIVE_BRDCAST_NLINE; + break; + } + ////////////////////////////// + case CC_RECEIVE_BRDCAST_NLINE: + { + // initialize dspin received data + uint64_t receive_data = p_dspin_m2p.data.read(); + // wait for both dcache and icache to take the request + // TODO maybe we need to wait for both only to leave the state, but + // not to actually post a request to an available cache => need a + // flip_flop to check that ? + if (not (r_cc_receive_icache_req.read()) and + not (r_cc_receive_dcache_req.read()) and + (p_dspin_m2p.write.read())) + { + // request dcache to handle the BROADCAST + r_cc_receive_dcache_req = true; + r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data, + DspinDhccpParam::BROADCAST_NLINE); + r_cc_receive_dcache_type = CC_TYPE_INVAL; + // request icache to handle the BROADCAST + r_cc_receive_icache_req = true; + r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data, + DspinDhccpParam::BROADCAST_NLINE); + r_cc_receive_icache_type = CC_TYPE_INVAL; + // get back to idle state + r_cc_receive_fsm = CC_RECEIVE_IDLE; + break; + } + // keep waiting for the caches to accept the request + break; + } + ///////////////////////////// + case CC_RECEIVE_DATA_INVAL_HEADER: + { + // sample updt tab index in the HEADER, then skip to second flit + r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_NLINE; + break; + } + ///////////////////////////// + case CC_RECEIVE_INS_INVAL_HEADER: + { + // sample updt tab index in the HEADER, then skip to second flit + r_cc_receive_fsm = CC_RECEIVE_INS_INVAL_NLINE; + break; + } + //////////////////////////// + case CC_RECEIVE_DATA_INVAL_NLINE: + { + // sample nline in the second flit + uint64_t receive_data = p_dspin_m2p.data.read(); + // for data INVAL, wait for dcache to take the request + if (p_dspin_m2p.write.read() and + not r_cc_receive_dcache_req.read() ) + { + // request dcache to handle the INVAL + r_cc_receive_dcache_req = true; + r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE); + r_cc_receive_dcache_type = CC_TYPE_INVAL; + // get back to idle state + r_cc_receive_fsm = CC_RECEIVE_IDLE; + break; + } + break; + } + ////////////////////////////// + case CC_RECEIVE_INS_INVAL_NLINE: + { + // sample nline in the second flit + uint64_t receive_data = p_dspin_m2p.data.read(); + // for ins INVAL, wait for icache to take the request + if (p_dspin_m2p.write.read() and + not r_cc_receive_icache_req.read() ) + { + // request icache to handle the INVAL + r_cc_receive_icache_req = true; + r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE); + r_cc_receive_icache_type = CC_TYPE_INVAL; + // get back to idle state + r_cc_receive_fsm = CC_RECEIVE_IDLE; + break; + } + break; + } + //////////////////////////// + case CC_RECEIVE_DATA_UPDT_HEADER: + { + // sample updt tab index in the HEADER, than skip to second flit + uint64_t receive_data = p_dspin_m2p.data.read(); + // for data INVAL, wait for dcache to take the request and fifo to + // be empty + if (not r_cc_receive_dcache_req.read()) + { + r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX); + r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_NLINE; + break; + } + break; + } + //////////////////////////// + case CC_RECEIVE_INS_UPDT_HEADER: + { + // sample updt tab index in the HEADER, than skip to second flit + uint64_t receive_data = p_dspin_m2p.data.read(); + // for ins INVAL, wait for icache to take the request and fifo to be + // empty + if (not r_cc_receive_icache_req.read()) + { + r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX); + r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_NLINE; + break; + } + // keep waiting for the correct cache to accept the request + break; + } + /////////////////////////// + case CC_RECEIVE_DATA_UPDT_NLINE: + { + // sample nline and word index in the second flit + uint64_t receive_data = p_dspin_m2p.data.read(); + // for data INVAL, wait for dcache to take the request and fifo to + // be empty + if ( r_cc_receive_updt_fifo_be.empty() and + p_dspin_m2p.write.read() ) + { + r_cc_receive_dcache_req = true; + r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE); + r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX); + r_cc_receive_dcache_type = CC_TYPE_UPDT; + // get back to idle state + r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_DATA; + break; + } + break; + } + //////////////////////////// + case CC_RECEIVE_INS_UPDT_NLINE: + { + // sample nline and word index in the second flit + uint64_t receive_data = p_dspin_m2p.data.read(); + // for ins INVAL, wait for icache to take the request and fifo to be + // empty + if ( r_cc_receive_updt_fifo_be.empty() and + p_dspin_m2p.write.read() ) + { + r_cc_receive_icache_req = true; + r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE); + r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX); + r_cc_receive_icache_type = CC_TYPE_UPDT; + // get back to idle state + r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_DATA; + break; + } + break; + } + ////////////////////////// + case CC_RECEIVE_DATA_UPDT_DATA: + { + // wait for the fifo + if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read())) + { + uint64_t receive_data = p_dspin_m2p.data.read(); + bool receive_eop = p_dspin_m2p.eop.read(); + cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE); + cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA); + cc_receive_updt_fifo_eop = receive_eop; + cc_receive_updt_fifo_put = true; + if ( receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE; + } + break; + } + ////////////////////////// + case CC_RECEIVE_INS_UPDT_DATA: + { + // wait for the fifo + if (r_cc_receive_updt_fifo_be.wok() and (p_dspin_m2p.write.read())) + { + uint64_t receive_data = p_dspin_m2p.data.read(); + bool receive_eop = p_dspin_m2p.eop.read(); + cc_receive_updt_fifo_be = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE); + cc_receive_updt_fifo_data = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA); + cc_receive_updt_fifo_eop = receive_eop; + cc_receive_updt_fifo_put = true; + if ( receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE; + } + break; + } + + } // end switch CC_RECEIVE FSM + + ///////////////// DSPIN CLACK interface /////////////// + + uint64_t clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), + DspinDhccpParam::CLACK_TYPE); + + size_t clack_way = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), + DspinDhccpParam::CLACK_WAY); + + size_t clack_set = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), + DspinDhccpParam::CLACK_SET); + + bool dspin_clack_get = false; + bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA); + bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST); + + if (r_dspin_clack_req.read()) + { + // CLACK DATA: Send request to DCACHE FSM + if (dcache_clack_request and not r_dcache_clack_req.read()){ + r_dcache_clack_req = true; + r_dcache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1); + r_dcache_clack_set = clack_set & ((1ULL<<(uint32_log2(m_dcache_sets)))-1); + dspin_clack_get = true; + } + + // CLACK INST: Send request to ICACHE FSM + else if (icache_clack_request and not r_icache_clack_req.read()){ + r_icache_clack_req = true; + r_icache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1); + r_icache_clack_set = clack_set & ((1ULL<<(uint32_log2(m_icache_sets)))-1); + dspin_clack_get = true; + } + } + else + { + dspin_clack_get = true; + } + + if (dspin_clack_get) + { + r_dspin_clack_req = p_dspin_clack.write.read(); + r_dspin_clack_flit = p_dspin_clack.data.read(); + } + + ///////////////// Response FIFOs update ////////////////////// + r_vci_rsp_fifo_icache.update(vci_rsp_fifo_icache_get, + vci_rsp_fifo_icache_put, + vci_rsp_fifo_icache_data); + + r_vci_rsp_fifo_dcache.update(vci_rsp_fifo_dcache_get, + vci_rsp_fifo_dcache_put, + vci_rsp_fifo_dcache_data); + + ///////////////// updt FIFO update ////////////////////// + //TODO check this + r_cc_receive_updt_fifo_be.update(cc_receive_updt_fifo_get, + cc_receive_updt_fifo_put, + cc_receive_updt_fifo_be); + r_cc_receive_updt_fifo_data.update(cc_receive_updt_fifo_get, + cc_receive_updt_fifo_put, + cc_receive_updt_fifo_data); + r_cc_receive_updt_fifo_eop.update(cc_receive_updt_fifo_get, + cc_receive_updt_fifo_put, + cc_receive_updt_fifo_eop); + +} // end transition() + +/////////////////////// +tmpl(void)::genMoore() +/////////////////////// +{ + + // VCI initiator command on the direct network + // it depends on the CMD FSM state + + bool is_sc_or_cas = (r_vci_cmd_fsm.read() == CMD_DATA_CAS) or + (r_vci_cmd_fsm.read() == CMD_DATA_SC ); + + p_vci.pktid = 0; + p_vci.srcid = m_srcid; + p_vci.cons = is_sc_or_cas; + p_vci.contig = not is_sc_or_cas; + p_vci.wrap = false; + p_vci.clen = 0; + p_vci.cfixed = false; + + if ( m_monitor_ok ) { + if ( p_vci.cmdack.read() == true and p_vci.cmdval == true) { + if (((p_vci.address.read()) >= m_monitor_base) and + ((p_vci.address.read()) < m_monitor_base + m_monitor_length) ) { + std::cout << "CC_VCACHE Monitor " << name() << std::hex + << " Access type = " << vci_cmd_type_str[p_vci.cmd.read()] + << " Pktid type = " << vci_pktid_type_str[p_vci.pktid.read()] + << " : address = " << p_vci.address.read() + << " / be = " << p_vci.be.read(); + if ( p_vci.cmd.read() == vci_param::CMD_WRITE ) { + std::cout << " / data = " << p_vci.wdata.read(); + } + std::cout << std::dec << std::endl; + } + } + } + + switch ( r_vci_cmd_fsm.read() ) { + + case CMD_IDLE: + p_vci.cmdval = false; + p_vci.address = 0; + p_vci.wdata = 0; + p_vci.be = 0; + p_vci.trdid = 0; + p_vci.pktid = 0; + p_vci.plen = 0; + p_vci.cmd = vci_param::CMD_NOP; + p_vci.eop = false; + break; + + case CMD_INS_MISS: + p_vci.cmdval = true; + p_vci.address = r_icache_vci_paddr.read() & m_icache_yzmask; + p_vci.wdata = 0; + p_vci.be = 0xF; + p_vci.trdid = 0; + p_vci.pktid = TYPE_READ_INS_MISS; + p_vci.plen = m_icache_words<<2; + p_vci.cmd = vci_param::CMD_READ; + p_vci.eop = true; + break; + + case CMD_INS_UNC: + p_vci.cmdval = true; + p_vci.address = r_icache_vci_paddr.read() & ~0x3; + p_vci.wdata = 0; + p_vci.be = 0xF; + p_vci.trdid = 0; + p_vci.pktid = TYPE_READ_INS_UNC; + p_vci.plen = 4; + p_vci.cmd = vci_param::CMD_READ; + p_vci.eop = true; + break; + + case CMD_DATA_MISS: + p_vci.cmdval = true; + p_vci.address = r_dcache_vci_paddr.read() & m_dcache_yzmask; + p_vci.wdata = 0; + p_vci.be = 0xF; + p_vci.trdid = 0; + p_vci.pktid = TYPE_READ_DATA_MISS; + p_vci.plen = m_dcache_words << 2; + p_vci.cmd = vci_param::CMD_READ; + p_vci.eop = true; + break; + + case CMD_DATA_UNC_READ: + p_vci.cmdval = true; + p_vci.address = r_dcache_vci_paddr.read() & ~0x3; + p_vci.wdata = 0; + p_vci.be = r_dcache_vci_unc_be.read(); + p_vci.trdid = 0; + p_vci.pktid = TYPE_DATA_UNC; + p_vci.plen = 4; + p_vci.cmd = vci_param::CMD_READ; + p_vci.eop = true; + break; + + case CMD_DATA_UNC_WRITE: + p_vci.cmdval = true; + p_vci.address = r_dcache_vci_paddr.read() & ~0x3; + p_vci.wdata = r_dcache_vci_wdata.read(); + p_vci.be = r_dcache_vci_unc_be.read(); + p_vci.trdid = 0; + p_vci.pktid = TYPE_DATA_UNC; + p_vci.plen = 4; + p_vci.cmd = vci_param::CMD_WRITE; + p_vci.eop = true; + break; + + case CMD_DATA_WRITE: + p_vci.cmdval = true; + p_vci.address = r_wbuf.getAddress(r_vci_cmd_cpt.read()) & ~0x3; + p_vci.wdata = r_wbuf.getData(r_vci_cmd_cpt.read()); + p_vci.be = r_wbuf.getBe(r_vci_cmd_cpt.read()); + p_vci.trdid = r_wbuf.getIndex(); + p_vci.pktid = TYPE_WRITE; + p_vci.plen = (r_vci_cmd_max.read() - r_vci_cmd_min.read() + 1) << 2; + p_vci.cmd = vci_param::CMD_WRITE; + p_vci.eop = (r_vci_cmd_cpt.read() == r_vci_cmd_max.read()); + break; + + case CMD_DATA_LL: + p_vci.cmdval = true; + p_vci.address = r_dcache_vci_paddr.read() & ~0x3; + p_vci.wdata = 0; + p_vci.be = 0xF; + p_vci.trdid = 0; + p_vci.pktid = TYPE_LL; + p_vci.plen = 8; + p_vci.cmd = vci_param::CMD_LOCKED_READ; + p_vci.eop = true; + break; + + case CMD_DATA_SC: + p_vci.cmdval = true; + p_vci.address = r_dcache_vci_paddr.read() & ~0x3; + if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_llsc_key.read(); + else p_vci.wdata = r_dcache_vci_sc_data.read(); + p_vci.be = 0xF; + p_vci.trdid = 0; + p_vci.pktid = TYPE_SC; + p_vci.plen = 8; + p_vci.cmd = vci_param::CMD_NOP; + p_vci.eop = (r_vci_cmd_cpt.read() == 1); + break; + + case CMD_DATA_CAS: + p_vci.cmdval = true; + p_vci.address = r_dcache_vci_paddr.read() & ~0x3; + if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_vci_cas_old.read(); + else p_vci.wdata = r_dcache_vci_cas_new.read(); + p_vci.be = 0xF; + p_vci.trdid = 0; + p_vci.pktid = TYPE_CAS; + p_vci.plen = 8; + p_vci.cmd = vci_param::CMD_NOP; + p_vci.eop = (r_vci_cmd_cpt.read() == 1); + break; + } // end switch r_vci_cmd_fsm + + // VCI initiator response on the direct network + // it depends on the VCI_RSP FSM + + switch (r_vci_rsp_fsm.read() ) + { + case RSP_DATA_WRITE : p_vci.rspack = true; break; + case RSP_INS_MISS : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break; + case RSP_INS_UNC : p_vci.rspack = r_vci_rsp_fifo_icache.wok(); break; + case RSP_DATA_MISS : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break; + case RSP_DATA_UNC : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break; + case RSP_DATA_LL : p_vci.rspack = r_vci_rsp_fifo_dcache.wok(); break; + case RSP_IDLE : p_vci.rspack = false; break; + } // end switch r_vci_rsp_fsm + + + // Send coherence packets on DSPIN P2M + // it depends on the CC_SEND FSM + + uint64_t dspin_send_data = 0; + switch ( r_cc_send_fsm.read() ) + { + ////////////////// + case CC_SEND_IDLE: + { + p_dspin_p2m.write = false; + break; + } + /////////////////////// + case CC_SEND_CLEANUP_1: + { + // initialize dspin send data +// DspinDhccpParam::dspin_set(dspin_send_data, +// 0, +// DspinDhccpParam::P2M_EOP); + DspinDhccpParam::dspin_set(dspin_send_data, + m_cc_global_id, + DspinDhccpParam::CLEANUP_SRCID); + DspinDhccpParam::dspin_set(dspin_send_data, + 0, + DspinDhccpParam::P2M_BC); + + if(r_cc_send_last_client.read() == 0) // dcache active request + { + uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read() + >> (m_nline_width - m_x_width - m_y_width) + << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); + + DspinDhccpParam::dspin_set(dspin_send_data, + dest, + DspinDhccpParam::CLEANUP_DEST); + + DspinDhccpParam::dspin_set(dspin_send_data, + (r_dcache_cc_send_nline.read() & 0x300000000ULL)>>32, + DspinDhccpParam::CLEANUP_NLINE_MSB); + + DspinDhccpParam::dspin_set(dspin_send_data, + r_dcache_cc_send_way.read(), + DspinDhccpParam::CLEANUP_WAY_INDEX); + + DspinDhccpParam::dspin_set(dspin_send_data, + DspinDhccpParam::TYPE_CLEANUP_DATA, + DspinDhccpParam::P2M_TYPE); + } + else // icache active request + { + uint64_t dest = (uint64_t) r_icache_cc_send_nline.read() + >> (m_nline_width - m_x_width - m_y_width) + << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); + + DspinDhccpParam::dspin_set(dspin_send_data, + dest, + DspinDhccpParam::CLEANUP_DEST); + + DspinDhccpParam::dspin_set(dspin_send_data, + (r_icache_cc_send_nline.read() & 0x300000000ULL)>>32, + DspinDhccpParam::CLEANUP_NLINE_MSB); + + DspinDhccpParam::dspin_set(dspin_send_data, + r_icache_cc_send_way.read(), + DspinDhccpParam::CLEANUP_WAY_INDEX); + + DspinDhccpParam::dspin_set(dspin_send_data, + DspinDhccpParam::TYPE_CLEANUP_INST, + DspinDhccpParam::P2M_TYPE); + } + // send flit + p_dspin_p2m.data = dspin_send_data; + p_dspin_p2m.write = true; + p_dspin_p2m.eop = false; + break; + } + /////////////////////// + case CC_SEND_CLEANUP_2: + { + // initialize dspin send data +// DspinDhccpParam::dspin_set(dspin_send_data, +// 1, +// DspinDhccpParam::P2M_EOP); + + if(r_cc_send_last_client.read() == 0) // dcache active request + { + DspinDhccpParam::dspin_set(dspin_send_data, + r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL, + DspinDhccpParam::CLEANUP_NLINE_LSB); + } + else // icache active request + { + DspinDhccpParam::dspin_set(dspin_send_data, + r_icache_cc_send_nline.read() & 0xFFFFFFFFULL, + DspinDhccpParam::CLEANUP_NLINE_LSB); + } + // send flit + p_dspin_p2m.data = dspin_send_data; + p_dspin_p2m.write = true; + p_dspin_p2m.eop = true; + break; + } + /////////////////////// + case CC_SEND_MULTI_ACK: + { + // initialize dspin send data +// DspinDhccpParam::dspin_set(dspin_send_data, +// 1, +// DspinDhccpParam::P2M_EOP); + DspinDhccpParam::dspin_set(dspin_send_data, + 0, + DspinDhccpParam::P2M_BC); + DspinDhccpParam::dspin_set(dspin_send_data, + DspinDhccpParam::TYPE_MULTI_ACK, + DspinDhccpParam::P2M_TYPE); + + if(r_cc_send_last_client.read() == 0) // dcache active request + { + uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read() + >> (m_nline_width - m_x_width - m_y_width) + << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); + + DspinDhccpParam::dspin_set(dspin_send_data, + dest, + DspinDhccpParam::MULTI_ACK_DEST); + + DspinDhccpParam::dspin_set(dspin_send_data, + r_dcache_cc_send_updt_tab_idx.read(), + DspinDhccpParam::MULTI_ACK_UPDT_INDEX); + } + else // icache active request + { + uint64_t dest = (uint64_t) r_icache_cc_send_nline.read() + >> (m_nline_width - m_x_width - m_y_width) + << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); + + + DspinDhccpParam::dspin_set(dspin_send_data, + dest, + DspinDhccpParam::MULTI_ACK_DEST); + + DspinDhccpParam::dspin_set(dspin_send_data, + r_icache_cc_send_updt_tab_idx.read(), + DspinDhccpParam::MULTI_ACK_UPDT_INDEX); + } + // send flit + p_dspin_p2m.data = dspin_send_data; + p_dspin_p2m.write = true; + p_dspin_p2m.eop = true; + + break; + } + } // end switch CC_SEND FSM + + // Receive coherence packets + // It depends on the CC_RECEIVE FSM + switch( r_cc_receive_fsm.read() ) + { + ///////////////////// + case CC_RECEIVE_IDLE: + { + p_dspin_m2p.read = false; + break; + } + /////////////////////////////// + case CC_RECEIVE_BRDCAST_HEADER: + { + p_dspin_m2p.read = true; + break; + } + ////////////////////////////// + case CC_RECEIVE_BRDCAST_NLINE: + { + // TODO maybe we need to wait for both only to leave the state, but + // not to actually post a request to an available cache => need a + // flip_flop to check that ? + if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read())) + p_dspin_m2p.read = true; + else + p_dspin_m2p.read = false; + break; + } + ///////////////////////////// + case CC_RECEIVE_DATA_INVAL_HEADER: + case CC_RECEIVE_INS_INVAL_HEADER: + { + p_dspin_m2p.read = true; + break; + } + //////////////////////////// + case CC_RECEIVE_DATA_INVAL_NLINE: + { + p_dspin_m2p.read = not r_cc_receive_dcache_req.read(); + break; + } + case CC_RECEIVE_INS_INVAL_NLINE: + { + p_dspin_m2p.read = not r_cc_receive_icache_req.read(); + break; + } + /////////////////////////// + case CC_RECEIVE_DATA_UPDT_HEADER: + { + if (not r_cc_receive_dcache_req.read()) + p_dspin_m2p.read = true; + else + p_dspin_m2p.read = false; + break; + } + //////////////////////////// + case CC_RECEIVE_INS_UPDT_HEADER: + { + if ( not r_cc_receive_icache_req.read()) + p_dspin_m2p.read = true; + else + p_dspin_m2p.read = false; + break; + } + /////////////////////////// + case CC_RECEIVE_DATA_UPDT_NLINE: + case CC_RECEIVE_INS_UPDT_NLINE: + { + if(r_cc_receive_updt_fifo_be.empty()) + p_dspin_m2p.read = true; + else + p_dspin_m2p.read = false; + break; + } + /////////////////////////// + case CC_RECEIVE_DATA_UPDT_DATA: + case CC_RECEIVE_INS_UPDT_DATA: + { + if (r_cc_receive_updt_fifo_be.wok()) + p_dspin_m2p.read = true; + else + p_dspin_m2p.read = false; + break; + } + } // end switch CC_RECEIVE FSM + + + int clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), + DspinDhccpParam::CLACK_TYPE); + + bool dspin_clack_get = false; + bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA); + bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST); + + if (r_dspin_clack_req.read()) + { + // CLACK DATA: wait if pending request to DCACHE FSM + if (dcache_clack_request and not r_dcache_clack_req.read()) + { + dspin_clack_get = true; + } + + // CLACK INST: wait if pending request to ICACHE FSM + else if (icache_clack_request and not r_icache_clack_req.read()) + { + dspin_clack_get = true; + } + } + else + { + dspin_clack_get = true; + } + + p_dspin_clack.read = dspin_clack_get; +} // end genMoore + +tmpl(void)::start_monitor(paddr_t base, paddr_t length) +// This version of monitor print both Read and Write request +{ + m_monitor_ok = true; + m_monitor_base = base; + m_monitor_length = length; +} + +tmpl(void)::stop_monitor() +{ + m_monitor_ok = false; +} + +}} + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 Index: /branches/fault_tolerance/modules/vci_ethernet_tsar/caba/metadata/vci_ethernet.sd =================================================================== --- /branches/fault_tolerance/modules/vci_ethernet_tsar/caba/metadata/vci_ethernet.sd (revision 724) +++ /branches/fault_tolerance/modules/vci_ethernet_tsar/caba/metadata/vci_ethernet.sd (revision 724) @@ -0,0 +1,35 @@ + +# -*- python -*- + +Module('caba:vci_ethernet_tsar', + classname = 'soclib::caba::VciEthernet', + tmpl_parameters = [ + parameter.Module('vci_param', default = 'caba:vci_param'), + ], + header_files = ['../source/include/vci_ethernet.h', + ], + interface_files = [ + '../../include/soclib/ethernet.h' + ], + implementation_files = ['../source/src/vci_ethernet.cpp',], + ports = [ + Port('caba:vci_target', 'p_vci_target'), + Port('caba:vci_initiator', 'p_vci_initiator'), + Port('caba:bit_out', 'p_irq'), + Port('caba:bit_in', 'p_resetn', auto = 'resetn'), + Port('caba:clock_in', 'p_clk', auto = 'clock'), + ], + uses = [ + Uses('caba:base_module'), + Uses('caba:vci_target_fsm', default_target = 'true', support_llsc = 'false'), + Uses('caba:vci_initiator_simple_read_req'), + Uses('caba:vci_initiator_simple_write_req'), + Uses('caba:vci_initiator_fsm'), + ], + instance_parameters = [ + parameter.Module('mt', typename = 'common:mapping_table'), + parameter.IntTab('srcid'), + parameter.IntTab('tgtid'), + parameter.String('filename'), + ], +) Index: /branches/fault_tolerance/modules/vci_ethernet_tsar/caba/source/include/vci_ethernet.h =================================================================== --- /branches/fault_tolerance/modules/vci_ethernet_tsar/caba/source/include/vci_ethernet.h (revision 724) +++ /branches/fault_tolerance/modules/vci_ethernet_tsar/caba/source/include/vci_ethernet.h (revision 724) @@ -0,0 +1,149 @@ +/* -*- c++ -*- + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Copyright (c) Telecom ParisTech + * Alexandre Becoulet , 2012 + * + * Maintainers: becoulet + * + * Maintainers: nipo + */ + +#ifndef SOCLIB_VCI_ETHERNET_H +#define SOCLIB_VCI_ETHERNET_H + +#include +#include + +#include +#include +#include +#include +#include + +#include "vci_target_fsm.h" +#include "vci_initiator_fsm.h" +#include "caba_base_module.h" +#include "mapping_table.h" + +#define VCI_ETHERNET_FIFO_SIZE 8 +#define VCI_ETHERNET_MAX_PKT_SIZE 1500 + +namespace soclib { +namespace caba { + +using namespace sc_core; + +template +class VciEthernet + : public caba::BaseModule +{ +private: + soclib::caba::VciTargetFsm m_vci_target_fsm; + soclib::caba::VciInitiatorFsm m_vci_init_fsm; + typedef typename soclib::caba::VciInitiatorReq req_t; + + bool on_write(int seg, typename vci_param::addr_t addr, typename vci_param::data_t data, int be); + bool on_read(int seg, typename vci_param::addr_t addr, typename vci_param::data_t &data); + void read_finish( req_t *req ); + void write_finish( req_t *req ); + void transition(); + void genMoore(); + void cleanup_fifos(); + + struct fifo_entry_t + { + uint32_t addr; + uint32_t size; + uint32_t status; + uint8_t *data; + int dma_offset; + union { + VciInitSimpleReadReq *rd_req; + VciInitSimpleWriteReq *wr_req; + }; + }; + + int _rx_start; //< index of first available rx buffer + int _rx_free; //< number of yet unused rx buffers + int _rx_done; //< number of rx buffers ready to pop + int _rx_count; //< total number of rx buffers + + int _tx_start; //< index of first tx buffer + int _tx_waiting; //< number of yet unprocessed tx buffers + int _tx_done; //< number of tx buffers ready to pop + int _tx_count; //< total number of tx buffers + + int _link_check_counter; + + bool _dma_busy; + bool _link_up; + bool _link_changed; + + fifo_entry_t _tx_fifo[VCI_ETHERNET_FIFO_SIZE]; + fifo_entry_t _rx_fifo[VCI_ETHERNET_FIFO_SIZE]; + + uint32_t _tx_size; //< next tx buffer size + uint32_t _rx_size; //< next rx buffer size + + bool _rx_irq_en; + bool _tx_irq_en; + bool _link_irq_en; + bool _soft_reset; + + int _fd; + uint8_t _mac[6]; + + struct ifreq _tap_ifr; + + inline void ended(int status); + +protected: + SC_HAS_PROCESS(VciEthernet); + +public: + sc_in p_clk; + sc_in p_resetn; + soclib::caba::VciTarget p_vci_target; + soclib::caba::VciInitiator p_vci_initiator; + sc_out p_irq; + + VciEthernet(sc_module_name name, const soclib::common::MappingTable &mt, + const soclib::common::IntTab &srcid, const soclib::common::IntTab &tgtid, + const std::string &if_name = "soclib0"); + + ~VciEthernet(); +}; + +}} + +#endif /* SOCLIB_VCI_ETHERNET_H */ + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: /branches/fault_tolerance/modules/vci_ethernet_tsar/caba/source/src/.tags =================================================================== --- /branches/fault_tolerance/modules/vci_ethernet_tsar/caba/source/src/.tags (revision 724) +++ /branches/fault_tolerance/modules/vci_ethernet_tsar/caba/source/src/.tags (revision 724) @@ -0,0 +1,137 @@ +!_TAG_FILE_FORMAT 2 /extended format; --format=1 will not append ;" to lines/ +!_TAG_FILE_SORTED 1 /0=unsorted, 1=sorted, 2=foldcase/ +!_TAG_PROGRAM_AUTHOR Darren Hiebert /dhiebert@users.sourceforge.net/ +!_TAG_PROGRAM_NAME Exuberant Ctags // +!_TAG_PROGRAM_URL http://ctags.sourceforge.net /official site/ +!_TAG_PROGRAM_VERSION 5.9~svn20110310 // +CHUNCK_SIZE /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp 41;" d file: +SC_HAS_PROCESS /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ SC_HAS_PROCESS(VciEthernet);$/;" p class:soclib::caba::VciEthernet access:protected signature:(VciEthernet) +SOCLIB_VCI_ETHERNET_H /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h 32;" d +VCI_ETHERNET_FIFO_SIZE /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h 48;" d +VCI_ETHERNET_MAX_PKT_SIZE /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h 49;" d +VciEthernet /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ VciEthernet(sc_module_name name, const soclib::common::MappingTable &mt,$/;" p class:soclib::caba::VciEthernet access:public signature:(sc_module_name name, const soclib::common::MappingTable &mt, const soclib::common::IntTab &srcid, const soclib::common::IntTab &tgtid, const std::string &if_name = Ó) +VciEthernet /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^class VciEthernet$/;" c namespace:soclib::caba inherits:caba::BaseModule +_dma_busy /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool _dma_busy;$/;" m class:soclib::caba::VciEthernet access:private +_fd /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _fd;$/;" m class:soclib::caba::VciEthernet access:private +_link_changed /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool _link_changed;$/;" m class:soclib::caba::VciEthernet access:private +_link_check_counter /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _link_check_counter;$/;" m class:soclib::caba::VciEthernet access:private +_link_irq_en /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool _link_irq_en;$/;" m class:soclib::caba::VciEthernet access:private +_link_up /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool _link_up;$/;" m class:soclib::caba::VciEthernet access:private +_mac /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ uint8_t _mac[6];$/;" m class:soclib::caba::VciEthernet access:private +_rx_count /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _rx_count; \/\/< total number of rx buffers$/;" m class:soclib::caba::VciEthernet access:private +_rx_done /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _rx_done; \/\/< number of rx buffers ready to pop$/;" m class:soclib::caba::VciEthernet access:private +_rx_fifo /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ fifo_entry_t _rx_fifo[VCI_ETHERNET_FIFO_SIZE];$/;" m class:soclib::caba::VciEthernet access:private +_rx_free /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _rx_free; \/\/< number of yet unused rx buffers$/;" m class:soclib::caba::VciEthernet access:private +_rx_irq_en /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool _rx_irq_en;$/;" m class:soclib::caba::VciEthernet access:private +_rx_size /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ uint32_t _rx_size; \/\/< next rx buffer size$/;" m class:soclib::caba::VciEthernet access:private +_rx_start /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _rx_start; \/\/< index of first available rx buffer$/;" m class:soclib::caba::VciEthernet access:private +_soft_reset /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool _soft_reset;$/;" m class:soclib::caba::VciEthernet access:private +_tap_ifr /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ struct ifreq _tap_ifr;$/;" m class:soclib::caba::VciEthernet typeref:struct:soclib::caba::VciEthernet::ifreq access:private +_tx_count /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _tx_count; \/\/< total number of tx buffers$/;" m class:soclib::caba::VciEthernet access:private +_tx_done /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _tx_done; \/\/< number of tx buffers ready to pop$/;" m class:soclib::caba::VciEthernet access:private +_tx_fifo /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ fifo_entry_t _tx_fifo[VCI_ETHERNET_FIFO_SIZE];$/;" m class:soclib::caba::VciEthernet access:private +_tx_irq_en /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool _tx_irq_en;$/;" m class:soclib::caba::VciEthernet access:private +_tx_size /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ uint32_t _tx_size; \/\/< next tx buffer size$/;" m class:soclib::caba::VciEthernet access:private +_tx_start /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _tx_start; \/\/< index of first tx buffer$/;" m class:soclib::caba::VciEthernet access:private +_tx_waiting /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _tx_waiting; \/\/< number of yet unprocessed tx buffers$/;" m class:soclib::caba::VciEthernet access:private +addr /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ uint32_t addr;$/;" m struct:soclib::caba::VciEthernet::fifo_entry_t access:public +caba /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^namespace caba {$/;" n namespace:soclib +caba /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^namespace soclib { namespace caba {$/;" n namespace:soclib file: +cleanup_fifos /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ void cleanup_fifos();$/;" p class:soclib::caba::VciEthernet access:private signature:() +data /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ uint8_t *data;$/;" m struct:soclib::caba::VciEthernet::fifo_entry_t access:public +dma_offset /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int dma_offset;$/;" m struct:soclib::caba::VciEthernet::fifo_entry_t access:public +ended /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ inline void ended(int status);$/;" p class:soclib::caba::VciEthernet access:private signature:(int status) +fifo_entry_t /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ struct fifo_entry_t$/;" s class:soclib::caba::VciEthernet access:private +genMoore /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ void genMoore();$/;" p class:soclib::caba::VciEthernet access:private signature:() +m_vci_init_fsm /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ soclib::caba::VciInitiatorFsm m_vci_init_fsm;$/;" m class:soclib::caba::VciEthernet access:private +m_vci_target_fsm /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ soclib::caba::VciTargetFsm m_vci_target_fsm;$/;" m class:soclib::caba::VciEthernet access:private +on_read /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool on_read(int seg, typename vci_param::addr_t addr, typename vci_param::data_t &data);$/;" p class:soclib::caba::VciEthernet access:private signature:(int seg, typename vci_param::addr_t addr, typename vci_param::data_t &data) +on_write /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool on_write(int seg, typename vci_param::addr_t addr, typename vci_param::data_t data, int be);$/;" p class:soclib::caba::VciEthernet access:private signature:(int seg, typename vci_param::addr_t addr, typename vci_param::data_t data, int be) +p_clk /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ sc_in p_clk;$/;" m class:soclib::caba::VciEthernet access:public +p_irq /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ sc_out p_irq;$/;" m class:soclib::caba::VciEthernet access:public +p_resetn /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ sc_in p_resetn;$/;" m class:soclib::caba::VciEthernet access:public +p_vci_initiator /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ soclib::caba::VciInitiator p_vci_initiator;$/;" m class:soclib::caba::VciEthernet access:public +p_vci_target /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ soclib::caba::VciTarget p_vci_target;$/;" m class:soclib::caba::VciEthernet access:public +rd_req /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ VciInitSimpleReadReq *rd_req;$/;" m union:soclib::caba::VciEthernet::fifo_entry_t::__anon1 access:public +read_finish /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ void read_finish( req_t *req );$/;" p class:soclib::caba::VciEthernet access:private signature:( req_t *req ) +req_t /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ typedef typename soclib::caba::VciInitiatorReq req_t;$/;" t class:soclib::caba::VciEthernet access:private +size /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ uint32_t size;$/;" m struct:soclib::caba::VciEthernet::fifo_entry_t access:public +soclib /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^namespace soclib {$/;" n +soclib /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^namespace soclib { namespace caba {$/;" n file: +soclib::caba /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^namespace caba {$/;" n namespace:soclib +soclib::caba /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^namespace soclib { namespace caba {$/;" n namespace:soclib file: +soclib::caba::VciEthernet /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^class VciEthernet$/;" c namespace:soclib::caba inherits:caba::BaseModule +soclib::caba::VciEthernet::SC_HAS_PROCESS /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ SC_HAS_PROCESS(VciEthernet);$/;" p class:soclib::caba::VciEthernet access:protected signature:(VciEthernet) +soclib::caba::VciEthernet::VciEthernet /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ VciEthernet(sc_module_name name, const soclib::common::MappingTable &mt,$/;" p class:soclib::caba::VciEthernet access:public signature:(sc_module_name name, const soclib::common::MappingTable &mt, const soclib::common::IntTab &srcid, const soclib::common::IntTab &tgtid, const std::string &if_name = Ó) +soclib::caba::VciEthernet::_dma_busy /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool _dma_busy;$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_fd /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _fd;$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_link_changed /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool _link_changed;$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_link_check_counter /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _link_check_counter;$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_link_irq_en /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool _link_irq_en;$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_link_up /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool _link_up;$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_mac /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ uint8_t _mac[6];$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_rx_count /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _rx_count; \/\/< total number of rx buffers$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_rx_done /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _rx_done; \/\/< number of rx buffers ready to pop$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_rx_fifo /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ fifo_entry_t _rx_fifo[VCI_ETHERNET_FIFO_SIZE];$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_rx_free /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _rx_free; \/\/< number of yet unused rx buffers$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_rx_irq_en /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool _rx_irq_en;$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_rx_size /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ uint32_t _rx_size; \/\/< next rx buffer size$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_rx_start /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _rx_start; \/\/< index of first available rx buffer$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_soft_reset /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool _soft_reset;$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_tap_ifr /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ struct ifreq _tap_ifr;$/;" m class:soclib::caba::VciEthernet typeref:struct:soclib::caba::VciEthernet::ifreq access:private +soclib::caba::VciEthernet::_tx_count /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _tx_count; \/\/< total number of tx buffers$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_tx_done /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _tx_done; \/\/< number of tx buffers ready to pop$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_tx_fifo /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ fifo_entry_t _tx_fifo[VCI_ETHERNET_FIFO_SIZE];$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_tx_irq_en /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool _tx_irq_en;$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_tx_size /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ uint32_t _tx_size; \/\/< next tx buffer size$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_tx_start /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _tx_start; \/\/< index of first tx buffer$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::_tx_waiting /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int _tx_waiting; \/\/< number of yet unprocessed tx buffers$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::cleanup_fifos /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ void cleanup_fifos();$/;" p class:soclib::caba::VciEthernet access:private signature:() +soclib::caba::VciEthernet::ended /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ inline void ended(int status);$/;" p class:soclib::caba::VciEthernet access:private signature:(int status) +soclib::caba::VciEthernet::fifo_entry_t /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ struct fifo_entry_t$/;" s class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::fifo_entry_t::__anon1::rd_req /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ VciInitSimpleReadReq *rd_req;$/;" m union:soclib::caba::VciEthernet::fifo_entry_t::__anon1 access:public +soclib::caba::VciEthernet::fifo_entry_t::__anon1::wr_req /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ VciInitSimpleWriteReq *wr_req;$/;" m union:soclib::caba::VciEthernet::fifo_entry_t::__anon1 access:public +soclib::caba::VciEthernet::fifo_entry_t::addr /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ uint32_t addr;$/;" m struct:soclib::caba::VciEthernet::fifo_entry_t access:public +soclib::caba::VciEthernet::fifo_entry_t::data /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ uint8_t *data;$/;" m struct:soclib::caba::VciEthernet::fifo_entry_t access:public +soclib::caba::VciEthernet::fifo_entry_t::dma_offset /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ int dma_offset;$/;" m struct:soclib::caba::VciEthernet::fifo_entry_t access:public +soclib::caba::VciEthernet::fifo_entry_t::size /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ uint32_t size;$/;" m struct:soclib::caba::VciEthernet::fifo_entry_t access:public +soclib::caba::VciEthernet::fifo_entry_t::status /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ uint32_t status;$/;" m struct:soclib::caba::VciEthernet::fifo_entry_t access:public +soclib::caba::VciEthernet::genMoore /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ void genMoore();$/;" p class:soclib::caba::VciEthernet access:private signature:() +soclib::caba::VciEthernet::m_vci_init_fsm /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ soclib::caba::VciInitiatorFsm m_vci_init_fsm;$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::m_vci_target_fsm /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ soclib::caba::VciTargetFsm m_vci_target_fsm;$/;" m class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::on_read /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool on_read(int seg, typename vci_param::addr_t addr, typename vci_param::data_t &data);$/;" p class:soclib::caba::VciEthernet access:private signature:(int seg, typename vci_param::addr_t addr, typename vci_param::data_t &data) +soclib::caba::VciEthernet::on_write /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ bool on_write(int seg, typename vci_param::addr_t addr, typename vci_param::data_t data, int be);$/;" p class:soclib::caba::VciEthernet access:private signature:(int seg, typename vci_param::addr_t addr, typename vci_param::data_t data, int be) +soclib::caba::VciEthernet::p_clk /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ sc_in p_clk;$/;" m class:soclib::caba::VciEthernet access:public +soclib::caba::VciEthernet::p_irq /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ sc_out p_irq;$/;" m class:soclib::caba::VciEthernet access:public +soclib::caba::VciEthernet::p_resetn /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ sc_in p_resetn;$/;" m class:soclib::caba::VciEthernet access:public +soclib::caba::VciEthernet::p_vci_initiator /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ soclib::caba::VciInitiator p_vci_initiator;$/;" m class:soclib::caba::VciEthernet access:public +soclib::caba::VciEthernet::p_vci_target /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ soclib::caba::VciTarget p_vci_target;$/;" m class:soclib::caba::VciEthernet access:public +soclib::caba::VciEthernet::read_finish /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ void read_finish( req_t *req );$/;" p class:soclib::caba::VciEthernet access:private signature:( req_t *req ) +soclib::caba::VciEthernet::req_t /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ typedef typename soclib::caba::VciInitiatorReq req_t;$/;" t class:soclib::caba::VciEthernet access:private +soclib::caba::VciEthernet::transition /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ void transition();$/;" p class:soclib::caba::VciEthernet access:private signature:() +soclib::caba::VciEthernet::write_finish /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ void write_finish( req_t *req );$/;" p class:soclib::caba::VciEthernet access:private signature:( req_t *req ) +soclib::caba::VciEthernet::~VciEthernet /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ ~VciEthernet();$/;" p class:soclib::caba::VciEthernet access:public signature:() +soclib::caba::tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(\/**\/)::VciEthernet(sc_module_name name, const MappingTable &mt,$/;" f namespace:soclib::caba signature:( ) +soclib::caba::tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(\/**\/)::~VciEthernet()$/;" f namespace:soclib::caba signature:( ) +soclib::caba::tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(bool)::on_read(int seg, typename vci_param::addr_t addr, typename vci_param::data_t &data)$/;" f namespace:soclib::caba signature:(bool) +soclib::caba::tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(bool)::on_write(int seg, typename vci_param::addr_t addr, typename vci_param::data_t data, int be)$/;" f namespace:soclib::caba signature:(bool) +soclib::caba::tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(void)::cleanup_fifos()$/;" f namespace:soclib::caba signature:(void) +soclib::caba::tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(void)::genMoore()$/;" f namespace:soclib::caba signature:(void) +soclib::caba::tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(void)::read_finish( req_t *req )$/;" f namespace:soclib::caba signature:(void) +soclib::caba::tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(void)::transition()$/;" f namespace:soclib::caba signature:(void) +soclib::caba::tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(void)::write_finish( req_t *req )$/;" f namespace:soclib::caba signature:(void) +status /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ uint32_t status;$/;" m struct:soclib::caba::VciEthernet::fifo_entry_t access:public +tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(\/**\/)::VciEthernet(sc_module_name name, const MappingTable &mt,$/;" f namespace:soclib::caba signature:( ) +tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(\/**\/)::~VciEthernet()$/;" f namespace:soclib::caba signature:( ) +tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(bool)::on_read(int seg, typename vci_param::addr_t addr, typename vci_param::data_t &data)$/;" f namespace:soclib::caba signature:(bool) +tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(bool)::on_write(int seg, typename vci_param::addr_t addr, typename vci_param::data_t data, int be)$/;" f namespace:soclib::caba signature:(bool) +tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(void)::cleanup_fifos()$/;" f namespace:soclib::caba signature:(void) +tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(void)::genMoore()$/;" f namespace:soclib::caba signature:(void) +tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(void)::read_finish( req_t *req )$/;" f namespace:soclib::caba signature:(void) +tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(void)::transition()$/;" f namespace:soclib::caba signature:(void) +tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp /^ tmpl(void)::write_finish( req_t *req )$/;" f namespace:soclib::caba signature:(void) +tmpl /home/lambert/Documents/stage/almos-tsarv5/tsar_almos_generic_xbar_mono/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp 47;" d file: +transition /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ void transition();$/;" p class:soclib::caba::VciEthernet access:private signature:() +wr_req /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ VciInitSimpleWriteReq *wr_req;$/;" m union:soclib::caba::VciEthernet::fifo_entry_t::__anon1 access:public +write_finish /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ void write_finish( req_t *req );$/;" p class:soclib::caba::VciEthernet access:private signature:( req_t *req ) +~VciEthernet /home/lambert/Documents/Stage/almos-tsarv5/tsar_almos_generic_xbar_mono_vci_ethernet/vci_ethernet_tsar/caba/source/include/vci_ethernet.h /^ ~VciEthernet();$/;" p class:soclib::caba::VciEthernet access:public signature:() Index: /branches/fault_tolerance/modules/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp =================================================================== --- /branches/fault_tolerance/modules/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp (revision 724) +++ /branches/fault_tolerance/modules/vci_ethernet_tsar/caba/source/src/vci_ethernet.cpp (revision 724) @@ -0,0 +1,478 @@ +/* -*- c++ -*- + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Copyright (c) Telecom ParisTech + * Alexandre Becoulet , 2012 + * + * Maintainers: becoulet + */ + +#include +#include +#include +#include +#include + +#include + +#include "register.h" +#include "../include/vci_ethernet.h" +#include "ethernet.h" + +#define CHUNCK_SIZE (64) // Width of a cache line +#define CHUNCK_MASK ((~0ULL) << (6)) // MASK of a cache line + +//#define SOCLIB_MODULE_DEBUG + +namespace soclib { namespace caba { + +#define tmpl(t) template t VciEthernet + + tmpl(bool)::on_write(int seg, typename vci_param::addr_t addr, typename vci_param::data_t data, int be) + { + int cell = (int)addr / vci_param::B; + +#ifdef SOCLIB_MODULE_DEBUG + std::cout + << name() + << ": write config register " + << cell + << " with data 0x" + << std::hex << data + << std::dec + << std::endl; +#endif + + fifo_entry_t *f; + + switch ((enum SoclibEthernetRegisters)cell) + { + case ETHERNET_TX_SIZE: + _tx_size = std::min((int)data, VCI_ETHERNET_MAX_PKT_SIZE); + return true; + + case ETHERNET_TX_FIFO: + if (_tx_count >= VCI_ETHERNET_FIFO_SIZE) { + std::cout << name() << ": TX fifo full, can not push more packets!" << std::endl; + return false; + } + + f = _tx_fifo + (_tx_start + _tx_count++) % VCI_ETHERNET_FIFO_SIZE; + _tx_waiting++; + + f->addr = data; + f->size = _tx_size; + f->status = 0; + f->data = (uint8_t*)malloc(_tx_size); + return true; + + case ETHERNET_RX_SIZE: + _rx_size = std::min((int)data, VCI_ETHERNET_MAX_PKT_SIZE); + return true; + + case ETHERNET_RX_FIFO: + if (_rx_count >= VCI_ETHERNET_FIFO_SIZE) { + std::cout << name() << ": RX fifo full, can not push more packet buffers!" << std::endl; + return false; + } + + f = _rx_fifo + (_rx_start + _rx_count++) % VCI_ETHERNET_FIFO_SIZE; + _rx_free++; + + f->addr = data; + f->size = _rx_size; + f->status = 0; + f->data = (uint8_t*)malloc(_rx_size); + return true; + + case ETHERNET_CTRL: + if (data & ETHERNET_CTRL_RESET) + _soft_reset = true; + if (data & ETHERNET_CTRL_TX_IRQ) + _tx_irq_en = true; + else + _tx_irq_en = false; + if (data & ETHERNET_CTRL_RX_IRQ) + _rx_irq_en = true; + else + _rx_irq_en = false; + if (data & ETHERNET_CTRL_LINK_IRQ) + _link_irq_en = true; + else + _link_irq_en = false; + return true; + + default: + return false; + } + } + + tmpl(bool)::on_read(int seg, typename vci_param::addr_t addr, typename vci_param::data_t &data) + { + int cell = (int)addr / vci_param::B; + +#ifdef SOCLIB_MODULE_DEBUG + std::cout + << name() + << ": read config register " + << cell + << std::endl; +#endif + + fifo_entry_t *f; + + switch ((enum SoclibEthernetRegisters)cell) { + case ETHERNET_TX_FIFO: + if (_tx_done == 0) { + data = 0; + } else { + f = _tx_fifo + _tx_start++ % VCI_ETHERNET_FIFO_SIZE; + _tx_count--; + _tx_done--; + data = f->status; + free(f->data); + } + return true; + + case ETHERNET_RX_SIZE: + if (_rx_done == 0) { + data = 0; + } else { + f = _rx_fifo + _rx_start % VCI_ETHERNET_FIFO_SIZE; + data = f->size; + } + return true; + + case ETHERNET_RX_FIFO: + if (_rx_done == 0) { + data = 0; + } else { + f = _rx_fifo + _rx_start++ % VCI_ETHERNET_FIFO_SIZE; + _rx_count--; + _rx_done--; + free(f->data); + data = f->status; + } + return true; + + case ETHERNET_STATUS: + data = 0; + _link_changed = false; + if (_link_up) + data |= ETHERNET_ST_LINK_UP; + if (_rx_done > 0) + data |= ETHERNET_ST_RX_DONE; + if (_tx_done > 0) + data |= ETHERNET_ST_TX_DONE; + return true; + + case ETHERNET_FIFO_SIZE: + data = VCI_ETHERNET_FIFO_SIZE; + return true; + + case ETHERNET_MAC_LOW: + data = _mac[0] | (_mac[1] << 8) | (_mac[2] << 16) | (_mac[3] << 24); + return true; + + case ETHERNET_MAC_HIGH: + data = _mac[4] | (_mac[5] << 8); + return true; + + default: + return false; + } + } + + tmpl(void)::write_finish( req_t *req ) + { + fifo_entry_t *f = _rx_fifo + (_rx_start + _rx_count - _rx_free - 1) % VCI_ETHERNET_FIFO_SIZE; + + assert(req == f->rd_req); + delete req; + + if (req->failed()) { + std::cout << name() << ": RX dma write error for packet @" << f->addr << std::endl; + f->status = ETHERNET_RX_DMA_ERR; + _rx_done++; + _dma_busy = false; + + } else if ((unsigned)f->dma_offset >= f->size) { +#ifdef SOCLIB_MODULE_DEBUG + std::cout << name() << ": RX dma done for packet @" << f->addr << std::endl; +#endif + f->status = ETHERNET_RX_DONE; + _rx_done++; + _dma_busy = false; + + } else { + int chunck_size = std::min((unsigned)CHUNCK_SIZE, f->size - f->dma_offset); + f->wr_req = new VciInitSimpleWriteReq(f->addr + f->dma_offset, f->data + f->dma_offset, chunck_size); + f->dma_offset += chunck_size; + f->wr_req->setDone(this, ON_T(write_finish)); + f->wr_req->setPacket(0x4); + m_vci_init_fsm.doReq(f->wr_req); + } + } + + tmpl(void)::read_finish( req_t *req ) + { + fifo_entry_t *f = _tx_fifo + (_tx_start + _tx_count - _tx_waiting - 1) % VCI_ETHERNET_FIFO_SIZE; + + assert(req == f->rd_req); + delete req; + + if (req->failed()) { + std::cout << name() << ": TX dma read error for packet @" << f->addr << std::endl; + f->status = ETHERNET_TX_DMA_ERR; + _tx_done++; + _dma_busy = false; + + } else if ((unsigned)f->dma_offset >= f->size) { +#ifdef SOCLIB_MODULE_DEBUG + std::cout << name() << ": TX dma done for packet @" << f->addr << std::endl; +#endif + f->status = ETHERNET_TX_DONE; + + if (!_link_up || ::write(_fd, f->data, f->size) != f->size) { + std::cout << name() << ": TX tap write error for packet @" << f->addr << std::endl; + f->status = ETHERNET_TX_PHY_ERR; + _link_check_counter = 1; + } + + _tx_done++; + _dma_busy = false; + + } else { + int chunck_size = std::min((unsigned)CHUNCK_SIZE, f->size - f->dma_offset); + f->rd_req = new VciInitSimpleReadReq(f->data + f->dma_offset, f->addr + f->dma_offset, chunck_size); + f->dma_offset += chunck_size; + f->rd_req->setDone(this, ON_T(read_finish)); + m_vci_init_fsm.doReq(f->rd_req); + } + } + + tmpl(void)::cleanup_fifos() + { + for (int i = 0; i < _rx_count; i++) { + fifo_entry_t *f = _rx_fifo + (_rx_start + i) % VCI_ETHERNET_FIFO_SIZE; + free(f->data); + } + + for (int i = 0; i < _tx_count; i++) { + fifo_entry_t *f = _tx_fifo + (_tx_start + i) % VCI_ETHERNET_FIFO_SIZE; + free(f->data); + } + } + + tmpl(void)::transition() + { + if (!p_resetn || _soft_reset) { + m_vci_target_fsm.reset(); + m_vci_init_fsm.reset(); + _soft_reset = false; + + cleanup_fifos(); + + _rx_start = _rx_free = _rx_done = _rx_count = 0; + _tx_start = _tx_waiting = _tx_done = _tx_count = 0; + _rx_irq_en = _tx_irq_en = _link_irq_en = false; + _link_check_counter = 1; + _link_changed = _link_up = false; + _dma_busy = false; + return; + } + + if (_fd >= 0 && --_link_check_counter <= 0) { + _link_check_counter = 100000; + + int sock = socket(AF_INET, SOCK_DGRAM, 0); + + if (sock >= 0) { + if (ioctl(sock, SIOCGIFFLAGS, &_tap_ifr) < 0) { + std::cout << name() << ": link status check error: " << _tap_ifr.ifr_flags << std::endl; + } else if (_link_up != !!(_tap_ifr.ifr_flags & IFF_UP)) { + _link_up = !_link_up; + _link_changed = true; +#ifdef SOCLIB_MODULE_DEBUG + std::cout << name() << ": link status changed to: " << (_link_up ? "up" : "down") << std::endl; +#endif + } + close(sock); + } + } + + if (!_dma_busy) { + + if (_tx_waiting > 0) { + + fifo_entry_t *f = _tx_fifo + (_tx_start + _tx_count - _tx_waiting--) % VCI_ETHERNET_FIFO_SIZE; + + // start DMA read + int chunck_size = std::min((unsigned)CHUNCK_SIZE, f->size); + if ((f->addr & CHUNCK_MASK) != ((f->addr + chunck_size) & CHUNCK_MASK)) { + chunck_size = ((f->addr & CHUNCK_MASK) + CHUNCK_SIZE) - f->addr; + } + f->rd_req = new VciInitSimpleReadReq(f->data, f->addr, chunck_size); + f->dma_offset = chunck_size; + f->rd_req->setDone(this, ON_T(read_finish)); + m_vci_init_fsm.doReq(f->rd_req); + _dma_busy = true; + +#ifdef SOCLIB_MODULE_DEBUG + std::cout << name() << ": started TX dma read @" << f->addr << ", " << f->size << " bytes " << std::endl; +#endif + } else if (_rx_free > 0 && _link_up) { + + fifo_entry_t *f = _rx_fifo + (_rx_start + _rx_count - _rx_free) % VCI_ETHERNET_FIFO_SIZE; + int rd = ::read(_fd, f->data, f->size); + + if (rd < 0 && errno != EAGAIN) { + f->status = ETHERNET_RX_PHY_ERR; + _rx_done++; + std::cout << name() << ": tap read error on RX" << std::endl; + _link_check_counter = 1; + + } else if (rd > 0) { + if (_rx_free > 0) { + f->size = rd; + _rx_free--; + + // start DMA write + int chunck_size = std::min((unsigned)CHUNCK_SIZE, f->size); + if ((f->addr & CHUNCK_MASK) != ((f->addr + chunck_size) & CHUNCK_MASK)) { + chunck_size = ((f->addr & CHUNCK_MASK) + CHUNCK_SIZE) - f->addr; + } + f->wr_req = new VciInitSimpleWriteReq(f->addr, f->data, chunck_size); + f->dma_offset = chunck_size; + f->wr_req->setDone(this, ON_T(write_finish)); + f->wr_req->setPacket(0x4); + m_vci_init_fsm.doReq(f->wr_req); + _dma_busy = true; + +#ifdef SOCLIB_MODULE_DEBUG + std::cout << name() << ": started RX dma write @" << f->addr << ", " << f->size << " bytes " << std::endl; +#endif + } + else { + std::cout << name() << ": No rx buffer free so paquet is dropped" << std::endl; + } + } + } + } + + m_vci_target_fsm.transition(); + m_vci_init_fsm.transition(); + } + + tmpl(void)::genMoore() + { + m_vci_target_fsm.genMoore(); + m_vci_init_fsm.genMoore(); + + p_irq = (_rx_irq_en && _rx_done > 0) || (_tx_irq_en && _tx_done > 0) || (_link_changed && _link_irq_en); + } + + tmpl(/**/)::VciEthernet(sc_module_name name, const MappingTable &mt, + const IntTab &srcid, const IntTab &tgtid, + const std::string &if_name) + : caba::BaseModule(name), + m_vci_target_fsm(p_vci_target, mt.getSegmentList(tgtid)), + m_vci_init_fsm(p_vci_initiator, mt.indexForId(srcid)), + p_clk("clk"), + p_resetn("resetn"), + p_vci_target("vci_target"), + p_vci_initiator("vci_initiator"), + p_irq("irq") + { + m_vci_target_fsm.on_read_write(on_read, on_write); + _fd = open("/dev/net/tun", O_RDWR); + + if ( _fd < 0 ) { + std::cerr << name << ": Unable to open /dev/net/tun" << std::endl; + } else { + int flags = fcntl(_fd, F_GETFL, 0); + fcntl(_fd, F_SETFL, flags | O_NONBLOCK); + + memset((void*)&_tap_ifr, 0, sizeof(_tap_ifr)); + _tap_ifr.ifr_flags = IFF_TAP | IFF_NO_PI; + strncpy(_tap_ifr.ifr_name, if_name.c_str(), IFNAMSIZ); + + + if (ioctl(_fd, TUNSETIFF, (void *) &_tap_ifr) < 0) { + close(_fd); + _fd = -1; + std::cerr << name << ": Unable to setup tap interface, check privileges." +#ifdef __linux__ + << " (try: sudo setcap cap_net_admin=eip ./system.x)" +#endif + << std::endl; + } + flags = 2; + if (ioctl(_fd, TUNSETDEBUG, (void *) &flags) < 0) { + std::cerr << "Warning couldn't use debug option for TAP" << std::endl; + } + + /* ioctl(_fd, SIOCGIFHWADDR, &_tap_ifr); + memcpy(_mac, _tap_ifr.ifr_hwaddr.sa_data, 6);*/ + srand(time(0) * getpid()); + _mac[0] = 0x00; + _mac[1] = 0x16; + _mac[2] = 0x3e; + _mac[3] = rand(); + _mac[4] = rand(); + _mac[5] = rand(); + } + + _link_check_counter = 1; + _rx_start = _rx_free = _rx_done = _rx_count = 0; + _tx_start = _tx_waiting = _tx_done = _tx_count = 0; + _dma_busy = false; + _link_up = false; + + SC_METHOD(transition); + dont_initialize(); + sensitive << p_clk.pos(); + + SC_METHOD(genMoore); + dont_initialize(); + sensitive << p_clk.neg(); + } + + tmpl(/**/)::~VciEthernet() + { + cleanup_fifos(); + + if (_fd >= 0) + close(_fd); + } + +}} + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: /branches/fault_tolerance/modules/vci_ethernet_tsar/doc/README =================================================================== --- /branches/fault_tolerance/modules/vci_ethernet_tsar/doc/README (revision 724) +++ /branches/fault_tolerance/modules/vci_ethernet_tsar/doc/README (revision 724) @@ -0,0 +1,10 @@ +This files describes the differences between vci_ethernet_tsar and +vci_ethernet + +* Added f->wr_req->setPacket(0x4); for every Write command from vci_ethernet in + order to respect overloading of vci CMD in pktid of Tsar architecture + +* Added overlapping detection in read and write vci CMD. First, vci CMD is now + made at maximum with the boundary of a cache line (64 alignement) + +* Added set and reset for IRQ lines enable Index: /branches/fault_tolerance/modules/vci_ethernet_tsar/include/soclib/ethernet.h =================================================================== --- /branches/fault_tolerance/modules/vci_ethernet_tsar/include/soclib/ethernet.h (revision 724) +++ /branches/fault_tolerance/modules/vci_ethernet_tsar/include/soclib/ethernet.h (revision 724) @@ -0,0 +1,83 @@ +/* + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Copyright (c) Telecom ParisTech + * Alexandre Becoulet , 2012 + * + * Maintainers: becoulet + */ + +#ifndef ETHERNET_REGS_H +#define ETHERNET_REGS_H + +enum SoclibEthernetRegisters { + ETHERNET_TX_SIZE = 0, /*< on write: set size of packet to send for next adress push */ + ETHERNET_TX_FIFO = 1, /*< on write: push address and size of packet to send on tx fifo, + on read: pop status of sent packet from tx fifo. 0 if empty */ + ETHERNET_RX_SIZE = 2, /*< on write: set size of rx buffer for next adress push, + on read: get size of last rx packet, 0 if empty. */ + ETHERNET_RX_FIFO = 3, /*< on write: push address and size of buffer on rx fifo, + on read: pop status of last rx packet. 0 if empty */ + ETHERNET_STATUS = 4, /*< on read: contains device status flags */ + ETHERNET_CTRL = 4, /*< on write: device control actions */ + ETHERNET_FIFO_SIZE = 5, /*< contains size of TX & RX FIFOs */ + ETHERNET_MAC_LOW = 6, /*< contains mac address bytes 0, 1, 2 and 3 */ + ETHERNET_MAC_HIGH = 7, /*< contains mac address bytes 4 and 5 */ +}; + +enum SoclibEthernetRxStatus { + ETHERNET_RX_EMPTY = 0, + ETHERNET_RX_DONE = 1, + ETHERNET_RX_DMA_ERR = 2, + ETHERNET_RX_PHY_ERR = 3, +}; + +enum SoclibEthernetTxStatus { + ETHERNET_TX_EMPTY = 0, + ETHERNET_TX_DONE = 1, + ETHERNET_TX_DMA_ERR = 2, + ETHERNET_TX_PHY_ERR = 3, +}; + +enum SoclibEthernetStatus { + ETHERNET_ST_LINK_UP = 1, + ETHERNET_ST_TX_DONE = 2, /*< The ETHERNET_TX_FIFO register content is valid */ + ETHERNET_ST_RX_DONE = 4, /*< The ETHERNET_RX_FIFO register content is valid */ +}; + +enum SoclibEthernetCtrl { + ETHERNET_CTRL_RESET = 1, //< fifos become empty, disable interrupts + ETHERNET_CTRL_TX_IRQ = 2, //< enable TX irq when written to 1 + ETHERNET_CTRL_RX_IRQ = 4, //< enable RX irq when written to 1 + ETHERNET_CTRL_LINK_IRQ = 8, //< enable link status change irq when written to 1 +}; + +#endif /* ETHERNET_REGS_H */ + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: /branches/fault_tolerance/modules/vci_io_bridge/caba/metadata/vci_io_bridge.sd =================================================================== --- /branches/fault_tolerance/modules/vci_io_bridge/caba/metadata/vci_io_bridge.sd (revision 724) +++ /branches/fault_tolerance/modules/vci_io_bridge/caba/metadata/vci_io_bridge.sd (revision 724) @@ -0,0 +1,66 @@ + +# -*- python -*- + +__id__ = "$Id: vci_io_bridge.sd 20 2012-6-11 $" + +Module('caba:vci_io_bridge', + classname = 'soclib::caba::VciIoBridge', + + tmpl_parameters = [ + parameter.Module('vci_param_int', + default = 'caba:vci_param', + cell_size = parameter.Reference('iob_cell_size_int')), + parameter.Module('vci_param_ext', + default = 'caba:vci_param', + cell_size = parameter.Reference('iob_cell_size_ext')), + ], + + header_files = [ + '../source/include/vci_io_bridge.h', + '../source/include/transaction_tab_io.h' + ], + + implementation_files = [ '../source/src/vci_io_bridge.cpp' ], + + uses = [ Uses('caba:base_module'), + Uses('common:mapping_table'), + Uses('caba:generic_fifo'), + Uses('caba:generic_tlb', + addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', + parameter.Reference('addr_size'))), + Uses('common:address_decoding_table', + input_t = 'unsigned long', + output_t = 'bool'), + Uses('common:address_decoding_table', + input_t = 'unsigned long', + output_t = 'int'), + ], + + ports = [ + Port('caba:vci_initiator', 'p_vci_ini_ram'), + Port('caba:vci_target', 'p_vci_tgt_iox'), + Port('caba:vci_initiator', 'p_vci_ini_iox'), + Port('caba:vci_target', 'p_vci_tgt_int'), + Port('caba:vci_initiator', 'p_vci_ini_int'), + Port('caba:bit_in','p_irq', 32), + Port('caba:bit_in', 'p_resetn', auto = 'resetn'), + Port('caba:clock_in', 'p_clk', auto = 'clock'), + ], + + instance_parameters = [ + parameter.Module('mt_ext', 'common:mapping_table'), + parameter.Module('mt_int', 'common:mapping_table'), + parameter.Module('mt_iox', 'common:mapping_table'), + parameter.IntTab('int_tgtid'), + parameter.IntTab('int_srcid'), + parameter.IntTab('iox_tgtid'), + parameter.IntTab('iox_srcid'), + parameter.IntTab('ext_srcid'), + parameter.Int('dcache_words'), + parameter.Int('iotlb_ways'), + parameter.Int('iotlb_sets'), + parameter.Int('debug_start_cycle'), + parameter.Bool('debug_ok'), + ], +) + Index: /branches/fault_tolerance/modules/vci_io_bridge/caba/source/include/transaction_tab_io.h =================================================================== --- /branches/fault_tolerance/modules/vci_io_bridge/caba/source/include/transaction_tab_io.h (revision 724) +++ /branches/fault_tolerance/modules/vci_io_bridge/caba/source/include/transaction_tab_io.h (revision 724) @@ -0,0 +1,227 @@ +#ifndef IOB_TRANSACTION_H_ +#define IOB_TRANSACTION_H_ + +#include +#include +#include +#include "arithmetics.h" + +#define DEBUG_IOB_TRANSACTION 0 + +//////////////////////////////////////////////////////////////////////// +// A transaction tab entry +//////////////////////////////////////////////////////////////////////// + +class TransactionTabIOEntry { + typedef uint32_t size_t; + + public: + bool valid; // valid entry + size_t srcid; // initiator requesting the transaction + size_t trdid; // thread ID of transaction + + ///////////////////////////////////////////////////////////////////// + // The init() function initializes the entry + ///////////////////////////////////////////////////////////////////// + void init() + { + valid = false; + } + + //////////////////////////////////////////////////////////////////// + // The copy() function copies an existing entry + // Its arguments are : + // - source : the transaction tab entry to copy + //////////////////////////////////////////////////////////////////// + void copy(const TransactionTabIOEntry &source) + { + valid = source.valid; + srcid = source.srcid; + trdid = source.trdid; + } + + //////////////////////////////////////////////////////////////////// + // The print() function prints the entry + //////////////////////////////////////////////////////////////////// + void print(){ + std::cout << " valid = " << valid << std::hex + << " / srcid = " << srcid + << " / trdid = " << trdid << std::dec + << std::endl; + } + + ///////////////////////////////////////////////////////////////////// + // Constructors + ///////////////////////////////////////////////////////////////////// + + TransactionTabIOEntry() + { + valid = false; + } + + TransactionTabIOEntry(const TransactionTabIOEntry &source){ + valid = source.valid; + srcid = source.srcid; + trdid = source.trdid; + } + +}; // end class TransactionTabIOEntry + +//////////////////////////////////////////////////////////////////////// +// The transaction tab +//////////////////////////////////////////////////////////////////////// +class TransactionTabIO{ + private: + const size_t size_tab; // The size of the tab + + public: + TransactionTabIOEntry *tab; // The transaction tab + + //////////////////////////////////////////////////////////////////// + // Constructors + //////////////////////////////////////////////////////////////////// + TransactionTabIO(size_t n_entries) : size_tab(n_entries) + { + tab = new TransactionTabIOEntry[size_tab]; + } + + ~TransactionTabIO() + { + delete [] tab; + } + + ///////////////////////////////////////////////////////////////////// + // The size() function returns the size of the tab + ///////////////////////////////////////////////////////////////////// + const size_t& size() + { + return size_tab; + } + + ///////////////////////////////////////////////////////////////////// + // The init() function initializes the transaction tab entries + ///////////////////////////////////////////////////////////////////// + void init() + { + for ( size_t index = 0; index < size_tab; index++) + { + tab[index].init(); + } + } + + ///////////////////////////////////////////////////////////////////// + // The print() function prints a transaction tab entry + // Arguments : + // - index : the index of the entry to print + ///////////////////////////////////////////////////////////////////// + void print(const size_t index) + { + assert( (index < size_tab) && "Invalid Transaction Tab Entry"); + tab[index].print(); + return; + } + + ///////////////////////////////////////////////////////////////////// + // The printTrace() function prints all transaction tab entries + ///////////////////////////////////////////////////////////////////// + void printTrace() + { + for (size_t index = 0; index < size_tab; index++) + { + tab[index].print(); + } + } + + ///////////////////////////////////////////////////////////////////// + // The read() function returns a transaction tab entry. + // Arguments : + // - index : the index of the entry to read + ///////////////////////////////////////////////////////////////////// + TransactionTabIOEntry& read(const size_t index) + { + assert( (index < size_tab) && "Invalid Transaction Tab Entry"); + return tab[index]; + } + + ///////////////////////////////////////////////////////////////////// + // The readSrcid() function returns the srcid field of a transaction tab entry. + // Arguments : + // - index : the index of the entry to read + ///////////////////////////////////////////////////////////////////// + size_t readSrcid(const size_t index) + { + assert( (index < size_tab) && "Invalid Transaction Tab Entry"); + return tab[index].srcid; + } + + ///////////////////////////////////////////////////////////////////// + // The readTrdid() function returns the trdid field of a transaction tab entry. + // Arguments : + // - index : the index of the entry to read + ///////////////////////////////////////////////////////////////////// + size_t readTrdid(const size_t index) + { + assert( (index < size_tab) && "Invalid Transaction Tab Entry"); + return tab[index].trdid; + } + + ///////////////////////////////////////////////////////////////////// + // The full() function returns the state of the transaction tab + // Arguments : + // - index : (return argument) the index of an empty entry + // The function returns true if the transaction tab is full + ///////////////////////////////////////////////////////////////////// + bool full(size_t &index) + { + for(size_t i=0; i +#include +#include "caba_base_module.h" +#include "generic_fifo.h" +#include "generic_tlb.h" +#include "mapping_table.h" +#include "address_decoding_table.h" +#include "address_masking_table.h" +#include "static_assert.h" +#include "vci_initiator.h" +#include "vci_target.h" +#include "transaction_tab_io.h" +#include "../../../include/soclib/io_bridge.h" + +namespace soclib { +namespace caba { + +using namespace soclib::common; + +/////////////////////////////////////////////////////////////////////////////////// +template +class VciIoBridge +/////////////////////////////////////////////////////////////////////////////////// + : public soclib::caba::BaseModule +{ + // Data and be fields have different widths on INT and EXT/IOC networks + typedef typename vci_param_ext::data_t ext_data_t; + typedef typename vci_param_int::data_t int_data_t; + typedef typename vci_param_ext::be_t ext_be_t; + typedef typename vci_param_int::be_t int_be_t; + + // Other fields must be equal + typedef typename vci_param_int::fast_addr_t vci_addr_t; + typedef typename vci_param_int::srcid_t vci_srcid_t; + typedef typename vci_param_int::trdid_t vci_trdid_t; + typedef typename vci_param_int::pktid_t vci_pktid_t; + typedef typename vci_param_int::plen_t vci_plen_t; + typedef typename vci_param_int::cmd_t vci_cmd_t; + typedef typename vci_param_int::contig_t vci_contig_t; + typedef typename vci_param_int::eop_t vci_eop_t; + typedef typename vci_param_int::const_t vci_cons_t; + typedef typename vci_param_int::wrap_t vci_wrap_t; + typedef typename vci_param_int::clen_t vci_clen_t; + typedef typename vci_param_int::cfixed_t vci_cfixed_t; + typedef typename vci_param_int::rerror_t vci_rerror_t; + + enum + { + CACHE_LINE_MASK = 0xFFFFFFFFC0LL, + PPN1_MASK = 0x0007FFFF, + PPN2_MASK = 0x0FFFFFFF, + K_PAGE_OFFSET_MASK = 0x00000FFF, + M_PAGE_OFFSET_MASK = 0x001FFFFF, + PTE2_LINE_OFFSET = 0x00007000, // bits 12,13,14. + PTE1_LINE_OFFSET = 0x01E00000, // bits 21,22,23,24 + }; + + // States for DMA_CMD FSM (from IOX to RAM) + enum dma_cmd_fsm_state + { + DMA_CMD_IDLE, + DMA_CMD_DMA_REQ, + DMA_CMD_WTI_IOX_REQ, + DMA_CMD_ERR_WAIT_EOP, + DMA_CMD_ERR_WTI_REQ, + DMA_CMD_ERR_RSP_REQ, + DMA_CMD_TLB_MISS_WAIT, + }; + + // States for DMA_RSP FSM + enum dma_rsp_fsm_state + { + DMA_RSP_IDLE_DMA, + DMA_RSP_IDLE_WTI, + DMA_RSP_IDLE_ERR, + DMA_RSP_PUT_DMA, + DMA_RSP_PUT_WTI, + DMA_RSP_PUT_ERR, + }; + + // States for TLB_MISS FSM + enum dma_tlb_fsm_state + { + TLB_IDLE, + TLB_MISS, + TLB_PTE1_GET, + TLB_PTE1_SELECT, + TLB_PTE1_UPDT, + TLB_PTE2_GET, + TLB_PTE2_SELECT, + TLB_PTE2_UPDT, + TLB_WAIT, + TLB_RETURN, + TLB_INVAL_CHECK, + }; + + // States for CONFIG_CMD FSM + enum config_cmd_fsm_state + { + CONFIG_CMD_IDLE, + CONFIG_CMD_WAIT, + CONFIG_CMD_HI, + CONFIG_CMD_LO, + CONFIG_CMD_PUT, + CONFIG_CMD_RSP, + }; + + // states for CONFIG_RSP FSM + enum config_rsp_fsm_state + { + CONFIG_RSP_IDLE_IOX, + CONFIG_RSP_IDLE_LOC, + CONFIG_RSP_PUT_LO, + CONFIG_RSP_PUT_HI, + CONFIG_RSP_PUT_UNC, + CONFIG_RSP_PUT_LOC, + + }; + + // States for MISS_WTI_RSP FSM + enum miss_wti_rsp_state + { + MISS_WTI_RSP_IDLE, + MISS_WTI_RSP_WTI_IOX, + MISS_WTI_RSP_WTI_MMU, + MISS_WTI_RSP_MISS, + }; + + // PKTID values for TLB MISS and WTI transactions + enum pktid_values_e + { + PKTID_MISS = 0x0, // TSAR code for read data uncached + PKTID_WTI_IOX = 0x4, // TSAR code for write + PKTID_WTI_MMU = 0xC, // TSAR code for write + }; + + // Miss types for iotlb + enum tlb_miss_type_e + { + PTE1_MISS, + PTE2_MISS, + }; + +public: + sc_in p_clk; + sc_in p_resetn; + + soclib::caba::VciInitiator p_vci_ini_ram; + + soclib::caba::VciTarget p_vci_tgt_iox; + soclib::caba::VciInitiator p_vci_ini_iox; + + soclib::caba::VciTarget p_vci_tgt_int; + soclib::caba::VciInitiator p_vci_ini_int; + +private: + const size_t m_words; + + // INT & IOX Networks + std::list m_int_seglist; + const vci_srcid_t m_int_srcid; // SRCID on INT network + std::list m_iox_seglist; + const vci_srcid_t m_iox_srcid; // SRCID on IOX network + + // INT & RAM srcid masking table + const AddressMaskingTable m_srcid_gid_mask; + const AddressMaskingTable m_srcid_lid_mask; + + // TLB parameters + const size_t m_iotlb_ways; + const size_t m_iotlb_sets; + + // debug variables + uint32_t m_debug_start_cycle; + bool m_debug_ok; + bool m_debug_activated; + + /////////////////////////////// + // MEMORY MAPPED REGISTERS + /////////////////////////////// + sc_signal r_iommu_ptpr; // page table pointer + sc_signal r_iommu_active; // iotlb mode + sc_signal r_iommu_bvar; // bad vaddr + sc_signal r_iommu_etr; // error type + sc_signal r_iommu_bad_id; // faulty srcid + sc_signal r_iommu_wti_enable; // enable IOB WTI + sc_signal r_iommu_wti_addr_lo; // IOMMU WTI paddr (32 lsb) + sc_signal r_iommu_wti_addr_hi; // IOMMU WTI paddr (32 msb) + + /////////////////////////////////// + // DMA_CMD FSM REGISTERS + /////////////////////////////////// + sc_signal r_dma_cmd_fsm; + sc_signal r_dma_cmd_paddr; // output paddr + + sc_signal r_dma_cmd_to_miss_wti_cmd_req; + sc_signal r_dma_cmd_to_miss_wti_cmd_addr; + sc_signal r_dma_cmd_to_miss_wti_cmd_cmd; + sc_signal r_dma_cmd_to_miss_wti_cmd_srcid; + sc_signal r_dma_cmd_to_miss_wti_cmd_trdid; + sc_signal r_dma_cmd_to_miss_wti_cmd_pktid; + sc_signal r_dma_cmd_to_miss_wti_cmd_wdata; + + sc_signal r_dma_cmd_to_dma_rsp_req; + sc_signal r_dma_cmd_to_dma_rsp_rsrcid; + sc_signal r_dma_cmd_to_dma_rsp_rtrdid; + sc_signal r_dma_cmd_to_dma_rsp_rpktid; + sc_signal r_dma_cmd_to_dma_rsp_rerror; + sc_signal r_dma_cmd_to_dma_rsp_rdata; + + sc_signal r_dma_cmd_to_tlb_req; + sc_signal r_dma_cmd_to_tlb_vaddr; // input vaddr + + /////////////////////////////////// + // DMA_RSP FSM REGISTERS + /////////////////////////////////// + sc_signal r_dma_rsp_fsm; + + /////////////////////////////////// + // CONFIG_CMD FSM REGISTERS + /////////////////////////////////// + sc_signal r_config_cmd_fsm; + + sc_signal r_config_cmd_to_tlb_req; + sc_signal r_config_cmd_to_tlb_vaddr; + + sc_signal r_config_cmd_to_config_rsp_req; + sc_signal r_config_cmd_to_config_rsp_rerror; + sc_signal r_config_cmd_to_config_rsp_rdata; + sc_signal r_config_cmd_to_config_rsp_rsrcid; + sc_signal r_config_cmd_to_config_rsp_rtrdid; + sc_signal r_config_cmd_to_config_rsp_rpktid; + + sc_signal r_config_cmd_wdata; + sc_signal r_config_cmd_be; + sc_signal r_config_cmd_cmd; + sc_signal r_config_cmd_address; + sc_signal r_config_cmd_srcid; + sc_signal r_config_cmd_trdid; + sc_signal r_config_cmd_pktid; + sc_signal r_config_cmd_plen; + sc_signal r_config_cmd_clen; + sc_signal r_config_cmd_cons; + sc_signal r_config_cmd_contig; + sc_signal r_config_cmd_cfixed; + sc_signal r_config_cmd_wrap; + sc_signal r_config_cmd_eop; + + TransactionTabIO m_iox_transaction_tab; + + /////////////////////////////////// + // CONFIG_RSP FSM REGISTERS + /////////////////////////////////// + sc_signal r_config_rsp_fsm; + sc_signal r_config_rsp_rsrcid; + sc_signal r_config_rsp_rtrdid; + + /////////////////////////////////// + // TLB FSM REGISTERS + /////////////////////////////////// + sc_signal r_tlb_fsm; // state register + sc_signal r_waiting_transaction; // Flag for returning from + sc_signal r_tlb_miss_type; + sc_signal r_tlb_miss_error; + + sc_signal r_tlb_paddr; // physical address of pte + sc_signal r_tlb_pte_flags; // pte1 or first word of pte2 + sc_signal r_tlb_pte_ppn; // second word of pte2 + sc_signal r_tlb_way; // selected way in tlb + sc_signal r_tlb_set; // selected set in tlb + + uint32_t* r_tlb_buf_data; // prefetch buffer for PTEs + sc_signal r_tlb_buf_valid; // one valit flag for all PTEs + sc_signal r_tlb_buf_tag; // cache line number + sc_signal r_tlb_buf_vaddr; // vaddr for first PTE + sc_signal r_tlb_buf_big_page; // ??? + + sc_signal r_tlb_to_miss_wti_cmd_req; + + /////////////////////////////////// + // MISS_WTI_RSP FSM REGISTERS + /////////////////////////////////// + sc_signal r_miss_wti_rsp_fsm; + sc_signal r_miss_wti_rsp_error_wti; // VCI error on WTI + sc_signal r_miss_wti_rsp_error_miss; // VCI error on MISS + sc_signal r_miss_wti_rsp_count; // flits counter + + sc_signal r_miss_wti_rsp_to_dma_rsp_req; + sc_signal r_miss_wti_rsp_to_dma_rsp_rerror; + sc_signal r_miss_wti_rsp_to_dma_rsp_rsrcid; + sc_signal r_miss_wti_rsp_to_dma_rsp_rtrdid; + sc_signal r_miss_wti_rsp_to_dma_rsp_rpktid; + + + ///////////////////////////////////////////////////// + // ALLOCATORS for CONFIG_RSP fifo & DMA_RSP fifo + ///////////////////////////////////////////////////// + sc_signal r_alloc_fifo_config_rsp_local; + + + ////////////////////////////////////////////////////////////////// + // IOTLB + ////////////////////////////////////////////////////////////////// + GenericTlb r_iotlb; + + + ///////////////////////// + // FIFOs + ///////////////////////// + + // ouput FIFO to VCI INI port on RAM network (VCI command) + GenericFifo m_dma_cmd_addr_fifo; + GenericFifo m_dma_cmd_srcid_fifo; + GenericFifo m_dma_cmd_trdid_fifo; + GenericFifo m_dma_cmd_pktid_fifo; + GenericFifo m_dma_cmd_be_fifo; + GenericFifo m_dma_cmd_cmd_fifo; + GenericFifo m_dma_cmd_contig_fifo; + GenericFifo m_dma_cmd_data_fifo; + GenericFifo m_dma_cmd_eop_fifo; + GenericFifo m_dma_cmd_cons_fifo; + GenericFifo m_dma_cmd_plen_fifo; + GenericFifo m_dma_cmd_wrap_fifo; + GenericFifo m_dma_cmd_cfixed_fifo; + GenericFifo m_dma_cmd_clen_fifo; + + // output FIFO to VCI TGT port on IOX network (VCI response) + GenericFifo m_dma_rsp_data_fifo; + GenericFifo m_dma_rsp_rsrcid_fifo; + GenericFifo m_dma_rsp_rtrdid_fifo; + GenericFifo m_dma_rsp_rpktid_fifo; + GenericFifo m_dma_rsp_reop_fifo; + GenericFifo m_dma_rsp_rerror_fifo; + + // output FIFO to VCI INI port on IOX network (VCI command) + GenericFifo m_config_cmd_addr_fifo; + GenericFifo m_config_cmd_srcid_fifo; + GenericFifo m_config_cmd_trdid_fifo; + GenericFifo m_config_cmd_pktid_fifo; + GenericFifo m_config_cmd_be_fifo; + GenericFifo m_config_cmd_cmd_fifo; + GenericFifo m_config_cmd_contig_fifo; + GenericFifo m_config_cmd_data_fifo; + GenericFifo m_config_cmd_eop_fifo; + GenericFifo m_config_cmd_cons_fifo; + GenericFifo m_config_cmd_plen_fifo; + GenericFifo m_config_cmd_wrap_fifo; + GenericFifo m_config_cmd_cfixed_fifo; + GenericFifo m_config_cmd_clen_fifo; + + // output FIFO to VCI TGT port on INT network (VCI response) + GenericFifo m_config_rsp_data_fifo; + GenericFifo m_config_rsp_rsrcid_fifo; + GenericFifo m_config_rsp_rtrdid_fifo; + GenericFifo m_config_rsp_rpktid_fifo; + GenericFifo m_config_rsp_reop_fifo; + GenericFifo m_config_rsp_rerror_fifo; + + // output FIFO to VCI_INI port on INT network (VCI command) + GenericFifo m_miss_wti_cmd_addr_fifo; + GenericFifo m_miss_wti_cmd_srcid_fifo; + GenericFifo m_miss_wti_cmd_trdid_fifo; + GenericFifo m_miss_wti_cmd_pktid_fifo; + GenericFifo m_miss_wti_cmd_be_fifo; + GenericFifo m_miss_wti_cmd_cmd_fifo; + GenericFifo m_miss_wti_cmd_contig_fifo; + GenericFifo m_miss_wti_cmd_data_fifo; + GenericFifo m_miss_wti_cmd_eop_fifo; + GenericFifo m_miss_wti_cmd_cons_fifo; + GenericFifo m_miss_wti_cmd_plen_fifo; + GenericFifo m_miss_wti_cmd_wrap_fifo; + GenericFifo m_miss_wti_cmd_cfixed_fifo; + GenericFifo m_miss_wti_cmd_clen_fifo; + + //////////////////////////////// + // Activity counters + //////////////////////////////// + + uint32_t m_cpt_total_cycles; // total number of cycles + + // TLB activity counters + uint32_t m_cpt_iotlb_read; // number of iotlb read + uint32_t m_cpt_iotlb_miss; // number of iotlb miss + uint32_t m_cost_iotlb_miss; // number of wait cycles (not treatment itself) + uint32_t m_cpt_iotlbmiss_transaction; // number of tlb miss transactions + uint32_t m_cost_iotlbmiss_transaction; // cumulated duration tlb miss transactions + + //Transaction Tabs (TRTs) activity counters + uint32_t m_cpt_trt_dma_full; // DMA TRT full when a new command arrives + uint32_t m_cpt_trt_dma_full_cost; // total number of cycles blocked + uint32_t m_cpt_trt_config_full; // Config TRT full when a new command arrives + uint32_t m_cpt_trt_config_full_cost; // total number of cycles blocked + + // FSM activity counters + // unused on print_stats + uint32_t m_cpt_fsm_dma_cmd [32]; + uint32_t m_cpt_fsm_dma_rsp [32]; + uint32_t m_cpt_fsm_tlb [32]; + uint32_t m_cpt_fsm_config_cmd [32]; + uint32_t m_cpt_fsm_config_rsp [32]; + uint32_t m_cpt_fsm_miss_wti_rsp [32]; + +protected: + + SC_HAS_PROCESS(VciIoBridge); + +public: + + VciIoBridge( + sc_module_name insname, + const soclib::common::MappingTable &mt_ext, // external network + const soclib::common::MappingTable &mt_int, // internal network + const soclib::common::MappingTable &mt_iox, // iox network + const soclib::common::IntTab &int_tgtid, // INT network TGTID + const soclib::common::IntTab &int_srcid, // INT network SRCID + const soclib::common::IntTab &iox_tgtid, // IOX network TGTID + const soclib::common::IntTab &iox_srcid, // IOX network SRCID + const size_t dcache_words, + const size_t iotlb_ways, + const size_t iotlb_sets, + const uint32_t debug_start_cycle, + const bool debug_ok ); + + ~VciIoBridge(); + + void print_stats(); + void clear_stats(); + void print_trace(size_t mode = 0); + + +private: + + bool is_wti( vci_addr_t paddr ); + void transition(); + void genMoore(); +}; + +}} + +#endif /* SOCLIB_CABA_VCI_CC_VCACHE_WRAPPER_V4_H */ + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + + + + Index: /branches/fault_tolerance/modules/vci_io_bridge/caba/source/src/vci_io_bridge.cpp =================================================================== --- /branches/fault_tolerance/modules/vci_io_bridge/caba/source/src/vci_io_bridge.cpp (revision 724) +++ /branches/fault_tolerance/modules/vci_io_bridge/caba/source/src/vci_io_bridge.cpp (revision 724) @@ -0,0 +1,2667 @@ +/* -*- c++ -*- + * File : vci_io_bridge.cpp + * Copyright (c) UPMC, Lip6, SoC + * Authors: Cassio Fraga, Alain Greiner + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + */ + +#include +#include "arithmetics.h" +#include "alloc_elems.h" +#include "../include/vci_io_bridge.h" + + +////// debug services /////////////////////////////////////////////////////// +// All debug messages are conditionned by two variables: +// - compile time : DEBUG_*** : defined below +// - execution time : m_debug_*** : defined by constructor arguments +// m_debug_activated = (m_debug_ok) and (m_cpt_cycle > m_debug_start_cycle) +///////////////////////////////////////////////////////////////////////////////// + +#define DEBUG_DMA_CMD 1 +#define DEBUG_DMA_RSP 1 +#define DEBUG_TLB_MISS 1 +#define DEBUG_CONFIG_CMD 1 +#define DEBUG_CONFIG_RSP 1 +#define DEBUG_MISS_WTI_CMD 1 + +namespace soclib { +namespace caba { + +namespace { + +const char *dma_cmd_fsm_state_str[] = + { + "DMA_CMD_IDLE", + "DMA_CMD_DMA_REQ", + "DMA_CMD_WTI_IOX_REQ", + "DMA_CMD_ERR_WAIT_EOP", + "DMA_CMD_ERR_WTI_REQ", + "DMA_CMD_ERR_RSP_REQ", + "DMA_CMD_TLB_MISS_WAIT", + }; + +const char *dma_rsp_fsm_state_str[] = + { + "DMA_RSP_IDLE_DMA", + "DMA_RSP_IDLE_WTI", + "DMA_RSP_IDLE_ERR", + "DMA_RSP_PUT_DMA", + "DMA_RSP_PUT_WTI", + "DMA_RSP_PUT_ERR", + }; + +const char *tlb_fsm_state_str[] = + { + "TLB_IDLE", + "TLB_MISS", + "TLB_PTE1_GET", + "TLB_PTE1_SELECT", + "TLB_PTE1_UPDT", + "TLB_PTE2_GET", + "TLB_PTE2_SELECT", + "TLB_PTE2_UPDT", + "TLB_WAIT", + "TLB_RETURN", + "TLB_INVAL_CHECK", + }; + +const char *config_cmd_fsm_state_str[] = + { + "CONFIG_CMD_IDLE", + "CONFIG_CMD_WAIT", + "CONFIG_CMD_HI", + "CONFIG_CMD_LO", + "CONFIG_CMD_PUT", + "CONFIG_CMD_RSP", + }; + +const char *config_rsp_fsm_state_str[] = + { + "CONFIG_RSP_IDLE_IOX", + "CONFIG_RSP_IDLE_LOC", + "CONFIG_RSP_PUT_LO", + "CONFIG_RSP_PUT_HI", + "CONFIG_RSP_PUT_UNC", + "CONFIG_RSP_PUT_LOC", + }; + +const char *miss_wti_rsp_state_str[] = + { + "MISS_WTI_RSP_IDLE", + "MISS_WTI_RSP_WTI_IOX", + "MISS_WTI_RSP_WTI_MMU", + "MISS_WTI_RSP_MISS", + }; +} + +#define tmpl(...) template __VA_ARGS__ VciIoBridge + +//////////////////////// +tmpl(/**/)::VciIoBridge( + sc_module_name name, + const soclib::common::MappingTable &mt_ext, + const soclib::common::MappingTable &mt_int, + const soclib::common::MappingTable &mt_iox, + const soclib::common::IntTab &int_tgtid, // INT network TGTID + const soclib::common::IntTab &int_srcid, // INT network SRCID + const soclib::common::IntTab &iox_tgtid, // IOX network TGTID + const soclib::common::IntTab &iox_srcid, // IOX network SRCID + const size_t dcache_words, + const size_t iotlb_ways, + const size_t iotlb_sets, + const uint32_t debug_start_cycle, + const bool debug_ok) + : soclib::caba::BaseModule(name), + + p_clk("p_clk"), + p_resetn("p_resetn"), + p_vci_ini_ram("p_vci_ini_ram"), + p_vci_tgt_iox("p_vci_tgt_iox"), + p_vci_ini_iox("p_vci_ini_iox"), + p_vci_tgt_int("p_vci_tgt_int"), + p_vci_ini_int("p_vci_ini_int"), + + m_words( dcache_words ), + + // INT & IOX Network + m_int_seglist( mt_int.getSegmentList( int_tgtid )), + m_int_srcid( mt_int.indexForId( int_srcid )), + m_iox_seglist( mt_iox.getSegmentList( iox_tgtid )), + m_iox_srcid( mt_iox.indexForId( iox_srcid )), + + m_srcid_gid_mask( mt_int.getSrcidLevelBits()[0], // use global bits + mt_int.getSrcidLevelBits()[1]), // drop local bits + m_srcid_lid_mask( mt_int.getSrcidLevelBits()[1], // use local bits + 0), + + m_iotlb_ways(iotlb_ways), + m_iotlb_sets(iotlb_sets), + + m_debug_start_cycle(debug_start_cycle), + m_debug_ok(debug_ok), + + // addressable registers + r_iommu_ptpr("r_iommu_ptpr"), + r_iommu_active("r_iommu_active"), + r_iommu_bvar("r_iommu_bvar"), + r_iommu_etr("r_iommu_etr"), + r_iommu_bad_id("r_iommu_bad_id"), + r_iommu_wti_enable("r_iommu_wti_enable"), + r_iommu_wti_addr_lo("r_iommu_wti_addr_lo"), + + // DMA_CMD FSM registers + r_dma_cmd_fsm("r_dma_cmd_fsm"), + r_dma_cmd_paddr("r_dma_cmd_paddr"), + + r_dma_cmd_to_miss_wti_cmd_req("r_dma_cmd_to_miss_wti_cmd_req"), + r_dma_cmd_to_miss_wti_cmd_addr("r_dma_cmd_to_miss_wti_cmd_addr"), + r_dma_cmd_to_miss_wti_cmd_srcid("r_dma_cmd_to_miss_wti_cmd_srcid"), + r_dma_cmd_to_miss_wti_cmd_trdid("r_dma_cmd_to_miss_wti_cmd_trdid"), + r_dma_cmd_to_miss_wti_cmd_pktid("r_dma_cmd_to_miss_wti_cmd_pktid"), + r_dma_cmd_to_miss_wti_cmd_wdata("r_dma_cmd_to_miss_wti_cmd_wdata"), + + r_dma_cmd_to_dma_rsp_req("r_dma_cmd_to_dma_rsp_req"), + r_dma_cmd_to_dma_rsp_rsrcid("r_dma_cmd_to_dma_rsp_rsrcid"), + r_dma_cmd_to_dma_rsp_rtrdid("r_dma_cmd_to_dma_rsp_rtrdid"), + r_dma_cmd_to_dma_rsp_rpktid("r_dma_cmd_to_dma_rsp_rpktid"), + + r_dma_cmd_to_tlb_req("r_dma_cmd_to_tlb_req"), + r_dma_cmd_to_tlb_vaddr("r_dma_cmd_to_tlb_vaddr"), + + //DMA_RSP FSM registers + r_dma_rsp_fsm("r_dma_rsp_fsm"), + + // CONFIG_CMD FSM registers + r_config_cmd_fsm("r_config_cmd_fsm"), + + r_config_cmd_to_tlb_req("r_config_cmd_to_tlb_req"), + r_config_cmd_to_tlb_vaddr("r_config_cmd_to_tlb_vaddr"), + + r_config_cmd_to_config_rsp_req("r_config_cmd_to_config_rsp_req"), + r_config_cmd_to_config_rsp_rerror("r_config_cmd_to_config_rsp_rerror"), + r_config_cmd_to_config_rsp_rdata("r_config_cmd_to_config_rsp_rdata"), + r_config_cmd_to_config_rsp_rsrcid("r_config_cmd_to_config_rsp_rsrcid"), + r_config_cmd_to_config_rsp_rtrdid("r_config_cmd_to_config_rsp_rtrdid"), + r_config_cmd_to_config_rsp_rpktid("r_config_cmd_to_config_rsp_rpktid"), + + r_config_cmd_wdata("r_config_cmd_wdata"), + r_config_cmd_be("r_config_cmd_be"), + r_config_cmd_cmd("r_config_cmd_wdata"), + r_config_cmd_address("r_config_cmd_address"), + r_config_cmd_srcid("r_config_cmd_srcid"), + r_config_cmd_trdid("r_config_cmd_trdid"), + r_config_cmd_pktid("r_config_cmd_pktid"), + r_config_cmd_plen("r_config_cmd_plen"), + r_config_cmd_clen("r_config_cmd_clen"), + r_config_cmd_cons("r_config_cmd_cons"), + r_config_cmd_contig("r_config_cmd_contig"), + r_config_cmd_cfixed("r_config_cmd_cfixed"), + r_config_cmd_wrap("r_config_cmd_wrap"), + r_config_cmd_eop("r_config_cmd_eop"), + + // ID translation table used by CONFIG_CMD and CONFIG_RSP FSMs + m_iox_transaction_tab(1), + + // CONFIG_RSP FSM registers + r_config_rsp_fsm("r_config_rsp_fsm"), + r_config_rsp_rsrcid("r_config_rsp_rsrcid"), + r_config_rsp_rtrdid("r_config_rsp_rtrdid"), + + // TLB FSM registers + r_tlb_fsm("r_tlb_fsm"), + r_waiting_transaction("r_waiting_transaction"), + r_tlb_miss_type("r_tlb_miss_type"), + r_tlb_miss_error("r_tlb_miss_error"), + + r_tlb_paddr("r_tlb_paddr"), + r_tlb_pte_flags("r_tlb_pte_flags"), + r_tlb_pte_ppn("r_tlb_pte_ppn"), + r_tlb_way("r_tlb_way"), + r_tlb_set("r_tlb_set"), + + r_tlb_buf_valid("r_tlb_buf_valid"), + r_tlb_buf_tag("r_tlb_buf_tag"), + r_tlb_buf_vaddr("r_tlb_buf_vaddr"), + r_tlb_buf_big_page("r_tlb_buf_big_page"), + + r_tlb_to_miss_wti_cmd_req("r_tlb_to_miss_wti_cmd_req"), + + // MISS_WTI_RSP FSM registers + r_miss_wti_rsp_fsm("r_miss_wti_rsp_fsm"), + r_miss_wti_rsp_error_wti("r_miss_wti_rsp_error_wti"), + r_miss_wti_rsp_error_miss("r_miss_wti_rsp_error_miss"), + r_miss_wti_rsp_count("r_miss_wti_rsp_count"), + + r_miss_wti_rsp_to_dma_rsp_req("r_miss_wti_rsp_to_dma_rsp_req"), + r_miss_wti_rsp_to_dma_rsp_rerror("r_miss_wti_rsp_to_dma_rsp_rerror"), + r_miss_wti_rsp_to_dma_rsp_rsrcid("r_miss_wti_rsp_to_dma_rsp_rsrcid"), + r_miss_wti_rsp_to_dma_rsp_rtrdid("r_miss_wti_rsp_to_dma_rsp_rtrdid"), + r_miss_wti_rsp_to_dma_rsp_rpktid("r_miss_wti_rsp_to_dma_rsp_rpktid"), + + // TLB for IOMMU + r_iotlb("iotlb", 0, iotlb_ways, iotlb_sets, vci_param_int::N), + + // DMA_CMD FIFOs + m_dma_cmd_addr_fifo("m_dma_cmd_addr_fifo",2), + m_dma_cmd_srcid_fifo("m_dma_cmd_srcid_fifo",2), + m_dma_cmd_trdid_fifo("m_dma_cmd_trdid_fifo",2), + m_dma_cmd_pktid_fifo("m_dma_cmd_pktid_fifo",2), + m_dma_cmd_be_fifo("m_dma_cmd_be_fifo",2), + m_dma_cmd_cmd_fifo("m_dma_cmd_cmd_fifo",2), + m_dma_cmd_contig_fifo("m_dma_cmd_contig_fifo",2), + m_dma_cmd_data_fifo("m_dma_cmd_data_fifo",2), + m_dma_cmd_eop_fifo("m_dma_cmd_eop_fifo",2), + m_dma_cmd_cons_fifo("m_dma_cmd_cons_fifo",2), + m_dma_cmd_plen_fifo("m_dma_cmd_plen_fifo",2), + m_dma_cmd_wrap_fifo("m_dma_cmd_wrap_fifo",2), + m_dma_cmd_cfixed_fifo("m_dma_cmd_cfixed_fifo",2), + m_dma_cmd_clen_fifo("m_dma_cmd_clen_fifo",2), + + // DMA_RSP FIFOs + m_dma_rsp_data_fifo("m_dma_rsp_data_fifo",2), + m_dma_rsp_rsrcid_fifo("m_dma_rsp_rsrcid_fifo",2), + m_dma_rsp_rtrdid_fifo("m_dma_rsp_rtrdid_fifo",2), + m_dma_rsp_rpktid_fifo("m_dma_rsp_rpktid_fifo",2), + m_dma_rsp_reop_fifo("m_dma_rsp_reop_fifo",2), + m_dma_rsp_rerror_fifo("m_dma_rsp_rerror_fifo",2), + + // CONFIG_CMD FIFOs + m_config_cmd_addr_fifo("m_config_cmd_addr_fifo",2), + m_config_cmd_srcid_fifo("m_config_cmd_srcid_fifo",2), + m_config_cmd_trdid_fifo("m_config_cmd_trdid_fifo",2), + m_config_cmd_pktid_fifo("m_config_cmd_pktid_fifo",2), + m_config_cmd_be_fifo("m_config_cmd_be_fifo",2), + m_config_cmd_cmd_fifo("m_config_cmd_cmd_fifo",2), + m_config_cmd_contig_fifo("m_config_cmd_contig_fifo",2), + m_config_cmd_data_fifo("m_config_cmd_data_fifo",2), + m_config_cmd_eop_fifo("m_config_cmd_eop_fifo",2), + m_config_cmd_cons_fifo("m_config_cmd_cons_fifo",2), + m_config_cmd_plen_fifo("m_config_cmd_plen_fifo",2), + m_config_cmd_wrap_fifo("m_config_cmd_wrap_fifo",2), + m_config_cmd_cfixed_fifo("m_config_cmd_cfixed_fifo",2), + m_config_cmd_clen_fifo("m_config_cmd_clen_fifo",2), + + // CONFIG_RSP FIFOs + m_config_rsp_data_fifo("m_config_rsp_data_fifo",2), + m_config_rsp_rsrcid_fifo("m_config_rsp_rsrcid_fifo",2), + m_config_rsp_rtrdid_fifo("m_config_rsp_rtrdid_fifo",2), + m_config_rsp_rpktid_fifo("m_config_rsp_rpktid_fifo",2), + m_config_rsp_reop_fifo("m_config_rsp_reop_fifo",2), + m_config_rsp_rerror_fifo("m_config_rsp_rerror_fifo",2), + + // MISS_WTI_CMD FIFOs + m_miss_wti_cmd_addr_fifo("m_miss_wti_cmd_addr_fifo",2), + m_miss_wti_cmd_srcid_fifo("m_miss_wti_cmd_srcid_fifo",2), + m_miss_wti_cmd_trdid_fifo("m_miss_wti_cmd_trdid_fifo",2), + m_miss_wti_cmd_pktid_fifo("m_miss_wti_cmd_pktid_fifo",2), + m_miss_wti_cmd_be_fifo("m_miss_wti_cmd_be_fifo",2), + m_miss_wti_cmd_cmd_fifo("m_miss_wti_cmd_cmd_fifo",2), + m_miss_wti_cmd_contig_fifo("m_miss_wti_cmd_contig_fifo",2), + m_miss_wti_cmd_data_fifo("m_miss_wti_cmd_data_fifo",2), + m_miss_wti_cmd_eop_fifo("m_miss_wti_cmd_eop_fifo",2), + m_miss_wti_cmd_cons_fifo("m_miss_wti_cmd_cons_fifo",2), + m_miss_wti_cmd_plen_fifo("m_miss_wti_cmd_plen_fifo",2), + m_miss_wti_cmd_wrap_fifo("m_miss_wti_cmd_wrap_fifo",2), + m_miss_wti_cmd_cfixed_fifo("m_miss_wti_cmd_cfixed_fifo",2), + m_miss_wti_cmd_clen_fifo("m_miss_wti_cmd_clen_fifo",2) +{ + std::cout << " - Building VciIoBridge : " << name << std::endl; + + // checking segments on INT network + assert ( ( not m_int_seglist.empty() ) and + "VCI_IO_BRIDGE ERROR : no segment allocated on INT network"); + + std::list::iterator int_seg; + for ( int_seg = m_int_seglist.begin() ; int_seg != m_int_seglist.end() ; int_seg++ ) + { + std::cout << " => segment " << int_seg->name() + << " / base = " << std::hex << int_seg->baseAddress() + << " / size = " << int_seg->size() + << " / special = " << int_seg->special() << std::endl; + } + + // checking segments on IOX network + assert ( ( not m_iox_seglist.empty() ) and + "VCI_IO_BRIDGE ERROR : no segment allocated on IOX network"); + + std::list::iterator iox_seg; + for ( iox_seg = m_iox_seglist.begin() ; iox_seg != m_iox_seglist.end() ; iox_seg++ ) + { + std::cout << " => segment " << iox_seg->name() + << " / base = " << std::hex << iox_seg->baseAddress() + << " / size = " << iox_seg->size() << std::endl; + } + + assert( (vci_param_int::N == vci_param_ext::N) and + "VCI_IO_BRIDGE ERROR: VCI ADDRESS widths must be equal on the 3 networks"); + + assert( (vci_param_int::N <= 64) and + "VCI_IO_BRIDGE ERROR: VCI ADDRESS width cannot be bigger than 64 bits"); + + assert( (vci_param_int::B == 4) and + "VCI_IO_BRIDGE ERROR: VCI DATA width must be 32 bits on internal network"); + + assert( (vci_param_ext::B == 8) and + "VCI_IO_BRIDGE ERROR: VCI DATA width must be 64 bits on external network"); + + assert( (vci_param_int::S == vci_param_ext::S) and + "VCI_IO_BRIDGE ERROR: SRCID widths must be equal on the 3 networks"); + + // Cache line buffer + r_tlb_buf_data = new uint32_t[dcache_words]; + + SC_METHOD(transition); + dont_initialize(); + sensitive << p_clk.pos(); + + SC_METHOD(genMoore); + dont_initialize(); + sensitive << p_clk.neg(); + + } + +///////////////////////////////////// +tmpl(/**/)::~VciIoBridge() +///////////////////////////////////// +{ + delete [] r_tlb_buf_data; +} + +//////////////////////////////////// +tmpl(void)::print_trace(size_t mode) +//////////////////////////////////// +{ + // b0 : IOTLB trace + + std::cout << std::dec << "IO_BRIDGE " << name() << std::endl; + + std::cout << " " << dma_cmd_fsm_state_str[r_dma_cmd_fsm.read()] + << " | " << dma_rsp_fsm_state_str[r_dma_rsp_fsm.read()] + << " | " << tlb_fsm_state_str[r_tlb_fsm.read()] + << " | " << config_cmd_fsm_state_str[r_config_cmd_fsm.read()] + << " | " << config_rsp_fsm_state_str[r_config_rsp_fsm.read()] + << " | " << miss_wti_rsp_state_str[r_miss_wti_rsp_fsm.read()] + << std::endl; + + if(mode & 0x01) + { + std::cout << " IOTLB" << std::endl; + r_iotlb.printTrace(); + } + + if(mode & 0x02) + { + std::cout << " IOX TRANSACTION TAB" << std::endl; + m_iox_transaction_tab.printTrace(); + } +} + +//////////////////////// +tmpl(void)::print_stats() +//////////////////////// +{ + std::cout << name() + << "\n- IOTLB MISS RATE = " + << (float)m_cpt_iotlb_miss/m_cpt_iotlb_read + << "\n- IOTLB MISS COST = " + << (float)m_cost_iotlb_miss/m_cpt_iotlb_miss + << "\n- IOTLB MISS TRANSACTION COST = " + << (float)m_cost_iotlbmiss_transaction/m_cpt_iotlbmiss_transaction + << "\n- IOTLB MISS TRANSACTION RATE (OVER ALL MISSES) = " + << (float)m_cpt_iotlbmiss_transaction/m_cpt_iotlb_miss + << std::endl; +} + +//////////////////////// +tmpl(void)::clear_stats() +//////////////////////// +{ + m_cpt_iotlb_read = 0; + m_cpt_iotlb_miss = 0; + m_cost_iotlb_miss = 0; + m_cpt_iotlbmiss_transaction = 0; + m_cost_iotlbmiss_transaction = 0; +} + +//////////////////////////////////// +tmpl(bool)::is_wti(vci_addr_t paddr) +//////////////////////////////////// +{ + std::list::iterator seg; + for ( seg = m_iox_seglist.begin() ; + seg != m_iox_seglist.end() ; + seg++ ) + { + if ( seg->contains(paddr) ) return seg->special(); + } + return false; +} + +///////////////////////// +tmpl(void)::transition() +///////////////////////// +{ + if ( not p_resetn.read() ) + { + r_dma_cmd_fsm = DMA_CMD_IDLE; + r_dma_rsp_fsm = DMA_RSP_IDLE_DMA; + r_tlb_fsm = TLB_IDLE; + r_config_cmd_fsm = CONFIG_CMD_IDLE; + r_config_rsp_fsm = CONFIG_RSP_IDLE_IOX; + r_miss_wti_rsp_fsm = MISS_WTI_RSP_IDLE; + + r_tlb_buf_valid = false; + r_iommu_active = false; + r_iommu_wti_enable = false; + + // initializing translation table + m_iox_transaction_tab.init(); + + // initializing FIFOs + m_dma_cmd_addr_fifo.init(); + m_dma_cmd_srcid_fifo.init(); + m_dma_cmd_trdid_fifo.init(); + m_dma_cmd_pktid_fifo.init(); + m_dma_cmd_be_fifo.init(); + m_dma_cmd_cmd_fifo.init(); + m_dma_cmd_contig_fifo.init(); + m_dma_cmd_data_fifo.init(); + m_dma_cmd_eop_fifo.init(); + m_dma_cmd_cons_fifo.init(); + m_dma_cmd_plen_fifo.init(); + m_dma_cmd_wrap_fifo.init(); + m_dma_cmd_cfixed_fifo.init(); + m_dma_cmd_clen_fifo.init(); + + m_dma_rsp_rsrcid_fifo.init(); + m_dma_rsp_rtrdid_fifo.init(); + m_dma_rsp_rpktid_fifo.init(); + m_dma_rsp_data_fifo.init(); + m_dma_rsp_rerror_fifo.init(); + m_dma_rsp_reop_fifo.init(); + + m_config_cmd_addr_fifo.init(); + m_config_cmd_srcid_fifo.init(); + m_config_cmd_trdid_fifo.init(); + m_config_cmd_pktid_fifo.init(); + m_config_cmd_be_fifo.init(); + m_config_cmd_cmd_fifo.init(); + m_config_cmd_contig_fifo.init(); + m_config_cmd_data_fifo.init(); + m_config_cmd_eop_fifo.init(); + m_config_cmd_cons_fifo.init(); + m_config_cmd_plen_fifo.init(); + m_config_cmd_wrap_fifo.init(); + m_config_cmd_cfixed_fifo.init(); + m_config_cmd_clen_fifo.init(); + + m_miss_wti_cmd_addr_fifo.init(); + m_miss_wti_cmd_srcid_fifo.init(); + m_miss_wti_cmd_trdid_fifo.init(); + m_miss_wti_cmd_pktid_fifo.init(); + m_miss_wti_cmd_be_fifo.init(); + m_miss_wti_cmd_cmd_fifo.init(); + m_miss_wti_cmd_contig_fifo.init(); + m_miss_wti_cmd_data_fifo.init(); + m_miss_wti_cmd_eop_fifo.init(); + m_miss_wti_cmd_cons_fifo.init(); + m_miss_wti_cmd_plen_fifo.init(); + m_miss_wti_cmd_wrap_fifo.init(); + m_miss_wti_cmd_cfixed_fifo.init(); + m_miss_wti_cmd_clen_fifo.init(); + + m_config_rsp_rsrcid_fifo.init(); + m_config_rsp_rtrdid_fifo.init(); + m_config_rsp_rpktid_fifo.init(); + m_config_rsp_data_fifo.init(); + m_config_rsp_rerror_fifo.init(); + m_config_rsp_reop_fifo.init(); + + // SET/RESET Communication flip-flops + r_dma_cmd_to_miss_wti_cmd_req = false; + r_dma_cmd_to_dma_rsp_req = false; + r_dma_cmd_to_tlb_req = false; + r_config_cmd_to_tlb_req = false; + r_config_cmd_to_config_rsp_req = false; + r_tlb_to_miss_wti_cmd_req = false; + r_miss_wti_rsp_to_dma_rsp_req = false; + + // error flip_flops + r_miss_wti_rsp_error_miss = false; + r_miss_wti_rsp_error_wti = false; + + // Debug variable + m_debug_activated = false; + + // activity counters + m_cpt_total_cycles = 0; + m_cpt_iotlb_read = 0; + m_cpt_iotlb_miss = 0; + m_cpt_iotlbmiss_transaction = 0; + m_cost_iotlbmiss_transaction = 0; + + m_cpt_trt_dma_full = 0; + m_cpt_trt_dma_full_cost = 0; + m_cpt_trt_config_full = 0; + m_cpt_trt_config_full_cost = 0; + + for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dma_cmd [i] = 0; + for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dma_rsp [i] = 0; + for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_tlb [i] = 0; + for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_config_cmd [i] = 0; + for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_config_rsp [i] = 0; + for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_miss_wti_rsp [i] = 0; + + return; + } + + // default values for the 5 FIFOs + bool dma_cmd_fifo_put = false; + bool dma_cmd_fifo_get = p_vci_ini_ram.cmdack.read(); + vci_srcid_t dma_cmd_fifo_srcid = 0; + + bool dma_rsp_fifo_put = false; + bool dma_rsp_fifo_get = p_vci_tgt_iox.rspack.read(); + vci_rerror_t dma_rsp_fifo_rerror = 0; + vci_srcid_t dma_rsp_fifo_rsrcid = 0; + vci_trdid_t dma_rsp_fifo_rtrdid = 0; + vci_pktid_t dma_rsp_fifo_rpktid = 0; + ext_data_t dma_rsp_fifo_rdata = 0; + bool dma_rsp_fifo_reop = false; + + bool config_cmd_fifo_put = false; + bool config_cmd_fifo_get = p_vci_ini_iox.cmdack.read(); + + bool config_rsp_fifo_put = false; + bool config_rsp_fifo_get = p_vci_tgt_int.rspack.read(); + vci_rerror_t config_rsp_fifo_rerror = 0; + vci_srcid_t config_rsp_fifo_rsrcid = 0; + vci_trdid_t config_rsp_fifo_rtrdid = 0; + vci_pktid_t config_rsp_fifo_rpktid = 0; + ext_data_t config_rsp_fifo_rdata = 0; + bool config_rsp_fifo_reop = false; + + bool miss_wti_cmd_fifo_put = false; + bool miss_wti_cmd_fifo_get = p_vci_ini_int.cmdack.read(); + vci_addr_t miss_wti_cmd_fifo_address = 0; + vci_cmd_t miss_wti_cmd_fifo_cmd = 0; + vci_srcid_t miss_wti_cmd_fifo_srcid = 0; + vci_trdid_t miss_wti_cmd_fifo_trdid = 0; + vci_pktid_t miss_wti_cmd_fifo_pktid = 0; + int_data_t miss_wti_cmd_fifo_wdata = 0; + +#ifdef INSTRUMENTATION + m_cpt_fsm_dma_cmd [r_dma_cmd_fsm.read()] ++; + m_cpt_fsm_dma_rsp [r_dma_rsp_fsm.read() ] ++; + m_cpt_fsm_tlb [r_tlb_fsm.read() ] ++; + m_cpt_fsm_config_cmd [r_config_cmd_fsm.read() ] ++; + m_cpt_fsm_config_rsp [r_config_rsp_fsm.read() ] ++; + m_cpt_fsm_miss_wti_rsp [r_miss_wti_rsp_fsm.read() ] ++; +#endif + + m_cpt_total_cycles++; + + m_debug_activated = (m_cpt_total_cycles > m_debug_start_cycle) and m_debug_ok; + + ////////////////////////////////////////////////////////////////////////////// + // The DMA_CMD_FSM handles transactions requested by peripherals. + // - it can be DMA transactions to RAM network (DMA_REQ state). + // - it can be WTI transactions to INT network (EXT_WTI_REQ state). + // It makes the address translation if IOMMU is activated, requesting + // the TLB_MISS FSM in case of TLB miss (TLB_MISS_WAIT state). + // When the IOMMU is activated, a DMA request can fail in two cases: + // - write to a read-only address : detected in IDLE state + // - virtual address unmapped : detected in MISS_WAIT state + // In both cases of violation, the DMA_CMD FSM makes the following actions : + // 1. register the error in r_iommu_*** registers + // 2. wait the faulty command EOP (ERR_WAIT_EOP state) + // 3. request a IOMMU WTI to MISS_WTI FSM, (ERR_WTI_REQ state) + // 4. request a response error to DMA_RSP FSM (ERR_RSP_REQ state) + /////////////////////////////////////////////////////////////////////////////// + + switch( r_dma_cmd_fsm.read() ) + { + ////////////////// + case DMA_CMD_IDLE: // wait a DMA or WTI VCI transaction and route it + // after an IOMMU translation if IOMMU activated. + // no VCI flit is consumed in this state + { + if ( p_vci_tgt_iox.cmdval.read() ) + { + if ( not r_iommu_active.read() ) // tlb not activated + { + // save paddr address + r_dma_cmd_paddr = p_vci_tgt_iox.address.read(); + + // analyse paddr for WTI/DMA routing + // WTI requests must be single flit (READ or WRITE) + if ( is_wti( p_vci_tgt_iox.address.read() ) ) + { + assert( p_vci_tgt_iox.eop.read() and + "ERROR in VCI_IOB illegal VCI WTI command from IOX network"); + + r_dma_cmd_fsm = DMA_CMD_WTI_IOX_REQ; + } + else + { + r_dma_cmd_fsm = DMA_CMD_DMA_REQ; + } + +#if DEBUG_DMA_CMD +if( m_debug_activated ) +std::cout << name() + << " DMA command" + << " : address = " << std::hex << p_vci_tgt_iox.address.read() + << " / srcid = " << p_vci_tgt_iox.srcid.read() + << " / wdata = " << std::hex << p_vci_tgt_iox.wdata.read() + << " / plen = " << std::dec << p_vci_tgt_iox.plen.read() + << " / eop = " << p_vci_tgt_iox.eop.read() << std::endl; +#endif + } + else if (r_tlb_fsm.read() == TLB_IDLE || + r_tlb_fsm.read() == TLB_WAIT ) // tlb access possible + { + vci_addr_t iotlb_paddr; + pte_info_t iotlb_flags; + size_t iotlb_way; + size_t iotlb_set; + vci_addr_t iotlb_nline; + bool iotlb_hit; + +#ifdef INSTRUMENTATION +m_cpt_iotlb_read++; +#endif + iotlb_hit = r_iotlb.translate(p_vci_tgt_iox.address.read(), + &iotlb_paddr, + &iotlb_flags, + &iotlb_nline, // unused + &iotlb_way, // unused + &iotlb_set ); // unused + + if ( iotlb_hit ) // tlb hit + { + if ( not iotlb_flags.w and // access right violation + (p_vci_tgt_iox.cmd.read() == vci_param_ext::CMD_WRITE) ) + { + // register error + r_iommu_etr = MMU_WRITE_ACCES_VIOLATION; + r_iommu_bvar = p_vci_tgt_iox.address.read(); + r_iommu_bad_id = p_vci_tgt_iox.srcid.read(); + + // prepare response error request to DMA_RSP FSM + r_dma_cmd_to_dma_rsp_rsrcid = p_vci_tgt_iox.srcid.read(); + r_dma_cmd_to_dma_rsp_rtrdid = p_vci_tgt_iox.trdid.read(); + r_dma_cmd_to_dma_rsp_rpktid = p_vci_tgt_iox.pktid.read(); + + // jumps IOMMU error sequence + r_dma_cmd_fsm = DMA_CMD_ERR_WAIT_EOP; +#if DEBUG_DMA_CMD +if( m_debug_activated ) +std::cout << name() + << " TLB HIT but writable violation" << std::endl; +#endif + } + else // no access rights violation + { +#if DEBUG_DMA_CMD +if( m_debug_activated ) +std::cout << name() + << " TLB HIT" << std::endl; +#endif + // save paddr address + r_dma_cmd_paddr = iotlb_paddr; + + // analyse address for WTI/DMA routing + if ( is_wti( iotlb_paddr ) ) + { + assert( p_vci_tgt_iox.eop.read() and + (p_vci_tgt_iox.cmd == vci_param_int::CMD_WRITE) and + "ERROR in VCI_IOB illegal VCI WTI command from IOX network"); + + r_dma_cmd_fsm = DMA_CMD_WTI_IOX_REQ; + } + else + { + r_dma_cmd_fsm = DMA_CMD_DMA_REQ; + } + } + } + else // TLB miss + { + +#ifdef INSTRUMENTATION +m_cpt_iotlb_miss++; +#endif + // register virtual address, and send request to TLB FSM + r_dma_cmd_to_tlb_vaddr = p_vci_tgt_iox.address.read(); + r_dma_cmd_to_tlb_req = true; + r_dma_cmd_fsm = DMA_CMD_TLB_MISS_WAIT; +#if DEBUG_DMA_CMD +if( m_debug_activated ) +std::cout << name() + << " TLB MISS" << std::endl; +#endif + } // end tlb miss + } // end if tlb_activated + } // end if cmdval + break; + } + ///////////////////// + case DMA_CMD_DMA_REQ: // put a flit in DMA_CMD FIFO + // if contig, VCI address must be incremented + // after initial translation by IOMMU. + // flit is consumed if DMA_CMD FIFO not full + { + if ( p_vci_tgt_iox.cmdval && m_dma_cmd_addr_fifo.wok() ) + { + // SRCID in RAM network is the concatenation of the IO bridge + // cluster id with the DMA peripheral local id + assert((m_srcid_gid_mask[p_vci_tgt_iox.srcid.read()] == 0) && + "error: external DMA peripherals global id must be 0"); + + dma_cmd_fifo_srcid = (m_srcid_gid_mask.mask() & m_int_srcid) | + p_vci_tgt_iox.srcid.read(); + dma_cmd_fifo_put = true; + + if ( p_vci_tgt_iox.contig.read() ) + { + r_dma_cmd_paddr = r_dma_cmd_paddr.read() + vci_param_ext::B; + } + + if ( p_vci_tgt_iox.eop.read() ) + { + r_dma_cmd_fsm = DMA_CMD_IDLE; + } + +#if DEBUG_DMA_CMD +if( m_debug_activated ) +std::cout << name() + << " Push into DMA_CMD fifo:" + << " address = " << std::hex << r_dma_cmd_paddr.read() + << " srcid = " << dma_cmd_fifo_srcid + << " wdata = " << p_vci_tgt_iox.wdata.read() + << " plen = " << std::dec << p_vci_tgt_iox.plen.read() + << " eop = " << std::dec << p_vci_tgt_iox.eop.read() << std::endl; +#endif + } + break; + } + ///////////////////////// + case DMA_CMD_WTI_IOX_REQ: // post a WTI_IOX request to MISS_WTI FSM + // if no prending previous request + // command arguments are stored in dedicated registers + // VCI flit is consumed if no previous request + { + if ( not r_dma_cmd_to_miss_wti_cmd_req.read() ) // no previous pending request + { + // SRCID in INT network for WTI transactions is the concatenation + // of the IO bridge cluster id with the DMA peripheral local id + assert((m_srcid_gid_mask[p_vci_tgt_iox.srcid.read()] == 0) && + "error: external DMA peripherals global id must be 0"); + + vci_srcid_t wti_srcid = (m_srcid_gid_mask.mask() & m_int_srcid) | + p_vci_tgt_iox.srcid.read(); + + r_dma_cmd_to_miss_wti_cmd_req = true; + r_dma_cmd_to_miss_wti_cmd_addr = p_vci_tgt_iox.address.read(); + r_dma_cmd_to_miss_wti_cmd_cmd = p_vci_tgt_iox.cmd.read(); + r_dma_cmd_to_miss_wti_cmd_wdata = (uint32_t)p_vci_tgt_iox.wdata.read(); + r_dma_cmd_to_miss_wti_cmd_srcid = wti_srcid; + r_dma_cmd_to_miss_wti_cmd_trdid = p_vci_tgt_iox.trdid.read(); + r_dma_cmd_to_miss_wti_cmd_pktid = PKTID_WTI_IOX; + + r_dma_cmd_fsm = DMA_CMD_IDLE; + +#if DEBUG_DMA_CMD +if( m_debug_activated ) +std::cout << name() + << " request WTI transaction from ext peripheral" + << " : address = " << std::hex << r_dma_cmd_paddr.read() + << " / srcid = " << wti_srcid + << " / wdata = " << p_vci_tgt_iox.wdata.read() << std::endl; +#endif + } + break; + } + ////////////////////////// + case DMA_CMD_ERR_WAIT_EOP: // wait EOP before requesting WTI & error response + // VCI flit is always consumed + { + if ( p_vci_tgt_iox.eop.read() ) r_dma_cmd_fsm = DMA_CMD_ERR_WTI_REQ; + +#if DEBUG_DMA_CMD +if( m_debug_activated ) +std::cout << name() + << " wait EOP for faulty DMA command" << std::endl; +#endif + break; + } + + ///////////////////////// + case DMA_CMD_ERR_WTI_REQ: // post a WTI_MMU request to MISS_WTI_CMD FSM + // if no prending previous request + // response arguments are stored in dedicated registers + // no VCI flit is consumed + { + if ( not r_dma_cmd_to_miss_wti_cmd_req.read() ) // no pending previous request + { + r_dma_cmd_to_miss_wti_cmd_req = true; + r_dma_cmd_to_miss_wti_cmd_addr = (vci_addr_t)r_iommu_wti_addr_lo.read() | + (((vci_addr_t)r_iommu_wti_addr_hi.read())<<32); + r_dma_cmd_to_miss_wti_cmd_wdata = 0; + r_dma_cmd_to_miss_wti_cmd_srcid = m_int_srcid; + r_dma_cmd_to_miss_wti_cmd_trdid = 0; + r_dma_cmd_to_miss_wti_cmd_pktid = PKTID_WTI_MMU; + + r_dma_cmd_fsm = DMA_CMD_ERR_RSP_REQ; + +#if DEBUG_DMA_CMD +if( m_debug_activated ) +std::cout << name() + << " request an IOMMU WTI" << std::endl; +#endif + } + break; + } + ///////////////////////// + case DMA_CMD_ERR_RSP_REQ: // post an error response request to DMA_RSP FSM + // if no prending previous request + // response arguments are stored in dedicated registers + // no VCI flit is consumed + { + if ( not r_dma_cmd_to_dma_rsp_req.read() ) // no pending previous request + { + r_dma_cmd_to_dma_rsp_req = true; + r_dma_cmd_to_dma_rsp_rerror = 0x1; + r_dma_cmd_to_dma_rsp_rdata = 0; + } + break; + } + /////////////////////////// + case DMA_CMD_TLB_MISS_WAIT: // waiting completion of a TLB miss + // we must test a possible page fault error... + { + if ( not r_dma_cmd_to_tlb_req.read() ) // TLB miss completed + { + if ( r_tlb_miss_error.read() ) // Error reported by TLB FSM + { + r_iommu_etr = MMU_READ_PT2_UNMAPPED; + r_iommu_bvar = r_dma_cmd_to_tlb_vaddr.read(); + r_iommu_bad_id = p_vci_tgt_iox.srcid.read(); + r_dma_cmd_fsm = DMA_CMD_ERR_WAIT_EOP; + } + else // No error + { + r_dma_cmd_fsm = DMA_CMD_IDLE; + } + } + break; + } + } // end switch DMA_CMD FSM + + //////////////////////////////////////////////////////////////////////////////// + // The DMA_RSP_FSM controls access to the DMA_RSP FIFO to the IOX network. + // There exist 3 "clients" to send VCI responses on the IOX network: + // - request from p_vci_ini_ram : normal DMA response from RAM network, + // - request from MISS_WTI_RSP FSM : normal WTI response from INT network, + // - request from DMA_CMD FSM : bad address error response + // This FSM implements a round robin priority, with a "dead cycle" between + // two transactions. It could be optimized if throughput is critical... + //////////////////////////////////////////////////////////////////////////////// + + // does nothing if FIFO is full + if ( m_dma_rsp_rerror_fifo.wok() ) + { + switch( r_dma_rsp_fsm.read() ) + { + ////////////////////// + case DMA_RSP_IDLE_DMA: // normal DMA response has highest priority + { + if (p_vci_ini_ram.rspval.read()) r_dma_rsp_fsm = DMA_RSP_PUT_DMA; + else if(r_miss_wti_rsp_to_dma_rsp_req.read()) r_dma_rsp_fsm = DMA_RSP_PUT_WTI; + else if(r_dma_cmd_to_dma_rsp_req.read()) r_dma_rsp_fsm = DMA_RSP_PUT_ERR; + break; + } + ////////////////////// + case DMA_RSP_IDLE_WTI: // normal WTI response has highest priority + { + if (r_miss_wti_rsp_to_dma_rsp_req.read()) r_dma_rsp_fsm = DMA_RSP_PUT_WTI; + else if(r_dma_cmd_to_dma_rsp_req.read()) r_dma_rsp_fsm = DMA_RSP_PUT_ERR; + else if(p_vci_ini_ram.rspval.read()) r_dma_rsp_fsm = DMA_RSP_PUT_DMA; + break; + } + ////////////////////// + case DMA_RSP_IDLE_ERR: // error response has highest priority + { + if (r_dma_cmd_to_dma_rsp_req.read()) r_dma_rsp_fsm = DMA_RSP_PUT_ERR; + else if(p_vci_ini_ram.rspval.read()) r_dma_rsp_fsm = DMA_RSP_PUT_DMA; + else if(r_miss_wti_rsp_to_dma_rsp_req.read()) r_dma_rsp_fsm = DMA_RSP_PUT_WTI; + break; + } + /////////////////////// + case DMA_RSP_PUT_DMA: // put one flit of the DMA response into FIFO + { + dma_rsp_fifo_put = true; + dma_rsp_fifo_rerror = p_vci_ini_ram.rerror.read(); + dma_rsp_fifo_rdata = p_vci_ini_ram.rdata.read(); + dma_rsp_fifo_rsrcid = m_srcid_lid_mask[p_vci_ini_ram.rsrcid.read()]; + dma_rsp_fifo_rtrdid = p_vci_ini_ram.rtrdid.read(); + dma_rsp_fifo_rpktid = p_vci_ini_ram.rpktid.read(); + dma_rsp_fifo_reop = p_vci_ini_ram.reop.read(); + + // update priority + if ( p_vci_ini_ram.reop.read() ) r_dma_rsp_fsm = DMA_RSP_IDLE_WTI; + +#if DEBUG_DMA_RSP +if( m_debug_activated ) +std::cout << name() + << " Push DMA response into DMA_RSP FIFO" + << std::hex + << " : rsrcid = " << m_srcid_lid_mask[p_vci_ini_ram.rsrcid.read()] + << " / rtrdid = " << p_vci_ini_ram.rtrdid.read() + << " / rpktid = " << p_vci_ini_ram.rpktid.read() + << " / rdata = " << p_vci_ini_ram.rdata.read() + << " / rerror = " << p_vci_ini_ram.rerror.read() + << " / reop = " << p_vci_ini_ram.reop.read() << std::endl; +#endif + break; + } + /////////////////////// + case DMA_RSP_PUT_WTI: // put single flit WTI response into FIFO + { + dma_rsp_fifo_put = true; + dma_rsp_fifo_rerror = r_miss_wti_rsp_to_dma_rsp_rerror.read(); + dma_rsp_fifo_rdata = 0; + dma_rsp_fifo_rsrcid = + m_srcid_lid_mask[r_miss_wti_rsp_to_dma_rsp_rsrcid.read()]; + dma_rsp_fifo_rtrdid = r_miss_wti_rsp_to_dma_rsp_rtrdid.read(); + dma_rsp_fifo_rpktid = r_miss_wti_rsp_to_dma_rsp_rpktid.read(); + dma_rsp_fifo_reop = true; + + // acknowledge request + r_miss_wti_rsp_to_dma_rsp_req = false; + + // update priority + r_dma_rsp_fsm = DMA_RSP_IDLE_ERR; + +#if DEBUG_DMA_RSP +if( m_debug_activated ) +std::cout << name() + << " Push WTI response into DMA_RSP FIFO" + << std::hex + << " : rsrcid = " << m_srcid_lid_mask[r_miss_wti_rsp_to_dma_rsp_rsrcid.read()] + << " / rtrdid = " << r_miss_wti_rsp_to_dma_rsp_rtrdid.read() + << " / rpktid = " << r_miss_wti_rsp_to_dma_rsp_rpktid.read() + << " / rdata = " << 0 + << " / rerror = " << r_miss_wti_rsp_to_dma_rsp_rerror.read() + << " / reop = " << true << std::endl; +#endif + break; + } + /////////////////////// + case DMA_RSP_PUT_ERR: // put sinfle flit error response into FIFO + { + dma_rsp_fifo_put = true; + dma_rsp_fifo_rerror = 0x1; + dma_rsp_fifo_rdata = 0; + dma_rsp_fifo_rsrcid = r_dma_cmd_to_dma_rsp_rsrcid.read(); + dma_rsp_fifo_rtrdid = r_dma_cmd_to_dma_rsp_rtrdid.read(); + dma_rsp_fifo_rpktid = r_dma_cmd_to_dma_rsp_rpktid.read(); + dma_rsp_fifo_reop = true; + + // acknowledge request + r_dma_cmd_to_dma_rsp_req = false; + + // update priority + r_dma_rsp_fsm = DMA_RSP_PUT_DMA; + +#if DEBUG_DMA_RSP +if( m_debug_activated ) +std::cout << name() + << " Push IOMMU ERROR response into DMA_RSP FIFO" + << " : rsrcid = " << std::hex << r_dma_cmd_to_dma_rsp_rsrcid.read() + << " / rtrdid = " << r_dma_cmd_to_dma_rsp_rtrdid.read() + << " / rpktid = " << r_dma_cmd_to_dma_rsp_rpktid.read() + << " / rdata = " << 0 + << " / rerror = " << r_dma_cmd_to_dma_rsp_rerror.read() + << " / reop = " << true << std::endl; +#endif + break; + } + } // end switch DMA_RSP FSM + } // end if FIFO full + + + ////////////////////////////////////////////////////////////////////////////////// + // The TLB FSM handles the TLB miss requests from DMA_CMD FSM, + // and the PTE inval request (from CONFIG_CMD FSM). + // PTE inval request have highest priority. In case of TLB miss, + // this fsm searchs the requested PTE on the prefetch buffer. + // In case of buffer miss, it request the MISS_WTI FSM to access the memory. + // It bypass the first level page table access if possible. + // It reset the r_dma_cmd_to_tlb_req flip-flop to signal TLB miss completion. + // An unexpected, but possible page fault is signaled in r_tlb_miss_error flip_flop. + //////////////////////////////////////////////////////////////////////////////////// + + switch (r_tlb_fsm.read()) + { + ////////////// + case TLB_IDLE: // In case of TLB miss request, chek the prefetch buffer first + // PTE inval request are handled as unmaskable interrupts + { + if ( r_config_cmd_to_tlb_req.read() ) // Request for a PTE invalidation + { + r_config_cmd_to_tlb_req = false; + r_waiting_transaction = false; + r_tlb_fsm = TLB_INVAL_CHECK; + } + + else if ( r_dma_cmd_to_tlb_req.read() ) // request for a TLB Miss + { + // Checking prefetch buffer + if( not r_tlb_buf_big_page ) // small page => PTE2 + { + if( r_tlb_buf_valid && // Hit on prefetch buffer + (r_tlb_buf_vaddr.read() == + (r_dma_cmd_to_tlb_vaddr.read()& ~PTE2_LINE_OFFSET & ~K_PAGE_OFFSET_MASK))) + { + size_t pte_offset = (r_dma_cmd_to_tlb_vaddr.read()& PTE2_LINE_OFFSET)>>12; + uint32_t pte_flags = r_tlb_buf_data[2*pte_offset]; + uint32_t pte_ppn = r_tlb_buf_data[2*pte_offset+1]; + + // Bit valid checking + if ( not ( pte_flags & PTE_V_MASK) ) // unmapped + { + std::cout << "VCI_IO_BRIDGE ERROR : " << name() + << " Page Table entry unmapped" << std::endl; + + r_tlb_miss_error = true; + r_dma_cmd_to_tlb_req = false; +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +std::cout << name() + << " PTE2 Unmapped" << std::hex + << " / paddr = " << r_tlb_paddr.read() + << " / PTE_FLAGS = " << pte_flags + << " / PTE_PPN = " << pte_ppn << std::endl; +#endif + break; + } + + // valid PTE2 : we must update the TLB + r_tlb_pte_flags = pte_flags; + r_tlb_pte_ppn = pte_ppn; + r_tlb_fsm = TLB_PTE2_SELECT; +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +std::cout << name() + << " Hit on prefetch buffer: PTE2" << std::hex + << " / PTE_FLAGS = " << pte_flags + << " / PTE_PPN = " << pte_ppn << std::endl; +#endif + break; + } + } + else // big page => PTE1 + { + if( r_tlb_buf_valid && // Hit on prefetch buffer + (r_tlb_buf_vaddr.read() == + (r_dma_cmd_to_tlb_vaddr.read()& ~PTE1_LINE_OFFSET & ~M_PAGE_OFFSET_MASK ))) + { + size_t pte_offset = (r_dma_cmd_to_tlb_vaddr.read()& PTE1_LINE_OFFSET)>>21; + uint32_t pte_flags = r_tlb_buf_data[pte_offset]; + + // Bit valid checking + if ( not ( pte_flags & PTE_V_MASK) ) // unmapped + { + std::cout << "VCI_IO_BRIDGE ERROR : " << name() + << " Page Table entry unmapped" << std::endl; + + r_tlb_miss_error = true; + r_dma_cmd_to_tlb_req = false; +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +std::cout << name() + << " PTE1 Unmapped" << std::hex + << " / paddr = " << r_tlb_paddr.read() + << " / PTE = " << pte_flags << std::endl; +#endif + break; + } + + // valid PTE1 : we must update the TLB + r_tlb_pte_flags = pte_flags; + r_tlb_fsm = TLB_PTE1_SELECT; +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +std::cout << name() + << " Hit on prefetch buffer: PTE1" << std::hex + << " / paddr = " << r_tlb_paddr.read() + << std::hex << " / PTE1 = " << pte_flags << std::endl; +#endif + break; + } + } + + // prefetch buffer miss + r_tlb_fsm = TLB_MISS; + +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +std::cout << name() + << " Miss on prefetch buffer" + << std::hex << " / vaddr = " << r_dma_cmd_to_tlb_vaddr.read() << std::endl; +#endif + } + break; + } + ////////////// + case TLB_MISS: // handling tlb miss + { + uint32_t ptba = 0; + bool bypass; + vci_addr_t pte_paddr; + +#ifdef INSTRUMENTATION +m_cpt_iotlbmiss_transaction++; +#endif + // evaluate bypass in order to skip first level page table access + bypass = r_iotlb.get_bypass(r_dma_cmd_to_tlb_vaddr.read(), &ptba); + + // Request MISS_WTI_FSM a transaction on INT Network + if ( not bypass ) // Read PTE1/PTD1 in XRAM + { + +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +std::cout << name() + << " Read PTE1/PTD1 in memory" << std::endl; +#endif + pte_paddr = (vci_addr_t)((r_iommu_ptpr.read()) << (INDEX1_NBITS+2)) | + (vci_addr_t)((r_dma_cmd_to_tlb_vaddr.read() >> PAGE_M_NBITS) << 2); + r_tlb_paddr = pte_paddr; + + r_tlb_to_miss_wti_cmd_req = true; + r_tlb_miss_type = PTE1_MISS; + r_tlb_fsm = TLB_WAIT; + } + else // Read PTE2 in XRAM + { + +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +std::cout << name() + << " Read PTE2 in memory" << std::endl; +#endif + //&PTE2 = PTBA + IX2 * 8 + pte_paddr = (vci_addr_t)ptba << PAGE_K_NBITS | + (vci_addr_t)(r_dma_cmd_to_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3); + + r_tlb_paddr = pte_paddr; + + r_tlb_to_miss_wti_cmd_req = true; + r_tlb_miss_type = PTE2_MISS; + r_tlb_fsm = TLB_WAIT; + } + + break; + } + ////////////////// + case TLB_PTE1_GET: // Try to read a PT1 entry in the miss buffer + { + + uint32_t entry; + + vci_addr_t line_number = (vci_addr_t)((r_tlb_paddr.read())&(CACHE_LINE_MASK)); + size_t word_position = (size_t)( ((r_tlb_paddr.read())&(~CACHE_LINE_MASK))>>2 ); + + // Hit test. Just to verify. + // Hit must happen, since we've just finished its' miss transaction + bool hit = (r_tlb_buf_valid && (r_tlb_buf_tag.read()== line_number) ); + assert(hit and "Error: No hit on prefetch buffer after Miss Transaction"); + + entry = r_tlb_buf_data[word_position]; + + // Bit valid checking + if ( not ( entry & PTE_V_MASK) ) // unmapped + { + //must not occur! + std::cout << "IOMMU ERROR " << name() << "TLB_IDLE state" << std::endl + << "The Page Table entry ins't valid (unmapped)" << std::endl; + + r_tlb_miss_error = true; + r_dma_cmd_to_tlb_req = false; + r_tlb_fsm = TLB_IDLE; + +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +{ + std::cout << name() + << " First level entry Unmapped" + << std::hex << " / paddr = " << r_tlb_paddr.read() + << std::hex << " / PTE = " << entry << std::endl; +} +#endif + break; + } + + if( entry & PTE_T_MASK ) // PTD : me must access PT2 + { + // register bypass + r_iotlb.set_bypass( r_dma_cmd_to_tlb_vaddr.read(), + entry & ((1 << (vci_param_int::N-PAGE_K_NBITS)) - 1), + 0); //nline, unused + + // &PTE2 = PTBA + IX2 * 8 + // ps: PAGE_K_NBITS corresponds also to the size of a second level page table + r_tlb_paddr = (vci_addr_t)(entry & ((1<<(vci_param_int::N-PAGE_K_NBITS))-1)) << PAGE_K_NBITS | + (vci_addr_t)(((r_dma_cmd_to_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); + + r_tlb_to_miss_wti_cmd_req = true; + r_tlb_miss_type = PTE2_MISS; + r_tlb_fsm = TLB_WAIT; + +#ifdef INSTRUMENTATION +m_cpt_iotlbmiss_transaction++; +#endif + +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +std::cout << name() + << " Success. Search PTE2" << std::hex + << " / PADDR = " << r_tlb_paddr.read() + << " / PTD = " << entry << std::endl; +#endif + } + else // PTE1 : we must update the IOTLB + // Should not occur if working only with small pages + { + r_tlb_pte_flags = entry; + r_tlb_fsm = TLB_PTE1_SELECT; + +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +std::cout << name() + << " Success. Big page" + << std::hex << " / paddr = " << r_tlb_paddr.read() + << std::hex << " / PTE1 = " << entry << std::endl; +#endif + } + break; + } + ///////////////////// + case TLB_PTE1_SELECT: // select a slot for PTE1 + { + size_t way; + size_t set; + + r_iotlb.select( r_dma_cmd_to_tlb_vaddr.read(), + true, // PTE1 + &way, + &set ); +#ifdef INSTRUMENTATION +m_cpt_iotlb_read++; +#endif + +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +std::cout << name() + << " Select a slot in TLB" + << " / way = " << std::dec << way + << " / set = " << set << std::endl; +#endif + r_tlb_way = way; + r_tlb_set = set; + r_tlb_fsm = TLB_PTE1_UPDT; + break; + } + /////////////////// + case TLB_PTE1_UPDT: // write a new PTE1 in tlb + // not necessary to treat the L/R bit + { + uint32_t pte = r_tlb_pte_flags.read(); + + r_tlb_paddr = (vci_addr_t)( ((r_tlb_pte_flags.read() & PPN1_MASK) << 21) + | (r_dma_cmd_to_tlb_vaddr.read()& M_PAGE_OFFSET_MASK) ); + + // update TLB + r_iotlb.write( true, // 2M page + pte, + 0, // argument unused for a PTE1 + r_dma_cmd_to_tlb_vaddr.read(), + r_tlb_way.read(), + r_tlb_set.read(), + 0 ); //we set nline = 0 + +#ifdef INSTRUMENTATION +m_cpt_iotlb_write++; +#endif + +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +{ +std::cout << name() + << " write PTE1 in TLB" + << " / set = " << std::dec << r_tlb_set.read() + << " / way = " << r_tlb_way.read() << std::endl; +r_iotlb.printTrace(); +} +#endif + // next state + r_tlb_fsm = TLB_RETURN; // exit sub-fsm + break; + } + ////////////////// + case TLB_PTE2_GET: // Try to read a PTE2 (64 bits) in the miss buffer + { + uint32_t pte_flags; + uint32_t pte_ppn; + + vci_addr_t line_number = (vci_addr_t)((r_tlb_paddr.read())&(CACHE_LINE_MASK)); + size_t word_position = (size_t)( ((r_tlb_paddr.read())&(~CACHE_LINE_MASK))>>2 ); + + + // Hit test. Just to verify. + bool hit = (r_tlb_buf_valid && (r_tlb_buf_tag.read()== line_number) ); + assert(hit and "Error: No hit on prefetch buffer after Miss Transaction"); + pte_flags= r_tlb_buf_data[word_position]; + pte_ppn= r_tlb_buf_data[word_position+1]; //because PTE2 is 2 words long + // Bit valid checking + if ( not ( pte_flags & PTE_V_MASK) ) // unmapped + { + //must not occur! + std::cout << "IOMMU ERROR " << name() << "TLB_IDLE state" << std::endl + << "The Page Table entry ins't valid (unmapped)" << std::endl; + + r_tlb_miss_error = true; + r_dma_cmd_to_tlb_req = false; + r_tlb_fsm = TLB_IDLE; + +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +std::cout << name() + << " PTE2 Unmapped" << std::hex + << " / PADDR = " << r_tlb_paddr.read() + << " / PTE = " << pte_flags << std::endl; +#endif + break; + } + + r_tlb_pte_flags = pte_flags; + r_tlb_pte_ppn = pte_ppn; + r_tlb_fsm = TLB_PTE2_SELECT; + +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +std::cout << name() + << " Mapped" << std::hex + << " / PTE_FLAGS = " << pte_flags + << " / PTE_PPN = " << pte_ppn << std::endl; +#endif + break; + } + //////////////////////////// + case TLB_PTE2_SELECT: // select a slot for PTE2 + { + size_t way; + size_t set; + + r_iotlb.select( r_dma_cmd_to_tlb_vaddr.read(), + false, // PTE2 + &way, + &set ); +#ifdef INSTRUMENTATION +m_cpt_iotlb_read++; +#endif + +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +std::cout << name() + << " Select a slot in IOTLB:" + << " way = " << std::dec << way + << " / set = " << set << std::endl; +#endif + r_tlb_way = way; + r_tlb_set = set; + r_tlb_fsm = TLB_PTE2_UPDT; + break; + } + /////////////////// + case TLB_PTE2_UPDT: // write a new PTE2 in tlb + // not necessary to treat the L/R bit + { + uint32_t pte_flags = r_tlb_pte_flags.read(); + uint32_t pte_ppn = r_tlb_pte_ppn.read(); + + r_tlb_paddr = (vci_addr_t)( ((r_tlb_pte_ppn.read() & PPN2_MASK) << 12) + | (r_dma_cmd_to_tlb_vaddr.read()& K_PAGE_OFFSET_MASK) ); + + // update TLB for a PTE2 + r_iotlb.write( false, // 4K page + pte_flags, + pte_ppn, + r_dma_cmd_to_tlb_vaddr.read(), + r_tlb_way.read(), + r_tlb_set.read(), + 0 ); // nline = 0 +#ifdef INSTRUMENTATION +m_cpt_iotlb_write++; +#endif + +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +{ +std::cout << name() + << " write PTE2 in IOTLB" + << " / set = " << std::dec << r_tlb_set.read() + << " / way = " << r_tlb_way.read() << std::endl; +r_iotlb.printTrace(); +} +#endif + // next state + r_tlb_fsm = TLB_RETURN; + break; + } + ////////////// + case TLB_WAIT: // waiting completion of a miss transaction from MISS_WTI FSM + // PTE inval request are handled as unmaskable interrupts + { + if ( r_config_cmd_to_tlb_req.read() ) // Request for a PTE invalidation + { + r_config_cmd_to_tlb_req = false; + r_waiting_transaction = true; + r_tlb_fsm = TLB_INVAL_CHECK; + } + +#ifdef INSTRUMENTATION +m_cost_iotlbmiss_transaction++; +#endif + if ( not r_tlb_to_miss_wti_cmd_req.read() ) // Miss transaction completed + { + if ( r_miss_wti_rsp_error_miss.read() ) // bus error reported + { + r_miss_wti_rsp_error_miss = false; + r_tlb_miss_error = true; + r_dma_cmd_to_tlb_req = false; + r_tlb_fsm = TLB_IDLE; + } + else if(r_tlb_miss_type == PTE1_MISS) + { + r_tlb_fsm = TLB_PTE1_GET; + } + else + { + r_tlb_fsm = TLB_PTE2_GET; + } + } + break; + } + //////////////// + case TLB_RETURN: // reset r_dma_cmd_to_tlb_req to signal TLB miss completion + // possible errors are signaled through r_tlb_miss_error + { +#if DEBUG_TLB_MISS +if ( m_debug_activated ) +std::cout << name() + << " IOTLB MISS completed" << std::endl; +#endif + r_dma_cmd_to_tlb_req = false; + r_tlb_fsm = TLB_IDLE; + break; + } + ///////////////////// + case TLB_INVAL_CHECK: // request from CONFIG_FSM to invalidate all PTE in a given line + // checks the necessity to invalidate prefetch buffer + { + // If a transaction is pending, no need to invalidate the prefetch + // We can ignore it, since we'll replace the line. + // The new line is necessarily up-to-date + if(!r_waiting_transaction.read() && r_tlb_buf_valid) + { + if(!r_tlb_buf_big_page) + { + if( r_tlb_buf_vaddr.read() == + (r_config_cmd_to_tlb_vaddr.read()& ~PTE2_LINE_OFFSET) ) + // The virtual address corresponds to one entry on the buffer line + { + r_tlb_buf_valid = false; //change here for individual invalidation + } + } + else // First level entries on buffer. Unused if only small pages + { + if( r_tlb_buf_vaddr.read() == + (r_config_cmd_to_tlb_vaddr.read()& ~PTE1_LINE_OFFSET) ) + // The virtual address corresponds to one entry on the buffer line + { + r_tlb_buf_valid = false; //change here for individual invalidation + } + } + } + + // Invalidation on IOTLB + r_iotlb.inval(r_config_cmd_to_tlb_vaddr.read()); + + if(r_waiting_transaction.read()) r_tlb_fsm =TLB_WAIT; + else r_tlb_fsm = TLB_IDLE; + break; + } + } //end switch r_tlb_fsm + + //////////////////////////////////////////////////////////////////////////////// + // The CONFIG_CMD_FSM handles the VCI commands from the INT network. + // - it can be single flit config transactions + // - it can be multi-flits data transactions to ROM (read) or FBF (write). + // The write burst transactions must be serialised from 32 to 64 bits width. + // The configuration requests can be local (IO_BRIDGE config registers) + // or remote (config registers of peripherals on IOX network). + // - The local configuration segment is identified by the "special" atribute + // in the mapping table. + // - All configuration requests are checked against segmentation violation. + // - In case of local config request, or in case of segmentation violation, + // the FSM send a response request to CONFIG_RSP FSM. + // - In case of remote transaction, it put the VCI command in CONFIG_CMD fifo, + // and this require two cycles per IOX flit in case of write burst. + /////////////////////////////////////////////////////////////////////////////// + + switch( r_config_cmd_fsm.read() ) + { + ///////////////////// + case CONFIG_CMD_IDLE: // A VCI INT command is always consumed in this state + { + if ( p_vci_tgt_int.cmdval.read() ) + { + +#if DEBUG_CONFIG_CMD +if( m_debug_activated ) +std::cout << name() + << " ### Config Command received" << std::endl + << " address = " << std::hex << p_vci_tgt_int.address.read() + << " / srcid = " << p_vci_tgt_int.srcid.read() + << " / trdid = " << p_vci_tgt_int.trdid.read() + << " / pktid = " << p_vci_tgt_int.pktid.read() + << " / wdata = " << std::hex << p_vci_tgt_int.wdata.read() + << " / be = " << p_vci_tgt_int.be.read() + << " / plen = " << std::dec << p_vci_tgt_int.plen.read() + << " / eop = " << p_vci_tgt_int.eop.read() << std::endl; +#endif + vci_addr_t paddr = p_vci_tgt_int.address.read(); + bool read = (p_vci_tgt_int.cmd.read() == vci_param_int::CMD_READ); + uint32_t cell = (uint32_t)((paddr & 0x1FF)>>2); + bool eop = p_vci_tgt_int.eop.read(); + bool high = (paddr & 0x4); + ext_data_t wdata = (ext_data_t)p_vci_tgt_int.wdata.read(); + ext_be_t be = (ext_be_t)p_vci_tgt_int.be.read(); + + // chek segments + std::list::iterator seg; + bool found = false; + bool special = false; + for ( seg = m_int_seglist.begin() ; + seg != m_int_seglist.end() and not found ; seg++ ) + { + if ( seg->contains(paddr) ) + { + found = true; + special = seg->special(); + } + } + + if ( found and special ) // IO_BRIDGE itself + { + bool rerror = false; + int_data_t rdata; + + assert( (be == 0xF) and + "ERROR in vci_io_bridge : BE must be 0xF for a config access"); + + assert( ( eop ) and + "ERROR in vci_io_bridge : local config access must be one flit"); + + if ( not read && (cell == IOB_IOMMU_PTPR) ) // WRITE PTPR + { + r_iommu_ptpr = (uint32_t)wdata; + } + else if ( read && (cell == IOB_IOMMU_PTPR) ) // READ PTPR + { + rdata = r_iommu_ptpr.read(); + } + else if( not read && (cell == IOB_WTI_ENABLE)) // WRITE WTI_ENABLE + { + r_iommu_wti_enable = wdata; + } + else if( read && (cell == IOB_WTI_ENABLE)) // READ WTI ENABLE + { + rdata = r_iommu_wti_enable.read(); + } + else if( read && (cell == IOB_IOMMU_BVAR)) // READ BVAR + { + rdata = r_iommu_bvar.read(); + } + else if( read && (cell == IOB_IOMMU_ETR)) // READ ETR + { + rdata = r_iommu_etr.read(); + } + else if( read && (cell == IOB_IOMMU_BAD_ID)) // READ BAD_ID + { + rdata = r_iommu_bad_id.read(); + } + else if( not read && (cell == IOB_INVAL_PTE)) // WRITE INVAL_PTE + { + r_config_cmd_to_tlb_req = true; + r_config_cmd_to_tlb_vaddr = (uint32_t)wdata; + } + else if( not read && (cell == IOB_WTI_ADDR_LO)) // WRITE WTI_PADDR_LO + { + r_iommu_wti_addr_lo = (vci_addr_t)wdata; + } + else if( read && (cell == IOB_WTI_ADDR_LO)) // READ WTI_PADDR_LO + { + rdata = r_iommu_wti_addr_lo.read(); + } + else if( not read && (cell == IOB_WTI_ADDR_HI)) // WRITE WTI_PADDR_HI + { + r_iommu_wti_addr_hi = (vci_addr_t)wdata; + } + else if( read && (cell == IOB_WTI_ADDR_HI)) // READ WTI_PADDR_HI + { + rdata = r_iommu_wti_addr_hi.read(); + } + else // Error: Wrong address, or invalid operation. + { + rerror = true; + } + r_config_cmd_to_config_rsp_rerror = rerror; + r_config_cmd_to_config_rsp_rdata = rdata; + r_config_cmd_to_config_rsp_rsrcid = p_vci_tgt_int.srcid.read(); + r_config_cmd_to_config_rsp_rtrdid = p_vci_tgt_int.trdid.read(); + r_config_cmd_to_config_rsp_rpktid = p_vci_tgt_int.pktid.read(); + r_config_cmd_fsm = CONFIG_CMD_RSP; + } + else if ( found ) // remote peripheral + { + // buffer VCI command + r_config_cmd_address = p_vci_tgt_int.address.read(); + r_config_cmd_pktid = p_vci_tgt_int.pktid.read(); + r_config_cmd_plen = p_vci_tgt_int.plen.read(); + r_config_cmd_cmd = p_vci_tgt_int.cmd.read(); + r_config_cmd_cons = p_vci_tgt_int.cons.read(); + r_config_cmd_clen = p_vci_tgt_int.clen.read(); + r_config_cmd_wrap = p_vci_tgt_int.wrap.read(); + r_config_cmd_contig = p_vci_tgt_int.contig.read(); + r_config_cmd_cfixed = p_vci_tgt_int.cfixed.read(); + r_config_cmd_eop = eop; + r_config_cmd_wdata = (wdata << (high ? 32 : 0)); + r_config_cmd_be = (be << (high ? 4 : 0)); + + size_t tab_index; + if (m_iox_transaction_tab.full(tab_index)) + { +#ifdef INSTRUMENTATION +m_cpt_trt_config_full++; +#endif + + // wait for an empty slot in the IOX transaction table. + // buffer SRCID and TRDID of VCI command to store them + // later in IOX transaction table. + r_config_cmd_srcid = p_vci_tgt_int.srcid.read(); + r_config_cmd_trdid = p_vci_tgt_int.trdid.read(); + r_config_cmd_fsm = CONFIG_CMD_WAIT; + break; + } + + // TRDID in IOX interconnect is the translation table index + r_config_cmd_trdid = tab_index; + + // create new entry in IOX transaction table + m_iox_transaction_tab.set( tab_index, + p_vci_tgt_int.srcid.read(), + p_vci_tgt_int.trdid.read()); + + if (eop) r_config_cmd_fsm = CONFIG_CMD_PUT; + else r_config_cmd_fsm = CONFIG_CMD_HI; + +#if DEBUG_CONFIG_CMD +if( m_debug_activated ) +{ +std::cout << name() + << " ### new entry in IOX transaction table" + << std::endl; +m_iox_transaction_tab.printTrace(); +} +#endif + + } + else if ( eop ) // out of segment address + { + r_config_cmd_to_config_rsp_rerror = true; + r_config_cmd_to_config_rsp_rdata = 0; + r_config_cmd_to_config_rsp_rsrcid = p_vci_tgt_int.srcid.read(); + r_config_cmd_to_config_rsp_rtrdid = p_vci_tgt_int.trdid.read(); + r_config_cmd_to_config_rsp_rpktid = p_vci_tgt_int.pktid.read(); + r_config_cmd_fsm = CONFIG_CMD_RSP; + } + } // end if cmdval + break; + } + ///////////////////// + case CONFIG_CMD_WAIT: + { + // wait for an empty slot in the translation table. + size_t tab_index; + if (m_iox_transaction_tab.full(tab_index)) + { +#ifdef INSTRUMENTATION +m_cpt_trt_config_full_cost++; +#endif + break; + } + + // create new entry in IOX transaction table + m_iox_transaction_tab.set( tab_index, + r_config_cmd_srcid.read(), + r_config_cmd_trdid.read()); + + // TRDID in IOX interconnect is the translation table index + r_config_cmd_trdid = tab_index; + if (r_config_cmd_eop.read()) r_config_cmd_fsm = CONFIG_CMD_PUT; + else r_config_cmd_fsm = CONFIG_CMD_HI; + +#if DEBUG_CONFIG_CMD +if( m_debug_activated ) +{ +std::cout << name() + << " ### new entry in IOX transaction table" + << std::endl; +m_iox_transaction_tab.printTrace(); +} +#endif + break; + } + ///////////////////// + case CONFIG_CMD_HI: // consume the second flit for a multi-flits write + { + if ( p_vci_tgt_int.cmdval.read() ) + { + vci_addr_t paddr = p_vci_tgt_int.address.read(); + bool high = ((paddr & 0x4) == 0x4); + bool eop = p_vci_tgt_int.eop.read(); + + assert( (paddr == r_config_cmd_address.read() + 4) and high and + "ERROR in vci_io_bridge : addresses must be contiguous in write burst" ); + + r_config_cmd_wdata = r_config_cmd_wdata.read() | + ((ext_data_t)p_vci_tgt_int.wdata.read()<<32); + r_config_cmd_be = r_config_cmd_be.read() | + ((ext_be_t)p_vci_tgt_int.be.read()<<4); + r_config_cmd_eop = eop; + r_config_cmd_fsm = CONFIG_CMD_PUT; + } + break; + } + ///////////////////// + case CONFIG_CMD_LO: // consume the first flit for a multi-flits write + { + if ( p_vci_tgt_int.cmdval.read() ) + { + vci_addr_t paddr = p_vci_tgt_int.address.read(); + bool high = ((paddr & 0x4) == 0x4); + bool eop = p_vci_tgt_int.eop.read(); + + assert( (paddr == r_config_cmd_address.read() + 4) and !high and + "ERROR in vci_io_bridge : addresses must be contiguous in write burst" ); + + r_config_cmd_address = p_vci_tgt_int.address.read(); + r_config_cmd_wdata = (ext_data_t)p_vci_tgt_int.wdata.read(); + r_config_cmd_be = (ext_be_t)p_vci_tgt_int.be.read(); + r_config_cmd_eop = eop; + + if (eop) r_config_cmd_fsm = CONFIG_CMD_PUT; + else r_config_cmd_fsm = CONFIG_CMD_HI; + } + break; + } + //////////////////// + case CONFIG_CMD_PUT: // post a command to CONFIG_CMD fifo (to IOX network) + { + config_cmd_fifo_put = true; + + if ( m_config_cmd_addr_fifo.wok() ) + { + +#if DEBUG_CONFIG_CMD +if( m_debug_activated ) +std::cout << name() + << " Transmit VCI command to IOX network" + << " : address = " << std::hex << r_config_cmd_address.read() + << " / srcid = " << m_iox_srcid + << " / trdid = " << r_config_cmd_trdid.read() + << " / eop = " << r_config_cmd_eop.read() + << std::endl; +#endif + if (r_config_cmd_eop.read()) r_config_cmd_fsm = CONFIG_CMD_IDLE; + else r_config_cmd_fsm = CONFIG_CMD_LO; + } + break; + } + //////////////////// + case CONFIG_CMD_RSP: // Post a request to CONFIG_RSP FSM, + // if no previous pending request. + // r_config_cmd_to_config_rsp_rerror + // has been set in IDLE state. + { + if ( not r_config_cmd_to_config_rsp_req.read() ) + { + r_config_cmd_to_config_rsp_req = true; + +#if DEBUG_CONFIG_CMD +if( m_debug_activated ) +std::cout << name() + << " Request a response to CONFIG_RSP FSM" + << " / error = " << r_config_cmd_to_config_rsp_rerror.read() << std::endl; +#endif + r_config_cmd_fsm = CONFIG_CMD_IDLE; + } + break; + } + } // end switch CONFIG_CMD FSM + + ////////////////////////////////////////////////////////////////////////////// + // The CONFIG_RSP_FSM controls access to the CONFIG_RSP FIFO to INT network. + // It implements a round robin priority between 2 clients FSMs : + // - CONFIG_CMD : response to a local config command. + // - CONFIG_RSP : responses from peripherals on IOX network + // Regarding the responses from IOX network it handles both single flit + // config responses, and multi-flits read responses (ROM), where data must + // be serialised (64 bits -> 32 bits). + // Note: We use the VCI RPKTID field to distinguish between read cached + // (multi-flits response) and others (single flit response). + // The VCI response flit is only consumed in the PUT_UNC or PUT_HI states. + ////////////////////////////////////////////////////////////////////////////// + + // does nothing if FIFO full + if ( m_config_rsp_rerror_fifo.wok() ) + { + switch( r_config_rsp_fsm.read() ) + { + ///////////////////////// + case CONFIG_RSP_IDLE_IOX: // IOX requests have highest priority + // no flit on IOX network is consumed + { + if ( p_vci_ini_iox.rspval.read() ) // IOX request + { + // recover srcid and trdid from the IOX transaction table + size_t tab_index = (size_t)p_vci_ini_iox.rtrdid.read(); + r_config_rsp_rsrcid = m_iox_transaction_tab.readSrcid(tab_index); + r_config_rsp_rtrdid = m_iox_transaction_tab.readTrdid(tab_index); + + // erase entry + m_iox_transaction_tab.erase(tab_index); + + if ( (p_vci_ini_iox.rpktid.read() & 0x5) == 0x1 ) // multi-flits + { + r_config_rsp_fsm = CONFIG_RSP_PUT_LO; + } + else // single flit + { + r_config_rsp_fsm = CONFIG_RSP_PUT_UNC; + } +#if DEBUG_CONFIG_RSP +if( m_debug_activated ) +{ +std::cout << name() + << " ### remove entry in transaction table" + << std::endl; +m_iox_transaction_tab.printTrace(); +} +#endif + } + else if ( r_config_cmd_to_config_rsp_req.read() ) // LOCAL request + { + r_config_rsp_fsm = CONFIG_RSP_PUT_LOC; + } + break; + } + ///////////////////////// + case CONFIG_RSP_IDLE_LOC: // LOCAL requests have highest priority + // no flit on IOX network is consumed + { + if ( r_config_cmd_to_config_rsp_req.read() ) // LOCAL request + { + r_config_rsp_fsm = CONFIG_RSP_PUT_LOC; + } + else if ( p_vci_ini_iox.rspval.read() ) // IOX request + { + // recover srcid and trdid from the IOX transaction table + size_t tab_index = (size_t)p_vci_ini_iox.rtrdid.read(); + r_config_rsp_rsrcid = m_iox_transaction_tab.readSrcid(tab_index); + r_config_rsp_rtrdid = m_iox_transaction_tab.readTrdid(tab_index); + + // erase entry + m_iox_transaction_tab.erase(tab_index); + + if ( (p_vci_ini_iox.rpktid.read() & 0x5) == 0x1 ) // multi-flits + { + r_config_rsp_fsm = CONFIG_RSP_PUT_LO; + } + else // single flit + { + r_config_rsp_fsm = CONFIG_RSP_PUT_UNC; + } +#if DEBUG_CONFIG_RSP +if( m_debug_activated ) +{ +std::cout << name() + << " ### remove entry in transaction table" + << std::endl; +m_iox_transaction_tab.printTrace(); +} +#endif + } + break; + } + //////////////////////// + case CONFIG_RSP_PUT_LO: // put 32 low bits into CONFIG_RSP fifo + // no flit on IOX network is consumed + { + config_rsp_fifo_put = true; + config_rsp_fifo_rerror = p_vci_ini_iox.rerror.read(); + config_rsp_fifo_rdata = (uint32_t)p_vci_ini_iox.rdata.read(); + config_rsp_fifo_rsrcid = r_config_rsp_rsrcid.read(); + config_rsp_fifo_rtrdid = r_config_rsp_rtrdid.read(); + config_rsp_fifo_rpktid = p_vci_ini_iox.rpktid.read(); + config_rsp_fifo_reop = false; + + r_config_rsp_fsm = CONFIG_RSP_PUT_HI; + +#if DEBUG_CONFIG_RSP +if( m_debug_activated ) +std::cout << name() + << " Push multi-flit response into CONFIG_RSP FIFO" + << " / rsrcid = " << std::hex << r_config_rsp_rsrcid.read() + << " / rtrdid = " << r_config_rsp_rtrdid.read() + << " / rpktid = " << p_vci_ini_iox.rpktid.read() + << " / rdata = " << (uint32_t)p_vci_ini_iox.rdata.read() + << " / reop = " << false + << " / rerror = " << p_vci_ini_iox.rerror.read() << std::endl; +#endif + break; + } + /////////////////////// + case CONFIG_RSP_PUT_HI: // put 32 high bits into CONFIG_RSP fifo + // flit on IOX network is consumed + { + config_rsp_fifo_put = true; + config_rsp_fifo_rerror = p_vci_ini_iox.rerror.read(); + config_rsp_fifo_rdata = (uint32_t)(p_vci_ini_iox.rdata.read() >> 32); + config_rsp_fifo_rsrcid = r_config_rsp_rsrcid.read(); + config_rsp_fifo_rtrdid = r_config_rsp_rtrdid.read(); + config_rsp_fifo_rpktid = p_vci_ini_iox.rpktid.read(); + config_rsp_fifo_reop = p_vci_ini_iox.reop.read(); + + if( p_vci_ini_iox.reop.read() ) r_config_rsp_fsm = CONFIG_RSP_IDLE_LOC; + else r_config_rsp_fsm = CONFIG_RSP_PUT_LO; + +#if DEBUG_CONFIG_RSP +if( m_debug_activated ) +std::cout << name() + << " Push multi-flit response into CONFIG_RSP FIFO" + << " / rsrcid = " << std::hex << r_config_rsp_rsrcid.read() + << " / rtrdid = " << r_config_rsp_rtrdid.read() + << " / rpktid = " << p_vci_ini_iox.rpktid.read() + << " / rdata = " << (uint32_t)(p_vci_ini_iox.rdata.read() >> 32) + << " / reop = " << p_vci_ini_iox.reop.read() + << " / rerror = " << p_vci_ini_iox.rerror.read() << std::endl; +#endif + break; + } + //////////////////////// + case CONFIG_RSP_PUT_UNC: // put single flit into CONFIG_RSP fifo + // flit on IOX network is consumed + { + assert( p_vci_ini_iox.reop.read() and + "ERROR in vci_io_bridge : a remote config response should be one flit"); + + config_rsp_fifo_put = true; + config_rsp_fifo_rerror = p_vci_ini_iox.rerror.read(); + config_rsp_fifo_rdata = (uint32_t)p_vci_ini_iox.rdata.read(); + config_rsp_fifo_rsrcid = r_config_rsp_rsrcid.read(); + config_rsp_fifo_rtrdid = r_config_rsp_rtrdid.read(); + config_rsp_fifo_rpktid = p_vci_ini_iox.rpktid.read(); + config_rsp_fifo_reop = true; + + // update priority + r_config_rsp_fsm = CONFIG_RSP_IDLE_LOC; + +#if DEBUG_CONFIG_RSP +if( m_debug_activated ) +std::cout << name() + << " Push single flit response into CONFIG_RSP FIFO" + << " / rsrcid = " << std::hex << r_config_rsp_rsrcid.read() + << " / rtrdid = " << r_config_rsp_rtrdid.read() + << " / rpktid = " << p_vci_ini_iox.rpktid.read() + << " / rdata = " << (uint32_t)p_vci_ini_iox.rdata.read() + << " / reop = " << true + << " / rerror = " << p_vci_ini_iox.rerror.read() << std::endl; +#endif + break; + } + //////////////////////// + case CONFIG_RSP_PUT_LOC: // put single flit into CONFIG_RSP fifo + // no flit on IOX network is consumed + { + config_rsp_fifo_put = true; + config_rsp_fifo_rerror = r_config_cmd_to_config_rsp_rerror.read(); + config_rsp_fifo_rdata = r_config_cmd_to_config_rsp_rdata.read(); + config_rsp_fifo_rsrcid = r_config_cmd_to_config_rsp_rsrcid.read(); + config_rsp_fifo_rtrdid = r_config_cmd_to_config_rsp_rtrdid.read(); + config_rsp_fifo_rpktid = r_config_cmd_to_config_rsp_rpktid.read(); + config_rsp_fifo_reop = true; + + // acknowledge request + r_config_cmd_to_config_rsp_req = false; + + // update priority + r_config_rsp_fsm = CONFIG_RSP_IDLE_IOX; + +#if DEBUG_CONFIG_RSP +if( m_debug_activated ) +std::cout << name() + << " Push single flit response into CONFIG_RSP FIFO" + << " / rsrcid = " << std::hex << r_config_cmd_to_config_rsp_rsrcid.read() + << " / rtrdid = " << r_config_cmd_to_config_rsp_rtrdid.read() + << " / rpktid = " << r_config_cmd_to_config_rsp_rpktid.read() + << " / rdata = " << r_config_cmd_to_config_rsp_rdata.read() + << " / reop = " << true + << " / rerror = " << r_config_cmd_to_config_rsp_rerror.read() << std::endl; +#endif + break; + } + } // end switch CONFIG_RSP FSM + } // end if FIFO full + + /////////////////////////////////////////////////////////////////////////////////// + // The MISS_WTI_CMD component is a combinational switch that push one single flit + // VCI command in the MISS_WTI FIFO to INT Network, depending on two clients : + // 1. MISS requests from TLB_MISS FSM : + // These requests have highest priority because a TLB MISS is a blocking event + // for the DMA FSM. The r_tlb_to_miss_wti_cmd_req flip-flop is reset by the + // MISS_WTI_RSP FSM only when the response is received. + // 2. WTI requests from DMA_CMD FSM : + // These requestsare non blocking events, and the r_dma_cmd_to_miss_wti_cmd_req + // flip-flop is reset as soon as the WTI command has been sent. + // There is two types of WTI requests: + // - external WTI from peripherals on IOX network. + // - internal WTI caused by illegal DMA requests. + //////////////////////////////////////////////////////////////////////////////////// + + if ( r_tlb_to_miss_wti_cmd_req.read() and + m_miss_wti_cmd_addr_fifo.wok() ) // put MISS READ + { + miss_wti_cmd_fifo_put = true; + miss_wti_cmd_fifo_address = r_tlb_paddr.read(); + miss_wti_cmd_fifo_wdata = 0; + miss_wti_cmd_fifo_cmd = vci_param_int::CMD_READ; + miss_wti_cmd_fifo_pktid = PKTID_MISS; + miss_wti_cmd_fifo_srcid = m_int_srcid; + miss_wti_cmd_fifo_trdid = 0; + +#if DEBUG_MISS_WTI_CMD +if( m_debug_activated ) +std::cout << name() + << " push MISS TLB command into MISS_WTI FIFO" + << " / PADDR = " << miss_wti_cmd_fifo_address << std::endl; +#endif + + } + else if ( r_dma_cmd_to_miss_wti_cmd_req.read() and + m_miss_wti_cmd_addr_fifo.wok() ) // put WTI READ / WRITE + { + r_dma_cmd_to_miss_wti_cmd_req = false; + + miss_wti_cmd_fifo_put = true; + miss_wti_cmd_fifo_cmd = r_dma_cmd_to_miss_wti_cmd_cmd.read(); + miss_wti_cmd_fifo_address = r_dma_cmd_to_miss_wti_cmd_addr.read(); + miss_wti_cmd_fifo_wdata = r_dma_cmd_to_miss_wti_cmd_wdata.read(); + miss_wti_cmd_fifo_srcid = r_dma_cmd_to_miss_wti_cmd_srcid.read(); + miss_wti_cmd_fifo_trdid = r_dma_cmd_to_miss_wti_cmd_trdid.read(); + miss_wti_cmd_fifo_pktid = r_dma_cmd_to_miss_wti_cmd_pktid.read(); + +#if DEBUG_MISS_WTI_CMD +if( m_debug_activated ) +std::cout << name() + << " push WTI command into MISS_WTI FIFO" + << " / CMD = " << miss_wti_cmd_fifo_cmd + << " / PADDR = " << miss_wti_cmd_fifo_address << std::endl; +#endif + + } + + /////////////////////////////////////////////////////////////////////////////////// + // The MISS_WTI_RSP FSM handles VCI responses from the INT network: + // - for a TLB MISS (multi-flits read transaction), the cache line + // is written in r_tlb_buf_data[], and r_tlb_to_miss_wti_cmd_req flip-flop is reset. + // - for a WTI_IOX (single flit write transaction), the response must be + // forwarded to the source peripheral on the INT network + // - for a WTI_MMU (single flit write transaction), there is nothing to do. + // + // TODO VCI addressing errors for TLB MISS or for WTI_MMU (i.e. kernel errors...) + // are registered in the r_miss_wti_rsp_error_miss & r_miss_wti_rsp_error_wti + // flip-flops, and simulation stops... They could be signaled to OS by a WTI. + //////////////////////////////////////////////////////////////////////////////////// + + switch ( r_miss_wti_rsp_fsm.read() ) + { + /////////////////////// + case MISS_WTI_RSP_IDLE: // waiting a VCI response + // no VCI flit is consumed + { + if ( p_vci_ini_int.rspval.read() ) + { + if ( p_vci_ini_int.rpktid.read() == PKTID_WTI_IOX ) + { + r_miss_wti_rsp_fsm = MISS_WTI_RSP_WTI_IOX; + } + else if ( p_vci_ini_int.rpktid.read() == PKTID_WTI_MMU ) + { + r_miss_wti_rsp_fsm = MISS_WTI_RSP_WTI_MMU; + } + else if ( p_vci_ini_int.rpktid.read() == PKTID_MISS ) + { + r_miss_wti_rsp_fsm = MISS_WTI_RSP_MISS; + r_miss_wti_rsp_count = 0; + } + else + { + assert ( false and + "VCI_IO_BRIDGE ERROR : illegal response type on INT network"); + } + } + break; + } + ////////////////////////// + case MISS_WTI_RSP_WTI_IOX: // Handling response to a peripheral WTI + // consume VCI flit and transfer response + // to DMA_RSP FSM in dedicated registers + // if no pending previous request. + { + assert( p_vci_ini_int.reop.read() and + "VCI_IO_BRIDGE ERROR: WTI_IOX response should have one single flit" ); + + if ( not r_miss_wti_rsp_to_dma_rsp_req.read() ) // no previous pending request + { + r_miss_wti_rsp_to_dma_rsp_req = true; + r_miss_wti_rsp_to_dma_rsp_rerror = p_vci_ini_int.rerror.read(); + r_miss_wti_rsp_to_dma_rsp_rsrcid = p_vci_ini_int.rsrcid.read(); + r_miss_wti_rsp_to_dma_rsp_rtrdid = p_vci_ini_int.rtrdid.read(); + r_miss_wti_rsp_to_dma_rsp_rpktid = p_vci_ini_int.rpktid.read(); + + r_miss_wti_rsp_fsm = MISS_WTI_RSP_IDLE; + +#if DEBUG_MISS_WTI_RSP +if( m_debug_activated ) +std::cout << name() + << " Transfer response to a WTI_IOX" << std::endl; +#endif + } + break; + } + ////////////////////////// + case MISS_WTI_RSP_WTI_MMU: // Handling response to an iommu WTI + // consume VCI flit and test VCI error. + { + assert( p_vci_ini_int.reop.read() and + "VCI_IO_BRIDGE ERROR: WTI_MMU response should have one single flit" ); + + if ( (p_vci_ini_int.rerror.read()&0x1) != 0 ) // error reported + { + // set the specific error flip-flop + r_miss_wti_rsp_error_wti = true; + assert( false and + "VCI_IO_BRIDGE ERROR: VCI error response for a WTI_MMU transaction"); + } + +#if DEBUG_MISS_WTI_RSP +if( m_debug_activated ) +std::cout << name() + << " Receive response to a WTI_MMU" << std::endl; +#endif + break; + } + /////////////////////// + case MISS_WTI_RSP_MISS: // Handling response to a TLB MISS + // write cache line in r_tlb_buf buffer + // and analyse possible VCI error + // VCI flit is consumed. + { + if ( p_vci_ini_int.rspval.read() ) + { + if ( (p_vci_ini_int.rerror.read()&0x1) != 0 ) // error reported + { + // set the specific error flip-flop + r_miss_wti_rsp_error_miss = true; + assert( false and + "VCI_IO_BRIDGE ERROR: VCI error response for a TLB MISS transaction"); + + } + else // no error + { + +#if DEBUG_MISS_WTI_CMD +if( m_debug_activated ) +std::cout << name() + << " Receive response to a TLB MISS" + << " / Count = " << r_miss_wti_rsp_count.read() + << " / Data = " << std::hex << p_vci_ini_int.rdata.read() << std::endl; +#endif + r_tlb_buf_data[r_miss_wti_rsp_count.read()] = p_vci_ini_int.rdata.read(); + } + + if ( p_vci_ini_int.reop.read() ) // last flit + { + bool eop = p_vci_ini_int.eop.read(); + assert(((eop == (r_miss_wti_rsp_count.read() == (m_words-1)))) and + "VCI_IO_BRIDGE ERROR: invalid length for a TLB MISS response"); + + r_miss_wti_rsp_count = 0; + r_miss_wti_rsp_fsm = MISS_WTI_RSP_IDLE; + r_tlb_to_miss_wti_cmd_req = false; + } + else // not the last flit + { + r_miss_wti_rsp_count = r_miss_wti_rsp_count.read() + 1; + } + } + break; + } + } // end switch r_miss_wti_rsp_fsm + + + /////////////////////////////////////////////////////////// + // DMA_CMD fifo update + // writer : DMA_CMD FSM + /////////////////////////////////////////////////////////// + + m_dma_cmd_addr_fifo.update( dma_cmd_fifo_get, + dma_cmd_fifo_put, + r_dma_cmd_paddr.read() ); // address translation + m_dma_cmd_cmd_fifo.update( dma_cmd_fifo_get, + dma_cmd_fifo_put, + p_vci_tgt_iox.cmd.read() ); + m_dma_cmd_contig_fifo.update( dma_cmd_fifo_get, + dma_cmd_fifo_put, + p_vci_tgt_iox.contig.read() ); + m_dma_cmd_cons_fifo.update( dma_cmd_fifo_get, + dma_cmd_fifo_put, + p_vci_tgt_iox.cons.read() ); + m_dma_cmd_plen_fifo.update( dma_cmd_fifo_get, + dma_cmd_fifo_put, + p_vci_tgt_iox.plen.read() ); + m_dma_cmd_wrap_fifo.update( dma_cmd_fifo_get, + dma_cmd_fifo_put, + p_vci_tgt_iox.wrap.read() ); + m_dma_cmd_cfixed_fifo.update( dma_cmd_fifo_get, + dma_cmd_fifo_put, + p_vci_tgt_iox.cfixed.read() ); + m_dma_cmd_clen_fifo.update( dma_cmd_fifo_get, + dma_cmd_fifo_put, + p_vci_tgt_iox.clen.read() ); + m_dma_cmd_srcid_fifo.update( dma_cmd_fifo_get, + dma_cmd_fifo_put, + dma_cmd_fifo_srcid ); + m_dma_cmd_trdid_fifo.update( dma_cmd_fifo_get, + dma_cmd_fifo_put, + p_vci_tgt_iox.trdid.read() ); + m_dma_cmd_pktid_fifo.update( dma_cmd_fifo_get, + dma_cmd_fifo_put, + p_vci_tgt_iox.pktid.read() ); + m_dma_cmd_data_fifo.update( dma_cmd_fifo_get, + dma_cmd_fifo_put, + p_vci_tgt_iox.wdata.read() ); + m_dma_cmd_be_fifo.update( dma_cmd_fifo_get, + dma_cmd_fifo_put, + p_vci_tgt_iox.be.read() ); + m_dma_cmd_eop_fifo.update( dma_cmd_fifo_get, + dma_cmd_fifo_put, + p_vci_tgt_iox.eop.read() ); + + ////////////////////////////////////////////////////////////// + // DMA_RSP fifo update + // writer : DMA_RSP FSM + ////////////////////////////////////////////////////////////// + + m_dma_rsp_data_fifo.update( dma_rsp_fifo_get, + dma_rsp_fifo_put, + dma_rsp_fifo_rdata ); + m_dma_rsp_rsrcid_fifo.update( dma_rsp_fifo_get, + dma_rsp_fifo_put, + dma_rsp_fifo_rsrcid ); + m_dma_rsp_rtrdid_fifo.update( dma_rsp_fifo_get, + dma_rsp_fifo_put, + dma_rsp_fifo_rtrdid ); + m_dma_rsp_rpktid_fifo.update( dma_rsp_fifo_get, + dma_rsp_fifo_put, + dma_rsp_fifo_rpktid ); + m_dma_rsp_reop_fifo.update( dma_rsp_fifo_get, + dma_rsp_fifo_put, + dma_rsp_fifo_reop ); + m_dma_rsp_rerror_fifo.update( dma_rsp_fifo_get, + dma_rsp_fifo_put, + dma_rsp_fifo_rerror ); + + //////////////////////////////////////////////////////////////// + // CONFIG_CMD fifo update + // writer : CONFIG_CMD FSM + //////////////////////////////////////////////////////////////// + + m_config_cmd_addr_fifo.update( config_cmd_fifo_get, + config_cmd_fifo_put, + r_config_cmd_address.read() ); + m_config_cmd_cmd_fifo.update( config_cmd_fifo_get, + config_cmd_fifo_put, + r_config_cmd_cmd.read() ); + m_config_cmd_contig_fifo.update( config_cmd_fifo_get, + config_cmd_fifo_put, + r_config_cmd_contig.read() ); + m_config_cmd_cons_fifo.update( config_cmd_fifo_get, + config_cmd_fifo_put, + r_config_cmd_cons.read() ); + m_config_cmd_plen_fifo.update( config_cmd_fifo_get, + config_cmd_fifo_put, + r_config_cmd_plen.read() ); + m_config_cmd_wrap_fifo.update( config_cmd_fifo_get, + config_cmd_fifo_put, + r_config_cmd_wrap.read() ); + m_config_cmd_cfixed_fifo.update( config_cmd_fifo_get, + config_cmd_fifo_put, + r_config_cmd_cfixed.read() ); + m_config_cmd_clen_fifo.update( config_cmd_fifo_get, + config_cmd_fifo_put, + r_config_cmd_clen.read() ); + m_config_cmd_trdid_fifo.update( config_cmd_fifo_get, + config_cmd_fifo_put, + r_config_cmd_trdid.read() ); + m_config_cmd_pktid_fifo.update( config_cmd_fifo_get, + config_cmd_fifo_put, + r_config_cmd_pktid.read() ); + m_config_cmd_data_fifo.update( config_cmd_fifo_get, + config_cmd_fifo_put, + r_config_cmd_wdata.read() ); + m_config_cmd_be_fifo.update( config_cmd_fifo_get, + config_cmd_fifo_put, + r_config_cmd_be.read() ); + m_config_cmd_eop_fifo.update( config_cmd_fifo_get, + config_cmd_fifo_put, + r_config_cmd_eop.read() ); + + ////////////////////////////////////////////////////////////////////////// + // CONFIG_RSP fifo update + // writer : CONFIG_RSP FSM + ////////////////////////////////////////////////////////////////////////// + + m_config_rsp_data_fifo.update( config_rsp_fifo_get, + config_rsp_fifo_put, + config_rsp_fifo_rdata ); + m_config_rsp_rsrcid_fifo.update( config_rsp_fifo_get, + config_rsp_fifo_put, + config_rsp_fifo_rsrcid ); + m_config_rsp_rtrdid_fifo.update( config_rsp_fifo_get, + config_rsp_fifo_put, + config_rsp_fifo_rtrdid ); + m_config_rsp_rpktid_fifo.update( config_rsp_fifo_get, + config_rsp_fifo_put, + config_rsp_fifo_rpktid ); + m_config_rsp_reop_fifo.update( config_rsp_fifo_get, + config_rsp_fifo_put, + config_rsp_fifo_reop ); + m_config_rsp_rerror_fifo.update( config_rsp_fifo_get, + config_rsp_fifo_put, + config_rsp_fifo_rerror ); + + //////////////////////////////////////////////////////////////// + // MISS_WTI_CMD fifo update + // One writer : MISS_WTI switch + //////////////////////////////////////////////////////////////// + + m_miss_wti_cmd_addr_fifo.update( miss_wti_cmd_fifo_get, + miss_wti_cmd_fifo_put, + miss_wti_cmd_fifo_address ); + m_miss_wti_cmd_cmd_fifo.update( miss_wti_cmd_fifo_get, + miss_wti_cmd_fifo_put, + miss_wti_cmd_fifo_cmd ); + m_miss_wti_cmd_contig_fifo.update( config_cmd_fifo_get, + miss_wti_cmd_fifo_put, + true ); + m_miss_wti_cmd_cons_fifo.update( miss_wti_cmd_fifo_get, + miss_wti_cmd_fifo_put, + false ); + m_miss_wti_cmd_plen_fifo.update( miss_wti_cmd_fifo_get, + miss_wti_cmd_fifo_put, + 4 ); + m_miss_wti_cmd_wrap_fifo.update( miss_wti_cmd_fifo_get, + miss_wti_cmd_fifo_put, + false ); + m_miss_wti_cmd_cfixed_fifo.update( config_cmd_fifo_get, + miss_wti_cmd_fifo_put, + false ); + m_miss_wti_cmd_clen_fifo.update( miss_wti_cmd_fifo_get, + miss_wti_cmd_fifo_put, + 0 ); + m_miss_wti_cmd_srcid_fifo.update( miss_wti_cmd_fifo_get, + miss_wti_cmd_fifo_put, + miss_wti_cmd_fifo_srcid ); + m_miss_wti_cmd_trdid_fifo.update( miss_wti_cmd_fifo_get, + miss_wti_cmd_fifo_put, + miss_wti_cmd_fifo_trdid ); + m_miss_wti_cmd_pktid_fifo.update( miss_wti_cmd_fifo_get, + miss_wti_cmd_fifo_put, + miss_wti_cmd_fifo_pktid ); + m_miss_wti_cmd_data_fifo.update( miss_wti_cmd_fifo_get, + miss_wti_cmd_fifo_put, + miss_wti_cmd_fifo_wdata ); + m_miss_wti_cmd_be_fifo.update( miss_wti_cmd_fifo_get, + miss_wti_cmd_fifo_put, + 0xF ); + m_miss_wti_cmd_eop_fifo.update( miss_wti_cmd_fifo_get, + miss_wti_cmd_fifo_put, + true ); + +} // end transition() + +////////////////////////////////////////////////////////////////////////// +tmpl(void)::genMoore() +////////////////////////////////////////////////////////////////////////// +{ + ///////////////// p_vci_ini_ram ///////////////////////////// + + // VCI initiator command on RAM network + // directly the content of the dma_cmd FIFO + p_vci_ini_ram.cmdval = m_dma_cmd_addr_fifo.rok(); + p_vci_ini_ram.address = m_dma_cmd_addr_fifo.read(); + p_vci_ini_ram.be = m_dma_cmd_be_fifo.read(); + p_vci_ini_ram.cmd = m_dma_cmd_cmd_fifo.read(); + p_vci_ini_ram.contig = m_dma_cmd_contig_fifo.read(); + p_vci_ini_ram.wdata = m_dma_cmd_data_fifo.read(); + p_vci_ini_ram.eop = m_dma_cmd_eop_fifo.read(); + p_vci_ini_ram.cons = m_dma_cmd_cons_fifo.read(); + p_vci_ini_ram.plen = m_dma_cmd_plen_fifo.read(); + p_vci_ini_ram.wrap = m_dma_cmd_wrap_fifo.read(); + p_vci_ini_ram.cfixed = m_dma_cmd_cfixed_fifo.read(); + p_vci_ini_ram.clen = m_dma_cmd_clen_fifo.read(); + p_vci_ini_ram.trdid = m_dma_cmd_trdid_fifo.read(); + p_vci_ini_ram.pktid = m_dma_cmd_pktid_fifo.read(); + p_vci_ini_ram.srcid = m_dma_cmd_srcid_fifo.read(); + + // VCI initiator response on the RAM Network + // depends on the DMA_RSP FSM state + p_vci_ini_ram.rspack = m_dma_rsp_data_fifo.wok() and + (r_dma_rsp_fsm.read() == DMA_RSP_PUT_DMA); + + ///////////////// p_vci_tgt_iox ///////////////////////////// + + // VCI target response on IOX network is + // directly the content of the DMA_RSP FIFO + p_vci_tgt_iox.rspval = m_dma_rsp_data_fifo.rok(); + p_vci_tgt_iox.rsrcid = m_dma_rsp_rsrcid_fifo.read(); + p_vci_tgt_iox.rtrdid = m_dma_rsp_rtrdid_fifo.read(); + p_vci_tgt_iox.rpktid = m_dma_rsp_rpktid_fifo.read(); + p_vci_tgt_iox.rdata = m_dma_rsp_data_fifo.read(); + p_vci_tgt_iox.rerror = m_dma_rsp_rerror_fifo.read(); + p_vci_tgt_iox.reop = m_dma_rsp_reop_fifo.read(); + + // VCI target command ack on IOX network + // depends on the DMA_CMD FSM state + switch ( r_dma_cmd_fsm.read() ) + { + case DMA_CMD_IDLE: + p_vci_tgt_iox.cmdack = false; + break; + case DMA_CMD_DMA_REQ: + p_vci_tgt_iox.cmdack = m_dma_cmd_addr_fifo.wok(); + break; + case DMA_CMD_WTI_IOX_REQ: + p_vci_tgt_iox.cmdack = not r_dma_cmd_to_miss_wti_cmd_req.read(); + break; + case DMA_CMD_ERR_WTI_REQ: + p_vci_tgt_iox.cmdack = false; + break; + case DMA_CMD_ERR_WAIT_EOP: + p_vci_tgt_iox.cmdack = true; + break; + case DMA_CMD_ERR_RSP_REQ: + p_vci_tgt_iox.cmdack = false; + break; + case DMA_CMD_TLB_MISS_WAIT: + p_vci_tgt_iox.cmdack = false; + break; + } + + ////////////////// p_vci_ini_iox ///////////////////////////// + + // VCI initiator command on IOX network is + // directly the content of the CONFIG_CMD FIFO + p_vci_ini_iox.cmdval = m_config_cmd_addr_fifo.rok(); + p_vci_ini_iox.address = m_config_cmd_addr_fifo.read(); + p_vci_ini_iox.be = m_config_cmd_be_fifo.read(); + p_vci_ini_iox.cmd = m_config_cmd_cmd_fifo.read(); + p_vci_ini_iox.contig = m_config_cmd_contig_fifo.read(); + p_vci_ini_iox.wdata = m_config_cmd_data_fifo.read(); + p_vci_ini_iox.eop = m_config_cmd_eop_fifo.read(); + p_vci_ini_iox.cons = m_config_cmd_cons_fifo.read(); + p_vci_ini_iox.plen = m_config_cmd_plen_fifo.read(); + p_vci_ini_iox.wrap = m_config_cmd_wrap_fifo.read(); + p_vci_ini_iox.cfixed = m_config_cmd_cfixed_fifo.read(); + p_vci_ini_iox.clen = m_config_cmd_clen_fifo.read(); + p_vci_ini_iox.trdid = m_config_cmd_trdid_fifo.read(); + p_vci_ini_iox.pktid = m_config_cmd_pktid_fifo.read(); + p_vci_ini_iox.srcid = m_iox_srcid; + + // VCI initiator response on IOX Network + // it depends on the CONFIG_RSP FSM state + p_vci_ini_iox.rspack = m_config_rsp_data_fifo.wok() and + ( (r_config_rsp_fsm.read() == CONFIG_RSP_PUT_UNC) or + (r_config_rsp_fsm.read() == CONFIG_RSP_PUT_HI) ); + + ///////////////// p_vci_tgt_int //////////////////////////////// + + // VCI target response on INT network + // directly the content of the CONFIG_RSP FIFO + p_vci_tgt_int.rspval = m_config_rsp_data_fifo.rok(); + p_vci_tgt_int.rsrcid = m_config_rsp_rsrcid_fifo.read(); + p_vci_tgt_int.rtrdid = m_config_rsp_rtrdid_fifo.read(); + p_vci_tgt_int.rpktid = m_config_rsp_rpktid_fifo.read(); + p_vci_tgt_int.rdata = m_config_rsp_data_fifo.read(); + p_vci_tgt_int.rerror = m_config_rsp_rerror_fifo.read(); + p_vci_tgt_int.reop = m_config_rsp_reop_fifo.read(); + + // VCI target command ack on INT network + // it depends on the CONFIG_CMD FSM state + switch ( r_config_cmd_fsm.read() ) + { + case CONFIG_CMD_IDLE: + p_vci_tgt_int.cmdack = true; + break; + case CONFIG_CMD_WAIT: + p_vci_tgt_int.cmdack = false; + break; + case CONFIG_CMD_HI: + p_vci_tgt_int.cmdack = true; + break; + case CONFIG_CMD_LO: + p_vci_tgt_int.cmdack = true; + break; + case CONFIG_CMD_PUT: + p_vci_tgt_int.cmdack = false; + break; + case CONFIG_CMD_RSP: + p_vci_tgt_int.cmdack = false; + break; + } + + ///////////////// p_vci_ini_int //////////////////////////////// + + // VCI initiator command on INT network + // directly the content of the MISS_WTI_CMD FIFO + p_vci_ini_int.cmdval = m_miss_wti_cmd_addr_fifo.rok(); + p_vci_ini_int.address = m_miss_wti_cmd_addr_fifo.read(); + p_vci_ini_int.be = m_miss_wti_cmd_be_fifo.read(); + p_vci_ini_int.cmd = m_miss_wti_cmd_cmd_fifo.read(); + p_vci_ini_int.contig = m_miss_wti_cmd_contig_fifo.read(); + p_vci_ini_int.wdata = m_miss_wti_cmd_data_fifo.read(); + p_vci_ini_int.eop = m_miss_wti_cmd_eop_fifo.read(); + p_vci_ini_int.cons = m_miss_wti_cmd_cons_fifo.read(); + p_vci_ini_int.plen = m_miss_wti_cmd_plen_fifo.read(); + p_vci_ini_int.wrap = m_miss_wti_cmd_wrap_fifo.read(); + p_vci_ini_int.cfixed = m_miss_wti_cmd_cfixed_fifo.read(); + p_vci_ini_int.clen = m_miss_wti_cmd_clen_fifo.read(); + p_vci_ini_int.trdid = m_miss_wti_cmd_trdid_fifo.read(); + p_vci_ini_int.pktid = m_miss_wti_cmd_pktid_fifo.read(); + p_vci_ini_int.srcid = m_miss_wti_cmd_srcid_fifo.read(); + + // VCI initiator response on INT network + // It depends on the MISS_WTI_RSP FSM state + + if ( r_miss_wti_rsp_fsm.read() == MISS_WTI_RSP_IDLE ) + { + p_vci_ini_int.rspack = false; + } + else if ( r_miss_wti_rsp_fsm.read() == MISS_WTI_RSP_WTI_IOX ) + { + p_vci_ini_int.rspack = not r_miss_wti_rsp_to_dma_rsp_req.read(); + } + else // MISS_WTI_RSP_MISS or MISS_WTI_RESP_WTI_MMU + { + p_vci_ini_int.rspack = true; + } + +} // end genMoore + +}} + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 Index: /branches/fault_tolerance/modules/vci_io_bridge/include/soclib/io_bridge.h =================================================================== --- /branches/fault_tolerance/modules/vci_io_bridge/include/soclib/io_bridge.h (revision 724) +++ /branches/fault_tolerance/modules/vci_io_bridge/include/soclib/io_bridge.h (revision 724) @@ -0,0 +1,71 @@ +/* + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, Asim + * alain greiner + * + * Maintainers: alain + */ +#ifndef IO_BRIDGE_REGS_H +#define IO_BRIDGE_REGS_H + +// IOB Configuration registers +// Minimal required segment size = 64 bytes (16 words) +enum +{ + IOB_IOMMU_PTPR = 0, // R/W : Page Table Pointer Register + IOB_IOMMU_ACTIVE = 1, // R/W : IOMMU activated if not 0 + IOB_IOMMU_BVAR = 2, // R : Bad Virtual Address + IOB_IOMMU_ETR = 3, // R : Error type + IOB_IOMMU_BAD_ID = 4, // R : Faulty peripheral Index (SRCID) + IOB_INVAL_PTE = 5, // W : Invalidate PTE (using virtual address) + IOB_WTI_ENABLE = 6, // R/W : Enable WTI (both IOB and external IRQs) + IOB_WTI_ADDR_LO = 7, // R/W : IOB WTI address (32 LSB bits) + IOB_WTI_ADDR_HI = 8, // R/W : IOB WTI address (32 MSB bits) + /**/ + IOB_SPAN = 16, +}; + + +// IOMMU Error Type +enum mmu_error_type_e +{ + MMU_NONE = 0x0000, // None + MMU_WRITE_ACCES_VIOLATION = 0x0008, // Write access to non writable page + MMU_WRITE_PT1_ILLEGAL_ACCESS = 0x0040, // Write Bus Error accessing Table 1 + MMU_READ_PT1_UNMAPPED = 0x1001, // Read Page fault on Page Table 1 + MMU_READ_PT2_UNMAPPED = 0x1002, // Read Page fault on Page Table 2 + MMU_READ_PT1_ILLEGAL_ACCESS = 0x1040, // Read Bus Error in Table1 access + MMU_READ_PT2_ILLEGAL_ACCESS = 0x1080, // Read Bus Error in Table2 access + MMU_READ_DATA_ILLEGAL_ACCESS = 0x1100, // Read Bus Error in cache access +}; + +#endif /* IO_BRIDGE_REGS_H */ + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: /branches/fault_tolerance/modules/vci_iox_network/caba/metadata/vci_iox_network.sd =================================================================== --- /branches/fault_tolerance/modules/vci_iox_network/caba/metadata/vci_iox_network.sd (revision 724) +++ /branches/fault_tolerance/modules/vci_iox_network/caba/metadata/vci_iox_network.sd (revision 724) @@ -0,0 +1,44 @@ + +# -*- python -*- + +Module('caba:vci_iox_network', + classname = 'soclib::caba::VciIoxNetwork', + + tmpl_parameters = [ + parameter.Module('vci_param', default = 'caba:vci_param'), + ], + + header_files = [ + '../source/include/vci_iox_network.h', + ], + + implementation_files = [ + '../source/src/vci_iox_network.cpp', + ], + + ports = [ + Port('caba:vci_initiator', 'p_to_local_tgt', parameter.Reference('nb_local_tgt')), + Port('caba:vci_target', 'p_to_local_ini', parameter.Reference('nb_local_ini')), + Port('caba:vci_initiator', 'p_to_global_tgt', parameter.Reference('nb_global_tgt')), + Port('caba:vci_target', 'p_to_global_ini', parameter.Reference('nb_global_ini')), + Port('caba:bit_in', 'p_resetn', auto = 'resetn'), + Port('caba:clock_in', 'p_clk', auto = 'clock'), + ], + + instance_parameters = [ + parameter.Module('mt', typename = 'common:mapping_table'), + parameter.Int('cluster_id'), + parameter.Int('nb_local_tgt'), + parameter.Int('nb_local_ini'), + parameter.Int('nb_global_tgt'), + parameter.Int('nb_global_ini'), + ], + + uses = [ + Uses('caba:base_module'), + Uses('common:mapping_table'), + Uses('common:address_decoding_table', input_t = 'uint64_t', output_t = 'size_t'), + Uses('common:address_decoding_table', input_t = 'uint32_t', output_t = 'size_t'), + Uses('caba:vci_buffers'), + ], +) Index: /branches/fault_tolerance/modules/vci_iox_network/caba/source/include/vci_iox_network.h =================================================================== --- /branches/fault_tolerance/modules/vci_iox_network/caba/source/include/vci_iox_network.h (revision 724) +++ /branches/fault_tolerance/modules/vci_iox_network/caba/source/include/vci_iox_network.h (revision 724) @@ -0,0 +1,129 @@ +/* -*- c++ -*- + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, Asim + * Alain Greiner , 2013 + * + * Maintainers: alain + */ + +//////////////////////////////////////////////////////////////////////////////// +// This component emulates an external IO bus such as PCIe or Hypertransport, +// but respect the VCI protocol. It can be attached to one OR SEVERAL clusters, +// using a vci_io_bridge component. +// It is considered as a local interconnect, for the ADDRESS or SRCID +// decoding tables: +// - the CMD routing_table decodes the local field of the VCI ADDRESS +// to return the local target port +// - The RSP routing_table decodes the local field of the VCI SRCID +// to return the initator port +// It is implemented as two independant crossbars, for VCI commands and +// VCI responses respectively. +// - The CMD crossbar has nb_ini input ports, and nb_tgt output ports, +// including the ports to the vci_io_bridge component(s). +// - The RSP crossbar has nb_tgt input ports, and nb_ini output ports. +// including the ports to the vci_io_bridge component(s). +// For both crossbars, output ports allocation policy is round robin. +//////////////////////////////////////////////////////////////////////////////// + +#ifndef VCI_IOX_NETWORK_H +#define VCI_IOX_NETWORK_H + +#include +#include "caba_base_module.h" +#include "vci_initiator.h" +#include "vci_target.h" +#include "vci_buffers.h" +#include "mapping_table.h" +#include "address_decoding_table.h" + +namespace soclib { namespace caba { + +using namespace sc_core; +using namespace soclib::common; + +template class IoXbar; + +/////////////////////////////////////// +template +class VciIoxNetwork +/////////////////////////////////////// + : public BaseModule +{ + +public: + + sc_in p_clk; + sc_in p_resetn; + VciInitiator* p_to_tgt; + VciTarget* p_to_ini; + +private: + + typedef IoXbar > cmd_xbar_t; + typedef IoXbar > rsp_xbar_t; + + size_t m_nb_tgt; + size_t m_nb_ini; + + VciInitiator** m_ports_to_target; + VciTarget** m_ports_to_initiator; + + rsp_xbar_t* m_rsp_xbar; // RSP crossbar + cmd_xbar_t* m_cmd_xbar; // CMD crossbar + + AddressDecodingTable m_cmd_rt; // routing table for CMD + AddressDecodingTable m_rsp_rt; // routing table for RSP + + void transition(); + + void genMealy_cmd_val(); + void genMealy_cmd_ack(); + void genMealy_rsp_val(); + void genMealy_rsp_ack(); + +protected: + SC_HAS_PROCESS(VciIoxNetwork); + +public: + void print_trace(); + + VciIoxNetwork( sc_module_name name, + const soclib::common::MappingTable &mt, + size_t nb_tgt, + size_t nb_ini ); + + ~VciIoxNetwork(); +}; + +}} + +#endif + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 Index: /branches/fault_tolerance/modules/vci_iox_network/caba/source/src/vci_iox_network.cpp =================================================================== --- /branches/fault_tolerance/modules/vci_iox_network/caba/source/src/vci_iox_network.cpp (revision 724) +++ /branches/fault_tolerance/modules/vci_iox_network/caba/source/src/vci_iox_network.cpp (revision 724) @@ -0,0 +1,360 @@ +/* + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, Asim + * Alain Greiner 2013 + * + * Maintainers: alain + */ + +//////////////////////////////////////////////////////////////////////////////// +// This component emulates an external IO bus such as PCIe or Hypertransport, +// but respect the VCI protocol. It can be attached to one OR SEVERAL clusters, +// using a vci_io_bridge component. +// It is considered as a local interconnect, for the ADDRESS or SRCID +// decoding tables: +// - the CMD routing_table decodes the local field of the VCI ADDRESS +// to return the local target port +// - The RSP routing_table decodes the local field of the VCI SRCID +// to return the initator port +// It is implemented as two independant crossbars, for VCI commands and +// VCI responses respectively. +// - The CMD crossbar has nb_ini input ports, and nb_tgt output ports, +// including the ports to the vci_io_bridge component(s). +// - The RSP crossbar has nb_tgt input ports, and nb_ini output ports. +// including the ports to the vci_io_bridge component(s). +// For both crossbars, output ports allocation policy is round robin. +//////////////////////////////////////////////////////////////////////////////// + +#include +#include +#include "vci_buffers.h" +#include "../include/vci_iox_network.h" +#include "alloc_elems.h" + +namespace soclib { namespace caba { + +using soclib::common::alloc_elems; +using soclib::common::dealloc_elems; + +using namespace sc_core; + +/////////////////////////////////////////////////////////////////////////////////// +// The IoXbar class is instanciated twice, to implement the CMD & RSP XBARs +/////////////////////////////////////////////////////////////////////////////////// +template class IoXbar +{ + // pkt_t type must be VciCmdBuffer or VciRspBuffer + // the two following types can be found in these two classes + + typedef typename pkt_t::input_port_t input_port_t; + typedef typename pkt_t::output_port_t output_port_t; + + const bool m_is_cmd; // CMD XBAR if true + const size_t m_inputs; // number of inputs + const size_t m_outputs; // number of outputs + void* m_rt; // pointer on routing table (CMD or RSP) + + sc_signal* r_out_allocated; // for each output: allocation state + sc_signal* r_out_origin; // for each output: input port index + sc_signal* r_in_allocated; // for each input: allocation state + sc_signal* r_in_dest; // for each input: output port index + +public: + /////////////////////// + IoXbar( bool is_cmd, + size_t nb_inputs, + size_t nb_outputs, + void* rt ) + : m_is_cmd( is_cmd ), + m_inputs( nb_inputs ), + m_outputs( nb_outputs ), + m_rt ( rt ) + { + r_out_allocated = new sc_signal[nb_outputs]; + r_out_origin = new sc_signal[nb_outputs]; + r_in_allocated = new sc_signal[nb_inputs]; + r_in_dest = new sc_signal[nb_inputs]; + } + + //////////// + void reset() + { + for (size_t i=0 ; i tgt " << out << " | "; + } + } + } + else + { + std::cout << "IOX_RSP_XBAR : " << std::dec; + for( size_t out=0 ; out ini " << out << " | "; + } + } + } + std::cout << std::endl; + } + + /////////////////////////////////////////// + void transition( input_port_t **input_port, + output_port_t **output_port ) + { + // loop on the output ports + for ( size_t out = 0; out < m_outputs; out++) + { + if ( r_out_allocated[out].read() ) // possible desallocation + { + if ( output_port[out]->toPeerEnd() ) + { + size_t in = r_out_origin[out].read(); + r_out_allocated[out] = false; + r_in_allocated[in] = false; + } + } + else // possible allocation + { + // loop on the intput ports + bool found = false; + for(size_t x = 0 ; (x < m_inputs) and not found ; x++) + { + size_t in = (x + r_out_origin[out] + 1) % m_inputs; + if ( input_port[in]->getVal() ) + { + size_t req; // requested output port index + if ( m_is_cmd ) + { + AddressDecodingTable* rt = + (AddressDecodingTable*)m_rt; + req = rt->get_value((uint64_t)(input_port[in]->address.read())); + } + else + { + AddressDecodingTable* rt = + (AddressDecodingTable*)m_rt; + req = rt->get_value((uint32_t)(input_port[in]->rsrcid.read())); + } + // allocate the output port if requested + if ( out == req ) + { + r_out_allocated[out] = true; + r_in_allocated[in] = true; + r_out_origin[out] = in; + r_in_dest[in] = out; + found = true; + } + } + } // end loop inputs + } + } // end loop outputs + } // end transition + + ////////////////////////////////////////////// + void genMealy_ack( input_port_t **input_port, + output_port_t **output_port ) + { + for ( size_t in = 0 ; in < m_inputs ; in++ ) + { + size_t out = r_in_dest[in].read(); + bool ack = r_in_allocated[in].read() and output_port[out]->getAck(); + input_port[in]->setAck(ack); + } + } + + /////////////////////////////////////////////////////////////////////// + void genMealy_val( input_port_t **input_port, + output_port_t **output_port ) + { + for( size_t out = 0 ; out < m_outputs ; out++) + { + if (r_out_allocated[out]) + { + size_t in = r_out_origin[out]; + pkt_t tmp; + tmp.readFrom(*input_port[in]); + tmp.writeTo(*output_port[out]); + } + else + { + output_port[out]->setVal(false); + } + } + } + +}; // end class IoXbar + + +/////////////////////////////////////////////////////////////////////////////////// +#define tmpl(x) template x VciIoxNetwork +/////////////////////////////////////////////////////////////////////////////////// + +///////////////////////// +tmpl(void)::print_trace() +{ + m_cmd_xbar->print_trace(); + m_rsp_xbar->print_trace(); +} + +//////////////////////// +tmpl(void)::transition() +{ + if ( ! p_resetn.read() ) + { + m_cmd_xbar->reset(); + m_rsp_xbar->reset(); + return; + } + + m_cmd_xbar->transition( m_ports_to_initiator, m_ports_to_target ); + m_rsp_xbar->transition( m_ports_to_target, m_ports_to_initiator ); +} + +////////////////////////////// +tmpl(void)::genMealy_cmd_val() +{ + m_cmd_xbar->genMealy_val( m_ports_to_initiator, m_ports_to_target ); +} + +////////////////////////////// +tmpl(void)::genMealy_cmd_ack() +{ + m_cmd_xbar->genMealy_ack( m_ports_to_initiator, m_ports_to_target ); +} + +////////////////////////////// +tmpl(void)::genMealy_rsp_val() +{ + m_rsp_xbar->genMealy_val( m_ports_to_target, m_ports_to_initiator ); +} + +////////////////////////////// +tmpl(void)::genMealy_rsp_ack() +{ + m_rsp_xbar->genMealy_ack( m_ports_to_target, m_ports_to_initiator ); +} + +/////////////////////////////////////////////////////////////////////////// +tmpl(/**/)::VciIoxNetwork( sc_core::sc_module_name name, + const soclib::common::MappingTable &mt, + size_t nb_tgt, + size_t nb_ini ) + : BaseModule(name), + p_clk("clk"), + p_resetn("resetn"), + p_to_tgt(soclib::common::alloc_elems >( + "p_to_tgt", nb_tgt)), + p_to_ini(soclib::common::alloc_elems >( + "p_to_ini", nb_ini)), + + m_nb_tgt( nb_tgt ), + m_nb_ini( nb_ini ), + + m_cmd_rt( mt.getLocalIndexFromAddress(0) ), + m_rsp_rt( mt.getLocalIndexFromSrcid(0) ) +{ + std::cout << " Building VciIoxNetwork : " << name << std::endl; + + SC_METHOD(transition); + dont_initialize(); + sensitive << p_clk.pos(); + + SC_METHOD(genMealy_cmd_val); // controls to targets CMDVAL + dont_initialize(); + sensitive << p_clk.neg(); + for ( size_t i=0; i*[nb_ini]; + for (size_t g = 0 ; g < nb_ini ; g++) m_ports_to_initiator[g] = &p_to_ini[g]; + + m_ports_to_target = new VciInitiator*[nb_tgt]; + for (size_t g = 0 ; g < nb_tgt ; g++) m_ports_to_target[g] = &p_to_tgt[g]; +} + +//////////////////////////// +tmpl(/**/)::~VciIoxNetwork() +{ + soclib::common::dealloc_elems(p_to_ini, m_nb_ini); + soclib::common::dealloc_elems(p_to_tgt, m_nb_tgt); +} + +}} + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 Index: /branches/fault_tolerance/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd =================================================================== --- /branches/fault_tolerance/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd (revision 724) +++ /branches/fault_tolerance/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd (revision 724) @@ -0,0 +1,77 @@ + +# -*- python -*- + +__id__ = "$Id: vci_mem_cache.sd 295 2013-02-14 15:05:05Z cfuguet $" +__version__ = "$Revision: 295 $" + +Module('caba:vci_mem_cache', + classname = 'soclib::caba::VciMemCache', + + tmpl_parameters = [ + parameter.Module('vci_param_int', default = 'caba:vci_param', + cell_size = parameter.Reference('memc_cell_size_int') + ), + parameter.Module('vci_param_ext', default = 'caba:vci_param', + cell_size = parameter.Reference('memc_cell_size_ext') + ), + parameter.Int('dspin_in_width'), + parameter.Int('dspin_out_width'), + ], + + header_files = [ + '../source/include/vci_mem_cache.h', + '../source/include/xram_transaction.h', + '../source/include/mem_cache_directory.h', + '../source/include/update_tab.h' + ], + + interface_files = [ + '../../include/soclib/mem_cache.h', + ], + + implementation_files = [ + '../source/src/vci_mem_cache.cpp' + ], + + uses = [ + Uses('caba:base_module'), + Uses('common:loader'), + Uses('common:mapping_table'), + Uses('caba:generic_fifo'), + Uses('caba:generic_llsc_global_table'), + Uses('caba:dspin_dhccp_param') + ], + + ports = [ + Port('caba:clock_in' , 'p_clk' , auto = 'clock' ), + Port('caba:bit_in' , 'p_resetn' , auto = 'resetn'), + Port('caba:vci_target' , 'p_vci_tgt'), + Port('caba:vci_initiator', 'p_vci_ixr'), + Port('caba:dspin_input', + 'p_dspin_p2m', + dspin_data_size = parameter.Reference('dspin_in_width') + ), + Port('caba:dspin_output', + 'p_dspin_m2p', + dspin_data_size = parameter.Reference('dspin_out_width') + ), + Port('caba:dspin_output', + 'p_dspin_clack', + dspin_data_size = parameter.Reference('dspin_out_width') + ), + ], + + instance_parameters = [ + parameter.Module('mtp', 'common:mapping_table'), + parameter.Module('mtc', 'common:mapping_table'), + parameter.Module('mtx', 'common:mapping_table'), + parameter.IntTab('vci_ixr_index'), + parameter.IntTab('vci_ini_index'), + parameter.IntTab('vci_tgt_index'), + parameter.IntTab('vci_tgt_index_cleanup'), + parameter.Int ('nways'), + parameter.Int ('nsets'), + parameter.Int ('nwords'), + parameter.Int ('heap_size'), + ], +) Index: /branches/fault_tolerance/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h =================================================================== --- /branches/fault_tolerance/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h (revision 724) +++ /branches/fault_tolerance/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h (revision 724) @@ -0,0 +1,737 @@ +#ifndef SOCLIB_CABA_MEM_CACHE_DIRECTORY_H +#define SOCLIB_CABA_MEM_CACHE_DIRECTORY_H + +#include +#include +#include +#include "arithmetics.h" + +//#define RANDOM_EVICTION + +namespace soclib { namespace caba { + + using namespace sc_core; + + //////////////////////////////////////////////////////////////////////// + // A LRU entry + //////////////////////////////////////////////////////////////////////// + class LruEntry { + + public: + + bool recent; + + void init() + { + recent=false; + } + + }; // end class LruEntry + + //////////////////////////////////////////////////////////////////////// + // An Owner + //////////////////////////////////////////////////////////////////////// + class Owner{ + + public: + // Fields + bool inst; // Is the owner an ICache ? + size_t srcid; // The SRCID of the owner + + //////////////////////// + // Constructors + //////////////////////// + Owner(bool i_inst, + size_t i_srcid) + { + inst = i_inst; + srcid = i_srcid; + } + + Owner(const Owner &a) + { + inst = a.inst; + srcid = a.srcid; + } + + Owner() + { + inst = false; + srcid = 0; + } + // end constructors + + }; // end class Owner + + + //////////////////////////////////////////////////////////////////////// + // A directory entry + //////////////////////////////////////////////////////////////////////// + class DirectoryEntry { + + typedef uint32_t tag_t; + + public: + + bool valid; // entry valid + bool is_cnt; // directory entry is in counter mode + bool dirty; // entry dirty + bool lock; // entry locked + tag_t tag; // tag of the entry + size_t count; // number of copies + Owner owner; // an owner of the line + size_t ptr; // pointer to the next owner + + DirectoryEntry() + { + valid = false; + is_cnt = false; + dirty = false; + lock = false; + tag = 0; + count = 0; + owner.inst = 0; + owner.srcid = 0; + ptr = 0; + } + + DirectoryEntry(const DirectoryEntry &source) + { + valid = source.valid; + is_cnt = source.is_cnt; + dirty = source.dirty; + lock = source.lock; + tag = source.tag; + count = source.count; + owner = source.owner; + ptr = source.ptr; + } + + ///////////////////////////////////////////////////////////////////// + // The init() function initializes the entry + ///////////////////////////////////////////////////////////////////// + void init() + { + valid = false; + is_cnt = false; + dirty = false; + lock = false; + count = 0; + } + + ///////////////////////////////////////////////////////////////////// + // The copy() function copies an existing source entry to a target + ///////////////////////////////////////////////////////////////////// + void copy(const DirectoryEntry &source) + { + valid = source.valid; + is_cnt = source.is_cnt; + dirty = source.dirty; + lock = source.lock; + tag = source.tag; + count = source.count; + owner = source.owner; + ptr = source.ptr; + } + + //////////////////////////////////////////////////////////////////// + // The print() function prints the entry + //////////////////////////////////////////////////////////////////// + void print() + { + std::cout << "Valid = " << valid + << " ; IS COUNT = " << is_cnt + << " ; Dirty = " << dirty + << " ; Lock = " << lock + << " ; Tag = " << std::hex << tag << std::dec + << " ; Count = " << count + << " ; Owner = " << owner.srcid + << " " << owner.inst + << " ; Pointer = " << ptr << std::endl; + } + + }; // end class DirectoryEntry + + //////////////////////////////////////////////////////////////////////// + // The directory + //////////////////////////////////////////////////////////////////////// + class CacheDirectory { + + typedef sc_dt::sc_uint<40> addr_t; + typedef uint32_t data_t; + typedef uint32_t tag_t; + + private: + + // Directory constants + size_t m_ways; + size_t m_sets; + size_t m_words; + size_t m_width; + uint32_t lfsr; + + // the directory & lru tables + DirectoryEntry **m_dir_tab; + LruEntry **m_lru_tab; + + public: + + //////////////////////// + // Constructor + //////////////////////// + CacheDirectory( size_t ways, size_t sets, size_t words, size_t address_width) + { + m_ways = ways; + m_sets = sets; + m_words = words; + m_width = address_width; + lfsr = -1; + + m_dir_tab = new DirectoryEntry*[sets]; + for ( size_t i=0; i> (L2(m_words) + 2)) & (m_sets - 1); + const tag_t tag = (tag_t)(address >> (L2(m_sets) + L2(m_words) + 2)); +#undef L2 + + bool hit = false; + for ( size_t i=0 ; i> (L2(m_words) + 2)) & (m_sets - 1); + tag_t tag = (tag_t)(address >> (L2(m_sets) + L2(m_words) + 2)); +#undef L2 + + for ( size_t way = 0 ; way < m_ways ; way++ ) + { + bool equal = ( m_dir_tab[set][way].tag == tag ); + bool valid = m_dir_tab[set][way].valid; + if ( equal and valid ) + { + *ret_set = set; + *ret_way = way; + return DirectoryEntry(m_dir_tab[set][way]); + } + } + return DirectoryEntry(); + } // end read_neutral() + + ///////////////////////////////////////////////////////////////////// + // The write function writes a new entry, + // and updates the LRU bits if necessary. + // Arguments : + // - set : the set of the entry + // - way : the way of the entry + // - entry : the entry value + ///////////////////////////////////////////////////////////////////// + void write( const size_t &set, + const size_t &way, + const DirectoryEntry &entry) + { + assert( (set> 1) ^ ((-(lfsr & 1)) & 0xd0000001); + way = lfsr % m_ways; + return DirectoryEntry(m_dir_tab[set][way]); +#endif + + // looking for a not locked and not recently used entry + for(size_t i=0; i0 && "Memory Cache, HeapDirectory constructor : invalid size"); + ptr_free = 0; + full = false; + m_heap_tab = new HeapEntry[size]; + tab_size = size; + } // end constructor + + ///////////////// + // Destructor + ///////////////// + ~HeapDirectory(){ + delete [] m_heap_tab; + } // end destructor + + ///////////////////////////////////////////////////////////////////// + // Global initialisation function + ///////////////////////////////////////////////////////////////////// + void init(){ + ptr_free=0; + full=false; + for(size_t i=0; i< tab_size-1;i++){ + m_heap_tab[i].next = i+1; + } + m_heap_tab[tab_size-1].next = tab_size-1; + return; + } + + ///////////////////////////////////////////////////////////////////// + // The print() function prints a selected directory entry + // Arguments : + // - ptr : the pointer to the entry to print + ///////////////////////////////////////////////////////////////////// + void print(const size_t &ptr){ + std::cout << "Heap, printing the entry : " << std::dec << ptr << std::endl; + m_heap_tab[ptr].print(); + } // end print() + + ///////////////////////////////////////////////////////////////////// + // The print_list() function prints a list from selected directory entry + // Arguments : + // - ptr : the pointer to the first entry to print + ///////////////////////////////////////////////////////////////////// + void print_list(const size_t &ptr){ + bool end = false; + size_t ptr_temp = ptr; + std::cout << "Heap, printing the list from : " << std::dec << ptr << std::endl; + while(!end){ + m_heap_tab[ptr_temp].print(); + if(ptr_temp == m_heap_tab[ptr_temp].next) end = true; + ptr_temp = m_heap_tab[ptr_temp].next; + } + } // end print_list() + + ///////////////////////////////////////////////////////////////////// + // The is_full() function return true if the heap is full. + ///////////////////////////////////////////////////////////////////// + bool is_full(){ + return full; + } // end is_full() + + ///////////////////////////////////////////////////////////////////// + // The next_free_ptr() function returns the pointer + // to the next free entry. + ///////////////////////////////////////////////////////////////////// + size_t next_free_ptr(){ + return ptr_free; + } // end next_free_ptr() + + ///////////////////////////////////////////////////////////////////// + // The next_free_entry() function returns + // a copy of the next free entry. + ///////////////////////////////////////////////////////////////////// + HeapEntry next_free_entry(){ + return HeapEntry(m_heap_tab[ptr_free]); + } // end next_free_entry() + + ///////////////////////////////////////////////////////////////////// + // The write_free_entry() function modify the next free entry. + // Arguments : + // - entry : the entry to write + ///////////////////////////////////////////////////////////////////// + void write_free_entry(const HeapEntry &entry){ + m_heap_tab[ptr_free].copy(entry); + } // end write_free_entry() + + ///////////////////////////////////////////////////////////////////// + // The write_free_ptr() function writes the pointer + // to the next free entry + ///////////////////////////////////////////////////////////////////// + void write_free_ptr(const size_t &ptr){ + assert( (ptr * cache_line) + { + assert((set < m_sets ) && "Cache data error: Trying to read a wrong set" ); + assert((way < m_ways ) && "Cache data error: Trying to read a wrong way" ); + + for (uint32_t word=0; word +#include +#include +#include "arithmetics.h" + +//////////////////////////////////////////////////////////////////////// +// An update tab entry +//////////////////////////////////////////////////////////////////////// +class UpdateTabEntry { + + typedef uint32_t size_t; + typedef sc_dt::sc_uint<40> addr_t; + + public: + + bool valid; // It is a valid pending transaction + bool update; // It is an update transaction + bool brdcast; // It is a broadcast invalidate + bool rsp; // Response to the initiator required + bool ack; // Acknowledge to the CONFIG FSM required + size_t srcid; // The srcid of the initiator which wrote the data + size_t trdid; // The trdid of the initiator which wrote the data + size_t pktid; // The pktid of the initiator which wrote the data + addr_t nline; // The identifier of the cache line + size_t count; // The number of acknowledge responses to receive + + UpdateTabEntry() + { + valid = false; + update = false; + brdcast = false; + rsp = false; + ack = false; + srcid = 0; + trdid = 0; + pktid = 0; + nline = 0; + count = 0; + } + + UpdateTabEntry(bool i_valid, + bool i_update, + bool i_brdcast, + bool i_rsp, + bool i_ack, + size_t i_srcid, + size_t i_trdid, + size_t i_pktid, + addr_t i_nline, + size_t i_count) + { + valid = i_valid; + update = i_update; + brdcast = i_brdcast; + rsp = i_rsp; + ack = i_ack; + srcid = i_srcid; + trdid = i_trdid; + pktid = i_pktid; + nline = i_nline; + count = i_count; + } + + UpdateTabEntry(const UpdateTabEntry &source) + { + valid = source.valid; + update = source.update; + brdcast = source.brdcast; + rsp = source.rsp; + ack = source.ack; + srcid = source.srcid; + trdid = source.trdid; + pktid = source.pktid; + nline = source.nline; + count = source.count; + } + + //////////////////////////////////////////////////// + // The init() function initializes the entry + /////////////////////////////////////////////////// + void init() + { + valid = false; + update = false; + brdcast= false; + rsp = false; + ack = false; + srcid = 0; + trdid = 0; + pktid = 0; + nline = 0; + count = 0; + } + + //////////////////////////////////////////////////////////////////// + // The copy() function copies an existing entry + // Its arguments are : + // - source : the update tab entry to copy + //////////////////////////////////////////////////////////////////// + void copy(const UpdateTabEntry &source) + { + valid = source.valid; + update = source.update; + brdcast= source.brdcast; + rsp = source.rsp; + ack = source.ack ; + srcid = source.srcid; + trdid = source.trdid; + pktid = source.pktid; + nline = source.nline; + count = source.count; + } + + //////////////////////////////////////////////////////////////////// + // The print() function prints the entry + //////////////////////////////////////////////////////////////////// + void print() + { + std::cout << " val = " << std::dec << valid + << " / updt = " << update + << " / bc = " << brdcast + << " / rsp = " << rsp + << " / ack = " << ack + << " / count = " << count + << " / srcid = " << std::hex << srcid + << " / trdid = " << trdid + << " / pktid = " << pktid + << " / nline = " << nline << std::endl; + } +}; + +//////////////////////////////////////////////////////////////////////// +// The update tab +//////////////////////////////////////////////////////////////////////// +class UpdateTab{ + + typedef uint64_t addr_t; + + private: + size_t size_tab; + std::vector tab; + + public: + + UpdateTab() + : tab(0) + { + size_tab=0; + } + + UpdateTab(size_t size_tab_i) + : tab(size_tab_i) + { + size_tab=size_tab_i; + } + + //////////////////////////////////////////////////////////////////// + // The size() function returns the size of the tab + //////////////////////////////////////////////////////////////////// + const size_t size() + { + return size_tab; + } + + //////////////////////////////////////////////////////////////////// + // The print() function diplays the tab content + //////////////////////////////////////////////////////////////////// + void print() + { + std::cout << "UPDATE TABLE Content" << std::endl; + for(size_t i=0; i +#include +#include +#include +#include "arithmetics.h" +#include "alloc_elems.h" +#include "caba_base_module.h" +#include "vci_target.h" +#include "vci_initiator.h" +#include "generic_fifo.h" +#include "mapping_table.h" +#include "int_tab.h" +#include "generic_llsc_global_table.h" +#include "mem_cache_directory.h" +#include "xram_transaction.h" +#include "update_tab.h" +#include "dspin_interface.h" +#include "dspin_dhccp_param.h" + +#define TRT_ENTRIES 4 // Number of entries in TRT +#define UPT_ENTRIES 4 // Number of entries in UPT +#define IVT_ENTRIES 4 // Number of entries in IVT +#define HEAP_ENTRIES 1024 // Number of entries in HEAP + +namespace soclib { namespace caba { + + using namespace sc_core; + + template + class VciMemCache + : public soclib::caba::BaseModule + { + typedef typename vci_param_int::fast_addr_t addr_t; + typedef typename sc_dt::sc_uint<64> wide_data_t; + typedef uint32_t data_t; + typedef uint32_t tag_t; + typedef uint32_t be_t; + typedef uint32_t copy_t; + + /* States of the TGT_CMD fsm */ + enum tgt_cmd_fsm_state_e + { + TGT_CMD_IDLE, + TGT_CMD_READ, + TGT_CMD_WRITE, + TGT_CMD_CAS, + TGT_CMD_CONFIG, + TGT_CMD_ERROR + }; + + /* States of the TGT_RSP fsm */ + enum tgt_rsp_fsm_state_e + { + TGT_RSP_READ_IDLE, + TGT_RSP_WRITE_IDLE, + TGT_RSP_CAS_IDLE, + TGT_RSP_XRAM_IDLE, + TGT_RSP_MULTI_ACK_IDLE, + TGT_RSP_CLEANUP_IDLE, + TGT_RSP_TGT_CMD_IDLE, + TGT_RSP_CONFIG_IDLE, + TGT_RSP_READ, + TGT_RSP_WRITE, + TGT_RSP_CAS, + TGT_RSP_XRAM, + TGT_RSP_MULTI_ACK, + TGT_RSP_CLEANUP, + TGT_RSP_TGT_CMD, + TGT_RSP_CONFIG + }; + + /* States of the DSPIN_TGT fsm */ + enum cc_receive_fsm_state_e + { + CC_RECEIVE_IDLE, + CC_RECEIVE_CLEANUP, + CC_RECEIVE_CLEANUP_EOP, + CC_RECEIVE_MULTI_ACK + }; + + /* States of the CC_SEND fsm */ + enum cc_send_fsm_state_e + { + CC_SEND_XRAM_RSP_IDLE, + CC_SEND_WRITE_IDLE, + CC_SEND_CAS_IDLE, + CC_SEND_CONFIG_IDLE, + CC_SEND_XRAM_RSP_BRDCAST_HEADER, + CC_SEND_XRAM_RSP_BRDCAST_NLINE, + CC_SEND_XRAM_RSP_INVAL_HEADER, + CC_SEND_XRAM_RSP_INVAL_NLINE, + CC_SEND_WRITE_BRDCAST_HEADER, + CC_SEND_WRITE_BRDCAST_NLINE, + CC_SEND_WRITE_UPDT_HEADER, + CC_SEND_WRITE_UPDT_NLINE, + CC_SEND_WRITE_UPDT_DATA, + CC_SEND_CAS_BRDCAST_HEADER, + CC_SEND_CAS_BRDCAST_NLINE, + CC_SEND_CAS_UPDT_HEADER, + CC_SEND_CAS_UPDT_NLINE, + CC_SEND_CAS_UPDT_DATA, + CC_SEND_CAS_UPDT_DATA_HIGH, + CC_SEND_CONFIG_INVAL_HEADER, + CC_SEND_CONFIG_INVAL_NLINE, + CC_SEND_CONFIG_BRDCAST_HEADER, + CC_SEND_CONFIG_BRDCAST_NLINE + }; + + /* States of the MULTI_ACK fsm */ + enum multi_ack_fsm_state_e + { + MULTI_ACK_IDLE, + MULTI_ACK_UPT_LOCK, + MULTI_ACK_UPT_CLEAR, + MULTI_ACK_WRITE_RSP + }; + + /* States of the CONFIG fsm */ + enum config_fsm_state_e + { + CONFIG_IDLE, + CONFIG_LOOP, + CONFIG_WAIT, + CONFIG_RSP, + CONFIG_DIR_REQ, + CONFIG_DIR_ACCESS, + CONFIG_IVT_LOCK, + CONFIG_BC_SEND, + CONFIG_INVAL_SEND, + CONFIG_HEAP_REQ, + CONFIG_HEAP_SCAN, + CONFIG_HEAP_LAST, + CONFIG_TRT_LOCK, + CONFIG_TRT_SET, + CONFIG_PUT_REQ + }; + + /* States of the READ fsm */ + enum read_fsm_state_e + { + READ_IDLE, + READ_DIR_REQ, + READ_DIR_LOCK, + READ_DIR_HIT, + READ_HEAP_REQ, + READ_HEAP_LOCK, + READ_HEAP_WRITE, + READ_HEAP_ERASE, + READ_HEAP_LAST, + READ_RSP, + READ_TRT_LOCK, + READ_TRT_SET, + READ_TRT_REQ + }; + + /* States of the WRITE fsm */ + enum write_fsm_state_e + { + WRITE_IDLE, + WRITE_NEXT, + WRITE_DIR_REQ, + WRITE_DIR_LOCK, + WRITE_DIR_HIT, + WRITE_UPT_LOCK, + WRITE_UPT_HEAP_LOCK, + WRITE_UPT_REQ, + WRITE_UPT_NEXT, + WRITE_UPT_DEC, + WRITE_RSP, + WRITE_MISS_TRT_LOCK, + WRITE_MISS_TRT_DATA, + WRITE_MISS_TRT_SET, + WRITE_MISS_XRAM_REQ, + WRITE_BC_DIR_READ, + WRITE_BC_TRT_LOCK, + WRITE_BC_IVT_LOCK, + WRITE_BC_DIR_INVAL, + WRITE_BC_CC_SEND, + WRITE_BC_XRAM_REQ, + WRITE_WAIT + }; + + /* States of the IXR_RSP fsm */ + enum ixr_rsp_fsm_state_e + { + IXR_RSP_IDLE, + IXR_RSP_TRT_ERASE, + IXR_RSP_TRT_READ + }; + + /* States of the XRAM_RSP fsm */ + enum xram_rsp_fsm_state_e + { + XRAM_RSP_IDLE, + XRAM_RSP_TRT_COPY, + XRAM_RSP_TRT_DIRTY, + XRAM_RSP_DIR_LOCK, + XRAM_RSP_DIR_UPDT, + XRAM_RSP_DIR_RSP, + XRAM_RSP_IVT_LOCK, + XRAM_RSP_INVAL_WAIT, + XRAM_RSP_INVAL, + XRAM_RSP_WRITE_DIRTY, + XRAM_RSP_HEAP_REQ, + XRAM_RSP_HEAP_ERASE, + XRAM_RSP_HEAP_LAST, + XRAM_RSP_ERROR_ERASE, + XRAM_RSP_ERROR_RSP + }; + + /* States of the IXR_CMD fsm */ + enum ixr_cmd_fsm_state_e + { + IXR_CMD_READ_IDLE, + IXR_CMD_WRITE_IDLE, + IXR_CMD_CAS_IDLE, + IXR_CMD_XRAM_IDLE, + IXR_CMD_CONFIG_IDLE, + IXR_CMD_READ_TRT, + IXR_CMD_WRITE_TRT, + IXR_CMD_CAS_TRT, + IXR_CMD_XRAM_TRT, + IXR_CMD_CONFIG_TRT, + IXR_CMD_READ_SEND, + IXR_CMD_WRITE_SEND, + IXR_CMD_CAS_SEND, + IXR_CMD_XRAM_SEND, + IXR_CMD_CONFIG_SEND + }; + + /* States of the CAS fsm */ + enum cas_fsm_state_e + { + CAS_IDLE, + CAS_DIR_REQ, + CAS_DIR_LOCK, + CAS_DIR_HIT_READ, + CAS_DIR_HIT_COMPARE, + CAS_DIR_HIT_WRITE, + CAS_UPT_LOCK, + CAS_UPT_HEAP_LOCK, + CAS_UPT_REQ, + CAS_UPT_NEXT, + CAS_BC_TRT_LOCK, + CAS_BC_IVT_LOCK, + CAS_BC_DIR_INVAL, + CAS_BC_CC_SEND, + CAS_BC_XRAM_REQ, + CAS_RSP_FAIL, + CAS_RSP_SUCCESS, + CAS_MISS_TRT_LOCK, + CAS_MISS_TRT_SET, + CAS_MISS_XRAM_REQ, + CAS_WAIT + }; + + /* States of the CLEANUP fsm */ + enum cleanup_fsm_state_e + { + CLEANUP_IDLE, + CLEANUP_GET_NLINE, + CLEANUP_DIR_REQ, + CLEANUP_DIR_LOCK, + CLEANUP_DIR_WRITE, + CLEANUP_HEAP_REQ, + CLEANUP_HEAP_LOCK, + CLEANUP_HEAP_SEARCH, + CLEANUP_HEAP_CLEAN, + CLEANUP_HEAP_FREE, + CLEANUP_IVT_LOCK, + CLEANUP_IVT_DECREMENT, + CLEANUP_IVT_CLEAR, + CLEANUP_WRITE_RSP, + CLEANUP_SEND_CLACK + }; + + /* States of the ALLOC_DIR fsm */ + enum alloc_dir_fsm_state_e + { + ALLOC_DIR_RESET, + ALLOC_DIR_READ, + ALLOC_DIR_WRITE, + ALLOC_DIR_CAS, + ALLOC_DIR_CLEANUP, + ALLOC_DIR_XRAM_RSP, + ALLOC_DIR_CONFIG + }; + + /* States of the ALLOC_TRT fsm */ + enum alloc_trt_fsm_state_e + { + ALLOC_TRT_READ, + ALLOC_TRT_WRITE, + ALLOC_TRT_CAS, + ALLOC_TRT_XRAM_RSP, + ALLOC_TRT_IXR_RSP, + ALLOC_TRT_IXR_CMD, + ALLOC_TRT_CONFIG + }; + + /* States of the ALLOC_UPT fsm */ + enum alloc_upt_fsm_state_e + { + ALLOC_UPT_WRITE, + ALLOC_UPT_CAS, + ALLOC_UPT_MULTI_ACK + }; + + /* States of the ALLOC_IVT fsm */ + enum alloc_ivt_fsm_state_e + { + ALLOC_IVT_WRITE, + ALLOC_IVT_XRAM_RSP, + ALLOC_IVT_CLEANUP, + ALLOC_IVT_CAS, + ALLOC_IVT_CONFIG + }; + + /* States of the ALLOC_HEAP fsm */ + enum alloc_heap_fsm_state_e + { + ALLOC_HEAP_RESET, + ALLOC_HEAP_READ, + ALLOC_HEAP_WRITE, + ALLOC_HEAP_CAS, + ALLOC_HEAP_CLEANUP, + ALLOC_HEAP_XRAM_RSP, + ALLOC_HEAP_CONFIG + }; + + /* transaction type, pktid field */ + enum transaction_type_e + { + // b3 unused + // b2 READ / NOT READ + // Si READ + // b1 DATA / INS + // b0 UNC / MISS + // Si NOT READ + // b1 accÚs table llsc type SW / other + // b2 WRITE/CAS/LL/SC + TYPE_READ_DATA_UNC = 0x0, + TYPE_READ_DATA_MISS = 0x1, + TYPE_READ_INS_UNC = 0x2, + TYPE_READ_INS_MISS = 0x3, + TYPE_WRITE = 0x4, + TYPE_CAS = 0x5, + TYPE_LL = 0x6, + TYPE_SC = 0x7 + }; + + /* SC return values */ + enum sc_status_type_e + { + SC_SUCCESS = 0x00000000, + SC_FAIL = 0x00000001 + }; + + // debug variables + bool m_debug; + bool m_debug_previous_valid; + size_t m_debug_previous_count; + bool m_debug_previous_dirty; + data_t * m_debug_previous_data; + data_t * m_debug_data; + + // instrumentation counters + uint32_t m_cpt_cycles; // Counter of cycles + uint32_t m_cpt_reset_count; // Cycle at which the counters were last reset + + // Counters accessible in software (not yet but eventually) + uint32_t m_cpt_read_local; // Number of local READ transactions + uint32_t m_cpt_read_remote; // number of remote READ transactions + uint32_t m_cpt_read_cost; // Number of (flits * distance) for READs + + uint32_t m_cpt_write_local; // Number of local WRITE transactions + uint32_t m_cpt_write_remote; // number of remote WRITE transactions + uint32_t m_cpt_write_flits_local; // number of flits for local WRITEs + uint32_t m_cpt_write_flits_remote; // number of flits for remote WRITEs + uint32_t m_cpt_write_cost; // Number of (flits * distance) for WRITEs + + uint32_t m_cpt_ll_local; // Number of local LL transactions + uint32_t m_cpt_ll_remote; // number of remote LL transactions + uint32_t m_cpt_ll_cost; // Number of (flits * distance) for LLs + + uint32_t m_cpt_sc_local; // Number of local SC transactions + uint32_t m_cpt_sc_remote; // number of remote SC transactions + uint32_t m_cpt_sc_cost; // Number of (flits * distance) for SCs + + uint32_t m_cpt_cas_local; // Number of local SC transactions + uint32_t m_cpt_cas_remote; // number of remote SC transactions + uint32_t m_cpt_cas_cost; // Number of (flits * distance) for SCs + + uint32_t m_cpt_update; // Number of requests causing an UPDATE + uint32_t m_cpt_update_local; // Number of local UPDATE transactions + uint32_t m_cpt_update_remote; // Number of remote UPDATE transactions + uint32_t m_cpt_update_cost; // Number of (flits * distance) for UPDT + + uint32_t m_cpt_minval; // Number of requests causing M_INV + uint32_t m_cpt_minval_local; // Number of local M_INV transactions + uint32_t m_cpt_minval_remote; // Number of remote M_INV transactions + uint32_t m_cpt_minval_cost; // Number of (flits * distance) for M_INV + + uint32_t m_cpt_binval; // Number of BROADCAST INVAL + + uint32_t m_cpt_cleanup_local; // Number of local CLEANUP transactions + uint32_t m_cpt_cleanup_remote; // Number of remote CLEANUP transactions + uint32_t m_cpt_cleanup_cost; // Number of (flits * distance) for CLEANUPs + + // Counters not accessible by software + uint32_t m_cpt_read_miss; // Number of MISS READ + uint32_t m_cpt_write_miss; // Number of MISS WRITE + uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions + uint32_t m_cpt_write_broadcast;// Number of BROADCAST INVAL because of writes + + uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt + uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt + + uint32_t m_cpt_get; + uint32_t m_cpt_put; + + size_t m_prev_count; + + protected: + + SC_HAS_PROCESS(VciMemCache); + + public: + sc_in p_clk; + sc_in p_resetn; + sc_out p_irq; + soclib::caba::VciTarget p_vci_tgt; + soclib::caba::VciInitiator p_vci_ixr; + soclib::caba::DspinInput p_dspin_p2m; + soclib::caba::DspinOutput p_dspin_m2p; + soclib::caba::DspinOutput p_dspin_clack; + +#if MONITOR_MEMCACHE_FSM == 1 + sc_out p_read_fsm; + sc_out p_write_fsm; + sc_out p_xram_rsp_fsm; + sc_out p_cas_fsm; + sc_out p_cleanup_fsm; + sc_out p_config_fsm; + sc_out p_alloc_heap_fsm; + sc_out p_alloc_dir_fsm; + sc_out p_alloc_trt_fsm; + sc_out p_alloc_upt_fsm; + sc_out p_alloc_ivt_fsm; + sc_out p_tgt_cmd_fsm; + sc_out p_tgt_rsp_fsm; + sc_out p_ixr_cmd_fsm; + sc_out p_ixr_rsp_fsm; + sc_out p_cc_send_fsm; + sc_out p_cc_receive_fsm; + sc_out p_multi_ack_fsm; +#endif + + VciMemCache( + sc_module_name name, // Instance Name + const soclib::common::MappingTable &mtp, // Mapping table INT network + const soclib::common::MappingTable &mtx, // Mapping table RAM network + const soclib::common::IntTab &srcid_x, // global index RAM network + const soclib::common::IntTab &tgtid_d, // global index INT network + const size_t x_width, // X width in platform + const size_t y_width, // Y width in platform + const size_t nways, // Number of ways per set + const size_t nsets, // Number of sets + const size_t nwords, // Number of words per line + const size_t max_copies, // max number of copies + const size_t heap_size=HEAP_ENTRIES, + const size_t trt_lines=TRT_ENTRIES, + const size_t upt_lines=UPT_ENTRIES, + const size_t ivt_lines=IVT_ENTRIES, + const size_t debug_start_cycle=0, + const bool debug_ok=false ); + + ~VciMemCache(); + + void reset_counters(); + void print_stats(bool activity_counters = true, bool stats = true); + void print_trace( size_t detailed = 0 ); + void cache_monitor(addr_t addr); + void start_monitor(addr_t addr, addr_t length); + void stop_monitor(); + + private: + + void transition(); + void genMoore(); + void check_monitor(addr_t addr, data_t data, bool read); + + uint32_t req_distance(uint32_t req_srcid); + bool is_local_req(uint32_t req_srcid); + int read_instrumentation(uint32_t regr, uint32_t & rdata); + + // Component attributes + std::list m_seglist; // segments allocated + size_t m_nseg; // number of segments + soclib::common::Segment **m_seg; // array of segments pointers + size_t m_seg_config; // config segment index + const size_t m_srcid_x; // global index on RAM network + const size_t m_initiators; // Number of initiators + const size_t m_heap_size; // Size of the heap + const size_t m_ways; // Number of ways in a set + const size_t m_sets; // Number of cache sets + const size_t m_words; // Number of words in a line + size_t m_x_self; // X self coordinate + size_t m_y_self; // Y self coordinate + const size_t m_x_width; // number of x bits in platform + const size_t m_y_width; // number of y bits in platform + size_t m_debug_start_cycle; + bool m_debug_ok; + uint32_t m_trt_lines; + TransactionTab m_trt; // xram transaction table + uint32_t m_upt_lines; + UpdateTab m_upt; // pending update + UpdateTab m_ivt; // pending invalidate + CacheDirectory m_cache_directory; // data cache directory + CacheData m_cache_data; // data array[set][way][word] + HeapDirectory m_heap; // heap for copies + size_t m_max_copies; // max number of copies in heap + GenericLLSCGlobalTable + < 32 , // number of slots + 4096, // number of processors in the system + 8000, // registration life (# of LL operations) + addr_t > m_llsc_table; // ll/sc registration table + + // adress masks + const soclib::common::AddressMaskingTable m_x; + const soclib::common::AddressMaskingTable m_y; + const soclib::common::AddressMaskingTable m_z; + const soclib::common::AddressMaskingTable m_nline; + + // broadcast address + uint32_t m_broadcast_boundaries; + + // configuration interface constants + const uint32_t m_config_addr_mask; + const uint32_t m_config_regr_width; + const uint32_t m_config_func_width; + const uint32_t m_config_regr_idx_mask; + const uint32_t m_config_func_idx_mask; + + // Fifo between TGT_CMD fsm and READ fsm + GenericFifo m_cmd_read_addr_fifo; + GenericFifo m_cmd_read_length_fifo; + GenericFifo m_cmd_read_srcid_fifo; + GenericFifo m_cmd_read_trdid_fifo; + GenericFifo m_cmd_read_pktid_fifo; + + // Fifo between TGT_CMD fsm and WRITE fsm + GenericFifo m_cmd_write_addr_fifo; + GenericFifo m_cmd_write_eop_fifo; + GenericFifo m_cmd_write_srcid_fifo; + GenericFifo m_cmd_write_trdid_fifo; + GenericFifo m_cmd_write_pktid_fifo; + GenericFifo m_cmd_write_data_fifo; + GenericFifo m_cmd_write_be_fifo; + + // Fifo between TGT_CMD fsm and CAS fsm + GenericFifo m_cmd_cas_addr_fifo; + GenericFifo m_cmd_cas_eop_fifo; + GenericFifo m_cmd_cas_srcid_fifo; + GenericFifo m_cmd_cas_trdid_fifo; + GenericFifo m_cmd_cas_pktid_fifo; + GenericFifo m_cmd_cas_wdata_fifo; + + // Fifo between CC_RECEIVE fsm and CLEANUP fsm + GenericFifo m_cc_receive_to_cleanup_fifo; + + // Fifo between CC_RECEIVE fsm and MULTI_ACK fsm + GenericFifo m_cc_receive_to_multi_ack_fifo; + + // Buffer between TGT_CMD fsm and TGT_RSP fsm + // (segmentation violation response request) + sc_signal r_tgt_cmd_to_tgt_rsp_req; + + sc_signal r_tgt_cmd_to_tgt_rsp_rdata; + sc_signal r_tgt_cmd_to_tgt_rsp_error; + sc_signal r_tgt_cmd_to_tgt_rsp_srcid; + sc_signal r_tgt_cmd_to_tgt_rsp_trdid; + sc_signal r_tgt_cmd_to_tgt_rsp_pktid; + + sc_signal r_tgt_cmd_config_addr; + sc_signal r_tgt_cmd_config_cmd; + + ////////////////////////////////////////////////// + // Registers controlled by the TGT_CMD fsm + ////////////////////////////////////////////////// + + sc_signal r_tgt_cmd_fsm; + + /////////////////////////////////////////////////////// + // Registers controlled by the CONFIG fsm + /////////////////////////////////////////////////////// + + sc_signal r_config_fsm; // FSM state + sc_signal r_config_lock; // lock protecting exclusive access + sc_signal r_config_cmd; // config request type + sc_signal r_config_address; // target buffer physical address + sc_signal r_config_srcid; // config request srcid + sc_signal r_config_trdid; // config request trdid + sc_signal r_config_pktid; // config request pktid + sc_signal r_config_cmd_lines; // number of lines to be handled + sc_signal r_config_rsp_lines; // number of lines not completed + sc_signal r_config_dir_way; // DIR: selected way + sc_signal r_config_dir_lock; // DIR: locked entry + sc_signal r_config_dir_count; // DIR: number of copies + sc_signal r_config_dir_is_cnt; // DIR: counter mode (broadcast) + sc_signal r_config_dir_copy_srcid; // DIR: first copy SRCID + sc_signal r_config_dir_copy_inst; // DIR: first copy L1 type + sc_signal r_config_dir_ptr; // DIR: index of next copy in HEAP + sc_signal r_config_heap_next; // current pointer to scan HEAP + sc_signal r_config_trt_index; // selected entry in TRT + sc_signal r_config_ivt_index; // selected entry in IVT + + // Buffer between CONFIG fsm and IXR_CMD fsm + sc_signal r_config_to_ixr_cmd_req; // valid request + sc_signal r_config_to_ixr_cmd_index; // TRT index + + // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache) + sc_signal r_config_to_tgt_rsp_req; // valid request + sc_signal r_config_to_tgt_rsp_error; // error response + sc_signal r_config_to_tgt_rsp_srcid; // Transaction srcid + sc_signal r_config_to_tgt_rsp_trdid; // Transaction trdid + sc_signal r_config_to_tgt_rsp_pktid; // Transaction pktid + + // Buffer between CONFIG fsm and CC_SEND fsm (multi-inval / broadcast-inval) + sc_signal r_config_to_cc_send_multi_req; // multi-inval request + sc_signal r_config_to_cc_send_brdcast_req; // broadcast-inval request + sc_signal r_config_to_cc_send_nline; // line index + sc_signal r_config_to_cc_send_trdid; // UPT index + GenericFifo m_config_to_cc_send_inst_fifo; // fifo for the L1 type + GenericFifo m_config_to_cc_send_srcid_fifo; // fifo for owners srcid + + /////////////////////////////////////////////////////// + // Registers controlled by the READ fsm + /////////////////////////////////////////////////////// + + sc_signal r_read_fsm; // FSM state + sc_signal r_read_copy; // Srcid of the first copy + sc_signal r_read_copy_cache; // Srcid of the first copy + sc_signal r_read_copy_inst; // Type of the first copy + sc_signal r_read_tag; // cache line tag (in directory) + sc_signal r_read_is_cnt; // is_cnt bit (in directory) + sc_signal r_read_lock; // lock bit (in directory) + sc_signal r_read_dirty; // dirty bit (in directory) + sc_signal r_read_count; // number of copies + sc_signal r_read_ptr; // pointer to the heap + sc_signal * r_read_data; // data (one cache line) + sc_signal r_read_way; // associative way (in cache) + sc_signal r_read_trt_index; // Transaction Table index + sc_signal r_read_next_ptr; // Next entry to point to + sc_signal r_read_last_free; // Last free entry + sc_signal r_read_ll_key; // LL key from llsc_global_table + + // Buffer between READ fsm and IXR_CMD fsm + sc_signal r_read_to_ixr_cmd_req; // valid request + sc_signal r_read_to_ixr_cmd_index; // TRT index + + // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache) + sc_signal r_read_to_tgt_rsp_req; // valid request + sc_signal r_read_to_tgt_rsp_srcid; // Transaction srcid + sc_signal r_read_to_tgt_rsp_trdid; // Transaction trdid + sc_signal r_read_to_tgt_rsp_pktid; // Transaction pktid + sc_signal * r_read_to_tgt_rsp_data; // data (one cache line) + sc_signal r_read_to_tgt_rsp_word; // first word of the response + sc_signal r_read_to_tgt_rsp_length; // length of the response + sc_signal r_read_to_tgt_rsp_ll_key; // LL key from llsc_global_table + + /////////////////////////////////////////////////////////////// + // Registers controlled by the WRITE fsm + /////////////////////////////////////////////////////////////// + + sc_signal r_write_fsm; // FSM state + sc_signal r_write_address; // first word address + sc_signal r_write_word_index; // first word index in line + sc_signal r_write_word_count; // number of words in line + sc_signal r_write_srcid; // transaction srcid + sc_signal r_write_trdid; // transaction trdid + sc_signal r_write_pktid; // transaction pktid + sc_signal * r_write_data; // data (one cache line) + sc_signal * r_write_be; // one byte enable per word + sc_signal r_write_byte; // (BE != 0X0) and (BE != 0xF) + sc_signal r_write_is_cnt; // is_cnt bit (in directory) + sc_signal r_write_lock; // lock bit (in directory) + sc_signal r_write_tag; // cache line tag (in directory) + sc_signal r_write_copy; // first owner of the line + sc_signal r_write_copy_cache; // first owner of the line + sc_signal r_write_copy_inst; // is this owner a ICache ? + sc_signal r_write_count; // number of copies + sc_signal r_write_ptr; // pointer to the heap + sc_signal r_write_next_ptr; // next pointer to the heap + sc_signal r_write_to_dec; // need to decrement update counter + sc_signal r_write_way; // way of the line + sc_signal r_write_trt_index; // index in Transaction Table + sc_signal r_write_upt_index; // index in Update Table + sc_signal r_write_sc_fail; // sc command failed + sc_signal r_write_sc_key; // sc command key + sc_signal r_write_bc_data_we; // Write enable for data buffer + + // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1) + sc_signal r_write_to_tgt_rsp_req; // valid request + sc_signal r_write_to_tgt_rsp_srcid; // transaction srcid + sc_signal r_write_to_tgt_rsp_trdid; // transaction trdid + sc_signal r_write_to_tgt_rsp_pktid; // transaction pktid + sc_signal r_write_to_tgt_rsp_sc_fail; // sc command failed + + // Buffer between WRITE fsm and IXR_CMD fsm + sc_signal r_write_to_ixr_cmd_req; // valid request + sc_signal r_write_to_ixr_cmd_index; // TRT index + + // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches) + sc_signal r_write_to_cc_send_multi_req; // valid multicast request + sc_signal r_write_to_cc_send_brdcast_req; // valid brdcast request + sc_signal r_write_to_cc_send_nline; // cache line index + sc_signal r_write_to_cc_send_trdid; // index in Update Table + sc_signal * r_write_to_cc_send_data; // data (one cache line) + sc_signal * r_write_to_cc_send_be; // word enable + sc_signal r_write_to_cc_send_count; // number of words in line + sc_signal r_write_to_cc_send_index; // index of first word in line + GenericFifo m_write_to_cc_send_inst_fifo; // fifo for the L1 type + GenericFifo m_write_to_cc_send_srcid_fifo; // fifo for srcids + + // Buffer between WRITE fsm and MULTI_ACK fsm (Decrement UPT entry) + sc_signal r_write_to_multi_ack_req; // valid request + sc_signal r_write_to_multi_ack_upt_index; // index in update table + + ///////////////////////////////////////////////////////// + // Registers controlled by MULTI_ACK fsm + ////////////////////////////////////////////////////////// + + sc_signal r_multi_ack_fsm; // FSM state + sc_signal r_multi_ack_upt_index; // index in the Update Table + sc_signal r_multi_ack_srcid; // pending write srcid + sc_signal r_multi_ack_trdid; // pending write trdid + sc_signal r_multi_ack_pktid; // pending write pktid + sc_signal r_multi_ack_nline; // pending write nline + + // Buffer between MULTI_ACK fsm and TGT_RSP fsm (complete write/update transaction) + sc_signal r_multi_ack_to_tgt_rsp_req; // valid request + sc_signal r_multi_ack_to_tgt_rsp_srcid; // Transaction srcid + sc_signal r_multi_ack_to_tgt_rsp_trdid; // Transaction trdid + sc_signal r_multi_ack_to_tgt_rsp_pktid; // Transaction pktid + + /////////////////////////////////////////////////////// + // Registers controlled by CLEANUP fsm + /////////////////////////////////////////////////////// + + sc_signal r_cleanup_fsm; // FSM state + sc_signal r_cleanup_srcid; // transaction srcid + sc_signal r_cleanup_inst; // Instruction or Data ? + sc_signal r_cleanup_way_index; // L1 Cache Way index + sc_signal r_cleanup_nline; // cache line index + + + sc_signal r_cleanup_copy; // first copy + sc_signal r_cleanup_copy_cache; // first copy + sc_signal r_cleanup_copy_inst; // type of the first copy + sc_signal r_cleanup_count; // number of copies + sc_signal r_cleanup_ptr; // pointer to the heap + sc_signal r_cleanup_prev_ptr; // previous pointer to the heap + sc_signal r_cleanup_prev_srcid; // srcid of previous heap entry + sc_signal r_cleanup_prev_cache_id; // srcid of previous heap entry + sc_signal r_cleanup_prev_inst; // inst bit of previous heap entry + sc_signal r_cleanup_next_ptr; // next pointer to the heap + sc_signal r_cleanup_tag; // cache line tag (in directory) + sc_signal r_cleanup_is_cnt; // inst bit (in directory) + sc_signal r_cleanup_lock; // lock bit (in directory) + sc_signal r_cleanup_dirty; // dirty bit (in directory) + sc_signal r_cleanup_way; // associative way (in cache) + + sc_signal r_cleanup_write_srcid; // srcid of write rsp + sc_signal r_cleanup_write_trdid; // trdid of write rsp + sc_signal r_cleanup_write_pktid; // pktid of write rsp + + sc_signal r_cleanup_need_rsp; // write response required + sc_signal r_cleanup_need_ack; // config acknowledge required + + sc_signal r_cleanup_index; // index of the INVAL line (in the UPT) + + // Buffer between CLEANUP fsm and TGT_RSP fsm (acknowledge a write command from L1) + sc_signal r_cleanup_to_tgt_rsp_req; // valid request + sc_signal r_cleanup_to_tgt_rsp_srcid; // transaction srcid + sc_signal r_cleanup_to_tgt_rsp_trdid; // transaction trdid + sc_signal r_cleanup_to_tgt_rsp_pktid; // transaction pktid + + /////////////////////////////////////////////////////// + // Registers controlled by CAS fsm + /////////////////////////////////////////////////////// + + sc_signal r_cas_fsm; // FSM state + sc_signal r_cas_wdata; // write data word + sc_signal * r_cas_rdata; // read data word + sc_signal r_cas_lfsr; // lfsr for random introducing + sc_signal r_cas_cpt; // size of command + sc_signal r_cas_copy; // Srcid of the first copy + sc_signal r_cas_copy_cache; // Srcid of the first copy + sc_signal r_cas_copy_inst; // Type of the first copy + sc_signal r_cas_count; // number of copies + sc_signal r_cas_ptr; // pointer to the heap + sc_signal r_cas_next_ptr; // next pointer to the heap + sc_signal r_cas_is_cnt; // is_cnt bit (in directory) + sc_signal r_cas_dirty; // dirty bit (in directory) + sc_signal r_cas_way; // way in directory + sc_signal r_cas_set; // set in directory + sc_signal r_cas_tag; // cache line tag (in directory) + sc_signal r_cas_trt_index; // Transaction Table index + sc_signal r_cas_upt_index; // Update Table index + sc_signal * r_cas_data; // cache line data + + // Buffer between CAS fsm and IXR_CMD fsm + sc_signal r_cas_to_ixr_cmd_req; // valid request + sc_signal r_cas_to_ixr_cmd_index; // TRT index + + // Buffer between CAS fsm and TGT_RSP fsm + sc_signal r_cas_to_tgt_rsp_req; // valid request + sc_signal r_cas_to_tgt_rsp_data; // read data word + sc_signal r_cas_to_tgt_rsp_srcid; // Transaction srcid + sc_signal r_cas_to_tgt_rsp_trdid; // Transaction trdid + sc_signal r_cas_to_tgt_rsp_pktid; // Transaction pktid + + // Buffer between CAS fsm and CC_SEND fsm (Update/Invalidate L1 caches) + sc_signal r_cas_to_cc_send_multi_req; // valid request + sc_signal r_cas_to_cc_send_brdcast_req; // brdcast request + sc_signal r_cas_to_cc_send_nline; // cache line index + sc_signal r_cas_to_cc_send_trdid; // index in Update Table + sc_signal r_cas_to_cc_send_wdata; // data (one word) + sc_signal r_cas_to_cc_send_is_long; // it is a 64 bits CAS + sc_signal r_cas_to_cc_send_wdata_high; // data high (one word) + sc_signal r_cas_to_cc_send_index; // index of the word in line + GenericFifo m_cas_to_cc_send_inst_fifo; // fifo for the L1 type + GenericFifo m_cas_to_cc_send_srcid_fifo; // fifo for srcids + + //////////////////////////////////////////////////// + // Registers controlled by the IXR_RSP fsm + //////////////////////////////////////////////////// + + sc_signal r_ixr_rsp_fsm; // FSM state + sc_signal r_ixr_rsp_trt_index; // TRT entry index + sc_signal r_ixr_rsp_cpt; // word counter + + // Buffer between IXR_RSP fsm and CONFIG fsm (response from the XRAM) + sc_signal r_ixr_rsp_to_config_ack; // one single bit + + // Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM) + sc_signal * r_ixr_rsp_to_xram_rsp_rok; // one bit per TRT entry + + //////////////////////////////////////////////////// + // Registers controlled by the XRAM_RSP fsm + //////////////////////////////////////////////////// + + sc_signal r_xram_rsp_fsm; // FSM state + sc_signal r_xram_rsp_trt_index; // TRT entry index + TransactionTabEntry r_xram_rsp_trt_buf; // TRT entry local buffer + sc_signal r_xram_rsp_victim_inval; // victim line invalidate + sc_signal r_xram_rsp_victim_is_cnt; // victim line inst bit + sc_signal r_xram_rsp_victim_dirty; // victim line dirty bit + sc_signal r_xram_rsp_victim_way; // victim line way + sc_signal r_xram_rsp_victim_set; // victim line set + sc_signal r_xram_rsp_victim_nline; // victim line index + sc_signal r_xram_rsp_victim_copy; // victim line first copy + sc_signal r_xram_rsp_victim_copy_cache; // victim line first copy + sc_signal r_xram_rsp_victim_copy_inst; // victim line type of first copy + sc_signal r_xram_rsp_victim_count; // victim line number of copies + sc_signal r_xram_rsp_victim_ptr; // victim line pointer to the heap + sc_signal * r_xram_rsp_victim_data; // victim line data + sc_signal r_xram_rsp_ivt_index; // IVT entry index + sc_signal r_xram_rsp_next_ptr; // Next pointer to the heap + sc_signal r_xram_rsp_rerror_irq; // WRITE MISS rerror irq + sc_signal r_xram_rsp_rerror_irq_enable; // WRITE MISS rerror irq enable + sc_signal r_xram_rsp_rerror_address; // WRITE MISS rerror address + sc_signal r_xram_rsp_rerror_rsrcid; // WRITE MISS rerror srcid + + // Buffer between XRAM_RSP fsm and TGT_RSP fsm (response to L1 cache) + sc_signal r_xram_rsp_to_tgt_rsp_req; // Valid request + sc_signal r_xram_rsp_to_tgt_rsp_srcid; // Transaction srcid + sc_signal r_xram_rsp_to_tgt_rsp_trdid; // Transaction trdid + sc_signal r_xram_rsp_to_tgt_rsp_pktid; // Transaction pktid + sc_signal * r_xram_rsp_to_tgt_rsp_data; // data (one cache line) + sc_signal r_xram_rsp_to_tgt_rsp_word; // first word index + sc_signal r_xram_rsp_to_tgt_rsp_length; // length of the response + sc_signal r_xram_rsp_to_tgt_rsp_rerror; // send error to requester + sc_signal r_xram_rsp_to_tgt_rsp_ll_key; // LL key from llsc_global_table + + // Buffer between XRAM_RSP fsm and CC_SEND fsm (Inval L1 Caches) + sc_signal r_xram_rsp_to_cc_send_multi_req; // Valid request + sc_signal r_xram_rsp_to_cc_send_brdcast_req; // Broadcast request + sc_signal r_xram_rsp_to_cc_send_nline; // cache line index; + sc_signal r_xram_rsp_to_cc_send_trdid; // index of UPT entry + GenericFifo m_xram_rsp_to_cc_send_inst_fifo; // fifo for the L1 type + GenericFifo m_xram_rsp_to_cc_send_srcid_fifo; // fifo for srcids + + // Buffer between XRAM_RSP fsm and IXR_CMD fsm + sc_signal r_xram_rsp_to_ixr_cmd_req; // Valid request + sc_signal r_xram_rsp_to_ixr_cmd_index; // TRT index + + //////////////////////////////////////////////////// + // Registers controlled by the IXR_CMD fsm + //////////////////////////////////////////////////// + + sc_signal r_ixr_cmd_fsm; + sc_signal r_ixr_cmd_word; // word index for a put + sc_signal r_ixr_cmd_trdid; // TRT index value + sc_signal r_ixr_cmd_address; // address to XRAM + sc_signal * r_ixr_cmd_wdata; // cache line buffer + sc_signal r_ixr_cmd_get; // transaction type (PUT/GET) + + //////////////////////////////////////////////////// + // Registers controlled by TGT_RSP fsm + //////////////////////////////////////////////////// + + sc_signal r_tgt_rsp_fsm; + sc_signal r_tgt_rsp_cpt; + sc_signal r_tgt_rsp_key_sent; + + //////////////////////////////////////////////////// + // Registers controlled by CC_SEND fsm + //////////////////////////////////////////////////// + + sc_signal r_cc_send_fsm; + sc_signal r_cc_send_cpt; + sc_signal r_cc_send_inst; + + //////////////////////////////////////////////////// + // Registers controlled by CC_RECEIVE fsm + //////////////////////////////////////////////////// + + sc_signal r_cc_receive_fsm; + + //////////////////////////////////////////////////// + // Registers controlled by ALLOC_DIR fsm + //////////////////////////////////////////////////// + + sc_signal r_alloc_dir_fsm; + sc_signal r_alloc_dir_reset_cpt; + + //////////////////////////////////////////////////// + // Registers controlled by ALLOC_TRT fsm + //////////////////////////////////////////////////// + + sc_signal r_alloc_trt_fsm; + + //////////////////////////////////////////////////// + // Registers controlled by ALLOC_UPT fsm + //////////////////////////////////////////////////// + + sc_signal r_alloc_upt_fsm; + + //////////////////////////////////////////////////// + // Registers controlled by ALLOC_IVT fsm + //////////////////////////////////////////////////// + + sc_signal r_alloc_ivt_fsm; + + //////////////////////////////////////////////////// + // Registers controlled by ALLOC_HEAP fsm + //////////////////////////////////////////////////// + + sc_signal r_alloc_heap_fsm; + sc_signal r_alloc_heap_reset_cpt; + }; // end class VciMemCache + +}} + +#endif + +// Local Variables: +// tab-width: 2 +// c-basic-offset: 2 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=2:tabstop=2:softtabstop=2 + Index: /branches/fault_tolerance/modules/vci_mem_cache/caba/source/include/xram_transaction.h =================================================================== --- /branches/fault_tolerance/modules/vci_mem_cache/caba/source/include/xram_transaction.h (revision 724) +++ /branches/fault_tolerance/modules/vci_mem_cache/caba/source/include/xram_transaction.h (revision 724) @@ -0,0 +1,474 @@ +#ifndef XRAM_TRANSACTION_H_ +#define XRAM_TRANSACTION_H_ + +#include +#include +#include +#include "arithmetics.h" + +#define DEBUG_XRAM_TRANSACTION 0 + +//////////////////////////////////////////////////////////////////////// +// A transaction tab entry +//////////////////////////////////////////////////////////////////////// + +class TransactionTabEntry +{ + typedef sc_dt::sc_uint<64> wide_data_t; + typedef sc_dt::sc_uint<40> addr_t; + typedef uint32_t data_t; + typedef uint32_t be_t; + + public: + bool valid; // entry valid + bool xram_read; // read request to XRAM + addr_t nline; // index (zy) of the requested line + size_t srcid; // processor requesting the transaction + size_t trdid; // processor requesting the transaction + size_t pktid; // processor requesting the transaction + bool proc_read; // read request from processor + size_t read_length; // length of the read (for the response) + size_t word_index; // index of the first read word (for response) + std::vector wdata; // write buffer (one cache line) + std::vector wdata_be; // be for each data in the write buffer + bool rerror; // error returned by xram + data_t ll_key; // LL key returned by the llsc_global_table + bool config; // transaction required by CONFIG FSM + + ///////////////////////////////////////////////////////////////////// + // The init() function initializes the entry + ///////////////////////////////////////////////////////////////////// + void init() + { + valid = false; + rerror = false; + config = false; + } + + ///////////////////////////////////////////////////////////////////// + // The alloc() function initializes the vectors of an entry + // The "n_words" argument is the number of words in a cache line. + ///////////////////////////////////////////////////////////////////// + void alloc(size_t n_words) + { + wdata_be.reserve( (int)n_words ); + wdata.reserve( (int)n_words ); + for(size_t i=0; i wide_data_t; + typedef sc_dt::sc_uint<40> addr_t; + typedef uint32_t data_t; + typedef uint32_t be_t; + + private: + const std::string tab_name; // the name for logs + size_t size_tab; // the size of the tab + + data_t be_to_mask(be_t be) + { + data_t ret = 0; + if ( be&0x1 ) { + ret = ret | 0x000000FF; + } + if ( be&0x2 ) { + ret = ret | 0x0000FF00; + } + if ( be&0x4 ) { + ret = ret | 0x00FF0000; + } + if ( be&0x8 ) { + ret = ret | 0xFF000000; + } + return ret; + } + + public: + TransactionTabEntry *tab; // The transaction tab + + //////////////////////////////////////////////////////////////////// + // Constructors + //////////////////////////////////////////////////////////////////// + TransactionTab() + { + size_tab=0; + tab=NULL; + } + + TransactionTab(const std::string &name, + size_t n_entries, + size_t n_words ) + : tab_name( name ), + size_tab( n_entries ) + { + tab = new TransactionTabEntry[size_tab]; + for ( size_t i=0; i" << std::endl; + for ( size_t id = 0 ; id < size_tab ; id++ ) + { + tab[id].print( id , detailed ); + } + } + ///////////////////////////////////////////////////////////////////// + // The read() function returns a transaction tab entry. + // Arguments : + // - index : the index of the entry to read + ///////////////////////////////////////////////////////////////////// + TransactionTabEntry read(const size_t index) + { + assert( (index < size_tab) and + "MEMC ERROR: Invalid Transaction Tab Entry"); + + return tab[index]; + } + ///////////////////////////////////////////////////////////////////// + // The full() function returns the state of the transaction tab + // Arguments : + // - index : (return argument) the index of an empty entry + // The function returns true if the transaction tab is full + ///////////////////////////////////////////////////////////////////// + bool full(size_t &index) + { + for(size_t i=0; i &be, + const std::vector &data) + { + assert( (index < size_tab) and + "MEMC ERROR: The selected entry is out of range in TRT write_data_mask()"); + + assert( (be.size()==tab[index].wdata_be.size()) and + "MEMC ERROR: Bad be size in TRT write_data_mask()"); + + assert( (data.size()==tab[index].wdata.size()) and + "MEMC ERROR: Bad data size in TRT write_data_mask()"); + + for(size_t i=0; i &data_be, + const std::vector &data, + const data_t ll_key = 0, + const bool config = false) + { + assert( (index < size_tab) and + "MEMC ERROR: The selected entry is out of range in TRT set()"); + + assert( (data_be.size()==tab[index].wdata_be.size()) and + "MEMC ERROR: Bad data_be argument in TRT set()"); + + assert( (data.size()==tab[index].wdata.size()) and + "MEMC ERROR: Bad data argument in TRT set()"); + + tab[index].valid = true; + tab[index].xram_read = xram_read; + tab[index].nline = nline; + tab[index].srcid = srcid; + tab[index].trdid = trdid; + tab[index].pktid = pktid; + tab[index].proc_read = proc_read; + tab[index].read_length = read_length; + tab[index].word_index = word_index; + tab[index].ll_key = ll_key; + tab[index].config = config; + for(size_t i=0; i>32); + mask = be_to_mask(tab[index].wdata_be[word+1]); + tab[index].wdata[word+1] = (tab[index].wdata[word+1] & mask) | (value & ~mask); + } + ///////////////////////////////////////////////////////////////////// + // The erase() function erases an entry in the transaction tab. + // Arguments : + // - index : the index of the request in the transaction tab + ///////////////////////////////////////////////////////////////////// + void erase(const size_t index) + { + assert( (index < size_tab) and + "MEMC ERROR: The selected entry is out of range in TRT erase()"); + + tab[index].valid = false; + tab[index].rerror = false; + } + ///////////////////////////////////////////////////////////////////// + // The is_config() function returns the config flag value. + // Arguments : + // - index : the index of the entry in the transaction tab + ///////////////////////////////////////////////////////////////////// + bool is_config(const size_t index) + { + assert( (index < size_tab) and + "MEMC ERROR: The selected entry is out of range in TRT is_config()"); + + return tab[index].config; + } +}; // end class TransactionTab + +#endif + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: /branches/fault_tolerance/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp =================================================================== --- /branches/fault_tolerance/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 724) +++ /branches/fault_tolerance/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 724) @@ -0,0 +1,9045 @@ +/* -*- c++ -*- + * + * File : vci_mem_cache.cpp + * Date : 30/10/2008 + * Copyright : UPMC / LIP6 + * Authors : Alain Greiner / Eric Guthmuller + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Maintainers: alain.greiner@lip6.fr + * eric.guthmuller@polytechnique.edu + * cesar.fuguet-tortolero@lip6.fr + * alexandre.joannou@lip6.fr + */ + + +#include "../include/vci_mem_cache.h" +#include "mem_cache.h" + +////// debug services ///////////////////////////////////////////////////////////// +// All debug messages are conditionned by two variables: +// - compile time : DEBUG_MEMC_*** : defined below +// - execution time : m_debug = (m_debug_ok) and (m_cpt_cycle > m_debug_start_cycle) +/////////////////////////////////////////////////////////////////////////////////////// + +#define DEBUG_MEMC_GLOBAL 0 // synthetic trace of all FSMs +#define DEBUG_MEMC_CONFIG 1 // detailed trace of CONFIG FSM +#define DEBUG_MEMC_READ 1 // detailed trace of READ FSM +#define DEBUG_MEMC_WRITE 1 // detailed trace of WRITE FSM +#define DEBUG_MEMC_CAS 1 // detailed trace of CAS FSM +#define DEBUG_MEMC_IXR_CMD 1 // detailed trace of IXR_CMD FSM +#define DEBUG_MEMC_IXR_RSP 1 // detailed trace of IXR_RSP FSM +#define DEBUG_MEMC_XRAM_RSP 1 // detailed trace of XRAM_RSP FSM +#define DEBUG_MEMC_CC_SEND 1 // detailed trace of CC_SEND FSM +#define DEBUG_MEMC_MULTI_ACK 1 // detailed trace of MULTI_ACK FSM +#define DEBUG_MEMC_TGT_CMD 1 // detailed trace of TGT_CMD FSM +#define DEBUG_MEMC_TGT_RSP 1 // detailed trace of TGT_RSP FSM +#define DEBUG_MEMC_CLEANUP 1 // detailed trace of CLEANUP FSM + +#define RANDOMIZE_CAS 1 + +namespace soclib { namespace caba { + + const char *tgt_cmd_fsm_str[] = + { + "TGT_CMD_IDLE", + "TGT_CMD_READ", + "TGT_CMD_WRITE", + "TGT_CMD_CAS", + "TGT_CMD_CONFIG", + "TGT_CMD_ERROR" + }; + const char *tgt_rsp_fsm_str[] = + { + "TGT_RSP_READ_IDLE", + "TGT_RSP_WRITE_IDLE", + "TGT_RSP_CAS_IDLE", + "TGT_RSP_XRAM_IDLE", + "TGT_RSP_MULTI_ACK_IDLE", + "TGT_RSP_CLEANUP_IDLE", + "TGT_RSP_TGT_CMD_IDLE", + "TGT_RSP_CONFIG_IDLE", + "TGT_RSP_READ", + "TGT_RSP_WRITE", + "TGT_RSP_CAS", + "TGT_RSP_XRAM", + "TGT_RSP_MULTI_ACK", + "TGT_RSP_CLEANUP", + "TGT_RSP_TGT_CMD", + "TGT_RSP_CONFIG" + }; + const char *cc_receive_fsm_str[] = + { + "CC_RECEIVE_IDLE", + "CC_RECEIVE_CLEANUP", + "CC_RECEIVE_CLEANUP_EOP", + "CC_RECEIVE_MULTI_ACK" + }; + const char *cc_send_fsm_str[] = + { + "CC_SEND_XRAM_RSP_IDLE", + "CC_SEND_WRITE_IDLE", + "CC_SEND_CAS_IDLE", + "CC_SEND_CONFIG_IDLE", + "CC_SEND_XRAM_RSP_BRDCAST_HEADER", + "CC_SEND_XRAM_RSP_BRDCAST_NLINE", + "CC_SEND_XRAM_RSP_INVAL_HEADER", + "CC_SEND_XRAM_RSP_INVAL_NLINE", + "CC_SEND_WRITE_BRDCAST_HEADER", + "CC_SEND_WRITE_BRDCAST_NLINE", + "CC_SEND_WRITE_UPDT_HEADER", + "CC_SEND_WRITE_UPDT_NLINE", + "CC_SEND_WRITE_UPDT_DATA", + "CC_SEND_CAS_BRDCAST_HEADER", + "CC_SEND_CAS_BRDCAST_NLINE", + "CC_SEND_CAS_UPDT_HEADER", + "CC_SEND_CAS_UPDT_NLINE", + "CC_SEND_CAS_UPDT_DATA", + "CC_SEND_CAS_UPDT_DATA_HIGH", + "CC_SEND_CONFIG_INVAL_HEADER", + "CC_SEND_CONFIG_INVAL_NLINE", + "CC_SEND_CONFIG_BRDCAST_HEADER", + "CC_SEND_CONFIG_BRDCAST_NLINE" + }; + const char *multi_ack_fsm_str[] = + { + "MULTI_ACK_IDLE", + "MULTI_ACK_UPT_LOCK", + "MULTI_ACK_UPT_CLEAR", + "MULTI_ACK_WRITE_RSP" + }; + const char *config_fsm_str[] = + { + "CONFIG_IDLE", + "CONFIG_LOOP", + "CONFIG_WAIT", + "CONFIG_RSP", + "CONFIG_DIR_REQ", + "CONFIG_DIR_ACCESS", + "CONFIG_IVT_LOCK", + "CONFIG_BC_SEND", + "CONFIG_INVAL_SEND", + "CONFIG_HEAP_REQ", + "CONFIG_HEAP_SCAN", + "CONFIG_HEAP_LAST", + "CONFIG_TRT_LOCK", + "CONFIG_TRT_SET", + "CONFIG_PUT_REQ" + }; + const char *read_fsm_str[] = + { + "READ_IDLE", + "READ_DIR_REQ", + "READ_DIR_LOCK", + "READ_DIR_HIT", + "READ_HEAP_REQ", + "READ_HEAP_LOCK", + "READ_HEAP_WRITE", + "READ_HEAP_ERASE", + "READ_HEAP_LAST", + "READ_RSP", + "READ_TRT_LOCK", + "READ_TRT_SET", + "READ_TRT_REQ" + }; + const char *write_fsm_str[] = + { + "WRITE_IDLE", + "WRITE_NEXT", + "WRITE_DIR_REQ", + "WRITE_DIR_LOCK", + "WRITE_DIR_HIT", + "WRITE_UPT_LOCK", + "WRITE_UPT_HEAP_LOCK", + "WRITE_UPT_REQ", + "WRITE_UPT_NEXT", + "WRITE_UPT_DEC", + "WRITE_RSP", + "WRITE_MISS_TRT_LOCK", + "WRITE_MISS_TRT_DATA", + "WRITE_MISS_TRT_SET", + "WRITE_MISS_XRAM_REQ", + "WRITE_BC_DIR_READ", + "WRITE_BC_TRT_LOCK", + "WRITE_BC_IVT_LOCK", + "WRITE_BC_DIR_INVAL", + "WRITE_BC_CC_SEND", + "WRITE_BC_XRAM_REQ", + "WRITE_WAIT" + }; + const char *ixr_rsp_fsm_str[] = + { + "IXR_RSP_IDLE", + "IXR_RSP_TRT_ERASE", + "IXR_RSP_TRT_READ" + }; + const char *xram_rsp_fsm_str[] = + { + "XRAM_RSP_IDLE", + "XRAM_RSP_TRT_COPY", + "XRAM_RSP_TRT_DIRTY", + "XRAM_RSP_DIR_LOCK", + "XRAM_RSP_DIR_UPDT", + "XRAM_RSP_DIR_RSP", + "XRAM_RSP_IVT_LOCK", + "XRAM_RSP_INVAL_WAIT", + "XRAM_RSP_INVAL", + "XRAM_RSP_WRITE_DIRTY", + "XRAM_RSP_HEAP_REQ", + "XRAM_RSP_HEAP_ERASE", + "XRAM_RSP_HEAP_LAST", + "XRAM_RSP_ERROR_ERASE", + "XRAM_RSP_ERROR_RSP" + }; + const char *ixr_cmd_fsm_str[] = + { + "IXR_CMD_READ_IDLE", + "IXR_CMD_WRITE_IDLE", + "IXR_CMD_CAS_IDLE", + "IXR_CMD_XRAM_IDLE", + "IXR_CMD_CONFIG_IDLE", + "IXR_CMD_READ_TRT", + "IXR_CMD_WRITE_TRT", + "IXR_CMD_CAS_TRT", + "IXR_CMD_XRAM_TRT", + "IXR_CMD_CONFIG_TRT", + "IXR_CMD_READ_SEND", + "IXR_CMD_WRITE_SEND", + "IXR_CMD_CAS_SEND", + "IXR_CMD_XRAM_SEND", + "IXR_CMD_CONFIG_SEND" + }; + const char *cas_fsm_str[] = + { + "CAS_IDLE", + "CAS_DIR_REQ", + "CAS_DIR_LOCK", + "CAS_DIR_HIT_READ", + "CAS_DIR_HIT_COMPARE", + "CAS_DIR_HIT_WRITE", + "CAS_UPT_LOCK", + "CAS_UPT_HEAP_LOCK", + "CAS_UPT_REQ", + "CAS_UPT_NEXT", + "CAS_BC_TRT_LOCK", + "CAS_BC_IVT_LOCK", + "CAS_BC_DIR_INVAL", + "CAS_BC_CC_SEND", + "CAS_BC_XRAM_REQ", + "CAS_RSP_FAIL", + "CAS_RSP_SUCCESS", + "CAS_MISS_TRT_LOCK", + "CAS_MISS_TRT_SET", + "CAS_MISS_XRAM_REQ", + "CAS_WAIT" + }; + const char *cleanup_fsm_str[] = + { + "CLEANUP_IDLE", + "CLEANUP_GET_NLINE", + "CLEANUP_DIR_REQ", + "CLEANUP_DIR_LOCK", + "CLEANUP_DIR_WRITE", + "CLEANUP_HEAP_REQ", + "CLEANUP_HEAP_LOCK", + "CLEANUP_HEAP_SEARCH", + "CLEANUP_HEAP_CLEAN", + "CLEANUP_HEAP_FREE", + "CLEANUP_IVT_LOCK", + "CLEANUP_IVT_DECREMENT", + "CLEANUP_IVT_CLEAR", + "CLEANUP_WRITE_RSP", + "CLEANUP_SEND_CLACK" + }; + const char *alloc_dir_fsm_str[] = + { + "ALLOC_DIR_RESET", + "ALLOC_DIR_READ", + "ALLOC_DIR_WRITE", + "ALLOC_DIR_CAS", + "ALLOC_DIR_CLEANUP", + "ALLOC_DIR_XRAM_RSP", + "ALLOC_DIR_CONFIG" + }; + const char *alloc_trt_fsm_str[] = + { + "ALLOC_TRT_READ", + "ALLOC_TRT_WRITE", + "ALLOC_TRT_CAS", + "ALLOC_TRT_XRAM_RSP", + "ALLOC_TRT_IXR_RSP", + "ALLOC_TRT_IXR_CMD", + "ALLOC_TRT_CONFIG" + }; + const char *alloc_upt_fsm_str[] = + { + "ALLOC_UPT_WRITE", + "ALLOC_UPT_CAS", + "ALLOC_UPT_MULTI_ACK" + }; + const char *alloc_ivt_fsm_str[] = + { + "ALLOC_IVT_WRITE", + "ALLOC_IVT_XRAM_RSP", + "ALLOC_IVT_CLEANUP", + "ALLOC_IVT_CAS", + "ALLOC_IVT_CONFIG" + }; + const char *alloc_heap_fsm_str[] = + { + "ALLOC_HEAP_RESET", + "ALLOC_HEAP_READ", + "ALLOC_HEAP_WRITE", + "ALLOC_HEAP_CAS", + "ALLOC_HEAP_CLEANUP", + "ALLOC_HEAP_XRAM_RSP", + "ALLOC_HEAP_CONFIG" + }; + +#define tmpl(x) \ + template x \ + VciMemCache + + using namespace soclib::common; + + //////////////////////////////// + // Constructor + //////////////////////////////// + + tmpl(/**/)::VciMemCache( + sc_module_name name, + const MappingTable &mtp, // mapping table for direct network + const MappingTable &mtx, // mapping table for external network + const IntTab &srcid_x, // global index on external network + const IntTab &tgtid_d, // global index on direct network + const size_t x_width, // number of x bits in platform + const size_t y_width, // number of x bits in platform + const size_t nways, // number of ways per set + const size_t nsets, // number of associative sets + const size_t nwords, // number of words in cache line + const size_t max_copies, // max number of copies in heap + const size_t heap_size, // number of heap entries + const size_t trt_lines, // number of TRT entries + const size_t upt_lines, // number of UPT entries + const size_t ivt_lines, // number of IVT entries + const size_t debug_start_cycle, + const bool debug_ok) + + : soclib::caba::BaseModule(name), + + p_clk( "p_clk" ), + p_resetn( "p_resetn" ), + p_irq ( "p_irq" ), + p_vci_tgt( "p_vci_tgt" ), + p_vci_ixr( "p_vci_ixr" ), + p_dspin_p2m( "p_dspin_p2m" ), + p_dspin_m2p( "p_dspin_m2p" ), + p_dspin_clack( "p_dspin_clack" ), + + m_seglist(mtp.getSegmentList(tgtid_d)), + m_nseg(0), + m_srcid_x( mtx.indexForId(srcid_x)), + m_initiators(1 << vci_param_int::S), + m_heap_size(heap_size), + m_ways(nways), + m_sets(nsets), + m_words(nwords), + m_x_width(x_width), + m_y_width(y_width), + m_debug_start_cycle(debug_start_cycle), + m_debug_ok(debug_ok), + m_trt_lines(trt_lines), + m_trt(this->name(), trt_lines, nwords), + m_upt_lines(upt_lines), + m_upt(upt_lines), + m_ivt(ivt_lines), + m_cache_directory(nways, nsets, nwords, vci_param_int::N), + m_cache_data(nways, nsets, nwords), + m_heap(m_heap_size), + m_max_copies(max_copies), + m_llsc_table(), + +#define L2 soclib::common::uint32_log2 + m_x(L2(m_words), 2), + m_y(L2(m_sets), L2(m_words) + 2), + m_z(vci_param_int::N - L2(m_sets) - L2(m_words) - 2, L2(m_sets) + L2(m_words) + 2), + m_nline(vci_param_int::N - L2(m_words) - 2, L2(m_words) + 2), +#undef L2 + + // XMIN(5 bits) / XMAX(5 bits) / YMIN(5 bits) / YMAX(5 bits) + // 0b00000 / 0b11111 / 0b00000 / 0b11111 + m_broadcast_boundaries(0x7C1F), + + // CONFIG interface + m_config_addr_mask((1<<12)-1), + + m_config_regr_width(7), + m_config_func_width(3), + m_config_regr_idx_mask((1<::iterator seg; + size_t i = 0; + + for (seg = m_seglist.begin(); seg != m_seglist.end(); seg++) + { + std::cout << " => segment " << seg->name() + << " / base = " << std::hex << seg->baseAddress() + << " / size = " << seg->size() << std::endl; + m_nseg++; + } + + assert( (m_nseg > 0) and + "MEMC ERROR : At least one segment must be mapped to this component"); + + m_seg = new soclib::common::Segment*[m_nseg]; + + for (seg = m_seglist.begin(); seg != m_seglist.end(); seg++) + { + if (seg->special() ) m_seg_config = i; + m_seg[i] = & (*seg); + i++; + } + + addr_t gid = m_seg[0]->baseAddress() >> (vci_param_int::N - x_width - y_width); + m_x_self = (gid >> m_y_width) & ((1 << m_x_width) - 1); + m_y_self = gid & ((1 << m_y_width) - 1); + + // Allocation for IXR_RSP FSM + r_ixr_rsp_to_xram_rsp_rok = new sc_signal[m_trt_lines]; + + // Allocation for XRAM_RSP FSM + r_xram_rsp_victim_data = new sc_signal[nwords]; + r_xram_rsp_to_tgt_rsp_data = new sc_signal[nwords]; + + // Allocation for READ FSM + r_read_data = new sc_signal[nwords]; + r_read_to_tgt_rsp_data = new sc_signal[nwords]; + + // Allocation for WRITE FSM + r_write_data = new sc_signal[nwords]; + r_write_be = new sc_signal[nwords]; + r_write_to_cc_send_data = new sc_signal[nwords]; + r_write_to_cc_send_be = new sc_signal[nwords]; + + // Allocation for CAS FSM + r_cas_data = new sc_signal[nwords]; + r_cas_rdata = new sc_signal[2]; + + // Allocation for IXR_CMD FSM + r_ixr_cmd_wdata = new sc_signal[nwords]; + + // Allocation for debug + m_debug_previous_data = new data_t[nwords]; + m_debug_data = new data_t[nwords]; + + SC_METHOD(transition); + dont_initialize(); + sensitive << p_clk.pos(); + + SC_METHOD(genMoore); + dont_initialize(); + sensitive << p_clk.neg(); + } // end constructor + + + ///////////////////////////////////////////////////// + tmpl(void)::cache_monitor(addr_t addr) + ///////////////////////////////////////////////////// + { + size_t way = 0; + size_t set = 0; + DirectoryEntry entry = m_cache_directory.read_neutral(addr, &way, &set); + + // read data and compute data_change + bool data_change = false; + if (entry.valid) + { + for (size_t word = 0; word> (srcid_width - m_x_width)); + uint8_t req_y = (req_srcid >> (srcid_width - m_x_width - m_y_width)) & ((1 << m_y_width) - 1); + + return abs(m_x_self - req_x) + abs(m_y_self - req_y); + } + + + ///////////////////////////////////////////////////// + tmpl(bool)::is_local_req(uint32_t req_srcid) + ///////////////////////////////////////////////////// + { + return req_distance(req_srcid) == 0; + } + + ///////////////////////////////////////////////////// + tmpl(int)::read_instrumentation(uint32_t regr, uint32_t & rdata) + ///////////////////////////////////////////////////// + { + int error = 0; + + switch(regr) + { + /////////////////////////////////////////////////////// + // DIRECT instrumentation registers // + // Registers of 32 bits and therefore only LO is // + // implemented. // + // // + // The HI may be used in future implementations // + /////////////////////////////////////////////////////// + + // LOCAL + + case MEMC_LOCAL_READ_LO : rdata = m_cpt_read_local ; break; + case MEMC_LOCAL_WRITE_LO : rdata = m_cpt_write_flits_local ; break; + case MEMC_LOCAL_LL_LO : rdata = m_cpt_ll_local ; break; + case MEMC_LOCAL_SC_LO : rdata = m_cpt_sc_local ; break; + case MEMC_LOCAL_CAS_LO : rdata = m_cpt_cas_local ; break; + case MEMC_LOCAL_READ_HI : + case MEMC_LOCAL_WRITE_HI : + case MEMC_LOCAL_LL_HI : + case MEMC_LOCAL_SC_HI : + case MEMC_LOCAL_CAS_HI : rdata = 0; break; + + // REMOTE + + case MEMC_REMOTE_READ_LO : rdata = m_cpt_read_remote ; break; + case MEMC_REMOTE_WRITE_LO : rdata = m_cpt_write_flits_remote ; break; + case MEMC_REMOTE_LL_LO : rdata = m_cpt_ll_remote ; break; + case MEMC_REMOTE_SC_LO : rdata = m_cpt_sc_remote ; break; + case MEMC_REMOTE_CAS_LO : rdata = m_cpt_cas_remote ; break; + case MEMC_REMOTE_READ_HI : + case MEMC_REMOTE_WRITE_HI : + case MEMC_REMOTE_LL_HI : + case MEMC_REMOTE_SC_HI : + case MEMC_REMOTE_CAS_HI : rdata = 0; break; + + // COST + + case MEMC_COST_READ_LO : rdata = m_cpt_read_cost ; break; + case MEMC_COST_WRITE_LO : rdata = m_cpt_write_cost; break; + case MEMC_COST_LL_LO : rdata = m_cpt_ll_cost ; break; + case MEMC_COST_SC_LO : rdata = m_cpt_sc_cost ; break; + case MEMC_COST_CAS_LO : rdata = m_cpt_cas_cost ; break; + case MEMC_COST_READ_HI : + case MEMC_COST_WRITE_HI : + case MEMC_COST_LL_HI : + case MEMC_COST_SC_HI : + case MEMC_COST_CAS_HI : rdata = 0; break; + + /////////////////////////////////////////////////////// + // COHERENCE instrumentation registers // + // Registers of 32 bits and therefore only LO is // + // implemented. // + // // + // The HI may be used in future implementations // + /////////////////////////////////////////////////////// + + // LOCAL + + case MEMC_LOCAL_MUPDATE_LO : rdata = m_cpt_update_local ; break; + case MEMC_LOCAL_MINVAL_LO : rdata = m_cpt_minval_local ; break; + case MEMC_LOCAL_CLEANUP_LO : rdata = m_cpt_cleanup_local; break; + case MEMC_LOCAL_MUPDATE_HI : + case MEMC_LOCAL_MINVAL_HI : + case MEMC_LOCAL_CLEANUP_HI : rdata = 0; break; + + // REMOTE + + case MEMC_REMOTE_MUPDATE_LO : rdata = m_cpt_update_remote ; break; + case MEMC_REMOTE_MINVAL_LO : rdata = m_cpt_minval_remote ; break; + case MEMC_REMOTE_CLEANUP_LO : rdata = m_cpt_cleanup_remote; break; + case MEMC_REMOTE_MUPDATE_HI : + case MEMC_REMOTE_MINVAL_HI : + case MEMC_REMOTE_CLEANUP_HI : rdata = 0; break; + + // COST + + case MEMC_COST_MUPDATE_LO : rdata = m_cpt_update_cost ; break; + case MEMC_COST_MINVAL_LO : rdata = m_cpt_minval_cost ; break; + case MEMC_COST_CLEANUP_LO : rdata = m_cpt_cleanup_cost ; break; + case MEMC_COST_MUPDATE_HI : + case MEMC_COST_MINVAL_HI : + case MEMC_COST_CLEANUP_HI : rdata = 0; break; + + // TOTAL + + case MEMC_TOTAL_MUPDATE_LO : rdata = m_cpt_update ; break; + case MEMC_TOTAL_MINVAL_LO : rdata = m_cpt_minval ; break; + case MEMC_TOTAL_BINVAL_LO : rdata = m_cpt_binval ; break; + case MEMC_TOTAL_MUPDATE_HI : + case MEMC_TOTAL_MINVAL_HI : + case MEMC_TOTAL_BINVAL_HI : rdata = 0; break; + + // unknown register + + default : error = 1; + } + + return error; + } + + ////////////////////////////////////////////////// + tmpl(void)::print_trace( size_t detailed ) + ////////////////////////////////////////////////// + { + std::cout << "MEMC " << name() << std::endl; + std::cout << " " << tgt_cmd_fsm_str[r_tgt_cmd_fsm.read()] + << " | " << tgt_rsp_fsm_str[r_tgt_rsp_fsm.read()] + << " | " << read_fsm_str[r_read_fsm.read()] + << " | " << write_fsm_str[r_write_fsm.read()] + << " | " << cas_fsm_str[r_cas_fsm.read()] + << " | " << config_fsm_str[r_config_fsm.read()] + << " | " << cleanup_fsm_str[r_cleanup_fsm.read()] << std::endl; + std::cout << " " << cc_send_fsm_str[r_cc_send_fsm.read()] + << " | " << cc_receive_fsm_str[r_cc_receive_fsm.read()] + << " | " << multi_ack_fsm_str[r_multi_ack_fsm.read()] + << " | " << ixr_cmd_fsm_str[r_ixr_cmd_fsm.read()] + << " | " << ixr_rsp_fsm_str[r_ixr_rsp_fsm.read()] + << " | " << xram_rsp_fsm_str[r_xram_rsp_fsm.read()] << std::endl; + std::cout << " " << alloc_dir_fsm_str[r_alloc_dir_fsm.read()] + << " | " << alloc_trt_fsm_str[r_alloc_trt_fsm.read()] + << " | " << alloc_upt_fsm_str[r_alloc_upt_fsm.read()] + << " | " << alloc_ivt_fsm_str[r_alloc_ivt_fsm.read()] + << " | " << alloc_heap_fsm_str[r_alloc_heap_fsm.read()] << std::endl; + + if ( detailed ) m_trt.print(0); + } + + + ///////////////////////////////////////// + tmpl(void)::reset_counters() + ///////////////////////////////////////// + { + m_cpt_reset_count = m_cpt_cycles; + m_cpt_read_local = 0; + m_cpt_read_remote = 0; + m_cpt_read_cost = 0; + m_cpt_write_local = 0; + m_cpt_write_remote = 0; + m_cpt_write_flits_local = 0; + m_cpt_write_flits_remote = 0; + m_cpt_write_cost = 0; + m_cpt_ll_local = 0; + m_cpt_ll_remote = 0; + m_cpt_ll_cost = 0; + m_cpt_sc_local = 0; + m_cpt_sc_remote = 0; + m_cpt_sc_cost = 0; + m_cpt_cas_local = 0; + m_cpt_cas_remote = 0; + m_cpt_cas_cost = 0; + m_cpt_update = 0; + m_cpt_update_local = 0; + m_cpt_update_remote = 0; + m_cpt_update_cost = 0; + m_cpt_minval = 0; + m_cpt_minval_local = 0; + m_cpt_minval_remote = 0; + m_cpt_minval_cost = 0; + m_cpt_binval = 0; + m_cpt_cleanup_local = 0; + m_cpt_cleanup_remote = 0; + m_cpt_cleanup_cost = 0; + m_cpt_read_miss = 0; + m_cpt_write_miss = 0; + m_cpt_write_dirty = 0; + m_cpt_trt_rb = 0; + m_cpt_trt_full = 0; + m_cpt_get = 0; + m_cpt_put = 0; + } + + ///////////////////////////////////////// + tmpl(void)::print_stats(bool activity_counters, bool stats) + ///////////////////////////////////////// + { + std::cout << "**********************************" << std::dec << std::endl; + std::cout << "*** MEM_CACHE " << name() << std::endl; + std::cout << "**********************************" << std::dec << std::endl; + if (activity_counters) { + std::cout << "----------------------------------" << std::dec << std::endl; + std::cout << "--- Activity Counters ---" << std::dec << std::endl; + std::cout << "----------------------------------" << std::dec << std::endl; + std::cout + << "[000] COUNTERS RESET AT CYCLE = " << m_cpt_reset_count << std::endl + << "[001] NUMBER OF CYCLES = " << m_cpt_cycles << std::endl + << std::endl + << "[002] LOCAL READ = " << m_cpt_read_local << std::endl + << "[003] REMOTE READ = " << m_cpt_read_remote << std::endl + << "[004] READ COST (FLITS * DIST) = " << m_cpt_read_cost << std::endl + << std::endl + << "[005] LOCAL WRITE = " << m_cpt_write_local << std::endl + << "[006] REMOTE WRITE = " << m_cpt_write_remote << std::endl + << "[007] WRITE FLITS LOCAL = " << m_cpt_write_flits_local << std::endl + << "[008] WRITE FLITS REMOTE = " << m_cpt_write_flits_remote << std::endl + << "[009] WRITE COST (FLITS * DIST) = " << m_cpt_write_cost << std::endl + << std::endl + << "[010] LOCAL LL = " << m_cpt_ll_local << std::endl + << "[011] REMOTE LL = " << m_cpt_ll_remote << std::endl + << "[012] LL COST (FLITS * DIST) = " << m_cpt_ll_cost << std::endl + << std::endl + << "[013] LOCAL SC = " << m_cpt_sc_local << std::endl + << "[014] REMOTE SC = " << m_cpt_sc_remote << std::endl + << "[015] SC COST (FLITS * DIST) = " << m_cpt_sc_cost << std::endl + << std::endl + << "[016] LOCAL CAS = " << m_cpt_cas_local << std::endl + << "[017] REMOTE CAS = " << m_cpt_cas_remote << std::endl + << "[018] CAS COST (FLITS * DIST) = " << m_cpt_cas_cost << std::endl + << std::endl + << "[019] REQUESTS TRIG. UPDATE = " << m_cpt_update << std::endl + << "[020] LOCAL UPDATE = " << m_cpt_update_local << std::endl + << "[021] REMOTE UPDATE = " << m_cpt_update_remote << std::endl + << "[022] UPDT COST (FLITS * DIST) = " << m_cpt_update_cost << std::endl + << std::endl + << "[023] REQUESTS TRIG. M_INV = " << m_cpt_minval << std::endl + << "[024] LOCAL M_INV = " << m_cpt_minval_local << std::endl + << "[025] REMOTE M_INV = " << m_cpt_minval_remote << std::endl + << "[026] M_INV COST (FLITS * DIST) = " << m_cpt_minval_cost << std::endl + << std::endl + << "[027] BROADCAT INVAL = " << m_cpt_binval << std::endl + << std::endl + << "[028] LOCAL CLEANUP = " << m_cpt_cleanup_local << std::endl + << "[029] REMOTE CLEANUP = " << m_cpt_cleanup_remote << std::endl + << "[030] CLNUP COST (FLITS * DIST) = " << m_cpt_cleanup_cost << std::endl + << std::endl + << std::endl + << "[031] READ MISS = " << m_cpt_read_miss << std::endl + << "[032] WRITE MISS = " << m_cpt_write_miss << std::endl + << "[033] WRITE DIRTY = " << m_cpt_write_dirty << std::endl + << "[034] RD BLOCKED BY HIT IN TRT = " << m_cpt_trt_rb << std::endl + << "[035] TRANS BLOCKED BY FULL TRT = " << m_cpt_trt_full << std::endl + << "[036] PUT (UNIMPLEMENTED) = " << m_cpt_put << std::endl + << "[037] GET (UNIMPLEMENTED) = " << m_cpt_get << std::endl + << "[038] WRITE BROADCAST = " << m_cpt_write_broadcast << std::endl + << std::endl; + } + + if (stats) { + std::cout << "----------------------------------" << std::dec << std::endl; + std::cout << "--- Calculated Stats ---" << std::dec << std::endl; + std::cout << "----------------------------------" << std::dec << std::endl; + std::cout + << "[100] READ TOTAL = " << m_cpt_read_local + m_cpt_read_remote << std::endl + << "[101] READ RATE = " << (double) (m_cpt_read_local + m_cpt_read_remote) / m_cpt_cycles << std::endl + << "[102] LOCAL READ RATE = " << (double) m_cpt_read_local / m_cpt_cycles << std::endl + << "[103] REMOTE READ RATE = " << (double) m_cpt_read_remote / m_cpt_cycles << std::endl + << "[104] READ MISS RATE = " << (double) m_cpt_read_miss / (m_cpt_read_local + m_cpt_read_remote) << std::endl + << std::endl + << "[105] WRITE TOTAL = " << m_cpt_write_local + m_cpt_write_remote << std::endl + << "[106] WRITE RATE = " << (double) (m_cpt_write_local + m_cpt_write_remote) / m_cpt_cycles << std::endl + << "[107] LOCAL WRITE RATE = " << (double) m_cpt_write_local / m_cpt_cycles << std::endl + << "[108] REMOTE WRITE RATE = " << (double) m_cpt_write_remote / m_cpt_cycles << std::endl + << "[109] WRITE MISS RATE = " << (double) m_cpt_write_miss / (m_cpt_write_local + m_cpt_write_remote) << std::endl + << "[110] WRITE BURST TOTAL = " << m_cpt_write_flits_local + m_cpt_write_flits_remote << std::endl + << "[111] WRITE BURST AVERAGE = " << (double) (m_cpt_write_flits_local + m_cpt_write_flits_remote) / (m_cpt_write_local + m_cpt_write_remote) << std::endl + << "[112] LOCAL WRITE BURST AV. = " << (double) m_cpt_write_flits_local / (m_cpt_write_local + m_cpt_write_remote) << std::endl + << "[113] REMOTE WRITE BURST AV = " << (double) m_cpt_write_flits_remote / (m_cpt_write_local + m_cpt_write_remote) << std::endl + << std::endl + << "[114] UPDATE RATE = " << (double) m_cpt_update / m_cpt_cycles << std::endl + << "[115] AV. UPDATE PER UP REQ = " << (double) (m_cpt_update_local + m_cpt_update_remote) / m_cpt_update << std::endl + << "[116] AV. LOC UPDT PER UP REQ = " << (double) m_cpt_update_local / m_cpt_update << std::endl + << "[117] AV. REMOTE UPDT PER UP REQ = " << (double) m_cpt_update_remote / m_cpt_update << std::endl + << std::endl + << "[118] INVAL MULTICAST RATE = " << (double) m_cpt_minval / m_cpt_cycles << std::endl + << "[119] AVE. INVAL PER M_INV = " << (double) (m_cpt_minval_local + m_cpt_minval_remote) / m_cpt_minval << std::endl + << "[120] AV. LOC INV PER M_INV = " << (double) m_cpt_minval_local / m_cpt_minval << std::endl + << "[121] AV. REM INV PER M_INV = " << (double) m_cpt_minval_remote / m_cpt_minval << std::endl + << std::endl + << "[122] INVAL BROADCAST RATE = " << (double) m_cpt_binval / m_cpt_cycles << std::endl + << "[123] WRITE DIRTY RATE = " << (double) m_cpt_write_dirty / m_cpt_cycles << std::endl + << std::endl + << "[124] CLEANUP RATE = " << (double) (m_cpt_cleanup_local + m_cpt_cleanup_remote) / m_cpt_cycles << std::endl + << "[125] LOCAL CLEANUP RATE = " << (double) m_cpt_cleanup_local / m_cpt_cycles << std::endl + << "[126] REMOTE CLEANUP RATE = " << (double) m_cpt_cleanup_remote / m_cpt_cycles << std::endl + << "[127] LL RATE = " << (double) (m_cpt_ll_local + m_cpt_ll_remote) / m_cpt_cycles << std::endl + << "[128] LOCAL LL RATE = " << (double) m_cpt_ll_local / m_cpt_cycles << std::endl + << "[129] REMOTE LL RATE = " << (double) m_cpt_ll_remote / m_cpt_cycles << std::endl + << "[130] SC RATE = " << (double) (m_cpt_sc_local + m_cpt_sc_remote) / m_cpt_cycles << std::endl + << "[131] LOCAL SC RATE = " << (double) m_cpt_sc_local / m_cpt_cycles << std::endl + << "[132] REMOTE SC RATE = " << (double) m_cpt_sc_remote / m_cpt_cycles << std::endl + << "[133] CAS RATE = " << (double) (m_cpt_cas_local + m_cpt_cas_remote) / m_cpt_cycles << std::endl + << "[134] LOCAL CAS RATE = " << (double) m_cpt_cas_local / m_cpt_cycles << std::endl + << "[135] REMOTE CAS RATE = " << (double) m_cpt_cas_remote / m_cpt_cycles << std::endl + << std::endl + << std::endl; + } + } + + + ///////////////////////////////// + tmpl(/**/)::~VciMemCache() + ///////////////////////////////// + { + delete [] m_seg; + + delete [] r_ixr_rsp_to_xram_rsp_rok; + delete [] r_xram_rsp_victim_data; + delete [] r_xram_rsp_to_tgt_rsp_data; + + delete [] r_read_data; + delete [] r_read_to_tgt_rsp_data; + + delete [] r_write_data; + delete [] r_write_be; + delete [] r_write_to_cc_send_data; + delete [] r_write_to_cc_send_be; + + delete [] r_cas_data; + delete [] r_cas_rdata; + + delete [] r_ixr_cmd_wdata; + delete [] m_debug_previous_data; + delete [] m_debug_data; + + //print_stats(); + } + + ////////////////////////////////// + tmpl(void) ::transition() + ////////////////////////////////// + { + using soclib::common::uint32_log2; + + // RESET + if (! p_resetn.read()) + { + + // Initializing FSMs + r_tgt_cmd_fsm = TGT_CMD_IDLE; + r_config_fsm = CONFIG_IDLE; + r_tgt_rsp_fsm = TGT_RSP_READ_IDLE; + r_cc_send_fsm = CC_SEND_XRAM_RSP_IDLE; + r_cc_receive_fsm = CC_RECEIVE_IDLE; + r_multi_ack_fsm = MULTI_ACK_IDLE; + r_read_fsm = READ_IDLE; + r_write_fsm = WRITE_IDLE; + r_cas_fsm = CAS_IDLE; + r_cleanup_fsm = CLEANUP_IDLE; + r_alloc_dir_fsm = ALLOC_DIR_RESET; + r_alloc_heap_fsm = ALLOC_HEAP_RESET; + r_alloc_trt_fsm = ALLOC_TRT_READ; + r_alloc_upt_fsm = ALLOC_UPT_WRITE; + r_alloc_ivt_fsm = ALLOC_IVT_WRITE; + r_ixr_rsp_fsm = IXR_RSP_IDLE; + r_xram_rsp_fsm = XRAM_RSP_IDLE; + r_ixr_cmd_fsm = IXR_CMD_READ_IDLE; + + m_debug = false; + m_debug_previous_valid = false; + m_debug_previous_dirty = false; + m_debug_previous_count = 0; + + // Initializing Tables + m_trt.init(); + m_upt.init(); + m_ivt.init(); + m_llsc_table.init(); + + // initializing FIFOs and communication Buffers + + m_cmd_read_addr_fifo.init(); + m_cmd_read_length_fifo.init(); + m_cmd_read_srcid_fifo.init(); + m_cmd_read_trdid_fifo.init(); + m_cmd_read_pktid_fifo.init(); + + m_cmd_write_addr_fifo.init(); + m_cmd_write_eop_fifo.init(); + m_cmd_write_srcid_fifo.init(); + m_cmd_write_trdid_fifo.init(); + m_cmd_write_pktid_fifo.init(); + m_cmd_write_data_fifo.init(); + + m_cmd_cas_addr_fifo.init() ; + m_cmd_cas_srcid_fifo.init() ; + m_cmd_cas_trdid_fifo.init() ; + m_cmd_cas_pktid_fifo.init() ; + m_cmd_cas_wdata_fifo.init() ; + m_cmd_cas_eop_fifo.init() ; + + r_config_cmd = MEMC_CMD_NOP; + r_config_lock = false; + + m_config_to_cc_send_inst_fifo.init(); + m_config_to_cc_send_srcid_fifo.init(); + + r_tgt_cmd_to_tgt_rsp_req = false; + + r_read_to_tgt_rsp_req = false; + r_read_to_ixr_cmd_req = false; + + r_write_to_tgt_rsp_req = false; + r_write_to_ixr_cmd_req = false; + r_write_to_cc_send_multi_req = false; + r_write_to_cc_send_brdcast_req = false; + r_write_to_multi_ack_req = false; + + m_write_to_cc_send_inst_fifo.init(); + m_write_to_cc_send_srcid_fifo.init(); + + r_cleanup_to_tgt_rsp_req = false; + + m_cc_receive_to_cleanup_fifo.init(); + + r_multi_ack_to_tgt_rsp_req = false; + + m_cc_receive_to_multi_ack_fifo.init(); + + r_cas_to_tgt_rsp_req = false; + r_cas_cpt = 0 ; + r_cas_lfsr = -1 ; + r_cas_to_ixr_cmd_req = false; + r_cas_to_cc_send_multi_req = false; + r_cas_to_cc_send_brdcast_req = false; + + m_cas_to_cc_send_inst_fifo.init(); + m_cas_to_cc_send_srcid_fifo.init(); + + for (size_t i = 0; i < m_trt_lines ; i++) + { + r_ixr_rsp_to_xram_rsp_rok[i] = false; + } + + r_xram_rsp_to_tgt_rsp_req = false; + r_xram_rsp_to_cc_send_multi_req = false; + r_xram_rsp_to_cc_send_brdcast_req = false; + r_xram_rsp_to_ixr_cmd_req = false; + r_xram_rsp_trt_index = 0; + r_xram_rsp_rerror_irq = false; + r_xram_rsp_rerror_irq_enable = false; + + m_xram_rsp_to_cc_send_inst_fifo.init(); + m_xram_rsp_to_cc_send_srcid_fifo.init(); + + r_alloc_dir_reset_cpt = 0; + r_alloc_heap_reset_cpt = 0; + + r_tgt_rsp_key_sent = false; + + // Activity counters + m_cpt_cycles = 0; + m_cpt_reset_count = 0; + m_cpt_read_local = 0; + m_cpt_read_remote = 0; + m_cpt_read_cost = 0; + m_cpt_write_local = 0; + m_cpt_write_remote = 0; + m_cpt_write_flits_local = 0; + m_cpt_write_flits_remote = 0; + m_cpt_write_cost = 0; + m_cpt_ll_local = 0; + m_cpt_ll_remote = 0; + m_cpt_ll_cost = 0; + m_cpt_sc_local = 0; + m_cpt_sc_remote = 0; + m_cpt_sc_cost = 0; + m_cpt_cas_local = 0; + m_cpt_cas_remote = 0; + m_cpt_cas_cost = 0; + m_cpt_update = 0; + m_cpt_update_local = 0; + m_cpt_update_remote = 0; + m_cpt_update_cost = 0; + m_cpt_minval = 0; + m_cpt_minval_local = 0; + m_cpt_minval_remote = 0; + m_cpt_minval_cost = 0; + m_cpt_binval = 0; + m_cpt_cleanup_local = 0; + m_cpt_cleanup_remote = 0; + m_cpt_cleanup_cost = 0; + + m_cpt_read_miss = 0; + m_cpt_write_miss = 0; + m_cpt_write_dirty = 0; + m_cpt_write_broadcast = 0; + m_cpt_trt_rb = 0; + m_cpt_trt_full = 0; + m_cpt_get = 0; + m_cpt_put = 0; + + return; + } + + bool cmd_read_fifo_put = false; + bool cmd_read_fifo_get = false; + + bool cmd_write_fifo_put = false; + bool cmd_write_fifo_get = false; + + bool cmd_cas_fifo_put = false; + bool cmd_cas_fifo_get = false; + + bool cc_receive_to_cleanup_fifo_get = false; + bool cc_receive_to_cleanup_fifo_put = false; + + bool cc_receive_to_multi_ack_fifo_get = false; + bool cc_receive_to_multi_ack_fifo_put = false; + + bool write_to_cc_send_fifo_put = false; + bool write_to_cc_send_fifo_get = false; + bool write_to_cc_send_fifo_inst = false; + size_t write_to_cc_send_fifo_srcid = 0; + + bool xram_rsp_to_cc_send_fifo_put = false; + bool xram_rsp_to_cc_send_fifo_get = false; + bool xram_rsp_to_cc_send_fifo_inst = false; + size_t xram_rsp_to_cc_send_fifo_srcid = 0; + + bool config_rsp_lines_incr = false; + bool config_rsp_lines_cleanup_decr = false; + bool config_rsp_lines_ixr_rsp_decr = false; + + bool config_to_cc_send_fifo_put = false; + bool config_to_cc_send_fifo_get = false; + bool config_to_cc_send_fifo_inst = false; + size_t config_to_cc_send_fifo_srcid = 0; + + bool cas_to_cc_send_fifo_put = false; + bool cas_to_cc_send_fifo_get = false; + bool cas_to_cc_send_fifo_inst = false; + size_t cas_to_cc_send_fifo_srcid = 0; + + m_debug = (m_cpt_cycles > m_debug_start_cycle) and m_debug_ok; + +#if DEBUG_MEMC_GLOBAL + if (m_debug) + { + std::cout + << "---------------------------------------------" << std::dec << std::endl + << "MEM_CACHE " << name() + << " ; Time = " << m_cpt_cycles << std::endl + << " - TGT_CMD FSM = " << tgt_cmd_fsm_str[r_tgt_cmd_fsm.read()] << std::endl + << " - TGT_RSP FSM = " << tgt_rsp_fsm_str[r_tgt_rsp_fsm.read()] << std::endl + << " - CC_SEND FSM = " << cc_send_fsm_str[r_cc_send_fsm.read()] << std::endl + << " - CC_RECEIVE FSM = " << cc_receive_fsm_str[r_cc_receive_fsm.read()] << std::endl + << " - MULTI_ACK FSM = " << multi_ack_fsm_str[r_multi_ack_fsm.read()] << std::endl + << " - READ FSM = " << read_fsm_str[r_read_fsm.read()] << std::endl + << " - WRITE FSM = " << write_fsm_str[r_write_fsm.read()] << std::endl + << " - CAS FSM = " << cas_fsm_str[r_cas_fsm.read()] << std::endl + << " - CLEANUP FSM = " << cleanup_fsm_str[r_cleanup_fsm.read()] << std::endl + << " - IXR_CMD FSM = " << ixr_cmd_fsm_str[r_ixr_cmd_fsm.read()] << std::endl + << " - IXR_RSP FSM = " << ixr_rsp_fsm_str[r_ixr_rsp_fsm.read()] << std::endl + << " - XRAM_RSP FSM = " << xram_rsp_fsm_str[r_xram_rsp_fsm.read()] << std::endl + << " - ALLOC_DIR FSM = " << alloc_dir_fsm_str[r_alloc_dir_fsm.read()] << std::endl + << " - ALLOC_TRT FSM = " << alloc_trt_fsm_str[r_alloc_trt_fsm.read()] << std::endl + << " - ALLOC_UPT FSM = " << alloc_upt_fsm_str[r_alloc_upt_fsm.read()] << std::endl + << " - ALLOC_HEAP FSM = " << alloc_heap_fsm_str[r_alloc_heap_fsm.read()] << std::endl; + } +#endif + + //////////////////////////////////////////////////////////////////////////////////// + // TGT_CMD FSM + //////////////////////////////////////////////////////////////////////////////////// + // The TGT_CMD_FSM controls the incoming VCI command pakets from the processors, + // and dispatch these commands to the proper FSM through dedicated FIFOs. + // + // There are 5 types of commands accepted in the XRAM segment: + // - READ : A READ request has a length of 1 VCI flit. It can be a single word + // or an entire cache line, depending on the PLEN value => READ FSM + // - WRITE : A WRITE request has a maximum length of 16 flits, and can only + // concern words in a same line => WRITE FSM + // - CAS : A CAS request has a length of 2 flits or 4 flits => CAS FSM + // - LL : An LL request has a length of 1 flit => READ FSM + // - SC : An SC request has a length of 2 flits. First flit contains the + // acces key, second flit the data to write => WRITE FSM. + // + // The READ/WRITE commands accepted in the configuration segment are targeting + // configuration or status registers. They must contain one single flit. + // - For almost all addressable registers, the response is returned immediately. + // - For MEMC_CMD_TYPE, the response is delayed until the operation is completed. + //////////////////////////////////////////////////////////////////////////////////// + + + switch (r_tgt_cmd_fsm.read()) + { + ////////////////// + case TGT_CMD_IDLE: // waiting a VCI command (RAM or CONFIG) + if (p_vci_tgt.cmdval) + { +#if DEBUG_MEMC_TGT_CMD + if (m_debug) + std::cout << " Receive command from srcid " + << std::hex << p_vci_tgt.srcid.read() + << " / address " << std::hex << p_vci_tgt.address.read() << std::endl; +#endif + // checking segmentation violation + addr_t address = p_vci_tgt.address.read(); + uint32_t plen = p_vci_tgt.plen.read(); + bool config = false; + + for (size_t seg_id = 0; (seg_id < m_nseg) ; seg_id++) + { + if (m_seg[seg_id]->contains(address) && + m_seg[seg_id]->contains(address + plen - vci_param_int::B)) + { + if (m_seg[seg_id]->special()) config = true; + } + } + + if (config) /////////// configuration command + { + if (!p_vci_tgt.eop.read()) r_tgt_cmd_fsm = TGT_CMD_ERROR; + else r_tgt_cmd_fsm = TGT_CMD_CONFIG; + } + else //////////// memory access + { + if (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) + { + // check that the pktid is either : + // TYPE_READ_DATA_UNC + // TYPE_READ_DATA_MISS + // TYPE_READ_INS_UNC + // TYPE_READ_INS_MISS + // ==> bit2 must be zero with the TSAR encoding + // ==> mask = 0b0100 = 0x4 + assert(((p_vci_tgt.pktid.read() & 0x4) == 0x0) and + "The type specified in the pktid field is incompatible with the READ CMD"); + r_tgt_cmd_fsm = TGT_CMD_READ; + } + else if (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) + { + // check that the pktid is TYPE_WRITE + // ==> TYPE_WRITE = X100 with the TSAR encoding + // ==> mask = 0b0111 = 0x7 + assert((((p_vci_tgt.pktid.read() & 0x7) == 0x4) or ((p_vci_tgt.pktid.read() & 0x7) == 0x0)) and + "The type specified in the pktid field is incompatible with the WRITE CMD"); + r_tgt_cmd_fsm = TGT_CMD_WRITE; + } + else if (p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) + { + // check that the pktid is TYPE_LL + // ==> TYPE_LL = X110 with the TSAR encoding + // ==> mask = 0b0111 = 0x7 + assert(((p_vci_tgt.pktid.read() & 0x7) == 0x6) and + "The type specified in the pktid field is incompatible with the LL CMD"); + r_tgt_cmd_fsm = TGT_CMD_READ; + } + else if (p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP) + { + // check that the pktid is either : + // TYPE_CAS + // TYPE_SC + // ==> TYPE_CAS = X101 with the TSAR encoding + // ==> TYPE_SC = X111 with the TSAR encoding + // ==> mask = 0b0101 = 0x5 + assert(((p_vci_tgt.pktid.read() & 0x5) == 0x5) and + "The type specified in the pktid field is incompatible with the NOP CMD"); + + if ((p_vci_tgt.pktid.read() & 0x7) == TYPE_CAS) r_tgt_cmd_fsm = TGT_CMD_CAS; + else r_tgt_cmd_fsm = TGT_CMD_WRITE; + } + else + { + r_tgt_cmd_fsm = TGT_CMD_ERROR; + } + } + } + break; + + /////////////////// + case TGT_CMD_ERROR: // response error must be sent + + // wait if pending request + if (r_tgt_cmd_to_tgt_rsp_req.read()) break; + + // consume all the command packet flits before sending response error + if (p_vci_tgt.cmdval and p_vci_tgt.eop) + { + r_tgt_cmd_to_tgt_rsp_srcid = p_vci_tgt.srcid.read(); + r_tgt_cmd_to_tgt_rsp_trdid = p_vci_tgt.trdid.read(); + r_tgt_cmd_to_tgt_rsp_pktid = p_vci_tgt.pktid.read(); + r_tgt_cmd_to_tgt_rsp_req = true; + r_tgt_cmd_to_tgt_rsp_error = 1; + r_tgt_cmd_fsm = TGT_CMD_IDLE; + +#if DEBUG_MEMC_TGT_CMD + if (m_debug) + std::cout << " Segmentation violation:" + << " address = " << std::hex << p_vci_tgt.address.read() + << " / srcid = " << p_vci_tgt.srcid.read() + << " / trdid = " << p_vci_tgt.trdid.read() + << " / pktid = " << p_vci_tgt.pktid.read() + << " / plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; +#endif + + } + break; + + //////////////////// + case TGT_CMD_CONFIG: // execute config request and return response + { + /////////////////////////////////////////////////////////// + // Decoding CONFIG interface commands // + // // + // VCI ADDRESS // + // ================================================ // + // GLOBAL | LOCAL | ... | FUNC_IDX | REGS_IDX | 00 // + // IDX | IDX | | (3 bits) | (7 bits) | // + // ================================================ // + // // + // For instrumentation : FUNC_IDX = 0b001 // + // // + // REGS_IDX // + // ============================================ // + // Z | Y | X | W // + // (1 bit) | (2 bits) | (3 bits) | (1 bit) // + // ============================================ // + // // + // Z : DIRECT / COHERENCE // + // Y : SUBTYPE ( LOCAL, REMOTE, OTHER ) // + // X : REGISTER INDEX // + // W : HI / LO // + // // + // For configuration: FUNC_IDX = 0b000 // + // // + // REGS_IDX // + // ============================================ // + // RESERVED | X | // + // (4 bits) | (3 bits) | // + // ============================================ // + // // + // X : REGISTER INDEX // + // // + // For WRITE MISS error signaling: FUNC = 0x010 // + // // + // REGS_IDX // + // ============================================ // + // RESERVED | X | // + // (4 bits) | (3 bits) | // + // ============================================ // + // // + // X : REGISTER INDEX // + // // + /////////////////////////////////////////////////////////// + + addr_t addr_lsb = p_vci_tgt.address.read() & + m_config_addr_mask; + + addr_t cell = (addr_lsb / vci_param_int::B); + + size_t regr = cell & + m_config_regr_idx_mask; + + size_t func = (cell >> m_config_regr_width) & + m_config_func_idx_mask; + + bool need_rsp; + int error; + uint32_t rdata = 0; // default value + uint32_t wdata = p_vci_tgt.wdata.read(); + + switch(func) + { + // memory operation + case MEMC_CONFIG: + { + if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) // get lock + and (regr == MEMC_LOCK)) + { + rdata = (uint32_t) r_config_lock.read(); + need_rsp = true; + error = 0; + r_config_lock = true; + } + else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // release lock + and (regr == MEMC_LOCK)) + { + need_rsp = true; + error = 0; + r_config_lock = false; + } + else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_lo + and (regr == MEMC_ADDR_LO)) + { + assert( ((wdata % (m_words * vci_param_int::B)) == 0) and + "VCI_MEM_CACHE CONFIG ERROR: The buffer must be aligned on a cache line"); + + need_rsp = true; + error = 0; + r_config_address = (r_config_address.read() & 0xFFFFFFFF00000000LL) | + ((addr_t)wdata); + } + else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_hi + and (regr == MEMC_ADDR_HI)) + + { + need_rsp = true; + error = 0; + r_config_address = (r_config_address.read() & 0x00000000FFFFFFFFLL) | + (((addr_t) wdata) << 32); + } + else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set buf_lines + and (regr == MEMC_BUF_LENGTH)) + { + need_rsp = true; + error = 0; + size_t lines = wdata / (m_words << 2); + if (wdata % (m_words << 2)) lines++; + r_config_cmd_lines = lines; + r_config_rsp_lines = 0; + } + else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set cmd type + and (regr == MEMC_CMD_TYPE)) + { + need_rsp = false; + error = 0; + r_config_cmd = wdata; + + // prepare delayed response from CONFIG FSM + r_config_srcid = p_vci_tgt.srcid.read(); + r_config_trdid = p_vci_tgt.trdid.read(); + r_config_pktid = p_vci_tgt.pktid.read(); + } + else + { + need_rsp = true; + error = 1; + } + + break; + } + + // instrumentation registers + case MEMC_INSTRM: + { + need_rsp = true; + + if (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) + { + error = read_instrumentation(regr, rdata); + } + else + { + error = 1; + } + + break; + } + + // xram GET bus error registers + case MEMC_RERROR: + { + need_rsp = true; + error = 0; + + if (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) + { + switch (regr) + { + case MEMC_RERROR_IRQ_ENABLE: + r_xram_rsp_rerror_irq_enable = + (p_vci_tgt.wdata.read() != 0); + + break; + + default: + error = 1; + break; + } + } + else if (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) + { + switch (regr) + { + case MEMC_RERROR_SRCID: + rdata = (uint32_t) + r_xram_rsp_rerror_rsrcid.read(); + + break; + + case MEMC_RERROR_ADDR_LO: + rdata = (uint32_t) + (r_xram_rsp_rerror_address.read()) & + ((1ULL<<32)-1); + + break; + + case MEMC_RERROR_ADDR_HI: + rdata = (uint32_t) + (r_xram_rsp_rerror_address.read() >> 32) & + ((1ULL<<32)-1); + + break; + + case MEMC_RERROR_IRQ_RESET: + if (not r_xram_rsp_rerror_irq.read()) break; + + r_xram_rsp_rerror_irq = false; + + break; + + case MEMC_RERROR_IRQ_ENABLE: + rdata = (uint32_t) + (r_xram_rsp_rerror_irq_enable.read()) ? 1 : 0; + + break; + + default: + error = 1; + break; + } + } + else + { + error = 1; + } + + break; + } + + //unknown function + default: + { + need_rsp = true; + error = 1; + + break; + } + } + + if (need_rsp) + { + // blocked if previous pending request to TGT_RSP FSM + if (r_tgt_cmd_to_tgt_rsp_req.read()) break; + + r_tgt_cmd_to_tgt_rsp_srcid = p_vci_tgt.srcid.read(); + r_tgt_cmd_to_tgt_rsp_trdid = p_vci_tgt.trdid.read(); + r_tgt_cmd_to_tgt_rsp_pktid = p_vci_tgt.pktid.read(); + r_tgt_cmd_to_tgt_rsp_req = true; + r_tgt_cmd_to_tgt_rsp_error = error; + r_tgt_cmd_to_tgt_rsp_rdata = rdata; + } + + r_tgt_cmd_fsm = TGT_CMD_IDLE; + +#if DEBUG_MEMC_TGT_CMD + if (m_debug) + std::cout << " Configuration request:" + << " address = " << std::hex << p_vci_tgt.address.read() + << " / func = " << func + << " / regr = " << regr + << " / rdata = " << rdata + << " / wdata = " << p_vci_tgt.wdata.read() + << " / need_rsp = " << need_rsp + << " / error = " << error << std::endl; +#endif + break; + } + ////////////////// + case TGT_CMD_READ: // Push a read request into read fifo + + // check that the read does not cross a cache line limit. + if (((m_x[(addr_t) p_vci_tgt.address.read()] + (p_vci_tgt.plen.read() >> 2)) > 16) and + (p_vci_tgt.cmd.read() != vci_param_int::CMD_LOCKED_READ)) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state" + << " illegal address/plen for VCI read command" << std::endl; + exit(0); + } + // check single flit + if (!p_vci_tgt.eop.read()) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state" + << " read command packet must contain one single flit" << std::endl; + exit(0); + } + // check plen for LL + if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) and + (p_vci_tgt.plen.read() != 8)) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state" + << " ll command packets must have a plen of 8" << std::endl; + exit(0); + } + + if (p_vci_tgt.cmdval and m_cmd_read_addr_fifo.wok()) + { + +#if DEBUG_MEMC_TGT_CMD + if (m_debug) + std::cout << " Push into read_fifo:" + << " address = " << std::hex << p_vci_tgt.address.read() + << " / srcid = " << p_vci_tgt.srcid.read() + << " / trdid = " << p_vci_tgt.trdid.read() + << " / pktid = " << p_vci_tgt.pktid.read() + << " / plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; +#endif + cmd_read_fifo_put = true; + // + if (p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) { + if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_ll_local++; + else m_cpt_ll_remote++; + m_cpt_ll_cost += req_distance(p_vci_tgt.srcid.read()); // LL on a single word + } + else { + if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_read_local++; + else m_cpt_read_remote++; + m_cpt_read_cost += req_distance(p_vci_tgt.srcid.read()); + } + // + r_tgt_cmd_fsm = TGT_CMD_IDLE; + } + break; + + /////////////////// + case TGT_CMD_WRITE: + if (p_vci_tgt.cmdval and m_cmd_write_addr_fifo.wok()) + { + +#if DEBUG_MEMC_TGT_CMD + if (m_debug) + std::cout << " Push into write_fifo:" + << " address = " << std::hex << p_vci_tgt.address.read() + << " / srcid = " << p_vci_tgt.srcid.read() + << " / trdid = " << p_vci_tgt.trdid.read() + << " / pktid = " << p_vci_tgt.pktid.read() + << " / wdata = " << p_vci_tgt.wdata.read() + << " / be = " << p_vci_tgt.be.read() + << " / plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; +#endif + cmd_write_fifo_put = true; + // + if (p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP) { + m_cpt_sc_cost += req_distance(p_vci_tgt.srcid.read()); + } + else { + if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_write_flits_local++; + else m_cpt_write_flits_remote++; + m_cpt_write_cost += req_distance(p_vci_tgt.srcid.read()); + } + // + + if (p_vci_tgt.eop) { + // + if (p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP) { + if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_sc_local++; + else m_cpt_sc_remote++; + + } + else { + if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_write_local++; + else m_cpt_write_remote++; + } + // + r_tgt_cmd_fsm = TGT_CMD_IDLE; + } + } + break; + + ///////////////// + case TGT_CMD_CAS: + if ((p_vci_tgt.plen.read() != 8) and (p_vci_tgt.plen.read() != 16)) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_CAS state" + << "illegal format for CAS command " << std::endl; + exit(0); + } + + if (p_vci_tgt.cmdval and m_cmd_cas_addr_fifo.wok()) + { + +#if DEBUG_MEMC_TGT_CMD + if (m_debug) + std::cout << " Pushing command into cmd_cas_fifo:" + << " address = " << std::hex << p_vci_tgt.address.read() + << " srcid = " << p_vci_tgt.srcid.read() + << " trdid = " << p_vci_tgt.trdid.read() + << " pktid = " << p_vci_tgt.pktid.read() + << " wdata = " << p_vci_tgt.wdata.read() + << " be = " << p_vci_tgt.be.read() + << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; +#endif + cmd_cas_fifo_put = true; + if (p_vci_tgt.eop) { + // + if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_cas_local++; + else m_cpt_cas_remote++; + m_cpt_cas_cost += req_distance(p_vci_tgt.srcid.read()); + // + r_tgt_cmd_fsm = TGT_CMD_IDLE; + } + } + break; + } // end switch tgt_cmd_fsm + + ///////////////////////////////////////////////////////////////////////// + // MULTI_ACK FSM + ///////////////////////////////////////////////////////////////////////// + // This FSM controls the response to the multicast update requests sent + // by the memory cache to the L1 caches and update the UPT. + // + // - The FSM decrements the proper entry in UPT, + // and clear the UPT entry when all responses have been received. + // - If required, it sends a request to the TGT_RSP FSM to complete + // a pending write transaction. + // + // All those multi-ack packets are one flit packet. + // The index in the UPT is defined in the TRDID field. + //////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "multi_ack_fsm" << std::endl; + + switch(r_multi_ack_fsm.read()) + { + //////////////////// + case MULTI_ACK_IDLE: + { + bool multi_ack_fifo_rok = m_cc_receive_to_multi_ack_fifo.rok(); + + // No CC_RECEIVE FSM request and no WRITE FSM request + if (not multi_ack_fifo_rok and not r_write_to_multi_ack_req.read()) + break; + + uint8_t updt_index; + + // handling WRITE FSM request to decrement update table response + // counter if no CC_RECEIVE FSM request + if (not multi_ack_fifo_rok) + { + updt_index = r_write_to_multi_ack_upt_index.read(); + r_write_to_multi_ack_req = false; + } + // Handling CC_RECEIVE FSM request + else + { + uint64_t flit = m_cc_receive_to_multi_ack_fifo.read(); + updt_index = DspinDhccpParam::dspin_get(flit, + DspinDhccpParam::MULTI_ACK_UPDT_INDEX); + + cc_receive_to_multi_ack_fifo_get = true; + } + + assert((updt_index < m_upt.size()) and + "VCI_MEM_CACHE ERROR in MULTI_ACK_IDLE : " + "index too large for UPT"); + + r_multi_ack_upt_index = updt_index; + r_multi_ack_fsm = MULTI_ACK_UPT_LOCK; + +#if DEBUG_MEMC_MULTI_ACK + if (m_debug) + { + if (multi_ack_fifo_rok) + { + std::cout << " Response for UPT entry " + << (size_t)updt_index << std::endl; + } + else + { + std::cout << " Write FSM request to decrement UPT entry " + << updt_index << std::endl; + } + } +#endif + break; + } + + //////////////////////// + case MULTI_ACK_UPT_LOCK: + { + // get lock to the UPDATE table + if (r_alloc_upt_fsm.read() != ALLOC_UPT_MULTI_ACK) break; + + // decrement the number of expected responses + size_t count = 0; + bool valid = m_upt.decrement(r_multi_ack_upt_index.read(), count); + + if (not valid) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() + << " MULTI_ACK_UPT_LOCK state" << std::endl + << "unsuccessful access to decrement the UPT" << std::endl; + exit(0); + } + + if (count == 0) + { + r_multi_ack_fsm = MULTI_ACK_UPT_CLEAR; + } + else + { + r_multi_ack_fsm = MULTI_ACK_IDLE; + } + +#if DEBUG_MEMC_MULTI_ACK + if (m_debug) + std::cout << " Decrement the responses counter for UPT:" + << " entry = " << r_multi_ack_upt_index.read() + << " / rsp_count = " << std::dec << count << std::endl; +#endif + break; + } + + ///////////////////////// + case MULTI_ACK_UPT_CLEAR: // Clear UPT entry / Test if rsp or ack required + { + if (r_alloc_upt_fsm.read() != ALLOC_UPT_MULTI_ACK) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() + << " MULTI_ACK_UPT_CLEAR state" + << " bad UPT allocation" << std::endl; + exit(0); + } + + r_multi_ack_srcid = m_upt.srcid(r_multi_ack_upt_index.read()); + r_multi_ack_trdid = m_upt.trdid(r_multi_ack_upt_index.read()); + r_multi_ack_pktid = m_upt.pktid(r_multi_ack_upt_index.read()); + r_multi_ack_nline = m_upt.nline(r_multi_ack_upt_index.read()); + bool need_rsp = m_upt.need_rsp(r_multi_ack_upt_index.read()); + + // clear the UPT entry + m_upt.clear(r_multi_ack_upt_index.read()); + + if ( need_rsp ) r_multi_ack_fsm = MULTI_ACK_WRITE_RSP; + else r_multi_ack_fsm = MULTI_ACK_IDLE; + +#if DEBUG_MEMC_MULTI_ACK + if (m_debug) + std::cout << " Clear UPT entry " + << std::dec << r_multi_ack_upt_index.read() << std::endl; +#endif + break; + } + ///////////////////////// + case MULTI_ACK_WRITE_RSP: // Post a response request to TGT_RSP FSM + // Wait if pending request + { + if (r_multi_ack_to_tgt_rsp_req.read()) break; + + r_multi_ack_to_tgt_rsp_req = true; + r_multi_ack_to_tgt_rsp_srcid = r_multi_ack_srcid.read(); + r_multi_ack_to_tgt_rsp_trdid = r_multi_ack_trdid.read(); + r_multi_ack_to_tgt_rsp_pktid = r_multi_ack_pktid.read(); + r_multi_ack_fsm = MULTI_ACK_IDLE; + +#if DEBUG_MEMC_MULTI_ACK + if (m_debug) + std::cout << " " + << " Request TGT_RSP FSM to send a response to srcid " + << std::hex << r_multi_ack_srcid.read() << std::endl; +#endif + break; + } + } // end switch r_multi_ack_fsm + + //////////////////////////////////////////////////////////////////////////////////// + // CONFIG FSM + //////////////////////////////////////////////////////////////////////////////////// + // The CONFIG FSM handles the VCI configuration requests (INVAL & SYNC). + // The target buffer can have any size, and there is one single command for + // all cache lines covered by the target buffer. + // + // An INVAL or SYNC configuration operation is defined by the following registers: + // - bool r_config_cmd : INVAL / SYNC / NOP + // - uint64_t r_config_address : buffer base address + // - uint32_t r_config_cmd_lines : number of lines to be handled + // - uint32_t r_config_rsp_lines : number of lines not completed + // + // For both INVAL and SYNC commands, the CONFIG FSM contains the loop handling + // all cache lines covered by the buffer. The various lines of a given buffer + // can be pipelined: the CONFIG FSM does not wait the response for line (n) to send + // the command for line (n+1). It decrements the r_config_cmd_lines counter until + // the last request has been registered in TRT (for a SYNC), or in IVT (for an INVAL). + // The r_config_rsp_lines counter contains the number of expected responses from + // CLEANUP FSM (inval) or from IXR_RSP FSM (sync). This register is incremented by + // the CONFIG FSM (each time a transaction is requested), and decremented by the + // CLEANUP or IXR_RSP FSMs(each time a response is received. As this register can + // be concurently accessed by those three FSMs, it is implemented as an [incr/decr] + // counter. + // + // - INVAL request: + // For each line, it access to the DIR. + // In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. + // In case of hit, with no copies in L1 caches, the line is invalidated and + // a response is requested to TGT_RSP FSM. + // If there is copies, a multi-inval, or a broadcast-inval coherence transaction + // is launched and registered in UPT. The multi-inval transaction completion + // is signaled by the CLEANUP FSM by decrementing the r_config_rsp_lines counter. + // The CONFIG INVAL response is sent only when the last line has been invalidated. + // There is no PUT transaction to XRAM, even if the invalidated line is dirty... + // TODO : The target buffer address must be aligned on a cache line boundary. + // This constraint can be released, but it requires to make 2 PUT transactions + // for the first and the last line... + // + // - SYNC request: + // For each line, it access to the DIR. + // In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. + // In case of hit, a PUT transaction is registered in TRT and a request is sent + // to IXR_CMD FSM. The IXR_RSP FSM decrements the r_config_rsp_lines counter + // when a PUT response is received. + // The CONFIG SYNC response is sent only when the last PUT response is received. + // + // From the software point of view, a configuration request is a sequence + // of 6 atomic accesses in an uncached segment. A dedicated lock is used + // to handle only one configuration command at a given time: + // - Read MEMC_LOCK : Get the lock + // - Write MEMC_ADDR_LO : Set the buffer address LSB + // - Write MEMC_ADDR_HI : Set the buffer address MSB + // - Write MEMC_BUF_LENGTH : set buffer length (bytes) + // - Write MEMC_CMD_TYPE : launch the actual operation + // - WRITE MEMC_LOCK : release the lock + //////////////////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "config_fsm" << std::endl; + + switch( r_config_fsm.read()) + { + ///////////////// + case CONFIG_IDLE: // waiting a config request + { + if (r_config_cmd.read() != MEMC_CMD_NOP ) + { + r_config_fsm = CONFIG_LOOP; + +#if DEBUG_MEMC_CONFIG +if (m_debug) + std::cout << " Config Request received" + << " / address = " << std::hex << r_config_address.read() + << " / lines = " << std::dec << r_config_cmd_lines.read() + << " / type = " << r_config_cmd.read() << std::endl; +#endif + } + break; + } + ///////////////// + case CONFIG_LOOP: // test if last line to be handled + { + if (r_config_cmd_lines.read() == 0 ) + { + r_config_cmd = MEMC_CMD_NOP; + r_config_fsm = CONFIG_WAIT; + } + else + { + r_config_fsm = CONFIG_DIR_REQ; + } + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " " + << " / address = " << std::hex << r_config_address.read() + << " / lines not handled = " << std::dec << r_config_cmd_lines.read() + << " / command = " << r_config_cmd.read() << std::endl; +#endif + break; + } + ///////////////// + case CONFIG_WAIT: // wait completion (last response) + { + if (r_config_rsp_lines.read() == 0 ) // last response received + { + r_config_fsm = CONFIG_RSP; + } + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " " + << " / lines to do = " << std::dec << r_config_rsp_lines.read() << std::endl; +#endif + break; + } + //////////////// + case CONFIG_RSP: // request TGT_RSP FSM to return response + { + if (not r_config_to_tgt_rsp_req.read()) + { + r_config_to_tgt_rsp_srcid = r_config_srcid.read(); + r_config_to_tgt_rsp_trdid = r_config_trdid.read(); + r_config_to_tgt_rsp_pktid = r_config_pktid.read(); + r_config_to_tgt_rsp_error = false; + r_config_to_tgt_rsp_req = true; + r_config_fsm = CONFIG_IDLE; + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " Request TGT_RSP FSM to send response:" + << " error = " << r_config_to_tgt_rsp_error.read() + << " / rsrcid = " << std::hex << r_config_srcid.read() + << " / rtrdid = " << std::hex << r_config_trdid.read() + << " / rpktid = " << std::hex << r_config_pktid.read() << std::endl; +#endif + } + break; + } + //////////////////// + case CONFIG_DIR_REQ: // Request directory lock + { + if (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG ) + { + r_config_fsm = CONFIG_DIR_ACCESS; + } + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " " + << " Request DIR access" << std::endl; +#endif + break; + } + /////////////////////// + case CONFIG_DIR_ACCESS: // Access directory and decode config command + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and + "MEMC ERROR in CONFIG_DIR_ACCESS state: bad DIR allocation"); + + size_t way = 0; + DirectoryEntry entry = m_cache_directory.read(r_config_address.read(), way); + + r_config_dir_way = way; + r_config_dir_copy_inst = entry.owner.inst; + r_config_dir_copy_srcid = entry.owner.srcid; + r_config_dir_is_cnt = entry.is_cnt; + r_config_dir_lock = entry.lock; + r_config_dir_count = entry.count; + r_config_dir_ptr = entry.ptr; + + if (entry.valid and // hit & inval command + (r_config_cmd.read() == MEMC_CMD_INVAL)) + { + r_config_fsm = CONFIG_IVT_LOCK; + } + else if (entry.valid and // hit & sync command + entry.dirty and + (r_config_cmd.read() == MEMC_CMD_SYNC)) + { + r_config_fsm = CONFIG_TRT_LOCK; + } + else // miss : return to LOOP + { + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_address = r_config_address.read() + (m_words<<2); + r_config_fsm = CONFIG_LOOP; + } + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " Accessing directory: " + << " address = " << std::hex << r_config_address.read() + << " / hit = " << std::dec << entry.valid + << " / dirty = " << entry.dirty + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt << std::endl; +#endif + break; + } + ///////////////////// + case CONFIG_TRT_LOCK: // enter this state in case of SYNC command + // to a dirty cache line + // keep DIR lock, and try to get TRT lock + // return to LOOP state if TRT full + // reset dirty bit in DIR and register a PUT + // transaction in TRT if not full. + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and + "MEMC ERROR in CONFIG_TRT_LOCK state: bad DIR allocation"); + + if (r_alloc_trt_fsm.read() == ALLOC_TRT_CONFIG ) + { + size_t index = 0; + bool wok = not m_trt.full(index); + + if (not wok ) + { + r_config_fsm = CONFIG_LOOP; + } + else + { + size_t way = r_config_dir_way.read(); + size_t set = m_y[r_config_address.read()]; + + // reset dirty bit in DIR + DirectoryEntry entry; + entry.valid = true; + entry.dirty = false; + entry.tag = m_z[r_config_address.read()]; + entry.is_cnt = r_config_dir_is_cnt.read(); + entry.lock = r_config_dir_lock.read(); + entry.ptr = r_config_dir_ptr.read(); + entry.count = r_config_dir_count.read(); + entry.owner.inst = r_config_dir_copy_inst.read(); + entry.owner.srcid = r_config_dir_copy_srcid.read(); + m_cache_directory.write( set, way, entry ); + + r_config_trt_index = index; + r_config_fsm = CONFIG_TRT_SET; + } + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " Access TRT: " + << " wok = " << std::dec << wok + << " index = " << index << std::endl; +#endif + } + break; + } + //////////////////// + case CONFIG_TRT_SET: // read data in cache + // and post a PUT request in TRT + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and + "MEMC ERROR in CONFIG_TRT_SET state: bad DIR allocation"); + + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_CONFIG) and + "MEMC ERROR in CONFIG_TRT_SET state: bad TRT allocation"); + + // read data into cache + size_t way = r_config_dir_way.read(); + size_t set = m_y[r_config_address.read()]; + std::vector data_vector; + data_vector.clear(); + for(size_t word=0; word(m_words,0xF), // byte-enable: unused + data_vector, // data to be written + 0, // ll_key: unused + true ); // requested by config FSM + config_rsp_lines_incr = true; + r_config_fsm = CONFIG_PUT_REQ; + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " PUT request in TRT:" + << " address = " << std::hex << r_config_address.read() + << " index = " << std::dec << r_config_trt_index.read() << std::endl; +#endif + break; + } + //////////////////// + case CONFIG_PUT_REQ: // post PUT request to IXR_CMD_FSM + { + if (not r_config_to_ixr_cmd_req.read()) + { + r_config_to_ixr_cmd_req = true; + r_config_to_ixr_cmd_index = r_config_trt_index.read(); + + // prepare next iteration + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_address = r_config_address.read() + (m_words<<2); + r_config_fsm = CONFIG_LOOP; + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " post PUT request to IXR_CMD_FSM" + << " / address = " << std::hex << r_config_address.read() << std::endl; +#endif + } + break; + } + ///////////////////// + case CONFIG_IVT_LOCK: // enter this state in case of INVAL command + // Keep DIR lock and Try to get IVT lock. + // Return to LOOP state if IVT full. + // Register inval in IVT, and invalidate the + // directory if IVT not full. + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and + "MEMC ERROR in CONFIG_IVT_LOCK state: bad DIR allocation"); + + if (r_alloc_ivt_fsm.read() == ALLOC_IVT_CONFIG ) + { + size_t set = m_y[(addr_t)(r_config_address.read())]; + size_t way = r_config_dir_way.read(); + + if (r_config_dir_count.read() == 0 ) // inval DIR and return to LOOP + { + m_cache_directory.inval( way, set ); + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_address = r_config_address.read() + (m_words<<2); + r_config_fsm = CONFIG_LOOP; + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " " + << " No copies in L1 : inval DIR entry" << std::endl; +#endif + } + else // try to register inval in IVT + { + bool wok = false; + size_t index = 0; + bool broadcast = r_config_dir_is_cnt.read(); + size_t srcid = r_config_srcid.read(); + size_t trdid = r_config_trdid.read(); + size_t pktid = r_config_pktid.read(); + addr_t nline = m_nline[(addr_t)(r_config_address.read())]; + size_t nb_copies = r_config_dir_count.read(); + + wok = m_ivt.set( false, // it's an inval transaction + broadcast, + false, // no response required + true, // acknowledge required + srcid, + trdid, + pktid, + nline, + nb_copies, + index ); + + if (wok ) // IVT success => inval DIR slot + { + m_cache_directory.inval( way, set ); + r_config_ivt_index = index; + config_rsp_lines_incr = true; + if (broadcast ) r_config_fsm = CONFIG_BC_SEND; + else r_config_fsm = CONFIG_INVAL_SEND; + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " " + << " Inval DIR entry and register inval in IVT" + << " / index = " << std::dec << index + << " / broadcast = " << broadcast << std::endl; +#endif + } + else // IVT full => release both DIR and IVT locks + { + r_config_fsm = CONFIG_LOOP; + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " " + << " IVT full : release DIR & IVT locks and retry" << std::endl; +#endif + } + } + } + break; + } + //////////////////// + case CONFIG_BC_SEND: // Post a broadcast inval request to CC_SEND FSM + { + if (not r_config_to_cc_send_multi_req.read() and + not r_config_to_cc_send_brdcast_req.read()) + { + // post bc inval request + r_config_to_cc_send_multi_req = false; + r_config_to_cc_send_brdcast_req = true; + r_config_to_cc_send_trdid = r_config_ivt_index.read(); + r_config_to_cc_send_nline = m_nline[(addr_t)(r_config_address.read())]; + + // prepare next iteration + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_address = r_config_address.read() + (m_words << 2); + r_config_fsm = CONFIG_LOOP; + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " " + << " Post a broadcast inval request to CC_SEND FSM" + << " / address = " << r_config_address.read() <" + << " Post multi inval request to CC_SEND FSM" + << " / address = " << std::hex << r_config_address.read() + << " / copy = " << r_config_dir_copy_srcid.read() + << " / inst = " << std::dec << r_config_dir_copy_inst.read() << std::endl; +#endif + } + break; + } + ///////////////////// + case CONFIG_HEAP_REQ: // Try to get access to Heap + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_CONFIG ) + { + r_config_fsm = CONFIG_HEAP_SCAN; + r_config_heap_next = r_config_dir_ptr.read(); + } + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " " + << " Requesting HEAP lock" << std::endl; +#endif + break; + } + ////////////////////// + case CONFIG_HEAP_SCAN: // scan HEAP and send inval to CC_SEND FSM + { + HeapEntry entry = m_heap.read( r_config_heap_next.read()); + bool last_copy = (entry.next == r_config_heap_next.read()); + + config_to_cc_send_fifo_srcid = entry.owner.srcid; + config_to_cc_send_fifo_inst = entry.owner.inst; + // config_to_cc_send_fifo_last = last_copy; + config_to_cc_send_fifo_put = true; + + if (m_config_to_cc_send_inst_fifo.wok()) // inval request accepted + { + r_config_heap_next = entry.next; + if (last_copy ) r_config_fsm = CONFIG_HEAP_LAST; + } + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " " + << " Post multi inval request to CC_SEND FSM" + << " / address = " << std::hex << r_config_address.read() + << " / copy = " << entry.owner.srcid + << " / inst = " << std::dec << entry.owner.inst << std::endl; +#endif + break; + } + ////////////////////// + case CONFIG_HEAP_LAST: // HEAP housekeeping + { + size_t free_pointer = m_heap.next_free_ptr(); + HeapEntry last_entry; + last_entry.owner.srcid = 0; + last_entry.owner.inst = false; + + if (m_heap.is_full()) + { + last_entry.next = r_config_dir_ptr.read(); + m_heap.unset_full(); + } + else + { + last_entry.next = free_pointer; + } + + m_heap.write_free_ptr( r_config_dir_ptr.read()); + m_heap.write( r_config_heap_next.read(), last_entry ); + + // prepare next iteration + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_address = r_config_address.read() + (m_words<<2); + r_config_fsm = CONFIG_LOOP; + +#if DEBUG_MEMC_CONFIG +if (m_debug) +std::cout << " " + << " Heap housekeeping" << std::endl; +#endif + break; + } + } // end switch r_config_fsm + + + + //////////////////////////////////////////////////////////////////////////////////// + // READ FSM + //////////////////////////////////////////////////////////////////////////////////// + // The READ FSM controls the VCI read and ll requests. + // It takes the lock protecting the cache directory to check the cache line status: + // - In case of HIT + // The fsm copies the data (one line, or one single word) + // in the r_read_to_tgt_rsp buffer. It waits if this buffer is not empty. + // The requesting initiator is registered in the cache directory. + // If the number of copy is larger than 1, the new copy is registered + // in the HEAP. + // If the number of copy is larger than the threshold, the HEAP is cleared, + // and the corresponding line switches to the counter mode. + // - In case of MISS + // The READ fsm takes the lock protecting the transaction tab. + // If a read transaction to the XRAM for this line already exists, + // or if the transaction tab is full, the fsm is stalled. + // If a TRT entry is free, the READ request is registered in TRT, + // it is consumed in the request FIFO, and transmited to the IXR_CMD FSM. + // The READ FSM returns in the IDLE state as the read transaction will be + // completed when the missing line will be received. + //////////////////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "read_fsm" << std::endl; + + switch(r_read_fsm.read()) + { + /////////////// + case READ_IDLE: // waiting a read request + { + if (m_cmd_read_addr_fifo.rok()) + { + +#if DEBUG_MEMC_READ + if (m_debug) + std::cout << " Read request" + << " : address = " << std::hex << m_cmd_read_addr_fifo.read() + << " / srcid = " << m_cmd_read_srcid_fifo.read() + << " / trdid = " << m_cmd_read_trdid_fifo.read() + << " / pktid = " << m_cmd_read_pktid_fifo.read() + << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; +#endif + r_read_fsm = READ_DIR_REQ; + } + break; + } + ////////////////// + case READ_DIR_REQ: // Get the lock to the directory + { + if (r_alloc_dir_fsm.read() == ALLOC_DIR_READ) + { + r_read_fsm = READ_DIR_LOCK; + } + +#if DEBUG_MEMC_READ + if (m_debug) + std::cout << " Requesting DIR lock " << std::endl; +#endif + break; + } + + /////////////////// + case READ_DIR_LOCK: // check directory for hit / miss + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_READ) and + "MEMC ERROR in READ_DIR_LOCK state: Bad DIR allocation"); + + size_t way = 0; + DirectoryEntry entry = m_cache_directory.read(m_cmd_read_addr_fifo.read(), way); + + // access the global table ONLY when we have an LL cmd + if ((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) + { + r_read_ll_key = m_llsc_table.ll(m_cmd_read_addr_fifo.read()); + } + r_read_is_cnt = entry.is_cnt; + r_read_dirty = entry.dirty; + r_read_lock = entry.lock; + r_read_tag = entry.tag; + r_read_way = way; + r_read_count = entry.count; + r_read_copy = entry.owner.srcid; + r_read_copy_inst = entry.owner.inst; + r_read_ptr = entry.ptr; // pointer to the heap + + // check if this is a cached read, this means pktid is either + // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding + // TYPE_READ_INS_MISS 0bX011 with TSAR encoding + bool cached_read = (m_cmd_read_pktid_fifo.read() & 0x1); + if (entry.valid) // hit + { + // test if we need to register a new copy in the heap + if (entry.is_cnt or (entry.count == 0) or !cached_read) + { + r_read_fsm = READ_DIR_HIT; + } + else + { + r_read_fsm = READ_HEAP_REQ; + } + } + else // miss + { + r_read_fsm = READ_TRT_LOCK; + } + +#if DEBUG_MEMC_READ + if (m_debug) + { + std::cout << " Accessing directory: " + << " address = " << std::hex << m_cmd_read_addr_fifo.read() + << " / hit = " << std::dec << entry.valid + << " / count = " < we must update the copies + { + if (!is_cnt) // Not counter mode + { + entry.owner.srcid = m_cmd_read_srcid_fifo.read(); + entry.owner.inst = inst_read; + entry.count = r_read_count.read() + 1; + } + else // Counter mode + { + entry.owner.srcid = 0; + entry.owner.inst = false; + entry.count = r_read_count.read() + 1; + } + } + else // Uncached read + { + entry.owner.srcid = r_read_copy.read(); + entry.owner.inst = r_read_copy_inst.read(); + entry.count = r_read_count.read(); + } + +#if DEBUG_MEMC_READ + if (m_debug) + std::cout << " Update directory entry:" + << " addr = " << std::hex << m_cmd_read_addr_fifo.read() + << " / set = " << std::dec << set + << " / way = " << way + << " / owner_id = " << std::hex << entry.owner.srcid + << " / owner_ins = " << std::dec << entry.owner.inst + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt << std::endl; +#endif + m_cache_directory.write(set, way, entry); + r_read_fsm = READ_RSP; + break; + } + /////////////////// + case READ_HEAP_REQ: // Get the lock to the HEAP directory + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) + { + r_read_fsm = READ_HEAP_LOCK; + } + +#if DEBUG_MEMC_READ + if (m_debug) + std::cout << " " + << " Requesting HEAP lock " << std::endl; +#endif + break; + } + + //////////////////// + case READ_HEAP_LOCK: // read data in cache, update the directory + // and prepare the HEAP update + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) + { + // enter counter mode when we reach the limit of copies or the heap is full + bool go_cnt = (r_read_count.read() >= m_max_copies) or m_heap.is_full(); + + // read data in the cache + size_t set = m_y[(addr_t)(m_cmd_read_addr_fifo.read())]; + size_t way = r_read_way.read(); + + m_cache_data.read_line(way, set, r_read_data); + + // update the cache directory + DirectoryEntry entry; + entry.valid = true; + entry.is_cnt = go_cnt; + entry.dirty = r_read_dirty.read(); + entry.tag = r_read_tag.read(); + entry.lock = r_read_lock.read(); + entry.count = r_read_count.read() + 1; + + if (not go_cnt) // Not entering counter mode + { + entry.owner.srcid = r_read_copy.read(); + entry.owner.inst = r_read_copy_inst.read(); + entry.ptr = m_heap.next_free_ptr(); // set pointer on the heap + } + else // Entering Counter mode + { + entry.owner.srcid = 0; + entry.owner.inst = false; + entry.ptr = 0; + } + + m_cache_directory.write(set, way, entry); + + // prepare the heap update (add an entry, or clear the linked list) + if (not go_cnt) // not switching to counter mode + { + // We test if the next free entry in the heap is the last + HeapEntry heap_entry = m_heap.next_free_entry(); + r_read_next_ptr = heap_entry.next; + r_read_last_free = (heap_entry.next == m_heap.next_free_ptr()); + + r_read_fsm = READ_HEAP_WRITE; // add an entry in the HEAP + } + else // switching to counter mode + { + if (r_read_count.read() >1) // heap must be cleared + { + HeapEntry next_entry = m_heap.read(r_read_ptr.read()); + r_read_next_ptr = m_heap.next_free_ptr(); + m_heap.write_free_ptr(r_read_ptr.read()); + + if (next_entry.next == r_read_ptr.read()) // last entry + { + r_read_fsm = READ_HEAP_LAST; // erase the entry + } + else // not the last entry + { + r_read_ptr = next_entry.next; + r_read_fsm = READ_HEAP_ERASE; // erase the list + } + } + else // the heap is not used / nothing to do + { + r_read_fsm = READ_RSP; + } + } + +#if DEBUG_MEMC_READ + if (m_debug) + std::cout << " Update directory:" + << " tag = " << std::hex << entry.tag + << " set = " << std::dec << set + << " way = " << way + << " count = " << entry.count + << " is_cnt = " << entry.is_cnt << std::endl; +#endif + } + else + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_LOCK" + << "Bad HEAP allocation" << std::endl; + exit(0); + } + break; + } + ///////////////////// + case READ_HEAP_WRITE: // add an entry in the heap + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) + { + HeapEntry heap_entry; + heap_entry.owner.srcid = m_cmd_read_srcid_fifo.read(); + heap_entry.owner.inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); + + if (r_read_count.read() == 1) // creation of a new linked list + { + heap_entry.next = m_heap.next_free_ptr(); + } + else // head insertion in existing list + { + heap_entry.next = r_read_ptr.read(); + } + m_heap.write_free_entry(heap_entry); + m_heap.write_free_ptr(r_read_next_ptr.read()); + if (r_read_last_free.read()) m_heap.set_full(); + + r_read_fsm = READ_RSP; + +#if DEBUG_MEMC_READ + if (m_debug) + std::cout << " Add an entry in the heap:" + << " owner_id = " << std::hex << heap_entry.owner.srcid + << " owner_ins = " << std::dec << heap_entry.owner.inst << std::endl; +#endif + } + else + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_WRITE" + << "Bad HEAP allocation" << std::endl; + exit(0); + } + break; + } + ///////////////////// + case READ_HEAP_ERASE: + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) + { + HeapEntry next_entry = m_heap.read(r_read_ptr.read()); + if (next_entry.next == r_read_ptr.read()) + { + r_read_fsm = READ_HEAP_LAST; + } + else + { + r_read_ptr = next_entry.next; + r_read_fsm = READ_HEAP_ERASE; + } + } + else + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_ERASE" + << "Bad HEAP allocation" << std::endl; + exit(0); + } + break; + } + + //////////////////// + case READ_HEAP_LAST: + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) + { + HeapEntry last_entry; + last_entry.owner.srcid = 0; + last_entry.owner.inst = false; + + if (m_heap.is_full()) + { + last_entry.next = r_read_ptr.read(); + m_heap.unset_full(); + } + else + { + last_entry.next = r_read_next_ptr.read(); + } + m_heap.write(r_read_ptr.read(),last_entry); + r_read_fsm = READ_RSP; + } + else + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_LAST" + << "Bad HEAP allocation" << std::endl; + exit(0); + } + break; + } + ////////////// + case READ_RSP: // request the TGT_RSP FSM to return data + { + if (!r_read_to_tgt_rsp_req) + { + for(size_t i=0 ; i Request TGT_RSP FSM to return data:" + << " rsrcid = " << std::hex << m_cmd_read_srcid_fifo.read() + << " / address = " << std::hex << m_cmd_read_addr_fifo.read() + << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; +#endif + } + break; + } + /////////////////// + case READ_TRT_LOCK: // read miss : check the Transaction Table + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_READ) + { + size_t index = 0; + addr_t addr = (addr_t) m_cmd_read_addr_fifo.read(); + bool hit_read = m_trt.hit_read(m_nline[addr], index); + bool hit_write = m_trt.hit_write(m_nline[addr]); + bool wok = not m_trt.full(index); + + if (hit_read or !wok or hit_write) // line already requested or no space + { + if (!wok) m_cpt_trt_full++; + if (hit_read or hit_write) m_cpt_trt_rb++; + r_read_fsm = READ_IDLE; + } + else // missing line is requested to the XRAM + { + m_cpt_read_miss++; + r_read_trt_index = index; + r_read_fsm = READ_TRT_SET; + } + +#if DEBUG_MEMC_READ + if (m_debug) + std::cout << " Check TRT:" + << " hit_read = " << hit_read + << " / hit_write = " << hit_write + << " / full = " << !wok << std::endl; +#endif + } + break; + } + ////////////////// + case READ_TRT_SET: // register get transaction in TRT + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_READ) + { + m_trt.set( r_read_trt_index.read(), + true, // GET + m_nline[(addr_t)(m_cmd_read_addr_fifo.read())], + m_cmd_read_srcid_fifo.read(), + m_cmd_read_trdid_fifo.read(), + m_cmd_read_pktid_fifo.read(), + true, // proc read + m_cmd_read_length_fifo.read(), + m_x[(addr_t)(m_cmd_read_addr_fifo.read())], + std::vector (m_words,0), + std::vector (m_words,0), + r_read_ll_key.read()); +#if DEBUG_MEMC_READ + if (m_debug) + std::cout << " Set a GET in TRT:" + << " address = " << std::hex << m_cmd_read_addr_fifo.read() + << " / srcid = " << std::hex << m_cmd_read_srcid_fifo.read() << std::endl; +#endif + r_read_fsm = READ_TRT_REQ; + } + break; + } + + ////////////////// + case READ_TRT_REQ: // consume the read request in FIFO and send it to IXR_CMD_FSM + { + if (not r_read_to_ixr_cmd_req) + { + cmd_read_fifo_get = true; + r_read_to_ixr_cmd_req = true; + r_read_to_ixr_cmd_index = r_read_trt_index.read(); + r_read_fsm = READ_IDLE; + +#if DEBUG_MEMC_READ + if (m_debug) + std::cout << " Request GET transaction for address " + << std::hex << m_cmd_read_addr_fifo.read() << std::endl; +#endif + } + break; + } + } // end switch read_fsm + + /////////////////////////////////////////////////////////////////////////////////// + // WRITE FSM + /////////////////////////////////////////////////////////////////////////////////// + // The WRITE FSM handles the write bursts and sc requests sent by the processors. + // All addresses in a burst must be in the same cache line. + // A complete write burst is consumed in the FIFO & copied to a local buffer. + // Then the FSM takes the lock protecting the cache directory, to check + // if the line is in the cache. + // + // - In case of HIT, the cache is updated. + // If there is no other copy, an acknowledge response is immediately + // returned to the writing processor. + // If the data is cached by other processors, a coherence transaction must + // be launched (sc requests always require a coherence transaction): + // It is a multicast update if the line is not in counter mode: the processor + // takes the lock protecting the Update Table (UPT) to register this transaction. + // If the UPT is full, it releases the lock(s) and retry. Then, it sends + // a multi-update request to all owners of the line (but the writer), + // through the CC_SEND FSM. In case of coherence transaction, the WRITE FSM + // does not respond to the writing processor, as this response will be sent by + // the MULTI_ACK FSM when all update responses have been received. + // It is a broadcast invalidate if the line is in counter mode: The line + // should be erased in memory cache, and written in XRAM with a PUT transaction, + // after registration in TRT. + // + // - In case of MISS, the WRITE FSM takes the lock protecting the transaction + // table (TRT). If a read transaction to the XRAM for this line already exists, + // it writes in the TRT (write buffer). Otherwise, if a TRT entry is free, + // the WRITE FSM register a new transaction in TRT, and sends a GET request + // to the XRAM. If the TRT is full, it releases the lock, and waits. + // Finally, the WRITE FSM returns an aknowledge response to the writing processor. + ///////////////////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "write_fsm" << std::endl; + + switch(r_write_fsm.read()) + { + //////////////// + case WRITE_IDLE: // copy first word of a write burst in local buffer + { + if (not m_cmd_write_addr_fifo.rok()) break; + + // consume a word in the FIFO & write it in the local buffer + cmd_write_fifo_get = true; + size_t index = m_x[(addr_t)(m_cmd_write_addr_fifo.read())]; + + r_write_address = (addr_t)(m_cmd_write_addr_fifo.read()); + r_write_word_index = index; + r_write_word_count = 0; + r_write_data[index] = m_cmd_write_data_fifo.read(); + r_write_srcid = m_cmd_write_srcid_fifo.read(); + r_write_trdid = m_cmd_write_trdid_fifo.read(); + r_write_pktid = m_cmd_write_pktid_fifo.read(); + + // if SC command, get the SC key + if ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC) + { + assert( not m_cmd_write_eop_fifo.read() && + "MEMC ERROR in WRITE_IDLE state: " + "invalid packet format for SC command"); + + r_write_sc_key = m_cmd_write_data_fifo.read(); + } + + // initialize the be field for all words + for(size_t word=0 ; word Write request " + << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read() + << " / address = " << std::hex << m_cmd_write_addr_fifo.read() + << " / data = " << m_cmd_write_data_fifo.read() << std::endl; +#endif + break; + } + //////////////// + case WRITE_NEXT: // copy next word of a write burst in local buffer + { + if (not m_cmd_write_addr_fifo.rok()) break; + + // check that the next word is in the same cache line + assert((m_nline[(addr_t)(r_write_address.read())] == + m_nline[(addr_t)(m_cmd_write_addr_fifo.read())]) && + "MEMC ERROR in WRITE_NEXT state: Illegal write burst"); + + size_t index = m_x[(addr_t)(m_cmd_write_addr_fifo.read())]; + bool is_sc = ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC); + + // check that SC command has constant address + assert((not is_sc or (index == r_write_word_index)) && + "MEMC ERROR in WRITE_NEXT state: " + "the address must be constant on a SC command"); + + // check that SC command has two flits + assert((not is_sc or m_cmd_write_eop_fifo.read()) && + "MEMC ERROR in WRITE_NEXT state: " + "invalid packet format for SC command"); + + // consume a word in the FIFO & write it in the local buffer + cmd_write_fifo_get = true; + + r_write_be[index] = m_cmd_write_be_fifo.read(); + r_write_data[index] = m_cmd_write_data_fifo.read(); + + // the first flit of a SC command is the reservation key and + // therefore it must not be counted as a data to write + if (not is_sc) + { + r_write_word_count = r_write_word_count.read() + 1; + } + + if (m_cmd_write_eop_fifo.read()) r_write_fsm = WRITE_DIR_REQ; + +#if DEBUG_MEMC_WRITE + if (m_debug) + std::cout << " Write another word in local buffer" + << std::endl; +#endif + break; + } + /////////////////// + case WRITE_DIR_REQ: // Get the lock to the directory + // and access the llsc_global_table + { + if (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE ) break; + + if ((r_write_pktid.read() & 0x7) == TYPE_SC) + { + // test address and key match of the SC command on the + // LL/SC table without removing reservation. The reservation + // will be erased after in this FSM. + bool sc_success = m_llsc_table.check(r_write_address.read(), + r_write_sc_key.read()); + + r_write_sc_fail = not sc_success; + + if (not sc_success) r_write_fsm = WRITE_RSP; + else r_write_fsm = WRITE_DIR_LOCK; + } + else + { + // write burst +#define L2 soclib::common::uint32_log2 + addr_t min = r_write_address.read(); + addr_t max = r_write_address.read() + + (r_write_word_count.read() << L2(vci_param_int::B)); +#undef L2 + + m_llsc_table.sw(min, max); + + r_write_fsm = WRITE_DIR_LOCK; + } + +#if DEBUG_MEMC_WRITE + if (m_debug) + std::cout << " Requesting DIR lock " + << std::endl; +#endif + break; + } + //////////////////// + case WRITE_DIR_LOCK: // access directory to check hit/miss + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and + "MEMC ERROR in ALLOC_DIR_LOCK state: Bad DIR allocation"); + + size_t way = 0; + DirectoryEntry entry(m_cache_directory.read(r_write_address.read(), way)); + + if (entry.valid) // hit + { + // copy directory entry in local buffer in case of hit + r_write_is_cnt = entry.is_cnt; + r_write_lock = entry.lock; + r_write_tag = entry.tag; + r_write_copy = entry.owner.srcid; + r_write_copy_inst = entry.owner.inst; + r_write_count = entry.count; + r_write_ptr = entry.ptr; + r_write_way = way; + + if (entry.is_cnt and entry.count) r_write_fsm = WRITE_BC_DIR_READ; + else r_write_fsm = WRITE_DIR_HIT; + } + else // miss + { + r_write_fsm = WRITE_MISS_TRT_LOCK; + } + +#if DEBUG_MEMC_WRITE + if (m_debug) + { + std::cout << " Check the directory: " + << " address = " << std::hex << r_write_address.read() + << " / hit = " << std::dec << entry.valid + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt ; + if ((r_write_pktid.read() & 0x7) == TYPE_SC) + std::cout << " / SC access" << std::endl; + else + std::cout << " / SW access" << std::endl; + } +#endif + break; + } + /////////////////// + case WRITE_DIR_HIT: // update the cache directory with Dirty bit + // and update data cache + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and + "MEMC ERROR in ALLOC_DIR_HIT state: Bad DIR allocation"); + + DirectoryEntry entry; + entry.valid = true; + entry.dirty = true; + entry.tag = r_write_tag.read(); + entry.is_cnt = r_write_is_cnt.read(); + entry.lock = r_write_lock.read(); + entry.owner.srcid = r_write_copy.read(); + entry.owner.inst = r_write_copy_inst.read(); + entry.count = r_write_count.read(); + entry.ptr = r_write_ptr.read(); + + size_t set = m_y[(addr_t)(r_write_address.read())]; + size_t way = r_write_way.read(); + + // update directory + m_cache_directory.write(set, way, entry); + + // owner is true when the the first registered copy is the writer itself + bool owner = ( (r_write_copy.read() == r_write_srcid.read()) + and not r_write_copy_inst.read()); + + // no_update is true when there is no need for coherence transaction + bool no_update = ( (r_write_count.read() == 0) or + (owner and (r_write_count.read() == 1) and + ((r_write_pktid.read() & 0x7) != TYPE_SC))); + + // write data in the cache if no coherence transaction + if (no_update) + { + // SC command but zero copies + if ((r_write_pktid.read() & 0x7) == TYPE_SC) + { + m_llsc_table.sc(r_write_address.read(), + r_write_sc_key.read()); + } + + for(size_t word=0 ; word Write into cache / No coherence transaction" << std::endl; + } + else + { + std::cout << " Coherence update required:" + << " is_cnt = " << r_write_is_cnt.read() + << " nb_copies = " << std::dec << r_write_count.read() << std::endl; + if (owner) std::cout << " ... but the first copy is the writer" << std::endl; + } + } +#endif + break; + } + //////////////////// + case WRITE_UPT_LOCK: // Try to register the update request in UPT + { + if (r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE) + { + bool wok = false; + size_t index = 0; + size_t srcid = r_write_srcid.read(); + size_t trdid = r_write_trdid.read(); + size_t pktid = r_write_pktid.read(); + addr_t nline = m_nline[(addr_t)(r_write_address.read())]; + size_t nb_copies = r_write_count.read(); + size_t set = m_y[(addr_t)(r_write_address.read())]; + size_t way = r_write_way.read(); + + wok = m_upt.set( true, // it's an update transaction + false, // it's not a broadcast + true, // response required + false, // no acknowledge required + srcid, + trdid, + pktid, + nline, + nb_copies, + index); + + if (wok ) // write data in cache + { + + if ((r_write_pktid.read() & 0x7) == TYPE_SC) + { + m_llsc_table.sc(r_write_address.read(), + r_write_sc_key.read()); + } + + for(size_t word=0 ; word Register the multicast update in UPT / " + << " nb_copies = " << r_write_count.read() << std::endl; + } +#endif + r_write_upt_index = index; + // releases the lock protecting UPT and the DIR if no entry... + if (wok) r_write_fsm = WRITE_UPT_HEAP_LOCK; + else r_write_fsm = WRITE_WAIT; + } + break; + } + + ///////////////////////// + case WRITE_UPT_HEAP_LOCK: // get access to heap + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE) + { + +#if DEBUG_MEMC_WRITE + if (m_debug) + std::cout << " Get acces to the HEAP" << std::endl; +#endif + r_write_fsm = WRITE_UPT_REQ; + } + break; + } + + ////////////////// + case WRITE_UPT_REQ: // prepare the coherence transaction for the CC_SEND FSM + // and write the first copy in the FIFO + // send the request if only one copy + { + assert(not r_write_to_cc_send_multi_req.read() and + not r_write_to_cc_send_brdcast_req.read() and + "Error in VCI_MEM_CACHE : pending multicast or broadcast\n" + "transaction in WRITE_UPT_REQ state" + ); + + r_write_to_cc_send_brdcast_req = false; + r_write_to_cc_send_trdid = r_write_upt_index.read(); + r_write_to_cc_send_nline = m_nline[(addr_t)(r_write_address.read())]; + r_write_to_cc_send_index = r_write_word_index.read(); + r_write_to_cc_send_count = r_write_word_count.read(); + + for(size_t i=0; i Post first request to CC_SEND FSM" + << " / srcid = " << std::dec << r_write_copy.read() + << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; + + if (r_write_count.read() == 1) + std::cout << " ... and this is the last" << std::endl; + } +#endif + break; + } + + /////////////////// + case WRITE_UPT_NEXT: + { + // continue the multi-update request to CC_SEND fsm + // when there is copies in the heap. + // if one copy in the heap is the writer itself + // the corresponding SRCID should not be written in the fifo, + // but the UPT counter must be decremented. + // As this decrement is done in the WRITE_UPT_DEC state, + // after the last copy has been found, the decrement request + // must be registered in the r_write_to_dec flip-flop. + + HeapEntry entry = m_heap.read(r_write_ptr.read()); + + bool dec_upt_counter; + + // put the next srcid in the fifo + if ((entry.owner.srcid != r_write_srcid.read()) or + ((r_write_pktid.read() & 0x7) == TYPE_SC) or + entry.owner.inst) + { + dec_upt_counter = false; + write_to_cc_send_fifo_put = true; + write_to_cc_send_fifo_inst = entry.owner.inst; + write_to_cc_send_fifo_srcid = entry.owner.srcid; + +#if DEBUG_MEMC_WRITE + if (m_debug) + { + std::cout << " Post another request to CC_SEND FSM" + << " / heap_index = " << std::dec << r_write_ptr.read() + << " / srcid = " << std::dec << r_write_copy.read() + << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; + if (entry.next == r_write_ptr.read()) + std::cout << " ... and this is the last" << std::endl; + } +#endif + } + else // the UPT counter must be decremented + { + dec_upt_counter = true; + +#if DEBUG_MEMC_WRITE + if (m_debug) + { + std::cout << " Skip one entry in heap matching the writer" + << " / heap_index = " << std::dec << r_write_ptr.read() + << " / srcid = " << std::dec << r_write_copy.read() + << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; + if (entry.next == r_write_ptr.read()) + std::cout << " ... and this is the last" << std::endl; + } +#endif + } + + // register the possible UPT decrement request + r_write_to_dec = dec_upt_counter or r_write_to_dec.read(); + + if (not m_write_to_cc_send_inst_fifo.wok()) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_UPT_NEXT state" << std::endl + << "The write_to_cc_send_fifo should not be full" << std::endl + << "as the depth should be larger than the max number of copies" << std::endl; + exit(0); + } + + r_write_ptr = entry.next; + + if (entry.next == r_write_ptr.read()) // last copy + { + r_write_to_cc_send_multi_req = true; + if (r_write_to_dec.read() or dec_upt_counter) r_write_fsm = WRITE_UPT_DEC; + else r_write_fsm = WRITE_IDLE; + } + break; + } + + ////////////////// + case WRITE_UPT_DEC: + { + // If the initial writer has a copy, it should not + // receive an update request, but the counter in the + // update table must be decremented by the MULTI_ACK FSM. + + if (!r_write_to_multi_ack_req.read()) + { + r_write_to_multi_ack_req = true; + r_write_to_multi_ack_upt_index = r_write_upt_index.read(); + r_write_fsm = WRITE_IDLE; + } + break; + } + + /////////////// + case WRITE_RSP: // Post a request to TGT_RSP FSM to acknowledge the write + // In order to increase the Write requests throughput, + // we don't wait to return in the IDLE state to consume + // a new request in the write FIFO + { + if (not r_write_to_tgt_rsp_req.read()) + { + // post the request to TGT_RSP_FSM + r_write_to_tgt_rsp_req = true; + r_write_to_tgt_rsp_srcid = r_write_srcid.read(); + r_write_to_tgt_rsp_trdid = r_write_trdid.read(); + r_write_to_tgt_rsp_pktid = r_write_pktid.read(); + r_write_to_tgt_rsp_sc_fail = r_write_sc_fail.read(); + + // try to get a new write request from the FIFO + if (not m_cmd_write_addr_fifo.rok()) + { + r_write_fsm = WRITE_IDLE; + } + else + { + // consume a word in the FIFO & write it in the local buffer + cmd_write_fifo_get = true; + size_t index = m_x[(addr_t) (m_cmd_write_addr_fifo.read())]; + + r_write_address = (addr_t) (m_cmd_write_addr_fifo.read()); + r_write_word_index = index; + r_write_word_count = 0; + r_write_data[index] = m_cmd_write_data_fifo.read(); + r_write_srcid = m_cmd_write_srcid_fifo.read(); + r_write_trdid = m_cmd_write_trdid_fifo.read(); + r_write_pktid = m_cmd_write_pktid_fifo.read(); + + // if SC command, get the SC key + if ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC) + { + assert( not m_cmd_write_eop_fifo.read() && + "MEMC ERROR in WRITE_RSP state: " + "invalid packet format for SC command"); + + r_write_sc_key = m_cmd_write_data_fifo.read(); + } + + // initialize the be field for all words + for(size_t word=0 ; word Post a request to TGT_RSP FSM" + << " : rsrcid = " << std::hex << r_write_srcid.read() << std::endl; + if (m_cmd_write_addr_fifo.rok()) + { + std::cout << " New Write request: " + << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read() + << " / address = " << m_cmd_write_addr_fifo.read() + << " / data = " << m_cmd_write_data_fifo.read() << std::endl; + } + } +#endif + } + break; + } + + ///////////////////////// + case WRITE_MISS_TRT_LOCK: // Miss : check Transaction Table + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) + { + +#if DEBUG_MEMC_WRITE + if (m_debug) + std::cout << " Check the TRT" << std::endl; +#endif + size_t hit_index = 0; + size_t wok_index = 0; + addr_t addr = (addr_t) r_write_address.read(); + bool hit_read = m_trt.hit_read(m_nline[addr], hit_index); + bool hit_write = m_trt.hit_write(m_nline[addr]); + bool wok = not m_trt.full(wok_index); + + // wait an empty entry in TRT + if(not hit_read and (not wok or hit_write)) + { + r_write_fsm = WRITE_WAIT; + m_cpt_trt_full++; + + break; + } + + if ((r_write_pktid.read() & 0x7) == TYPE_SC) + { + m_llsc_table.sc(r_write_address.read(), + r_write_sc_key.read()); + } + + // register the modified data in TRT + if (hit_read) + { + r_write_trt_index = hit_index; + r_write_fsm = WRITE_MISS_TRT_DATA; + m_cpt_write_miss++; + break; + } + + // set a new entry in TRT + if (wok and not hit_write) + { + r_write_trt_index = wok_index; + r_write_fsm = WRITE_MISS_TRT_SET; + m_cpt_write_miss++; + break; + } + + assert(false && "VCI_MEM_CACHE ERROR: this part must not be reached"); + } + break; + } + + //////////////// + case WRITE_WAIT: // release the locks protecting the shared ressources + { + +#if DEBUG_MEMC_WRITE + if (m_debug) + std::cout << " Releases the locks before retry" << std::endl; +#endif + r_write_fsm = WRITE_DIR_REQ; + break; + } + + //////////////////////// + case WRITE_MISS_TRT_SET: // register a new transaction in TRT (Write Buffer) + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) + { + std::vector be_vector; + std::vector data_vector; + be_vector.clear(); + data_vector.clear(); + for(size_t i=0; i Set a new entry in TRT" << std::endl; +#endif + } + break; + } + + ///////////////////////// + case WRITE_MISS_TRT_DATA: // update an entry in TRT (used as a Write Buffer) + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) + { + std::vector be_vector; + std::vector data_vector; + be_vector.clear(); + data_vector.clear(); + for(size_t i=0; i Modify an existing entry in TRT" << std::endl; +#endif + } + break; + } + ///////////////////////// + case WRITE_MISS_XRAM_REQ: // send a GET request to IXR_CMD FSM + { + if (not r_write_to_ixr_cmd_req.read()) + { + r_write_to_ixr_cmd_req = true; + r_write_to_ixr_cmd_index = r_write_trt_index.read(); + r_write_fsm = WRITE_RSP; + +#if DEBUG_MEMC_WRITE + if (m_debug) + std::cout << " Post a GET request to the" + << " IXR_CMD FSM" << std::endl; +#endif + } + break; + } + /////////////////////// + case WRITE_BC_DIR_READ: // enter this state if a broadcast-inval is required + // the cache line must be erased in mem-cache, and written + // into XRAM. + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and + "MEMC ERROR in WRITE_BC_DIR_READ state: Bad DIR allocation"); + + // write enable signal for data buffer. + r_write_bc_data_we = true; + + r_write_fsm = WRITE_BC_TRT_LOCK; + +#if DEBUG_MEMC_WRITE + if (m_debug) + std::cout << " " + << " Read the cache to complete local buffer" << std::endl; +#endif + break; + } + /////////////////////// + case WRITE_BC_TRT_LOCK: // get TRT lock to check TRT not full + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and + "MEMC ERROR in WRITE_BC_TRT_LOCK state: Bad DIR allocation"); + + // We read the cache and complete the buffer. As the DATA cache uses a + // synchronous RAM, the read DATA request has been performed in the + // WRITE_BC_DIR_READ state but the data is available in this state. + if (r_write_bc_data_we.read()) + { + size_t set = m_y[(addr_t)(r_write_address.read())]; + size_t way = r_write_way.read(); + for(size_t word=0 ; word Complete data buffer" << std::endl; +#endif + } + + if (r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE) + { + // if we loop in this state, the data does not need to be + // rewritten (for energy consuption) + r_write_bc_data_we = false; + break; + } + + size_t wok_index = 0; + bool wok = not m_trt.full(wok_index); + if (wok ) + { + r_write_trt_index = wok_index; + r_write_fsm = WRITE_BC_IVT_LOCK; + } + else // wait an empty slot in TRT + { + r_write_fsm = WRITE_WAIT; + } + +#if DEBUG_MEMC_WRITE + if (m_debug) + std::cout << " Check TRT : wok = " << wok + << " / index = " << wok_index << std::endl; +#endif + break; + } + ////////////////////// + case WRITE_BC_IVT_LOCK: // get IVT lock and register BC transaction in IVT + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and + "MEMC ERROR in WRITE_BC_IVT_LOCK state: Bad DIR allocation"); + + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) and + "MEMC ERROR in WRITE_BC_IVT_LOCK state: Bad TRT allocation"); + + if (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) + { + bool wok = false; + size_t index = 0; + size_t srcid = r_write_srcid.read(); + size_t trdid = r_write_trdid.read(); + size_t pktid = r_write_pktid.read(); + addr_t nline = m_nline[(addr_t)(r_write_address.read())]; + size_t nb_copies = r_write_count.read(); + + wok = m_ivt.set(false, // it's an inval transaction + true, // it's a broadcast + true, // response required + false, // no acknowledge required + srcid, + trdid, + pktid, + nline, + nb_copies, + index); +#if DEBUG_MEMC_WRITE + if (m_debug and wok ) + std::cout << " Register broadcast inval in IVT" + << " / nb_copies = " << r_write_count.read() << std::endl; +#endif + r_write_upt_index = index; + + if (wok ) r_write_fsm = WRITE_BC_DIR_INVAL; + else r_write_fsm = WRITE_WAIT; + } + break; + } + //////////////////////// + case WRITE_BC_DIR_INVAL: // Register a put transaction in TRT + // and invalidate the line in directory + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and + "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad DIR allocation"); + + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) and + "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad TRT allocation"); + + assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) and + "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad IVT allocation"); + + // register PUT request in TRT + std::vector data_vector; + data_vector.clear(); + for(size_t i=0; i (m_words,0), + data_vector ); + + // invalidate directory entry + DirectoryEntry entry; + entry.valid = false; + entry.dirty = false; + entry.tag = 0; + entry.is_cnt = false; + entry.lock = false; + entry.owner.srcid = 0; + entry.owner.inst = false; + entry.ptr = 0; + entry.count = 0; + size_t set = m_y[(addr_t)(r_write_address.read())]; + size_t way = r_write_way.read(); + + m_cache_directory.write(set, way, entry); + + if ((r_write_pktid.read() & 0x7) == TYPE_SC) + { + m_llsc_table.sc(r_write_address.read(), + r_write_sc_key.read()); + } + +#if DEBUG_MEMC_WRITE + if (m_debug) + std::cout << " Inval DIR and register in TRT:" + << " address = " << r_write_address.read() << std::endl; +#endif + r_write_fsm = WRITE_BC_CC_SEND; + break; + } + + ////////////////////// + case WRITE_BC_CC_SEND: // Post a coherence broadcast request to CC_SEND FSM + { + if (!r_write_to_cc_send_multi_req.read() and !r_write_to_cc_send_brdcast_req.read()) + { + r_write_to_cc_send_multi_req = false; + r_write_to_cc_send_brdcast_req = true; + r_write_to_cc_send_trdid = r_write_upt_index.read(); + r_write_to_cc_send_nline = m_nline[(addr_t)(r_write_address.read())]; + r_write_to_cc_send_index = 0; + r_write_to_cc_send_count = 0; + + for(size_t i=0; i Post a broadcast request to CC_SEND FSM" << std::endl; +#endif + } + break; + } + + /////////////////////// + case WRITE_BC_XRAM_REQ: // Post a PUT request to IXR_CMD FSM + { + if (not r_write_to_ixr_cmd_req.read()) + { + r_write_to_ixr_cmd_req = true; + r_write_to_ixr_cmd_index = r_write_trt_index.read(); + r_write_fsm = WRITE_IDLE; + +#if DEBUG_MEMC_WRITE + if (m_debug) + std::cout << " Post a put request to IXR_CMD FSM" << std::endl; +#endif + } + break; + } + } // end switch r_write_fsm + + /////////////////////////////////////////////////////////////////////// + // IXR_CMD FSM + /////////////////////////////////////////////////////////////////////// + // The IXR_CMD fsm controls the command packets to the XRAM : + // It handles requests from 5 FSMs with a round-robin priority: + // READ > WRITE > CAS > XRAM_RSP > CONFIG + // + // - It sends a single flit VCI read to the XRAM in case of + // GET request posted by the READ, WRITE or CAS FSMs. + // - It sends a multi-flit VCI write in case of PUT request posted by + // the XRAM_RSP, WRITE, CAS, or CONFIG FSMs. + // + // For each client, there is three steps: + // - IXR_CMD_*_IDLE : round-robin allocation to a client + // - IXR_CMD_*_TRT : access to TRT for address and data + // - IXR_CMD_*_SEND : send the PUT or GET VCI command + // + // The address and data to be written (for a PUT) are stored in TRT. + // The trdid field contains always the TRT entry index. + //////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "ixr_cmd_fsm" << std::endl; + + switch(r_ixr_cmd_fsm.read()) + { + /////////////////////// + case IXR_CMD_READ_IDLE: + { + if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; + else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; + else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; + else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; + else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; + break; + } + //////////////////////// + case IXR_CMD_WRITE_IDLE: + { + if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; + else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; + else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; + else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; + else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; + break; + } + ////////////////////// + case IXR_CMD_CAS_IDLE: + { + if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; + else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; + else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; + else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; + else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; + break; + } + /////////////////////// + case IXR_CMD_XRAM_IDLE: + { + if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; + else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; + else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; + else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; + else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; + break; + } + ///////////////////////// + case IXR_CMD_CONFIG_IDLE: + { + if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; + else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; + else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; + else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; + else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; + break; + } + + ////////////////////// + case IXR_CMD_READ_TRT: // access TRT for a GET + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) + { + TransactionTabEntry entry = m_trt.read( r_read_to_ixr_cmd_index.read()); + r_ixr_cmd_address = entry.nline * (m_words<<2); + r_ixr_cmd_trdid = r_read_to_ixr_cmd_index.read(); + r_ixr_cmd_get = true; + r_ixr_cmd_word = 0; + r_ixr_cmd_fsm = IXR_CMD_READ_SEND; + +#if DEBUG_MEMC_IXR_CMD + if (m_debug) + std::cout << " TRT access" + << " index = " << std::dec << r_read_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; +#endif + } + break; + } + /////////////////////// + case IXR_CMD_WRITE_TRT: // access TRT for a PUT or a GET + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) + { + TransactionTabEntry entry = m_trt.read( r_write_to_ixr_cmd_index.read()); + r_ixr_cmd_address = entry.nline * (m_words<<2); + r_ixr_cmd_trdid = r_write_to_ixr_cmd_index.read(); + r_ixr_cmd_get = entry.xram_read; + r_ixr_cmd_word = 0; + r_ixr_cmd_fsm = IXR_CMD_WRITE_SEND; + + // Read data from TRT if PUT transaction + if (not entry.xram_read) + { + for( size_t i=0 ; i TRT access" + << " index = " << std::dec << r_write_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; +#endif + } + break; + } + ///////////////////// + case IXR_CMD_CAS_TRT: // access TRT for a PUT or a GET + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) + { + TransactionTabEntry entry = m_trt.read( r_cas_to_ixr_cmd_index.read()); + r_ixr_cmd_address = entry.nline * (m_words<<2); + r_ixr_cmd_trdid = r_cas_to_ixr_cmd_index.read(); + r_ixr_cmd_get = entry.xram_read; + r_ixr_cmd_word = 0; + r_ixr_cmd_fsm = IXR_CMD_CAS_SEND; + + // Read data from TRT if PUT transaction + if (not entry.xram_read) + { + for( size_t i=0 ; i TRT access" + << " index = " << std::dec << r_cas_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; +#endif + } + break; + } + ////////////////////// + case IXR_CMD_XRAM_TRT: // access TRT for a PUT + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) + { + TransactionTabEntry entry = m_trt.read( r_xram_rsp_to_ixr_cmd_index.read()); + r_ixr_cmd_address = entry.nline * (m_words<<2); + r_ixr_cmd_trdid = r_xram_rsp_to_ixr_cmd_index.read(); + r_ixr_cmd_get = false; + r_ixr_cmd_word = 0; + r_ixr_cmd_fsm = IXR_CMD_XRAM_SEND; + for( size_t i=0 ; i TRT access" + << " index = " << std::dec << r_xram_rsp_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; +#endif + } + break; + } + //////////////////////// + case IXR_CMD_CONFIG_TRT: // access TRT for a PUT + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) + { + TransactionTabEntry entry = m_trt.read( r_config_to_ixr_cmd_index.read()); + r_ixr_cmd_address = entry.nline * (m_words<<2); + r_ixr_cmd_trdid = r_config_to_ixr_cmd_index.read(); + r_ixr_cmd_get = false; + r_ixr_cmd_word = 0; + r_ixr_cmd_fsm = IXR_CMD_CONFIG_SEND; + for( size_t i=0 ; i TRT access" + << " index = " << std::dec << r_config_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; +#endif + } + break; + } + + /////////////////////// + case IXR_CMD_READ_SEND: // send a get from READ FSM + { + if (p_vci_ixr.cmdack) + { + r_ixr_cmd_fsm = IXR_CMD_READ_IDLE; + r_read_to_ixr_cmd_req = false; + +#if DEBUG_MEMC_IXR_CMD + if (m_debug) + std::cout << " GET request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; +#endif + } + break; + } + //////////////////////// + case IXR_CMD_WRITE_SEND: // send a put or get from WRITE FSM + { + if (p_vci_ixr.cmdack) + { + if (not r_ixr_cmd_get.read()) // PUT + { + if (r_ixr_cmd_word.read() == (m_words - 2)) + { + r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE; + r_write_to_ixr_cmd_req = false; + } + else + { + r_ixr_cmd_word = r_ixr_cmd_word.read() + 2; + } + +#if DEBUG_MEMC_IXR_CMD + if (m_debug) + std::cout << " PUT request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; +#endif + } + else // GET + { + r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE; + r_write_to_ixr_cmd_req = false; + +#if DEBUG_MEMC_IXR_CMD + if (m_debug) + std::cout << " GET request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; +#endif + } + } + break; + } + ////////////////////// + case IXR_CMD_CAS_SEND: // send a put or get command from CAS FSM + { + if (p_vci_ixr.cmdack) + { + if (not r_ixr_cmd_get.read()) // PUT + { + if (r_ixr_cmd_word.read() == (m_words - 2)) + { + r_ixr_cmd_fsm = IXR_CMD_CAS_IDLE; + r_cas_to_ixr_cmd_req = false; + } + else + { + r_ixr_cmd_word = r_ixr_cmd_word.read() + 2; + } + +#if DEBUG_MEMC_IXR_CMD + if (m_debug) + std::cout << " PUT request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; +#endif + } + else // GET + { + r_ixr_cmd_fsm = IXR_CMD_CAS_IDLE; + r_cas_to_ixr_cmd_req = false; + +#if DEBUG_MEMC_IXR_CMD + if (m_debug) + std::cout << " GET request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; +#endif + } + } + break; + } + /////////////////////// + case IXR_CMD_XRAM_SEND: // send a put from XRAM_RSP FSM + { + if (p_vci_ixr.cmdack.read()) + { + if (r_ixr_cmd_word.read() == (m_words - 2)) + { + r_ixr_cmd_fsm = IXR_CMD_XRAM_IDLE; + r_xram_rsp_to_ixr_cmd_req = false; + } + else + { + r_ixr_cmd_word = r_ixr_cmd_word.read() + 2; + } + +#if DEBUG_MEMC_IXR_CMD + if (m_debug) + std::cout << " PUT request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; +#endif + } + break; + } + ///////////////////////// + case IXR_CMD_CONFIG_SEND: // send a put from CONFIG FSM + { + if (p_vci_ixr.cmdack.read()) + { + if (r_ixr_cmd_word.read() == (m_words - 2)) + { + r_ixr_cmd_fsm = IXR_CMD_CONFIG_IDLE; + r_config_to_ixr_cmd_req = false; + } + else + { + r_ixr_cmd_word = r_ixr_cmd_word.read() + 2; + } + +#if DEBUG_MEMC_IXR_CMD + if (m_debug) + std::cout << " PUT request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; +#endif + } + break; + } + } // end switch r_ixr_cmd_fsm + + //////////////////////////////////////////////////////////////////////////// + // IXR_RSP FSM + //////////////////////////////////////////////////////////////////////////// + // The IXR_RSP FSM receives the response packets from the XRAM, + // for both PUT transaction, and GET transaction. + // + // - A response to a PUT request is a single-cell VCI packet. + // The TRT index is contained in the RTRDID field. + // The FSM takes the lock protecting the TRT, and the corresponding + // entry is erased. If an acknowledge was required (in case of software SYNC) + // the r_config_rsp_lines counter is decremented. + // + // - A response to a GET request is a multi-cell VCI packet. + // The TRT index is contained in the RTRDID field. + // The N cells contain the N words of the cache line in the RDATA field. + // The FSM takes the lock protecting the TRT to store the line in the TRT + // (taking into account the write requests already stored in the TRT). + // When the line is completely written, the r_ixr_rsp_to_xram_rsp_rok[index] + // signal is set to inform the XRAM_RSP FSM. + /////////////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "ixr_rsp_fsm" << std::endl; + + switch(r_ixr_rsp_fsm.read()) + { + ////////////////// + case IXR_RSP_IDLE: // test transaction type: PUT/GET + { + if (p_vci_ixr.rspval.read()) + { + r_ixr_rsp_cpt = 0; + r_ixr_rsp_trt_index = p_vci_ixr.rtrdid.read(); + + if (p_vci_ixr.reop.read() and not + p_vci_ixr.rerror.read()) // PUT + { + r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE; + +#if DEBUG_MEMC_IXR_RSP +if (m_debug) +std::cout << " Response from XRAM to a put transaction" << std::endl; +#endif + } + else // GET + { + r_ixr_rsp_fsm = IXR_RSP_TRT_READ; + +#if DEBUG_MEMC_IXR_RSP +if (m_debug) +std::cout << " Response from XRAM to a get transaction" << std::endl; +#endif + } + } + break; + } + //////////////////////// + case IXR_RSP_TRT_ERASE: // erase the entry in the TRT + // decrease the line counter if config request + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) + { + size_t index = r_ixr_rsp_trt_index.read(); + + if (m_trt.is_config(index)) // it's a config transaction + { + config_rsp_lines_ixr_rsp_decr = true; + } + + m_trt.erase(index); + r_ixr_rsp_fsm = IXR_RSP_IDLE; + +#if DEBUG_MEMC_IXR_RSP +if (m_debug) +std::cout << " Erase TRT entry " + << r_ixr_rsp_trt_index.read() << std::endl; +#endif + } + break; + } + ////////////////////// + case IXR_RSP_TRT_READ: // write a 64 bits data word in TRT + { + if ((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and p_vci_ixr.rspval) + { + size_t index = r_ixr_rsp_trt_index.read(); + size_t word = r_ixr_rsp_cpt.read(); + bool eop = p_vci_ixr.reop.read(); + wide_data_t data = p_vci_ixr.rdata.read(); + bool rerror = ((p_vci_ixr.rerror.read() & 0x1) == 1); + + assert(((eop == (word == (m_words-2))) or rerror) and + "MEMC ERROR in IXR_RSP_TRT_READ state : invalid response from XRAM"); + + m_trt.write_rsp( index, word, data, rerror ); + + r_ixr_rsp_cpt = word + 2; + + if (eop ) + { + r_ixr_rsp_to_xram_rsp_rok[r_ixr_rsp_trt_index.read()] = true; + r_ixr_rsp_fsm = IXR_RSP_IDLE; + } + +#if DEBUG_MEMC_IXR_RSP +if (m_debug) +std::cout << " Writing 2 words in TRT : " + << " index = " << std::dec << index + << " / word = " << word + << " / data = " << std::hex << data << std::endl; +#endif + } + break; + } + } // end swich r_ixr_rsp_fsm + + //////////////////////////////////////////////////////////////////////////// + // XRAM_RSP FSM + //////////////////////////////////////////////////////////////////////////// + // The XRAM_RSP FSM handles the incoming cache lines after an XRAM GET. + // The cache line has been written in the TRT by the IXR_CMD_FSM. + // As the IXR_RSP FSM and the XRAM_RSP FSM are running in parallel, + // there is as many flip-flops r_ixr_rsp_to_xram_rsp_rok[i] as the number + // of entries in the TRT, that are handled with a round-robin priority... + // + // The FSM takes the lock protecting TRT, and the lock protecting DIR. + // The selected TRT entry is copied in the local buffer r_xram_rsp_trt_buf. + // It selects a cache slot and save the victim line in another local buffer + // r_xram_rsp_victim_***. + // It writes the line extracted from TRT in the cache. + // If it was a read MISS, the XRAM_RSP FSM send a request to the TGT_RSP + // FSM to return the cache line to the registered processor. + // If there is no empty slot, a victim line is evicted, and + // invalidate requests are sent to the L1 caches containing copies. + // If this line is dirty, the XRAM_RSP FSM send a request to the IXR_CMD + // FSM to save the victim line to the XRAM, and register the write transaction + // in the TRT (using the entry previously used by the read transaction). + /////////////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "xram_rsp_fsm" << std::endl; + + switch(r_xram_rsp_fsm.read()) + { + /////////////////// + case XRAM_RSP_IDLE: // scan the XRAM responses / select a TRT index (round robin) + { + size_t old = r_xram_rsp_trt_index.read(); + size_t lines = m_trt_lines; + for(size_t i=0 ; i" + << " Available cache line in TRT:" + << " index = " << std::dec << index << std::endl; +#endif + break; + } + } + break; + } + /////////////////////// + case XRAM_RSP_DIR_LOCK: // Takes the DIR lock and the TRT lock + // Copy the TRT entry in a local buffer + { + if ((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and + (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP)) + { + // copy the TRT entry in the r_xram_rsp_trt_buf local buffer + size_t index = r_xram_rsp_trt_index.read(); + r_xram_rsp_trt_buf.copy( m_trt.read(index)); + r_xram_rsp_fsm = XRAM_RSP_TRT_COPY; + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " " + << " Get access to DIR and TRT" << std::endl; +#endif + } + break; + } + /////////////////////// + case XRAM_RSP_TRT_COPY: // Select a victim cache line + // and copy it in a local buffer + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and + "MEMC ERROR in XRAM_RSP_TRT_COPY state: Bad DIR allocation"); + + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and + "MEMC ERROR in XRAM_RSP_TRT_COPY state: Bad TRT allocation"); + + // selects & extracts a victim line from cache + size_t way = 0; + size_t set = m_y[(addr_t)(r_xram_rsp_trt_buf.nline * m_words * 4)]; + + DirectoryEntry victim(m_cache_directory.select(set, way)); + + bool inval = (victim.count and victim.valid) ; + + // copy the victim line in a local buffer (both data dir) + m_cache_data.read_line(way, set, r_xram_rsp_victim_data); + + r_xram_rsp_victim_copy = victim.owner.srcid; + r_xram_rsp_victim_copy_inst = victim.owner.inst; + r_xram_rsp_victim_count = victim.count; + r_xram_rsp_victim_ptr = victim.ptr; + r_xram_rsp_victim_way = way; + r_xram_rsp_victim_set = set; + r_xram_rsp_victim_nline = (addr_t)victim.tag*m_sets + set; + r_xram_rsp_victim_is_cnt = victim.is_cnt; + r_xram_rsp_victim_inval = inval ; + r_xram_rsp_victim_dirty = victim.dirty; + + if (not r_xram_rsp_trt_buf.rerror ) r_xram_rsp_fsm = XRAM_RSP_IVT_LOCK; + else r_xram_rsp_fsm = XRAM_RSP_ERROR_ERASE; + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " " + << " Select a victim slot: " + << " way = " << std::dec << way + << " / set = " << set + << " / inval_required = " << inval << std::endl; +#endif + break; + } + /////////////////////// + case XRAM_RSP_IVT_LOCK: // Keep DIR and TRT locks and take the IVT lock + // to check a possible pending inval + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and + "MEMC ERROR in XRAM_RSP_IVT_LOCK state: Bad DIR allocation"); + + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and + "MEMC ERROR in XRAM_RSP_IVT_LOCK state: Bad TRT allocation"); + + if (r_alloc_ivt_fsm == ALLOC_IVT_XRAM_RSP) + { + size_t index = 0; + if (m_ivt.search_inval(r_xram_rsp_trt_buf.nline, index)) // pending inval + { + r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " " + << " Get acces to IVT, but line invalidation registered" + << " / address = " << std::hex << r_xram_rsp_trt_buf.nline*m_words*4 + << " / index = " << std::dec << index << std::endl; +#endif + + } + else if (m_ivt.is_full() and r_xram_rsp_victim_inval.read()) // IVT full + { + r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " " + << " Get acces to IVT, but inval required and IVT full" << std::endl; +#endif + } + else + { + r_xram_rsp_fsm = XRAM_RSP_DIR_UPDT; + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " " + << " Get acces to IVT / no pending inval request" << std::endl; +#endif + } + } + break; + } + ///////////////////////// + case XRAM_RSP_INVAL_WAIT: // release all locks and returns to DIR_LOCK to retry + { + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " " + << " Release all locks and retry" << std::endl; +#endif + r_xram_rsp_fsm = XRAM_RSP_DIR_LOCK; + break; + } + /////////////////////// + case XRAM_RSP_DIR_UPDT: // updates the cache (both data & directory), + // erases the TRT entry if victim not dirty, + // and set inval request in IVT if required + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and + "MEMC ERROR in XRAM_RSP_DIR_UPDT state: Bad DIR allocation"); + + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and + "MEMC ERROR in XRAM_RSP_DIR_UPDT state: Bad TRT allocation"); + + assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_XRAM_RSP) and + "MEMC ERROR in XRAM_RSP_DIR_UPDT state: Bad IVT allocation"); + + // check if this is an instruction read, this means pktid is either + // TYPE_READ_INS_UNC 0bX010 with TSAR encoding + // TYPE_READ_INS_MISS 0bX011 with TSAR encoding + bool inst_read = (r_xram_rsp_trt_buf.pktid & 0x2) and r_xram_rsp_trt_buf.proc_read; + + // check if this is a cached read, this means pktid is either + // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding + // TYPE_READ_INS_MISS 0bX011 with TSAR encoding + bool cached_read = (r_xram_rsp_trt_buf.pktid & 0x1) and r_xram_rsp_trt_buf.proc_read; + + bool dirty = false; + + // update cache data + size_t set = r_xram_rsp_victim_set.read(); + size_t way = r_xram_rsp_victim_way.read(); + + for(size_t word=0; word" + << " Cache update: " + << " way = " << std::dec << way + << " / set = " << set + << " / owner_id = " << std::hex << entry.owner.srcid + << " / owner_ins = " << std::dec << entry.owner.inst + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt << std::endl; + if (r_xram_rsp_victim_inval.read()) + std::cout << " Invalidation request for address " + << std::hex << r_xram_rsp_victim_nline.read()*m_words*4 + << " / broadcast = " << r_xram_rsp_victim_is_cnt.read() << std::endl; + } +#endif + + // If the victim is not dirty, we don't need to reuse the TRT entry for + // another PUT transaction, and we can erase the TRT entry + if (not r_xram_rsp_victim_dirty.read()) + { + m_trt.erase(r_xram_rsp_trt_index.read()); + } + + // Next state + if (r_xram_rsp_victim_dirty.read()) r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY; + else if (r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_DIR_RSP; + else if (r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; + else r_xram_rsp_fsm = XRAM_RSP_IDLE; + break; + } + //////////////////////// + case XRAM_RSP_TRT_DIRTY: // set the TRT entry (PUT to XRAM) if the victim is dirty + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) + { + std::vector data_vector; + data_vector.clear(); + for(size_t i=0; i(m_words,0xF), + data_vector); + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " " + << " Set TRT entry for the put transaction" + << " / address = " << (r_xram_rsp_victim_nline.read()*m_words*4) << std::endl; +#endif + if (r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_DIR_RSP; + else if (r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; + else r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; + } + break; + } + ////////////////////// + case XRAM_RSP_DIR_RSP: // Request a response to TGT_RSP FSM + { + if (not r_xram_rsp_to_tgt_rsp_req.read()) + { + r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid; + r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid; + r_xram_rsp_to_tgt_rsp_pktid = r_xram_rsp_trt_buf.pktid; + for(size_t i=0; i < m_words; i++) + { + r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i]; + } + r_xram_rsp_to_tgt_rsp_word = r_xram_rsp_trt_buf.word_index; + r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length; + r_xram_rsp_to_tgt_rsp_ll_key = r_xram_rsp_trt_buf.ll_key; + r_xram_rsp_to_tgt_rsp_rerror = false; + r_xram_rsp_to_tgt_rsp_req = true; + + if (r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; + else if (r_xram_rsp_victim_dirty.read()) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; + else r_xram_rsp_fsm = XRAM_RSP_IDLE; + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " " + << " Request the TGT_RSP FSM to return data:" + << " rsrcid = " << std::hex << r_xram_rsp_trt_buf.srcid + << " / address = " << std::hex << r_xram_rsp_trt_buf.nline*m_words*4 + << " / nwords = " << std::dec << r_xram_rsp_trt_buf.read_length << std::endl; +#endif + } + break; + } + //////////////////// + case XRAM_RSP_INVAL: // send invalidate request to CC_SEND FSM + { + if (!r_xram_rsp_to_cc_send_multi_req.read() and + !r_xram_rsp_to_cc_send_brdcast_req.read()) + { + bool multi_req = !r_xram_rsp_victim_is_cnt.read(); + bool last_multi_req = multi_req and (r_xram_rsp_victim_count.read() == 1); + bool not_last_multi_req = multi_req and (r_xram_rsp_victim_count.read() != 1); + + r_xram_rsp_to_cc_send_multi_req = last_multi_req; + r_xram_rsp_to_cc_send_brdcast_req = r_xram_rsp_victim_is_cnt.read(); + r_xram_rsp_to_cc_send_nline = r_xram_rsp_victim_nline.read(); + r_xram_rsp_to_cc_send_trdid = r_xram_rsp_ivt_index; + xram_rsp_to_cc_send_fifo_srcid = r_xram_rsp_victim_copy.read(); + xram_rsp_to_cc_send_fifo_inst = r_xram_rsp_victim_copy_inst.read(); + xram_rsp_to_cc_send_fifo_put = multi_req; + r_xram_rsp_next_ptr = r_xram_rsp_victim_ptr.read(); + + if (r_xram_rsp_victim_dirty) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; + else if (not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ; + else r_xram_rsp_fsm = XRAM_RSP_IDLE; + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " " + << " Send an inval request to CC_SEND FSM" + << " / address = " << r_xram_rsp_victim_nline.read()*m_words*4 << std::endl; +#endif + } + break; + } + ////////////////////////// + case XRAM_RSP_WRITE_DIRTY: // send a write request to IXR_CMD FSM + { + if (not r_xram_rsp_to_ixr_cmd_req.read()) + { + r_xram_rsp_to_ixr_cmd_req = true; + r_xram_rsp_to_ixr_cmd_index = r_xram_rsp_trt_index.read(); + + m_cpt_write_dirty++; + + bool multi_req = not r_xram_rsp_victim_is_cnt.read() and + r_xram_rsp_victim_inval.read(); + bool not_last_multi_req = multi_req and (r_xram_rsp_victim_count.read() != 1); + + if (not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ; + else r_xram_rsp_fsm = XRAM_RSP_IDLE; + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " " + << " Send the put request to IXR_CMD FSM" + << " / address = " << r_xram_rsp_victim_nline.read()*m_words*4 << std::endl; +#endif + } + break; + } + ///////////////////////// + case XRAM_RSP_HEAP_REQ: // Get the lock to the HEAP + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP) + { + r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE; + } + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " " + << " Requesting HEAP lock" << std::endl; +#endif + break; + } + ///////////////////////// + case XRAM_RSP_HEAP_ERASE: // erase the copies and send invalidations + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP) + { + HeapEntry entry = m_heap.read(r_xram_rsp_next_ptr.read()); + + xram_rsp_to_cc_send_fifo_srcid = entry.owner.srcid; + xram_rsp_to_cc_send_fifo_inst = entry.owner.inst; + xram_rsp_to_cc_send_fifo_put = true; + if (m_xram_rsp_to_cc_send_inst_fifo.wok()) + { + r_xram_rsp_next_ptr = entry.next; + if (entry.next == r_xram_rsp_next_ptr.read()) // last copy + { + r_xram_rsp_to_cc_send_multi_req = true; + r_xram_rsp_fsm = XRAM_RSP_HEAP_LAST; + } + else + { + r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE; + } + } + else + { + r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE; + } + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " " + << " Erase copy:" + << " srcid = " << std::hex << entry.owner.srcid + << " / inst = " << std::dec << entry.owner.inst << std::endl; +#endif + } + break; + } + ///////////////////////// + case XRAM_RSP_HEAP_LAST: // last copy + { + if (r_alloc_heap_fsm.read() != ALLOC_HEAP_XRAM_RSP) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_HEAP_LAST" + << " bad HEAP allocation" << std::endl; + exit(0); + } + size_t free_pointer = m_heap.next_free_ptr(); + + HeapEntry last_entry; + last_entry.owner.srcid = 0; + last_entry.owner.inst = false; + if (m_heap.is_full()) + { + last_entry.next = r_xram_rsp_next_ptr.read(); + m_heap.unset_full(); + } + else + { + last_entry.next = free_pointer; + } + + m_heap.write_free_ptr(r_xram_rsp_victim_ptr.read()); + m_heap.write(r_xram_rsp_next_ptr.read(),last_entry); + + r_xram_rsp_fsm = XRAM_RSP_IDLE; + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " " + << " Heap housekeeping" << std::endl; +#endif + break; + } + ////////////////////////// + case XRAM_RSP_ERROR_ERASE: // erase TRT entry in case of error + { + m_trt.erase(r_xram_rsp_trt_index.read()); + + // Next state + if (r_xram_rsp_trt_buf.proc_read) + { + r_xram_rsp_fsm = XRAM_RSP_ERROR_RSP; + } + else + { + // Trigger an interruption to signal a bus error from + // the XRAM because a processor WRITE MISS (XRAM GET + // transaction and not processor read). + // + // To avoid deadlocks we do not wait an error to be + // acknowledged before signaling another one. + // Therefore, when there is an active error, and other + // errors arrive, these are not considered + + if (!r_xram_rsp_rerror_irq.read() && r_xram_rsp_rerror_irq_enable.read() + && r_xram_rsp_trt_buf.xram_read ) + { + r_xram_rsp_rerror_irq = true; + r_xram_rsp_rerror_address = r_xram_rsp_trt_buf.nline * m_words * 4; + r_xram_rsp_rerror_rsrcid = r_xram_rsp_trt_buf.srcid; + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout + << " " + << " Triggering interrupt to signal WRITE MISS bus error" + << " / irq_enable = " << r_xram_rsp_rerror_irq_enable.read() + << " / nline = " << r_xram_rsp_trt_buf.nline + << " / rsrcid = " << r_xram_rsp_trt_buf.srcid + << std::endl; +#endif + } + + r_xram_rsp_fsm = XRAM_RSP_IDLE; + } + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " " + << " Error reported by XRAM / erase the TRT entry" << std::endl; +#endif + break; + } + //////////////////////// + case XRAM_RSP_ERROR_RSP: // Request an error response to TGT_RSP FSM + { + if (!r_xram_rsp_to_tgt_rsp_req.read()) + { + r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid; + r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid; + r_xram_rsp_to_tgt_rsp_pktid = r_xram_rsp_trt_buf.pktid; + for(size_t i=0; i < m_words; i++) + { + r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i]; + } + r_xram_rsp_to_tgt_rsp_word = r_xram_rsp_trt_buf.word_index; + r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length; + r_xram_rsp_to_tgt_rsp_rerror = true; + r_xram_rsp_to_tgt_rsp_req = true; + + r_xram_rsp_fsm = XRAM_RSP_IDLE; + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + std::cout << " Request a response error to TGT_RSP FSM:" + << " srcid = " << std::dec << r_xram_rsp_trt_buf.srcid << std::endl; +#endif + } + break; + } + } // end swich r_xram_rsp_fsm + + //////////////////////////////////////////////////////////////////////////////////// + // CLEANUP FSM + //////////////////////////////////////////////////////////////////////////////////// + // The CLEANUP FSM handles the cleanup request from L1 caches. + // It accesses the cache directory and the heap to update the list of copies. + //////////////////////////////////////////////////////////////////////////////////// + + switch(r_cleanup_fsm.read()) + { + ////////////////// + case CLEANUP_IDLE: // Get first DSPIN flit of the CLEANUP command + { + if (not m_cc_receive_to_cleanup_fifo.rok()) break; + + uint64_t flit = m_cc_receive_to_cleanup_fifo.read(); + + uint32_t srcid = DspinDhccpParam::dspin_get(flit, + DspinDhccpParam::CLEANUP_SRCID); + + uint8_t type = DspinDhccpParam::dspin_get(flit, + DspinDhccpParam::P2M_TYPE); + + r_cleanup_way_index = DspinDhccpParam::dspin_get(flit, + DspinDhccpParam::CLEANUP_WAY_INDEX); + + r_cleanup_nline = DspinDhccpParam::dspin_get(flit, + DspinDhccpParam::CLEANUP_NLINE_MSB) << 32; + + r_cleanup_inst = (type == DspinDhccpParam::TYPE_CLEANUP_INST); + r_cleanup_srcid = srcid; + + assert((srcid < m_initiators) and + "MEMC ERROR in CLEANUP_IDLE state : illegal SRCID value"); + + cc_receive_to_cleanup_fifo_get = true; + r_cleanup_fsm = CLEANUP_GET_NLINE; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " Cleanup request:" << std::hex + << " owner_id = " << srcid + << " / owner_ins = " << (type == DspinDhccpParam::TYPE_CLEANUP_INST) << std::endl; +#endif + break; + } + /////////////////////// + case CLEANUP_GET_NLINE: // GET second DSPIN flit of the cleanup command + { + if (not m_cc_receive_to_cleanup_fifo.rok()) break; + + uint64_t flit = m_cc_receive_to_cleanup_fifo.read(); + + addr_t nline = r_cleanup_nline.read() | + DspinDhccpParam::dspin_get(flit, DspinDhccpParam::CLEANUP_NLINE_LSB); + + cc_receive_to_cleanup_fifo_get = true; + r_cleanup_nline = nline; + r_cleanup_fsm = CLEANUP_DIR_REQ; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " Cleanup request:" + << " address = " << std::hex << nline * m_words * 4 << std::endl; +#endif + break; + } + ///////////////////// + case CLEANUP_DIR_REQ: // Get the lock to the directory + { + if (r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP) break; + + r_cleanup_fsm = CLEANUP_DIR_LOCK; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " Requesting DIR lock" << std::endl; +#endif + break; + } + ////////////////////// + case CLEANUP_DIR_LOCK: // test directory status + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CLEANUP) and + "MEMC ERROR in CLEANUP_DIR_LOCK: bad DIR allocation"); + + // Read the directory + size_t way = 0; + addr_t cleanup_address = r_cleanup_nline.read() * m_words * 4; + DirectoryEntry entry = m_cache_directory.read(cleanup_address , way); + r_cleanup_is_cnt = entry.is_cnt; + r_cleanup_dirty = entry.dirty; + r_cleanup_tag = entry.tag; + r_cleanup_lock = entry.lock; + r_cleanup_way = way; + r_cleanup_count = entry.count; + r_cleanup_ptr = entry.ptr; + r_cleanup_copy = entry.owner.srcid; + r_cleanup_copy_inst = entry.owner.inst; + + if (entry.valid) // hit : the copy must be cleared + { + assert( (entry.count > 0) and + "MEMC ERROR in CLEANUP_DIR_LOCK state, CLEANUP on valid entry with no copies"); + + if ((entry.count == 1) or (entry.is_cnt)) // no access to the heap + { + r_cleanup_fsm = CLEANUP_DIR_WRITE; + } + else // access to the heap + { + r_cleanup_fsm = CLEANUP_HEAP_REQ; + } + } + else // miss : check IVT for a pending inval + { + r_cleanup_fsm = CLEANUP_IVT_LOCK; + } + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " Test directory status: " + << std::hex << " address = " << cleanup_address + << " / hit = " << entry.valid + << " / dir_id = " << entry.owner.srcid + << " / dir_ins = " << entry.owner.inst + << " / search_id = " << r_cleanup_srcid.read() + << " / search_ins = " << r_cleanup_inst.read() + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt << std::endl; +#endif + break; + } + /////////////////////// + case CLEANUP_DIR_WRITE: // Update the directory entry without heap access + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CLEANUP) and + "MEMC ERROR in CLEANUP_DIR_LOCK: bad DIR allocation"); + + size_t way = r_cleanup_way.read(); + size_t set = m_y[(addr_t)(r_cleanup_nline.read()*m_words*4)]; + bool match_srcid = (r_cleanup_copy.read() == r_cleanup_srcid.read()); + bool match_inst = (r_cleanup_copy_inst.read() == r_cleanup_inst.read()); + bool match = match_srcid and match_inst; + + assert( (r_cleanup_is_cnt.read() or match) and + "MEMC ERROR in CLEANUP_DIR_LOCK: illegal CLEANUP on valid entry"); + + // update the cache directory (for the copies) + DirectoryEntry entry; + entry.valid = true; + entry.is_cnt = r_cleanup_is_cnt.read(); + entry.dirty = r_cleanup_dirty.read(); + entry.tag = r_cleanup_tag.read(); + entry.lock = r_cleanup_lock.read(); + entry.ptr = r_cleanup_ptr.read(); + entry.count = r_cleanup_count.read() - 1; + entry.owner.srcid = 0; + entry.owner.inst = 0; + + m_cache_directory.write(set, way, entry); + + r_cleanup_fsm = CLEANUP_SEND_CLACK; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " Update directory:" + << std::hex << " address = " << r_cleanup_nline.read() * m_words * 4 + << " / dir_id = " << entry.owner.srcid + << " / dir_ins = " << entry.owner.inst + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt << std::endl; +#endif + + break; + } + ////////////////////// + case CLEANUP_HEAP_REQ: // get the lock to the HEAP directory + { + if (r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP) break; + + r_cleanup_fsm = CLEANUP_HEAP_LOCK; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " HEAP lock acquired " << std::endl; +#endif + break; + } + ////////////////////// + case CLEANUP_HEAP_LOCK: // two cases are handled in this state : + // 1. the matching copy is directly in the directory + // 2. the matching copy is the first copy in the heap + { + assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and + "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation"); + + size_t way = r_cleanup_way.read(); + size_t set = m_y[(addr_t)(r_cleanup_nline.read() *m_words*4)]; + + HeapEntry heap_entry = m_heap.read(r_cleanup_ptr.read()); + bool last = (heap_entry.next == r_cleanup_ptr.read()); + + // match_dir computation + bool match_dir_srcid = (r_cleanup_copy.read() == r_cleanup_srcid.read()); + bool match_dir_inst = (r_cleanup_copy_inst.read() == r_cleanup_inst.read()); + bool match_dir = match_dir_srcid and match_dir_inst; + + // match_heap computation + bool match_heap_srcid = (heap_entry.owner.srcid == r_cleanup_srcid.read()); + bool match_heap_inst = (heap_entry.owner.inst == r_cleanup_inst.read()); + bool match_heap = match_heap_srcid and match_heap_inst; + + r_cleanup_prev_ptr = r_cleanup_ptr.read(); + r_cleanup_prev_srcid = heap_entry.owner.srcid; + r_cleanup_prev_inst = heap_entry.owner.inst; + + assert( (not last or match_dir or match_heap) and + "MEMC ERROR in CLEANUP_HEAP_LOCK state: hit but no copy found"); + + assert( (not match_dir or not match_heap) and + "MEMC ERROR in CLEANUP_HEAP_LOCK state: two matching copies found"); + + DirectoryEntry dir_entry; + dir_entry.valid = true; + dir_entry.is_cnt = r_cleanup_is_cnt.read(); + dir_entry.dirty = r_cleanup_dirty.read(); + dir_entry.tag = r_cleanup_tag.read(); + dir_entry.lock = r_cleanup_lock.read(); + dir_entry.count = r_cleanup_count.read()-1; + + // the matching copy is registered in the directory and + // it must be replaced by the first copy registered in + // the heap. The corresponding entry must be freed + if (match_dir) + { + dir_entry.ptr = heap_entry.next; + dir_entry.owner.srcid = heap_entry.owner.srcid; + dir_entry.owner.inst = heap_entry.owner.inst; + r_cleanup_next_ptr = r_cleanup_ptr.read(); + r_cleanup_fsm = CLEANUP_HEAP_FREE; + } + + // the matching copy is the first copy in the heap + // It must be freed and the copy registered in directory + // must point to the next copy in heap + else if (match_heap) + { + dir_entry.ptr = heap_entry.next; + dir_entry.owner.srcid = r_cleanup_copy.read(); + dir_entry.owner.inst = r_cleanup_copy_inst.read(); + r_cleanup_next_ptr = r_cleanup_ptr.read(); + r_cleanup_fsm = CLEANUP_HEAP_FREE; + } + + // The matching copy is in the heap, but is not the first copy + // The directory entry must be modified to decrement count + else + { + dir_entry.ptr = r_cleanup_ptr.read(); + dir_entry.owner.srcid = r_cleanup_copy.read(); + dir_entry.owner.inst = r_cleanup_copy_inst.read(); + r_cleanup_next_ptr = heap_entry.next; + r_cleanup_fsm = CLEANUP_HEAP_SEARCH; + } + + m_cache_directory.write(set,way,dir_entry); + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " Checks matching:" + << " address = " << r_cleanup_nline.read() * m_words * 4 + << " / dir_id = " << r_cleanup_copy.read() + << " / dir_ins = " << r_cleanup_copy_inst.read() + << " / heap_id = " << heap_entry.owner.srcid + << " / heap_ins = " << heap_entry.owner.inst + << " / search_id = " << r_cleanup_srcid.read() + << " / search_ins = " << r_cleanup_inst.read() << std::endl; +#endif + break; + } + //////////////////////// + case CLEANUP_HEAP_SEARCH: // This state is handling the case where the copy + // is in the heap, but not the first in linked list + { + assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and + "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation"); + + HeapEntry heap_entry = m_heap.read(r_cleanup_next_ptr.read()); + + bool last = (heap_entry.next == r_cleanup_next_ptr.read()); + bool match_heap_srcid = (heap_entry.owner.srcid == r_cleanup_srcid.read()); + bool match_heap_inst = (heap_entry.owner.inst == r_cleanup_inst.read()); + bool match_heap = match_heap_srcid and match_heap_inst; + + assert( (not last or match_heap) and + "MEMC ERROR in CLEANUP_HEAP_SEARCH state: no copy found"); + + // the matching copy must be removed + if (match_heap) + { + // re-use ressources + r_cleanup_ptr = heap_entry.next; + r_cleanup_fsm = CLEANUP_HEAP_CLEAN; + } + // test the next in the linked list + else + { + r_cleanup_prev_ptr = r_cleanup_next_ptr.read(); + r_cleanup_prev_srcid = heap_entry.owner.srcid; + r_cleanup_prev_inst = heap_entry.owner.inst; + r_cleanup_next_ptr = heap_entry.next; + r_cleanup_fsm = CLEANUP_HEAP_SEARCH; + } + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + { + if (not match_heap) + { + std::cout + << " Matching copy not found, search next:" + << std::endl; + } + else + { + std::cout + << " Matching copy found:" + << std::endl; + } + std::cout + << " address = " << r_cleanup_nline.read() * m_words * 4 + << " / heap_id = " << heap_entry.owner.srcid + << " / heap_ins = " << heap_entry.owner.inst + << " / search_id = " << r_cleanup_srcid.read() + << " / search_ins = " << r_cleanup_inst.read() + << " / last = " << last + << std::endl; + } +#endif + break; + } + //////////////////////// + case CLEANUP_HEAP_CLEAN: // remove a copy in the linked list + { + assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and + "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation"); + + HeapEntry heap_entry; + heap_entry.owner.srcid = r_cleanup_prev_srcid.read(); + heap_entry.owner.inst = r_cleanup_prev_inst.read(); + bool last = (r_cleanup_next_ptr.read() == r_cleanup_ptr.read()); + + if (last) // this is the last entry of the list of copies + { + heap_entry.next = r_cleanup_prev_ptr.read(); + } + else // this is not the last entry + { + heap_entry.next = r_cleanup_ptr.read(); + } + + m_heap.write(r_cleanup_prev_ptr.read(), heap_entry); + + r_cleanup_fsm = CLEANUP_HEAP_FREE; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " " + << " Remove the copy in the linked list" << std::endl; +#endif + break; + } + /////////////////////// + case CLEANUP_HEAP_FREE: // The heap entry pointed by r_cleanup_next_ptr is freed + // and becomes the head of the list of free entries + { + assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and + "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation"); + + HeapEntry heap_entry; + heap_entry.owner.srcid = 0; + heap_entry.owner.inst = false; + + if (m_heap.is_full()) + { + heap_entry.next = r_cleanup_next_ptr.read(); + } + else + { + heap_entry.next = m_heap.next_free_ptr(); + } + + m_heap.write(r_cleanup_next_ptr.read(),heap_entry); + m_heap.write_free_ptr(r_cleanup_next_ptr.read()); + m_heap.unset_full(); + + r_cleanup_fsm = CLEANUP_SEND_CLACK; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " " + << " Update the list of free entries" << std::endl; +#endif + break; + } + ////////////////////// + case CLEANUP_IVT_LOCK: // get the lock protecting the IVT to search a pending + // invalidate transaction matching the cleanup + { + if (r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) break; + + size_t index = 0; + bool match_inval; + + match_inval = m_ivt.search_inval(r_cleanup_nline.read(), index); + + if (not match_inval ) // no pending inval in IVT + { + r_cleanup_fsm = CLEANUP_SEND_CLACK; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " " + << " Unexpected cleanup with no corresponding IVT entry:" + << " address = " << std::hex << (r_cleanup_nline.read()*4*m_words) << std::endl; +#endif + } + else // pending inval in IVT + { + r_cleanup_write_srcid = m_ivt.srcid(index); + r_cleanup_write_trdid = m_ivt.trdid(index); + r_cleanup_write_pktid = m_ivt.pktid(index); + r_cleanup_need_rsp = m_ivt.need_rsp(index); + r_cleanup_need_ack = m_ivt.need_ack(index); + r_cleanup_index = index; + r_cleanup_fsm = CLEANUP_IVT_DECREMENT; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " " + << " Cleanup matching pending invalidate transaction on IVT:" + << " address = " << std::hex << (r_cleanup_nline.read()*m_words*4) + << " / ivt_entry = " << index << std::endl; +#endif + } + break; + } + /////////////////////////// + case CLEANUP_IVT_DECREMENT: // decrement response counter in IVT matching entry + // and test if last + { + assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP) and + "MEMC ERROR in CLEANUP_IVT_DECREMENT state: Bad IVT allocation"); + + size_t count = 0; + m_ivt.decrement(r_cleanup_index.read(), count); + + if (count == 0) r_cleanup_fsm = CLEANUP_IVT_CLEAR; + else r_cleanup_fsm = CLEANUP_SEND_CLACK ; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " " + << " Decrement response counter in IVT:" + << " IVT_index = " << r_cleanup_index.read() + << " / rsp_count = " << count << std::endl; +#endif + break; + } + /////////////////////// + case CLEANUP_IVT_CLEAR: // Clear IVT entry + // Acknowledge CONFIG FSM if required + { + assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP) and + "MEMC ERROR in CLEANUP_IVT_CLEAR state : bad IVT allocation"); + + m_ivt.clear(r_cleanup_index.read()); + + if (r_cleanup_need_ack.read()) + { + assert( (r_config_rsp_lines.read() > 0) and + "MEMC ERROR in CLEANUP_IVT_CLEAR state"); + + config_rsp_lines_cleanup_decr = true; + } + + if (r_cleanup_need_rsp.read()) r_cleanup_fsm = CLEANUP_WRITE_RSP; + else r_cleanup_fsm = CLEANUP_SEND_CLACK; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " Clear entry in IVT:" + << " IVT_index = " << r_cleanup_index.read() << std::endl; +#endif + break; + } + /////////////////////// + case CLEANUP_WRITE_RSP: // response to a previous write on the direct network + // wait if pending request to the TGT_RSP FSM + { + if (r_cleanup_to_tgt_rsp_req.read()) break; + + // no pending request + r_cleanup_to_tgt_rsp_req = true; + r_cleanup_to_tgt_rsp_srcid = r_cleanup_write_srcid.read(); + r_cleanup_to_tgt_rsp_trdid = r_cleanup_write_trdid.read(); + r_cleanup_to_tgt_rsp_pktid = r_cleanup_write_pktid.read(); + r_cleanup_fsm = CLEANUP_SEND_CLACK; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " " + << " Send a response to a previous write request: " + << " rsrcid = " << std::hex << r_cleanup_write_srcid.read() + << " / rtrdid = " << r_cleanup_write_trdid.read() + << " / rpktid = " << r_cleanup_write_pktid.read() << std::endl; +#endif + break; + } + //////////////////////// + case CLEANUP_SEND_CLACK: // acknowledgement to a cleanup command + // on the coherence CLACK network. + { + if (not p_dspin_clack.read) break; + + r_cleanup_fsm = CLEANUP_IDLE; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + std::cout << " Send the response to a cleanup request:" + << " address = " << std::hex << r_cleanup_nline.read()*m_words*4 + << " / way = " << std::dec << r_cleanup_way.read() + << " / srcid = " << std::hex << r_cleanup_srcid.read() + << std::endl; +#endif + break; + } + } // end switch cleanup fsm + + //////////////////////////////////////////////////////////////////////////////////// + // CAS FSM + //////////////////////////////////////////////////////////////////////////////////// + // The CAS FSM handles the CAS (Compare And Swap) atomic commands. + // + // This command contains two or four flits: + // - In case of 32 bits atomic access, the first flit contains the value read + // by a previous READ instruction, the second flit contains the value to be writen. + // - In case of 64 bits atomic access, the 2 first flits contains the value read + // by a previous READ instruction, the 2 next flits contains the value to be writen. + // + // The target address is cachable. If it is replicated in other L1 caches + // than the writer, a coherence operation is done. + // + // It access the directory to check hit / miss. + // - In case of miss, the CAS FSM must register a GET transaction in TRT. + // If a read transaction to the XRAM for this line already exists, + // or if the transaction table is full, it goes to the WAIT state + // to release the locks and try again. When the GET transaction has been + // launched, it goes to the WAIT state and try again. + // The CAS request is not consumed in the FIFO until a HIT is obtained. + // - In case of hit... + /////////////////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "cas_fsm" << std::endl; + + switch(r_cas_fsm.read()) + { + //////////// + case CAS_IDLE: // fill the local rdata buffers + { + if (m_cmd_cas_addr_fifo.rok()) + { + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " CAS command: " << std::hex + << " srcid = " << std::dec << m_cmd_cas_srcid_fifo.read() + << " addr = " << std::hex << m_cmd_cas_addr_fifo.read() + << " wdata = " << m_cmd_cas_wdata_fifo.read() + << " eop = " << std::dec << m_cmd_cas_eop_fifo.read() + << " cpt = " << std::dec << r_cas_cpt.read() << std::endl; +#endif + if (m_cmd_cas_eop_fifo.read()) + { + r_cas_fsm = CAS_DIR_REQ; + } + else // we keep the last word in the FIFO + { + cmd_cas_fifo_get = true; + } + + // We fill the two buffers + if (r_cas_cpt.read() < 2) // 32 bits access + r_cas_rdata[r_cas_cpt.read()] = m_cmd_cas_wdata_fifo.read(); + + if ((r_cas_cpt.read() == 1) and m_cmd_cas_eop_fifo.read()) + r_cas_wdata = m_cmd_cas_wdata_fifo.read(); + + assert( (r_cas_cpt.read() <= 3) and // no more than 4 flits... + "MEMC ERROR in CAS_IDLE state: illegal CAS command"); + + if (r_cas_cpt.read() ==2) + r_cas_wdata = m_cmd_cas_wdata_fifo.read(); + + r_cas_cpt = r_cas_cpt.read() +1; + } + break; + } + ///////////////// + case CAS_DIR_REQ: + { + if (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) + { + r_cas_fsm = CAS_DIR_LOCK; + } + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Requesting DIR lock " << std::endl; +#endif + break; + } + ///////////////// + case CAS_DIR_LOCK: // Read the directory + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and + "MEMC ERROR in CAS_DIR_LOCK: Bad DIR allocation"); + + size_t way = 0; + DirectoryEntry entry(m_cache_directory.read(m_cmd_cas_addr_fifo.read(), way)); + + r_cas_is_cnt = entry.is_cnt; + r_cas_dirty = entry.dirty; + r_cas_tag = entry.tag; + r_cas_way = way; + r_cas_copy = entry.owner.srcid; + r_cas_copy_inst = entry.owner.inst; + r_cas_ptr = entry.ptr; + r_cas_count = entry.count; + + if (entry.valid) r_cas_fsm = CAS_DIR_HIT_READ; + else r_cas_fsm = CAS_MISS_TRT_LOCK; + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Directory acces" + << " / address = " << std::hex << m_cmd_cas_addr_fifo.read() + << " / hit = " << std::dec << entry.valid + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt << std::endl; +#endif + + break; + } + ///////////////////// + case CAS_DIR_HIT_READ: // update directory for lock and dirty bit + // and check data change in cache + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and + "MEMC ERROR in CAS_DIR_HIT_READ: Bad DIR allocation"); + + size_t way = r_cas_way.read(); + size_t set = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())]; + + // update directory (lock & dirty bits) + DirectoryEntry entry; + entry.valid = true; + entry.is_cnt = r_cas_is_cnt.read(); + entry.dirty = true; + entry.lock = true; + entry.tag = r_cas_tag.read(); + entry.owner.srcid = r_cas_copy.read(); + entry.owner.inst = r_cas_copy_inst.read(); + entry.count = r_cas_count.read(); + entry.ptr = r_cas_ptr.read(); + + m_cache_directory.write(set, way, entry); + + // Store data from cache in buffer to do the comparison in next state + m_cache_data.read_line(way, set, r_cas_data); + + r_cas_fsm = CAS_DIR_HIT_COMPARE; + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Read data from " + << " cache and store it in buffer" << std::endl; +#endif + break; + } + //////////////////////// + case CAS_DIR_HIT_COMPARE: + { + size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]; + + // check data change + bool ok = (r_cas_rdata[0].read() == r_cas_data[word].read()); + + if (r_cas_cpt.read() == 4) // 64 bits CAS + ok &= (r_cas_rdata[1] == r_cas_data[word+1]); + + // to avoid livelock, force the atomic access to fail pseudo-randomly + bool forced_fail = ((r_cas_lfsr % (64) == 0) and RANDOMIZE_CAS); + r_cas_lfsr = (r_cas_lfsr >> 1) ^ ((- (r_cas_lfsr & 1)) & 0xd0000001); + + if (ok and not forced_fail) r_cas_fsm = CAS_DIR_HIT_WRITE; + else r_cas_fsm = CAS_RSP_FAIL; + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Compare old and new data" + << " / expected value = " << std::hex << r_cas_rdata[0].read() + << " / actual value = " << std::hex << r_cas_data[word].read() + << " / forced_fail = " << std::dec << forced_fail << std::endl; +#endif + break; + } + ////////////////////// + case CAS_DIR_HIT_WRITE: // test if a CC transaction is required + // write data in cache if no CC request + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and + "MEMC ERROR in CAS_DIR_HIT_WRITE: Bad DIR allocation"); + + // The CAS is a success => sw access to the llsc_global_table + m_llsc_table.sw(m_cmd_cas_addr_fifo.read(), m_cmd_cas_addr_fifo.read()); + + // test coherence request + if (r_cas_count.read()) // replicated line + { + if (r_cas_is_cnt.read()) + { + r_cas_fsm = CAS_BC_TRT_LOCK; // broadcast invalidate required + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " " + << " Broacast Inval required" + << " / copies = " << r_cas_count.read() << std::endl; +#endif + } + else if (not r_cas_to_cc_send_multi_req.read() and + not r_cas_to_cc_send_brdcast_req.read()) + { + r_cas_fsm = CAS_UPT_LOCK; // multi update required + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " " + << " Multi Inval required" + << " / copies = " << r_cas_count.read() << std::endl; +#endif + } + else + { + r_cas_fsm = CAS_WAIT; + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " " + << " CC_SEND FSM busy: release all locks and retry" << std::endl; +#endif + } + } + else // no copies + { + size_t way = r_cas_way.read(); + size_t set = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())]; + size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]; + + // cache update + m_cache_data.write(way, set, word, r_cas_wdata.read()); + if (r_cas_cpt.read() == 4) + m_cache_data.write(way, set, word+1, m_cmd_cas_wdata_fifo.read()); + + r_cas_fsm = CAS_RSP_SUCCESS; + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Update cache:" + << " way = " << std::dec << way + << " / set = " << set + << " / word = " << word + << " / value = " << r_cas_wdata.read() + << " / count = " << r_cas_count.read() + << " / global_llsc_table access" << std::endl; +#endif + } + break; + } + ///////////////// + case CAS_UPT_LOCK: // try to register the transaction in UPT + // and write data in cache if successful registration + // releases locks to retry later if UPT full + { + if (r_alloc_upt_fsm.read() == ALLOC_UPT_CAS) + { + bool wok = false; + size_t index = 0; + size_t srcid = m_cmd_cas_srcid_fifo.read(); + size_t trdid = m_cmd_cas_trdid_fifo.read(); + size_t pktid = m_cmd_cas_pktid_fifo.read(); + addr_t nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; + size_t nb_copies = r_cas_count.read(); + + wok = m_upt.set( true, // it's an update transaction + false, // it's not a broadcast + true, // response required + false, // no acknowledge required + srcid, + trdid, + pktid, + nline, + nb_copies, + index); + if (wok) // coherence transaction registered in UPT + { + // cache update + size_t way = r_cas_way.read(); + size_t set = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())]; + size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]; + + m_cache_data.write(way, set, word, r_cas_wdata.read()); + if (r_cas_cpt.read() ==4) + m_cache_data.write(way, set, word+1, m_cmd_cas_wdata_fifo.read()); + + r_cas_upt_index = index; + r_cas_fsm = CAS_UPT_HEAP_LOCK; + } + else // releases the locks protecting UPT and DIR UPT full + { + r_cas_fsm = CAS_WAIT; + } + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Register multi-update transaction in UPT" + << " / wok = " << wok + << " / address = " << std::hex << nline*m_words*4 + << " / count = " << nb_copies << std::endl; +#endif + } + break; + } + ///////////// + case CAS_WAIT: // release all locks and retry from beginning + { + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Release all locks" << std::endl; +#endif + r_cas_fsm = CAS_DIR_REQ; + break; + } + ////////////////////// + case CAS_UPT_HEAP_LOCK: // lock the heap + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS) + { + +#if DEBUG_MEMC_CAS + if (m_debug) + { + std::cout << " Get access to the heap" << std::endl; + } +#endif + r_cas_fsm = CAS_UPT_REQ; + } + break; + } + //////////////// + case CAS_UPT_REQ: // send a first update request to CC_SEND FSM + { + assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS) and + "VCI_MEM_CACHE ERROR : bad HEAP allocation"); + + if (!r_cas_to_cc_send_multi_req.read() and !r_cas_to_cc_send_brdcast_req.read()) + { + r_cas_to_cc_send_brdcast_req = false; + r_cas_to_cc_send_trdid = r_cas_upt_index.read(); + r_cas_to_cc_send_nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; + r_cas_to_cc_send_index = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]; + r_cas_to_cc_send_wdata = r_cas_wdata.read(); + + if (r_cas_cpt.read() == 4) + { + r_cas_to_cc_send_is_long = true; + r_cas_to_cc_send_wdata_high = m_cmd_cas_wdata_fifo.read(); + } + else + { + r_cas_to_cc_send_is_long = false; + r_cas_to_cc_send_wdata_high = 0; + } + + // We put the first copy in the fifo + cas_to_cc_send_fifo_put = true; + cas_to_cc_send_fifo_inst = r_cas_copy_inst.read(); + cas_to_cc_send_fifo_srcid = r_cas_copy.read(); + if (r_cas_count.read() == 1) // one single copy + { + r_cas_fsm = CAS_IDLE; // Response will be sent after receiving + // update responses + cmd_cas_fifo_get = true; + r_cas_to_cc_send_multi_req = true; + r_cas_cpt = 0; + } + else // several copies + { + r_cas_fsm = CAS_UPT_NEXT; + } + +#if DEBUG_MEMC_CAS + if (m_debug) + { + std::cout << " Send the first update request to CC_SEND FSM " + << " / address = " << std::hex << m_cmd_cas_addr_fifo.read() + << " / wdata = " << std::hex << r_cas_wdata.read() + << " / srcid = " << std::dec << r_cas_copy.read() + << " / inst = " << std::dec << r_cas_copy_inst.read() << std::endl; + } +#endif + } + break; + } + ///////////////// + case CAS_UPT_NEXT: // send a multi-update request to CC_SEND FSM + { + assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS) + and "VCI_MEM_CACHE ERROR : bad HEAP allocation"); + + HeapEntry entry = m_heap.read(r_cas_ptr.read()); + cas_to_cc_send_fifo_srcid = entry.owner.srcid; + cas_to_cc_send_fifo_inst = entry.owner.inst; + cas_to_cc_send_fifo_put = true; + + if (m_cas_to_cc_send_inst_fifo.wok()) // request accepted by CC_SEND FSM + { + r_cas_ptr = entry.next; + if (entry.next == r_cas_ptr.read()) // last copy + { + r_cas_to_cc_send_multi_req = true; + r_cas_fsm = CAS_IDLE; // Response will be sent after receiving + // all update responses + cmd_cas_fifo_get = true; + r_cas_cpt = 0; + } + } + +#if DEBUG_MEMC_CAS + if (m_debug) + { + std::cout << " Send the next update request to CC_SEND FSM " + << " / address = " << std::hex << m_cmd_cas_addr_fifo.read() + << " / wdata = " << std::hex << r_cas_wdata.read() + << " / srcid = " << std::dec << entry.owner.srcid + << " / inst = " << std::dec << entry.owner.inst << std::endl; + } +#endif + break; + } + ///////////////////// + case CAS_BC_TRT_LOCK: // get TRT lock to check TRT not full + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and + "MEMC ERROR in CAS_BC_TRT_LOCK state: Bas DIR allocation"); + + if (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) + { + size_t wok_index = 0; + bool wok = !m_trt.full(wok_index); + if (wok ) + { + r_cas_trt_index = wok_index; + r_cas_fsm = CAS_BC_IVT_LOCK; + } + else + { + r_cas_fsm = CAS_WAIT; + } + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Check TRT" + << " : wok = " << wok << " / index = " << wok_index << std::endl; +#endif + } + break; + } + ///////////////////// + case CAS_BC_IVT_LOCK: // get IVT lock and register BC transaction in IVT + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and + "MEMC ERROR in CAS_BC_IVT_LOCK state: Bas DIR allocation"); + + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and + "MEMC ERROR in CAS_BC_IVT_LOCK state: Bas TRT allocation"); + + if (r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS ) + { + // register broadcast inval transaction in IVT + bool wok = false; + size_t index = 0; + size_t srcid = m_cmd_cas_srcid_fifo.read(); + size_t trdid = m_cmd_cas_trdid_fifo.read(); + size_t pktid = m_cmd_cas_pktid_fifo.read(); + addr_t nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; + size_t nb_copies = r_cas_count.read(); + + wok = m_ivt.set( false, // it's an inval transaction + true, // it's a broadcast + true, // response required + false, // no acknowledge required + srcid, + trdid, + pktid, + nline, + nb_copies, + index); +#if DEBUG_MEMC_CAS + if (m_debug and wok ) + std::cout << " Register broadcast inval in IVT" + << " / copies = " << r_cas_count.read() << std::endl; +#endif + r_cas_upt_index = index; + if (wok ) r_cas_fsm = CAS_BC_DIR_INVAL; + else r_cas_fsm = CAS_WAIT; + } + break; + } + ////////////////////// + case CAS_BC_DIR_INVAL: // Register PUT transaction in TRT, + // and inval the DIR entry + { + assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and + "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad DIR allocation"); + + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and + "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad TRT allocation"); + + assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS) and + "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad IVT allocation"); + + // set TRT + std::vector data_vector; + data_vector.clear(); + size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]; + for(size_t i=0; i (m_words,0), + data_vector ); + + // invalidate directory entry + DirectoryEntry entry; + entry.valid = false; + entry.dirty = false; + entry.tag = 0; + entry.is_cnt = false; + entry.lock = false; + entry.count = 0; + entry.owner.srcid = 0; + entry.owner.inst = false; + entry.ptr = 0; + size_t set = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())]; + size_t way = r_cas_way.read(); + + m_cache_directory.write(set, way, entry); + + r_cas_fsm = CAS_BC_CC_SEND; + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Inval DIR & register in TRT:" + << " address = " << m_cmd_cas_addr_fifo.read() << std::endl; +#endif + break; + } + /////////////////// + case CAS_BC_CC_SEND: // Request the broadcast inval to CC_SEND FSM + { + if (not r_cas_to_cc_send_multi_req.read() and + not r_cas_to_cc_send_brdcast_req.read()) + { + r_cas_to_cc_send_multi_req = false; + r_cas_to_cc_send_brdcast_req = true; + r_cas_to_cc_send_trdid = r_cas_upt_index.read(); + r_cas_to_cc_send_nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; + r_cas_to_cc_send_index = 0; + r_cas_to_cc_send_wdata = 0; + + r_cas_fsm = CAS_BC_XRAM_REQ; + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Post a broadcast request to CC_SEND FSM" << std::endl; +#endif + } + break; + } + //////////////////// + case CAS_BC_XRAM_REQ: // request the IXR FSM to start a PUT transaction + { + if (not r_cas_to_ixr_cmd_req.read()) + { + r_cas_to_ixr_cmd_req = true; + r_cas_to_ixr_cmd_index = r_cas_trt_index.read(); + r_cas_fsm = CAS_IDLE; + cmd_cas_fifo_get = true; + r_cas_cpt = 0; + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Request a PUT transaction to IXR_CMD FSM" << std::hex + << " / address = " << (addr_t) m_cmd_cas_addr_fifo.read() + << " / trt_index = " << r_cas_trt_index.read() << std::endl; +#endif + } + break; + } + ///////////////// + case CAS_RSP_FAIL: // request TGT_RSP FSM to send a failure response + { + if (not r_cas_to_tgt_rsp_req.read()) + { + cmd_cas_fifo_get = true; + r_cas_cpt = 0; + r_cas_to_tgt_rsp_req = true; + r_cas_to_tgt_rsp_data = 1; + r_cas_to_tgt_rsp_srcid = m_cmd_cas_srcid_fifo.read(); + r_cas_to_tgt_rsp_trdid = m_cmd_cas_trdid_fifo.read(); + r_cas_to_tgt_rsp_pktid = m_cmd_cas_pktid_fifo.read(); + r_cas_fsm = CAS_IDLE; + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Request TGT_RSP to send a failure response" << std::endl; +#endif + } + break; + } + //////////////////// + case CAS_RSP_SUCCESS: // request TGT_RSP FSM to send a success response + { + if (not r_cas_to_tgt_rsp_req.read()) + { + cmd_cas_fifo_get = true; + r_cas_cpt = 0; + r_cas_to_tgt_rsp_req = true; + r_cas_to_tgt_rsp_data = 0; + r_cas_to_tgt_rsp_srcid = m_cmd_cas_srcid_fifo.read(); + r_cas_to_tgt_rsp_trdid = m_cmd_cas_trdid_fifo.read(); + r_cas_to_tgt_rsp_pktid = m_cmd_cas_pktid_fifo.read(); + r_cas_fsm = CAS_IDLE; + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Request TGT_RSP to send a success response" << std::endl; +#endif + } + break; + } + /////////////////////// + case CAS_MISS_TRT_LOCK: // cache miss : request access to transaction Table + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) + { + size_t index = 0; + bool hit_read = m_trt.hit_read( + m_nline[(addr_t) m_cmd_cas_addr_fifo.read()],index); + bool hit_write = m_trt.hit_write( + m_nline[(addr_t) m_cmd_cas_addr_fifo.read()]); + bool wok = not m_trt.full(index); + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Check TRT state" + << " / hit_read = " << hit_read + << " / hit_write = " << hit_write + << " / wok = " << wok + << " / index = " << index << std::endl; +#endif + + if (hit_read or !wok or hit_write) // missing line already requested or TRT full + { + r_cas_fsm = CAS_WAIT; + } + else + { + r_cas_trt_index = index; + r_cas_fsm = CAS_MISS_TRT_SET; + } + } + break; + } + ////////////////////// + case CAS_MISS_TRT_SET: // register the GET transaction in TRT + { + assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and + "MEMC ERROR in CAS_MISS_TRT_SET state: Bad TRT allocation"); + + std::vector be_vector; + std::vector data_vector; + be_vector.clear(); + data_vector.clear(); + for(size_t i=0; i(m_words,0), + std::vector(m_words,0)); + + r_cas_fsm = CAS_MISS_XRAM_REQ; + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Register GET transaction in TRT" + << " / address = " << std::hex << (addr_t)m_cmd_cas_addr_fifo.read() + << " / trt_index = " << std::dec << r_cas_trt_index.read() << std::endl; +#endif + break; + } + ////////////////////// + case CAS_MISS_XRAM_REQ: // request the IXR_CMD FSM a GET request + { + if (not r_cas_to_ixr_cmd_req.read()) + { + r_cas_to_ixr_cmd_req = true; + r_cas_to_ixr_cmd_index = r_cas_trt_index.read(); + r_cas_fsm = CAS_WAIT; + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Request a GET transaction" + << " / address = " << std::hex << (addr_t) m_cmd_cas_addr_fifo.read() + << " / trt_index = " << std::dec << r_cas_trt_index.read() << std::endl; +#endif + } + break; + } + } // end switch r_cas_fsm + + + ////////////////////////////////////////////////////////////////////////////// + // CC_SEND FSM + ////////////////////////////////////////////////////////////////////////////// + // The CC_SEND fsm controls the DSPIN initiator port on the coherence + // network, used to update or invalidate cache lines in L1 caches. + // + // It implements a round-robin priority between the four possible client FSMs + // XRAM_RSP > CAS > WRITE > CONFIG + // + // Each FSM can request the next services: + // - r_xram_rsp_to_cc_send_multi_req : multi-inval + // r_xram_rsp_to_cc_send_brdcast_req : broadcast-inval + // - r_write_to_cc_send_multi_req : multi-update + // r_write_to_cc_send_brdcast_req : broadcast-inval + // - r_cas_to_cc_send_multi_req : multi-update + // r_cas_to_cc_send_brdcast_req : broadcast-inval + // - r_config_to_cc_send_multi_req : multi-inval + // r_config_to_cc_send_brdcast_req : broadcast-inval + // + // An inval request is a double DSPIN flit command containing: + // 1. the index of the line to be invalidated. + // + // An update request is a multi-flit DSPIN command containing: + // 1. the index of the cache line to be updated. + // 2. the index of the first modified word in the line. + // 3. the data to update + /////////////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "cc_send_fsm" << std::endl; + + switch(r_cc_send_fsm.read()) + { + ///////////////////////// + case CC_SEND_CONFIG_IDLE: // XRAM_RSP FSM has highest priority + { + // XRAM_RSP + if (m_xram_rsp_to_cc_send_inst_fifo.rok() or + r_xram_rsp_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER; + break; + } + if (r_xram_rsp_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER; + break; + } + // CAS + if (m_cas_to_cc_send_inst_fifo.rok() or + r_cas_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; + break; + } + if (r_cas_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER; + break; + } + // WRITE + if (m_write_to_cc_send_inst_fifo.rok() or + r_write_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER; + break; + } + if (r_write_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER; + break; + } + // CONFIG + if (r_config_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; + break; + } + if (r_config_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; + break; + } + break; + } + //////////////////////// + case CC_SEND_WRITE_IDLE: // CONFIG FSM has highest priority + { + // CONFIG + if (r_config_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; + break; + } + if (r_config_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; + break; + } + // XRAM_RSP + if (m_xram_rsp_to_cc_send_inst_fifo.rok() or + r_xram_rsp_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER; + break; + } + if (r_xram_rsp_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER; + break; + } + // CAS + if (m_cas_to_cc_send_inst_fifo.rok() or + r_cas_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; + break; + } + if (r_cas_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER; + break; + } + // WRITE + if (m_write_to_cc_send_inst_fifo.rok() or + r_write_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER; + break; + } + if (r_write_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER; + break; + } + break; + } + /////////////////////////// + case CC_SEND_XRAM_RSP_IDLE: // CAS FSM has highest priority + { + // CAS + if (m_cas_to_cc_send_inst_fifo.rok() or + r_cas_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; + break; + } + if (r_cas_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER; + break; + } + // WRITE + if (m_write_to_cc_send_inst_fifo.rok() or + r_write_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER; + break; + } + + if (r_write_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER; + break; + } + // CONFIG + if (r_config_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; + break; + } + if (r_config_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; + break; + } + // XRAM_RSP + if (m_xram_rsp_to_cc_send_inst_fifo.rok() or + r_xram_rsp_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER; + break; + } + if (r_xram_rsp_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER; + break; + } + break; + } + ////////////////////// + case CC_SEND_CAS_IDLE: // CLEANUP FSM has highest priority + { + if (m_write_to_cc_send_inst_fifo.rok() or + r_write_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER; + break; + } + if (r_write_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER; + break; + } + // CONFIG + if (r_config_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; + break; + } + if (r_config_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; + break; + } + if (m_xram_rsp_to_cc_send_inst_fifo.rok() or + r_xram_rsp_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER; + break; + } + if (r_xram_rsp_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER; + break; + } + if (m_cas_to_cc_send_inst_fifo.rok() or + r_cas_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; + break; + } + if (r_cas_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER; + break; + } + break; + } + ///////////////////////////////// + case CC_SEND_CONFIG_INVAL_HEADER: // send first flit multi-inval (from CONFIG FSM) + { + if (m_config_to_cc_send_inst_fifo.rok()) + { + if (not p_dspin_m2p.read) break; + // + if (is_local_req(m_config_to_cc_send_srcid_fifo.read())) + { + m_cpt_minval_local++; + } + else + { + m_cpt_minval_remote++; + m_cpt_minval_cost += req_distance(m_config_to_cc_send_srcid_fifo.read()); + } + // + r_cc_send_fsm = CC_SEND_CONFIG_INVAL_NLINE; + break; + } + if (r_config_to_cc_send_multi_req.read()) r_config_to_cc_send_multi_req = false; + // + m_cpt_minval++; + // + r_cc_send_fsm = CC_SEND_CONFIG_IDLE; + break; + } + //////////////////////////////// + case CC_SEND_CONFIG_INVAL_NLINE: // send second flit multi-inval (from CONFIG FSM) + { + if (not p_dspin_m2p.read) break; + config_to_cc_send_fifo_get = true; + r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; + +#if DEBUG_MEMC_CC_SEND + if (m_debug) + std::cout << " multi-inval for line " + << std::hex << r_config_to_cc_send_nline.read() << std::endl; +#endif + break; + } + /////////////////////////////////// + case CC_SEND_CONFIG_BRDCAST_HEADER: // send first flit BC-inval (from CONFIG FSM) + { + if (not p_dspin_m2p.read) break; + r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_NLINE; + break; + } + ////////////////////////////////// + case CC_SEND_CONFIG_BRDCAST_NLINE: // send second flit BC-inval (from CONFIG FSM) + { + if (not p_dspin_m2p.read) break; + // + m_cpt_binval++; + // + r_config_to_cc_send_brdcast_req = false; + r_cc_send_fsm = CC_SEND_CONFIG_IDLE; + +#if DEBUG_MEMC_CC_SEND + if (m_debug) + std::cout << " BC-Inval for line " + << std::hex << r_config_to_cc_send_nline.read() << std::endl; +#endif + break; + } + /////////////////////////////////// + case CC_SEND_XRAM_RSP_INVAL_HEADER: // send first flit multi-inval (from XRAM_RSP FSM) + { + if (m_xram_rsp_to_cc_send_inst_fifo.rok()) + { + if (not p_dspin_m2p.read) break; + // + if (is_local_req(m_xram_rsp_to_cc_send_srcid_fifo.read())) + { + m_cpt_minval_local++; + } + else + { + m_cpt_minval_remote++; + m_cpt_minval_cost += req_distance(m_xram_rsp_to_cc_send_srcid_fifo.read()); + } + // + r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_NLINE; + break; + } + if (r_xram_rsp_to_cc_send_multi_req.read()) r_xram_rsp_to_cc_send_multi_req = false; + // + m_cpt_minval++; + // + r_cc_send_fsm = CC_SEND_XRAM_RSP_IDLE; + break; + } + ////////////////////////////////// + case CC_SEND_XRAM_RSP_INVAL_NLINE: // send second flit multi-inval (from XRAM_RSP FSM) + { + if (not p_dspin_m2p.read) break; + xram_rsp_to_cc_send_fifo_get = true; + r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER; + +#if DEBUG_MEMC_CC_SEND + if (m_debug) + std::cout << " Multicast-Inval for line " + << std::hex << r_xram_rsp_to_cc_send_nline.read() << std::endl; +#endif + break; + } + ///////////////////////////////////// + case CC_SEND_XRAM_RSP_BRDCAST_HEADER: // send first flit broadcast-inval (from XRAM_RSP FSM) + { + if (not p_dspin_m2p.read) break; + r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_NLINE; + break; + } + //////////////////////////////////// + case CC_SEND_XRAM_RSP_BRDCAST_NLINE: // send second flit broadcast-inval (from XRAM_RSP FSM) + { + if (not p_dspin_m2p.read) break; + // + m_cpt_binval++; + // + r_xram_rsp_to_cc_send_brdcast_req = false; + r_cc_send_fsm = CC_SEND_XRAM_RSP_IDLE; + +#if DEBUG_MEMC_CC_SEND + if (m_debug) + std::cout << " BC-Inval for line " + << std::hex << r_xram_rsp_to_cc_send_nline.read() << std::endl; +#endif + break; + } + ////////////////////////////////// + case CC_SEND_WRITE_BRDCAST_HEADER: // send first flit broadcast-inval (from WRITE FSM) + { + if (not p_dspin_m2p.read) break; + r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_NLINE; + break; + } + ///////////////////////////////// + case CC_SEND_WRITE_BRDCAST_NLINE: // send second flit broadcast-inval (from WRITE FSM) + { + if (not p_dspin_m2p.read) break; + + // + m_cpt_binval++; + m_cpt_write_broadcast++; + // + + r_write_to_cc_send_brdcast_req = false; + r_cc_send_fsm = CC_SEND_WRITE_IDLE; + +#if DEBUG_MEMC_CC_SEND + if (m_debug) + std::cout << " BC-Inval for line " + << std::hex << r_write_to_cc_send_nline.read() << std::endl; +#endif + break; + } + /////////////////////////////// + case CC_SEND_WRITE_UPDT_HEADER: // send first flit for a multi-update (from WRITE FSM) + { + if (m_write_to_cc_send_inst_fifo.rok()) + { + if (not p_dspin_m2p.read) break; + // + if (is_local_req(m_write_to_cc_send_srcid_fifo.read())) + { + m_cpt_update_local++; + } + else + { + m_cpt_update_remote++; + m_cpt_update_cost += req_distance(m_write_to_cc_send_srcid_fifo.read()); + } + // + + r_cc_send_fsm = CC_SEND_WRITE_UPDT_NLINE; + break; + } + + if (r_write_to_cc_send_multi_req.read()) + { + r_write_to_cc_send_multi_req = false; + } + + // + m_cpt_update++; + // + r_cc_send_fsm = CC_SEND_WRITE_IDLE; + break; + } + ////////////////////////////// + case CC_SEND_WRITE_UPDT_NLINE: // send second flit for a multi-update (from WRITE FSM) + { + if (not p_dspin_m2p.read) break; + + r_cc_send_cpt = 0; + r_cc_send_fsm = CC_SEND_WRITE_UPDT_DATA; + +#if DEBUG_MEMC_CC_SEND + if (m_debug) + std::cout << " Multicast-Update for address " + << r_write_to_cc_send_nline.read()*m_words*4 << std::endl; +#endif + break; + } + ///////////////////////////// + case CC_SEND_WRITE_UPDT_DATA: // send data flits for multi-update (from WRITE FSM) + { + if (not p_dspin_m2p.read) break; + if (r_cc_send_cpt.read() == r_write_to_cc_send_count.read()) + { + write_to_cc_send_fifo_get = true; + r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER; + break; + } + + r_cc_send_cpt = r_cc_send_cpt.read() + 1; + break; + } + //////////////////////////////// + case CC_SEND_CAS_BRDCAST_HEADER: // send first flit broadcast-inval (from CAS FSM) + { + if (not p_dspin_m2p.read) break; + r_cc_send_fsm = CC_SEND_CAS_BRDCAST_NLINE; + break; + } + /////////////////////////////// + case CC_SEND_CAS_BRDCAST_NLINE: // send second flit broadcast-inval (from CAS FSM) + { + if (not p_dspin_m2p.read) break; + // + m_cpt_binval++; + // + + r_cas_to_cc_send_brdcast_req = false; + r_cc_send_fsm = CC_SEND_CAS_IDLE; + +#if DEBUG_MEMC_CC_SEND + if (m_debug) + std::cout << " Broadcast-Inval for address: " + << r_cas_to_cc_send_nline.read()*m_words*4 << std::endl; +#endif + break; + } + ///////////////////////////// + case CC_SEND_CAS_UPDT_HEADER: // send first flit for a multi-update (from CAS FSM) + { + if (m_cas_to_cc_send_inst_fifo.rok()) + { + if (not p_dspin_m2p.read) break; + // + if (is_local_req(m_cas_to_cc_send_srcid_fifo.read())) + { + m_cpt_update_local++; + } + else + { + m_cpt_update_remote++; + m_cpt_update_cost += req_distance(m_cas_to_cc_send_srcid_fifo.read()); + } + // + r_cc_send_fsm = CC_SEND_CAS_UPDT_NLINE; + break; + } + + // no more packets to send for the multi-update + if (r_cas_to_cc_send_multi_req.read()) + { + r_cas_to_cc_send_multi_req = false; + } + + // + m_cpt_update++; + // + r_cc_send_fsm = CC_SEND_CAS_IDLE; + break; + } + //////////////////////////// + case CC_SEND_CAS_UPDT_NLINE: // send second flit for a multi-update (from CAS FSM) + { + if (not p_dspin_m2p.read) break; + r_cc_send_cpt = 0; + r_cc_send_fsm = CC_SEND_CAS_UPDT_DATA; + +#if DEBUG_MEMC_CC_SEND + if (m_debug) + std::cout << " Multicast-Update for address " + << r_cas_to_cc_send_nline.read()*m_words*4 << std::endl; +#endif + break; + } + /////////////////////////// + case CC_SEND_CAS_UPDT_DATA: // send first data for a multi-update (from CAS FSM) + { + if (not p_dspin_m2p.read) break; + + if (r_cas_to_cc_send_is_long.read()) + { + r_cc_send_fsm = CC_SEND_CAS_UPDT_DATA_HIGH; + break; + } + + cas_to_cc_send_fifo_get = true; + r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; + break; + } + //////////////////////////////// + case CC_SEND_CAS_UPDT_DATA_HIGH: // send second data for multi-update (from CAS FSM) + { + if (not p_dspin_m2p.read) break; + cas_to_cc_send_fifo_get = true; + r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; + break; + } + } + // end switch r_cc_send_fsm + + ////////////////////////////////////////////////////////////////////////////// + // CC_RECEIVE FSM + ////////////////////////////////////////////////////////////////////////////// + // The CC_RECEIVE fsm controls the DSPIN target port on the coherence + // network. + ////////////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "cc_receive_fsm" << std::endl; + + switch(r_cc_receive_fsm.read()) + { + ///////////////////// + case CC_RECEIVE_IDLE: + { + if (not p_dspin_p2m.write) break; + + uint8_t type = + DspinDhccpParam::dspin_get( + p_dspin_p2m.data.read(), + DspinDhccpParam::P2M_TYPE); + + if ((type == DspinDhccpParam::TYPE_CLEANUP_DATA) or + (type == DspinDhccpParam::TYPE_CLEANUP_INST)) + { + r_cc_receive_fsm = CC_RECEIVE_CLEANUP; + break; + } + + if (type == DspinDhccpParam::TYPE_MULTI_ACK) + { + r_cc_receive_fsm = CC_RECEIVE_MULTI_ACK; + break; + } + + assert(false and + "VCI_MEM_CACHE ERROR in CC_RECEIVE : " + "Illegal type in coherence request"); + + break; + } + //////////////////////// + case CC_RECEIVE_CLEANUP: + { + // write first CLEANUP flit in CC_RECEIVE to CLEANUP fifo + + if (not p_dspin_p2m.write or not m_cc_receive_to_cleanup_fifo.wok()) + break; + + assert(not p_dspin_p2m.eop.read() and + "VCI_MEM_CACHE ERROR in CC_RECEIVE : " + "CLEANUP command must have two flits"); + + cc_receive_to_cleanup_fifo_put = true; + r_cc_receive_fsm = CC_RECEIVE_CLEANUP_EOP; + + // + uint32_t srcid = DspinDhccpParam::dspin_get( + p_dspin_p2m.data.read(), + DspinDhccpParam::CLEANUP_SRCID); + + if (is_local_req(srcid)) { + m_cpt_cleanup_local++; + } + else { + m_cpt_cleanup_remote++; + m_cpt_cleanup_cost += req_distance(srcid); + } + // + + break; + } + //////////////////////////// + case CC_RECEIVE_CLEANUP_EOP: + { + // write second CLEANUP flit in CC_RECEIVE to CLEANUP fifo + + if (not p_dspin_p2m.write or not m_cc_receive_to_cleanup_fifo.wok()) + break; + + assert(p_dspin_p2m.eop.read() and + "VCI_MEM_CACHE ERROR in CC_RECEIVE : " + "CLEANUP command must have two flits"); + + cc_receive_to_cleanup_fifo_put = true; + r_cc_receive_fsm = CC_RECEIVE_IDLE; + + break; + } + + ////////////////////////// + case CC_RECEIVE_MULTI_ACK: + { + // write MULTI_ACK flit in CC_RECEIVE to MULTI_ACK fifo + + // wait for a WOK in the CC_RECEIVE to MULTI_ACK fifo + if (not p_dspin_p2m.write or not m_cc_receive_to_multi_ack_fifo.wok()) + break; + + assert(p_dspin_p2m.eop.read() and + "VCI_MEM_CACHE ERROR in CC_RECEIVE : " + "MULTI_ACK command must have one flit"); + + cc_receive_to_multi_ack_fifo_put = true; + r_cc_receive_fsm = CC_RECEIVE_IDLE; + break; + } + } + + ////////////////////////////////////////////////////////////////////////// + // TGT_RSP FSM + ////////////////////////////////////////////////////////////////////////// + // The TGT_RSP fsm sends the responses on the VCI target port + // with a round robin priority between eigth requests : + // - r_config_to_tgt_rsp_req + // - r_tgt_cmd_to_tgt_rsp_req + // - r_read_to_tgt_rsp_req + // - r_write_to_tgt_rsp_req + // - r_cas_to_tgt_rsp_req + // - r_cleanup_to_tgt_rsp_req + // - r_xram_rsp_to_tgt_rsp_req + // - r_multi_ack_to_tgt_rsp_req + // + // The ordering is : + // config >tgt_cmd > read > write > cas > xram > multi_ack > cleanup + ////////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "tgt_rsp_fsm" << std::endl; + + switch(r_tgt_rsp_fsm.read()) + { + ///////////////////////// + case TGT_RSP_CONFIG_IDLE: // tgt_cmd requests have the highest priority + { + if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + else if (r_read_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_READ; + r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); + } + else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; + else if (r_xram_rsp_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_XRAM; + r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); + } + else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; + else if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + break; + } + ////////////////////////// + case TGT_RSP_TGT_CMD_IDLE: // read requests have the highest priority + { + if (r_read_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_READ; + r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); + } + else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; + else if (r_xram_rsp_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_XRAM; + r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); + } + else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; + else if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + break; + } + /////////////////////// + case TGT_RSP_READ_IDLE: // write requests have the highest priority + { + if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; + else if (r_xram_rsp_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_XRAM; + r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); + } + else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; + else if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + else if (r_read_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_READ; + r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); + } + break; + } + //////////////////////// + case TGT_RSP_WRITE_IDLE: // cas requests have the highest priority + { + if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; + else if (r_xram_rsp_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_XRAM; + r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); + } + else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; + else if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + else if (r_read_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_READ; + r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); + } + else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + break; + } + /////////////////////// + case TGT_RSP_CAS_IDLE: // xram_rsp requests have the highest priority + { + if (r_xram_rsp_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_XRAM; + r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); + } + else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK ; + else if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + else if (r_read_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_READ; + r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); + } + else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; + break; + } + /////////////////////// + case TGT_RSP_XRAM_IDLE: // multi ack requests have the highest priority + { + + if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK ; + else if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + else if (r_read_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_READ; + r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); + } + else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; + else if (r_xram_rsp_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_XRAM; + r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); + } + break; + } + //////////////////////////// + case TGT_RSP_MULTI_ACK_IDLE: // cleanup requests have the highest priority + { + if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + else if (r_read_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_READ; + r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); + } + else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; + else if (r_xram_rsp_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_XRAM; + r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); + } + else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; + break; + } + ////////////////////////// + case TGT_RSP_CLEANUP_IDLE: // tgt cmd requests have the highest priority + { + if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + else if (r_read_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_READ; + r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); + } + else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; + else if (r_xram_rsp_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_XRAM; + r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); + } + else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK ; + else if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + break; + } + //////////////////// + case TGT_RSP_CONFIG: // send the response for a config transaction + { + if (p_vci_tgt.rspack ) + { + r_config_to_tgt_rsp_req = false; + r_tgt_rsp_fsm = TGT_RSP_CONFIG_IDLE; + +#if DEBUG_MEMC_TGT_RSP + if (m_debug ) + { + std::cout + << " Config transaction completed response" + << " / rsrcid = " << std::hex << r_config_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_config_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_config_to_tgt_rsp_pktid.read() + << std::endl; + } +#endif + } + break; + } + ///////////////////// + case TGT_RSP_TGT_CMD: // send the response for a configuration access + { + if (p_vci_tgt.rspack ) + { + r_tgt_cmd_to_tgt_rsp_req = false; + r_tgt_rsp_fsm = TGT_RSP_TGT_CMD_IDLE; + +#if DEBUG_MEMC_TGT_RSP + if (m_debug ) + { + std::cout + << " Send response for a configuration access" + << " / rsrcid = " << std::hex << r_tgt_cmd_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_tgt_cmd_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_tgt_cmd_to_tgt_rsp_pktid.read() + << " / error = " << r_tgt_cmd_to_tgt_rsp_error.read() + << std::endl; + } +#endif + } + break; + } + ////////////////// + case TGT_RSP_READ: // send the response to a read + { + if (p_vci_tgt.rspack ) + { + +#if DEBUG_MEMC_TGT_RSP + if (m_debug ) + { + std::cout + << " Read response" + << " / rsrcid = " << std::hex << r_read_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_read_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_read_to_tgt_rsp_pktid.read() + << " / rdata = " << r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read() + << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl; + } +#endif + + uint32_t last_word_idx = r_read_to_tgt_rsp_word.read() + + r_read_to_tgt_rsp_length.read() - 1; + bool is_last_word = (r_tgt_rsp_cpt.read() == last_word_idx); + bool is_ll = ((r_read_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL); + + if ((is_last_word and not is_ll) or + (r_tgt_rsp_key_sent.read() and is_ll)) + { + // Last word in case of READ or second flit in case if LL + r_tgt_rsp_key_sent = false; + r_read_to_tgt_rsp_req = false; + r_tgt_rsp_fsm = TGT_RSP_READ_IDLE; + } + else + { + if (is_ll) + { + r_tgt_rsp_key_sent = true; // Send second flit of ll + } + else + { + r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1; // Send next word of read + } + } + } + break; + } + ////////////////// + case TGT_RSP_WRITE: // send the write acknowledge + { + if (p_vci_tgt.rspack) + { + +#if DEBUG_MEMC_TGT_RSP + if (m_debug) + std::cout << " Write response" + << " / rsrcid = " << std::hex << r_write_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_write_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_write_to_tgt_rsp_pktid.read() << std::endl; +#endif + r_tgt_rsp_fsm = TGT_RSP_WRITE_IDLE; + r_write_to_tgt_rsp_req = false; + } + break; + } + ///////////////////// + case TGT_RSP_CLEANUP: // pas clair pour moi (AG) + { + if (p_vci_tgt.rspack) + { + +#if DEBUG_MEMC_TGT_RSP + if (m_debug) + std::cout << " Cleanup response" + << " / rsrcid = " << std::hex << r_cleanup_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_cleanup_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_cleanup_to_tgt_rsp_pktid.read() << std::endl; +#endif + r_tgt_rsp_fsm = TGT_RSP_CLEANUP_IDLE; + r_cleanup_to_tgt_rsp_req = false; + } + break; + } + ///////////////// + case TGT_RSP_CAS: // send one atomic word response + { + if (p_vci_tgt.rspack) + { + +#if DEBUG_MEMC_TGT_RSP + if (m_debug) + std::cout << " CAS response" + << " / rsrcid = " << std::hex << r_cas_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_cas_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_cas_to_tgt_rsp_pktid.read() << std::endl; +#endif + r_tgt_rsp_fsm = TGT_RSP_CAS_IDLE; + r_cas_to_tgt_rsp_req = false; + } + break; + } + ////////////////// + case TGT_RSP_XRAM: // send the response after XRAM access + { + if (p_vci_tgt.rspack ) + { + +#if DEBUG_MEMC_TGT_RSP + if (m_debug ) + std::cout << " Response following XRAM access" + << " / rsrcid = " << std::hex << r_xram_rsp_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_xram_rsp_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_xram_rsp_to_tgt_rsp_pktid.read() + << " / rdata = " << r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read() + << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl; +#endif + uint32_t last_word_idx = r_xram_rsp_to_tgt_rsp_word.read() + + r_xram_rsp_to_tgt_rsp_length.read() - 1; + bool is_last_word = (r_tgt_rsp_cpt.read() == last_word_idx); + bool is_ll = ((r_xram_rsp_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL); + bool is_error = r_xram_rsp_to_tgt_rsp_rerror.read(); + + if (((is_last_word or is_error) and not is_ll) or + (r_tgt_rsp_key_sent.read() and is_ll)) + { + // Last word sent in case of READ or second flit sent in case if LL + r_tgt_rsp_key_sent = false; + r_xram_rsp_to_tgt_rsp_req = false; + r_tgt_rsp_fsm = TGT_RSP_XRAM_IDLE; + } + else + { + if (is_ll) + { + r_tgt_rsp_key_sent = true; // Send second flit of ll + } + else + { + r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1; // Send next word of read + } + } + } + break; + } + /////////////////////// + case TGT_RSP_MULTI_ACK: // send the write response after coherence transaction + { + if (p_vci_tgt.rspack) + { + +#if DEBUG_MEMC_TGT_RSP + if (m_debug) + std::cout << " Write response after coherence transaction" + << " / rsrcid = " << std::hex << r_multi_ack_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_multi_ack_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_multi_ack_to_tgt_rsp_pktid.read() << std::endl; +#endif + r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK_IDLE; + r_multi_ack_to_tgt_rsp_req = false; + } + break; + } + } // end switch tgt_rsp_fsm + + //////////////////////////////////////////////////////////////////////////////////// + // ALLOC_UPT FSM + //////////////////////////////////////////////////////////////////////////////////// + // The ALLOC_UPT FSM allocates the access to the Update Table (UPT), + // with a round robin priority between three FSMs, with the following order: + // WRITE -> CAS -> MULTI_ACK + // - The WRITE FSM initiates update transaction and sets a new entry in UPT. + // - The CAS FSM does the same thing as the WRITE FSM. + // - The MULTI_ACK FSM complete those trasactions and erase the UPT entry. + // The resource is always allocated. + ///////////////////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "alloc_upt_fsm" << std::endl; + + switch(r_alloc_upt_fsm.read()) + { + ///////////////////////// + case ALLOC_UPT_WRITE: // allocated to WRITE FSM + if (r_write_fsm.read() != WRITE_UPT_LOCK) + { + if (r_cas_fsm.read() == CAS_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_CAS; + + else if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; + } + break; + + ///////////////////////// + case ALLOC_UPT_CAS: // allocated to CAS FSM + if (r_cas_fsm.read() != CAS_UPT_LOCK) + { + if (r_multi_ack_fsm.read() == MULTI_ACK_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_MULTI_ACK; + + else if (r_write_fsm.read() == WRITE_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_WRITE; + } + break; + + ///////////////////////// + case ALLOC_UPT_MULTI_ACK: // allocated to MULTI_ACK FSM + if (r_multi_ack_fsm.read() != MULTI_ACK_UPT_LOCK) + { + if (r_write_fsm.read() == WRITE_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_WRITE; + + else if (r_cas_fsm.read() == CAS_UPT_LOCK) + r_alloc_upt_fsm = ALLOC_UPT_CAS; + } + break; + } // end switch r_alloc_upt_fsm + + //////////////////////////////////////////////////////////////////////////////////// + // ALLOC_IVT FSM + //////////////////////////////////////////////////////////////////////////////////// + // The ALLOC_IVT FSM allocates the access to the Invalidate Table (IVT), + // with a round robin priority between five FSMs, with the following order: + // WRITE -> XRAM_RSP -> CLEANUP -> CAS -> CONFIG + // - The WRITE FSM initiates broadcast invalidate transactions and sets a new entry + // in IVT. + // - The CAS FSM does the same thing as the WRITE FSM. + // - The XRAM_RSP FSM initiates broadcast/multicast invalidate transaction and sets + // a new entry in the IVT + // - The CONFIG FSM does the same thing as the XRAM_RSP FSM + // - The CLEANUP FSM complete those trasactions and erase the IVT entry. + // The resource is always allocated. + ///////////////////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "alloc_ivt_fsm" << std::endl; + + switch(r_alloc_ivt_fsm.read()) + { + ///////////////////// + case ALLOC_IVT_WRITE: // allocated to WRITE FSM + if (r_write_fsm.read() != WRITE_BC_IVT_LOCK) + { + if (r_xram_rsp_fsm.read() == XRAM_RSP_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; + + else if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; + + else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CAS; + + else if (r_config_fsm.read() == CONFIG_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; + } + break; + + //////////////////////// + case ALLOC_IVT_XRAM_RSP: // allocated to XRAM_RSP FSM + if (r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK) + { + if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; + + else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CAS; + + else if (r_config_fsm.read() == CONFIG_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; + + else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_WRITE; + } + break; + + /////////////////////// + case ALLOC_IVT_CLEANUP: // allocated to CLEANUP FSM + if ((r_cleanup_fsm.read() != CLEANUP_IVT_LOCK ) and + (r_cleanup_fsm.read() != CLEANUP_IVT_DECREMENT)) + { + if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CAS; + + else if (r_config_fsm.read() == CONFIG_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; + + else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_WRITE; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; + } + break; + + ////////////////////////// + case ALLOC_IVT_CAS: // allocated to CAS FSM + if (r_cas_fsm.read() != CAS_BC_IVT_LOCK) + { + if (r_config_fsm.read() == CONFIG_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; + + else if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_WRITE; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; + + else if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; + } + break; + + ////////////////////////// + case ALLOC_IVT_CONFIG: // allocated to CONFIG FSM + if (r_config_fsm.read() != CONFIG_IVT_LOCK) + { + if (r_write_fsm.read() == WRITE_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_WRITE; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; + + else if (r_cleanup_fsm.read() == CLEANUP_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; + + else if (r_cas_fsm.read() == CAS_BC_IVT_LOCK) + r_alloc_ivt_fsm = ALLOC_IVT_CAS; + } + break; + + } // end switch r_alloc_ivt_fsm + + //////////////////////////////////////////////////////////////////////////////////// + // ALLOC_DIR FSM + //////////////////////////////////////////////////////////////////////////////////// + // The ALLOC_DIR FSM allocates the access to the directory and + // the data cache with a round robin priority between 6 user FSMs : + // The cyclic ordering is CONFIG > READ > WRITE > CAS > CLEANUP > XRAM_RSP + // The ressource is always allocated. + ///////////////////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "alloc_dir_fsm" << std::endl; + + switch(r_alloc_dir_fsm.read()) + { + ///////////////////// + case ALLOC_DIR_RESET: // Initializes the directory one SET per cycle. + // All the WAYS of a SET initialized in parallel + + r_alloc_dir_reset_cpt.write(r_alloc_dir_reset_cpt.read() + 1); + + if (r_alloc_dir_reset_cpt.read() == (m_sets - 1)) + { + m_cache_directory.init(); + r_alloc_dir_fsm = ALLOC_DIR_READ; + } + break; + + ////////////////////// + case ALLOC_DIR_CONFIG: // allocated to CONFIG FSM + if ((r_config_fsm.read() != CONFIG_DIR_REQ) and + (r_config_fsm.read() != CONFIG_DIR_ACCESS) and + (r_config_fsm.read() != CONFIG_TRT_LOCK) and + (r_config_fsm.read() != CONFIG_TRT_SET) and + (r_config_fsm.read() != CONFIG_IVT_LOCK)) + { + if (r_read_fsm.read() == READ_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_READ; + + else if (r_write_fsm.read() == WRITE_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_WRITE; + + else if (r_cas_fsm.read() == CAS_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CAS; + + else if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) + r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; + } + break; + + //////////////////// + case ALLOC_DIR_READ: // allocated to READ FSM + if (((r_read_fsm.read() != READ_DIR_REQ) and + (r_read_fsm.read() != READ_DIR_LOCK) and + (r_read_fsm.read() != READ_TRT_LOCK) and + (r_read_fsm.read() != READ_HEAP_REQ)) + or + ((r_read_fsm.read() == READ_TRT_LOCK) and + (r_alloc_trt_fsm.read() == ALLOC_TRT_READ))) + { + if (r_write_fsm.read() == WRITE_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_WRITE; + + else if (r_cas_fsm.read() == CAS_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CAS; + + else if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) + r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; + + else if (r_config_fsm.read() == CONFIG_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CONFIG; + } + break; + + ///////////////////// + case ALLOC_DIR_WRITE: // allocated to WRITE FSM + if (((r_write_fsm.read() != WRITE_DIR_REQ) and + (r_write_fsm.read() != WRITE_DIR_LOCK) and + (r_write_fsm.read() != WRITE_BC_DIR_READ) and + (r_write_fsm.read() != WRITE_DIR_HIT) and + (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and + (r_write_fsm.read() != WRITE_BC_IVT_LOCK) and + (r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and + (r_write_fsm.read() != WRITE_UPT_LOCK) and + (r_write_fsm.read() != WRITE_UPT_HEAP_LOCK)) + or + ((r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) and + (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE)) + or + ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) and + (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE))) + { + if (r_cas_fsm.read() == CAS_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CAS; + + else if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) + r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; + + else if (r_config_fsm.read() == CONFIG_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CONFIG; + + else if (r_read_fsm.read() == READ_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_READ; + } + break; + + /////////////////// + case ALLOC_DIR_CAS: // allocated to CAS FSM + if (((r_cas_fsm.read() != CAS_DIR_REQ) and + (r_cas_fsm.read() != CAS_DIR_LOCK) and + (r_cas_fsm.read() != CAS_DIR_HIT_READ) and + (r_cas_fsm.read() != CAS_DIR_HIT_COMPARE) and + (r_cas_fsm.read() != CAS_DIR_HIT_WRITE) and + (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and + (r_cas_fsm.read() != CAS_BC_IVT_LOCK) and + (r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and + (r_cas_fsm.read() != CAS_UPT_LOCK) and + (r_cas_fsm.read() != CAS_UPT_HEAP_LOCK)) + or + ((r_cas_fsm.read() == CAS_UPT_HEAP_LOCK) and + (r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS)) + or + ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) and + (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS))) + { + if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) + r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; + + else if (r_config_fsm.read() == CONFIG_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CONFIG; + + else if (r_read_fsm.read() == READ_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_READ; + + else if (r_write_fsm.read() == WRITE_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_WRITE; + } + break; + + /////////////////////// + case ALLOC_DIR_CLEANUP: // allocated to CLEANUP FSM + if ((r_cleanup_fsm.read() != CLEANUP_DIR_REQ) and + (r_cleanup_fsm.read() != CLEANUP_DIR_LOCK) and + (r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) and + (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK)) + { + if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) + r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; + + else if (r_config_fsm.read() == CONFIG_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CONFIG; + + else if (r_read_fsm.read() == READ_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_READ; + + else if (r_write_fsm.read() == WRITE_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_WRITE; + + else if (r_cas_fsm.read() == CAS_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CAS; + } + break; + + //////////////////////// + case ALLOC_DIR_XRAM_RSP: // allocated to XRAM_RSP FSM + if ((r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) and + (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) and + (r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK)) + { + if (r_config_fsm.read() == CONFIG_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CONFIG; + + else if (r_read_fsm.read() == READ_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_READ; + + else if (r_write_fsm.read() == WRITE_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_WRITE; + + else if (r_cas_fsm.read() == CAS_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CAS; + + else if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ) + r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; + } + break; + + } // end switch alloc_dir_fsm + + //////////////////////////////////////////////////////////////////////////////////// + // ALLOC_TRT FSM + //////////////////////////////////////////////////////////////////////////////////// + // The ALLOC_TRT fsm allocates the access to the Transaction Table (write buffer) + // with a round robin priority between 7 user FSMs : + // The priority is READ > WRITE > CAS > IXR_CMD > XRAM_RSP > IXR_RSP > CONFIG + // The ressource is always allocated. + /////////////////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "alloc_trt_fsm" << std::endl; + + switch(r_alloc_trt_fsm.read()) + { + //////////////////// + case ALLOC_TRT_READ: + if (r_read_fsm.read() != READ_TRT_LOCK) + { + if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or + (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_WRITE; + + else if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or + (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_CAS; + + else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; + + else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and + (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) + r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; + + else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or + (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; + + else if (r_config_fsm.read() == CONFIG_TRT_LOCK ) + r_alloc_trt_fsm = ALLOC_TRT_CONFIG; + } + break; + + ///////////////////// + case ALLOC_TRT_WRITE: + if ((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and + (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and + (r_write_fsm.read() != WRITE_BC_IVT_LOCK)) + { + if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or + (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_CAS; + + else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; + + else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and + (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) + r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; + + else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or + (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; + + else if (r_config_fsm.read() == CONFIG_TRT_LOCK ) + r_alloc_trt_fsm = ALLOC_TRT_CONFIG; + + else if (r_read_fsm.read() == READ_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_READ; + } + break; + + /////////////////// + case ALLOC_TRT_CAS: + if ((r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and + (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and + (r_cas_fsm.read() != CAS_BC_IVT_LOCK)) + { + if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; + + else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and + (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) + r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; + + else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or + (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; + + else if (r_config_fsm.read() == CONFIG_TRT_LOCK ) + r_alloc_trt_fsm = ALLOC_TRT_CONFIG; + + else if (r_read_fsm.read() == READ_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_READ; + + else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or + (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_WRITE; + } + break; + + /////////////////////// + case ALLOC_TRT_IXR_CMD: + if ((r_ixr_cmd_fsm.read() != IXR_CMD_READ_TRT) and + (r_ixr_cmd_fsm.read() != IXR_CMD_WRITE_TRT) and + (r_ixr_cmd_fsm.read() != IXR_CMD_CAS_TRT) and + (r_ixr_cmd_fsm.read() != IXR_CMD_XRAM_TRT) and + (r_ixr_cmd_fsm.read() != IXR_CMD_CONFIG_TRT)) + { + if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and + (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) + r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; + + else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or + (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; + + else if (r_config_fsm.read() == CONFIG_TRT_LOCK ) + r_alloc_trt_fsm = ALLOC_TRT_CONFIG; + + else if (r_read_fsm.read() == READ_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_READ; + + else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or + (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_WRITE; + + else if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or + (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_CAS; + } + break; + + //////////////////////// + case ALLOC_TRT_XRAM_RSP: + if (((r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) or + (r_alloc_dir_fsm.read() != ALLOC_DIR_XRAM_RSP)) and + (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) and + (r_xram_rsp_fsm.read() != XRAM_RSP_DIR_UPDT) and + (r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK)) + { + if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or + (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; + + else if (r_config_fsm.read() == CONFIG_TRT_LOCK ) + r_alloc_trt_fsm = ALLOC_TRT_CONFIG; + + else if (r_read_fsm.read() == READ_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_READ; + + else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or + (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_WRITE; + + else if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or + (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_CAS; + + else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; + + } + break; + + /////////////////////// + case ALLOC_TRT_IXR_RSP: + if ((r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE) and + (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ)) + { + if (r_config_fsm.read() == CONFIG_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_CONFIG; + + else if (r_read_fsm.read() == READ_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_READ; + + else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or + (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_WRITE; + + else if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or + (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_CAS; + + else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; + + else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and + (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) + r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; + } + break; + + ////////////////////// + case ALLOC_TRT_CONFIG: + if ((r_config_fsm.read() != CONFIG_TRT_LOCK) and + (r_config_fsm.read() != CONFIG_TRT_SET)) + { + if (r_read_fsm.read() == READ_TRT_LOCK) + r_alloc_trt_fsm = ALLOC_TRT_READ; + + else if ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) or + (r_write_fsm.read() == WRITE_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_WRITE; + + else if ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) or + (r_cas_fsm.read() == CAS_BC_TRT_LOCK)) + r_alloc_trt_fsm = ALLOC_TRT_CAS; + + else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_TRT) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; + + else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and + (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) + r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; + + else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or + (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) + r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; + } + break; + + } // end switch alloc_trt_fsm + + //////////////////////////////////////////////////////////////////////////////////// + // ALLOC_HEAP FSM + //////////////////////////////////////////////////////////////////////////////////// + // The ALLOC_HEAP FSM allocates the access to the heap + // with a round robin priority between 6 user FSMs : + // The cyclic ordering is READ > WRITE > CAS > CLEANUP > XRAM_RSP > CONFIG + // The ressource is always allocated. + ///////////////////////////////////////////////////////////////////////////////////// + + //std::cout << std::endl << "alloc_heap_fsm" << std::endl; + + switch (r_alloc_heap_fsm.read()) + { + //////////////////// + case ALLOC_HEAP_RESET: + // Initializes the heap one ENTRY each cycle. + + r_alloc_heap_reset_cpt.write(r_alloc_heap_reset_cpt.read() + 1); + + if (r_alloc_heap_reset_cpt.read() == (m_heap_size - 1)) + { + m_heap.init(); + + r_alloc_heap_fsm = ALLOC_HEAP_READ; + } + break; + + //////////////////// + case ALLOC_HEAP_READ: + if ((r_read_fsm.read() != READ_HEAP_REQ) and + (r_read_fsm.read() != READ_HEAP_LOCK) and + (r_read_fsm.read() != READ_HEAP_ERASE)) + { + if (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) + r_alloc_heap_fsm = ALLOC_HEAP_WRITE; + + else if (r_cas_fsm.read() == CAS_UPT_HEAP_LOCK) + r_alloc_heap_fsm = ALLOC_HEAP_CAS; + + else if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; + + else if (r_config_fsm.read() == CONFIG_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; + } + break; + + ///////////////////// + case ALLOC_HEAP_WRITE: + if ((r_write_fsm.read() != WRITE_UPT_HEAP_LOCK) and + (r_write_fsm.read() != WRITE_UPT_REQ) and + (r_write_fsm.read() != WRITE_UPT_NEXT)) + { + if (r_cas_fsm.read() == CAS_UPT_HEAP_LOCK) + r_alloc_heap_fsm = ALLOC_HEAP_CAS; + + else if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; + + else if (r_config_fsm.read() == CONFIG_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; + + else if (r_read_fsm.read() == READ_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_READ; + } + break; + + //////////////////// + case ALLOC_HEAP_CAS: + if ((r_cas_fsm.read() != CAS_UPT_HEAP_LOCK) and + (r_cas_fsm.read() != CAS_UPT_REQ) and + (r_cas_fsm.read() != CAS_UPT_NEXT)) + { + if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; + + else if (r_config_fsm.read() == CONFIG_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; + + else if (r_read_fsm.read() == READ_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_READ; + + else if (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) + r_alloc_heap_fsm = ALLOC_HEAP_WRITE; + } + break; + + /////////////////////// + case ALLOC_HEAP_CLEANUP: + if ((r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) and + (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK) and + (r_cleanup_fsm.read() != CLEANUP_HEAP_SEARCH) and + (r_cleanup_fsm.read() != CLEANUP_HEAP_CLEAN)) + { + if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; + + else if (r_config_fsm.read() == CONFIG_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; + + else if (r_read_fsm.read() == READ_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_READ; + + else if (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) + r_alloc_heap_fsm = ALLOC_HEAP_WRITE; + + else if (r_cas_fsm.read() == CAS_UPT_HEAP_LOCK) + r_alloc_heap_fsm = ALLOC_HEAP_CAS; + } + break; + + //////////////////////// + case ALLOC_HEAP_XRAM_RSP: + if ((r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_REQ) and + (r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_ERASE)) + { + if (r_config_fsm.read() == CONFIG_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; + + else if (r_read_fsm.read() == READ_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_READ; + + else if (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) + r_alloc_heap_fsm = ALLOC_HEAP_WRITE; + + else if (r_cas_fsm.read() == CAS_UPT_HEAP_LOCK) + r_alloc_heap_fsm = ALLOC_HEAP_CAS; + + else if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; + + } + break; + + /////////////////////// + case ALLOC_HEAP_CONFIG: + if ((r_config_fsm.read() != CONFIG_HEAP_REQ) and + (r_config_fsm.read() != CONFIG_HEAP_SCAN)) + { + if (r_read_fsm.read() == READ_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_READ; + + else if (r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) + r_alloc_heap_fsm = ALLOC_HEAP_WRITE; + + else if (r_cas_fsm.read() == CAS_UPT_HEAP_LOCK) + r_alloc_heap_fsm = ALLOC_HEAP_CAS; + + else if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; + + else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ) + r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; + } + break; + + } // end switch alloc_heap_fsm + + //std::cout << std::endl << "fifo_update" << std::endl; + + ///////////////////////////////////////////////////////////////////// + // TGT_CMD to READ FIFO + ///////////////////////////////////////////////////////////////////// + + m_cmd_read_addr_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, + p_vci_tgt.address.read()); + m_cmd_read_length_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, + p_vci_tgt.plen.read() >> 2 ); + m_cmd_read_srcid_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, + p_vci_tgt.srcid.read()); + m_cmd_read_trdid_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, + p_vci_tgt.trdid.read()); + m_cmd_read_pktid_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, + p_vci_tgt.pktid.read()); + + ///////////////////////////////////////////////////////////////////// + // TGT_CMD to WRITE FIFO + ///////////////////////////////////////////////////////////////////// + + m_cmd_write_addr_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put, + (addr_t)p_vci_tgt.address.read()); + m_cmd_write_eop_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put, + p_vci_tgt.eop.read()); + m_cmd_write_srcid_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put, + p_vci_tgt.srcid.read()); + m_cmd_write_trdid_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put, + p_vci_tgt.trdid.read()); + m_cmd_write_pktid_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put, + p_vci_tgt.pktid.read()); + m_cmd_write_data_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put, + p_vci_tgt.wdata.read()); + m_cmd_write_be_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put, + p_vci_tgt.be.read()); + + //////////////////////////////////////////////////////////////////////////////////// + // TGT_CMD to CAS FIFO + //////////////////////////////////////////////////////////////////////////////////// + + m_cmd_cas_addr_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put, + (addr_t)p_vci_tgt.address.read()); + m_cmd_cas_eop_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put, + p_vci_tgt.eop.read()); + m_cmd_cas_srcid_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put, + p_vci_tgt.srcid.read()); + m_cmd_cas_trdid_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put, + p_vci_tgt.trdid.read()); + m_cmd_cas_pktid_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put, + p_vci_tgt.pktid.read()); + m_cmd_cas_wdata_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put, + p_vci_tgt.wdata.read()); + + //////////////////////////////////////////////////////////////////////////////////// + // CC_RECEIVE to CLEANUP FIFO + //////////////////////////////////////////////////////////////////////////////////// + + m_cc_receive_to_cleanup_fifo.update( cc_receive_to_cleanup_fifo_get, + cc_receive_to_cleanup_fifo_put, + p_dspin_p2m.data.read()); + + //////////////////////////////////////////////////////////////////////////////////// + // CC_RECEIVE to MULTI_ACK FIFO + //////////////////////////////////////////////////////////////////////////////////// + + m_cc_receive_to_multi_ack_fifo.update( cc_receive_to_multi_ack_fifo_get, + cc_receive_to_multi_ack_fifo_put, + p_dspin_p2m.data.read()); + + //////////////////////////////////////////////////////////////////////////////////// + // WRITE to CC_SEND FIFO + //////////////////////////////////////////////////////////////////////////////////// + + m_write_to_cc_send_inst_fifo.update( write_to_cc_send_fifo_get, + write_to_cc_send_fifo_put, + write_to_cc_send_fifo_inst ); + m_write_to_cc_send_srcid_fifo.update( write_to_cc_send_fifo_get, + write_to_cc_send_fifo_put, + write_to_cc_send_fifo_srcid ); + + //////////////////////////////////////////////////////////////////////////////////// + // CONFIG to CC_SEND FIFO + //////////////////////////////////////////////////////////////////////////////////// + + m_config_to_cc_send_inst_fifo.update( config_to_cc_send_fifo_get, + config_to_cc_send_fifo_put, + config_to_cc_send_fifo_inst ); + m_config_to_cc_send_srcid_fifo.update( config_to_cc_send_fifo_get, + config_to_cc_send_fifo_put, + config_to_cc_send_fifo_srcid ); + + //////////////////////////////////////////////////////////////////////////////////// + // XRAM_RSP to CC_SEND FIFO + //////////////////////////////////////////////////////////////////////////////////// + + m_xram_rsp_to_cc_send_inst_fifo.update( xram_rsp_to_cc_send_fifo_get, + xram_rsp_to_cc_send_fifo_put, + xram_rsp_to_cc_send_fifo_inst ); + m_xram_rsp_to_cc_send_srcid_fifo.update( xram_rsp_to_cc_send_fifo_get, + xram_rsp_to_cc_send_fifo_put, + xram_rsp_to_cc_send_fifo_srcid ); + + //////////////////////////////////////////////////////////////////////////////////// + // CAS to CC_SEND FIFO + //////////////////////////////////////////////////////////////////////////////////// + + m_cas_to_cc_send_inst_fifo.update( cas_to_cc_send_fifo_get, + cas_to_cc_send_fifo_put, + cas_to_cc_send_fifo_inst ); + m_cas_to_cc_send_srcid_fifo.update( cas_to_cc_send_fifo_get, + cas_to_cc_send_fifo_put, + cas_to_cc_send_fifo_srcid ); + m_cpt_cycles++; + + //////////////////////////////////////////////////////////////////////////////////// + // Update r_config_rsp_lines counter. + // The three sources of (increment / decrement) are CONFIG / CLEANUP / IXR_RSP FSMs + //////////////////////////////////////////////////////////////////////////////////// + if ( config_rsp_lines_incr and not + (config_rsp_lines_cleanup_decr or config_rsp_lines_ixr_rsp_decr) ) + { + r_config_rsp_lines = r_config_rsp_lines.read() + 1; + } + if ( not config_rsp_lines_incr and + (config_rsp_lines_cleanup_decr or config_rsp_lines_ixr_rsp_decr) ) + { + r_config_rsp_lines = r_config_rsp_lines.read() - 1; + } + + } // end transition() + + ///////////////////////////// + tmpl(void)::genMoore() + ///////////////////////////// + { +#if MONITOR_MEMCACHE_FSM == 1 + p_read_fsm.write (r_read_fsm.read() ); + p_write_fsm.write (r_write_fsm.read() ); + p_xram_rsp_fsm.write (r_xram_rsp_fsm.read() ); + p_cas_fsm.write (r_cas_fsm.read() ); + p_cleanup_fsm.write (r_cleanup_fsm.read() ); + p_config_fsm.write (r_config_fsm.read() ); + p_alloc_heap_fsm.write (r_alloc_heap_fsm.read() ); + p_alloc_dir_fsm.write (r_alloc_dir_fsm.read() ); + p_alloc_trt_fsm.write (r_alloc_trt_fsm.read() ); + p_alloc_upt_fsm.write (r_alloc_upt_fsm.read() ); + p_alloc_ivt_fsm.write (r_alloc_ivt_fsm.read() ); + p_tgt_cmd_fsm.write (r_tgt_cmd_fsm.read() ); + p_tgt_rsp_fsm.write (r_tgt_rsp_fsm.read() ); + p_ixr_cmd_fsm.write (r_ixr_cmd_fsm.read() ); + p_ixr_rsp_fsm.write (r_ixr_rsp_fsm.read() ); + p_cc_send_fsm.write (r_cc_send_fsm.read() ); + p_cc_receive_fsm.write (r_cc_receive_fsm.read() ); + p_multi_ack_fsm.write (r_multi_ack_fsm.read() ); +#endif + + //////////////////////////////////////////////////////////// + // Command signals on the p_vci_ixr port + //////////////////////////////////////////////////////////// + + // DATA width is 8 bytes + // The following values are not transmitted to XRAM + // p_vci_ixr.be + // p_vci_ixr.pktid + // p_vci_ixr.cons + // p_vci_ixr.wrap + // p_vci_ixr.contig + // p_vci_ixr.clen + // p_vci_ixr.cfixed + + p_vci_ixr.plen = 64; + p_vci_ixr.srcid = m_srcid_x; + p_vci_ixr.trdid = r_ixr_cmd_trdid.read(); + p_vci_ixr.address = (addr_t)r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2); + p_vci_ixr.be = 0xFF; + p_vci_ixr.pktid = 0; + p_vci_ixr.cons = false; + p_vci_ixr.wrap = false; + p_vci_ixr.contig = true; + p_vci_ixr.clen = 0; + p_vci_ixr.cfixed = false; + + if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_SEND) or + (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_SEND) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_SEND) or + (r_ixr_cmd_fsm.read() == IXR_CMD_XRAM_SEND) or + (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_SEND)) + { + p_vci_ixr.cmdval = true; + + if (r_ixr_cmd_get.read()) // GET + { + p_vci_ixr.cmd = vci_param_ext::CMD_READ; + p_vci_ixr.wdata = 0; + p_vci_ixr.eop = true; + } + else // PUT + { + size_t word = r_ixr_cmd_word.read(); + p_vci_ixr.cmd = vci_param_ext::CMD_WRITE; + p_vci_ixr.wdata = ((wide_data_t)(r_ixr_cmd_wdata[word].read())) | + ((wide_data_t)(r_ixr_cmd_wdata[word+1].read()) << 32); + p_vci_ixr.eop = (word == (m_words-2)); + } + } + else + { + p_vci_ixr.cmdval = false; + } + + //////////////////////////////////////////////////// + // Response signals on the p_vci_ixr port + //////////////////////////////////////////////////// + + if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ) or + (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE)) + { + p_vci_ixr.rspack = (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP); + } + else // r_ixr_rsp_fsm == IXR_RSP_IDLE + { + p_vci_ixr.rspack = false; + } + + //////////////////////////////////////////////////// + // Command signals on the p_vci_tgt port + //////////////////////////////////////////////////// + + switch((tgt_cmd_fsm_state_e) r_tgt_cmd_fsm.read()) + { + case TGT_CMD_IDLE: + p_vci_tgt.cmdack = false; + break; + + case TGT_CMD_CONFIG: + { + addr_t addr_lsb = p_vci_tgt.address.read() & + m_config_addr_mask; + + addr_t cell = (addr_lsb / vci_param_int::B); + + size_t regr = cell & + m_config_regr_idx_mask; + + size_t func = (cell >> m_config_regr_width) & + m_config_func_idx_mask; + + switch(func) + { + case MEMC_CONFIG: + if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) + and (regr == MEMC_CMD_TYPE)) + { + p_vci_tgt.cmdack = true; + } + else + { + p_vci_tgt.cmdack = not r_tgt_cmd_to_tgt_rsp_req.read(); + } + break; + + default: + p_vci_tgt.cmdack = not r_tgt_cmd_to_tgt_rsp_req.read(); + break; + } + + break; + } + case TGT_CMD_ERROR: + p_vci_tgt.cmdack = not r_tgt_cmd_to_tgt_rsp_req.read(); + break; + + case TGT_CMD_READ: + p_vci_tgt.cmdack = m_cmd_read_addr_fifo.wok(); + break; + + case TGT_CMD_WRITE: + p_vci_tgt.cmdack = m_cmd_write_addr_fifo.wok(); + break; + + case TGT_CMD_CAS: + p_vci_tgt.cmdack = m_cmd_cas_addr_fifo.wok(); + break; + } + + //////////////////////////////////////////////////// + // Response signals on the p_vci_tgt port + //////////////////////////////////////////////////// + + switch(r_tgt_rsp_fsm.read()) + { + case TGT_RSP_CONFIG_IDLE: + case TGT_RSP_TGT_CMD_IDLE: + case TGT_RSP_READ_IDLE: + case TGT_RSP_WRITE_IDLE: + case TGT_RSP_CAS_IDLE: + case TGT_RSP_XRAM_IDLE: + case TGT_RSP_MULTI_ACK_IDLE: + case TGT_RSP_CLEANUP_IDLE: + { + p_vci_tgt.rspval = false; + p_vci_tgt.rsrcid = 0; + p_vci_tgt.rdata = 0; + p_vci_tgt.rpktid = 0; + p_vci_tgt.rtrdid = 0; + p_vci_tgt.rerror = 0; + p_vci_tgt.reop = false; + break; + } + case TGT_RSP_CONFIG: + { + p_vci_tgt.rspval = true; + p_vci_tgt.rdata = 0; + p_vci_tgt.rsrcid = r_config_to_tgt_rsp_srcid.read(); + p_vci_tgt.rtrdid = r_config_to_tgt_rsp_trdid.read(); + p_vci_tgt.rpktid = r_config_to_tgt_rsp_pktid.read(); + p_vci_tgt.rerror = r_config_to_tgt_rsp_error.read(); + p_vci_tgt.reop = true; + + break; + } + case TGT_RSP_TGT_CMD: + { + p_vci_tgt.rspval = true; + p_vci_tgt.rdata = r_tgt_cmd_to_tgt_rsp_rdata.read(); + p_vci_tgt.rsrcid = r_tgt_cmd_to_tgt_rsp_srcid.read(); + p_vci_tgt.rtrdid = r_tgt_cmd_to_tgt_rsp_trdid.read(); + p_vci_tgt.rpktid = r_tgt_cmd_to_tgt_rsp_pktid.read(); + p_vci_tgt.rerror = r_tgt_cmd_to_tgt_rsp_error.read(); + p_vci_tgt.reop = true; + + break; + } + case TGT_RSP_READ: + { + uint32_t last_word_idx = r_read_to_tgt_rsp_word.read() + r_read_to_tgt_rsp_length - 1; + bool is_last_word = (r_tgt_rsp_cpt.read() == last_word_idx); + bool is_ll = ((r_read_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL); + + p_vci_tgt.rspval = true; + + if (is_ll and not r_tgt_rsp_key_sent.read()) + { + // LL response first flit + p_vci_tgt.rdata = r_read_to_tgt_rsp_ll_key.read(); + } + else + { + // LL response second flit or READ response + p_vci_tgt.rdata = r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read(); + } + + p_vci_tgt.rsrcid = r_read_to_tgt_rsp_srcid.read(); + p_vci_tgt.rtrdid = r_read_to_tgt_rsp_trdid.read(); + p_vci_tgt.rpktid = r_read_to_tgt_rsp_pktid.read(); + p_vci_tgt.rerror = 0; + p_vci_tgt.reop = (is_last_word and not is_ll) or (r_tgt_rsp_key_sent.read() and is_ll); + break; + } + + case TGT_RSP_WRITE: + p_vci_tgt.rspval = true; + if (((r_write_to_tgt_rsp_pktid.read() & 0x7) == TYPE_SC) and r_write_to_tgt_rsp_sc_fail.read()) + p_vci_tgt.rdata = 1; + else + p_vci_tgt.rdata = 0; + p_vci_tgt.rsrcid = r_write_to_tgt_rsp_srcid.read(); + p_vci_tgt.rtrdid = r_write_to_tgt_rsp_trdid.read(); + p_vci_tgt.rpktid = r_write_to_tgt_rsp_pktid.read(); + p_vci_tgt.rerror = 0; + p_vci_tgt.reop = true; + break; + + case TGT_RSP_CLEANUP: + p_vci_tgt.rspval = true; + p_vci_tgt.rdata = 0; + p_vci_tgt.rsrcid = r_cleanup_to_tgt_rsp_srcid.read(); + p_vci_tgt.rtrdid = r_cleanup_to_tgt_rsp_trdid.read(); + p_vci_tgt.rpktid = r_cleanup_to_tgt_rsp_pktid.read(); + p_vci_tgt.rerror = 0; // Can be a CAS rsp + p_vci_tgt.reop = true; + break; + + case TGT_RSP_CAS: + p_vci_tgt.rspval = true; + p_vci_tgt.rdata = r_cas_to_tgt_rsp_data.read(); + p_vci_tgt.rsrcid = r_cas_to_tgt_rsp_srcid.read(); + p_vci_tgt.rtrdid = r_cas_to_tgt_rsp_trdid.read(); + p_vci_tgt.rpktid = r_cas_to_tgt_rsp_pktid.read(); + p_vci_tgt.rerror = 0; + p_vci_tgt.reop = true; + break; + + case TGT_RSP_XRAM: + { + uint32_t last_word_idx = r_xram_rsp_to_tgt_rsp_word.read() + r_xram_rsp_to_tgt_rsp_length.read() - 1; + bool is_last_word = (r_tgt_rsp_cpt.read() == last_word_idx); + bool is_ll = ((r_xram_rsp_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL); + bool is_error = r_xram_rsp_to_tgt_rsp_rerror.read(); + + p_vci_tgt.rspval = true; + + if (is_ll and not r_tgt_rsp_key_sent.read()) { + // LL response first flit + p_vci_tgt.rdata = r_xram_rsp_to_tgt_rsp_ll_key.read(); + } + else { + // LL response second flit or READ response + p_vci_tgt.rdata = r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read(); + } + + p_vci_tgt.rsrcid = r_xram_rsp_to_tgt_rsp_srcid.read(); + p_vci_tgt.rtrdid = r_xram_rsp_to_tgt_rsp_trdid.read(); + p_vci_tgt.rpktid = r_xram_rsp_to_tgt_rsp_pktid.read(); + p_vci_tgt.rerror = is_error; + p_vci_tgt.reop = (((is_last_word or is_error) and not is_ll) or + (r_tgt_rsp_key_sent.read() and is_ll)); + break; + } + + case TGT_RSP_MULTI_ACK: + p_vci_tgt.rspval = true; + p_vci_tgt.rdata = 0; // Can be a CAS or SC rsp + p_vci_tgt.rsrcid = r_multi_ack_to_tgt_rsp_srcid.read(); + p_vci_tgt.rtrdid = r_multi_ack_to_tgt_rsp_trdid.read(); + p_vci_tgt.rpktid = r_multi_ack_to_tgt_rsp_pktid.read(); + p_vci_tgt.rerror = 0; + p_vci_tgt.reop = true; + break; + } // end switch r_tgt_rsp_fsm + + //////////////////////////////////////////////////////////////////// + // p_irq port + // + // WRITE MISS response error signaling + //////////////////////////////////////////////////////////////////// + + p_irq = + r_xram_rsp_rerror_irq.read() && + r_xram_rsp_rerror_irq_enable.read(); + + //////////////////////////////////////////////////////////////////// + // p_dspin_m2p port (CC_SEND FSM) + //////////////////////////////////////////////////////////////////// + + p_dspin_m2p.write = false; + p_dspin_m2p.eop = false; + p_dspin_m2p.data = 0; + + switch(r_cc_send_fsm.read()) + { + /////////////////////////// + case CC_SEND_CONFIG_IDLE: + case CC_SEND_XRAM_RSP_IDLE: + case CC_SEND_WRITE_IDLE: + case CC_SEND_CAS_IDLE: + { + break; + } + //////////////////////////////// + case CC_SEND_CONFIG_INVAL_HEADER: + { + uint8_t multi_inval_type; + if (m_config_to_cc_send_inst_fifo.read()) + { + multi_inval_type = DspinDhccpParam::TYPE_MULTI_INVAL_INST; + } + else + { + multi_inval_type = DspinDhccpParam::TYPE_MULTI_INVAL_DATA; + } + + uint64_t flit = 0; + uint64_t dest = m_config_to_cc_send_srcid_fifo.read() << + (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); + + DspinDhccpParam::dspin_set( flit, + dest, + DspinDhccpParam::MULTI_INVAL_DEST); + + DspinDhccpParam::dspin_set( flit, + r_config_to_cc_send_trdid.read(), + DspinDhccpParam::MULTI_INVAL_UPDT_INDEX); + + DspinDhccpParam::dspin_set( flit, + multi_inval_type, + DspinDhccpParam::M2P_TYPE); + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; + break; + } + //////////////////////////////// + case CC_SEND_CONFIG_INVAL_NLINE: + { + uint64_t flit = 0; + DspinDhccpParam::dspin_set( flit, + r_config_to_cc_send_nline.read(), + DspinDhccpParam::MULTI_INVAL_NLINE); + p_dspin_m2p.eop = true; + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; + break; + } + /////////////////////////////////// + case CC_SEND_XRAM_RSP_INVAL_HEADER: + { + if (not m_xram_rsp_to_cc_send_inst_fifo.rok()) break; + + uint8_t multi_inval_type; + if (m_xram_rsp_to_cc_send_inst_fifo.read()) + { + multi_inval_type = DspinDhccpParam::TYPE_MULTI_INVAL_INST; + } + else + { + multi_inval_type = DspinDhccpParam::TYPE_MULTI_INVAL_DATA; + } + + uint64_t flit = 0; + uint64_t dest = m_xram_rsp_to_cc_send_srcid_fifo.read() << + (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); + + DspinDhccpParam::dspin_set( flit, + dest, + DspinDhccpParam::MULTI_INVAL_DEST); + + DspinDhccpParam::dspin_set( flit, + r_xram_rsp_to_cc_send_trdid.read(), + DspinDhccpParam::MULTI_INVAL_UPDT_INDEX); + + DspinDhccpParam::dspin_set( flit, + multi_inval_type, + DspinDhccpParam::M2P_TYPE); + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; + break; + } + + ////////////////////////////////// + case CC_SEND_XRAM_RSP_INVAL_NLINE: + { + uint64_t flit = 0; + + DspinDhccpParam::dspin_set( flit, + r_xram_rsp_to_cc_send_nline.read(), + DspinDhccpParam::MULTI_INVAL_NLINE); + p_dspin_m2p.eop = true; + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; + break; + } + + ///////////////////////////////////// + case CC_SEND_CONFIG_BRDCAST_HEADER: + case CC_SEND_XRAM_RSP_BRDCAST_HEADER: + case CC_SEND_WRITE_BRDCAST_HEADER: + case CC_SEND_CAS_BRDCAST_HEADER: + { + uint64_t flit = 0; + + DspinDhccpParam::dspin_set( flit, + m_broadcast_boundaries, + DspinDhccpParam::BROADCAST_BOX); + + DspinDhccpParam::dspin_set( flit, + 1ULL, + DspinDhccpParam::M2P_BC); + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; + break; + } + //////////////////////////////////// + case CC_SEND_XRAM_RSP_BRDCAST_NLINE: + { + uint64_t flit = 0; + DspinDhccpParam::dspin_set( flit, + r_xram_rsp_to_cc_send_nline.read(), + DspinDhccpParam::BROADCAST_NLINE); + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; + break; + } + ////////////////////////////////// + case CC_SEND_CONFIG_BRDCAST_NLINE: + { + uint64_t flit = 0; + DspinDhccpParam::dspin_set( flit, + r_config_to_cc_send_nline.read(), + DspinDhccpParam::BROADCAST_NLINE); + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; + break; + } + ///////////////////////////////// + case CC_SEND_WRITE_BRDCAST_NLINE: + { + uint64_t flit = 0; + DspinDhccpParam::dspin_set( flit, + r_write_to_cc_send_nline.read(), + DspinDhccpParam::BROADCAST_NLINE); + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; + break; + } + /////////////////////////////// + case CC_SEND_CAS_BRDCAST_NLINE: + { + uint64_t flit = 0; + DspinDhccpParam::dspin_set( flit, + r_cas_to_cc_send_nline.read(), + DspinDhccpParam::BROADCAST_NLINE); + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; + break; + } + /////////////////////////////// + case CC_SEND_WRITE_UPDT_HEADER: + { + if (not m_write_to_cc_send_inst_fifo.rok()) break; + + uint8_t multi_updt_type; + if (m_write_to_cc_send_inst_fifo.read()) + { + multi_updt_type = DspinDhccpParam::TYPE_MULTI_UPDT_INST; + } + else + { + multi_updt_type = DspinDhccpParam::TYPE_MULTI_UPDT_DATA; + } + + uint64_t flit = 0; + uint64_t dest = + m_write_to_cc_send_srcid_fifo.read() << + (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); + + DspinDhccpParam::dspin_set( + flit, + dest, + DspinDhccpParam::MULTI_UPDT_DEST); + + DspinDhccpParam::dspin_set( + flit, + r_write_to_cc_send_trdid.read(), + DspinDhccpParam::MULTI_UPDT_UPDT_INDEX); + + DspinDhccpParam::dspin_set( + flit, + multi_updt_type, + DspinDhccpParam::M2P_TYPE); + + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; + + break; + } + ////////////////////////////// + case CC_SEND_WRITE_UPDT_NLINE: + { + uint64_t flit = 0; + + DspinDhccpParam::dspin_set( + flit, + r_write_to_cc_send_index.read(), + DspinDhccpParam::MULTI_UPDT_WORD_INDEX); + + DspinDhccpParam::dspin_set( + flit, + r_write_to_cc_send_nline.read(), + DspinDhccpParam::MULTI_UPDT_NLINE); + + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; + + break; + } + ///////////////////////////// + case CC_SEND_WRITE_UPDT_DATA: + { + + uint8_t multi_updt_cpt = + r_cc_send_cpt.read() + r_write_to_cc_send_index.read(); + + uint8_t multi_updt_be = r_write_to_cc_send_be[multi_updt_cpt].read(); + uint32_t multi_updt_data = r_write_to_cc_send_data[multi_updt_cpt].read(); + + uint64_t flit = 0; + + DspinDhccpParam::dspin_set( + flit, + multi_updt_be, + DspinDhccpParam::MULTI_UPDT_BE); + + DspinDhccpParam::dspin_set( + flit, + multi_updt_data, + DspinDhccpParam::MULTI_UPDT_DATA); + + p_dspin_m2p.write = true; + p_dspin_m2p.eop = (r_cc_send_cpt.read() == r_write_to_cc_send_count.read()); + p_dspin_m2p.data = flit; + + break; + } + //////////////////////////// + case CC_SEND_CAS_UPDT_HEADER: + { + if (not m_cas_to_cc_send_inst_fifo.rok()) break; + + uint8_t multi_updt_type; + if (m_cas_to_cc_send_inst_fifo.read()) + { + multi_updt_type = DspinDhccpParam::TYPE_MULTI_UPDT_INST; + } + else + { + multi_updt_type = DspinDhccpParam::TYPE_MULTI_UPDT_DATA; + } + + uint64_t flit = 0; + uint64_t dest = + m_cas_to_cc_send_srcid_fifo.read() << + (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); + + DspinDhccpParam::dspin_set( + flit, + dest, + DspinDhccpParam::MULTI_UPDT_DEST); + + DspinDhccpParam::dspin_set( + flit, + r_cas_to_cc_send_trdid.read(), + DspinDhccpParam::MULTI_UPDT_UPDT_INDEX); + + DspinDhccpParam::dspin_set( + flit, + multi_updt_type, + DspinDhccpParam::M2P_TYPE); + + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; + + break; + } + //////////////////////////// + case CC_SEND_CAS_UPDT_NLINE: + { + uint64_t flit = 0; + + DspinDhccpParam::dspin_set( + flit, + r_cas_to_cc_send_index.read(), + DspinDhccpParam::MULTI_UPDT_WORD_INDEX); + + DspinDhccpParam::dspin_set( + flit, + r_cas_to_cc_send_nline.read(), + DspinDhccpParam::MULTI_UPDT_NLINE); + + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; + + break; + } + /////////////////////////// + case CC_SEND_CAS_UPDT_DATA: + { + uint64_t flit = 0; + + DspinDhccpParam::dspin_set( + flit, + 0xF, + DspinDhccpParam::MULTI_UPDT_BE); + + DspinDhccpParam::dspin_set( + flit, + r_cas_to_cc_send_wdata.read(), + DspinDhccpParam::MULTI_UPDT_DATA); + + p_dspin_m2p.write = true; + p_dspin_m2p.eop = not r_cas_to_cc_send_is_long.read(); + p_dspin_m2p.data = flit; + + break; + } + //////////////////////////////// + case CC_SEND_CAS_UPDT_DATA_HIGH: + { + uint64_t flit = 0; + + DspinDhccpParam::dspin_set( + flit, + 0xF, + DspinDhccpParam::MULTI_UPDT_BE); + + DspinDhccpParam::dspin_set( + flit, + r_cas_to_cc_send_wdata_high.read(), + DspinDhccpParam::MULTI_UPDT_DATA); + + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; + + break; + } + } + + //////////////////////////////////////////////////////////////////// + // p_dspin_clack port (CLEANUP FSM) + //////////////////////////////////////////////////////////////////// + + if (r_cleanup_fsm.read() == CLEANUP_SEND_CLACK) + { + uint8_t cleanup_ack_type; + if (r_cleanup_inst.read()) + { + cleanup_ack_type = DspinDhccpParam::TYPE_CLACK_INST; + } + else + { + cleanup_ack_type = DspinDhccpParam::TYPE_CLACK_DATA; + } + + uint64_t flit = 0; + uint64_t dest = r_cleanup_srcid.read() << + (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); + + DspinDhccpParam::dspin_set( + flit, + dest, + DspinDhccpParam::CLACK_DEST); + + DspinDhccpParam::dspin_set( + flit, + r_cleanup_nline.read(), + DspinDhccpParam::CLACK_SET); + + DspinDhccpParam::dspin_set( + flit, + r_cleanup_way_index.read(), + DspinDhccpParam::CLACK_WAY); + + DspinDhccpParam::dspin_set( + flit, + cleanup_ack_type, + DspinDhccpParam::CLACK_TYPE); + + p_dspin_clack.eop = true; + p_dspin_clack.write = true; + p_dspin_clack.data = flit; + } + else + { + p_dspin_clack.write = false; + p_dspin_clack.eop = false; + p_dspin_clack.data = 0; + } + + /////////////////////////////////////////////////////////////////// + // p_dspin_p2m port (CC_RECEIVE FSM) + /////////////////////////////////////////////////////////////////// + // + switch(r_cc_receive_fsm.read()) + { + case CC_RECEIVE_IDLE: + { + p_dspin_p2m.read = false; + break; + } + case CC_RECEIVE_CLEANUP: + case CC_RECEIVE_CLEANUP_EOP: + { + p_dspin_p2m.read = m_cc_receive_to_cleanup_fifo.wok(); + break; + } + case CC_RECEIVE_MULTI_ACK: + { + p_dspin_p2m.read = m_cc_receive_to_multi_ack_fifo.wok(); + break; + } + } + // end switch r_cc_send_fsm + } // end genMoore() + +} +} // end name space + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 Index: /branches/fault_tolerance/modules/vci_mem_cache/include/soclib/mem_cache.h =================================================================== --- /branches/fault_tolerance/modules/vci_mem_cache/include/soclib/mem_cache.h (revision 724) +++ /branches/fault_tolerance/modules/vci_mem_cache/include/soclib/mem_cache.h (revision 724) @@ -0,0 +1,200 @@ +/* + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, Asim + * alain greiner + * + * Maintainers: alain + */ +#ifndef MEM_CACHE_REGS_H +#define MEM_CACHE_REGS_H + +enum SoclibMemCacheFunc +{ + MEMC_CONFIG = 0, + MEMC_INSTRM = 1, + MEMC_RERROR = 2, + + MEMC_FUNC_SPAN = 0x200 +}; + +enum SoclibMemCacheConfigRegs +{ + MEMC_LOCK, + MEMC_ADDR_LO, + MEMC_ADDR_HI, + MEMC_BUF_LENGTH, + MEMC_CMD_TYPE +}; + +enum SoclibMemCacheConfigCmd +{ + MEMC_CMD_NOP, + MEMC_CMD_INVAL, + MEMC_CMD_SYNC +}; + +/////////////////////////////////////////////////////////// +// Decoding CONFIG interface commands // +// // +// VCI ADDRESS // +// ================================================ // +// GLOBAL | LOCAL | ... | FUNC_IDX | REGS_IDX | 00 // +// IDX | IDX | | (3 bits) | (7 bits) | // +// ================================================ // +// // +// For instrumentation: FUNC_IDX = 0b001 // +// // +// REGS_IDX // +// ============================================ // +// Z | Y | X | W // +// (1 bit) | (2 bits) | (3 bits) | (1 bit) // +// ============================================ // +// // +// For configuration: FUNC_IDX = 0b000 // +// // +// REGS_IDX // +// ============================================ // +// RESERVED | X | // +// (4 bits) | (3 bits) | // +// ============================================ // +// // +// X : REGISTER INDEX // +// // +// For WRITE MISS error signaling: FUNC = 0x010 // +// // +// REGS_IDX // +// ============================================ // +// RESERVED | X | // +// (4 bits) | (3 bits) | // +// ============================================ // +// // +// X : REGISTER INDEX // +// // +/////////////////////////////////////////////////////////// + +enum SoclibMemCacheInstrRegs { + /////////////////////////////////////////////////////// + // DIRECT instrumentation registers // + /////////////////////////////////////////////////////// + + // LOCAL + + MEMC_LOCAL_READ_LO = 0x00, + MEMC_LOCAL_READ_HI = 0x01, + MEMC_LOCAL_WRITE_LO = 0x02, + MEMC_LOCAL_WRITE_HI = 0x03, + MEMC_LOCAL_LL_LO = 0x04, + MEMC_LOCAL_LL_HI = 0x05, + MEMC_LOCAL_SC_LO = 0x06, + MEMC_LOCAL_SC_HI = 0x07, + MEMC_LOCAL_CAS_LO = 0x08, + MEMC_LOCAL_CAS_HI = 0x09, + + // REMOTE + + MEMC_REMOTE_READ_LO = 0x10, + MEMC_REMOTE_READ_HI = 0x11, + MEMC_REMOTE_WRITE_LO = 0x12, + MEMC_REMOTE_WRITE_HI = 0x13, + MEMC_REMOTE_LL_LO = 0x14, + MEMC_REMOTE_LL_HI = 0x15, + MEMC_REMOTE_SC_LO = 0x16, + MEMC_REMOTE_SC_HI = 0x17, + MEMC_REMOTE_CAS_LO = 0x18, + MEMC_REMOTE_CAS_HI = 0x19, + + // COST + + MEMC_COST_READ_LO = 0x20, + MEMC_COST_READ_HI = 0x21, + MEMC_COST_WRITE_LO = 0x22, + MEMC_COST_WRITE_HI = 0x23, + MEMC_COST_LL_LO = 0x24, + MEMC_COST_LL_HI = 0x25, + MEMC_COST_SC_LO = 0x26, + MEMC_COST_SC_HI = 0x27, + MEMC_COST_CAS_LO = 0x28, + MEMC_COST_CAS_HI = 0x29, + + /////////////////////////////////////////////////////// + // COHERENCE instrumentation registers // + /////////////////////////////////////////////////////// + + // LOCAL + + MEMC_LOCAL_MUPDATE_LO = 0x40, + MEMC_LOCAL_MUPDATE_HI = 0x41, + MEMC_LOCAL_MINVAL_LO = 0x42, + MEMC_LOCAL_MINVAL_HI = 0x43, + MEMC_LOCAL_CLEANUP_LO = 0x44, + MEMC_LOCAL_CLEANUP_HI = 0x45, + + // REMOTE + + MEMC_REMOTE_MUPDATE_LO = 0x50, + MEMC_REMOTE_MUPDATE_HI = 0x51, + MEMC_REMOTE_MINVAL_LO = 0x52, + MEMC_REMOTE_MINVAL_HI = 0x53, + MEMC_REMOTE_CLEANUP_LO = 0x54, + MEMC_REMOTE_CLEANUP_HI = 0x55, + + // COST + + MEMC_COST_MUPDATE_LO = 0x60, + MEMC_COST_MUPDATE_HI = 0x61, + MEMC_COST_MINVAL_LO = 0x62, + MEMC_COST_MINVAL_HI = 0x63, + MEMC_COST_CLEANUP_LO = 0x64, + MEMC_COST_CLEANUP_HI = 0x65, + + // TOTAL + + MEMC_TOTAL_MUPDATE_LO = 0x68, + MEMC_TOTAL_MUPDATE_HI = 0x69, + MEMC_TOTAL_MINVAL_LO = 0x6A, + MEMC_TOTAL_MINVAL_HI = 0x6B, + MEMC_TOTAL_BINVAL_LO = 0x6C, + MEMC_TOTAL_BINVAL_HI = 0x6D, +}; + +enum SoclibMemCacheRerrorRegs +{ + MEMC_RERROR_ADDR_LO = 0, + MEMC_RERROR_ADDR_HI, + MEMC_RERROR_SRCID, + MEMC_RERROR_IRQ_RESET, + MEMC_RERROR_IRQ_ENABLE +}; + +#define MEMC_REG(func,idx) ((func<<7)|idx) + +#endif /* MEM_CACHE_REGS_H */ + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: /branches/fault_tolerance/modules/vci_spi/caba/metadata/vci_spi.sd =================================================================== --- /branches/fault_tolerance/modules/vci_spi/caba/metadata/vci_spi.sd (revision 724) +++ /branches/fault_tolerance/modules/vci_spi/caba/metadata/vci_spi.sd (revision 724) @@ -0,0 +1,53 @@ + +# -*- python -*- + +Module('caba:vci_spi', + classname = 'soclib::caba::VciSpi', + + tmpl_parameters = [ + parameter.Module('vci_param', default = 'caba:vci_param'), + ], + + header_files = [ + '../source/include/vci_spi.h', + ], + + interface_files = [ + '../../include/soclib/vcispi.h', + ], + + implementation_files = [ + '../source/src/vci_spi.cpp', + ], + + ports = [ + Port('caba:vci_target', 'p_vci_target'), + Port('caba:vci_initiator', 'p_vci_initiator'), + Port('caba:bit_out', 'p_irq'), + Port('caba:bit_out', 'p_spi_clk'), + Port('caba:bit_out', 'p_spi_ss'), + Port('caba:bit_out', 'p_spi_mosi'), + Port('caba:bit_in', 'p_spi_miso'), + Port('caba:bit_in', 'p_resetn', auto = 'resetn'), + Port('caba:clock_in', 'p_clk', auto = 'clock'), + ], + + uses = [ + Uses('caba:base_module'), + Uses('common:mapping_table'), + Uses('caba:generic_fifo'), + ], + + instance_parameters = [ + parameter.Module('mt', typename = 'common:mapping_table', auto = 'env:mapping_table'), + parameter.IntTab('srcid'), + parameter.IntTab('tgtid'), + parameter.Int('burst_size'), + ], + + extensions = [ + 'dsx:addressable=tgtid', + 'dsx:max_segments=1', + 'dsx:get_ident=tgtid:p_vci_target:mt,srcid:p_vci_initiator:mt', + ], +) Index: /branches/fault_tolerance/modules/vci_spi/caba/source/include/vci_spi.h =================================================================== --- /branches/fault_tolerance/modules/vci_spi/caba/source/include/vci_spi.h (revision 724) +++ /branches/fault_tolerance/modules/vci_spi/caba/source/include/vci_spi.h (revision 724) @@ -0,0 +1,222 @@ + +/* -*- c++ -*- + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * manuel.bouyer@lip6.fr october 2013 + * + * Maintainers: bouyer + */ + +////////////////////////////////////////////////////////////////////////////////////// +// This component is a SPI controller with a VCI interface +// It supports only 32 or 64 bits VCI DATA width, but all addressable registers +// contain 32 bits words. It supports VCI addresss lartger than 32 bits. +// +// This component can perform data transfers between one single file belonging +// to the host system and a buffer in the memory of the virtual prototype. +// The file name is an argument of the constructor. +// This component has a DMA capability, and is both a target and an initiator. +// The burst size (bytes) must be power of 2. +// The burst size is typically a cache line. +// The memory buffer must be aligned to a a burst boundary. +// Both read and write transfers are supported. An IRQ is optionally +// asserted when the transfer is completed. +// + +#ifndef SOCLIB_VCI_SPI_H +#define SOCLIB_VCI_SPI_H + +#include +#include +#include +#include "caba_base_module.h" +#include "mapping_table.h" +#include "vci_initiator.h" +#include "vci_target.h" +#include "generic_fifo.h" + +namespace soclib { +namespace caba { + +using namespace sc_core; + +template +class VciSpi + : public caba::BaseModule +{ +private: + + // Registers + sc_signal r_target_fsm; // target fsm state register + sc_signal r_initiator_fsm; // initiator fsm state register + sc_signal r_spi_fsm; // spi engine state + sc_signal r_txrx[2]; // data in/out + sc_signal r_divider; // SPI clk divider + sc_signal r_ss; // SPI slave select + sc_signal r_ctrl_cpol; // clock polarity + sc_signal r_ctrl_cpha; // clock phase + sc_signal r_ctrl_ie; // interrupt enable + sc_signal r_ctrl_char_len; // number of bits in xfer + sc_signal r_buf_address; // memory buffer address + sc_signal r_dma_count; // DMA burst count + sc_signal r_read; // DMA read/write + + sc_signal r_burst_word; // DMA burst word count + sc_signal r_dma_error; // DMA error + + sc_signal r_spi_bsy; // SPI shifter busy + sc_signal r_spi_bit_count; + sc_signal r_spi_word_count; + sc_signal r_spi_clk_counter; + sc_signal r_spi_clk; + sc_signal r_spi_clk_previous; + sc_signal r_spi_clk_ignore; + sc_signal r_spi_out; + sc_signal r_spi_done; + sc_signal r_irq; + + GenericFifo r_dma_fifo_read; // buffer data from SPI to network + GenericFifo r_dma_fifo_write;// buffer data from network to SPI + + sc_signal r_srcid; // save srcid + sc_signal r_trdid; // save trdid + sc_signal r_pktid; // save pktid + + sc_signal r_rdata; // save reply + + // structural parameters + std::list m_seglist; + uint32_t m_srcid; // initiator index + const uint32_t m_burst_size; // number of words in a burst + const uint32_t m_words_per_burst; // number of words in a burst + const uint32_t m_byte2burst_shift; // log2(burst_size) + + // methods + void transition(); + void genMoore(); + + // Master FSM states + enum { + M_IDLE = 0, + M_READ_WAIT = 1, + M_READ_CMD = 2, + M_READ_RSP = 3, + M_INTR = 4, + M_WRITE_WAIT = 5, + M_WRITE_CMD = 6, + M_WRITE_RSP = 7, + M_WRITE_END = 8 + }; + + // Target FSM states + enum { + T_IDLE = 0, + T_RSP_READ = 1, + T_RSP_WRITE = 2, + T_ERROR_READ = 3, + T_ERROR_WRITE = 4 + }; + + // SPI FSM states + enum { + S_IDLE = 0, + S_DMA_RECEIVE = 1, + S_DMA_SEND_START = 2, + S_DMA_SEND = 3, + S_DMA_SEND_END = 4, + S_XMIT = 5, + }; + + // Error codes values + enum { + VCI_READ_OK = 0, + VCI_READ_ERROR = 1, + VCI_WRITE_OK = 2, + VCI_WRITE_ERROR = 3, + }; + + /* transaction type, pktid field */ + enum transaction_type_e + { + // b3 unused + // b2 READ / NOT READ + // Si READ + // b1 DATA / INS + // b0 UNC / MISS + // Si NOT READ + // b1 accÚs table llsc type SW / other + // b2 WRITE/CAS/LL/SC + TYPE_READ_DATA_UNC = 0x0, + TYPE_READ_DATA_MISS = 0x1, + TYPE_READ_INS_UNC = 0x2, + TYPE_READ_INS_MISS = 0x3, + TYPE_WRITE = 0x4, + TYPE_CAS = 0x5, + TYPE_LL = 0x6, + TYPE_SC = 0x7 + }; + +protected: + + SC_HAS_PROCESS(VciSpi); + +public: + + // ports + sc_in p_clk; + sc_in p_resetn; + sc_out p_irq; + soclib::caba::VciInitiator p_vci_initiator; + soclib::caba::VciTarget p_vci_target; + sc_out p_spi_ss; + sc_out p_spi_clk; + sc_out p_spi_mosi; + sc_in p_spi_miso; + + void print_trace(); + + // Constructor + VciSpi( + sc_module_name name, + const soclib::common::MappingTable &mt, + const soclib::common::IntTab &srcid, + const soclib::common::IntTab &tgtid, + const uint32_t burst_size = 64); + + ~VciSpi(); + +}; + +}} + +#endif /* SOCLIB_VCI_SPI_H */ + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: /branches/fault_tolerance/modules/vci_spi/caba/source/src/vci_spi.cpp =================================================================== --- /branches/fault_tolerance/modules/vci_spi/caba/source/src/vci_spi.cpp (revision 724) +++ /branches/fault_tolerance/modules/vci_spi/caba/source/src/vci_spi.cpp (revision 724) @@ -0,0 +1,799 @@ +/* -*- c++ -*- + * + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * manuel.bouyer@lip6.fr october 2013 + * + * Maintainers: bouyer + */ + +#include +#include +#include +#include +#include "vci_spi.h" +#include "vcispi.h" + +namespace soclib { namespace caba { + +#define tmpl(t) template t VciSpi + +using namespace soclib::caba; +using namespace soclib::common; + +//////////////////////// +tmpl(void)::transition() +{ + + bool s_dma_bsy = (r_initiator_fsm != M_IDLE); + if(p_resetn.read() == false) + { + r_initiator_fsm = M_IDLE; + r_target_fsm = T_IDLE; + r_spi_fsm = S_IDLE; + r_ss = 0; + r_divider = 0xffff; + r_ctrl_char_len = 0; + r_ctrl_ie = false; + r_ctrl_cpol = false; + r_ctrl_cpha = false; + r_spi_bsy = false; + r_dma_count = 0; + r_dma_error = false; + r_spi_clk_counter = 0xffff; + r_spi_clk = 0; + r_spi_done = false; + + r_irq = false; + r_read = false; + + r_dma_fifo_read.init(); + r_dma_fifo_write.init(); + + return; + } + + ////////////////////////////////////////////////////////////////////////////// + // The Target FSM controls the following registers: + // r_target_fsm, r_irq_enable, r_nblocks, r_buf adress, r_lba, r_go, r_read + ////////////////////////////////////////////////////////////////////////////// + + if (r_spi_done) + r_spi_bsy = false; + + switch(r_target_fsm) { + //////////// + case T_IDLE: + { + if ( p_vci_target.cmdval.read() ) + { + r_srcid = p_vci_target.srcid.read(); + r_trdid = p_vci_target.trdid.read(); + r_pktid = p_vci_target.pktid.read(); + uint32_t wdata = p_vci_target.wdata.read(); + sc_dt::sc_uint address = p_vci_target.address.read(); + + bool found = false; + std::list::iterator seg; + for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) + { + if ( seg->contains(address) ) found = true; + } + + + if (not found) { + if (p_vci_target.cmd.read() == vci_param::CMD_WRITE) + r_target_fsm = T_ERROR_WRITE; + else + r_target_fsm = T_ERROR_READ; + } else if (p_vci_target.cmd.read() != vci_param::CMD_READ && + p_vci_target.cmd.read() != vci_param::CMD_WRITE) { + r_target_fsm = T_ERROR_READ; + } else { + bool write = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) & !r_spi_bsy &!s_dma_bsy; + uint32_t cell = (uint32_t)((address & 0x3F)>>2); + switch(cell) { + case SPI_DATA_TXRX0: + r_rdata = r_txrx[0] & (uint64_t)0x00000000ffffffffULL; + if (write) { + r_txrx[0] = + (r_txrx[0] & (uint64_t)0xffffffff00000000ULL) | + ((uint64_t)wdata); + } + r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; + break; + case SPI_DATA_TXRX1: + r_rdata = r_txrx[0] >> 32; + if (write) { + r_txrx[0] = + (r_txrx[0] & (uint64_t)0x00000000ffffffffULL) | + ((uint64_t)wdata << 32); + } + r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; + break; + case SPI_DATA_TXRX2: + r_rdata = r_txrx[1] & (uint64_t)0x00000000ffffffffULL; + if (write) { + r_txrx[1] = + (r_txrx[1] & (uint64_t)0xffffffff00000000ULL) | + ((uint64_t)wdata); + } + r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; + break; + case SPI_DATA_TXRX3: + r_rdata = r_txrx[1] >> 32; + if (write) { + r_txrx[1] = + (r_txrx[1] & (uint64_t)0x00000000ffffffffULL) | + ((uint64_t)wdata << 32); + } + r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; + break; + case SPI_CTRL: + { + uint32_t data = 0; + if (r_ctrl_cpol.read()) + data |= SPI_CTRL_CPOL; + if (r_ctrl_cpha.read()) + data |= SPI_CTRL_CPHA; + if (r_ctrl_ie.read()) + data |= SPI_CTRL_IE_EN; + if (r_spi_bsy.read()) + data |= SPI_CTRL_GO_BSY; + if (s_dma_bsy) + data |= SPI_CTRL_DMA_BSY; + if (r_dma_error) + data |= SPI_CTRL_DMA_ERR; + data |= (uint32_t)r_ctrl_char_len.read(); + r_rdata = data; + if (write) { + r_ctrl_cpol = ((wdata & SPI_CTRL_CPOL) != 0); + r_ctrl_cpha = ((wdata & SPI_CTRL_CPHA) != 0); + r_ctrl_ie = ((wdata & SPI_CTRL_IE_EN) != 0); + if (wdata & SPI_CTRL_GO_BSY) + r_spi_bsy = true; + r_ctrl_char_len = (wdata & SPI_CTRL_CHAR_LEN_MASK); +#ifdef SOCLIB_MODULE_DEBUG + if ((wdata & SPI_CTRL_GO_BSY) != 0) { + std::cout << name() << " start xfer " << std::dec << (int)r_ctrl_char_len.read() << " data " << std::hex << r_txrx[1] << " " << r_txrx[0] << std::endl; + } +#endif + } else { + r_irq = false; + } + r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; + break; + } + case SPI_DIVIDER: + r_rdata = r_divider.read(); + if (write) { +#ifdef SOCLIB_MODULE_DEBUG + std::cout << name() << " divider set to " << std::dec << wdata << std::endl; +#endif + r_divider = wdata; + } + r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; + break; + case SPI_SS: + r_rdata = r_ss.read(); + if (write) { + r_ss = wdata; + } + r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; + break; + case SPI_DMA_BASE: + r_rdata = r_buf_address.read(); + if (write) { + r_buf_address = (r_buf_address & (uint64_t)0xffffffff00000000) | wdata; + } + r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; + break; + case SPI_DMA_BASEH: + r_rdata = r_buf_address >> 32; + if (write) { + r_buf_address = (r_buf_address & (uint64_t)0x00000000ffffffff) | ((uint64_t)wdata << 32); + } + r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; + break; + case SPI_DMA_COUNT: + r_rdata = (r_dma_count.read() << m_byte2burst_shift) | + r_read; + if (write) { + r_read = (wdata & 0x1); + r_dma_count = wdata >> m_byte2burst_shift; + r_ctrl_char_len = vci_param::B * 8; + } + r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_RSP_WRITE : T_RSP_READ; + break; + default: + r_target_fsm = (p_vci_target.cmd.read() == vci_param::CMD_WRITE) ? T_ERROR_WRITE : T_ERROR_READ; + break; + } + } + } + break; + } + //////////////////// + case T_RSP_READ: + case T_RSP_WRITE: + case T_ERROR_READ: + case T_ERROR_WRITE: + if (p_vci_target.rspack.read() ) { + r_target_fsm = T_IDLE; + } + break; + } // end switch target fsm + + + + + ////////////////////////////////////////////////////////////////////////////// + // the SPI FSM controls SPI signals + ////////////////////////////////////////////////////////////////////////////// + if (r_spi_bsy == false) + r_spi_done = false; + switch (r_spi_fsm) { + case S_IDLE: + r_spi_clk_counter = r_divider.read(); + r_spi_clk = 0; + r_spi_clk_previous = r_ctrl_cpha; + r_spi_clk_ignore = r_ctrl_cpha; + r_spi_bit_count = r_ctrl_char_len; + if (r_dma_count != 0) { + if (r_read.read()) + r_spi_fsm = S_DMA_SEND_START; + else + r_spi_fsm = S_DMA_RECEIVE; + } else if (r_spi_bsy.read() && !r_spi_done.read()) { + r_spi_fsm = S_XMIT; + r_spi_out = (r_txrx[(r_ctrl_char_len -1)/ 64] >> ((r_ctrl_char_len - 1) % 64)) & (uint64_t)0x0000000000000001ULL; + } + break; + case S_DMA_RECEIVE: + { + r_spi_clk_counter = r_divider.read(); + r_spi_clk = 0; + r_spi_clk_previous = r_ctrl_cpha; + r_spi_clk_ignore = r_ctrl_cpha; + r_spi_bit_count = r_ctrl_char_len; + if (r_initiator_fsm != M_WRITE_RSP || !p_vci_initiator.rspval.read()) { + if (r_dma_fifo_write.rok()) { + typename vci_param::data_t v = r_dma_fifo_write.read(); + r_dma_fifo_write.simple_get(); + r_txrx[0] = v; + r_spi_out = (v >> ((vci_param::B * 8) - 1)) & 0x1; + r_spi_fsm = S_XMIT; + } else if (r_initiator_fsm == M_WRITE_END) { + r_spi_fsm = S_IDLE; + } + } + break; + } + case S_DMA_SEND_START: + r_spi_word_count = (r_dma_count << (m_byte2burst_shift - 2)) - 1; + r_spi_out = 1; + r_txrx[0] = 0xffffffff; + r_spi_fsm = S_XMIT; + break; + case S_DMA_SEND: + r_spi_out = 1; + r_spi_clk_counter = r_divider.read(); + r_spi_clk = 0; + r_spi_clk_previous = r_ctrl_cpha; + r_spi_clk_ignore = r_ctrl_cpha; + r_spi_bit_count = r_ctrl_char_len; + if (r_initiator_fsm != M_READ_CMD) { + if (r_dma_fifo_read.wok()) { + r_dma_fifo_read.simple_put( + (typename vci_param::data_t)r_txrx[0]); + r_spi_word_count = r_spi_word_count - 1; + r_txrx[0] = 0xffffffff; + if ( r_spi_word_count == 0 ) { + r_spi_fsm = S_DMA_SEND_END; + } else { + r_spi_fsm = S_XMIT; + } + } + } + break; + case S_DMA_SEND_END: + if (r_initiator_fsm == M_IDLE) + r_spi_fsm = S_IDLE; + break; + case S_XMIT: + { + bool s_clk_sample; + // on clock transition, sample input line, and shift data + s_clk_sample = r_spi_clk ^ r_ctrl_cpha; + if (!r_spi_clk_ignore) { + if (r_spi_clk_previous == 0 && s_clk_sample == 1) { + // low to high transition: shift and sample + r_txrx[1] = (r_txrx[1] << 1) | (r_txrx[0] >> 63); + r_txrx[0] = (r_txrx[0] << 1) | p_spi_miso; + r_spi_bit_count = r_spi_bit_count - 1; + } else if (r_spi_clk_previous == 1 && s_clk_sample == 0) { + // high to low transition: change output, or stop + if (r_spi_bit_count == 0) { + if (r_initiator_fsm != M_IDLE) { + if (r_read) + r_spi_fsm = S_DMA_SEND; + else + r_spi_fsm = S_DMA_RECEIVE; + } else { + r_spi_fsm = S_IDLE; + r_irq = r_ctrl_ie; + r_spi_done = true; + } +#ifdef SOCLIB_MODULE_DEBUG0 + std::cout << name() << " end xfer " << std::dec << (int)r_ctrl_char_len.read() << " data " << std::hex << r_txrx[1] << " " << r_txrx[0] << std::endl; +#endif + } else { + r_spi_out = (r_txrx[(r_ctrl_char_len -1)/ 64] >> ((r_ctrl_char_len - 1) % 64)) & (uint64_t)0x0000000000000001ULL; + } + } + } + r_spi_clk_previous = s_clk_sample; + // generate the SPI clock + if (r_spi_clk_counter.read() == 0) { + r_spi_clk_counter = r_divider.read(); + r_spi_clk = !r_spi_clk.read(); + r_spi_clk_ignore = false; + } else { + r_spi_clk_counter = r_spi_clk_counter.read() - 1; + } + break; + } + } + ////////////////////////////////////////////////////////////////////////////// + // The initiator FSM executes a loop, transfering one burst per iteration. + // data comes from or goes to fifos, the other end of the fifos is + // feed by or eaten by the SPI fsm. + ////////////////////////////////////////////////////////////////////////////// + + switch( r_initiator_fsm.read() ) { + //////////// + case M_IDLE: // check buffer alignment to compute the number of bursts + { + if ( r_dma_count != 0 ) + { + // start transfer + if ( r_read.read() ) r_initiator_fsm = M_READ_WAIT; + else r_initiator_fsm = M_WRITE_WAIT; + } + break; + } + case M_READ_WAIT: // wait for the FIFO to be full + if (!r_dma_fifo_read.wok()) { + r_burst_word = m_words_per_burst - 1; + r_initiator_fsm = M_READ_CMD; + } + break; + //////////////// + case M_READ_CMD: // Send a multi-flits VCI WRITE command + { + if ( p_vci_initiator.cmdack.read() ) + { + if ( r_burst_word == 0 ) // last flit + { + r_initiator_fsm = M_READ_RSP; + } + else // not the last flit + { + r_burst_word = r_burst_word.read() - 1; + } + + r_dma_fifo_read.simple_get(); // consume one fifo word + // compute next word address + r_buf_address = r_buf_address.read() + vci_param::B; + } + break; + } + //////////////// + case M_READ_RSP: // Wait a single flit VCI WRITE response + { + if ( p_vci_initiator.rspval.read() ) + { + if ( (p_vci_initiator.rerror.read()&0x1) != 0 ) + { + r_burst_word = 0; + r_dma_count = 0; + r_dma_error = true; + r_initiator_fsm = M_INTR; +#ifdef SOCLIB_MODULE_DEBUG + std::cout << "vci_bd M_READ_ERROR" << std::endl; +#endif + } + else if ( r_spi_fsm == S_DMA_SEND_END ) // last burst + { + r_dma_count = 0; + r_initiator_fsm = M_INTR; + r_dma_error = false; +#ifdef SOCLIB_MODULE_DEBUG + std::cout << "vci_bd M_READ_SUCCESS" << std::endl; +#endif + } + else // keep on reading + { + r_dma_count = r_dma_count - 1; + r_initiator_fsm = M_READ_WAIT; + } + } + break; + } + /////////////////// + case M_INTR: + r_initiator_fsm = M_IDLE; + r_irq = true; + break; + /////////////////// + case M_WRITE_WAIT: // wait for the FIFO to be empty + if (!r_dma_fifo_write.rok()) { + r_burst_word = m_words_per_burst - 1; + r_dma_count = r_dma_count - 1; + r_initiator_fsm = M_WRITE_CMD; + } + break; + ///////////////// + case M_WRITE_CMD: // This is actually a single flit VCI READ command + { + if ( p_vci_initiator.cmdack.read() ) r_initiator_fsm = M_WRITE_RSP; + break; + } + ///////////////// + case M_WRITE_RSP: // This is actually a multi-words VCI READ response + { + if ( p_vci_initiator.rspval.read() ) + { + typename vci_param::data_t v = p_vci_initiator.rdata.read(); + typename vci_param::data_t f = 0; + // byte-swap + for (int i = 0; i < (vci_param::B * 8); i += 8) { + f |= ((v >> i) & 0xff) << ((vci_param::B * 8) - 8 - i); + } + r_dma_fifo_write.simple_put(f); + r_burst_word = r_burst_word.read() - 1; + if ( p_vci_initiator.reop.read() ) // last flit of the burst + { + r_buf_address = r_buf_address.read() + m_burst_size; + + if( (p_vci_initiator.rerror.read()&0x1) != 0 ) + { + r_dma_count = 0; + r_dma_error = 1; + r_initiator_fsm = M_WRITE_END; +#ifdef SOCLIB_MODULE_DEBUG + std::cout << "vci_bd M_WRITE_ERROR" << std::endl; +#endif + } + else if ( r_dma_count.read() == 0) // last burst + { + r_dma_error = 0; + r_initiator_fsm = M_WRITE_END; + } + else // not the last burst + { + r_initiator_fsm = M_WRITE_WAIT; + } + } + } + break; + } + ///////////////// + case M_WRITE_END: // wait for the write to be complete + { + if (r_spi_fsm == S_IDLE) { // write complete + r_initiator_fsm = M_INTR; + } + break; + } + } // end switch r_initiator_fsm +} // end transition + +////////////////////// +tmpl(void)::genMoore() +{ + // p_vci_target port + p_vci_target.rsrcid = (sc_dt::sc_uint)r_srcid.read(); + p_vci_target.rtrdid = (sc_dt::sc_uint)r_trdid.read(); + p_vci_target.rpktid = (sc_dt::sc_uint)r_pktid.read(); + p_vci_target.reop = true; + + switch(r_target_fsm) { + case T_IDLE: + p_vci_target.cmdack = true; + p_vci_target.rspval = false; + p_vci_target.rdata = 0; + break; + case T_RSP_READ: + p_vci_target.cmdack = false; + p_vci_target.rspval = true; + p_vci_target.rdata = r_rdata; + p_vci_target.rerror = VCI_READ_OK; + break; + case T_RSP_WRITE: + p_vci_target.cmdack = false; + p_vci_target.rspval = true; + p_vci_target.rdata = 0; + p_vci_target.rerror = VCI_WRITE_OK; + break; + case T_ERROR_READ: + p_vci_target.cmdack = false; + p_vci_target.rspval = true; + p_vci_target.rdata = 0; + p_vci_target.rerror = VCI_READ_ERROR; + break; + case T_ERROR_WRITE: + p_vci_target.cmdack = false; + p_vci_target.rspval = true; + p_vci_target.rdata = 0; + p_vci_target.rerror = VCI_WRITE_ERROR; + break; + } // end switch target fsm + + // p_vci_initiator port + p_vci_initiator.srcid = (sc_dt::sc_uint)m_srcid; + p_vci_initiator.trdid = 0; + p_vci_initiator.contig = true; + p_vci_initiator.cons = false; + p_vci_initiator.wrap = false; + p_vci_initiator.cfixed = false; + p_vci_initiator.clen = 0; + + switch (r_initiator_fsm) { + case M_WRITE_CMD: // It is actually a single flit VCI read command + p_vci_initiator.rspack = false; + p_vci_initiator.cmdval = true; + p_vci_initiator.address = (sc_dt::sc_uint)r_buf_address.read(); + p_vci_initiator.cmd = vci_param::CMD_READ; + p_vci_initiator.pktid = TYPE_READ_DATA_UNC; + p_vci_initiator.wdata = 0; + p_vci_initiator.be = 0; + p_vci_initiator.plen = (sc_dt::sc_uint)(m_burst_size); + p_vci_initiator.eop = true; + break; + case M_READ_CMD: // It is actually a multi-words VCI WRITE command + { + typename vci_param::data_t v = 0; + typename vci_param::data_t f; + p_vci_initiator.rspack = false; + p_vci_initiator.cmdval = true; + p_vci_initiator.address = (sc_dt::sc_uint)r_buf_address.read(); + p_vci_initiator.cmd = vci_param::CMD_WRITE; + p_vci_initiator.pktid = TYPE_WRITE; + p_vci_initiator.plen = (sc_dt::sc_uint)(m_burst_size); + f = r_dma_fifo_read.read(); + // byte-swap + for (int i = 0; i < (vci_param::B * 8); i += 8) { + v |= ((f >> i) & 0xff) << ((vci_param::B * 8) - 8 - i); + } + p_vci_initiator.wdata = v; + p_vci_initiator.eop = ( r_burst_word.read() == 0); + if (vci_param::B == 8) + { + p_vci_initiator.be = 0xFF; + } + else + { + p_vci_initiator.be = 0xF; + } + break; + } + case M_READ_RSP: + case M_WRITE_RSP: + p_vci_initiator.rspack = true; + p_vci_initiator.cmdval = false; + break; + default: + p_vci_initiator.rspack = false; + p_vci_initiator.cmdval = false; + break; + } + + // SPI signals + p_spi_ss = ((r_ss & 0x1) == 0); + switch(r_spi_fsm) { + default: + p_spi_mosi = r_spi_out; + p_spi_clk = 0; + break; + case S_XMIT: + { + bool s_clk_sample = r_spi_clk ^ r_ctrl_cpha; + p_spi_clk = r_spi_clk ^ r_ctrl_cpol; + if (s_clk_sample == 0) { + // clock low: get data directly from shift register + // as r_spi_out may be delayed by one clock cycle + p_spi_mosi = (r_txrx[(r_ctrl_char_len -1)/ 64] >> ((r_ctrl_char_len - 1) % 64)) & (uint64_t)0x0000000000000001ULL; + } else { + // clock high: get data from saved value, as the shift register + // may have changed + p_spi_mosi = r_spi_out; + } + break; + } + } + + // IRQ signal + p_irq = r_irq; +} // end GenMoore() + +////////////////////////////////////////////////////////////////////////////// +tmpl(/**/)::VciSpi( sc_core::sc_module_name name, + const soclib::common::MappingTable &mt, + const soclib::common::IntTab &srcid, + const soclib::common::IntTab &tgtid, + const uint32_t burst_size) + +: caba::BaseModule(name), + m_seglist(mt.getSegmentList(tgtid)), + m_srcid(mt.indexForId(srcid)), + m_burst_size(burst_size), + m_words_per_burst(burst_size / vci_param::B), + m_byte2burst_shift(soclib::common::uint32_log2(burst_size)), + p_clk("p_clk"), + p_resetn("p_resetn"), + p_vci_initiator("p_vci_initiator"), + p_vci_target("p_vci_target"), + p_irq("p_irq"), + p_spi_ss("p_spi_ss"), + p_spi_clk("p_spi_clk"), + p_spi_mosi("p_spi_mosi"), + p_spi_miso("p_spi_miso"), + + r_dma_fifo_read("r_dma_fifo_read", burst_size / vci_param::B), // one cache line + r_dma_fifo_write("r_dma_fifo_read", burst_size / vci_param::B) // one cache line +{ + std::cout << " - Building VciSpi " << name << std::endl; + + SC_METHOD(transition); + dont_initialize(); + sensitive << p_clk.pos(); + + SC_METHOD(genMoore); + dont_initialize(); + sensitive << p_clk.neg(); + + size_t nbsegs = 0; + std::list::iterator seg; + for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) + { + nbsegs++; + + if ( (seg->baseAddress() & 0x0000003F) != 0 ) + { + std::cout << "Error in component VciSpi : " << name + << "The base address of segment " << seg->name() + << " must be multiple of 64 bytes" << std::endl; + exit(1); + } + if ( seg->size() < 64 ) + { + std::cout << "Error in component VciSpi : " << name + << "The size of segment " << seg->name() + << " cannot be smaller than 64 bytes" << std::endl; + exit(1); + } + std::cout << " => segment " << seg->name() + << " / base = " << std::hex << seg->baseAddress() + << " / size = " << seg->size() << std::endl; + } + + if( nbsegs == 0 ) + { + std::cout << "Error in component VciSpi : " << name + << " No segment allocated" << std::endl; + exit(1); + } + + if( (burst_size != 8 ) && + (burst_size != 16) && + (burst_size != 32) && + (burst_size != 64) ) + { + std::cout << "Error in component VciSpi : " << name + << " The burst size must be 8, 16, 32 or 64 bytes" << std::endl; + exit(1); + } + + if ( (vci_param::B != 4) and (vci_param::B != 8) ) + { + std::cout << "Error in component VciSpi : " << name + << " The VCI data fields must have 32 bits or 64 bits" << std::endl; + exit(1); + } + +} // end constructor + +tmpl(/**/)::~VciSpi() +{ +} + + +////////////////////////// +tmpl(void)::print_trace() +{ + const char* initiator_str[] = + { + "M_IDLE", + + "M_READ_WAIT", + "M_READ_CMD", + "M_READ_RSP", + "M_INTR", + + "M_WRITE_WAIT", + "M_WRITE_CMD", + "M_WRITE_RSP", + "M_WRITE_END", + }; + const char* target_str[] = + { + "T_IDLE", + "T_RSP_READ", + "T_RSP_WRITE", + "T_ERROR_READ", + "T_ERROR_WRITE", + }; + const char* spi_str[] = + { + "S_IDLE", + "S_DMA_RECEIVE", + "S_DMA_SEND_START", + "S_DMA_SEND", + "S_DMA_SEND_END", + "S_XMIT", + }; + + std::cout << name() << " _TGT : " << target_str[r_target_fsm.read()] + << std::endl; + std::cout << name() << " _SPI : " << spi_str[r_spi_fsm.read()] + << " clk_counter " << r_spi_clk_counter.read() + << " r_spi_bit_count " << r_spi_bit_count.read() + << " r_spi_bsy " << (int)r_spi_bsy.read() << std::endl; + std::cout << name() << " _SPI : " + << " r_spi_clk " << r_spi_clk.read() + << " cpol " << r_ctrl_cpol.read() + << " cpha " << r_ctrl_cpha.read() + << " r_spi_clk_ignore " << r_spi_clk_ignore.read() + << " r_txrx 0x" << std::hex + << r_txrx[1].read() << " " << r_txrx[0].read() + + << std::endl; + std::cout << name() << " _INI : " << initiator_str[r_initiator_fsm.read()] + << " buf = " << std::hex << r_buf_address.read() + << " burst = " << r_burst_word.read() + << " count = " << r_dma_count.read() + << " spi_count = " << r_spi_word_count.read() + < the 24 LSB bits = 0, and the 16 MSB bits define the target) +// The (x_width + y_width) MSB bits (left aligned) define +// the cluster index, and the LADR bits define the local index: +// | X_ID | Y_ID |---| LADR | OFFSET | +// |x_width|y_width|---| 8 | 24 | +///////////////////////////////////////////////////////////////////////// +// General policy for 14 bits SRCID decoding: +// Each component is identified by (x_id, y_id, l_id) tuple. +// | X_ID | Y_ID |---| L_ID | +// |x_width|y_width|---| 6 | +///////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include +#include +#include +#include + +#include "gdbserver.h" +#include "mapping_table.h" +#include "tsar_xbar_cluster.h" +#include "alloc_elems.h" + +/////////////////////////////////////////////////// +// Parallelisation +/////////////////////////////////////////////////// +#if USE_OPENMP +#include +#endif + +// cluster index (computed from x,y coordinates) +#define cluster(x,y) (y + ymax * x) + +#define min(x, y) (x < y ? x : y) + +/////////////////////////////////////////////////////////// +// DSPIN parameters +/////////////////////////////////////////////////////////// +#define dspin_cmd_width 39 +#define dspin_rsp_width 32 + +/////////////////////////////////////////////////////////// +// VCI parameters +/////////////////////////////////////////////////////////// +#define vci_cell_width_int 4 +#define vci_cell_width_ext 8 +#define vci_address_width 32 +#define vci_plen_width 8 +#define vci_rerror_width 1 +#define vci_clen_width 1 +#define vci_rflag_width 1 +#define vci_srcid_width 14 +#define vci_pktid_width 4 +#define vci_trdid_width 4 +#define vci_wrplen_width 1 + +//////////////////////////////////////////////////////////// +// Main Hardware Parameters values +//////////////////////////////////////////////////////////// +#define CLUSTER_X 1 +#define CLUSTER_Y 1 +#define NB_CLUSTERS 1 +#define NB_PROCS_MAX 4 +#define NB_DMA_CHANNELS 1 +#define NB_TTY_CHANNELS 4 +#define NB_IOC_CHANNELS 1 +#define NB_NIC_CHANNELS 1 +#define NB_CMA_CHANNELS 0 +#define USE_XICU 1 +#define IOMMU_ACTIVE 0 + +//////////////////////////////////////////////////////////// +// Secondary Hardware Parameters +//////////////////////////////////////////////////////////// +#define XRAM_LATENCY 0 + +#define MEMC_WAYS 16 +#define MEMC_SETS 256 + +#define L1_IWAYS 4 +#define L1_ISETS 64 +#define L1_DWAYS 4 +#define L1_DSETS 64 + +#define FBUF_X_SIZE 512 +#define FBUF_Y_SIZE 512 + +#define BDEV_SECTOR_SIZE 4096 +#define BDEV_IMAGE_NAME "hdd-img.bin" + +#define NIC_RX_NAME "rx_packets.txt" +#define NIC_TX_NAME "tx_packets.txt" +#define NIC_TIMEOUT 10000 + +#define NORTH 0 +#define SOUTH 1 +#define EAST 2 +#define WEST 3 + +//////////////////////////////////////////////////////////// +// Software to be loaded in ROM/RAM +//////////////////////////////////////////////////////////// +#define soft_name "bootloader.bin",\ + "kernel-soclib.bin@0xbfc10000:D",\ + "arch-info.bin@0xBFC08000:D" + +//////////////////////////////////////////////////////////// +// DEBUG Parameters default values +//////////////////////////////////////////////////////////// +#define MAX_FROZEN_CYCLES 100000000 + +//////////////////////////////////////////////////////////////////// +// TGTID definition in direct space +// For all components: global TGTID = global SRCID = cluster_index +//////////////////////////////////////////////////////////////////// +#define MEMC_TGTID 0 +#define XICU_TGTID 1 +#define MDMA_TGTID 2 +#define MTTY_TGTID 3 +#define FBUF_TGTID 4 +#define BDEV_TGTID 5 +#define MNIC_TGTID 6 +#define BROM_TGTID 7 +#define CDMA_TGTID 8 +#define SIMH_TGTID 9 + +///////////////////////////////////////////////////////// +// Physical segments definition +///////////////////////////////////////////////////////// +// There is 3 segments replicated in all clusters +// and 5 specific segments in the "IO" cluster +// (containing address 0xBF000000) +///////////////////////////////////////////////////////// +// Physical Address Decoding: 8 GID + 8 LID + 16 offset. +///////////////////////////////////////////////////////// +#define RAM_BASE 0x00000000 +#define RAM_SIZE 0x00C00000 + +#define BROM_BASE 0xBFC00000 +#define BROM_SIZE 0x00100000 + +#define FBUF_BASE 0xBFD00000 +#define FBUF_SIZE 0x00200000 + +#define XICU_BASE 0x00F00000 +#define XICU_SIZE 0x00002000 + +#define BDEV_BASE 0xBFF10000 +#define BDEV_SIZE 0x00000100 + +#define MTTY_BASE 0xBFF20000 +#define MTTY_SIZE 0x00000100 + +#define MDMA_BASE 0x00F30000 +#define MDMA_SIZE 0x00001000 * NB_DMA_CHANNELS // 4 Kbytes per channel + +#define MEMC_BASE 0x00F40000 +#define MEMC_SIZE 0x00001000 + +#define SIMH_BASE 0xBFF50000 +#define SIMH_SIZE 0x00001000 + +#define CDMA_BASE 0xBFF60000 +#define CDMA_SIZE 0x00000100 + +#define MNIC_BASE 0xB0F80000 +#define MNIC_SIZE 0x00080000 // 512 Kbytes (for 8 channels) + +bool stop_called = false; + +///////////////////////////////// +int _main(int argc, char *argv[]) +{ + using namespace sc_core; + using namespace soclib::caba; + using namespace soclib::common; + + uint64_t ncycles = 0xFFFFFFFFFFFFFFFF; // simulated cycles + char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image + char nic_rx_name[256] = NIC_RX_NAME; // pathname to the rx packets file + char nic_tx_name[256] = NIC_TX_NAME; // pathname to the tx packets file + ssize_t threads_nr = 1; // simulator's threads number + bool debug_ok = false; // trace activated + size_t debug_period = 1; // trace period + size_t debug_memc_id = 0; // index of memc to be traced + size_t debug_proc_id = 0; // index of proc to be traced + uint32_t debug_from = 0; // trace start cycle + uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor + size_t xmax = CLUSTER_X; // number of clusters in a row + size_t ymax = CLUSTER_Y; // number of clusters in a column + size_t nprocs = NB_PROCS_MAX; // number of processors per cluster + size_t xfb = FBUF_X_SIZE; // frameBuffer column number + size_t yfb = FBUF_Y_SIZE; // frameBuffer lines number + size_t fb_mode = 420; + size_t ram_size = RAM_SIZE; + size_t blk_size = BDEV_SECTOR_SIZE; + size_t l1_i_ways = L1_IWAYS; + size_t l1_d_ways = L1_DWAYS; + size_t l1_i_sets = L1_ISETS; + size_t l1_d_sets = L1_DSETS; + size_t memc_sets = MEMC_SETS; + size_t memc_ways = MEMC_WAYS; + size_t xram_latency = XRAM_LATENCY; + size_t xicu_base = XICU_BASE; + size_t mdma_base = MDMA_BASE; + size_t memc_base = MEMC_BASE; + bool isRamSizeSet = false; + size_t cluster_io_id; // index of cluster containing IOs + struct timeval t1,t2; + uint64_t ms1,ms2; + + ////////////// command line arguments ////////////////////// + if (argc > 1) + { + for (int n = 1; n < argc; n = n + 2) + { + if ((strcmp(argv[n], "-NCYCLES") == 0) && (n + 1 < argc)) + { + ncycles = atoi(argv[n + 1]); + } + else if( (strcmp(argv[n],"-NPROCS") == 0) && (n+1 vci_param_int; + + typedef soclib::caba::VciParams vci_param_ext; + +#if USE_OPENMP + omp_set_dynamic(false); + omp_set_num_threads(threads_nr); + std::cerr << "Built with openmp version " << _OPENMP << std::endl; +#endif + + // Define parameters depending on mesh size + size_t x_width; + size_t y_width; + + if (xmax == 1) x_width = 0; + else if (xmax == 2) x_width = 1; + else if (xmax <= 4) x_width = 2; + else if (xmax <= 8) x_width = 3; + else x_width = 4; + + if (ymax == 1) y_width = 0; + else if (ymax == 2) y_width = 1; + else if (ymax <= 4) y_width = 2; + else if (ymax <= 8) y_width = 3; + else y_width = 4; + + if((xmax == 1) && (ymax == 1)) + { + cluster_io_id = 0; + ram_size = (isRamSizeSet == true) ? ram_size : 0x8000000; + xicu_base = 0x80f00000; + memc_base = 0x80f40000; + mdma_base = 0x80f30000; + } + else + cluster_io_id = 0xbfc00000 >> (vci_address_width - x_width - y_width); // index of cluster containing IOs + + ///////////////////// + // Mapping Tables + ///////////////////// + + // internal network + MappingTable maptabd(vci_address_width, + IntTab(x_width + y_width, 16 - x_width - y_width), + IntTab(x_width + y_width, vci_srcid_width - x_width - y_width), + 0x00FFFF0000); + + for (size_t x = 0; x < xmax; x++) + { + for (size_t y = 0; y < ymax; y++) + { + sc_uint offset; + offset = (sc_uint)cluster(x,y) + << (vci_address_width-x_width-y_width); + + std::ostringstream si; + si << "seg_xicu_" << x << "_" << y; + maptabd.add(Segment(si.str(), xicu_base + offset, XICU_SIZE, + IntTab(cluster(x,y),XICU_TGTID), false)); + + std::ostringstream sd; + sd << "seg_mdma_" << x << "_" << y; + maptabd.add(Segment(sd.str(), mdma_base + offset, MDMA_SIZE, + IntTab(cluster(x,y),MDMA_TGTID), false)); + + std::ostringstream sh; + sh << "seg_ram_" << x << "_" << y; + maptabd.add(Segment(sh.str(), RAM_BASE + offset, ram_size, + IntTab(cluster(x,y),MEMC_TGTID), true)); + + std::ostringstream sconf; + sconf << "seg_memc_config_" << x << "_" << y; + maptabd.add(Segment(sconf.str(), memc_base + offset, MEMC_SIZE, + IntTab(cluster(x,y),MEMC_TGTID), true, true)); + + if ( cluster(x,y) == cluster_io_id ) + { + maptabd.add(Segment("seg_mtty", MTTY_BASE, MTTY_SIZE, + IntTab(cluster(x,y),MTTY_TGTID), false)); + maptabd.add(Segment("seg_fbuf", FBUF_BASE, FBUF_SIZE, + IntTab(cluster(x,y),FBUF_TGTID), false)); + maptabd.add(Segment("seg_bdev", BDEV_BASE, BDEV_SIZE, + IntTab(cluster(x,y),BDEV_TGTID), false)); + maptabd.add(Segment("seg_brom", BROM_BASE, BROM_SIZE, + IntTab(cluster(x,y),BROM_TGTID), true)); + maptabd.add(Segment("seg_mnic", MNIC_BASE, MNIC_SIZE, + IntTab(cluster(x,y),MNIC_TGTID), false)); + maptabd.add(Segment("seg_cdma", CDMA_BASE, CDMA_SIZE, + IntTab(cluster(x,y),CDMA_TGTID), false)); + maptabd.add(Segment("seg_simh", SIMH_BASE, SIMH_SIZE, + IntTab(cluster(x,y),SIMH_TGTID), false)); + } + } + } + std::cout << maptabd << std::endl; + + // external network + MappingTable maptabx(vci_address_width, + IntTab(x_width+y_width), + IntTab(x_width+y_width), + 0x00FFFF0000ULL); + + for (size_t x = 0; x < xmax; x++) + { + for (size_t y = 0; y < ymax ; y++) + { + + sc_uint offset; + offset = (sc_uint)cluster(x,y) + << (vci_address_width-x_width-y_width); + + std::ostringstream sh; + sh << "x_seg_memc_" << x << "_" << y; + + maptabx.add(Segment(sh.str(), RAM_BASE + offset, + ram_size, IntTab(cluster(x,y)), false)); + } + } + std::cout << maptabx << std::endl; + + //////////////////// + // Signals + /////////////////// + + std::cout << "Clock .. "; + sc_clock signal_clk("clk"); + std::cout << ". [OK]" << std::endl; + sc_signal signal_resetn("resetn"); + + // Horizontal inter-clusters DSPIN signals + DspinSignals*** signal_dspin_h_cmd_inc = + alloc_elems >("signal_dspin_h_cmd_inc", xmax-1, ymax, 3); + + DspinSignals*** signal_dspin_h_cmd_dec = + alloc_elems >("signal_dspin_h_cmd_dec", xmax-1, ymax, 3); + + DspinSignals*** signal_dspin_h_rsp_inc = + alloc_elems >("signal_dspin_h_rsp_inc", xmax-1, ymax, 2); + DspinSignals*** signal_dspin_h_rsp_dec = + alloc_elems >("signal_dspin_h_rsp_dec", xmax-1, ymax, 2); + + // Vertical inter-clusters DSPIN signals + DspinSignals*** signal_dspin_v_cmd_inc = + alloc_elems >("signal_dspin_v_cmd_inc", xmax, ymax-1, 3); + DspinSignals*** signal_dspin_v_cmd_dec = + alloc_elems >("signal_dspin_v_cmd_dec", xmax, ymax-1, 3); + DspinSignals*** signal_dspin_v_rsp_inc = + alloc_elems >("signal_dspin_v_rsp_inc", xmax, ymax-1, 2); + DspinSignals*** signal_dspin_v_rsp_dec = + alloc_elems >("signal_dspin_v_rsp_dec", xmax, ymax-1, 2); + + // Mesh boundaries DSPIN signals + DspinSignals**** signal_dspin_false_cmd_in = + alloc_elems >("signal_dspin_false_cmd_in" , xmax, ymax, 4, 3); + DspinSignals**** signal_dspin_false_cmd_out = + alloc_elems >("signal_dspin_false_cmd_out", xmax, ymax, 4, 3); + DspinSignals**** signal_dspin_false_rsp_in = + alloc_elems >("signal_dspin_false_rsp_in" , xmax, ymax, 4, 2); + DspinSignals**** signal_dspin_false_rsp_out = + alloc_elems >("signal_dspin_false_rsp_out", xmax, ymax, 4, 2); + + //////////////////////////// + // Loader + //////////////////////////// + + soclib::common::Loader loader(soft_name); + + typedef soclib::common::GdbServer proc_iss; + proc_iss::set_loader(loader); + + //////////////////////////// + // Clusters construction + //////////////////////////// + + TsarXbarCluster* clusters[xmax][ymax]; + +#if USE_OPENMP +#pragma omp parallel + { +#pragma omp for +#endif + for (size_t i = 0; i < (xmax * ymax); i++) + { + size_t x = i / ymax; + size_t y = i % ymax; + +#if USE_OPENMP +#pragma omp critical + { +#endif + std::cout << std::endl; + std::cout << "Cluster_" << x << "_" << y << std::endl; + std::cout << std::endl; + + std::ostringstream sc; + sc << "cluster_" << x << "_" << y; + clusters[x][y] = new TsarXbarCluster + ( + sc.str().c_str(), + nprocs, + NB_TTY_CHANNELS, + NB_DMA_CHANNELS, + x, + y, + cluster(x,y), + maptabd, + maptabx, + x_width, + y_width, + vci_srcid_width - x_width - y_width, // l_id width, + MEMC_TGTID, + XICU_TGTID, + MDMA_TGTID, + FBUF_TGTID, + MTTY_TGTID, + BROM_TGTID, + MNIC_TGTID, + CDMA_TGTID, + BDEV_TGTID, + SIMH_TGTID, + memc_ways, + memc_sets, + l1_i_ways, + l1_i_sets, + l1_d_ways, + l1_d_sets, + xram_latency, + (cluster(x,y) == cluster_io_id), + xfb, + yfb, + disk_name, + blk_size, + NB_NIC_CHANNELS, + nic_rx_name, + nic_tx_name, + NIC_TIMEOUT, + NB_CMA_CHANNELS, + loader, + frozen_cycles, + debug_from , + debug_ok and (cluster(x,y) == debug_memc_id), + debug_ok and (cluster(x,y) == debug_proc_id) + ); + +#if USE_OPENMP + } // end critical +#endif + } // end for +#if USE_OPENMP + } +#endif + + /////////////////////////////////////////////////////////////// + // Net-list + /////////////////////////////////////////////////////////////// + + // Clock & RESET + for (size_t x = 0; x < (xmax); x++){ + for (size_t y = 0; y < ymax; y++){ + clusters[x][y]->p_clk (signal_clk); + clusters[x][y]->p_resetn (signal_resetn); + } + } + + // Inter Clusters horizontal connections + if (xmax > 1){ + for (size_t x = 0; x < (xmax-1); x++){ + for (size_t y = 0; y < ymax; y++){ + for (size_t k = 0; k < 3; k++){ + clusters[x][y]->p_cmd_out[EAST][k] (signal_dspin_h_cmd_inc[x][y][k]); + clusters[x+1][y]->p_cmd_in[WEST][k] (signal_dspin_h_cmd_inc[x][y][k]); + clusters[x][y]->p_cmd_in[EAST][k] (signal_dspin_h_cmd_dec[x][y][k]); + clusters[x+1][y]->p_cmd_out[WEST][k] (signal_dspin_h_cmd_dec[x][y][k]); + } + + for (size_t k = 0; k < 2; k++){ + clusters[x][y]->p_rsp_out[EAST][k] (signal_dspin_h_rsp_inc[x][y][k]); + clusters[x+1][y]->p_rsp_in[WEST][k] (signal_dspin_h_rsp_inc[x][y][k]); + clusters[x][y]->p_rsp_in[EAST][k] (signal_dspin_h_rsp_dec[x][y][k]); + clusters[x+1][y]->p_rsp_out[WEST][k] (signal_dspin_h_rsp_dec[x][y][k]); + } + } + } + } + std::cout << std::endl << "Horizontal connections established" << std::endl; + + // Inter Clusters vertical connections + if (ymax > 1) { + for (size_t y = 0; y < (ymax-1); y++){ + for (size_t x = 0; x < xmax; x++){ + for (size_t k = 0; k < 3; k++){ + clusters[x][y]->p_cmd_out[NORTH][k] (signal_dspin_v_cmd_inc[x][y][k]); + clusters[x][y+1]->p_cmd_in[SOUTH][k] (signal_dspin_v_cmd_inc[x][y][k]); + clusters[x][y]->p_cmd_in[NORTH][k] (signal_dspin_v_cmd_dec[x][y][k]); + clusters[x][y+1]->p_cmd_out[SOUTH][k] (signal_dspin_v_cmd_dec[x][y][k]); + } + + for (size_t k = 0; k < 2; k++){ + clusters[x][y]->p_rsp_out[NORTH][k] (signal_dspin_v_rsp_inc[x][y][k]); + clusters[x][y+1]->p_rsp_in[SOUTH][k] (signal_dspin_v_rsp_inc[x][y][k]); + clusters[x][y]->p_rsp_in[NORTH][k] (signal_dspin_v_rsp_dec[x][y][k]); + clusters[x][y+1]->p_rsp_out[SOUTH][k] (signal_dspin_v_rsp_dec[x][y][k]); + } + } + } + } + std::cout << "Vertical connections established" << std::endl; + + // East & West boundary cluster connections + for (size_t y = 0; y < ymax; y++) + { + for (size_t k = 0; k < 3; k++) + { + clusters[0][y]->p_cmd_in[WEST][k] (signal_dspin_false_cmd_in[0][y][WEST][k]); + clusters[0][y]->p_cmd_out[WEST][k] (signal_dspin_false_cmd_out[0][y][WEST][k]); + clusters[xmax-1][y]->p_cmd_in[EAST][k] (signal_dspin_false_cmd_in[xmax-1][y][EAST][k]); + clusters[xmax-1][y]->p_cmd_out[EAST][k] (signal_dspin_false_cmd_out[xmax-1][y][EAST][k]); + } + + for (size_t k = 0; k < 2; k++) + { + clusters[0][y]->p_rsp_in[WEST][k] (signal_dspin_false_rsp_in[0][y][WEST][k]); + clusters[0][y]->p_rsp_out[WEST][k] (signal_dspin_false_rsp_out[0][y][WEST][k]); + clusters[xmax-1][y]->p_rsp_in[EAST][k] (signal_dspin_false_rsp_in[xmax-1][y][EAST][k]); + clusters[xmax-1][y]->p_rsp_out[EAST][k] (signal_dspin_false_rsp_out[xmax-1][y][EAST][k]); + } + } + + // North & South boundary clusters connections + for (size_t x = 0; x < xmax; x++) + { + for (size_t k = 0; k < 3; k++) + { + clusters[x][0]->p_cmd_in[SOUTH][k] (signal_dspin_false_cmd_in[x][0][SOUTH][k]); + clusters[x][0]->p_cmd_out[SOUTH][k] (signal_dspin_false_cmd_out[x][0][SOUTH][k]); + clusters[x][ymax-1]->p_cmd_in[NORTH][k] (signal_dspin_false_cmd_in[x][ymax-1][NORTH][k]); + clusters[x][ymax-1]->p_cmd_out[NORTH][k] (signal_dspin_false_cmd_out[x][ymax-1][NORTH][k]); + } + + for (size_t k = 0; k < 2; k++) + { + clusters[x][0]->p_rsp_in[SOUTH][k] (signal_dspin_false_rsp_in[x][0][SOUTH][k]); + clusters[x][0]->p_rsp_out[SOUTH][k] (signal_dspin_false_rsp_out[x][0][SOUTH][k]); + clusters[x][ymax-1]->p_rsp_in[NORTH][k] (signal_dspin_false_rsp_in[x][ymax-1][NORTH][k]); + clusters[x][ymax-1]->p_rsp_out[NORTH][k] (signal_dspin_false_rsp_out[x][ymax-1][NORTH][k]); + } + } + std::cout << "North, South, West, East connections established" << std::endl; + std::cout << std::endl; + + + //////////////////////////////////////////////////////// + // Simulation + /////////////////////////////////////////////////////// + + sc_start(sc_core::sc_time(0, SC_NS)); + signal_resetn = false; + + // network boundaries signals + for (size_t x = 0; x < xmax ; x++){ + for (size_t y = 0; y < ymax ; y++){ + for (size_t a = 0; a < 4; a++){ + for (size_t k = 0; k < 3; k++){ + signal_dspin_false_cmd_in [x][y][a][k].write = false; + signal_dspin_false_cmd_in [x][y][a][k].read = true; + signal_dspin_false_cmd_out[x][y][a][k].write = false; + signal_dspin_false_cmd_out[x][y][a][k].read = true; + } + + for (size_t k = 0; k < 2; k++){ + signal_dspin_false_rsp_in [x][y][a][k].write = false; + signal_dspin_false_rsp_in [x][y][a][k].read = true; + signal_dspin_false_rsp_out[x][y][a][k].write = false; + signal_dspin_false_rsp_out[x][y][a][k].read = true; + } + } + } + } + +#define STATS_CYCLES 10000000 + + sc_start(sc_core::sc_time(1, SC_NS)); + signal_resetn = true; + + uint64_t n = 0; + + while (!stop_called) { + if (gettimeofday(&t1, NULL) != 0) { + perror("gettimeofday"); + return EXIT_FAILURE; + } + sc_start(STATS_CYCLES); + n += STATS_CYCLES; + if (gettimeofday(&t2, NULL) != 0) { + perror("gettimeofday"); + return EXIT_FAILURE; + } + ms1 = (uint64_t)t1.tv_sec * 1000ULL + (uint64_t)t1.tv_usec / 1000; + ms2 = (uint64_t)t2.tv_sec * 1000ULL + (uint64_t)t2.tv_usec / 1000; + std::cerr << "cycle " << n + << " platform clock frequency " + << (double)STATS_CYCLES / (double)(ms2 - ms1) + << "Khz" << std::endl; + } + + // Free memory + for (size_t i = 0; i < (xmax * ymax); i++) + { + size_t x = i / ymax; + size_t y = i % ymax; + delete clusters[x][y]; + } + + dealloc_elems >(signal_dspin_h_cmd_inc, xmax - 1, ymax, 3); + dealloc_elems >(signal_dspin_h_cmd_dec, xmax - 1, ymax, 3); + dealloc_elems >(signal_dspin_h_rsp_inc, xmax - 1, ymax, 2); + dealloc_elems >(signal_dspin_h_rsp_dec, xmax - 1, ymax, 2); + dealloc_elems >(signal_dspin_v_cmd_inc, xmax, ymax - 1, 3); + dealloc_elems >(signal_dspin_v_cmd_dec, xmax, ymax - 1, 3); + dealloc_elems >(signal_dspin_v_rsp_inc, xmax, ymax - 1, 2); + dealloc_elems >(signal_dspin_v_rsp_dec, xmax, ymax - 1, 2); + dealloc_elems >(signal_dspin_false_cmd_in, xmax, ymax, 4, 3); + dealloc_elems >(signal_dspin_false_cmd_out, xmax, ymax, 4, 3); + dealloc_elems >(signal_dspin_false_rsp_in, xmax, ymax, 4, 2); + dealloc_elems >(signal_dspin_false_rsp_out, xmax, ymax, 4, 2); + + return EXIT_SUCCESS; +} + + +void handler(int dummy = 0) { + stop_called = true; + sc_stop(); +} + +void voidhandler(int dummy = 0) {} + +int sc_main (int argc, char *argv[]) +{ + signal(SIGINT, handler); + signal(SIGPIPE, voidhandler); + + try { + return _main(argc, argv); + } catch (std::exception &e) { + std::cout << e.what() << std::endl; + } catch (...) { + std::cout << "Unknown exception occured" << std::endl; + throw; + } + return 1; +} + + +// Local Variables: +// tab-width: 3 +// c-basic-offset: 3 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 Index: /branches/fault_tolerance/platforms/almos-tsar-mipsel/top.desc =================================================================== --- /branches/fault_tolerance/platforms/almos-tsar-mipsel/top.desc (revision 724) +++ /branches/fault_tolerance/platforms/almos-tsar-mipsel/top.desc (revision 724) @@ -0,0 +1,46 @@ + +# -*- python -*- + +# internal VCI parameters values +vci_cell_size_int = 4 +vci_cell_size_ext = 8 + +vci_plen_size = 8 +vci_addr_size = 32 +vci_rerror_size = 1 +vci_clen_size = 1 +vci_rflag_size = 1 +vci_srcid_size = 14 +vci_pktid_size = 4 +vci_trdid_size = 4 +vci_wrplen_size = 1 + +# DSPIN network parameters values +dspin_cmd_flit_size = 39 +dspin_rsp_flit_size = 32 + +todo = Platform('caba', 'top.cpp', + + uses = [ + Uses('caba:tsar_xbar_cluster_almos', + vci_data_width_int = vci_cell_size_int, + vci_data_width_ext = vci_cell_size_ext, + dspin_cmd_width = dspin_cmd_flit_size, + dspin_rsp_width = dspin_rsp_flit_size), + + Uses('common:elf_file_loader'), + Uses('common:plain_file_loader'), + ], + + # default VCI parameters (global variables) + cell_size = vci_cell_size_int, + plen_size = vci_plen_size, + addr_size = vci_addr_size, + rerror_size = vci_rerror_size, + clen_size = vci_clen_size, + rflag_size = vci_rflag_size, + srcid_size = vci_srcid_size, + pktid_size = vci_pktid_size, + trdid_size = vci_trdid_size, + wrplen_size = vci_wrplen_size, +) Index: /branches/fault_tolerance/platforms/almos-tsar-mipsel/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd =================================================================== --- /branches/fault_tolerance/platforms/almos-tsar-mipsel/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd (revision 724) +++ /branches/fault_tolerance/platforms/almos-tsar-mipsel/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd (revision 724) @@ -0,0 +1,107 @@ + +# -*- python -*- + +Module('caba:tsar_xbar_cluster_almos', + classname = 'soclib::caba::TsarXbarCluster', + tmpl_parameters = [ + parameter.Int('dspin_cmd_width'), + parameter.Int('dspin_rsp_width'), + parameter.Module('vci_param_int', default = 'caba:vci_param', + cell_size = parameter.Reference('vci_data_width_int')), + parameter.Module('vci_param_ext', default = 'caba:vci_param', + cell_size = parameter.Reference('vci_data_width_ext')), + ], + + header_files = [ '../source/include/tsar_xbar_cluster.h', + ], + + implementation_files = [ '../source/src/tsar_xbar_cluster.cpp', + ], + + uses = [ + Uses('caba:base_module'), + Uses('common:mapping_table'), + Uses('common:iss2'), + + Uses('caba:vci_cc_vcache_wrapper', + cell_size = parameter.Reference('vci_data_width_int'), + dspin_in_width = parameter.Reference('dspin_cmd_width'), + dspin_out_width = parameter.Reference('dspin_rsp_width'), + iss_t = 'common:gdb_iss', + gdb_iss_t = 'common:mips32el'), + + Uses('caba:vci_mem_cache', + memc_cell_size_int = parameter.Reference('vci_data_width_int'), + memc_cell_size_ext = parameter.Reference('vci_data_width_ext'), + dspin_in_width = parameter.Reference('dspin_rsp_width'), + dspin_out_width = parameter.Reference('dspin_cmd_width')), + + Uses('caba:vci_simple_rom', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_simple_ram', + cell_size = parameter.Reference('vci_data_width_ext')), + + Uses('caba:vci_simple_ram', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_xicu', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:dspin_local_crossbar', + flit_width = parameter.Reference('dspin_cmd_width')), + + Uses('caba:dspin_local_crossbar', + flit_width = parameter.Reference('dspin_rsp_width')), + + Uses('caba:virtual_dspin_router', + flit_width = parameter.Reference('dspin_cmd_width')), + + Uses('caba:virtual_dspin_router', + flit_width = parameter.Reference('dspin_rsp_width')), + + Uses('caba:vci_multi_tty', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_framebuffer', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_multi_nic', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_chbuf_dma', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_block_device_tsar', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_multi_dma', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_dspin_target_wrapper', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_dspin_initiator_wrapper', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_simhelper', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('common:elf_file_loader'), + ], + + ports = [ + Port('caba:bit_in', 'p_resetn', auto = 'resetn'), + Port('caba:clock_in', 'p_clk', auto = 'clock'), + Port('caba:dspin_output', 'p_cmd_out', [4, 3], + dspin_data_size = parameter.Reference('dspin_cmd_width')), + Port('caba:dspin_input', 'p_cmd_in', [4, 3], + dspin_data_size = parameter.Reference('dspin_cmd_width')), + Port('caba:dspin_output', 'p_rsp_out', [4, 2], + dspin_data_size = parameter.Reference('dspin_rsp_width')), + Port('caba:dspin_input', 'p_rsp_in', [4, 2], + dspin_data_size = parameter.Reference('dspin_rsp_width')), + ], +) + + Index: /branches/fault_tolerance/platforms/almos-tsar-mipsel/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h =================================================================== --- /branches/fault_tolerance/platforms/almos-tsar-mipsel/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h (revision 724) +++ /branches/fault_tolerance/platforms/almos-tsar-mipsel/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h (revision 724) @@ -0,0 +1,292 @@ +////////////////////////////////////////////////////////////////////////////// +// File: tsar_xbar_cluster.h +// Author: Alain Greiner +// Copyright: UPMC/LIP6 +// Date : march 2013 +// This program is released under the GNU public license +////////////////////////////////////////////////////////////////////////////// + +#ifndef SOCLIB_CABA_TSAR_XBAR_CLUSTER_H +#define SOCLIB_CABA_TSAR_XBAR_CLUSTER_H + +#include +#include +#include +#include +#include +#include + +#include "gdbserver.h" +#include "mapping_table.h" +#include "mips32.h" +#include "vci_simple_ram.h" +#include "vci_simple_rom.h" +#include "vci_xicu.h" +#include "dspin_local_crossbar.h" +#include "vci_dspin_initiator_wrapper.h" +#include "vci_dspin_target_wrapper.h" +#include "virtual_dspin_router.h" +#include "vci_multi_tty.h" +#include "vci_multi_nic.h" +#include "vci_chbuf_dma.h" +#include "vci_block_device_tsar.h" +#include "vci_framebuffer.h" +#include "vci_multi_dma.h" +#include "vci_mem_cache.h" +#include "vci_cc_vcache_wrapper.h" +#include "vci_simhelper.h" + +namespace soclib { namespace caba { + +/////////////////////////////////////////////////////////////////////////// +template class TsarXbarCluster +/////////////////////////////////////////////////////////////////////////// + : public soclib::caba::BaseModule +{ + public: + + // Used in destructor + size_t n_procs; + + // Ports + sc_in p_clk; + sc_in p_resetn; + soclib::caba::DspinOutput **p_cmd_out; + soclib::caba::DspinInput **p_cmd_in; + soclib::caba::DspinOutput **p_rsp_out; + soclib::caba::DspinInput **p_rsp_in; + + // interrupt signals + sc_signal signal_false; + sc_signal signal_irq_memc; + sc_signal signal_proc_it[8]; + sc_signal signal_irq_mdma[8]; + sc_signal signal_irq_mtty[23]; + sc_signal signal_irq_mnic_rx[8]; // unused + sc_signal signal_irq_mnic_tx[8]; // unused + sc_signal signal_irq_chbuf[8]; // unused + sc_signal signal_irq_bdev; + + // DSPIN signals between DSPIN routers and local_crossbars + DspinSignals signal_dspin_cmd_l2g_d; + DspinSignals signal_dspin_cmd_g2l_d; + DspinSignals signal_dspin_m2p_l2g_c; + DspinSignals signal_dspin_m2p_g2l_c; + DspinSignals signal_dspin_clack_l2g_c; + DspinSignals signal_dspin_clack_g2l_c; + DspinSignals signal_dspin_rsp_l2g_d; + DspinSignals signal_dspin_rsp_g2l_d; + DspinSignals signal_dspin_p2m_l2g_c; + DspinSignals signal_dspin_p2m_g2l_c; + + // Direct VCI signals to VCI/DSPIN wrappers + VciSignals signal_vci_ini_proc[8]; + VciSignals signal_vci_ini_mdma; + VciSignals signal_vci_ini_bdev; + VciSignals signal_vci_ini_chbuf; + + VciSignals signal_vci_tgt_memc; + VciSignals signal_vci_tgt_xicu; + VciSignals signal_vci_tgt_mdma; + VciSignals signal_vci_tgt_mtty; + VciSignals signal_vci_tgt_bdev; + VciSignals signal_vci_tgt_brom; + VciSignals signal_vci_tgt_fbuf; + VciSignals signal_vci_tgt_mnic; + VciSignals signal_vci_tgt_chbuf; + VciSignals signal_vci_tgt_simh; + + // Direct DSPIN signals to local crossbars + DspinSignals signal_dspin_cmd_proc_i[8]; + DspinSignals signal_dspin_rsp_proc_i[8]; + DspinSignals signal_dspin_cmd_mdma_i; + DspinSignals signal_dspin_rsp_mdma_i; + DspinSignals signal_dspin_cmd_bdev_i; + DspinSignals signal_dspin_rsp_bdev_i; + DspinSignals signal_dspin_cmd_chbuf_i; + DspinSignals signal_dspin_rsp_chbuf_i; + + DspinSignals signal_dspin_cmd_memc_t; + DspinSignals signal_dspin_rsp_memc_t; + DspinSignals signal_dspin_cmd_xicu_t; + DspinSignals signal_dspin_rsp_xicu_t; + DspinSignals signal_dspin_cmd_mdma_t; + DspinSignals signal_dspin_rsp_mdma_t; + DspinSignals signal_dspin_cmd_mtty_t; + DspinSignals signal_dspin_rsp_mtty_t; + DspinSignals signal_dspin_cmd_bdev_t; + DspinSignals signal_dspin_rsp_bdev_t; + DspinSignals signal_dspin_cmd_brom_t; + DspinSignals signal_dspin_rsp_brom_t; + DspinSignals signal_dspin_cmd_fbuf_t; + DspinSignals signal_dspin_rsp_fbuf_t; + DspinSignals signal_dspin_cmd_mnic_t; + DspinSignals signal_dspin_rsp_mnic_t; + DspinSignals signal_dspin_cmd_chbuf_t; + DspinSignals signal_dspin_rsp_chbuf_t; + DspinSignals signal_dspin_cmd_simh_t; + DspinSignals signal_dspin_rsp_simh_t; + + // Coherence DSPIN signals to local crossbar + DspinSignals signal_dspin_m2p_memc; + DspinSignals signal_dspin_clack_memc; + DspinSignals signal_dspin_p2m_memc; + DspinSignals signal_dspin_m2p_proc[8]; + DspinSignals signal_dspin_clack_proc[8]; + DspinSignals signal_dspin_p2m_proc[8]; + + // external RAM to MEMC VCI signal + VciSignals signal_vci_xram; + + // Components + + VciCcVCacheWrapper >* proc[8]; + + VciDspinInitiatorWrapper* wi_proc[8]; + + VciMemCache* memc; + + VciDspinTargetWrapper* wt_memc; + + VciXicu* xicu; + + VciDspinTargetWrapper* wt_xicu; + + VciMultiDma* mdma; + + VciDspinInitiatorWrapper* wi_mdma; + + VciDspinTargetWrapper* wt_mdma; + + VciSimpleRam* xram; + + VciSimpleRom* brom; + + VciDspinTargetWrapper* wt_brom; + + VciMultiTty* mtty; + + VciDspinTargetWrapper* wt_mtty; + + VciSimhelper* simhelper; + + VciDspinTargetWrapper* wt_simhelper; + + + VciFrameBuffer* fbuf; + + VciDspinTargetWrapper* wt_fbuf; + + VciMultiNic* mnic; + + VciDspinTargetWrapper* wt_mnic; + + VciChbufDma* chbuf; + + VciDspinTargetWrapper* wt_chbuf; + + VciDspinInitiatorWrapper* wi_chbuf; + + VciBlockDeviceTsar* bdev; + + VciDspinInitiatorWrapper* wi_bdev; + + VciDspinTargetWrapper* wt_bdev; + + DspinLocalCrossbar* xbar_cmd_d; + DspinLocalCrossbar* xbar_rsp_d; + DspinLocalCrossbar* xbar_m2p_c; + DspinLocalCrossbar* xbar_p2m_c; + DspinLocalCrossbar* xbar_clack_c; + + VirtualDspinRouter* router_cmd; + VirtualDspinRouter* router_rsp; + + TsarXbarCluster( sc_module_name insname, + size_t nb_procs, // processors + size_t nb_ttys, // TTY terminals + size_t nb_dmas, // DMA channels + size_t x, // x coordinate + size_t y, // y coordinate + size_t cluster, // y + ymax*x + const soclib::common::MappingTable &mtd, // internal + const soclib::common::MappingTable &mtx, // external + size_t x_width, // x field bits + size_t y_width, // y field bits + size_t l_width, // l field bits + size_t tgtid_memc, + size_t tgtid_xicu, + size_t tgtid_mdma, + size_t tgtid_fbuf, + size_t tgtid_mtty, + size_t tgtid_brom, + size_t tgtid_mnic, + size_t tgtid_chbuf, + size_t tgtid_bdev, + size_t tgtid_simh, + size_t memc_ways, + size_t memc_sets, + size_t l1_i_ways, + size_t l1_i_sets, + size_t l1_d_ways, + size_t l1_d_sets, + size_t xram_latency, // external ram + bool io, // I/O cluster + size_t xfb, // fbf pixels + size_t yfb, // fbf lines + char* disk_name, // virtual disk + size_t block_size, // block size + size_t nic_channels, // number channels + char* nic_rx_name, // filename rx + char* nic_tx_name, // filename tx + uint32_t nic_timeout, // cycles + size_t chbufdma_channels, // number channels + const Loader &loader, + uint32_t frozen_cycles, + uint32_t start_debug_cycle, + bool memc_debug_ok, + bool proc_debug_ok); + + ~TsarXbarCluster(); + +}; +}} + +#endif Index: /branches/fault_tolerance/platforms/almos-tsar-mipsel/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp =================================================================== --- /branches/fault_tolerance/platforms/almos-tsar-mipsel/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp (revision 724) +++ /branches/fault_tolerance/platforms/almos-tsar-mipsel/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp (revision 724) @@ -0,0 +1,903 @@ +////////////////////////////////////////////////////////////////////////////// +// File: tsar_xbar_cluster.cpp +// Author: Alain Greiner +// Copyright: UPMC/LIP6 +// Date : march 2011 +// This program is released under the GNU public license +////////////////////////////////////////////////////////////////////////////// +// This file define a TSAR cluster architecture with virtual memory: +// - It uses two virtual_dspin_router as distributed global interconnect +// - It uses four dspin_local_crossbar as local interconnect +// - It uses the vci_cc_vcache_wrapper +// - It uses the vci_mem_cache +// - It contains a private RAM with a variable latency to emulate the L3 cache +// - It can contains 1, 2 or 4 processors +// - Each processor has a private dma channel (vci_multi_dma) +// - It uses the vci_xicu interrupt controller +// - The peripherals MTTY, BDEV, FBUF, MNIC and BROM are in cluster (0,0) +// - The Multi-TTY component controls up to 15 terminals. +// - Each Multi-DMA component controls up to 8 DMA channels. +// - The DMA IRQs are connected to IRQ_IN[8]...IRQ_IN[15] +// - The TTY IRQs are connected to IRQ_IN[16]...IRQ_IN[30] +// - The BDEV IRQ is connected to IRQ_IN[31] +////////////////////////////////////////////////////////////////////////////////// + +#include "../include/tsar_xbar_cluster.h" + + +namespace soclib { +namespace caba { + +//////////////////////////////////////////////////////////////////////////////////// +template TsarXbarCluster::TsarXbarCluster( +//////////////////////////////////////////////////////////////////////////////////// + sc_module_name insname, + size_t nb_procs, + size_t nb_ttys, + size_t nb_dmas, + size_t x_id, + size_t y_id, + size_t cluster_id, + const soclib::common::MappingTable &mtd, + const soclib::common::MappingTable &mtx, + size_t x_width, + size_t y_width, + size_t l_width, + size_t tgtid_memc, + size_t tgtid_xicu, + size_t tgtid_mdma, + size_t tgtid_fbuf, + size_t tgtid_mtty, + size_t tgtid_brom, + size_t tgtid_mnic, + size_t tgtid_chbuf, + size_t tgtid_bdev, + size_t tgtid_simh, + size_t memc_ways, + size_t memc_sets, + size_t l1_i_ways, + size_t l1_i_sets, + size_t l1_d_ways, + size_t l1_d_sets, + size_t xram_latency, + bool io, + size_t xfb, + size_t yfb, + char* disk_name, + size_t block_size, + size_t nic_channels, + char* nic_rx_name, + char* nic_tx_name, + uint32_t nic_timeout, + size_t chbufdma_channels, + const Loader &loader, + uint32_t frozen_cycles, + uint32_t debug_start_cycle, + bool memc_debug_ok, + bool proc_debug_ok) + : soclib::caba::BaseModule(insname), + p_clk("clk"), + p_resetn("resetn") + +{ + + n_procs = nb_procs; + + // Vectors of ports definition + p_cmd_in = alloc_elems > ("p_cmd_in", 4, 3); + p_cmd_out = alloc_elems > ("p_cmd_out", 4, 3); + p_rsp_in = alloc_elems > ("p_rsp_in", 4, 2); + p_rsp_out = alloc_elems > ("p_rsp_out", 4, 2); + + ///////////////////////////////////////////////////////////////////////////// + // Components definition + ///////////////////////////////////////////////////////////////////////////// + + for (size_t p = 0; p < nb_procs; p++) + { + std::ostringstream sproc; + sproc << "proc_" << x_id << "_" << y_id << "_" << p; + proc[p] = new VciCcVCacheWrapper >( + sproc.str().c_str(), + cluster_id * nb_procs + p, // GLOBAL PROC_ID + mtd, // Mapping Table + IntTab(cluster_id,p), // SRCID + (cluster_id << l_width) + p, // CC_GLOBAL_ID + 8, // ITLB ways + 8, // ITLB sets + 8, // DTLB ways + 8, // DTLB sets + l1_i_ways,l1_i_sets, 16, // ICACHE size + l1_d_ways,l1_d_sets, 16, // DCACHE size + 4, // WBUF nlines + 4, // WBUF nwords + x_width, + y_width, + frozen_cycles, // max frozen cycles + debug_start_cycle, + proc_debug_ok); + + std::ostringstream swip; + swip << "wi_proc_" << x_id << "_" << y_id << "_" << p; + wi_proc[p] = new VciDspinInitiatorWrapper( + swip.str().c_str(), + x_width + y_width + l_width); + } + + ///////////////////////////////////////////////////////////////////////////// + std::ostringstream smemc; + smemc << "memc_" << x_id << "_" << y_id; + memc = new VciMemCache( + smemc.str().c_str(), + mtd, // Mapping Table direct space + mtx, // Mapping Table external space + IntTab(cluster_id), // SRCID external space + IntTab(cluster_id, tgtid_memc), // TGTID direct space + //(cluster_id << l_width) + nb_procs, // CC_GLOBAL_ID + x_width, // Number of x bits in platform + y_width, // Number of y bits in platform + memc_ways, memc_sets, 16, // CACHE SIZE + 3, // MAX NUMBER OF COPIES + 4096, // HEAP SIZE + 8, // TRANSACTION TABLE DEPTH + 8, // UPDATE TABLE DEPTH + 8, // INVALIDATE TABLE DEPTH + debug_start_cycle, + memc_debug_ok); + + wt_memc = new VciDspinTargetWrapper( + "wt_memc", + x_width + y_width + l_width); + + ///////////////////////////////////////////////////////////////////////////// + std::ostringstream sxram; + sxram << "xram_" << x_id << "_" << y_id; + xram = new VciSimpleRam( + sxram.str().c_str(), + IntTab(cluster_id), + mtx, + loader, + xram_latency); + + ///////////////////////////////////////////////////////////////////////////// + std::ostringstream sxicu; + sxicu << "xicu_" << x_id << "_" << y_id; + xicu = new VciXicu( + sxicu.str().c_str(), + mtd, // mapping table + IntTab(cluster_id, tgtid_xicu), // TGTID_D + nb_procs, // number of timer IRQs + 32, // number of hard IRQs + 32, // number of soft IRQs + nb_procs); // number of output IRQs + + wt_xicu = new VciDspinTargetWrapper( + "wt_xicu", + x_width + y_width + l_width); + + ///////////////////////////////////////////////////////////////////////////// + std::ostringstream smdma; + smdma << "mdma_" << x_id << "_" << y_id; + mdma = new VciMultiDma( + smdma.str().c_str(), + mtd, + IntTab(cluster_id, nb_procs), // SRCID + IntTab(cluster_id, tgtid_mdma), // TGTID + 64, // burst size + nb_dmas); // number of IRQs + + wt_mdma = new VciDspinTargetWrapper( + "wt_mdma", + x_width + y_width + l_width); + + wi_mdma = new VciDspinInitiatorWrapper( + "wi_mdma", + x_width + y_width + l_width); + + ///////////////////////////////////////////////////////////////////////////// + size_t nb_direct_initiators = nb_procs + 1; + size_t nb_direct_targets = 3; + if (io) + { + nb_direct_initiators = nb_procs + 3; + nb_direct_targets = 10; + } + + xbar_cmd_d = new DspinLocalCrossbar( + "xbar_cmd_d", + mtd, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, l_width, + nb_direct_initiators, // number of local of sources + nb_direct_targets, // number of local dests + 2, 2, // fifo depths + true, // CMD + true, // use local routing table + false ); // no broadcast + + ///////////////////////////////////////////////////////////////////////////// + xbar_rsp_d = new DspinLocalCrossbar( + "xbar_rsp_d", + mtd, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, l_width, + nb_direct_targets, // number of local sources + nb_direct_initiators, // number of local dests + 2, 2, // fifo depths + false, // RSP + false, // don't use local routing table + false ); // no broadcast + + ///////////////////////////////////////////////////////////////////////////// + xbar_m2p_c = new DspinLocalCrossbar( + "xbar_m2p_c", + mtd, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, l_width, + 1, // number of local sources + nb_procs, // number of local targets + 2, 2, // fifo depths + true, // CMD + false, // don't use local routing table + true ); // broadcast + + ///////////////////////////////////////////////////////////////////////////// + xbar_p2m_c = new DspinLocalCrossbar( + "xbar_p2m_c", + mtd, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, 0, // l_width unused on p2m network + nb_procs, // number of local sources + 1, // number of local dests + 2, 2, // fifo depths + false, // RSP + false, // don't use local routing table + false ); // no broadcast + + ///////////////////////////////////////////////////////////////////////////// + xbar_clack_c = new DspinLocalCrossbar( + "xbar_clack_c", + mtd, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, l_width, + 1, // number of local sources + nb_procs, // number of local targets + 1, 1, // fifo depths + true, // CMD + false, // don't use local routing table + false); // broadcast + + ///////////////////////////////////////////////////////////////////////////// + router_cmd = new VirtualDspinRouter( + "router_cmd", + x_id,y_id, // coordinate in the mesh + x_width, y_width, // x & y fields width + 3, // nb virtual channels + 4,4); // input & output fifo depths + + ///////////////////////////////////////////////////////////////////////////// + router_rsp = new VirtualDspinRouter( + "router_rsp", + x_id,y_id, // coordinates in mesh + x_width, y_width, // x & y fields width + 2, // nb virtual channels + 4,4); // input & output fifo depths + + // IO cluster components + if (io) + { + ///////////////////////////////////////////// + brom = new VciSimpleRom( + "brom", + IntTab(cluster_id, tgtid_brom), + mtd, + loader); + + wt_brom = new VciDspinTargetWrapper( + "wt_brom", + x_width + y_width + l_width); + + ///////////////////////////////////////////// + fbuf = new VciFrameBuffer( + "fbuf", + IntTab(cluster_id, tgtid_fbuf), + mtd, + xfb, yfb); + + wt_fbuf = new VciDspinTargetWrapper( + "wt_fbuf", + x_width + y_width + l_width); + + ///////////////////////////////////////////// + bdev = new VciBlockDeviceTsar( + "bdev", + mtd, + IntTab(cluster_id, nb_procs + 1), + IntTab(cluster_id, tgtid_bdev), + disk_name, + block_size, + 64); // burst size + + wt_bdev = new VciDspinTargetWrapper( + "wt_bdev", + x_width + y_width + l_width); + + wi_bdev = new VciDspinInitiatorWrapper( + "wi_bdev", + x_width + y_width + l_width); + + int mac = 0xBEEF0000; + mnic = new VciMultiNic( + "mnic", + IntTab(cluster_id, tgtid_mnic), + mtd, + nic_channels, + nic_rx_name, + nic_tx_name, + mac, // mac_4 address + 0xBABE ); // mac_2 address + + wt_mnic = new VciDspinTargetWrapper( + "wt_mnic", + x_width + y_width + l_width); + + ///////////////////////////////////////////// + chbuf = new VciChbufDma( + "chbuf_dma", + mtd, + IntTab(cluster_id, nb_procs + 2), + IntTab(cluster_id, tgtid_chbuf), + 64, + chbufdma_channels); + + wt_chbuf = new VciDspinTargetWrapper( + "wt_chbuf", + x_width + y_width + l_width); + + wi_chbuf = new VciDspinInitiatorWrapper( + "wi_chbuf", + x_width + y_width + l_width); + + ///////////////////////////////////////////// + std::vector vect_names; + for (size_t tid = 0; tid < nb_ttys; tid++) + { + std::ostringstream term_name; + term_name << "tty" << tid; + vect_names.push_back(term_name.str().c_str()); + } + mtty = new VciMultiTty( + "mtty", + IntTab(cluster_id, tgtid_mtty), + mtd, + vect_names); + + wt_mtty = new VciDspinTargetWrapper( + "wt_mtty", + x_width + y_width + l_width); + + simhelper = new VciSimhelper( + "sim_helper", + IntTab(cluster_id, tgtid_simh), + mtd); + + wt_simhelper = new VciDspinTargetWrapper( + "wt_simhelper", + x_width + y_width + l_width); + } + + //////////////////////////////////// + // Connections are defined here + //////////////////////////////////// + + //////////////////////// CMD ROUTER and RSP ROUTER + router_cmd->p_clk (this->p_clk); + router_cmd->p_resetn (this->p_resetn); + router_rsp->p_clk (this->p_clk); + router_rsp->p_resetn (this->p_resetn); + + for (int i = 0; i < 4; i++) + { + for (int k = 0; k < 3; k++) + { + router_cmd->p_out[i][k] (this->p_cmd_out[i][k]); + router_cmd->p_in[i][k] (this->p_cmd_in[i][k]); + } + + for (int k = 0; k < 2; k++) + { + router_rsp->p_out[i][k] (this->p_rsp_out[i][k]); + router_rsp->p_in[i][k] (this->p_rsp_in[i][k]); + } + } + + router_cmd->p_out[4][0] (signal_dspin_cmd_g2l_d); + router_cmd->p_out[4][1] (signal_dspin_m2p_g2l_c); + router_cmd->p_out[4][2] (signal_dspin_clack_g2l_c); + router_cmd->p_in[4][0] (signal_dspin_cmd_l2g_d); + router_cmd->p_in[4][1] (signal_dspin_m2p_l2g_c); + router_cmd->p_in[4][2] (signal_dspin_clack_l2g_c); + + router_rsp->p_out[4][0] (signal_dspin_rsp_g2l_d); + router_rsp->p_out[4][1] (signal_dspin_p2m_g2l_c); + router_rsp->p_in[4][0] (signal_dspin_rsp_l2g_d); + router_rsp->p_in[4][1] (signal_dspin_p2m_l2g_c); + + + std::cout << " - CMD & RSP routers connected" << std::endl; + + ///////////////////// CMD DSPIN local crossbar direct + xbar_cmd_d->p_clk (this->p_clk); + xbar_cmd_d->p_resetn (this->p_resetn); + xbar_cmd_d->p_global_out (signal_dspin_cmd_l2g_d); + xbar_cmd_d->p_global_in (signal_dspin_cmd_g2l_d); + + xbar_cmd_d->p_local_out[tgtid_memc] (signal_dspin_cmd_memc_t); + xbar_cmd_d->p_local_out[tgtid_xicu] (signal_dspin_cmd_xicu_t); + xbar_cmd_d->p_local_out[tgtid_mdma] (signal_dspin_cmd_mdma_t); + + xbar_cmd_d->p_local_in[nb_procs] (signal_dspin_cmd_mdma_i); + + for (size_t p = 0; p < nb_procs; p++) + xbar_cmd_d->p_local_in[p] (signal_dspin_cmd_proc_i[p]); + + if (io) + { + xbar_cmd_d->p_local_out[tgtid_mtty] (signal_dspin_cmd_mtty_t); + xbar_cmd_d->p_local_out[tgtid_brom] (signal_dspin_cmd_brom_t); + xbar_cmd_d->p_local_out[tgtid_bdev] (signal_dspin_cmd_bdev_t); + xbar_cmd_d->p_local_out[tgtid_fbuf] (signal_dspin_cmd_fbuf_t); + xbar_cmd_d->p_local_out[tgtid_mnic] (signal_dspin_cmd_mnic_t); + xbar_cmd_d->p_local_out[tgtid_chbuf] (signal_dspin_cmd_chbuf_t); + xbar_cmd_d->p_local_out[tgtid_simh] (signal_dspin_cmd_simh_t); + + xbar_cmd_d->p_local_in[nb_procs + 1] (signal_dspin_cmd_bdev_i); + xbar_cmd_d->p_local_in[nb_procs + 2] (signal_dspin_cmd_chbuf_i); + } + + std::cout << " - Command Direct crossbar connected" << std::endl; + + //////////////////////// RSP DSPIN local crossbar direct + xbar_rsp_d->p_clk (this->p_clk); + xbar_rsp_d->p_resetn (this->p_resetn); + xbar_rsp_d->p_global_out (signal_dspin_rsp_l2g_d); + xbar_rsp_d->p_global_in (signal_dspin_rsp_g2l_d); + + xbar_rsp_d->p_local_in[tgtid_memc] (signal_dspin_rsp_memc_t); + xbar_rsp_d->p_local_in[tgtid_xicu] (signal_dspin_rsp_xicu_t); + xbar_rsp_d->p_local_in[tgtid_mdma] (signal_dspin_rsp_mdma_t); + + xbar_rsp_d->p_local_out[nb_procs] (signal_dspin_rsp_mdma_i); + + for (size_t p = 0; p < nb_procs; p++) + xbar_rsp_d->p_local_out[p] (signal_dspin_rsp_proc_i[p]); + + if (io) + { + xbar_rsp_d->p_local_in[tgtid_mtty] (signal_dspin_rsp_mtty_t); + xbar_rsp_d->p_local_in[tgtid_brom] (signal_dspin_rsp_brom_t); + xbar_rsp_d->p_local_in[tgtid_bdev] (signal_dspin_rsp_bdev_t); + xbar_rsp_d->p_local_in[tgtid_fbuf] (signal_dspin_rsp_fbuf_t); + xbar_rsp_d->p_local_in[tgtid_mnic] (signal_dspin_rsp_mnic_t); + xbar_rsp_d->p_local_in[tgtid_chbuf] (signal_dspin_rsp_chbuf_t); + xbar_rsp_d->p_local_in[tgtid_simh] (signal_dspin_rsp_simh_t); + + xbar_rsp_d->p_local_out[nb_procs + 1] (signal_dspin_rsp_bdev_i); + xbar_rsp_d->p_local_out[nb_procs + 2] (signal_dspin_rsp_chbuf_i); + } + + std::cout << " - Response Direct crossbar connected" << std::endl; + + ////////////////////// M2P DSPIN local crossbar coherence + xbar_m2p_c->p_clk (this->p_clk); + xbar_m2p_c->p_resetn (this->p_resetn); + xbar_m2p_c->p_global_out (signal_dspin_m2p_l2g_c); + xbar_m2p_c->p_global_in (signal_dspin_m2p_g2l_c); + xbar_m2p_c->p_local_in[0] (signal_dspin_m2p_memc); + for (size_t p = 0; p < nb_procs; p++) + xbar_m2p_c->p_local_out[p] (signal_dspin_m2p_proc[p]); + + std::cout << " - M2P Coherence crossbar connected" << std::endl; + + ////////////////////// CLACK DSPIN local crossbar coherence + xbar_clack_c->p_clk (this->p_clk); + xbar_clack_c->p_resetn (this->p_resetn); + xbar_clack_c->p_global_out (signal_dspin_clack_l2g_c); + xbar_clack_c->p_global_in (signal_dspin_clack_g2l_c); + xbar_clack_c->p_local_in[0] (signal_dspin_clack_memc); + for (size_t p = 0; p < nb_procs; p++) + xbar_clack_c->p_local_out[p] (signal_dspin_clack_proc[p]); + + std::cout << " - Clack Coherence crossbar connected" << std::endl; + + ////////////////////////// P2M DSPIN local crossbar coherence + xbar_p2m_c->p_clk (this->p_clk); + xbar_p2m_c->p_resetn (this->p_resetn); + xbar_p2m_c->p_global_out (signal_dspin_p2m_l2g_c); + xbar_p2m_c->p_global_in (signal_dspin_p2m_g2l_c); + xbar_p2m_c->p_local_out[0] (signal_dspin_p2m_memc); + for (size_t p = 0; p < nb_procs; p++) + xbar_p2m_c->p_local_in[p] (signal_dspin_p2m_proc[p]); + + std::cout << " - P2M Coherence crossbar connected" << std::endl; + + + //////////////////////////////////// Processors + for (size_t p = 0; p < nb_procs; p++) + { + proc[p]->p_clk (this->p_clk); + proc[p]->p_resetn (this->p_resetn); + proc[p]->p_vci (signal_vci_ini_proc[p]); + proc[p]->p_dspin_m2p (signal_dspin_m2p_proc[p]); + proc[p]->p_dspin_p2m (signal_dspin_p2m_proc[p]); + proc[p]->p_dspin_clack (signal_dspin_clack_proc[p]); + proc[p]->p_irq[0] (signal_proc_it[p]); + for ( size_t j = 1 ; j < 6 ; j++) + { + proc[p]->p_irq[j] (signal_false); + } + + wi_proc[p]->p_clk (this->p_clk); + wi_proc[p]->p_resetn (this->p_resetn); + wi_proc[p]->p_dspin_cmd (signal_dspin_cmd_proc_i[p]); + wi_proc[p]->p_dspin_rsp (signal_dspin_rsp_proc_i[p]); + wi_proc[p]->p_vci (signal_vci_ini_proc[p]); + } + + std::cout << " - Processors connected" << std::endl; + + ///////////////////////////////////// XICU + xicu->p_clk (this->p_clk); + xicu->p_resetn (this->p_resetn); + xicu->p_vci (signal_vci_tgt_xicu); + for (size_t p = 0; p < nb_procs; p++) + { + xicu->p_irq[p] (signal_proc_it[p]); + } + +#if 1 + if(io) + { + xicu->p_hwi[0] (signal_irq_bdev); + xicu->p_hwi[1] (signal_irq_mdma[0]); + + for(size_t i=0; i<4; i++) + xicu->p_hwi[2+i] (signal_irq_mtty[i]); + + xicu->p_hwi[6] (signal_irq_memc); + } + else + { + xicu->p_hwi[1] (signal_irq_mdma[0]); + xicu->p_hwi[2] (signal_irq_memc); + } + + for(size_t i=0; i < 32; i++) + { + if((io && (i > 6)) || (!io && ((i == 0) || (i > 2)))) + xicu->p_hwi[i] (signal_false); + } +#else + for (size_t i = 0; i < 32; i++) + { + if (io) // I/O cluster + { + if (i < 8) xicu->p_hwi[i] (signal_false); + else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i - 8]); + else if (i < 16) xicu->p_hwi[i] (signal_false); + else if (i < (16 + nb_ttys)) xicu->p_hwi[i] (signal_irq_mtty[i - 16]); + else if (i < 31) xicu->p_hwi[i] (signal_false); + else xicu->p_hwi[i] (signal_irq_bdev); + } + else // other clusters + { + if (i < 8) xicu->p_hwi[i] (signal_false); + else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i - 8]); + else xicu->p_hwi[i] (signal_false); + } + } +#endif + + // wrapper XICU + wt_xicu->p_clk (this->p_clk); + wt_xicu->p_resetn (this->p_resetn); + wt_xicu->p_dspin_cmd (signal_dspin_cmd_xicu_t); + wt_xicu->p_dspin_rsp (signal_dspin_rsp_xicu_t); + wt_xicu->p_vci (signal_vci_tgt_xicu); + + std::cout << " - XICU connected" << std::endl; + + //////////////////////////////////////////////// MEMC + memc->p_clk (this->p_clk); + memc->p_resetn (this->p_resetn); + memc->p_vci_ixr (signal_vci_xram); + memc->p_vci_tgt (signal_vci_tgt_memc); + memc->p_dspin_p2m (signal_dspin_p2m_memc); + memc->p_dspin_m2p (signal_dspin_m2p_memc); + memc->p_dspin_clack (signal_dspin_clack_memc); + memc->p_irq (signal_irq_memc); + + // wrapper MEMC + wt_memc->p_clk (this->p_clk); + wt_memc->p_resetn (this->p_resetn); + wt_memc->p_dspin_cmd (signal_dspin_cmd_memc_t); + wt_memc->p_dspin_rsp (signal_dspin_rsp_memc_t); + wt_memc->p_vci (signal_vci_tgt_memc); + + std::cout << " - MEMC connected" << std::endl; + + /////////////////////////////////////////////// XRAM + xram->p_clk (this->p_clk); + xram->p_resetn (this->p_resetn); + xram->p_vci (signal_vci_xram); + + std::cout << " - XRAM connected" << std::endl; + + ////////////////////////////////////////////// MDMA + mdma->p_clk (this->p_clk); + mdma->p_resetn (this->p_resetn); + mdma->p_vci_target (signal_vci_tgt_mdma); + mdma->p_vci_initiator (signal_vci_ini_mdma); + for (size_t i = 0; i < nb_dmas; i++) + mdma->p_irq[i] (signal_irq_mdma[i]); + + // wrapper tgt MDMA + wt_mdma->p_clk (this->p_clk); + wt_mdma->p_resetn (this->p_resetn); + wt_mdma->p_dspin_cmd (signal_dspin_cmd_mdma_t); + wt_mdma->p_dspin_rsp (signal_dspin_rsp_mdma_t); + wt_mdma->p_vci (signal_vci_tgt_mdma); + + // wrapper ini MDMA + wi_mdma->p_clk (this->p_clk); + wi_mdma->p_resetn (this->p_resetn); + wi_mdma->p_dspin_cmd (signal_dspin_cmd_mdma_i); + wi_mdma->p_dspin_rsp (signal_dspin_rsp_mdma_i); + wi_mdma->p_vci (signal_vci_ini_mdma); + + std::cout << " - MDMA connected" << std::endl; + + /////////////////////////////// Components in I/O cluster + + if (io) + { + // BDEV + bdev->p_clk (this->p_clk); + bdev->p_resetn (this->p_resetn); + bdev->p_irq (signal_irq_bdev); + bdev->p_vci_target (signal_vci_tgt_bdev); + bdev->p_vci_initiator (signal_vci_ini_bdev); + + // wrapper tgt BDEV + wt_bdev->p_clk (this->p_clk); + wt_bdev->p_resetn (this->p_resetn); + wt_bdev->p_dspin_cmd (signal_dspin_cmd_bdev_t); + wt_bdev->p_dspin_rsp (signal_dspin_rsp_bdev_t); + wt_bdev->p_vci (signal_vci_tgt_bdev); + + // wrapper ini BDEV + wi_bdev->p_clk (this->p_clk); + wi_bdev->p_resetn (this->p_resetn); + wi_bdev->p_dspin_cmd (signal_dspin_cmd_bdev_i); + wi_bdev->p_dspin_rsp (signal_dspin_rsp_bdev_i); + wi_bdev->p_vci (signal_vci_ini_bdev); + + std::cout << " - BDEV connected" << std::endl; + + // FBUF + fbuf->p_clk (this->p_clk); + fbuf->p_resetn (this->p_resetn); + fbuf->p_vci (signal_vci_tgt_fbuf); + + // wrapper tgt FBUF + wt_fbuf->p_clk (this->p_clk); + wt_fbuf->p_resetn (this->p_resetn); + wt_fbuf->p_dspin_cmd (signal_dspin_cmd_fbuf_t); + wt_fbuf->p_dspin_rsp (signal_dspin_rsp_fbuf_t); + wt_fbuf->p_vci (signal_vci_tgt_fbuf); + + std::cout << " - FBUF connected" << std::endl; + + // MNIC + mnic->p_clk (this->p_clk); + mnic->p_resetn (this->p_resetn); + mnic->p_vci (signal_vci_tgt_mnic); + for (size_t i = 0; i < nic_channels; i++) + { + mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]); + mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]); + } + + // wrapper tgt MNIC + wt_mnic->p_clk (this->p_clk); + wt_mnic->p_resetn (this->p_resetn); + wt_mnic->p_dspin_cmd (signal_dspin_cmd_mnic_t); + wt_mnic->p_dspin_rsp (signal_dspin_rsp_mnic_t); + wt_mnic->p_vci (signal_vci_tgt_mnic); + + std::cout << " - MNIC connected" << std::endl; + + // CHBUF + chbuf->p_clk (this->p_clk); + chbuf->p_resetn (this->p_resetn); + chbuf->p_vci_target (signal_vci_tgt_chbuf); + chbuf->p_vci_initiator (signal_vci_ini_chbuf); + for (size_t i = 0; i < chbufdma_channels; i++) + { + chbuf->p_irq[i] (signal_irq_chbuf[i]); + } + + // wrapper tgt CHBUF + wt_chbuf->p_clk (this->p_clk); + wt_chbuf->p_resetn (this->p_resetn); + wt_chbuf->p_dspin_cmd (signal_dspin_cmd_chbuf_t); + wt_chbuf->p_dspin_rsp (signal_dspin_rsp_chbuf_t); + wt_chbuf->p_vci (signal_vci_tgt_chbuf); + + // wrapper ini CHBUF + wi_chbuf->p_clk (this->p_clk); + wi_chbuf->p_resetn (this->p_resetn); + wi_chbuf->p_dspin_cmd (signal_dspin_cmd_chbuf_i); + wi_chbuf->p_dspin_rsp (signal_dspin_rsp_chbuf_i); + wi_chbuf->p_vci (signal_vci_ini_chbuf); + + std::cout << " - CHBUF connected" << std::endl; + + // BROM + brom->p_clk (this->p_clk); + brom->p_resetn (this->p_resetn); + brom->p_vci (signal_vci_tgt_brom); + + // wrapper tgt BROM + wt_brom->p_clk (this->p_clk); + wt_brom->p_resetn (this->p_resetn); + wt_brom->p_dspin_cmd (signal_dspin_cmd_brom_t); + wt_brom->p_dspin_rsp (signal_dspin_rsp_brom_t); + wt_brom->p_vci (signal_vci_tgt_brom); + + std::cout << " - BROM connected" << std::endl; + + // MTTY + mtty->p_clk (this->p_clk); + mtty->p_resetn (this->p_resetn); + mtty->p_vci (signal_vci_tgt_mtty); + for (size_t i = 0; i < nb_ttys; i++) + { + mtty->p_irq[i] (signal_irq_mtty[i]); + } + + // wrapper tgt MTTY + wt_mtty->p_clk (this->p_clk); + wt_mtty->p_resetn (this->p_resetn); + wt_mtty->p_dspin_cmd (signal_dspin_cmd_mtty_t); + wt_mtty->p_dspin_rsp (signal_dspin_rsp_mtty_t); + wt_mtty->p_vci (signal_vci_tgt_mtty); + + + // Sim Helper + simhelper->p_clk (this->p_clk); + simhelper->p_resetn (this->p_resetn); + simhelper->p_vci (signal_vci_tgt_simh); + + // wrapper tgt Sim Helper + wt_simhelper->p_clk (this->p_clk); + wt_simhelper->p_resetn (this->p_resetn); + wt_simhelper->p_dspin_cmd (signal_dspin_cmd_simh_t); + wt_simhelper->p_dspin_rsp (signal_dspin_rsp_simh_t); + wt_simhelper->p_vci (signal_vci_tgt_simh); + + std::cout << " - MTTY connected" << std::endl; + } +} // end constructor + + + +template TsarXbarCluster::~TsarXbarCluster() { + + dealloc_elems > (p_cmd_in, 4, 3); + dealloc_elems >(p_cmd_out, 4, 3); + dealloc_elems > (p_rsp_in, 4, 2); + dealloc_elems >(p_rsp_out, 4, 2); + + for (size_t p = 0; p < n_procs; p++) + { + delete proc[p]; + delete wi_proc[p]; + } + + delete memc; + delete wt_memc; + delete xram; + delete xicu; + delete wt_xicu; + delete mdma; + delete wt_mdma; + delete wi_mdma; + delete xbar_cmd_d; + delete xbar_rsp_d; + delete xbar_m2p_c; + delete xbar_p2m_c; + delete xbar_clack_c; + delete router_cmd; + delete router_rsp; + if (brom != NULL) + { + delete brom; + delete wt_brom; + delete fbuf; + delete wt_fbuf; + delete bdev; + delete wt_bdev; + delete wi_bdev; + delete mnic; + delete wt_mnic; + delete chbuf; + delete wt_chbuf; + delete wi_chbuf; + delete mtty; + delete wt_mtty; + delete simhelper; + delete wt_simhelper; + } +} + + +}} + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + + + Index: /branches/fault_tolerance/platforms/linux_monocluster/.gdbinit =================================================================== --- /branches/fault_tolerance/platforms/linux_monocluster/.gdbinit (revision 724) +++ /branches/fault_tolerance/platforms/linux_monocluster/.gdbinit (revision 724) @@ -0,0 +1,136 @@ +define connect + target remote localhost:2346 +end + +# useful macros for Linux +define dmesg + set $__log_buf = $arg0 + set $log_start = $arg1 + set $log_end = $arg2 + set $x = $log_start + echo " + while ($x < $log_end) + set $c = (char)(($__log_buf)[$x++]) + printf "%c" , $c + end + echo "\n +end +document dmesg +dmesg __log_buf log_start log_end +Print the content of the kernel message buffer +end + +define thread_info + set $th = (struct thread_info*)$gp + echo "thread_info=" + print /x *$th +end +define task_struct + set $th = (struct thread_info*)$gp + set $ts = (struct task_struct*)$th->task + echo "task_struct=" + print /x *$ts +end +define active_mm + set $th = (struct thread_info*)$gp + set $ts = (struct task_struct*)$th->task + set $amm = (struct mm_struct*)$ts->active_mm + echo "active_mm=" + print /x *$amm +end +define pgd + set $th = (struct thread_info*)$gp + set $ts = (struct task_struct*)$th->task + set $ms = (struct mm_struct*)$ts->active_mm + set $pg = (pgd_t*)$ms->pgd + echo "pgd=" + print /x {pgd_t[2048]}$pg +end + +define task_struct_header + printf "Address PID State [User_EPC] [User-SP] Kernel-SP device comm\n" +end + +define task_struct_show + # task_struct addr and PID + printf "0x%08X %5d", $arg0, $arg0->pid + # Place a '<' marker on the current task + # if ($arg0 == current) + # For PowerPC, register r2 points to the "current" task + if ($arg0 == $r2) + printf "<" + else + printf " " + end + # State + if ($arg0->state == 0) + printf "Running " + else + if ($arg0->state == 1) + printf "Sleeping " + else + if ($arg0->state == 2) + printf "Disksleep " + else + if ($arg0->state == 4) + printf "Zombie " + else + if ($arg0->state == 8) + printf "sTopped " + else + if ($arg0->state == 16) + printf "Wpaging " + else + printf "%2d ", $arg0->state + end + end + end + end + end + end + # User PC + set $pt_regs = (struct pt_regs*)($arg0->stack + 0x2000 - sizeof(struct pt_regs)) + if ($pt_regs->cp0_epc) + printf "0x%08X ", $pt_regs->cp0_epc + else + printf " " + end + if ($pt_regs->regs[29]) + printf "0x%08X ", $pt_regs->regs[29] + else + printf " " + end + # Display the kernel stack pointer + set $th = (struct thread_info*)$arg0->stack + printf "0x%08X ", $th->ksp + # device + if ($arg0->signal->tty) + printf "%s ", $arg0->signal->tty->name + else + printf "(none) " + end + # comm + printf "%s\n", $arg0->comm +end + +define find_next_task + # Given a task address, find the next task in the linked list + set $t = (struct task_struct *)$arg0 + set $offset=((char *)&$t->tasks - (char *)$t) + set $t=(struct task_struct *)((char *)$t->tasks.next- (char *)$offset) +end + +define ps + # Print column headers + task_struct_header + set $t=&init_task + task_struct_show $t + find_next_task $t + # Walk the list + while &init_task!=$t + # Display useful info about each task + task_struct_show $t + find_next_task $t + end +end + Index: /branches/fault_tolerance/platforms/linux_monocluster/Makefile =================================================================== --- /branches/fault_tolerance/platforms/linux_monocluster/Makefile (revision 724) +++ /branches/fault_tolerance/platforms/linux_monocluster/Makefile (revision 724) @@ -0,0 +1,84 @@ +# where is soclib? +# +SOCLIB_DIR=$(shell soclib-cc --getpath) + +# name definitions +# +SOCLIB_DESC=desc.py +SOCLIB_TOP=top.cpp +SIMULATOR_BINARY=system.x +SIMULATOR_CMD=./$(SIMULATOR_BINARY) --nobanner + +# extra arguments for compilation +# +#SOCLIB_CC_ARGS=-v +SOCLIB_CC_ARGS+=-b common:mips32 + +# extra arguments for execution +# +# gdb +# - F: start the simulation in a frozen state so it can be attached with a gdb +# client +# - X: disable automatic break whenever an exception is caught, the exception +# handler will be called transparently +# - S: make the simulation stop and wait for a gdb attachment whenever an +# exception is caught +# - C: dump a trace of every inter-functions branch +# - T: exit the simulator on trap exception +# - Z: same as C but display only function's entrypoint +# - W: disable automatic break whenever a watchpoint is hit, just report it on +# stderr (watchpoints can be defined using SOCLIB_GDB_WATCH) +SIMULATOR_GDB= +ifeq ("$(origin GDB)", "command line") + ifeq ($(GDB), 1) + SIMULATOR_GDB=SOCLIB_GDB=FCX + else + SIMULATOR_GDB=SOCLIB_GDB=$(GDB) + endif +endif +# ncpus +SIMULATOR_NCPUS=4 +ifeq ("$(origin NCPUS)", "command line") + SIMULATOR_NCPUS=$(NCPUS) +endif +# vmlinux +SIMULATOR_VMLINUX=./vmlinux +ifeq ("$(origin VMLINUX)", "command line") + SIMULATOR_VMLINUX=$(VMLINUX) +endif +# dsk +SIMULATOR_DSK= +ifeq ("$(origin DSK)", "command line") + SIMULATOR_DSK=--dsk $(DSK) +endif +# trace +SIMULATOR_TRACE= +ifeq ("$(origin TRACE)", "command line") + SIMULATOR_TRACE=--trace $(TRACE) +endif +# ncycles +SIMULATOR_NCYCLES= +ifeq ("$(origin NCYCLES)", "command line") + SIMULATOR_NCYCLES=--ncycles $(NCYCLES) +endif + +# recipes +all: $(SIMULATOR_BINARY) + +$(SIMULATOR_BINARY): $(SOCLIB_DESC) $(SOCLIB_TOP) + soclib-cc $(SOCLIB_CC_ARGS) -P -p $(SOCLIB_DESC) -o $(SIMULATOR_BINARY) + +run_tsar_boot: all tsar_boot.bin + $(SIMULATOR_GDB) $(SIMULATOR_CMD) --ncpus $(SIMULATOR_NCPUS) --rom tsar_boot.bin $(SIMULATOR_DSK) $(SIMULATOR_TRACE) $(SIMULATOR_NCYCLES) + +run_dummy_boot: all + $(SIMULATOR_GDB) $(SIMULATOR_CMD) --ncpus $(SIMULATOR_NCPUS) --rom $(SIMULATOR_VMLINUX) $(SIMULATOR_DSK) --dummy-boot $(SIMULATOR_TRACE) $(SIMULATOR_NCYCLES) + +cscope.out: + soclib-cc -p $(SOCLIB_DESC) --tags + +clean: + soclib-cc -P -p $(SOCLIB_DESC) -x -o $(SIMULATOR_BINARY) + rm -f $(SIMULATOR_BINARY) *.o vci* + +.PHONY: $(SIMULATOR_BINARY) Index: /branches/fault_tolerance/platforms/linux_monocluster/README =================================================================== --- /branches/fault_tolerance/platforms/linux_monocluster/README (revision 724) +++ /branches/fault_tolerance/platforms/linux_monocluster/README (revision 724) @@ -0,0 +1,61 @@ +April 2014, Joel Porquet + +This platform is known for being able to run Linux. + +---- +Pre-requisites: + +* A working version of SoCLib (r2558) + - the command `soclib-cc --getpath` should return where SoCLib is installed +* A working version of TSAR (r668) + - TSAR directory should be properly added to SoCLib's configuration: either + globally, or through the `soclib.conf` file present in this directory (in + which case, the environment variable `TSARDIR` should be defined to point + on TSAR directory) + + +---- +Targets of the Makefile: + +* clean: clean the compilation files +* all (or none): compile the simulation system +* run_tsar_boot: runs the simulation system using a boot loader (in this case, + you want to use a blockdevice image that contains the kernel: see `DSK` + option below) +* run_dummy_boot: runs the simulation system using directly Linux instead of a + boot loader (i.e. Linux is already loaded in RAM before execution). + + +---- +Options for running: + +These options apply when using either `run_tsar_boot` or `run_dummy_boot` +targets. Example: `make run_dummy_boot GDB=1 VMLINUX=../vmlinux DSK=dsk.img` + +* GDB=1|[FXSCTZW]: options to the GDB server (1 means FCX which is a good + default) +* NCPUS=[1-4]: number of processors (the default is 4) +* DSK=[pathname]: path to a filesystem to use with the BlockDevice component + (also implies creating a system with such a component, other the component is + deactivated) +* TRACE=[number]: enables tracing the simulation starting from a certain cycle +* NCYCLES=[number]: runs the simulation for a certain number of cycles + + Only for run_dummy_boot: + * VMLINUX=[pathname]: path to Linux `vmlinux` image + + +---- +Using GDB server: + +A file named `.gdbinit` contains a few macros that can be useful for debugging +Linux when using the GDB server. + +* connect: connect to the GDB server that runs within the simulation +* dmesg: print the content of the kernel message buffer +* thread_info: print the thread_info structure of the current task +* task_struct: print the task_struct structure of the current task +* active_mm: print the active_mm structure of the current task +* pgd: print the content of the page table of the current task +* ps: print the list of running tasks + Index: /branches/fault_tolerance/platforms/linux_monocluster/desc.py =================================================================== --- /branches/fault_tolerance/platforms/linux_monocluster/desc.py (revision 724) +++ /branches/fault_tolerance/platforms/linux_monocluster/desc.py (revision 724) @@ -0,0 +1,47 @@ +dspin_cmd_flit_size = 39 +dspin_rsp_flit_size = 32 +cell_size = 4 + +todo = Platform('caba', 'top.cpp', + uses = [ + Uses('caba:vci_cc_vcache_wrapper', + dspin_in_width = dspin_cmd_flit_size, + dspin_out_width = dspin_rsp_flit_size, + iss_t = 'common:mips32el'), + Uses('caba:vci_cc_vcache_wrapper', + dspin_in_width = dspin_cmd_flit_size, + dspin_out_width = dspin_rsp_flit_size, + iss_t = 'common:gdb_iss', + gdb_iss_t = 'common:mips32el'), + Uses('caba:vci_simple_ram'), + Uses('caba:vci_simple_ram', cell_size = 8), + Uses('caba:vci_xicu'), + Uses('caba:vci_multi_tty'), + Uses('caba:vci_block_device_tsar'), + Uses('caba:vci_framebuffer'), + Uses('caba:vci_mem_cache', + memc_cell_size_int = cell_size, + memc_cell_size_ext = 8, + dspin_out_width = dspin_cmd_flit_size, + dspin_in_width = dspin_rsp_flit_size, + ), + Uses('caba:dspin_local_crossbar', + flit_width = dspin_cmd_flit_size), + Uses('caba:dspin_local_crossbar', + flit_width = dspin_rsp_flit_size), + Uses('caba:vci_local_crossbar', + cell_size = cell_size), + Uses('common:elf_file_loader'), + ], + cell_size = cell_size, + plen_size = 8, + addr_size = 32, + rerror_size = 1, + clen_size = 1, + rflag_size = 1, + srcid_size = 14, + pktid_size = 4, + trdid_size = 4, + wrplen_size = 1 + ) + Index: /branches/fault_tolerance/platforms/linux_monocluster/segmentation.h =================================================================== --- /branches/fault_tolerance/platforms/linux_monocluster/segmentation.h (revision 724) +++ /branches/fault_tolerance/platforms/linux_monocluster/segmentation.h (revision 724) @@ -0,0 +1,24 @@ +#ifndef _SEGMENTATION_H +#define _SEGMENTATION_H + +#define MEMC_BASE 0x00000000 +#define MEMC_SIZE 0x10000000 // 256Mb + +#define BOOT_BASE 0xbfc00000 +#define BOOT_SIZE 0x00040000 + +#define XICU_BASE 0x10000000 +#define XICU_SIZE 0x00001000 // 1 page + +#define MTTY_BASE 0x14000000 +#define MTTY_SIZE 0x0000000c // 3 mapped-registers + +#define BD_BASE 0x1c000000 +#define BD_SIZE 0x00000040 // 9 mapped-registers + +#define FB_XSIZE 640 +#define FB_YSIZE 480 +#define FB_BASE 0x20000000 +#define FB_SIZE (FB_XSIZE * FB_YSIZE * 2) + +#endif Index: /branches/fault_tolerance/platforms/linux_monocluster/soclib.conf =================================================================== --- /branches/fault_tolerance/platforms/linux_monocluster/soclib.conf (revision 724) +++ /branches/fault_tolerance/platforms/linux_monocluster/soclib.conf (revision 724) @@ -0,0 +1,5 @@ +#config.default.toolchain.set("cflags", config.default.toolchain.cflags + ['-ggdb']) + +import os +config.addDescPath(os.environ['TSARDIR'] + "/trunk") + Index: /branches/fault_tolerance/platforms/linux_monocluster/top.cpp =================================================================== --- /branches/fault_tolerance/platforms/linux_monocluster/top.cpp (revision 724) +++ /branches/fault_tolerance/platforms/linux_monocluster/top.cpp (revision 724) @@ -0,0 +1,623 @@ +/* + * global config + */ + +#define CONFIG_GDB_SERVER + +/* + * headers + */ + +#include +#include +#include +#include +#include +#include +#include +#ifdef _OPENMP +#include +#endif + +#ifdef CONFIG_GDB_SERVER +#include "gdbserver.h" +#endif + +#include "mapping_table.h" + +#include "mips32.h" +#include "vci_mem_cache.h" +#include "vci_cc_vcache_wrapper.h" +#include "vci_block_device_tsar.h" + +#include "vci_simple_ram.h" +#include "vci_multi_tty.h" +#include "vci_xicu.h" +#include "vci_framebuffer.h" + +#include "dspin_local_crossbar.h" +#include "vci_local_crossbar.h" + +/* + * pf global config + */ + +using namespace sc_core; +using namespace soclib::caba; +using namespace soclib::common; + +#define cell_width 4 +#define cell_width_ext 8 +#define address_width 32 +#define plen_width 8 +#define error_width 1 +#define clen_width 1 +#define rflag_width 1 +#define srcid_width 14 +#define pktid_width 4 +#define trdid_width 4 +#define wrplen_width 1 + +#define dspin_cmd_width 39 +#define dspin_rsp_width 32 + +typedef VciParams vci_param; + +typedef VciParams vci_param_ext; + +/* + * segmentation + */ + +#include "segmentation.h" + + +/* + * default parameters + */ + +struct param_s { + size_t nr_cpus; + char *rom_path; + bool dsk; + char *dsk_path; + bool dummy_boot; + bool framebuffer; + bool trace_enabled; + size_t trace_start_cycle; + uint64_t ncycles; +}; + +#define PARAM_INITIALIZER \ +{ \ + .nr_cpus = 1, \ + .rom_path = NULL, \ + .dsk = false, \ + .dsk_path = NULL, \ + .dummy_boot = false, \ + .framebuffer = false, \ + .trace_enabled = false, \ + .trace_start_cycle = 0, \ + .ncycles = 0, \ +} + +static inline void print_param(const struct param_s ¶m) +{ + std::cout << std::endl; + std::cout << "simulation parameters:" << std::endl; + std::cout << " nr_cpus = " << param.nr_cpus << std::endl; + std::cout << " rom = " << param.rom_path << std::endl; + std::cout << " dummy boot = " << param.dummy_boot << std::endl; + std::cout << " framebuffer = " << param.framebuffer << std::endl; + std::cout << " dsk = " << param.dsk << std::endl; + if (param.dsk) + std::cout << " dsk_path = " << param.dsk_path << std::endl; + std::cout << " trace = " << param.trace_enabled << std::endl; + if (param.trace_enabled) + std::cout << " start cyc = " << param.trace_start_cycle << std::endl; + if (param.ncycles > 0) + std::cout << " ncycles = " << param.ncycles << std::endl; + + std::cout << std::endl; +} + +#define MAX_FROZEN_CYCLES 500000 + +/* + * arguments parsing + */ + +void args_parse(unsigned int argc, char *argv[], struct param_s ¶m) +{ + for (size_t n = 1; n < argc; n = n + 2) + { + if ((strcmp(argv[n], "--ncpus") == 0) && ((n + 1) < argc)) + { + assert((param.nr_cpus = atoi(argv[n + 1])) + && "insufficient memory"); + } + else if ((strcmp(argv[n], "--rom") == 0) && ((n + 1) < argc)) + { + assert((param.rom_path = strdup(argv[n + 1])) + && "insufficient memory"); + } + else if ((strcmp(argv[n], "--dsk") == 0) && ((n + 1) < argc)) + { + param.dsk = true; + assert((param.dsk_path = strdup(argv[n + 1])) + && "insufficient memory"); + } + else if (strcmp(argv[n], "--dummy-boot") == 0) + { + param.dummy_boot = true; + /* we don't have an extra argument */ + n = n - 1; + } + else if (strcmp(argv[n], "--framebuffer") == 0) + { + param.framebuffer = true; + /* we don't have an extra argument */ + n = n - 1; + } + else if ((strcmp(argv[n], "--trace") == 0) && ((n + 1) < argc)) + { + param.trace_enabled = true; + param.trace_start_cycle = atoi(argv[n + 1]); + } + else if ((strcmp(argv[n], "--ncycles") == 0) && ((n + 1) < argc)) + { + param.ncycles = atoll(argv[n + 1]); + } + else + { + std::cout << "Error: don't understand option " << argv[n] << std::endl; + std::cout << "Accepted arguments are :" << std::endl; + std::cout << "--ncpus pathname" << std::endl; + std::cout << "--rom pathname" << std::endl; + std::cout << "[--dsk pathname]" << std::endl; + std::cout << "[--dummy-boot]" << std::endl; + std::cout << "[--framebuffer]" << std::endl; + std::cout << "[--trace trace_start_cycle]" << std::endl; + std::cout << "[--ncycles simulation_cycles]" << std::endl; + exit(0); + } + } + + /* check parameters */ + assert((param.nr_cpus <= 4) && "cannot support more than 4 cpus"); + assert(param.rom_path && "--rom is not optional"); + + print_param(param); +} + + +/* + * netlist + */ + +int _main(int argc, char *argv[]) +{ +#ifdef _OPENMP + omp_set_dynamic(false); + omp_set_num_threads(5); + std::cerr << "Built with openmp version " << _OPENMP << std::endl; +#endif + + struct param_s param = PARAM_INITIALIZER; + + /* parse arguments */ + args_parse(argc, argv, param); + + /* + * mapping tables + */ + + /* data mapping table */ + MappingTable maptabp(32, IntTab(0, 16), IntTab(0, srcid_width), 0xF0000000); + + /* ram */ + maptabp.add(Segment("mc_m", MEMC_BASE, MEMC_SIZE, IntTab(0, 0), true)); + maptabp.add(Segment("boot", BOOT_BASE, BOOT_SIZE, IntTab(0, 1), true)); + + /* uncached peripherals */ + maptabp.add(Segment("xicu", XICU_BASE, XICU_SIZE, IntTab(0, 2), false)); + maptabp.add(Segment("tty", MTTY_BASE, MTTY_SIZE, IntTab(0, 3), false)); + maptabp.add(Segment("bd", BD_BASE, BD_SIZE, IntTab(0, 4), false)); + maptabp.add(Segment("fb", FB_BASE, FB_SIZE, IntTab(0, 5), false)); + + std::cout << maptabp << std::endl; + + /* xram mapping table */ + MappingTable maptabx(32, IntTab(8), IntTab(8), 0x30000000); + maptabx.add(Segment("xram", MEMC_BASE, MEMC_SIZE, IntTab(0), false)); + + std::cout << maptabx << std::endl; + + /* + * components + */ + + Loader loader; + loader.load_file(param.rom_path); + +#ifdef CONFIG_GDB_SERVER + typedef GdbServer proc_iss; + proc_iss::set_loader(loader); +#else + typedef Mips32ElIss proc_iss; +#endif + + if (param.dummy_boot == true) + { + /* boot linux image directly */ + uint64_t entry_addr = loader.get_entry_point_address(); + std::cout << "setResetAdress: " << std::hex << entry_addr << std::endl << std::endl; + proc_iss::setResetAddress(entry_addr); + } + + VciCcVCacheWrapper **proc; + proc = new VciCcVCacheWrapper*[param.nr_cpus]; + for (size_t i = 0; i < param.nr_cpus; i++) + { + std::ostringstream o; + o << "ccvache" << "[" << i << "]"; + proc[i] = new VciCcVCacheWrapper( + o.str().c_str(), // name + i, // proc_id + maptabp, // direct space + IntTab(0, i), // srcid_d + i, // cc_global_id + 8, 8, // itlb size + 8, 8, // dtlb size + 4, 64, 16, // icache size + 4, 64, 16, // dcache size + 4, 4, // wbuf size + 0, 0, // x, y Width + MAX_FROZEN_CYCLES, // max frozen cycles + param.trace_start_cycle, + param.trace_enabled); + } + + VciSimpleRam xram("xram", IntTab(0), maptabx, loader); + + VciSimpleRam rom("rom", IntTab(0, 1), maptabp, loader); + + VciMemCache + memc("memc", + maptabp, // direct space + maptabx, // xram space + IntTab(0), // xram srcid + IntTab(0, 0), // direct tgtid + 0, 0, // x, y width + 16, 256, 16, // cache size + 3, // max copies + 4096, 8, 8, 8, // HEAP size, TRT size, UPT size, IVT size + param.trace_start_cycle, param.trace_enabled); + + VciXicu xicu("xicu", maptabp, IntTab(0, 2), + param.nr_cpus, // #timers + 3, // #input hw irqs + param.nr_cpus, // #ipis + param.nr_cpus); // #output irqs + + VciMultiTty mtty("mtty", IntTab(0, 3), maptabp, "vcitty0", NULL); + + VciBlockDeviceTsar *bd = NULL; + if (param.dsk == true) + bd = new VciBlockDeviceTsar("bd", maptabp, + IntTab(0, param.nr_cpus), // srcid + IntTab(0, 4), // tgtid + param.dsk_path); // filename + + VciFrameBuffer *fb = NULL; + if (param.framebuffer == true) + fb = new VciFrameBuffer("fb", IntTab(0, 5), maptabp, + FB_XSIZE, FB_YSIZE, // window size + FbController::RGB_16); // color type + + /* + * Interconnects + */ + + /* data network */ + VciLocalCrossbar xbar_d("xbar_d", + maptabp, // mapping table + 0, // cluster coordinates + param.nr_cpus + 1, // #src + 6, // #dst + 1); // default target + + /* coherence */ + DspinLocalCrossbar xbar_m2p_c("xbar_m2p_c", + maptabp, + 0, 0, + 0, 0, + srcid_width, + 1, param.nr_cpus, + 2, 2, + true, + false, + true); + DspinLocalCrossbar xbar_p2m_c("xbar_p2m_c", + maptabp, + 0, 0, + 0, 0, + 0, + param.nr_cpus, 1, + 2, 2, + false, + false, + false); + DspinLocalCrossbar xbar_clack_c("xbar_clack_c", + maptabp, + 0, 0, + 0, 0, + srcid_width, + 1, param.nr_cpus, + 1, 1, + true, + false, + false); + + /* + * signals + */ + + /* clk and resetn */ + sc_clock signal_clk ("clk"); + sc_signal signal_resetn("resetn"); + + /* irq lines */ + sc_signal **signal_proc_irq = + alloc_elems >("proc_irq", param.nr_cpus, proc_iss::n_irq); + sc_signal signal_mtty_irq("mtty_irq"); + sc_signal signal_bd_irq("bd_irq"); + sc_signal signal_memc_irq("memc_irq"); + + /* vci */ + VciSignals *signal_vci_proc = + alloc_elems >("vci_proc", param.nr_cpus); + VciSignals signal_vci_ini_bd ("vci_ini_bd"); + + VciSignals signal_vci_memc ("vci_memc"); + VciSignals signal_vci_rom ("vci_rom"); + VciSignals signal_vci_xicu ("vci_xicu"); + VciSignals signal_vci_tty ("vci_tty"); + VciSignals signal_vci_tgt_bd ("vci_tgt_bd"); + VciSignals signal_vci_fb ("vci_fb"); + + VciSignals signal_vci_xram ("vci_xram"); + + /* fake signals for in/out of cluster */ + VciSignals signal_vci_from_out("vci_from_out"); + VciSignals signal_vci_to_out("vci_to_out"); + + /* Coherence DSPIN signals to local crossbar */ + DspinSignals signal_dspin_m2p_l2g; + DspinSignals signal_dspin_m2p_g2l; + DspinSignals signal_dspin_p2m_l2g; + DspinSignals signal_dspin_p2m_g2l; + DspinSignals signal_dspin_clack_l2g; + DspinSignals signal_dspin_clack_g2l; + + DspinSignals signal_dspin_m2p_memc; + DspinSignals signal_dspin_clack_memc; + DspinSignals signal_dspin_p2m_memc; + DspinSignals *signal_dspin_m2p_proc = + alloc_elems >("dspin_m2p_proc", param.nr_cpus); + DspinSignals *signal_dspin_clack_proc = + alloc_elems >("dspin_clack_proc", param.nr_cpus); + DspinSignals *signal_dspin_p2m_proc = + alloc_elems >("dspin_p2m_proc", param.nr_cpus); + + /* + * netlist + */ + + /* components */ + for (size_t i = 0; i < param.nr_cpus; i++) + { + proc[i]->p_clk(signal_clk); + proc[i]->p_resetn(signal_resetn); + for (size_t j = 0; j < proc_iss::n_irq; j++) + proc[i]->p_irq[j](signal_proc_irq[i][j]); + proc[i]->p_vci(signal_vci_proc[i]); + proc[i]->p_dspin_m2p(signal_dspin_m2p_proc[i]); + proc[i]->p_dspin_p2m(signal_dspin_p2m_proc[i]); + proc[i]->p_dspin_clack(signal_dspin_clack_proc[i]); + } + + memc.p_clk(signal_clk); + memc.p_resetn(signal_resetn); + memc.p_irq(signal_memc_irq); + memc.p_vci_tgt(signal_vci_memc); + memc.p_dspin_p2m(signal_dspin_p2m_memc); + memc.p_dspin_m2p(signal_dspin_m2p_memc); + memc.p_dspin_clack(signal_dspin_clack_memc); + memc.p_vci_ixr(signal_vci_xram); + + rom.p_clk(signal_clk); + rom.p_resetn(signal_resetn); + rom.p_vci(signal_vci_rom); + + xicu.p_resetn(signal_resetn); + xicu.p_clk(signal_clk); + xicu.p_vci(signal_vci_xicu); + xicu.p_hwi[0](signal_mtty_irq); + xicu.p_hwi[1](signal_bd_irq); + xicu.p_hwi[2](signal_memc_irq); + for (size_t i = 0; i < param.nr_cpus; i++) + xicu.p_irq[i](signal_proc_irq[i][0]); + + mtty.p_clk(signal_clk); + mtty.p_resetn(signal_resetn); + mtty.p_vci(signal_vci_tty); + mtty.p_irq[0](signal_mtty_irq); + + if (param.dsk == true) + { + bd->p_clk(signal_clk); + bd->p_resetn(signal_resetn); + bd->p_vci_target(signal_vci_tgt_bd); + bd->p_vci_initiator(signal_vci_ini_bd); + bd->p_irq(signal_bd_irq); + } + + if (param.framebuffer == true) + { + fb->p_clk(signal_clk); + fb->p_resetn(signal_resetn); + fb->p_vci(signal_vci_fb); + } + + xram.p_clk(signal_clk); + xram.p_resetn(signal_resetn); + xram.p_vci(signal_vci_xram); + + /* interconnects */ + xbar_d.p_clk(signal_clk); + xbar_d.p_resetn(signal_resetn); + xbar_d.p_target_to_up(signal_vci_from_out); + xbar_d.p_initiator_to_up(signal_vci_to_out); + for (size_t i = 0; i < param.nr_cpus; i++) + xbar_d.p_to_initiator[i](signal_vci_proc[i]); + xbar_d.p_to_initiator[param.nr_cpus](signal_vci_ini_bd); + xbar_d.p_to_target[0](signal_vci_memc); + xbar_d.p_to_target[1](signal_vci_rom); + xbar_d.p_to_target[2](signal_vci_xicu); + xbar_d.p_to_target[3](signal_vci_tty); + xbar_d.p_to_target[4](signal_vci_tgt_bd); + xbar_d.p_to_target[5](signal_vci_fb); + + xbar_m2p_c.p_clk(signal_clk); + xbar_m2p_c.p_resetn(signal_resetn); + xbar_m2p_c.p_global_out(signal_dspin_m2p_l2g); + xbar_m2p_c.p_global_in(signal_dspin_m2p_g2l); + xbar_m2p_c.p_local_in[0](signal_dspin_m2p_memc); + for (size_t i = 0; i < param.nr_cpus; i++) + xbar_m2p_c.p_local_out[i](signal_dspin_m2p_proc[i]); + + xbar_clack_c.p_clk(signal_clk); + xbar_clack_c.p_resetn(signal_resetn); + xbar_clack_c.p_global_out(signal_dspin_clack_l2g); + xbar_clack_c.p_global_in(signal_dspin_clack_g2l); + xbar_clack_c.p_local_in[0](signal_dspin_clack_memc); + for (size_t i = 0; i < param.nr_cpus; i++) + xbar_clack_c.p_local_out[i](signal_dspin_clack_proc[i]); + + xbar_p2m_c.p_clk(signal_clk); + xbar_p2m_c.p_resetn(signal_resetn); + xbar_p2m_c.p_global_out(signal_dspin_p2m_l2g); + xbar_p2m_c.p_global_in(signal_dspin_p2m_g2l); + xbar_p2m_c.p_local_out[0](signal_dspin_p2m_memc); + for (size_t i = 0; i < param.nr_cpus; i++) + xbar_p2m_c.p_local_in[i](signal_dspin_p2m_proc[i]); + + /* + * simulation + */ + + for (size_t i = 0; i < param.nr_cpus; i++) + proc[i]->iss_set_debug_mask(0); + + sc_start(sc_time(0, SC_NS)); + signal_resetn = false; + + sc_start(sc_time(1, SC_NS)); + signal_resetn = true; + + /* network boundaries initialization */ + signal_dspin_m2p_l2g.write = false; + signal_dspin_m2p_l2g.read = true; + signal_dspin_m2p_g2l.write = false; + signal_dspin_m2p_g2l.read = true; + + if (param.ncycles > 0) + { + for (size_t n = 1; n < param.ncycles; n++) + { + if (param.trace_enabled and (n > param.trace_start_cycle)) + { + std::cout << "****************** cycle " << std::dec << n + << " ************************************************" << std::endl; + + proc[0]->print_trace(); + memc.print_trace(); + + signal_vci_proc[0].print_trace("signal_vci_proc[0]"); + signal_vci_memc.print_trace("signal_vci_memc"); + + signal_dspin_m2p_memc.print_trace("signal_m2p_memc"); + signal_dspin_clack_memc.print_trace("signal_clack_memc"); + signal_dspin_p2m_memc.print_trace("signal_p2m_memc"); + for (size_t i = 0; i < param.nr_cpus; i++) + { + std::ostringstream o; + o << "signal_m2p_proc" << "[" << i << "]"; + signal_dspin_m2p_proc[i].print_trace(o.str().c_str()); + } + } + sc_start(sc_core::sc_time(1, SC_NS)); + } + } else { + uint64_t n; + struct timeval t1, t2; + + gettimeofday(&t1, NULL); + + for (n = 1; ; n++) { + /* stats display */ + if ((n % 5000000) == 0) { + gettimeofday(&t2, NULL); + + uint64_t ms1 = (uint64_t)t1.tv_sec * 1000ULL + + (uint64_t)t1.tv_usec / 1000; + uint64_t ms2 = (uint64_t)t2.tv_sec * 1000ULL + + (uint64_t)t2.tv_usec / 1000; + std::cerr << "platform clock frequency " + << (double)5000000 / (double)(ms2 - ms1) << "Khz" << std::endl; + + gettimeofday(&t1, NULL); + } + + sc_start(sc_core::sc_time(1, SC_NS)); + }; + } + + return EXIT_SUCCESS; + +} + +int sc_main (int argc, char *argv[]) +{ + try { + return _main(argc, argv); + } catch (std::exception &e) { + std::cout << e.what() << std::endl; + } catch (...) { + std::cout << "Unknown exception occured" << std::endl; + throw; + } + return EXIT_FAILURE; +} + Index: /branches/fault_tolerance/platforms/tsar_generic_iob/Makefile =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_iob/Makefile (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_iob/Makefile (revision 724) @@ -0,0 +1,9 @@ +simul.x: top.cpp top.desc + soclib-cc -P -p top.desc -I. -o simul.x + +clean: + soclib-cc -x -p top.desc -I. + rm -rf *.o *.x tty* term* + +.PHONY:simul.x + Index: /branches/fault_tolerance/platforms/tsar_generic_iob/arch.py =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_iob/arch.py (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_iob/arch.py (revision 724) @@ -0,0 +1,329 @@ +#!/usr/bin/env python + +from mapping import * + +####################################################################################### +# file : arch.py (for the tsar_generic_iob architecture) +# date : may 2014 +# author : Alain Greiner +####################################################################################### +# This file contains a mapping generator for the "tsar_generic_iob" platform. +# This includes both the hardware architecture (clusters, processors, peripherals, +# physical space segmentation) and the mapping of all kernel objects (global vsegs). +# This platform includes 6 external peripherals, accessible through two IO_Bridge +# components located in cluster [0,0] and cluster [x_size-1, y_size-1]. +# Available peripherals are: TTY, BDV, FBF, ROM, NIC, CMA. +# +# The "constructor" parameters are: +# - x_size : number of clusters in a row +# - y_size : number of clusters in a column +# - nb_procs : number of processors per cluster +# +# The "hidden" platform parameters are: +# - nb_ttys : number of TTY channels +# - nb_nics : number of NIC channels +# - fbf_width : frame_buffer width = frame_buffer heigth +# - x_io : cluster_io x coordinate +# - y_io : cluster_io y coordinate +# - x_width : number of bits for x coordinate +# - y_width : number of bits for y coordinate +# - paddr_width : number of bits for physical address +# - irq_per_proc : number of input IRQs per processor +# - use_ramdisk : use a ramdisk when True +# - peri_increment : address increment for replicated peripherals +#################################################################################### + +######################## +def arch( x_size = 2, + y_size = 2, + nb_procs = 2 ): + + ### define architecture constants + + nb_ttys = 1 + nb_nics = 2 + fbf_width = 1024 + x_io = 0 + y_io = 0 + x_width = 4 + y_width = 4 + paddr_width = 40 + irq_per_proc = 4 + use_ramdisk = False + peri_increment = 0x10000 + + ### parameters checking + + assert( nb_procs <= 4 ) + + assert( (x_size == 1) or (x_size == 2) or (x_size == 4) + or (y_size == 8) or (x_size == 16) ) + + assert( (y_size == 1) or (y_size == 2) or (y_size == 4) + or (y_size == 8) or (y_size == 16) ) + + assert( nb_ttys == 1 ) + + assert( ((x_io == 0) and (y_io == 0)) or + ((x_io == x_size-1) and (y_io == y_size-1)) ) + + platform_name = 'tsar_iob_%d_%d_%d' % ( x_size, y_size, nb_procs ) + + ### define physical segments + + ram_base = 0x0000000000 + ram_size = 0x4000000 # 64 Mbytes + + xcu_base = 0x00B0000000 + xcu_size = 0x1000 # 4 Kbytes + + dma_base = 0x00B1000000 + dma_size = 0x1000 * nb_procs # 4 Kbytes * nb_procs + + mmc_base = 0x00B2000000 + mmc_size = 0x1000 # 4 Kbytes + + offset_io = ((x_io << y_width) + y_io) << (paddr_width - x_width - y_width) + + bdv_base = 0x00B3000000 + offset_io + bdv_size = 0x1000 # 4kbytes + + tty_base = 0x00B4000000 + offset_io + tty_size = 0x4000 # 16 Kbytes + + nic_base = 0x00B5000000 + offset_io + nic_size = 0x80000 # 512 kbytes + + cma_base = 0x00B6000000 + offset_io + cma_size = 0x1000 * 2 * nb_nics # 4 kbytes * 2 * nb_nics + + fbf_base = 0x00B7000000 + offset_io + fbf_size = fbf_width * fbf_width # fbf_width * fbf_width bytes + + pic_base = 0x00B8000000 + offset_io + pic_size = 0x1000 # 4 Kbytes + + iob_base = 0x00BE000000 + offset_io + iob_size = 0x1000 # 4kbytes + + rom_base = 0x00BFC00000 + offset_io + rom_size = 0x4000 # 16 Kbytes + + ### define bootloader vsegs base addresses + + boot_mapping_vbase = 0x00000000 # ident + boot_mapping_size = 0x00010000 # 64 Kbytes + + boot_code_vbase = 0x00010000 # ident + boot_code_size = 0x00020000 # 128 Kbytes + + boot_data_vbase = 0x00030000 # ident + boot_data_size = 0x00010000 # 64 Kbytes + + boot_buffer_vbase = 0x00040000 # ident + boot_buffer_size = 0x00060000 # 384 Kbytes + + boot_stack_vbase = 0x000A0000 # ident + boot_stack_size = 0x00050000 # 320 Kbytes + + ### define kernel vsegs base addresses + + kernel_code_vbase = 0x80000000 + kernel_code_size = 0x00020000 # 128 Kbytes + + kernel_data_vbase = 0x80020000 + kernel_data_size = 0x00060000 # 384 Kbytes + + kernel_uncdata_vbase = 0x80080000 + kernel_uncdata_size = 0x00040000 # 256 Kbytes + + kernel_init_vbase = 0x800C0000 + kernel_init_size = 0x00010000 # 64 Kbytes + + kernel_sched_vbase = 0xF0000000 # distributed in all clusters + kernel_sched_size = 0x1000 * nb_procs # 4 kbytes per processor + + ### create mapping + + mapping = Mapping( name = platform_name, + x_size = x_size, + y_size = y_size, + procs_max = nb_procs, + x_width = x_width, + y_width = y_width, + paddr_width = paddr_width, + coherence = True, + irq_per_proc = irq_per_proc, + use_ramdisk = use_ramdisk, + x_io = x_io, + y_io = y_io, + peri_increment = peri_increment ) + + ### external peripherals (accessible in cluster[0,0] only for this mapping) + + iob = mapping.addPeriph( 'IOB', base = iob_base, size = iob_size, ptype = 'IOB' ) + + bdv = mapping.addPeriph( 'BDV', base = bdv_base, size = bdv_size, ptype = 'IOC', subtype = 'BDV' ) + + tty = mapping.addPeriph( 'TTY', base = tty_base, size = tty_size, ptype = 'TTY', channels = nb_ttys ) + + nic = mapping.addPeriph( 'NIC', base = nic_base, size = nic_size, ptype = 'NIC', channels = nb_nics ) + + cma = mapping.addPeriph( 'CMA', base = cma_base, size = cma_size, ptype = 'CMA', channels = 2*nb_nics ) + + fbf = mapping.addPeriph( 'FBF', base = fbf_base, size = fbf_size, ptype = 'FBF', arg = fbf_width ) + + rom = mapping.addPeriph( 'ROM', base = rom_base, size = rom_size, ptype = 'ROM' ) + + pic = mapping.addPeriph( 'PIC', base = pic_base, size = pic_size, ptype = 'PIC', channels = 32 ) + + mapping.addIrq( pic, index = 0, isrtype = 'ISR_NIC_RX', channel = 0 ) + mapping.addIrq( pic, index = 1, isrtype = 'ISR_NIC_RX', channel = 1 ) + + mapping.addIrq( pic, index = 2, isrtype = 'ISR_NIC_TX', channel = 0 ) + mapping.addIrq( pic, index = 3, isrtype = 'ISR_NIC_TX', channel = 1 ) + + mapping.addIrq( pic, index = 4, isrtype = 'ISR_CMA' , channel = 0 ) + mapping.addIrq( pic, index = 5, isrtype = 'ISR_CMA' , channel = 1 ) + mapping.addIrq( pic, index = 6, isrtype = 'ISR_CMA' , channel = 2 ) + mapping.addIrq( pic, index = 7, isrtype = 'ISR_CMA' , channel = 3 ) + + mapping.addIrq( pic, index = 8, isrtype = 'ISR_BDV' , channel = 0 ) + + mapping.addIrq( pic, index = 9, isrtype = 'ISR_TTY_RX', channel = 0 ) + + ### hardware components replicated in all clusters + + for x in xrange( x_size ): + for y in xrange( y_size ): + cluster_xy = (x << y_width) + y; + offset = cluster_xy << (paddr_width - x_width - y_width) + + ram = mapping.addRam( 'RAM', base = ram_base + offset, size = ram_size ) + + mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset, size = mmc_size, + ptype = 'MMC' ) + + dma = mapping.addPeriph( 'DMA', base = dma_base + offset, size = dma_size, + ptype = 'DMA', channels = nb_procs ) + + xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset, size = xcu_size, + ptype = 'XCU', channels = nb_procs * irq_per_proc, arg = 16 ) + + # MMC IRQ replicated in all clusters + mapping.addIrq( xcu, index = 0, isrtype = 'ISR_MMC' ) + + # processors + for p in xrange ( nb_procs ): + mapping.addProc( x, y, p ) + + ### global vsegs for boot_loader / identity mapping + + mapping.addGlobal( 'seg_boot_mapping' , boot_mapping_vbase , boot_mapping_size , 'C_W_', + vtype = 'BLOB' , x = 0, y = 0, pseg = 'RAM', identity = True ) + + mapping.addGlobal( 'seg_boot_code' , boot_code_vbase , boot_code_size , 'CXW_', + vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) + + mapping.addGlobal( 'seg_boot_data' , boot_data_vbase , boot_data_size , 'C_W_', + vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) + + mapping.addGlobal( 'seg_boot_buffer' , boot_buffer_vbase , boot_buffer_size , 'C_W_', + vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) + + mapping.addGlobal( 'seg_boot_stack' , boot_stack_vbase , boot_stack_size , 'C_W_', + vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) + + ### global vsegs for kernel + + mapping.addGlobal( 'seg_kernel_code' , kernel_code_vbase , kernel_code_size , 'CXW_', + vtype = 'ELF' , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' ) + + mapping.addGlobal( 'seg_kernel_data' , kernel_data_vbase , kernel_data_size , 'C_W_', + vtype = 'ELF' , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' ) + + mapping.addGlobal( 'seg_kernel_uncdata', kernel_uncdata_vbase, kernel_uncdata_size, '__W_', + vtype = 'ELF' , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' ) + + mapping.addGlobal( 'seg_kernel_init' , kernel_init_vbase , kernel_init_size , 'CXW_', + vtype = 'ELF' , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' ) + + ### global vsegs for external peripherals / identity mapping + + mapping.addGlobal( 'seg_iob', iob_base, iob_size, '__W_', + vtype = 'PERI', x = 0, y = 0, pseg = 'IOB', identity = True ) + + mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size, '__W_', + vtype = 'PERI', x = 0, y = 0, pseg = 'BDV', identity = True ) + + mapping.addGlobal( 'seg_tty', tty_base, tty_size, '__W_', + vtype = 'PERI', x = 0, y = 0, pseg = 'TTY', identity = True ) + + mapping.addGlobal( 'seg_nic', nic_base, nic_size, '__W_', + vtype = 'PERI', x = 0, y = 0, pseg = 'NIC', identity = True ) + + mapping.addGlobal( 'seg_cma', cma_base, cma_size, '__W_', + vtype = 'PERI', x = 0, y = 0, pseg = 'CMA', identity = True ) + + mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, '__W_', + vtype = 'PERI', x = 0, y = 0, pseg = 'FBF', identity = True ) + + mapping.addGlobal( 'seg_pic', pic_base, pic_size, '__W_', + vtype = 'PERI', x = 0, y = 0, pseg = 'PIC', identity = True ) + + mapping.addGlobal( 'seg_rom', rom_base, rom_size, 'CXW_', + vtype = 'PERI', x = 0, y = 0, pseg = 'ROM', identity = True ) + + ### Global vsegs for replicated peripherals, and for schedulers + ### name is indexed by (x,y), base address is incremented by (cluster_xy * peri_increment) + + for x in xrange( x_size ): + for y in xrange( y_size ): + cluster_xy = (x << y_width) + y; + offset = cluster_xy * peri_increment + + mapping.addGlobal( 'seg_xcu_%d_%d' %(x,y), xcu_base + offset, xcu_size, + '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'XCU' ) + + mapping.addGlobal( 'seg_dma_%d_%d' %(x,y), dma_base + offset, dma_size, + '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'DMA' ) + + mapping.addGlobal( 'seg_mmc_%d_%d' %(x,y), mmc_base + offset, mmc_size, + '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'MMC' ) + + mapping.addGlobal( 'seg_sched_%d_%d' %(x,y), kernel_sched_vbase + offset, kernel_sched_size, + 'C_W_', vtype = 'SCHED', x = x , y = y , pseg = 'RAM' ) + + ### return mapping ### + + return mapping + +################################# platform test ####################################################### + +if __name__ == '__main__': + + mapping = genmap( x_size = 2, + y_size = 2, + nb_procs = 2, + nb_ttys = 1, + nb_nics = 2, + fbf_width = 128, + x_io = 0, + y_io = 0 ) + +# print mapping.netbsd_dts() + + print mapping.xml() + +# print mapping.giet_vsegs() + + +# Local Variables: +# tab-width: 4; +# c-basic-offset: 4; +# c-file-offsets:((innamespace . 0)(inline-open . 0)); +# indent-tabs-mode: nil; +# End: +# +# vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: /branches/fault_tolerance/platforms/tsar_generic_iob/giet_vm =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_iob/giet_vm (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_iob/giet_vm (revision 724) @@ -0,0 +1,1 @@ +link ../../../giet_vm Index: /branches/fault_tolerance/platforms/tsar_generic_iob/top.cpp =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_iob/top.cpp (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_iob/top.cpp (revision 724) @@ -0,0 +1,1571 @@ +/////////////////////////////////////////////////////////////////////////////// +// File: top.cpp (for tsar_generic_iob platform) +// Author: Alain Greiner +// Copyright: UPMC/LIP6 +// Date : august 2013 +// This program is released under the GNU public license +/////////////////////////////////////////////////////////////////////////////// +// This file define a generic TSAR architecture with an IO network emulating +// an external bus (i.e. Hypertransport) to access 7 external peripherals: +// +// - BROM : boot ROM +// - FBUF : Frame Buffer +// - MTTY : multi TTY (up to 15 channels) +// - MNIC : Network controller (up to 2 channels) +// - CDMA : Chained Buffer DMA controller (up to 4 channels) +// - BDEV : Dlock Device controler (1 channel) +// - IOPI : HWI to SWI translator. +// +// The internal physical address space is 40 bits, and the cluster index +// is defined by the 8 MSB bits, using a fixed format: X is encoded on 4 bits, +// Y is encodes on 4 bits, whatever the actual mesh size. +// => at most 16 * 16 clusters. Each cluster contains up to 4 processors. +// +// It contains 3 networks: +// +// 1) the "INT" network supports Read/Write transactions +// between processors and L2 caches or peripherals. +// (VCI ADDDRESS = 40 bits / VCI DATA width = 32 bits) +// It supports also coherence transactions between L1 & L2 caches. +// 3) the "RAM" network emulates the 3D network between L2 caches +// and L3 caches, and is implemented as a 2D mesh between the L2 caches, +// the two IO bridges and the physical RAMs disributed in all clusters. +// (VCI ADDRESS = 40 bits / VCI DATA = 64 bits) +// 4) the IOX network connects the two IO bridge components to the +// 7 external peripheral controllers. +// (VCI ADDDRESS = 40 bits / VCI DATA width = 64 bits) +// +// The external peripherals HWI IRQs are translated to WTI IRQs by the +// external IOPIC component, that must be configured by the OS to route +// these WTI ITQS to one or several internal XICU components. +// The total number of channels for the external peripherals (MTTY, MNIC, CDMA +// IOC or HBA) is limited by the IOPIC 32 HWI inputs:.. +// - IOPIC HWI[1:0] connected to IRQ_NIC_RX[1:0] +// - IOPIC HWI[3:2] connected to IRQ_NIC_TX[1:0] +// - IOPIC HWI[7:4] connected to IRQ_CMA_TX[3:0]] +// - IOPIC HWI[8] connected to IRQ_BDEV +// - IOPIC HWI[15:9] unused (grounded) +// - IOPIC HWI[23:16] connected to IRQ_TTY_RX[7:0]] +// - IOPIC HWI[31:24] connected to IRQ_TTY_TX[7:0]] TBD +// +// Besides the external peripherals, each cluster contains on XICU component, +// and one multi channels DMA component. +// The XICU component is mainly used to handle WTI IRQs, as only 2 HWI IRQs +// are connected to XICU in each cluster: +// - IRQ_IN[0] : MMC +// - IRQ_IN[1] : DMA channel 0 +// - IRQ_IN[2] : DMA channel 1 +// - IRQ_IN[3] : DMA channel 2 +// - IRQ_IN[4] : DMA channel 3 +// +// All clusters are identical, but cluster(0,0) and cluster(XMAX-1,YMAX-1) +// contain an extra IO bridge component. These IOB0 & IOB1 components are +// connected to the three networks (INT, RAM, IOX). +// +// - It uses two dspin_local_crossbar per cluster to implement the +// local interconnect correponding to the INT network. +// - It uses three dspin_local_crossbar per cluster to implement the +// local interconnect correponding to the coherence INT network. +// - It uses two virtual_dspin_router per cluster to implement +// the INT network (routing both the direct and coherence trafic). +// - It uses two dspin_router per cluster to implement the RAM network. +// - It uses the vci_cc_vcache_wrapper. +// - It uses the vci_mem_cache. +// - It contains one vci_xicu and one vci_multi_dma per cluster. +// - It contains one vci_simple ram per cluster to model the L3 cache. +// +// The TsarIobCluster component is defined in files +// tsar_iob_cluster.* (with * = cpp, h, sd) +// +// The main hardware parameters must be defined in the hard_config.h file : +// - X_SIZE : number of clusters in a row +// - Y_SIZE : number of clusters in a column +// - NB_PROCS_MAX : number of processors per cluster (power of 2) +// - NB_TTY_CHANNELS : number of TTY channels in I/O network (must be 1) +// - NB_NIC_CHANNELS : number of NIC channels in I/O network (up to 2) +// - NB_CMA_CHANNELS : number of CMA channels in I/O network (up to 4) +// - FBUF_X_SIZE : width of frame buffer (pixels) +// - FBUF_Y_SIZE : heigth of frame buffer (lines) +// - XCU_NB_INPUTS : number of HWIs = number of WTIs = number of PTIs +// +// Some secondary hardware parameters must be defined in this top.cpp file: +// - XRAM_LATENCY : external ram latency +// - MEMC_WAYS : L2 cache number of ways +// - MEMC_SETS : L2 cache number of sets +// - L1_IWAYS +// - L1_ISETS +// - L1_DWAYS +// - L1_DSETS +// - BDEV_IMAGE_NAME : file pathname for block device +// - NIC_RX_NAME : file pathname for NIC received packets +// - NIC_TX_NAME : file pathname for NIC transmited packets +// - NIC_TIMEOUT : max number of cycles before closing a container +// +// General policy for 40 bits physical address decoding: +// All physical segments base addresses are multiple of 1 Mbytes +// (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) +// The (x_width + y_width) MSB bits (left aligned) define +// the cluster index, and the LADR bits define the local index: +// |X_ID|Y_ID| LADR | OFFSET | +// | 4 | 4 | 8 | 24 | +// +// General policy for 14 bits SRCID decoding: +// Each component is identified by (x_id, y_id, l_id) tuple. +// |X_ID|Y_ID| L_ID | +// | 4 | 4 | 6 | +///////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include +#include +#include +#include + +#include "gdbserver.h" +#include "mapping_table.h" + +#include "tsar_iob_cluster.h" +#include "vci_chbuf_dma.h" +#include "vci_multi_tty.h" +#include "vci_multi_nic.h" +#include "vci_simple_rom.h" +#include "vci_block_device_tsar.h" +#include "vci_framebuffer.h" +#include "vci_iox_network.h" +#include "vci_iox_network.h" +#include "vci_iopic.h" + +#include "alloc_elems.h" + +/////////////////////////////////////////////////// +// OS +/////////////////////////////////////////////////// +#define USE_ALMOS 0 + +#define almos_bootloader_pathname "bootloader.bin" +#define almos_kernel_pathname "kernel-soclib.bin@0xbfc10000:D" +#define almos_archinfo_pathname "arch-info.bin@0xBFC08000:D" + +/////////////////////////////////////////////////// +// Parallelisation +/////////////////////////////////////////////////// +#define USE_OPENMP 0 + +#if USE_OPENMP +#include +#endif + +/////////////////////////////////////////////////////////// +// DSPIN parameters +/////////////////////////////////////////////////////////// + +#define dspin_int_cmd_width 39 +#define dspin_int_rsp_width 32 + +#define dspin_ram_cmd_width 64 +#define dspin_ram_rsp_width 64 + +/////////////////////////////////////////////////////////// +// VCI fields width for the 3 VCI networks +/////////////////////////////////////////////////////////// + +#define vci_cell_width_int 4 +#define vci_cell_width_ext 8 + +#define vci_plen_width 8 +#define vci_address_width 40 +#define vci_rerror_width 1 +#define vci_clen_width 1 +#define vci_rflag_width 1 +#define vci_srcid_width 14 +#define vci_pktid_width 4 +#define vci_trdid_width 4 +#define vci_wrplen_width 1 + +//////////////////////////////////////////////////////////// +// Main Hardware Parameters values +//////////////////////i///////////////////////////////////// + +#include "hard_config.h" + +//////////////////////////////////////////////////////////// +// Secondary Hardware Parameters values +//////////////////////i///////////////////////////////////// + +#define XMAX X_SIZE +#define YMAX Y_SIZE + +#define XRAM_LATENCY 0 + +#define MEMC_WAYS 16 +#define MEMC_SETS 256 + +#define L1_IWAYS 4 +#define L1_ISETS 64 + +#define L1_DWAYS 4 +#define L1_DSETS 64 + +#define BDEV_IMAGE_NAME "../../../giet_vm/hdd/virt_hdd.dmg" + +#define NIC_RX_NAME "giet_vm/nic/rx_packets.txt" +#define NIC_TX_NAME "giet_vm/nic/tx_packets.txt" +#define NIC_TIMEOUT 10000 + +#define NORTH 0 +#define SOUTH 1 +#define EAST 2 +#define WEST 3 + +#define cluster(x,y) ((y) + ((x) << 4)) + +//////////////////////////////////////////////////////////// +// Software to be loaded in ROM & RAM +//////////////////////i///////////////////////////////////// + +#define BOOT_SOFT_NAME "../../softs/tsar_boot/preloader.elf" + +// Activate Distributed Boot +// When this is activated, every processor boots with its physical address +// extension register initialized to its cluster index (X_LOCAL, Y_LOCAL). To +// support this feature, a distributed ROM is implemented in each cluster. + +#ifndef DISTRIBUTED_BOOT +#define DISTRIBUTED_BOOT false +#endif + +//////////////////////////////////////////////////////////// +// DEBUG Parameters default values +//////////////////////i///////////////////////////////////// + +#define MAX_FROZEN_CYCLES 200000 + +///////////////////////////////////////////////////////// +// Physical segments definition +///////////////////////////////////////////////////////// + +// Replicated RAMs : address is incremented by a cluster offset +// offset = cluster(x,y) << (address_width-x_width-y_width); + +#define SEG_RAM_BASE 0x0000000000 +#define SEG_RAM_SIZE 0x0004000000 // 64 Mbytes + +//////////////////////////////////////////////////////////////////////// +// SRCID definition +//////////////////////////////////////////////////////////////////////// +// All initiators are in the same indexing space (14 bits). +// The SRCID is structured in two fields: +// - The 10 MSB bits define the cluster index (left aligned) +// - The 4 LSB bits define the local index. +// Two different initiators cannot have the same SRCID, but a given +// initiator can have two alias SRCIDs: +// - Internal initiators (procs, mdma) are replicated in all clusters, +// and each initiator has one single SRCID. +// - External initiators (bdev, cdma) are not replicated, but can be +// accessed in 2 clusters : cluster_iob0 and cluster_iob1. +// They have the same local index, but two different cluster indexes. +// +// As cluster_iob0 and cluster_iob1 contain both internal initiators +// and external initiators, they must have different local indexes. +// Consequence: For a local interconnect, the INI_ID port index +// is NOT equal to the SRCID local index, and the local interconnect +// must make a translation: SRCID => INI_ID +//////////////////////////////////////////////////////////////////////// + +#define PROC_LOCAL_SRCID 0x0 // from 0 to 7 +#define MDMA_LOCAL_SRCID 0x8 +#define IOBX_LOCAL_SRCID 0x9 +#define MEMC_LOCAL_SRCID 0xA +#define CDMA_LOCAL_SRCID 0xB +#define BDEV_LOCAL_SRCID 0xC +#define IOPI_LOCAL_SRCID 0xD + +/////////////////////////////////////////////////////////////////////// +// TGT_ID and INI_ID port indexing for INT local interconnect +/////////////////////////////////////////////////////////////////////// + +#define INT_MEMC_TGT_ID 0 +#define INT_XICU_TGT_ID 1 +#define INT_MDMA_TGT_ID 2 +#define INT_BROM_TGT_ID 3 +#define INT_IOBX_TGT_ID 4 + +#define INT_PROC_INI_ID 0 // from 0 to (NB_PROCS_MAX-1) +#define INT_MDMA_INI_ID (NB_PROCS_MAX) +#define INT_IOBX_INI_ID (NB_PROCS_MAX+1) + +/////////////////////////////////////////////////////////////////////// +// TGT_ID and INI_ID port indexing for RAM local interconnect +/////////////////////////////////////////////////////////////////////// + +#define RAM_XRAM_TGT_ID 0 + +#define RAM_MEMC_INI_ID 0 +#define RAM_IOBX_INI_ID 1 + +/////////////////////////////////////////////////////////////////////// +// TGT_ID and INI_ID port indexing for I0X local interconnect +/////////////////////////////////////////////////////////////////////// + +#define IOX_FBUF_TGT_ID 0 +#define IOX_BDEV_TGT_ID 1 +#define IOX_MNIC_TGT_ID 2 +#define IOX_CDMA_TGT_ID 3 +#define IOX_MTTY_TGT_ID 4 +#define IOX_IOPI_TGT_ID 5 +#define IOX_IOB0_TGT_ID 6 +#define IOX_IOB1_TGT_ID 7 + +#define IOX_BDEV_INI_ID 0 +#define IOX_CDMA_INI_ID 1 +#define IOX_IOPI_INI_ID 2 +#define IOX_IOB0_INI_ID 3 +#define IOX_IOB1_INI_ID 4 + +//////////////////////////////////////////////////////////////////////// +int _main(int argc, char *argv[]) +//////////////////////////////////////////////////////////////////////// +{ + using namespace sc_core; + using namespace soclib::caba; + using namespace soclib::common; + + + char soft_name[256] = BOOT_SOFT_NAME; // pathname: binary code + size_t ncycles = 1000000000; // simulated cycles + char disk_name[256] = BDEV_IMAGE_NAME; // pathname: disk image + char nic_rx_name[256] = NIC_RX_NAME; // pathname: rx packets file + char nic_tx_name[256] = NIC_TX_NAME; // pathname: tx packets file + ssize_t threads_nr = 1; // simulator's threads number + bool debug_ok = false; // trace activated + size_t debug_period = 1; // trace period + size_t debug_memc_id = 0xFFFFFFFF; // index of traced memc + size_t debug_proc_id = 0xFFFFFFFF; // index of traced proc + size_t debug_xram_id = 0xFFFFFFFF; // index of traced xram + bool debug_iob = false; // trace iob0 & iob1 when true + uint32_t debug_from = 0; // trace start cycle + uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor + size_t cluster_iob0 = cluster(0,0); // cluster containing IOB0 + size_t cluster_iob1 = cluster(XMAX-1,YMAX-1); // cluster containing IOB1 + size_t x_width = 4; // at most 256 clusters + size_t y_width = 4; // at most 256 clusters + + assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and + "ERROR: we must have X_WIDTH == Y_WIDTH == 4"); + + ////////////// command line arguments ////////////////////// + if (argc > 1) + { + for (int n = 1; n < argc; n = n + 2) + { + if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1> 4; + size_t y = debug_memc_id & 0xF; + if( (x>=XMAX) || (y>=YMAX) ) + { + std::cout << "MEMCID parameter does'nt fit XMAX/YMAX" << std::endl; + exit(0); + } + } + else if ((strcmp(argv[n],"-XRAMID") == 0) && (n+1> 4; + size_t y = debug_xram_id & 0xF; + if( (x>=XMAX) || (y>=YMAX) ) + { + std::cout << "XRAMID parameter does'nt fit XMAX/YMAX" << std::endl; + exit(0); + } + } + else if ((strcmp(argv[n],"-IOB") == 0) && (n+1> 4; + size_t y = cluster_xy & 0xF; + if( (x>=XMAX) || (y>=YMAX) ) + { + std::cout << "PROCID parameter does'nt fit XMAX/YMAX" << std::endl; + exit(0); + } + } + else if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc)) + { + threads_nr = atoi(argv[n+1]); + threads_nr = (threads_nr < 1) ? 1 : threads_nr; + } + else if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc)) + { + frozen_cycles = atoi(argv[n+1]); + } + else if ((strcmp(argv[n], "-PERIOD") == 0) && (n+1 < argc)) + { + debug_period = atoi(argv[n+1]); + } + else + { + std::cout << " Arguments are (key,value) couples." << std::endl; + std::cout << " The order is not important." << std::endl; + std::cout << " Accepted arguments are :" << std::endl << std::endl; + std::cout << " -SOFT pathname_for_embedded_soft" << std::endl; + std::cout << " -DISK pathname_for_disk_image" << std::endl; + std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl; + std::cout << " -DEBUG debug_start_cycle" << std::endl; + std::cout << " -THREADS simulator's threads number" << std::endl; + std::cout << " -FROZEN max_number_of_lines" << std::endl; + std::cout << " -PERIOD number_of_cycles between trace" << std::endl; + std::cout << " -MEMCID index_memc_to_be_traced" << std::endl; + std::cout << " -XRAMID index_xram_to_be_traced" << std::endl; + std::cout << " -PROCID index_proc_to_be_traced" << std::endl; + std::cout << " -IOB non_zero_value" << std::endl; + exit(0); + } + } + } + + // checking hardware parameters + assert( (XMAX <= 16) and + "The XMAX parameter cannot be larger than 16" ); + + assert( (YMAX <= 16) and + "The YMAX parameter cannot be larger than 16" ); + + assert( (NB_PROCS_MAX <= 8) and + "The NB_PROCS_MAX parameter cannot be larger than 8" ); + + assert( (NB_DMA_CHANNELS <= 4) and + "The NB_DMA_CHANNELS parameter cannot be larger than 4" ); + + assert( (NB_TTY_CHANNELS == 1) and + "The NB_TTY_CHANNELS parameter must be 1" ); + + assert( (NB_NIC_CHANNELS == 2) and + "The NB_NIC_CHANNELS parameter must be 2" ); + + std::cout << std::endl << std::dec + << " - XMAX = " << XMAX << std::endl + << " - YMAX = " << YMAX << std::endl + << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl + << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl + << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl + << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl + << " - MEMC_WAYS = " << MEMC_WAYS << std::endl + << " - MEMC_SETS = " << MEMC_SETS << std::endl + << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl + << " - MAX_FROZEN = " << frozen_cycles << std::endl + << " - DEBUG_PROCID = " << debug_proc_id << std::endl + << " - DEBUG_MEMCID = " << debug_memc_id << std::endl + << " - DEBUG_XRAMID = " << debug_xram_id << std::endl; + + std::cout << std::endl; + +#if USE_OPENMP + omp_set_dynamic(false); + omp_set_num_threads(threads_nr); + std::cerr << "Built with openmp version " << _OPENMP << std::endl; +#endif + + // Define VciParams objects + typedef soclib::caba::VciParams vci_param_int; + + typedef soclib::caba::VciParams vci_param_ext; + + ///////////////////////////////////////////////////////////////////// + // INT network mapping table + // - two levels address decoding for commands + // - two levels srcid decoding for responses + // - NB_PROCS_MAX + 2 (MDMA, IOBX) local initiators per cluster + // - 4 local targets (MEMC, XICU, MDMA, IOBX) per cluster + ///////////////////////////////////////////////////////////////////// + MappingTable maptab_int( vci_address_width, + IntTab(x_width + y_width, 16 - x_width - y_width), + IntTab(x_width + y_width, vci_srcid_width - x_width - y_width), + 0x00FF000000); + + for (size_t x = 0; x < XMAX; x++) + { + for (size_t y = 0; y < YMAX; y++) + { + uint64_t offset = ((uint64_t)cluster(x,y)) + << (vci_address_width-x_width-y_width); + bool config = true; + bool cacheable = true; + + // the four following segments are defined in all clusters + + std::ostringstream smemc_conf; + smemc_conf << "int_seg_memc_conf_" << x << "_" << y; + maptab_int.add(Segment(smemc_conf.str(), SEG_MMC_BASE+offset, SEG_MMC_SIZE, + IntTab(cluster(x,y), INT_MEMC_TGT_ID), not cacheable, config )); + + std::ostringstream smemc_xram; + smemc_xram << "int_seg_memc_xram_" << x << "_" << y; + maptab_int.add(Segment(smemc_xram.str(), SEG_RAM_BASE+offset, SEG_RAM_SIZE, + IntTab(cluster(x,y), INT_MEMC_TGT_ID), cacheable)); + + std::ostringstream sxicu; + sxicu << "int_seg_xicu_" << x << "_" << y; + maptab_int.add(Segment(sxicu.str(), SEG_XCU_BASE+offset, SEG_XCU_SIZE, + IntTab(cluster(x,y), INT_XICU_TGT_ID), not cacheable)); + + std::ostringstream smdma; + smdma << "int_seg_mdma_" << x << "_" << y; + maptab_int.add(Segment(smdma.str(), SEG_DMA_BASE+offset, SEG_DMA_SIZE, + IntTab(cluster(x,y), INT_MDMA_TGT_ID), not cacheable)); + + std::ostringstream sbrom; + sbrom << "int_seg_brom_" << x << "_" << y; + maptab_int.add(Segment(sbrom.str(), SEG_ROM_BASE+offset, SEG_ROM_SIZE, + IntTab(cluster(x,y), INT_BROM_TGT_ID), cacheable)); + + // the following segments are only defined in cluster_iob0 or in cluster_iob1 + + if ( (cluster(x,y) == cluster_iob0) or (cluster(x,y) == cluster_iob1) ) + { + std::ostringstream siobx; + siobx << "int_seg_iobx_" << x << "_" << y; + maptab_int.add(Segment(siobx.str(), SEG_IOB_BASE+offset, SEG_IOB_SIZE, + IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable, config )); + + std::ostringstream stty; + stty << "int_seg_mtty_" << x << "_" << y; + maptab_int.add(Segment(stty.str(), SEG_TTY_BASE+offset, SEG_TTY_SIZE, + IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); + + std::ostringstream sfbf; + sfbf << "int_seg_fbuf_" << x << "_" << y; + maptab_int.add(Segment(sfbf.str(), SEG_FBF_BASE+offset, SEG_FBF_SIZE, + IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); + + std::ostringstream sbdv; + sbdv << "int_seg_bdev_" << x << "_" << y; + maptab_int.add(Segment(sbdv.str(), SEG_IOC_BASE+offset, SEG_IOC_SIZE, + IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); + + std::ostringstream snic; + snic << "int_seg_mnic_" << x << "_" << y; + maptab_int.add(Segment(snic.str(), SEG_NIC_BASE+offset, SEG_NIC_SIZE, + IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); + + std::ostringstream sdma; + sdma << "int_seg_cdma_" << x << "_" << y; + maptab_int.add(Segment(sdma.str(), SEG_CMA_BASE+offset, SEG_CMA_SIZE, + IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); + + std::ostringstream spic; + spic << "int_seg_iopi_" << x << "_" << y; + maptab_int.add(Segment(spic.str(), SEG_PIC_BASE+offset, SEG_PIC_SIZE, + IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); + } + + // This define the mapping between the SRCIDs + // and the port index on the local interconnect. + + maptab_int.srcid_map( IntTab( cluster(x,y), MDMA_LOCAL_SRCID ), + IntTab( cluster(x,y), INT_MDMA_INI_ID ) ); + + maptab_int.srcid_map( IntTab( cluster(x,y), IOBX_LOCAL_SRCID ), + IntTab( cluster(x,y), INT_IOBX_INI_ID ) ); + + maptab_int.srcid_map( IntTab( cluster(x,y), IOPI_LOCAL_SRCID ), + IntTab( cluster(x,y), INT_IOBX_INI_ID ) ); + + for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++ ) + maptab_int.srcid_map( IntTab( cluster(x,y), PROC_LOCAL_SRCID+p ), + IntTab( cluster(x,y), INT_PROC_INI_ID+p ) ); + } + } + std::cout << "INT network " << maptab_int << std::endl; + + ///////////////////////////////////////////////////////////////////////// + // RAM network mapping table + // - two levels address decoding for commands + // - two levels srcid decoding for responses + // - 2 local initiators (MEMC, IOBX) per cluster + // (IOBX component only in cluster_iob0 and cluster_iob1) + // - 1 local target (XRAM) per cluster + //////////////////////////////////////////////////////////////////////// + MappingTable maptab_ram( vci_address_width, + IntTab(x_width+y_width, 0), + IntTab(x_width+y_width, vci_srcid_width - x_width - y_width), + 0x00FF000000); + + for (size_t x = 0; x < XMAX; x++) + { + for (size_t y = 0; y < YMAX ; y++) + { + uint64_t offset = ((uint64_t)cluster(x,y)) + << (vci_address_width-x_width-y_width); + + std::ostringstream sxram; + sxram << "ext_seg_xram_" << x << "_" << y; + maptab_ram.add(Segment(sxram.str(), SEG_RAM_BASE+offset, + SEG_RAM_SIZE, IntTab(cluster(x,y), RAM_XRAM_TGT_ID), false)); + } + } + + // This define the mapping between the initiators SRCID + // and the port index on the RAM local interconnect. + // External initiator have two alias SRCID (iob0 / iob1) + + maptab_ram.srcid_map( IntTab( cluster_iob0, CDMA_LOCAL_SRCID ), + IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); + + maptab_ram.srcid_map( IntTab( cluster_iob1, CDMA_LOCAL_SRCID ), + IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); + + maptab_ram.srcid_map( IntTab( cluster_iob0, BDEV_LOCAL_SRCID ), + IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); + + maptab_ram.srcid_map( IntTab( cluster_iob1, BDEV_LOCAL_SRCID ), + IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); + + maptab_ram.srcid_map( IntTab( cluster_iob0, IOPI_LOCAL_SRCID ), + IntTab( cluster_iob0, RAM_IOBX_INI_ID ) ); + + maptab_ram.srcid_map( IntTab( cluster_iob1, IOPI_LOCAL_SRCID ), + IntTab( cluster_iob1, RAM_IOBX_INI_ID ) ); + + maptab_ram.srcid_map( IntTab( cluster_iob0, MEMC_LOCAL_SRCID ), + IntTab( cluster_iob0, RAM_MEMC_INI_ID ) ); + + maptab_ram.srcid_map( IntTab( cluster_iob1, MEMC_LOCAL_SRCID ), + IntTab( cluster_iob1, RAM_MEMC_INI_ID ) ); + + std::cout << "RAM network " << maptab_ram << std::endl; + + /////////////////////////////////////////////////////////////////////// + // IOX network mapping table + // - two levels address decoding for commands (9, 7) bits + // - two levels srcid decoding for responses + // - 5 initiators (IOB0, IOB1, BDEV, CDMA, IOPI) + // - 9 targets (IOB0, IOB1, BDEV, CDMA, MTTY, FBUF, BROM, MNIC, IOPI) + // + // Address bit 32 is used to determine if a command must be routed to + // IOB0 or IOB1. + /////////////////////////////////////////////////////////////////////// + MappingTable maptab_iox( + vci_address_width, + IntTab(x_width + y_width - 1, 16 - x_width - y_width + 1), + IntTab(x_width + y_width , vci_param_ext::S - x_width - y_width), + 0x00FF000000); + + // External peripherals segments + // When there is more than one cluster, external peripherals can be accessed + // through two segments, depending on the used IOB (IOB0 or IOB1). + + const uint64_t iob0_base = ((uint64_t)cluster_iob0) + << (vci_address_width - x_width - y_width); + + maptab_iox.add(Segment("iox_seg_mtty_0", SEG_TTY_BASE + iob0_base, SEG_TTY_SIZE, + IntTab(0, IOX_MTTY_TGT_ID), false)); + maptab_iox.add(Segment("iox_seg_fbuf_0", SEG_FBF_BASE + iob0_base, SEG_FBF_SIZE, + IntTab(0, IOX_FBUF_TGT_ID), false)); + maptab_iox.add(Segment("iox_seg_bdev_0", SEG_IOC_BASE + iob0_base, SEG_IOC_SIZE, + IntTab(0, IOX_BDEV_TGT_ID), false)); + maptab_iox.add(Segment("iox_seg_mnic_0", SEG_NIC_BASE + iob0_base, SEG_NIC_SIZE, + IntTab(0, IOX_MNIC_TGT_ID), false)); + maptab_iox.add(Segment("iox_seg_cdma_0", SEG_CMA_BASE + iob0_base, SEG_CMA_SIZE, + IntTab(0, IOX_CDMA_TGT_ID), false)); + maptab_iox.add(Segment("iox_seg_iopi_0", SEG_PIC_BASE + iob0_base, SEG_PIC_SIZE, + IntTab(0, IOX_IOPI_TGT_ID), false)); + + if ( cluster_iob0 != cluster_iob1 ) + { + const uint64_t iob1_base = ((uint64_t)cluster_iob1) + << (vci_address_width - x_width - y_width); + + maptab_iox.add(Segment("iox_seg_mtty_1", SEG_TTY_BASE + iob1_base, SEG_TTY_SIZE, + IntTab(0, IOX_MTTY_TGT_ID), false)); + maptab_iox.add(Segment("iox_seg_fbuf_1", SEG_FBF_BASE + iob1_base, SEG_FBF_SIZE, + IntTab(0, IOX_FBUF_TGT_ID), false)); + maptab_iox.add(Segment("iox_seg_bdev_1", SEG_IOC_BASE + iob1_base, SEG_IOC_SIZE, + IntTab(0, IOX_BDEV_TGT_ID), false)); + maptab_iox.add(Segment("iox_seg_mnic_1", SEG_NIC_BASE + iob1_base, SEG_NIC_SIZE, + IntTab(0, IOX_MNIC_TGT_ID), false)); + maptab_iox.add(Segment("iox_seg_cdma_1", SEG_CMA_BASE + iob1_base, SEG_CMA_SIZE, + IntTab(0, IOX_CDMA_TGT_ID), false)); + maptab_iox.add(Segment("iox_seg_iopi_1", SEG_PIC_BASE + iob1_base, SEG_PIC_SIZE, + IntTab(0, IOX_IOPI_TGT_ID), false)); + } + + // If there is more than one cluster, external peripherals + // can access RAM through two segments (IOB0 / IOB1). + // As IOMMU is not activated, addresses are 40 bits (physical addresses), + // and the choice depends on address bit A[32]. + for (size_t x = 0; x < XMAX; x++) + { + for (size_t y = 0; y < YMAX ; y++) + { + const bool wti = true; + const bool cacheable = true; + + const uint64_t offset = ((uint64_t)cluster(x,y)) + << (vci_address_width-x_width-y_width); + + const uint64_t xicu_base = SEG_XCU_BASE + offset; + + if ( (y & 0x1) == 0 ) // use IOB0 + { + std::ostringstream sxcu0; + sxcu0 << "iox_seg_xcu0_" << x << "_" << y; + maptab_iox.add(Segment(sxcu0.str(), xicu_base, SEG_XCU_SIZE, + IntTab(0, IOX_IOB0_TGT_ID), not cacheable, wti)); + + std::ostringstream siob0; + siob0 << "iox_seg_ram0_" << x << "_" << y; + maptab_iox.add(Segment(siob0.str(), offset, SEG_XCU_BASE, + IntTab(0, IOX_IOB0_TGT_ID), not cacheable, not wti)); + } + else // USE IOB1 + { + std::ostringstream sxcu1; + sxcu1 << "iox_seg_xcu1_" << x << "_" << y; + maptab_iox.add(Segment(sxcu1.str(), xicu_base, SEG_XCU_SIZE, + IntTab(0, IOX_IOB1_TGT_ID), not cacheable, wti)); + + std::ostringstream siob1; + siob1 << "iox_seg_ram1_" << x << "_" << y; + maptab_iox.add(Segment(siob1.str(), offset, SEG_XCU_BASE, + IntTab(0, IOX_IOB1_TGT_ID), not cacheable, not wti)); + } + } + } + + // This define the mapping between the external initiators (SRCID) + // and the port index on the IOX local interconnect. + + maptab_iox.srcid_map( IntTab( 0, CDMA_LOCAL_SRCID ) , + IntTab( 0, IOX_CDMA_INI_ID ) ); + maptab_iox.srcid_map( IntTab( 0, BDEV_LOCAL_SRCID ) , + IntTab( 0, IOX_BDEV_INI_ID ) ); + maptab_iox.srcid_map( IntTab( 0, IOPI_LOCAL_SRCID ) , + IntTab( 0, IOX_IOPI_INI_ID ) ); + maptab_iox.srcid_map( IntTab( 0, IOX_IOB0_INI_ID ) , + IntTab( 0, IOX_IOB0_INI_ID ) ); + + if ( cluster_iob0 != cluster_iob1 ) + { + maptab_iox.srcid_map( IntTab( 0, IOX_IOB1_INI_ID ) , + IntTab( 0, IOX_IOB1_INI_ID ) ); + } + + std::cout << "IOX network " << maptab_iox << std::endl; + + //////////////////// + // Signals + /////////////////// + + sc_clock signal_clk("clk"); + sc_signal signal_resetn("resetn"); + + sc_signal signal_irq_false; + sc_signal signal_irq_bdev; + sc_signal signal_irq_mtty_rx; + sc_signal signal_irq_mnic_rx[NB_NIC_CHANNELS]; + sc_signal signal_irq_mnic_tx[NB_NIC_CHANNELS]; + sc_signal signal_irq_cdma[NB_CMA_CHANNELS]; + + // VCI signals for IOX network + VciSignals signal_vci_ini_iob0("signal_vci_ini_iob0"); + VciSignals signal_vci_ini_iob1("signal_vci_ini_iob1"); + VciSignals signal_vci_ini_bdev("signal_vci_ini_bdev"); + VciSignals signal_vci_ini_cdma("signal_vci_ini_cdma"); + VciSignals signal_vci_ini_iopi("signal_vci_ini_iopi"); + + VciSignals signal_vci_tgt_iob0("signal_vci_tgt_iob0"); + VciSignals signal_vci_tgt_iob1("signal_vci_tgt_iob1"); + VciSignals signal_vci_tgt_mtty("signal_vci_tgt_mtty"); + VciSignals signal_vci_tgt_fbuf("signal_vci_tgt_fbuf"); + VciSignals signal_vci_tgt_mnic("signal_vci_tgt_mnic"); + VciSignals signal_vci_tgt_bdev("signal_vci_tgt_bdev"); + VciSignals signal_vci_tgt_cdma("signal_vci_tgt_cdma"); + VciSignals signal_vci_tgt_iopi("signal_vci_ini_iopi"); + + // Horizontal inter-clusters INT network DSPIN + DspinSignals*** signal_dspin_int_cmd_h_inc = + alloc_elems >("signal_dspin_int_cmd_h_inc", XMAX-1, YMAX, 3); + DspinSignals*** signal_dspin_int_cmd_h_dec = + alloc_elems >("signal_dspin_int_cmd_h_dec", XMAX-1, YMAX, 3); + DspinSignals*** signal_dspin_int_rsp_h_inc = + alloc_elems >("signal_dspin_int_rsp_h_inc", XMAX-1, YMAX, 2); + DspinSignals*** signal_dspin_int_rsp_h_dec = + alloc_elems >("signal_dspin_int_rsp_h_dec", XMAX-1, YMAX, 2); + + // Vertical inter-clusters INT network DSPIN + DspinSignals*** signal_dspin_int_cmd_v_inc = + alloc_elems >("signal_dspin_int_cmd_v_inc", XMAX, YMAX-1, 3); + DspinSignals*** signal_dspin_int_cmd_v_dec = + alloc_elems >("signal_dspin_int_cmd_v_dec", XMAX, YMAX-1, 3); + DspinSignals*** signal_dspin_int_rsp_v_inc = + alloc_elems >("signal_dspin_int_rsp_v_inc", XMAX, YMAX-1, 2); + DspinSignals*** signal_dspin_int_rsp_v_dec = + alloc_elems >("signal_dspin_int_rsp_v_dec", XMAX, YMAX-1, 2); + + // Mesh boundaries INT network DSPIN + DspinSignals**** signal_dspin_false_int_cmd_in = + alloc_elems >("signal_dspin_false_int_cmd_in", XMAX, YMAX, 4, 3); + DspinSignals**** signal_dspin_false_int_cmd_out = + alloc_elems >("signal_dspin_false_int_cmd_out", XMAX, YMAX, 4, 3); + DspinSignals**** signal_dspin_false_int_rsp_in = + alloc_elems >("signal_dspin_false_int_rsp_in", XMAX, YMAX, 4, 2); + DspinSignals**** signal_dspin_false_int_rsp_out = + alloc_elems >("signal_dspin_false_int_rsp_out", XMAX, YMAX, 4, 2); + + + // Horizontal inter-clusters RAM network DSPIN + DspinSignals** signal_dspin_ram_cmd_h_inc = + alloc_elems >("signal_dspin_ram_cmd_h_inc", XMAX-1, YMAX); + DspinSignals** signal_dspin_ram_cmd_h_dec = + alloc_elems >("signal_dspin_ram_cmd_h_dec", XMAX-1, YMAX); + DspinSignals** signal_dspin_ram_rsp_h_inc = + alloc_elems >("signal_dspin_ram_rsp_h_inc", XMAX-1, YMAX); + DspinSignals** signal_dspin_ram_rsp_h_dec = + alloc_elems >("signal_dspin_ram_rsp_h_dec", XMAX-1, YMAX); + + // Vertical inter-clusters RAM network DSPIN + DspinSignals** signal_dspin_ram_cmd_v_inc = + alloc_elems >("signal_dspin_ram_cmd_v_inc", XMAX, YMAX-1); + DspinSignals** signal_dspin_ram_cmd_v_dec = + alloc_elems >("signal_dspin_ram_cmd_v_dec", XMAX, YMAX-1); + DspinSignals** signal_dspin_ram_rsp_v_inc = + alloc_elems >("signal_dspin_ram_rsp_v_inc", XMAX, YMAX-1); + DspinSignals** signal_dspin_ram_rsp_v_dec = + alloc_elems >("signal_dspin_ram_rsp_v_dec", XMAX, YMAX-1); + + // Mesh boundaries RAM network DSPIN + DspinSignals*** signal_dspin_false_ram_cmd_in = + alloc_elems >("signal_dspin_false_ram_cmd_in", XMAX, YMAX, 4); + DspinSignals*** signal_dspin_false_ram_cmd_out = + alloc_elems >("signal_dspin_false_ram_cmd_out", XMAX, YMAX, 4); + DspinSignals*** signal_dspin_false_ram_rsp_in = + alloc_elems >("signal_dspin_false_ram_rsp_in", XMAX, YMAX, 4); + DspinSignals*** signal_dspin_false_ram_rsp_out = + alloc_elems >("signal_dspin_false_ram_rsp_out", XMAX, YMAX, 4); + + //////////////////////////// + // Loader + //////////////////////////// + +#if USE_ALMOS + soclib::common::Loader loader(almos_bootloader_pathname, + almos_archinfo_pathname, + almos_kernel_pathname); +#else + soclib::common::Loader loader(soft_name); +#endif + + typedef soclib::common::GdbServer proc_iss; + proc_iss::set_loader(loader); + + //////////////////////////////////////// + // Instanciated Hardware Components + //////////////////////////////////////// + + std::cout << std::endl << "External Bus and Peripherals" << std::endl << std::endl; + + const size_t nb_iox_initiators = (cluster_iob0 != cluster_iob1) ? 5 : 4; + const size_t nb_iox_targets = (cluster_iob0 != cluster_iob1) ? 8 : 7; + + // IOX network + VciIoxNetwork* iox_network; + iox_network = new VciIoxNetwork( "iox_network", + maptab_iox, + nb_iox_targets, + nb_iox_initiators ); + + // Network Controller + VciMultiNic* mnic; + mnic = new VciMultiNic( "mnic", + IntTab(0, IOX_MNIC_TGT_ID), + maptab_iox, + NB_NIC_CHANNELS, + 0, // mac_4 address + 0, // mac_2 address + nic_rx_name, + nic_tx_name); + + // Frame Buffer + VciFrameBuffer* fbuf; + fbuf = new VciFrameBuffer( "fbuf", + IntTab(0, IOX_FBUF_TGT_ID), + maptab_iox, + FBUF_X_SIZE, FBUF_Y_SIZE ); + + // Block Device + // for AHCI + // std::vector filenames; + // filenames.push_back(disk_name); // one single disk + VciBlockDeviceTsar* bdev; + bdev = new VciBlockDeviceTsar( "bdev", + maptab_iox, + IntTab(0, BDEV_LOCAL_SRCID), + IntTab(0, IOX_BDEV_TGT_ID), + disk_name, + 512, // block size + 64, // burst size (bytes) + 0 ); // disk latency + + // Chained Buffer DMA controller + VciChbufDma* cdma; + cdma = new VciChbufDma( "cdma", + maptab_iox, + IntTab(0, CDMA_LOCAL_SRCID), + IntTab(0, IOX_CDMA_TGT_ID), + 64, // burst size (bytes) + 2*NB_NIC_CHANNELS ); + // Multi-TTY controller + std::vector vect_names; + for( size_t tid = 0 ; tid < NB_TTY_CHANNELS ; tid++ ) + { + std::ostringstream term_name; + term_name << "term" << tid; + vect_names.push_back(term_name.str().c_str()); + } + VciMultiTty* mtty; + mtty = new VciMultiTty( "mtty", + IntTab(0, IOX_MTTY_TGT_ID), + maptab_iox, + vect_names); + + // IOPIC + VciIopic* iopi; + iopi = new VciIopic( "iopi", + maptab_iox, + IntTab(0, IOPI_LOCAL_SRCID), + IntTab(0, IOX_IOPI_TGT_ID), + 32 ); // number of input HWI + // Clusters + TsarIobCluster* clusters[XMAX][YMAX]; + +#if USE_OPENMP +#pragma omp parallel + { +#pragma omp for +#endif + for(size_t i = 0; i < (XMAX * YMAX); i++) + { + size_t x = i / YMAX; + size_t y = i % YMAX; + +#if USE_OPENMP +#pragma omp critical + { +#endif + std::cout << std::endl; + std::cout << "Cluster_" << std::dec << x << "_" << y << std::endl; + std::cout << std::endl; + + const bool is_iob0 = (cluster(x,y) == cluster_iob0); + const bool is_iob1 = (cluster(x,y) == cluster_iob1); + const bool is_io_cluster = is_iob0 || is_iob1; + + const int iox_iob_ini_id = is_iob0 ? + IOX_IOB0_INI_ID : + IOX_IOB1_INI_ID ; + const int iox_iob_tgt_id = is_iob0 ? + IOX_IOB0_TGT_ID : + IOX_IOB1_TGT_ID ; + + std::ostringstream sc; + sc << "cluster_" << x << "_" << y; + clusters[x][y] = new TsarIobCluster + ( + sc.str().c_str(), + NB_PROCS_MAX, + NB_DMA_CHANNELS, + x, + y, + XMAX, + YMAX, + + maptab_int, + maptab_ram, + maptab_iox, + + x_width, + y_width, + vci_srcid_width - x_width - y_width, // l_id width, + + INT_MEMC_TGT_ID, + INT_XICU_TGT_ID, + INT_MDMA_TGT_ID, + INT_BROM_TGT_ID, + INT_IOBX_TGT_ID, + + INT_PROC_INI_ID, + INT_MDMA_INI_ID, + INT_IOBX_INI_ID, + + RAM_XRAM_TGT_ID, + + RAM_MEMC_INI_ID, + RAM_IOBX_INI_ID, + + is_io_cluster, + iox_iob_tgt_id, + iox_iob_ini_id, + + MEMC_WAYS, + MEMC_SETS, + L1_IWAYS, + L1_ISETS, + L1_DWAYS, + L1_DSETS, + XRAM_LATENCY, + XCU_NB_INPUTS, + + DISTRIBUTED_BOOT, + + loader, + + frozen_cycles, + debug_from, + debug_ok and (cluster(x,y) == debug_memc_id), + debug_ok and (cluster(x,y) == debug_proc_id), + debug_ok and debug_iob + ); + +#if USE_OPENMP + } // end critical +#endif + } // end for +#if USE_OPENMP + } +#endif + + std::cout << std::endl; + + /////////////////////////////////////////////////////////////////////////////// + // Net-list + /////////////////////////////////////////////////////////////////////////////// + + // IOX network connexion + iox_network->p_clk (signal_clk); + iox_network->p_resetn (signal_resetn); + iox_network->p_to_ini[IOX_IOB0_INI_ID] (signal_vci_ini_iob0); + iox_network->p_to_ini[IOX_BDEV_INI_ID] (signal_vci_ini_bdev); + iox_network->p_to_ini[IOX_CDMA_INI_ID] (signal_vci_ini_cdma); + iox_network->p_to_ini[IOX_IOPI_INI_ID] (signal_vci_ini_iopi); + + iox_network->p_to_tgt[IOX_IOB0_TGT_ID] (signal_vci_tgt_iob0); + iox_network->p_to_tgt[IOX_MTTY_TGT_ID] (signal_vci_tgt_mtty); + iox_network->p_to_tgt[IOX_FBUF_TGT_ID] (signal_vci_tgt_fbuf); + iox_network->p_to_tgt[IOX_MNIC_TGT_ID] (signal_vci_tgt_mnic); + iox_network->p_to_tgt[IOX_BDEV_TGT_ID] (signal_vci_tgt_bdev); + iox_network->p_to_tgt[IOX_CDMA_TGT_ID] (signal_vci_tgt_cdma); + iox_network->p_to_tgt[IOX_IOPI_TGT_ID] (signal_vci_tgt_iopi); + + if (cluster_iob0 != cluster_iob1) + { + iox_network->p_to_ini[IOX_IOB1_INI_ID] (signal_vci_ini_iob1); + iox_network->p_to_tgt[IOX_IOB1_TGT_ID] (signal_vci_tgt_iob1); + } + + // BDEV connexion + bdev->p_clk (signal_clk); + bdev->p_resetn (signal_resetn); + bdev->p_irq (signal_irq_bdev); + bdev->p_vci_target (signal_vci_tgt_bdev); + bdev->p_vci_initiator (signal_vci_ini_bdev); + + std::cout << " - BDEV connected" << std::endl; + + // FBUF connexion + fbuf->p_clk (signal_clk); + fbuf->p_resetn (signal_resetn); + fbuf->p_vci (signal_vci_tgt_fbuf); + + std::cout << " - FBUF connected" << std::endl; + + // MNIC connexion + mnic->p_clk (signal_clk); + mnic->p_resetn (signal_resetn); + mnic->p_vci (signal_vci_tgt_mnic); + for ( size_t i=0 ; ip_rx_irq[i] (signal_irq_mnic_rx[i]); + mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]); + } + + std::cout << " - MNIC connected" << std::endl; + + // MTTY connexion + mtty->p_clk (signal_clk); + mtty->p_resetn (signal_resetn); + mtty->p_vci (signal_vci_tgt_mtty); + mtty->p_irq[0] (signal_irq_mtty_rx); + + std::cout << " - MTTY connected" << std::endl; + + // CDMA connexion + cdma->p_clk (signal_clk); + cdma->p_resetn (signal_resetn); + cdma->p_vci_target (signal_vci_tgt_cdma); + cdma->p_vci_initiator (signal_vci_ini_cdma); + for ( size_t i=0 ; i<(NB_NIC_CHANNELS*2) ; i++) + { + cdma->p_irq[i] (signal_irq_cdma[i]); + } + + std::cout << " - CDMA connected" << std::endl; + + // IOPI connexion + iopi->p_clk (signal_clk); + iopi->p_resetn (signal_resetn); + iopi->p_vci_target (signal_vci_tgt_iopi); + iopi->p_vci_initiator (signal_vci_ini_iopi); + for ( size_t i=0 ; i<32 ; i++) + { + if (i < NB_NIC_CHANNELS) iopi->p_hwi[i] (signal_irq_mnic_rx[i]); + else if(i < 2 ) iopi->p_hwi[i] (signal_irq_false); + else if(i < 2+NB_NIC_CHANNELS) iopi->p_hwi[i] (signal_irq_mnic_tx[i-2]); + else if(i < 4 ) iopi->p_hwi[i] (signal_irq_false); + else if(i < 4+NB_CMA_CHANNELS) iopi->p_hwi[i] (signal_irq_cdma[i-4]); + else if(i < 8) iopi->p_hwi[i] (signal_irq_false); + else if(i == 8) iopi->p_hwi[i] (signal_irq_bdev); + else if(i == 9) iopi->p_hwi[i] (signal_irq_mtty_rx); + else iopi->p_hwi[i] (signal_irq_false); + } + + std::cout << " - IOPIC connected" << std::endl; + + + // IOB0 cluster connexion to IOX network + (*clusters[0][0]->p_vci_iob_iox_ini) (signal_vci_ini_iob0); + (*clusters[0][0]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob0); + + // IOB1 cluster connexion to IOX network + // (only when there is more than 1 cluster) + if ( cluster_iob0 != cluster_iob1 ) + { + (*clusters[XMAX-1][YMAX-1]->p_vci_iob_iox_ini) (signal_vci_ini_iob1); + (*clusters[XMAX-1][YMAX-1]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob1); + } + + // All clusters Clock & RESET connexions + for ( size_t x = 0; x < (XMAX); x++ ) + { + for (size_t y = 0; y < YMAX; y++) + { + clusters[x][y]->p_clk (signal_clk); + clusters[x][y]->p_resetn (signal_resetn); + } + } + + // Inter Clusters horizontal connections + if (XMAX > 1) + { + for (size_t x = 0; x < (XMAX-1); x++) + { + for (size_t y = 0; y < YMAX; y++) + { + for (size_t k = 0; k < 3; k++) + { + clusters[x][y]->p_dspin_int_cmd_out[EAST][k] (signal_dspin_int_cmd_h_inc[x][y][k]); + clusters[x+1][y]->p_dspin_int_cmd_in[WEST][k] (signal_dspin_int_cmd_h_inc[x][y][k]); + clusters[x][y]->p_dspin_int_cmd_in[EAST][k] (signal_dspin_int_cmd_h_dec[x][y][k]); + clusters[x+1][y]->p_dspin_int_cmd_out[WEST][k] (signal_dspin_int_cmd_h_dec[x][y][k]); + } + + for (size_t k = 0; k < 2; k++) + { + clusters[x][y]->p_dspin_int_rsp_out[EAST][k] (signal_dspin_int_rsp_h_inc[x][y][k]); + clusters[x+1][y]->p_dspin_int_rsp_in[WEST][k] (signal_dspin_int_rsp_h_inc[x][y][k]); + clusters[x][y]->p_dspin_int_rsp_in[EAST][k] (signal_dspin_int_rsp_h_dec[x][y][k]); + clusters[x+1][y]->p_dspin_int_rsp_out[WEST][k] (signal_dspin_int_rsp_h_dec[x][y][k]); + } + + clusters[x][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_ram_cmd_h_inc[x][y]); + clusters[x+1][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_ram_cmd_h_inc[x][y]); + clusters[x][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_ram_cmd_h_dec[x][y]); + clusters[x+1][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_ram_cmd_h_dec[x][y]); + clusters[x][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_ram_rsp_h_inc[x][y]); + clusters[x+1][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_ram_rsp_h_inc[x][y]); + clusters[x][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_ram_rsp_h_dec[x][y]); + clusters[x+1][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_ram_rsp_h_dec[x][y]); + } + } + } + + std::cout << std::endl << "Horizontal connections established" << std::endl; + + // Inter Clusters vertical connections + if (YMAX > 1) + { + for (size_t y = 0; y < (YMAX-1); y++) + { + for (size_t x = 0; x < XMAX; x++) + { + for (size_t k = 0; k < 3; k++) + { + clusters[x][y]->p_dspin_int_cmd_out[NORTH][k] (signal_dspin_int_cmd_v_inc[x][y][k]); + clusters[x][y+1]->p_dspin_int_cmd_in[SOUTH][k] (signal_dspin_int_cmd_v_inc[x][y][k]); + clusters[x][y]->p_dspin_int_cmd_in[NORTH][k] (signal_dspin_int_cmd_v_dec[x][y][k]); + clusters[x][y+1]->p_dspin_int_cmd_out[SOUTH][k] (signal_dspin_int_cmd_v_dec[x][y][k]); + } + + for (size_t k = 0; k < 2; k++) + { + clusters[x][y]->p_dspin_int_rsp_out[NORTH][k] (signal_dspin_int_rsp_v_inc[x][y][k]); + clusters[x][y+1]->p_dspin_int_rsp_in[SOUTH][k] (signal_dspin_int_rsp_v_inc[x][y][k]); + clusters[x][y]->p_dspin_int_rsp_in[NORTH][k] (signal_dspin_int_rsp_v_dec[x][y][k]); + clusters[x][y+1]->p_dspin_int_rsp_out[SOUTH][k] (signal_dspin_int_rsp_v_dec[x][y][k]); + } + + clusters[x][y]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_ram_cmd_v_inc[x][y]); + clusters[x][y+1]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_ram_cmd_v_inc[x][y]); + clusters[x][y]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_ram_cmd_v_dec[x][y]); + clusters[x][y+1]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_ram_cmd_v_dec[x][y]); + clusters[x][y]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_ram_rsp_v_inc[x][y]); + clusters[x][y+1]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_ram_rsp_v_inc[x][y]); + clusters[x][y]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_ram_rsp_v_dec[x][y]); + clusters[x][y+1]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_ram_rsp_v_dec[x][y]); + } + } + } + + std::cout << "Vertical connections established" << std::endl; + + // East & West boundary cluster connections + for (size_t y = 0; y < YMAX; y++) + { + for (size_t k = 0; k < 3; k++) + { + clusters[0][y]->p_dspin_int_cmd_in[WEST][k] (signal_dspin_false_int_cmd_in[0][y][WEST][k]); + clusters[0][y]->p_dspin_int_cmd_out[WEST][k] (signal_dspin_false_int_cmd_out[0][y][WEST][k]); + clusters[XMAX-1][y]->p_dspin_int_cmd_in[EAST][k] (signal_dspin_false_int_cmd_in[XMAX-1][y][EAST][k]); + clusters[XMAX-1][y]->p_dspin_int_cmd_out[EAST][k] (signal_dspin_false_int_cmd_out[XMAX-1][y][EAST][k]); + } + + for (size_t k = 0; k < 2; k++) + { + clusters[0][y]->p_dspin_int_rsp_in[WEST][k] (signal_dspin_false_int_rsp_in[0][y][WEST][k]); + clusters[0][y]->p_dspin_int_rsp_out[WEST][k] (signal_dspin_false_int_rsp_out[0][y][WEST][k]); + clusters[XMAX-1][y]->p_dspin_int_rsp_in[EAST][k] (signal_dspin_false_int_rsp_in[XMAX-1][y][EAST][k]); + clusters[XMAX-1][y]->p_dspin_int_rsp_out[EAST][k] (signal_dspin_false_int_rsp_out[XMAX-1][y][EAST][k]); + } + + clusters[0][y]->p_dspin_ram_cmd_in[WEST] (signal_dspin_false_ram_cmd_in[0][y][WEST]); + clusters[0][y]->p_dspin_ram_cmd_out[WEST] (signal_dspin_false_ram_cmd_out[0][y][WEST]); + clusters[0][y]->p_dspin_ram_rsp_in[WEST] (signal_dspin_false_ram_rsp_in[0][y][WEST]); + clusters[0][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_false_ram_rsp_out[0][y][WEST]); + + clusters[XMAX-1][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_false_ram_cmd_in[XMAX-1][y][EAST]); + clusters[XMAX-1][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_false_ram_cmd_out[XMAX-1][y][EAST]); + clusters[XMAX-1][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_false_ram_rsp_in[XMAX-1][y][EAST]); + clusters[XMAX-1][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_false_ram_rsp_out[XMAX-1][y][EAST]); + } + + std::cout << "East & West boundaries established" << std::endl; + + // North & South boundary clusters connections + for (size_t x = 0; x < XMAX; x++) + { + for (size_t k = 0; k < 3; k++) + { + clusters[x][0]->p_dspin_int_cmd_in[SOUTH][k] (signal_dspin_false_int_cmd_in[x][0][SOUTH][k]); + clusters[x][0]->p_dspin_int_cmd_out[SOUTH][k] (signal_dspin_false_int_cmd_out[x][0][SOUTH][k]); + clusters[x][YMAX-1]->p_dspin_int_cmd_in[NORTH][k] (signal_dspin_false_int_cmd_in[x][YMAX-1][NORTH][k]); + clusters[x][YMAX-1]->p_dspin_int_cmd_out[NORTH][k] (signal_dspin_false_int_cmd_out[x][YMAX-1][NORTH][k]); + } + + for (size_t k = 0; k < 2; k++) + { + clusters[x][0]->p_dspin_int_rsp_in[SOUTH][k] (signal_dspin_false_int_rsp_in[x][0][SOUTH][k]); + clusters[x][0]->p_dspin_int_rsp_out[SOUTH][k] (signal_dspin_false_int_rsp_out[x][0][SOUTH][k]); + clusters[x][YMAX-1]->p_dspin_int_rsp_in[NORTH][k] (signal_dspin_false_int_rsp_in[x][YMAX-1][NORTH][k]); + clusters[x][YMAX-1]->p_dspin_int_rsp_out[NORTH][k] (signal_dspin_false_int_rsp_out[x][YMAX-1][NORTH][k]); + } + + clusters[x][0]->p_dspin_ram_cmd_in[SOUTH] (signal_dspin_false_ram_cmd_in[x][0][SOUTH]); + clusters[x][0]->p_dspin_ram_cmd_out[SOUTH] (signal_dspin_false_ram_cmd_out[x][0][SOUTH]); + clusters[x][0]->p_dspin_ram_rsp_in[SOUTH] (signal_dspin_false_ram_rsp_in[x][0][SOUTH]); + clusters[x][0]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_false_ram_rsp_out[x][0][SOUTH]); + + clusters[x][YMAX-1]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_false_ram_cmd_in[x][YMAX-1][NORTH]); + clusters[x][YMAX-1]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_false_ram_cmd_out[x][YMAX-1][NORTH]); + clusters[x][YMAX-1]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_false_ram_rsp_in[x][YMAX-1][NORTH]); + clusters[x][YMAX-1]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_false_ram_rsp_out[x][YMAX-1][NORTH]); + } + + std::cout << "North & South boundaries established" << std::endl << std::endl; + + //////////////////////////////////////////////////////// + // Simulation + /////////////////////////////////////////////////////// + + sc_start(sc_core::sc_time(0, SC_NS)); + + signal_resetn = false; + signal_irq_false = false; + + // network boundaries signals + for (size_t x = 0; x < XMAX ; x++) + { + for (size_t y = 0; y < YMAX ; y++) + { + for (size_t a = 0; a < 4; a++) + { + for (size_t k = 0; k < 3; k++) + { + signal_dspin_false_int_cmd_in[x][y][a][k].write = false; + signal_dspin_false_int_cmd_in[x][y][a][k].read = true; + signal_dspin_false_int_cmd_out[x][y][a][k].write = false; + signal_dspin_false_int_cmd_out[x][y][a][k].read = true; + } + + for (size_t k = 0; k < 2; k++) + { + signal_dspin_false_int_rsp_in[x][y][a][k].write = false; + signal_dspin_false_int_rsp_in[x][y][a][k].read = true; + signal_dspin_false_int_rsp_out[x][y][a][k].write = false; + signal_dspin_false_int_rsp_out[x][y][a][k].read = true; + } + + signal_dspin_false_ram_cmd_in[x][y][a].write = false; + signal_dspin_false_ram_cmd_in[x][y][a].read = true; + signal_dspin_false_ram_cmd_out[x][y][a].write = false; + signal_dspin_false_ram_cmd_out[x][y][a].read = true; + + signal_dspin_false_ram_rsp_in[x][y][a].write = false; + signal_dspin_false_ram_rsp_in[x][y][a].read = true; + signal_dspin_false_ram_rsp_out[x][y][a].write = false; + signal_dspin_false_ram_rsp_out[x][y][a].read = true; + } + } + } + + sc_start(sc_core::sc_time(1, SC_NS)); + signal_resetn = true; + + + // simulation loop + struct timeval t1,t2; + gettimeofday(&t1, NULL); + + for (size_t n = 1; n < ncycles; n++) + { + // stats display + if( (n % 1000000) == 0) + { + gettimeofday(&t2, NULL); + + uint64_t ms1 = (uint64_t) t1.tv_sec * 1000ULL + + (uint64_t) t1.tv_usec / 1000; + uint64_t ms2 = (uint64_t) t2.tv_sec * 1000ULL + + (uint64_t) t2.tv_usec / 1000; + std::cerr << "### cycle = " << n + << " / frequency = " + << (double) 1000000 / (double) (ms2 - ms1) << "Khz" + << std::endl; + + gettimeofday(&t1, NULL); + } + + // Monitor a specific address for one L1 cache + // clusters[1][1]->proc[0]->cache_monitor(0x50090ULL); + + // Monitor a specific address for one L2 cache + // clusters[0][0]->memc->cache_monitor( 0x170000ULL); + + // Monitor a specific address for one XRAM + // if (n == 3000000) clusters[0][0]->xram->start_monitor( 0x170000ULL , 64); + + if (debug_ok and (n > debug_from) and (n % debug_period == 0)) + { + std::cout << "****************** cycle " << std::dec << n ; + std::cout << " ************************************************" << std::endl; + + // trace proc[debug_proc_id] + if ( debug_proc_id != 0xFFFFFFFF ) + { + size_t l = debug_proc_id % NB_PROCS_MAX ; + size_t cluster_xy = debug_proc_id / NB_PROCS_MAX ; + size_t x = cluster_xy >> 4; + size_t y = cluster_xy & 0xF; + + clusters[x][y]->proc[l]->print_trace(1); + std::ostringstream proc_signame; + proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; + clusters[x][y]->signal_int_vci_ini_proc[l].print_trace(proc_signame.str()); + + clusters[x][y]->xicu->print_trace(l); + std::ostringstream xicu_signame; + xicu_signame << "[SIG]XICU_" << x << "_" << y; + clusters[x][y]->signal_int_vci_tgt_xicu.print_trace(xicu_signame.str()); + +// clusters[x][y]->mdma->print_trace(); +// std::ostringstream mdma_signame; +// mdma_signame << "[SIG]MDMA_" << x << "_" << y; +// clusters[x][y]->signal_int_vci_tgt_mdma.print_trace(mdma_signame.str()); + + if( clusters[x][y]->signal_proc_it[l].read() ) + std::cout << "### IRQ_PROC_" << std::dec + << x << "_" << y << "_" << l << " ACTIVE" << std::endl; + } + + // trace memc[debug_memc_id] + if ( debug_memc_id != 0xFFFFFFFF ) + { + size_t x = debug_memc_id >> 4; + size_t y = debug_memc_id & 0xF; + + clusters[x][y]->memc->print_trace(0); + std::ostringstream smemc_tgt; + smemc_tgt << "[SIG]MEMC_TGT_" << x << "_" << y; + clusters[x][y]->signal_int_vci_tgt_memc.print_trace(smemc_tgt.str()); + std::ostringstream smemc_ini; + smemc_ini << "[SIG]MEMC_INI_" << x << "_" << y; + clusters[x][y]->signal_ram_vci_ini_memc.print_trace(smemc_ini.str()); + + clusters[x][y]->xram->print_trace(); + std::ostringstream sxram_tgt; + sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y; + clusters[x][y]->signal_ram_vci_tgt_xram.print_trace(sxram_tgt.str()); + } + + + // trace XRAM and XRAM network routers in cluster[debug_xram_id] + if ( debug_xram_id != 0xFFFFFFFF ) + { + size_t x = debug_xram_id >> 4; + size_t y = debug_xram_id & 0xF; + + clusters[x][y]->xram->print_trace(); + std::ostringstream sxram_tgt; + sxram_tgt << "[SIG]XRAM_TGT_" << x << "_" << y; + clusters[x][y]->signal_ram_vci_tgt_xram.print_trace(sxram_tgt.str()); + + clusters[x][y]->ram_router_cmd->print_trace(); + clusters[x][y]->ram_router_rsp->print_trace(); + } + + // trace iob, iox and external peripherals + if ( debug_iob ) + { + clusters[0][0]->iob->print_trace(); + clusters[XMAX-1][YMAX-1]->iob->print_trace(); +// clusters[0][0]->signal_int_vci_tgt_iobx.print_trace( "[SIG]IOB0_INT_TGT"); +// clusters[0][0]->signal_int_vci_ini_iobx.print_trace( "[SIG]IOB0_INT_INI"); +// clusters[0][0]->signal_ram_vci_ini_iobx.print_trace( "[SIG]IOB0_RAM_INI"); + + signal_vci_ini_iob0.print_trace("[SIG]IOB0_IOX_INI"); + signal_vci_tgt_iob0.print_trace("[SIG]IOB0_IOX_TGT"); + +// cdma->print_trace(); +// signal_vci_tgt_cdma.print_trace("[SIG]IOX_CDMA_TGT"); +// signal_vci_ini_cdma.print_trace("[SIG]IOX_CDMA_INI"); + +// mtty->print_trace(); +// signal_vci_tgt_mtty.print_trace("[SIG]IOX_MTTY_TGT"); + + bdev->print_trace(); + signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT"); + signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); + + mnic->print_trace(); + signal_vci_tgt_mnic.print_trace("[SIG]MNIC_TGT"); + +// fbuf->print_trace(); +// signal_vci_tgt_fbuf.print_trace("[SIG]FBUF"); + + iopi->print_trace(); + signal_vci_ini_iopi.print_trace("[SIG]IOPI_INI"); + signal_vci_tgt_iopi.print_trace("[SIG]IOPI_TGT"); + iox_network->print_trace(); + + // interrupts + if (signal_irq_bdev) std::cout << "### IRQ_BDEV ACTIVE" << std::endl; + if (signal_irq_mtty_rx) std::cout << "### IRQ_MTTY ACTIVE" << std::endl; + if (signal_irq_mnic_rx[0]) std::cout << "### IRQ_MNIC_RX[0] ACTIVE" << std::endl; + if (signal_irq_mnic_rx[1]) std::cout << "### IRQ_MNIC_RX[1] ACTIVE" << std::endl; + if (signal_irq_mnic_tx[0]) std::cout << "### IRQ_MNIC_TX[0] ACTIVE" << std::endl; + if (signal_irq_mnic_tx[1]) std::cout << "### IRQ_MNIC_TX[1] ACTIVE" << std::endl; + } + } + + sc_start(sc_core::sc_time(1, SC_NS)); + } + return EXIT_SUCCESS; +} + +int sc_main (int argc, char *argv[]) +{ + try { + return _main(argc, argv); + } catch (std::exception &e) { + std::cout << e.what() << std::endl; + } catch (...) { + std::cout << "Unknown exception occured" << std::endl; + throw; + } + return 1; +} + + +// Local Variables: +// tab-width: 3 +// c-basic-offset: 3 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 + + + Index: /branches/fault_tolerance/platforms/tsar_generic_iob/top.desc =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_iob/top.desc (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_iob/top.desc (revision 724) @@ -0,0 +1,86 @@ + +# -*- python -*- + +# VCI parameters +vci_cell_size_int = 4 +vci_cell_size_ext = 8 + +vci_plen_size = 8 +vci_addr_size = 40 +vci_rerror_size = 1 +vci_clen_size = 1 +vci_rflag_size = 1 +vci_srcid_size = 14 +vci_pktid_size = 4 +vci_trdid_size = 4 +vci_wrplen_size = 1 + +# internal DSPIN network parameters +int_dspin_cmd_flit_size = 39 +int_dspin_rsp_flit_size = 32 + +# external DSPIN network parameters +ram_dspin_cmd_flit_size = 64 +ram_dspin_rsp_flit_size = 64 + +todo = Platform('caba', 'top.cpp', + + uses = [ + # cluster + Uses('caba:tsar_iob_cluster', + vci_data_width_int = vci_cell_size_int, + vci_data_width_ext = vci_cell_size_ext, + dspin_int_cmd_width = int_dspin_cmd_flit_size, + dspin_int_rsp_width = int_dspin_rsp_flit_size, + dspin_ram_cmd_width = ram_dspin_cmd_flit_size, + dspin_ram_rsp_width = ram_dspin_rsp_flit_size), + + # IOX Network + Uses('caba:vci_iox_network', + cell_size = vci_cell_size_ext), + + # ROM + Uses('caba:vci_simple_rom', + cell_size = vci_cell_size_ext), + + # Frame Buffer + Uses('caba:vci_framebuffer', + cell_size = vci_cell_size_ext), + + # Block Device + Uses('caba:vci_block_device_tsar', + cell_size = vci_cell_size_ext), + + # NIC + Uses('caba:vci_multi_nic', + cell_size = vci_cell_size_ext), + + # Chained DMA + Uses('caba:vci_chbuf_dma', + cell_size = vci_cell_size_ext), + + # TTY + Uses('caba:vci_multi_tty', + cell_size = vci_cell_size_ext), + + # IOPIC + Uses('caba:vci_iopic', + cell_size = vci_cell_size_ext), + + Uses('common:elf_file_loader'), + Uses('common:plain_file_loader'), + ], + + # default VCI parameters (global variables) + cell_size = vci_cell_size_int, + plen_size = vci_plen_size, + addr_size = vci_addr_size, + rerror_size = vci_rerror_size, + clen_size = vci_clen_size, + rflag_size = vci_rflag_size, + srcid_size = vci_srcid_size, + pktid_size = vci_pktid_size, + trdid_size = vci_trdid_size, + wrplen_size = vci_wrplen_size, + +) Index: /branches/fault_tolerance/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd (revision 724) @@ -0,0 +1,136 @@ + +# -*- python -*- + +Module('caba:tsar_iob_cluster', + classname = 'soclib::caba::TsarIobCluster', + + tmpl_parameters = [ + parameter.Module('vci_param_int', default = 'caba:vci_param', + cell_size = parameter.Reference('vci_data_width_int')), + parameter.Module('vci_param_ext', default = 'caba:vci_param', + cell_size = parameter.Reference('vci_data_width_ext')), + parameter.Int('dspin_int_cmd_width'), + parameter.Int('dspin_int_rsp_width'), + parameter.Int('dspin_ram_cmd_width'), + parameter.Int('dspin_ram_rsp_width'), + ], + + header_files = [ + '../source/include/tsar_iob_cluster.h', + ], + + implementation_files = [ + '../source/src/tsar_iob_cluster.cpp', + ], + + uses = [ + Uses('caba:base_module'), + Uses('common:mapping_table'), + Uses('common:iss2'), + Uses('common:elf_file_loader'), + + # internal network components + Uses('caba:vci_cc_vcache_wrapper', + cell_size = parameter.Reference('vci_data_width_int'), + dspin_in_width = parameter.Reference('dspin_int_cmd_width'), + dspin_out_width = parameter.Reference('dspin_int_rsp_width'), + iss_t = 'common:gdb_iss', + gdb_iss_t = 'common:mips32el'), + + Uses('caba:vci_mem_cache', + memc_cell_size_int = parameter.Reference('vci_data_width_int'), + memc_cell_size_ext = parameter.Reference('vci_data_width_ext'), + dspin_in_width = parameter.Reference('dspin_int_rsp_width'), + dspin_out_width = parameter.Reference('dspin_int_cmd_width')), + + Uses('caba:vci_xicu', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_multi_dma', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_simple_rom', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_local_crossbar', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:dspin_local_crossbar', + flit_width = parameter.Reference('dspin_int_cmd_width')), + + Uses('caba:dspin_local_crossbar', + flit_width = parameter.Reference('dspin_int_rsp_width')), + + Uses('caba:dspin_local_crossbar', + flit_width = parameter.Reference('dspin_ram_cmd_width')), + + Uses('caba:dspin_local_crossbar', + flit_width = parameter.Reference('dspin_ram_rsp_width')), + + Uses('caba:vci_dspin_initiator_wrapper', + cell_size = parameter.Reference('vci_data_width_int'), + dspin_cmd_width = parameter.Reference('dspin_int_cmd_width'), + dspin_rsp_width = parameter.Reference('dspin_int_rsp_width')), + + Uses('caba:vci_dspin_target_wrapper', + cell_size = parameter.Reference('vci_data_width_int'), + dspin_cmd_width = parameter.Reference('dspin_int_cmd_width'), + dspin_rsp_width = parameter.Reference('dspin_int_rsp_width')), + + Uses('caba:virtual_dspin_router', + flit_width = parameter.Reference('dspin_int_cmd_width')), + + Uses('caba:virtual_dspin_router', + flit_width = parameter.Reference('dspin_int_rsp_width')), + + # RAM network components + Uses('caba:vci_dspin_initiator_wrapper', + cell_size = parameter.Reference('vci_data_width_ext'), + dspin_cmd_width = parameter.Reference('dspin_ram_cmd_width'), + dspin_rsp_width = parameter.Reference('dspin_ram_rsp_width')), + + Uses('caba:vci_dspin_target_wrapper', + cell_size = parameter.Reference('vci_data_width_ext'), + dspin_cmd_width = parameter.Reference('dspin_ram_cmd_width'), + dspin_rsp_width = parameter.Reference('dspin_ram_rsp_width')), + + Uses('caba:dspin_router', + flit_width = parameter.Reference('dspin_ram_cmd_width')), + + Uses('caba:dspin_router', + flit_width = parameter.Reference('dspin_ram_rsp_width')), + + Uses('caba:vci_simple_ram', + cell_size = parameter.Reference('vci_data_width_ext')), + + # IOX network components + Uses('caba:vci_io_bridge', + iob_cell_size_int = parameter.Reference('vci_data_width_int'), + iob_cell_size_ext = parameter.Reference('vci_data_width_ext')), + ], + + ports = [ + Port('caba:bit_in', 'p_resetn', auto = 'resetn'), + Port('caba:clock_in', 'p_clk', auto = 'clock'), + + Port('caba:dspin_output', 'p_int_cmd_out', [4, 3], + dspin_data_size = parameter.Reference('dspin_int_cmd_width')), + Port('caba:dspin_input', 'p_int_cmd_in', [4, 3], + dspin_data_size = parameter.Reference('dspin_int_cmd_width')), + Port('caba:dspin_output', 'p_int_rsp_out', [4, 2], + dspin_data_size = parameter.Reference('dspin_int_rsp_width')), + Port('caba:dspin_input', 'p_int_rsp_in', [4, 2], + dspin_data_size = parameter.Reference('dspin_int_rsp_width')), + + Port('caba:dspin_output', 'p_ram_cmd_out', [4], + dspin_data_size = parameter.Reference('dspin_ram_cmd_width')), + Port('caba:dspin_input', 'p_ram_cmd_in', [4], + dspin_data_size = parameter.Reference('dspin_ram_cmd_width')), + Port('caba:dspin_output', 'p_ram_rsp_out', [4], + dspin_data_size = parameter.Reference('dspin_ram_rsp_width')), + Port('caba:dspin_input', 'p_ram_rsp_in', [4], + dspin_data_size = parameter.Reference('dspin_ram_rsp_width')), + ], +) + + Index: /branches/fault_tolerance/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h (revision 724) @@ -0,0 +1,265 @@ +////////////////////////////////////////////////////////////////////////////// +// File: tsar_iob_cluster.h +// Author: Alain Greiner +// Copyright: UPMC/LIP6 +// Date : april 2013 +// This program is released under the GNU public license +////////////////////////////////////////////////////////////////////////////// + +#ifndef SOCLIB_CABA_TSAR_IOB_CLUSTER_H +#define SOCLIB_CABA_TSAR_IOB_CLUSTER_H + +#include +#include +#include +#include +#include +#include + +#include "gdbserver.h" +#include "mapping_table.h" +#include "mips32.h" +#include "vci_simple_ram.h" +#include "vci_xicu.h" +#include "vci_local_crossbar.h" +#include "dspin_local_crossbar.h" +#include "vci_dspin_initiator_wrapper.h" +#include "vci_dspin_target_wrapper.h" +#include "dspin_router.h" +#include "virtual_dspin_router.h" +#include "vci_multi_dma.h" +#include "vci_mem_cache.h" +#include "vci_cc_vcache_wrapper.h" +#include "vci_io_bridge.h" +#include "vci_simple_rom.h" + +namespace soclib { namespace caba { + +/////////////////////////////////////////////////////////////////////////// +template +class TsarIobCluster +/////////////////////////////////////////////////////////////////////////// + : public soclib::caba::BaseModule +{ + + public: + + // Ports + sc_in p_clk; + sc_in p_resetn; + + // Thes two ports are used to connect IOB to IOX nework in top cell + soclib::caba::VciInitiator* p_vci_iob_iox_ini; + soclib::caba::VciTarget* p_vci_iob_iox_tgt; + + // These arrays of ports are used to connect the INT & RAM networks in top cell + soclib::caba::DspinOutput** p_dspin_int_cmd_out; + soclib::caba::DspinInput** p_dspin_int_cmd_in; + soclib::caba::DspinOutput** p_dspin_int_rsp_out; + soclib::caba::DspinInput** p_dspin_int_rsp_in; + + soclib::caba::DspinOutput* p_dspin_ram_cmd_out; + soclib::caba::DspinInput* p_dspin_ram_cmd_in; + soclib::caba::DspinOutput* p_dspin_ram_rsp_out; + soclib::caba::DspinInput* p_dspin_ram_rsp_in; + + // interrupt signals + sc_signal signal_false; + sc_signal signal_proc_it[8]; + sc_signal signal_irq_mdma[8]; + sc_signal signal_irq_memc; + + // INT network DSPIN signals between DSPIN routers and DSPIN local_crossbars + DspinSignals signal_int_dspin_cmd_l2g_d; + DspinSignals signal_int_dspin_cmd_g2l_d; + DspinSignals signal_int_dspin_m2p_l2g_c; + DspinSignals signal_int_dspin_m2p_g2l_c; + DspinSignals signal_int_dspin_clack_l2g_c; + DspinSignals signal_int_dspin_clack_g2l_c; + DspinSignals signal_int_dspin_rsp_l2g_d; + DspinSignals signal_int_dspin_rsp_g2l_d; + DspinSignals signal_int_dspin_p2m_l2g_c; + DspinSignals signal_int_dspin_p2m_g2l_c; + + // INT network VCI signals between VCI components and VCI local crossbar + VciSignals signal_int_vci_ini_proc[8]; + VciSignals signal_int_vci_ini_mdma; + VciSignals signal_int_vci_ini_iobx; + + VciSignals signal_int_vci_tgt_memc; + VciSignals signal_int_vci_tgt_xicu; + VciSignals signal_int_vci_tgt_mdma; + VciSignals signal_int_vci_tgt_brom; + VciSignals signal_int_vci_tgt_iobx; + + VciSignals signal_int_vci_l2g; + VciSignals signal_int_vci_g2l; + + // Coherence DSPIN signals between DSPIN local crossbars and CC components + DspinSignals signal_int_dspin_m2p_memc; + DspinSignals signal_int_dspin_clack_memc; + DspinSignals signal_int_dspin_p2m_memc; + DspinSignals signal_int_dspin_m2p_proc[8]; + DspinSignals signal_int_dspin_clack_proc[8]; + DspinSignals signal_int_dspin_p2m_proc[8]; + + // RAM network VCI signals between VCI components and VCI/DSPIN wrappers + VciSignals signal_ram_vci_ini_memc; + VciSignals signal_ram_vci_ini_iobx; + VciSignals signal_ram_vci_tgt_xram; + + // RAM network DSPIN signals between VCI/DSPIN wrappers, RAM dspin crossbar + // and routers + DspinSignals signal_ram_dspin_cmd_xram_t; + DspinSignals signal_ram_dspin_rsp_xram_t; + DspinSignals signal_ram_dspin_cmd_memc_i; + DspinSignals signal_ram_dspin_rsp_memc_i; + DspinSignals signal_ram_dspin_cmd_iob_i; + DspinSignals signal_ram_dspin_rsp_iob_i; + DspinSignals signal_ram_dspin_cmd_xbar; + DspinSignals signal_ram_dspin_rsp_xbar; + DspinSignals signal_ram_dspin_cmd_false; + DspinSignals signal_ram_dspin_rsp_false; + + ////////////////////////////////////// + // Hardwate Components (pointers) + ////////////////////////////////////// + VciCcVCacheWrapper >* proc[8]; + + VciMemCache* memc; + + VciDspinInitiatorWrapper* memc_ram_wi; + + VciXicu* xicu; + + VciMultiDma* mdma; + + VciSimpleRom* brom; + + VciLocalCrossbar* int_xbar_d; + + VciDspinInitiatorWrapper* int_wi_gate_d; + + VciDspinTargetWrapper* int_wt_gate_d; + + DspinLocalCrossbar* int_xbar_m2p_c; + DspinLocalCrossbar* int_xbar_p2m_c; + DspinLocalCrossbar* int_xbar_clack_c; + + VirtualDspinRouter* int_router_cmd; + VirtualDspinRouter* int_router_rsp; + + VciSimpleRam* xram; + + VciDspinTargetWrapper* xram_ram_wt; + + DspinRouter* ram_router_cmd; + DspinRouter* ram_router_rsp; + + DspinLocalCrossbar* ram_xbar_cmd; + DspinLocalCrossbar* ram_xbar_rsp; + + + // IO Network Components (not instanciated in all clusters) + + VciIoBridge* iob; + + VciDspinInitiatorWrapper* iob_ram_wi; + + // cluster constructor + TsarIobCluster( sc_module_name insname, + size_t nb_procs, + size_t nb_dmas, + size_t x, // x coordinate + size_t y, // y coordinate + size_t xmax, + size_t ymax, + + const soclib::common::MappingTable &mt_int, + const soclib::common::MappingTable &mt_ext, + const soclib::common::MappingTable &mt_iox, + + size_t x_width, // x field bits + size_t y_width, // y field bits + size_t l_width, // l field bits + + size_t int_memc_tgt_id, + size_t int_xicu_tgt_id, + size_t int_mdma_tgt_id, + size_t int_brom_tgt_id, + size_t int_iobx_tgt_id, + size_t int_proc_ini_id, + size_t int_mdma_ini_id, + size_t int_iobx_ini_id, + + size_t ram_xram_tgt_id, + size_t ram_memc_ini_id, + size_t ram_iobx_ini_id, + + bool is_io, + size_t iox_iobx_tgt_id, + size_t iox_iobx_ini_id, + + size_t memc_ways, + size_t memc_sets, + size_t l1_i_ways, + size_t l1_i_sets, + size_t l1_d_ways, + size_t l1_d_sets, + size_t xram_latency, + size_t xcu_nb_inputs, + + bool distboot, + + const Loader &loader, // loader for XRAM + + uint32_t frozen_cycles, + uint32_t start_debug_cycle, + bool memc_debug_ok, + bool proc_debug_ok, + bool iob0_debug_ok ); + + protected: + + SC_HAS_PROCESS(TsarIobCluster); + + void init(); + + +}; + +}} + +#endif + +// Local Variables: +// tab-width: 3 +// c-basic-offset: 3 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 +// Index: /branches/fault_tolerance/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp (revision 724) @@ -0,0 +1,663 @@ +////////////////////////////////////////////////////////////////////////////// +// File: tsar_iob_cluster.cpp +// Author: Alain Greiner +// Copyright: UPMC/LIP6 +// Date : april 2013 +// This program is released under the GNU public license +////////////////////////////////////////////////////////////////////////////// +// Cluster(0,0) & Cluster(xmax-1,ymax-1) contains the IOB0 & IOB1 components. +// These two clusters contain 6 extra components: +// - 1 vci_io_bridge (connected to the 3 networks. +// - 3 vci_dspin_wrapper for the IOB. +// - 2 dspin_local_crossbar for commands and responses. +////////////////////////////////////////////////////////////////////////////// + +#include "../include/tsar_iob_cluster.h" + +#define tmpl(x) \ + template\ + x TsarIobCluster<\ + vci_param_int , vci_param_ext,\ + dspin_int_cmd_width, dspin_int_rsp_width,\ + dspin_ram_cmd_width, dspin_ram_rsp_width> + +namespace soclib { namespace caba { + +////////////////////////////////////////////////////////////////////////// +// Constructor +////////////////////////////////////////////////////////////////////////// +tmpl(/**/)::TsarIobCluster( +////////////////////////////////////////////////////////////////////////// + sc_module_name insname, + size_t nb_procs, + size_t nb_dmas, + size_t x_id, + size_t y_id, + size_t xmax, + size_t ymax, + + const soclib::common::MappingTable &mt_int, + const soclib::common::MappingTable &mt_ram, + const soclib::common::MappingTable &mt_iox, + + size_t x_width, + size_t y_width, + size_t l_width, + + size_t int_memc_tgt_id, // local index + size_t int_xicu_tgt_id, // local index + size_t int_mdma_tgt_id, // local index + size_t int_brom_tgt_id, // local index + size_t int_iobx_tgt_id, // local index + + size_t int_proc_ini_id, // local index + size_t int_mdma_ini_id, // local index + size_t int_iobx_ini_id, // local index + + size_t ram_xram_tgt_id, // local index + size_t ram_memc_ini_id, // local index + size_t ram_iobx_ini_id, // local index + + bool is_io, // is IO cluster (IOB)? + size_t iox_iobx_tgt_id, // local_index + size_t iox_iobx_ini_id, // local index + + size_t memc_ways, + size_t memc_sets, + size_t l1_i_ways, + size_t l1_i_sets, + size_t l1_d_ways, + size_t l1_d_sets, + size_t xram_latency, + size_t xcu_nb_inputs, + + bool distboot, + + const Loader &loader, + + uint32_t frozen_cycles, + uint32_t debug_start_cycle, + bool memc_debug_ok, + bool proc_debug_ok, + bool iob_debug_ok ) + : soclib::caba::BaseModule(insname), + p_clk("clk"), + p_resetn("resetn") +{ + assert( (x_id < xmax) and (y_id < ymax) and "Illegal cluster coordinates"); + + size_t cluster_id = (x_id<<4) + y_id; + + // Vectors of DSPIN ports for inter-cluster communications + p_dspin_int_cmd_in = alloc_elems >("p_int_cmd_in", 4, 3); + p_dspin_int_cmd_out = alloc_elems >("p_int_cmd_out", 4, 3); + p_dspin_int_rsp_in = alloc_elems >("p_int_rsp_in", 4, 2); + p_dspin_int_rsp_out = alloc_elems >("p_int_rsp_out", 4, 2); + + p_dspin_ram_cmd_in = alloc_elems >("p_ext_cmd_in", 4); + p_dspin_ram_cmd_out = alloc_elems >("p_ext_cmd_out", 4); + p_dspin_ram_rsp_in = alloc_elems >("p_ext_rsp_in", 4); + p_dspin_ram_rsp_out = alloc_elems >("p_ext_rsp_out", 4); + + // VCI ports from IOB to IOX network (only in IO clusters) + if ( is_io ) + { + p_vci_iob_iox_ini = new soclib::caba::VciInitiator; + p_vci_iob_iox_tgt = new soclib::caba::VciTarget; + } + + ///////////////////////////////////////////////////////////////////////////// + // Hardware components + ///////////////////////////////////////////////////////////////////////////// + + //////////// PROCS + for (size_t p = 0; p < nb_procs; p++) + { + std::ostringstream s_proc; + s_proc << "proc_" << x_id << "_" << y_id << "_" << p; + proc[p] = new VciCcVCacheWrapper >( + s_proc.str().c_str(), + cluster_id*nb_procs + p, // GLOBAL PROC_ID + mt_int, // Mapping Table INT network + IntTab(cluster_id,p), // SRCID + (cluster_id << l_width) + p, // CC_GLOBAL_ID + 8, // ITLB ways + 8, // ITLB sets + 8, // DTLB ways + 8, // DTLB sets + l1_i_ways, l1_i_sets, 16, // ICACHE size + l1_d_ways, l1_d_sets, 16, // DCACHE size + 4, // WBUF nlines + 4, // WBUF nwords + x_width, + y_width, + frozen_cycles, // max frozen cycles + debug_start_cycle, + proc_debug_ok); + + // initialize physical address extension with cluster ID when using + // distributed boot + if (distboot) + { + proc[p]->set_dcache_paddr_ext_reset(cluster_id); + proc[p]->set_icache_paddr_ext_reset(cluster_id); + } + } + + /////////// MEMC + std::ostringstream s_memc; + s_memc << "memc_" << x_id << "_" << y_id; + memc = new VciMemCache( + s_memc.str().c_str(), + mt_int, // Mapping Table INT network + mt_ram, // Mapping Table RAM network + IntTab(cluster_id, ram_memc_ini_id), // SRCID RAM network + IntTab(cluster_id, int_memc_tgt_id), // TGTID INT network + x_width, // number of bits for x coordinate + y_width, // number of bits for y coordinate + memc_ways, memc_sets, 16, // CACHE SIZE + 3, // MAX NUMBER OF COPIES + 4096, // HEAP SIZE + 8, // TRANSACTION TABLE DEPTH + 8, // UPDATE TABLE DEPTH + 8, // INVALIDATE TABLE DEPTH + debug_start_cycle, + memc_debug_ok ); + + std::ostringstream s_wi_memc; + s_wi_memc << "memc_wi_" << x_id << "_" << y_id; + memc_ram_wi = new VciDspinInitiatorWrapper( + s_wi_memc.str().c_str(), + x_width + y_width + l_width); + + /////////// XICU + std::ostringstream s_xicu; + s_xicu << "xicu_" << x_id << "_" << y_id; + xicu = new VciXicu( + s_xicu.str().c_str(), + mt_int, // mapping table INT network + IntTab(cluster_id, int_xicu_tgt_id), // TGTID direct space + xcu_nb_inputs, // number of timer IRQs + xcu_nb_inputs, // number of hard IRQs + xcu_nb_inputs, // number of soft IRQs + 16); // number of output IRQs + + //////////// MDMA + std::ostringstream s_mdma; + s_mdma << "mdma_" << x_id << "_" << y_id; + mdma = new VciMultiDma( + s_mdma.str().c_str(), + mt_int, + IntTab(cluster_id, nb_procs), // SRCID + IntTab(cluster_id, int_mdma_tgt_id), // TGTID + 64, // burst size + nb_dmas); // number of IRQs + + /////////// DISTRIBUTED BOOT ROM + std::ostringstream s_brom; + s_brom << "brom_" << x_id << "_" << y_id; + brom = new VciSimpleRom( + s_brom.str().c_str(), + IntTab(cluster_id, int_brom_tgt_id), + mt_int, + loader, + x_width + y_width); // msb drop bits + + /////////// Direct LOCAL_XBAR(S) + size_t nb_direct_initiators = is_io ? nb_procs + 2 : nb_procs + 1; + size_t nb_direct_targets = is_io ? 5 : 4; + + std::ostringstream s_int_xbar_d; + s_int_xbar_d << "int_xbar_cmd_d_" << x_id << "_" << y_id; + int_xbar_d = new VciLocalCrossbar( + s_int_xbar_d.str().c_str(), + mt_int, // mapping table + cluster_id, // cluster id + nb_direct_initiators, // number of local initiators + nb_direct_targets, // number of local targets + 0 ); // default target + + std::ostringstream s_int_dspin_ini_wrapper_gate_d; + s_int_dspin_ini_wrapper_gate_d << "int_dspin_ini_wrapper_gate_d_" + << x_id << "_" << y_id; + int_wi_gate_d = new VciDspinInitiatorWrapper( + s_int_dspin_ini_wrapper_gate_d.str().c_str(), + x_width + y_width + l_width); + + std::ostringstream s_int_dspin_tgt_wrapper_gate_d; + s_int_dspin_tgt_wrapper_gate_d << "int_dspin_tgt_wrapper_gate_d_" + << x_id << "_" << y_id; + int_wt_gate_d = new VciDspinTargetWrapper( + s_int_dspin_tgt_wrapper_gate_d.str().c_str(), + x_width + y_width + l_width); + + //////////// Coherence LOCAL_XBAR(S) + std::ostringstream s_int_xbar_m2p_c; + s_int_xbar_m2p_c << "int_xbar_m2p_c_" << x_id << "_" << y_id; + int_xbar_m2p_c = new DspinLocalCrossbar( + s_int_xbar_m2p_c.str().c_str(), + mt_int, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, l_width, // several dests + 1, // number of local sources + nb_procs, // number of local dests + 2, 2, // fifo depths + true, // pseudo CMD + false, // no routing table + true ); // broacast + + std::ostringstream s_int_xbar_p2m_c; + s_int_xbar_p2m_c << "int_xbar_p2m_c_" << x_id << "_" << y_id; + int_xbar_p2m_c = new DspinLocalCrossbar( + s_int_xbar_p2m_c.str().c_str(), + mt_int, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, 0, // only one dest + nb_procs, // number of local sources + 1, // number of local dests + 2, 2, // fifo depths + false, // pseudo RSP + false, // no routing table + false ); // no broacast + + std::ostringstream s_int_xbar_clack_c; + s_int_xbar_clack_c << "int_xbar_clack_c_" << x_id << "_" << y_id; + int_xbar_clack_c = new DspinLocalCrossbar( + s_int_xbar_clack_c.str().c_str(), + mt_int, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, l_width, + 1, // number of local sources + nb_procs, // number of local targets + 1, 1, // fifo depths + true, // CMD + false, // no routing table + false); // broadcast + + ////////////// INT ROUTER(S) + std::ostringstream s_int_router_cmd; + s_int_router_cmd << "router_cmd_" << x_id << "_" << y_id; + int_router_cmd = new VirtualDspinRouter( + s_int_router_cmd.str().c_str(), + x_id,y_id, // coordinate in the mesh + x_width, y_width, // x & y fields width + 3, // nb virtual channels + 4,4); // input & output fifo depths + + std::ostringstream s_int_router_rsp; + s_int_router_rsp << "router_rsp_" << x_id << "_" << y_id; + int_router_rsp = new VirtualDspinRouter( + s_int_router_rsp.str().c_str(), + x_id,y_id, // router coordinates in mesh + x_width, y_width, // x & y fields width + 2, // nb virtual channels + 4,4); // input & output fifo depths + + ////////////// XRAM + std::ostringstream s_xram; + s_xram << "xram_" << x_id << "_" << y_id; + xram = new VciSimpleRam( + s_xram.str().c_str(), + IntTab(cluster_id, ram_xram_tgt_id), + mt_ram, + loader, + xram_latency); + + std::ostringstream s_wt_xram; + s_wt_xram << "xram_wt_" << x_id << "_" << y_id; + xram_ram_wt = new VciDspinTargetWrapper( + s_wt_xram.str().c_str(), + x_width + y_width + l_width); + + ///////////// RAM ROUTER(S) + std::ostringstream s_ram_router_cmd; + s_ram_router_cmd << "ram_router_cmd_" << x_id << "_" << y_id; + ram_router_cmd = new DspinRouter( + s_ram_router_cmd.str().c_str(), + x_id, y_id, // router coordinates in mesh + x_width, // x field width in first flit + y_width, // y field width in first flit + 4, 4); // input & output fifo depths + + std::ostringstream s_ram_router_rsp; + s_ram_router_rsp << "ram_router_rsp_" << x_id << "_" << y_id; + ram_router_rsp = new DspinRouter( + s_ram_router_rsp.str().c_str(), + x_id, y_id, // coordinates in mesh + x_width, // x field width in first flit + y_width, // y field width in first flit + 4, 4); // input & output fifo depths + + + ////////////////////// I/O CLUSTER ONLY /////////////////////// + if ( is_io ) + { + /////////// IO_BRIDGE + std::ostringstream s_iob; + s_iob << "iob_" << x_id << "_" << y_id; + iob = new VciIoBridge( + s_iob.str().c_str(), + mt_ram, // EXT network maptab + mt_int, // INT network maptab + mt_iox, // IOX network maptab + IntTab( cluster_id, int_iobx_tgt_id ), // INT TGTID + IntTab( cluster_id, int_iobx_ini_id ), // INT SRCID + IntTab( 0 , iox_iobx_tgt_id ), // IOX TGTID + IntTab( 0 , iox_iobx_ini_id ), // IOX SRCID + 16, // cache line words + 8, // IOTLB ways + 8, // IOTLB sets + debug_start_cycle, + iob_debug_ok ); + + std::ostringstream s_iob_ram_wi; + s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id; + iob_ram_wi = new VciDspinInitiatorWrapper( + s_iob_ram_wi.str().c_str(), + vci_param_int::S); + + std::ostringstream s_ram_xbar_cmd; + s_ram_xbar_cmd << "s_ram_xbar_cmd_" << x_id << "_" << y_id; + ram_xbar_cmd = new DspinLocalCrossbar( + s_ram_xbar_cmd.str().c_str(), // name + mt_ram, // mapping table + x_id, y_id, // x, y + x_width, y_width, l_width, // x_width, y_width, l_width + 2, 0, // local inputs, local outputs + 2, 2, // in fifo, out fifo depths + true, // is cmd ? + false, // use routing table ? + false); // support broadcast ? + + std::ostringstream s_ram_xbar_rsp; + s_ram_xbar_rsp << "s_ram_xbar_rsp_" << x_id << "_" << y_id; + ram_xbar_rsp = new DspinLocalCrossbar( + s_ram_xbar_rsp.str().c_str(), // name + mt_ram, // mapping table + x_id, y_id, // x, y + x_width, y_width, l_width, // x_width, y_width, l_width + 0, 2, // local inputs, local outputs + 2, 2, // in fifo, out fifo depths + false, // is cmd ? + true, // use routing table ? + false); // support broadcast ? + } // end if IO + + //////////////////////////////////// + // Connections are defined here + //////////////////////////////////// + + // on coherence network : local srcid[proc] in [0...nb_procs-1] + // : local srcid[memc] = nb_procs + + //////////////////////// internal CMD & RSP routers + int_router_cmd->p_clk (this->p_clk); + int_router_cmd->p_resetn (this->p_resetn); + int_router_rsp->p_clk (this->p_clk); + int_router_rsp->p_resetn (this->p_resetn); + + for (int i = 0; i < 4; i++) + { + for(int k = 0; k < 3; k++) + { + int_router_cmd->p_out[i][k] (this->p_dspin_int_cmd_out[i][k]); + int_router_cmd->p_in[i][k] (this->p_dspin_int_cmd_in[i][k]); + } + + for(int k = 0; k < 2; k++) + { + int_router_rsp->p_out[i][k] (this->p_dspin_int_rsp_out[i][k]); + int_router_rsp->p_in[i][k] (this->p_dspin_int_rsp_in[i][k]); + } + } + + // local ports + int_router_cmd->p_out[4][0] (signal_int_dspin_cmd_g2l_d); + int_router_cmd->p_out[4][1] (signal_int_dspin_m2p_g2l_c); + int_router_cmd->p_out[4][2] (signal_int_dspin_clack_g2l_c); + int_router_cmd->p_in[4][0] (signal_int_dspin_cmd_l2g_d); + int_router_cmd->p_in[4][1] (signal_int_dspin_m2p_l2g_c); + int_router_cmd->p_in[4][2] (signal_int_dspin_clack_l2g_c); + + int_router_rsp->p_out[4][0] (signal_int_dspin_rsp_g2l_d); + int_router_rsp->p_out[4][1] (signal_int_dspin_p2m_g2l_c); + int_router_rsp->p_in[4][0] (signal_int_dspin_rsp_l2g_d); + int_router_rsp->p_in[4][1] (signal_int_dspin_p2m_l2g_c); + + ///////////////////// CMD DSPIN local crossbar direct + int_xbar_d->p_clk (this->p_clk); + int_xbar_d->p_resetn (this->p_resetn); + int_xbar_d->p_initiator_to_up (signal_int_vci_l2g); + int_xbar_d->p_target_to_up (signal_int_vci_g2l); + + int_xbar_d->p_to_target[int_memc_tgt_id] (signal_int_vci_tgt_memc); + int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu); + int_xbar_d->p_to_target[int_mdma_tgt_id] (signal_int_vci_tgt_mdma); + int_xbar_d->p_to_target[int_brom_tgt_id] (signal_int_vci_tgt_brom); + int_xbar_d->p_to_initiator[int_mdma_ini_id] (signal_int_vci_ini_mdma); + for (size_t p = 0; p < nb_procs; p++) + int_xbar_d->p_to_initiator[int_proc_ini_id + p] (signal_int_vci_ini_proc[p]); + + if ( is_io ) + { + int_xbar_d->p_to_target[int_iobx_tgt_id] (signal_int_vci_tgt_iobx); + int_xbar_d->p_to_initiator[int_iobx_ini_id] (signal_int_vci_ini_iobx); + } + + int_wi_gate_d->p_clk (this->p_clk); + int_wi_gate_d->p_resetn (this->p_resetn); + int_wi_gate_d->p_vci (signal_int_vci_l2g); + int_wi_gate_d->p_dspin_cmd (signal_int_dspin_cmd_l2g_d); + int_wi_gate_d->p_dspin_rsp (signal_int_dspin_rsp_g2l_d); + + int_wt_gate_d->p_clk (this->p_clk); + int_wt_gate_d->p_resetn (this->p_resetn); + int_wt_gate_d->p_vci (signal_int_vci_g2l); + int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d); + int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d); + + ////////////////////// M2P DSPIN local crossbar coherence + int_xbar_m2p_c->p_clk (this->p_clk); + int_xbar_m2p_c->p_resetn (this->p_resetn); + int_xbar_m2p_c->p_global_out (signal_int_dspin_m2p_l2g_c); + int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c); + int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc); + for (size_t p = 0; p < nb_procs; p++) + int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]); + + ////////////////////////// P2M DSPIN local crossbar coherence + int_xbar_p2m_c->p_clk (this->p_clk); + int_xbar_p2m_c->p_resetn (this->p_resetn); + int_xbar_p2m_c->p_global_out (signal_int_dspin_p2m_l2g_c); + int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c); + int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc); + for (size_t p = 0; p < nb_procs; p++) + int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]); + + ////////////////////// CLACK DSPIN local crossbar coherence + int_xbar_clack_c->p_clk (this->p_clk); + int_xbar_clack_c->p_resetn (this->p_resetn); + int_xbar_clack_c->p_global_out (signal_int_dspin_clack_l2g_c); + int_xbar_clack_c->p_global_in (signal_int_dspin_clack_g2l_c); + int_xbar_clack_c->p_local_in[0] (signal_int_dspin_clack_memc); + for (size_t p = 0; p < nb_procs; p++) + int_xbar_clack_c->p_local_out[p] (signal_int_dspin_clack_proc[p]); + + //////////////////////////////////// Processors + for (size_t p = 0; p < nb_procs; p++) + { + proc[p]->p_clk (this->p_clk); + proc[p]->p_resetn (this->p_resetn); + proc[p]->p_vci (signal_int_vci_ini_proc[p]); + proc[p]->p_dspin_m2p (signal_int_dspin_m2p_proc[p]); + proc[p]->p_dspin_p2m (signal_int_dspin_p2m_proc[p]); + proc[p]->p_dspin_clack (signal_int_dspin_clack_proc[p]); + + for ( size_t j = 0 ; j < 6 ; j++) + { + if ( j < 4 ) proc[p]->p_irq[j] (signal_proc_it[4*p + j]); + else proc[p]->p_irq[j] (signal_false); + } + } + + ///////////////////////////////////// XICU + xicu->p_clk (this->p_clk); + xicu->p_resetn (this->p_resetn); + xicu->p_vci (signal_int_vci_tgt_xicu); + for ( size_t i=0 ; i < 16 ; i++) + { + xicu->p_irq[i] (signal_proc_it[i]); + } + for ( size_t i=0 ; i < xcu_nb_inputs ; i++) + { + if ( i == 0 ) xicu->p_hwi[i] (signal_irq_memc); + else if ( i <= nb_dmas ) xicu->p_hwi[i] (signal_irq_mdma[i-1]); + else xicu->p_hwi[i] (signal_false); + } + + ///////////////////////////////////// MEMC + memc->p_clk (this->p_clk); + memc->p_resetn (this->p_resetn); + memc->p_vci_ixr (signal_ram_vci_ini_memc); + memc->p_vci_tgt (signal_int_vci_tgt_memc); + memc->p_dspin_p2m (signal_int_dspin_p2m_memc); + memc->p_dspin_m2p (signal_int_dspin_m2p_memc); + memc->p_dspin_clack (signal_int_dspin_clack_memc); + memc->p_irq (signal_irq_memc); + + // wrapper to RAM network + memc_ram_wi->p_clk (this->p_clk); + memc_ram_wi->p_resetn (this->p_resetn); + memc_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_memc_i); + memc_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_memc_i); + memc_ram_wi->p_vci (signal_ram_vci_ini_memc); + + //////////////////////////////////// XRAM + xram->p_clk (this->p_clk); + xram->p_resetn (this->p_resetn); + xram->p_vci (signal_ram_vci_tgt_xram); + + // wrapper to RAM network + xram_ram_wt->p_clk (this->p_clk); + xram_ram_wt->p_resetn (this->p_resetn); + xram_ram_wt->p_dspin_cmd (signal_ram_dspin_cmd_xram_t); + xram_ram_wt->p_dspin_rsp (signal_ram_dspin_rsp_xram_t); + xram_ram_wt->p_vci (signal_ram_vci_tgt_xram); + + /////////////////////////////////// MDMA + mdma->p_clk (this->p_clk); + mdma->p_resetn (this->p_resetn); + mdma->p_vci_target (signal_int_vci_tgt_mdma); + mdma->p_vci_initiator (signal_int_vci_ini_mdma); + for (size_t i=0 ; ip_irq[i] (signal_irq_mdma[i]); + + /////////////////////////////////// BROM + brom->p_clk (this->p_clk); + brom->p_resetn (this->p_resetn); + brom->p_vci (signal_int_vci_tgt_brom); + + //////////////////////////// RAM network CMD & RSP routers + ram_router_cmd->p_clk (this->p_clk); + ram_router_cmd->p_resetn (this->p_resetn); + ram_router_rsp->p_clk (this->p_clk); + ram_router_rsp->p_resetn (this->p_resetn); + for( size_t n=0 ; n<4 ; n++) + { + ram_router_cmd->p_out[n] (this->p_dspin_ram_cmd_out[n]); + ram_router_cmd->p_in[n] (this->p_dspin_ram_cmd_in[n]); + ram_router_rsp->p_out[n] (this->p_dspin_ram_rsp_out[n]); + ram_router_rsp->p_in[n] (this->p_dspin_ram_rsp_in[n]); + } + + ram_router_cmd->p_out[4] (signal_ram_dspin_cmd_xram_t); + ram_router_rsp->p_in[4] (signal_ram_dspin_rsp_xram_t); + + if ( is_io ) + { + ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_xbar); + ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_xbar); + } + else + { + ram_router_cmd->p_in[4] (signal_ram_dspin_cmd_memc_i); + ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i); + } + + ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. + if ( is_io ) + { + // IO bridge + iob->p_clk (this->p_clk); + iob->p_resetn (this->p_resetn); + iob->p_vci_ini_iox (*(this->p_vci_iob_iox_ini)); + iob->p_vci_tgt_iox (*(this->p_vci_iob_iox_tgt)); + iob->p_vci_tgt_int (signal_int_vci_tgt_iobx); + iob->p_vci_ini_int (signal_int_vci_ini_iobx); + iob->p_vci_ini_ram (signal_ram_vci_ini_iobx); + + // initiator wrapper to RAM network + iob_ram_wi->p_clk (this->p_clk); + iob_ram_wi->p_resetn (this->p_resetn); + iob_ram_wi->p_dspin_cmd (signal_ram_dspin_cmd_iob_i); + iob_ram_wi->p_dspin_rsp (signal_ram_dspin_rsp_iob_i); + iob_ram_wi->p_vci (signal_ram_vci_ini_iobx); + + // crossbar between MEMC and IOB to RAM network + ram_xbar_cmd->p_clk (this->p_clk); + ram_xbar_cmd->p_resetn (this->p_resetn); + ram_xbar_cmd->p_global_out (signal_ram_dspin_cmd_xbar); + ram_xbar_cmd->p_global_in (signal_ram_dspin_cmd_false); + ram_xbar_cmd->p_local_in[ram_memc_ini_id] (signal_ram_dspin_cmd_memc_i); + ram_xbar_cmd->p_local_in[ram_iobx_ini_id] (signal_ram_dspin_cmd_iob_i); + + ram_xbar_rsp->p_clk (this->p_clk); + ram_xbar_rsp->p_resetn (this->p_resetn); + ram_xbar_rsp->p_global_out (signal_ram_dspin_rsp_false); + ram_xbar_rsp->p_global_in (signal_ram_dspin_rsp_xbar); + ram_xbar_rsp->p_local_out[ram_memc_ini_id] (signal_ram_dspin_rsp_memc_i); + ram_xbar_rsp->p_local_out[ram_iobx_ini_id] (signal_ram_dspin_rsp_iob_i); + } + + SC_METHOD(init); +} // end constructor + +tmpl(void)::init() +{ + signal_ram_dspin_cmd_false.write = false; + signal_ram_dspin_cmd_false.read = true; + signal_ram_dspin_rsp_false.write = false; + signal_ram_dspin_rsp_false.read = true; +} // end init + +}} + + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: /branches/fault_tolerance/platforms/tsar_generic_leti/Makefile =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_leti/Makefile (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_leti/Makefile (revision 724) @@ -0,0 +1,6 @@ +simul.x: top.cpp top.desc + soclib-cc -P -p top.desc -I. -o simul.x + +clean: + soclib-cc -x -p top.desc -I. + rm -rf *.o *.x term* tty* ext* temp Index: /branches/fault_tolerance/platforms/tsar_generic_leti/soclib.conf =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_leti/soclib.conf (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_leti/soclib.conf (revision 724) @@ -0,0 +1,1 @@ + Index: /branches/fault_tolerance/platforms/tsar_generic_leti/top.cpp =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_leti/top.cpp (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_leti/top.cpp (revision 724) @@ -0,0 +1,1422 @@ +///////////////////////////////////////////////////////////////////////// +// File: top.cpp (for tsar_generic_leti) +// Author: Alain Greiner +// Copyright: UPMC/LIP6 +// Date : february 2014 +// This program is released under the GNU public license +///////////////////////////////////////////////////////////////////////// +// This file define a generic TSAR architecture, fully compatible +// with the VLSI Hardware prototype developped by CEA-LETI and LIP6 +// in the framework of the SHARP project. +// +// The processor is a MIPS32 processor wrapped in a GDB server +// (this is defined in the tsar_xbar_cluster). +// +// It does not use an external ROM, as the boot code is (pre)loaded +// in cluster (0,0) memory at address 0x0. +// +// The physical address space is 40 bits. +// The 8 address MSB bits define the cluster index. +// +// The main hardware parameters are the mesh size (X_SIZE & Y_SIZE), +// and the number of processors per cluster (NB_PROCS_MAX). +// The number of clusters cannot be larger than 128. +// The number of processors per cluster cannot be larger than 4. +// +// Each cluster contains: +// - 5 dspin_local_crossbar (local interconnect) +// - 5 dspin_router (global interconnect) +// - up to 4 vci_cc_vcache wrapping a MIPS32 processor +// - 1 vci_mem_cache +// - 1 vci_xicu +// - 1 vci_simple_ram (to model the L3 cache). +// +// Each processor receives 4 consecutive IRQ lines from the local XICU. +// +// In all clusters, the MEMC IRQ line (signaling a late write error) +// is connected to XICU HWI[8] +// The cluster (0,0) contains two "backup" peripherals: +// - one block device controller, whose IRQ is connected to XICU HWI[9]. +// - one single channel TTY controller, whose IRQ is connected to XICU HWI[10]. +// +// The cluster internal architecture is defined in file tsar_leti_cluster, +// that must be considered as an extension of this top.cpp file. +// +// Besides the hardware components in clusters, "external" peripherals +// are connected to an external IO bus (implemented as a vci_local_crossbar): +// - one disk controller +// - one multi-channel ethernet controller +// - one multi-channel chained buffer dma controller +// - one multi-channel tty controller +// - one frame buffer controller +// - one 32 channels iopic controller +// +// This IOBUS is connected to the north port of the DIR_CMD +// and DIR_RSP routers, in cluster(X_SIZE-1, Y_SIZE-1). +// For all external peripherals, the hardware interrupts (HWI) are +// translated to write interrupts (WTI) by the iopic component: +// - IOPIC HWI[1:0] connected to IRQ_NIC_RX[1:0] +// - IOPIC HWI[3:2] connected to IRQ_NIC_TX[1:0] +// - IOPIC HWI[7:4] connected to IRQ_CMA_TX[3:0]] +// - IOPIC HWI[8] connected to IRQ_BDEV +// - IOPIC HWI[15:9] unused (grounded) +// - IOPIC HWI[23:16] connected to IRQ_TTY_RX[7:0]] +// - IOPIC HWI[31:24] connected to IRQ_TTY_TX[7:0]] +//////////////////////////////////////////////////////////////////////////// +// The following parameters must be defined in the hard_config.h file : +// - X_WIDTH : number of bits for x coordinate (must be 4) +// - Y_WIDTH : number of bits for y coordinate (must be 4) +// - X_SIZE : number of clusters in a row (1,2,4,8,16) +// - Y_SIZE : number of clusters in a column (1,2,4,8) +// - NB_PROCS_MAX : number of processors per cluster (1, 2 or 4) +// - NB_CMA_CHANNELS : number of CMA channels in I/0 cluster (4 max) +// - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (8 max) +// - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (2 max) +// +// Some other hardware parameters are not used when compiling the OS, +// and are only defined in this top.cpp file: +// - XRAM_LATENCY : external ram latency +// - MEMC_WAYS : L2 cache number of ways +// - MEMC_SETS : L2 cache number of sets +// - L1_IWAYS : L1 cache instruction number of ways +// - L1_ISETS : L1 cache instruction number of sets +// - L1_DWAYS : L1 cache data number of ways +// - L1_DSETS : L1 cache data number of sets +// - FBUF_X_SIZE : width of frame buffer (pixels) +// - FBUF_Y_SIZE : heigth of frame buffer (lines) +// - BDEV_IMAGE_NAME : file pathname for block device +// - NIC_RX_NAME : file pathname for NIC received packets +// - NIC_TX_NAME : file pathname for NIC transmited packets +// - NIC_MAC4 : MAC address +// - NIC_MAC2 : MAC address +///////////////////////////////////////////////////////////////////////// +// General policy for 40 bits physical address decoding: +// All physical segments base addresses are multiple of 1 Mbytes +// (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) +// The (X_WIDTH + Y_WIDTH) MSB bits (left aligned) define +// the cluster index, and the LADR bits define the local index: +// |X_ID|Y_ID| LADR | OFFSET | +// | 4 | 4 | 8 | 24 | +///////////////////////////////////////////////////////////////////////// +// General policy for 14 bits SRCID decoding: +// Each component is identified by (x_id, y_id, l_id) tuple. +// |X_ID|Y_ID| L_ID | +// | 4 | 4 | 6 | +///////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include +#include +#include +#include + +#include "gdbserver.h" +#include "mapping_table.h" +#include "tsar_leti_cluster.h" +#include "vci_local_crossbar.h" +#include "vci_dspin_initiator_wrapper.h" +#include "vci_dspin_target_wrapper.h" +#include "vci_multi_tty.h" +#include "vci_multi_nic.h" +#include "vci_chbuf_dma.h" +#include "vci_block_device_tsar.h" +#include "vci_framebuffer.h" +#include "vci_iopic.h" +#include "alloc_elems.h" + +////////////////////////////////////////////////////////////////////////////////////////// +// Parameters depending on the OS and software application +// - path to hard_config file +// - path to binary code for the RAM loader +// - path to disk image for RAMDISK loader +// - path to disk image for IOC device +////////////////////////////////////////////////////////////////////////////////////////// + +#define USE_GIET_VM 1 +#define USE_GIET_TSAR 0 + +#if ( USE_GIET_VM and USE_GIET_TSAR ) +#error "Can't use Two different OS" +#endif + +#if ( (not USE_GIET_VM) and (not USE_GIET_TSAR) ) +#error "You need to specify one OS" +#endif + +#if USE_GIET_TSAR +#include "hard_config.h" +#define BINARY_PATH_FOR_LOADER "../../softs/soft_transpose_giet/bin.soft" +#define DISK_IMAGE_PATH_FOR_IOC "../../softs/soft_transpose_giet/images.raw" +#define RAMDISK_PATH_FOR_LOADER DISK_IMAGE_PATH_FOR_IOC "@0x00800000:" +#endif + +#if USE_GIET_VM +#include "hard_config.h" +#define BINARY_PATH_FOR_LOADER "../../softs/tsar_boot/preloader.elf" +#define DISK_IMAGE_PATH_FOR_IOC "../../../giet_vm/hdd/virt_hdd.dmg" +#define RAMDISK_PATH_FOR_LOADER DISK_IMAGE_PATH_FOR_IOC "@0x02000000:" +#endif + +/////////////////////////////////////////////////// +// Parallelisation +/////////////////////////////////////////////////// +#define USE_OPENMP _OPENMP + +#if USE_OPENMP +#include +#endif + +/////////////////////////////////////////////////// +// cluster index (from x,y coordinates) +/////////////////////////////////////////////////// + +#define cluster(x,y) ((y) + ((x) << Y_WIDTH)) + +/////////////////////////////////////////////////////////// +// DSPIN parameters +/////////////////////////////////////////////////////////// + +#define dspin_cmd_width 39 +#define dspin_rsp_width 32 + +/////////////////////////////////////////////////////////// +// VCI parameters +/////////////////////////////////////////////////////////// + +#define vci_cell_width_int 4 +#define vci_cell_width_ext 8 +#define vci_address_width 40 +#define vci_plen_width 8 +#define vci_rerror_width 1 +#define vci_clen_width 1 +#define vci_rflag_width 1 +#define vci_srcid_width 14 +#define vci_pktid_width 4 +#define vci_trdid_width 4 +#define vci_wrplen_width 1 + + +///////////////////////////////////////////////////////////////////////////////////////// +// Secondary Hardware Parameters +///////////////////////////////////////////////////////////////////////////////////////// + +#define RESET_ADDRESS 0x0 + +#define MAX_TTY_CHANNELS 8 +#define MAX_CMA_CHANNELS 4 +#define MAX_NIC_CHANNELS 2 + +#define XRAM_LATENCY 0 +#define XRAM_SIZE 0x04000000 // 64 Mbytes per cluster + +#define MEMC_WAYS 16 +#define MEMC_SETS 256 + +#define L1_IWAYS 4 +#define L1_ISETS 64 + +#define L1_DWAYS 4 +#define L1_DSETS 64 + +#define FBUF_X_SIZE 128 +#define FBUF_Y_SIZE 128 + +#define NIC_MAC4 0XBABEF00D +#define NIC_MAC2 0xBEEF +#define NIC_RX_NAME "/dev/null" +#define NIC_TX_NAME "/dev/null" + +#define NORTH 0 +#define SOUTH 1 +#define EAST 2 +#define WEST 3 + +/////////////////////////////////////////////////////////////////////////////////////// +// DEBUG Parameters default values +/////////////////////////////////////////////////////////////////////////////////////// + +#define MAX_FROZEN_CYCLES 500000 + +/////////////////////////////////////////////////////////////////////////////////////// +// LOCAL TGTID & SRCID definition +// For all components: global TGTID = global SRCID = cluster_index +/////////////////////////////////////////////////////////////////////////////////////// + +#define MEMC_TGTID 0 +#define XICU_TGTID 1 +#define MTTY_TGTID 2 +#define BDEV_TGTID 3 +#define FBUF_TGTID 4 +#define MNIC_TGTID 5 +#define CDMA_TGTID 6 +#define IOPI_TGTID 7 + +#define BDEV_SRCID NB_PROCS_MAX +#define CDMA_SRCID NB_PROCS_MAX + 1 +#define IOPI_SRCID NB_PROCS_MAX + 2 + +////////////////////////////////////////////////////////////////////////////////////// +// Physical segments definition +////////////////////////////////////////////////////////////////////////////////////// +// - 3 segments are replicated in all clusters +// - 2 segments are only in cluster[0,0] +// - 4 segments are only in cluster [X_SIZE-1,Y_SIZE] +// The following values are for segments in cluster 0, +// and these 32 bits values must be concatenate with the cluster +// index (on 8 bits) to obtain the 40 bits address. +////////////////////////////////////////////////////////////////////////////////////// + +// in cluster [0,0] & [X_SIZE-1,Y_SIZE] + +#define MTTY_BASE 0xF4000000 +#define MTTY_SIZE 0x00001000 // 4 Kbytes + +#define BDEV_BASE 0xF2000000 +#define BDEV_SIZE 0x00001000 // 4 Kbytes + +// in cluster [X_SIZE-1,Y_SIZE] + +#define FBUF_BASE 0xF3000000 +#define FBUF_SIZE (FBUF_X_SIZE * FBUF_Y_SIZE * 2) + +#define MNIC_BASE 0xF7000000 +#define MNIC_SIZE 0x00800000 // 512 Kbytes (for 8 channels) + +#define CDMA_BASE 0xF8000000 +#define CDMA_SIZE 0x00004000 * NB_CMA_CHANNELS + +#define IOPI_BASE 0xF9000000 +#define IOPI_SIZE 0x00001000 // 4 Kbytes + +// replicated segments : address is extended to 40 bits by cluster_xy + +#define MEMC_BASE 0x00000000 +#define MEMC_SIZE XRAM_SIZE + +#define MCFG_BASE 0xE0000000 +#define MCFG_SIZE 0x00001000 // 4 Kbytes + +#define XICU_BASE 0xF0000000 +#define XICU_SIZE 0x00001000 // 4 Kbytes + +bool stop_called = false; + +///////////////////////////////// +int _main(int argc, char *argv[]) +{ + using namespace sc_core; + using namespace soclib::caba; + using namespace soclib::common; + + uint32_t ncycles = 0xFFFFFFFF; // max simulated cycles + size_t threads = 1; // simulator's threads number + bool trace_ok = false; // trace activated + uint32_t trace_from = 0; // trace start cycle + bool trace_proc_ok = false; // detailed proc trace activated + size_t trace_memc_ok = false; // detailed memc trace activated + size_t trace_memc_id = 0; // index of memc to be traced + size_t trace_proc_id = 0; // index of proc to be traced + uint32_t frozen_cycles = MAX_FROZEN_CYCLES; + char soft_name[256] = BINARY_PATH_FOR_LOADER; + char disk_name[256] = DISK_IMAGE_PATH_FOR_IOC; + char ramdisk_name[256] = RAMDISK_PATH_FOR_LOADER; + struct timeval t1,t2; + uint64_t ms1,ms2; + + ////////////// command line arguments ////////////////////// + if (argc > 1) + { + for (int n = 1; n < argc; n = n + 2) + { + if ((strcmp(argv[n], "-NCYCLES") == 0) && (n + 1 < argc)) + { + ncycles = (uint64_t) strtol(argv[n + 1], NULL, 0); + } + else if ((strcmp(argv[n],"-DEBUG") == 0) && (n + 1 < argc)) + { + trace_ok = true; + trace_from = (uint32_t) strtol(argv[n + 1], NULL, 0); + } + else if ((strcmp(argv[n], "-MEMCID") == 0) && (n + 1 < argc)) + { + trace_memc_ok = true; + trace_memc_id = (size_t) strtol(argv[n + 1], NULL, 0); + size_t x = trace_memc_id >> Y_WIDTH; + size_t y = trace_memc_id & ((1<> Y_WIDTH; + size_t y = cluster_xy & ((1< offset; + offset = ((sc_uint)cluster(x,y)) << 32; + + std::ostringstream si; + si << "seg_xicu_" << x << "_" << y; + maptabd.add(Segment(si.str(), XICU_BASE + offset, XICU_SIZE, + IntTab(cluster(x,y),XICU_TGTID), false)); + + std::ostringstream sd; + sd << "seg_mcfg_" << x << "_" << y; + maptabd.add(Segment(sd.str(), MCFG_BASE + offset, MCFG_SIZE, + IntTab(cluster(x,y),MEMC_TGTID), false)); + + std::ostringstream sh; + sh << "seg_memc_" << x << "_" << y; + maptabd.add(Segment(sh.str(), MEMC_BASE + offset, MEMC_SIZE, + IntTab(cluster(x,y),MEMC_TGTID), true)); + } + } + + // segments for peripherals in cluster(0,0) + maptabd.add(Segment("seg_tty0", MTTY_BASE, MTTY_SIZE, + IntTab(cluster(0,0),MTTY_TGTID), false)); + + maptabd.add(Segment("seg_ioc0", BDEV_BASE, BDEV_SIZE, + IntTab(cluster(0,0),BDEV_TGTID), false)); + + // segments for peripherals in cluster_io (X_SIZE-1,Y_SIZE) + sc_uint offset; + offset = ((sc_uint)cluster(X_SIZE-1,Y_SIZE)) << 32; + + maptabd.add(Segment("seg_mtty", MTTY_BASE + offset, MTTY_SIZE, + IntTab(cluster(X_SIZE-1, Y_SIZE),MTTY_TGTID), false)); + + maptabd.add(Segment("seg_fbuf", FBUF_BASE + offset, FBUF_SIZE, + IntTab(cluster(X_SIZE-1, Y_SIZE),FBUF_TGTID), false)); + + maptabd.add(Segment("seg_bdev", BDEV_BASE + offset, BDEV_SIZE, + IntTab(cluster(X_SIZE-1, Y_SIZE),BDEV_TGTID), false)); + + maptabd.add(Segment("seg_mnic", MNIC_BASE + offset, MNIC_SIZE, + IntTab(cluster(X_SIZE-1, Y_SIZE),MNIC_TGTID), false)); + + maptabd.add(Segment("seg_cdma", CDMA_BASE + offset, CDMA_SIZE, + IntTab(cluster(X_SIZE-1, Y_SIZE),CDMA_TGTID), false)); + + maptabd.add(Segment("seg_iopi", IOPI_BASE + offset, IOPI_SIZE, + IntTab(cluster(X_SIZE-1, Y_SIZE),IOPI_TGTID), false)); + + std::cout << maptabd << std::endl; + + ///////////////////////////////////////////////// + // Ram network mapping table + ///////////////////////////////////////////////// + + MappingTable maptabx(vci_address_width, + IntTab(X_WIDTH+Y_WIDTH), + IntTab(X_WIDTH+Y_WIDTH), + 0x00FF000000ULL); + + for (size_t x = 0; x < X_SIZE; x++) + { + for (size_t y = 0; y < (Y_SIZE) ; y++) + { + sc_uint offset; + offset = (sc_uint)cluster(x,y) + << (vci_address_width-X_WIDTH-Y_WIDTH); + + std::ostringstream sh; + sh << "x_seg_memc_" << x << "_" << y; + + maptabx.add(Segment(sh.str(), MEMC_BASE + offset, + MEMC_SIZE, IntTab(cluster(x,y)), false)); + } + } + std::cout << maptabx << std::endl; + + //////////////////// + // Signals + /////////////////// + + sc_clock signal_clk("clk"); + sc_signal signal_resetn("resetn"); + + // IRQs from external peripherals + sc_signal signal_irq_bdev; + sc_signal signal_irq_mnic_rx[NB_NIC_CHANNELS]; + sc_signal signal_irq_mnic_tx[NB_NIC_CHANNELS]; + sc_signal signal_irq_mtty_rx[NB_TTY_CHANNELS]; +// sc_signal signal_irq_mtty_tx[NB_TTY_CHANNELS]; + sc_signal signal_irq_cdma[NB_CMA_CHANNELS]; + sc_signal signal_irq_false; + + // Horizontal inter-clusters DSPIN signals + DspinSignals** signal_dspin_h_cmd_inc = + alloc_elems >("signal_dspin_h_cmd_inc", X_SIZE-1, Y_SIZE); + DspinSignals** signal_dspin_h_cmd_dec = + alloc_elems >("signal_dspin_h_cmd_dec", X_SIZE-1, Y_SIZE); + + DspinSignals** signal_dspin_h_rsp_inc = + alloc_elems >("signal_dspin_h_rsp_inc", X_SIZE-1, Y_SIZE); + DspinSignals** signal_dspin_h_rsp_dec = + alloc_elems >("signal_dspin_h_rsp_dec", X_SIZE-1, Y_SIZE); + + DspinSignals** signal_dspin_h_m2p_inc = + alloc_elems >("signal_dspin_h_m2p_inc", X_SIZE-1, Y_SIZE); + DspinSignals** signal_dspin_h_m2p_dec = + alloc_elems >("signal_dspin_h_m2p_dec", X_SIZE-1, Y_SIZE); + + DspinSignals** signal_dspin_h_p2m_inc = + alloc_elems >("signal_dspin_h_p2m_inc", X_SIZE-1, Y_SIZE); + DspinSignals** signal_dspin_h_p2m_dec = + alloc_elems >("signal_dspin_h_p2m_dec", X_SIZE-1, Y_SIZE); + + DspinSignals** signal_dspin_h_cla_inc = + alloc_elems >("signal_dspin_h_cla_inc", X_SIZE-1, Y_SIZE); + DspinSignals** signal_dspin_h_cla_dec = + alloc_elems >("signal_dspin_h_cla_dec", X_SIZE-1, Y_SIZE); + + // Vertical inter-clusters DSPIN signals + DspinSignals** signal_dspin_v_cmd_inc = + alloc_elems >("signal_dspin_v_cmd_inc", X_SIZE, Y_SIZE-1); + DspinSignals** signal_dspin_v_cmd_dec = + alloc_elems >("signal_dspin_v_cmd_dec", X_SIZE, Y_SIZE-1); + + DspinSignals** signal_dspin_v_rsp_inc = + alloc_elems >("signal_dspin_v_rsp_inc", X_SIZE, Y_SIZE-1); + DspinSignals** signal_dspin_v_rsp_dec = + alloc_elems >("signal_dspin_v_rsp_dec", X_SIZE, Y_SIZE-1); + + DspinSignals** signal_dspin_v_m2p_inc = + alloc_elems >("signal_dspin_v_m2p_inc", X_SIZE, Y_SIZE-1); + DspinSignals** signal_dspin_v_m2p_dec = + alloc_elems >("signal_dspin_v_m2p_dec", X_SIZE, Y_SIZE-1); + + DspinSignals** signal_dspin_v_p2m_inc = + alloc_elems >("signal_dspin_v_p2m_inc", X_SIZE, Y_SIZE-1); + DspinSignals** signal_dspin_v_p2m_dec = + alloc_elems >("signal_dspin_v_p2m_dec", X_SIZE, Y_SIZE-1); + + DspinSignals** signal_dspin_v_cla_inc = + alloc_elems >("signal_dspin_v_cla_inc", X_SIZE, Y_SIZE-1); + DspinSignals** signal_dspin_v_cla_dec = + alloc_elems >("signal_dspin_v_cla_dec", X_SIZE, Y_SIZE-1); + + // Mesh boundaries DSPIN signals (Most of those signals are not used...) + DspinSignals*** signal_dspin_bound_cmd_in = + alloc_elems >("signal_dspin_bound_cmd_in" , X_SIZE, Y_SIZE, 4); + DspinSignals*** signal_dspin_bound_cmd_out = + alloc_elems >("signal_dspin_bound_cmd_out", X_SIZE, Y_SIZE, 4); + + DspinSignals*** signal_dspin_bound_rsp_in = + alloc_elems >("signal_dspin_bound_rsp_in" , X_SIZE, Y_SIZE, 4); + DspinSignals*** signal_dspin_bound_rsp_out = + alloc_elems >("signal_dspin_bound_rsp_out", X_SIZE, Y_SIZE, 4); + + DspinSignals*** signal_dspin_bound_m2p_in = + alloc_elems >("signal_dspin_bound_m2p_in" , X_SIZE, Y_SIZE, 4); + DspinSignals*** signal_dspin_bound_m2p_out = + alloc_elems >("signal_dspin_bound_m2p_out", X_SIZE, Y_SIZE, 4); + + DspinSignals*** signal_dspin_bound_p2m_in = + alloc_elems >("signal_dspin_bound_p2m_in" , X_SIZE, Y_SIZE, 4); + DspinSignals*** signal_dspin_bound_p2m_out = + alloc_elems >("signal_dspin_bound_p2m_out", X_SIZE, Y_SIZE, 4); + + DspinSignals*** signal_dspin_bound_cla_in = + alloc_elems >("signal_dspin_bound_cla_in" , X_SIZE, Y_SIZE, 4); + DspinSignals*** signal_dspin_bound_cla_out = + alloc_elems >("signal_dspin_bound_cla_out", X_SIZE, Y_SIZE, 4); + + // VCI signals for iobus and peripherals + VciSignals signal_vci_ini_bdev("signal_vci_ini_bdev"); + VciSignals signal_vci_ini_cdma("signal_vci_ini_cdma"); + VciSignals signal_vci_ini_iopi("signal_vci_ini_iopi"); + + VciSignals* signal_vci_ini_proc = + alloc_elems >("signal_vci_ini_proc", NB_PROCS_MAX ); + + VciSignals signal_vci_tgt_memc("signal_vci_tgt_memc"); + VciSignals signal_vci_tgt_xicu("signal_vci_tgt_xicu"); + VciSignals signal_vci_tgt_bdev("signal_vci_tgt_bdev"); + VciSignals signal_vci_tgt_mtty("signal_vci_tgt_mtty"); + VciSignals signal_vci_tgt_fbuf("signal_vci_tgt_fbuf"); + VciSignals signal_vci_tgt_mnic("signal_vci_tgt_mnic"); + VciSignals signal_vci_tgt_cdma("signal_vci_tgt_cdma"); + VciSignals signal_vci_tgt_iopi("signal_vci_tgt_iopi"); + + VciSignals signal_vci_cmd_to_noc("signal_vci_cmd_to_noc"); + VciSignals signal_vci_cmd_from_noc("signal_vci_cmd_from_noc"); + + //////////////////////////// + // Loader + //////////////////////////// + +#if USE_IOC_RDK + soclib::common::Loader loader( soft_name, ramdisk_name ); +#else + soclib::common::Loader loader( soft_name ); +#endif + loader.memory_default(0xAA); + + /////////////////////////// + // processor iss + /////////////////////////// + + typedef soclib::common::GdbServer proc_iss; + proc_iss::set_loader( loader ); + + ////////////////////////////////////////////////////////////// + // mesh construction: only (X_SIZE) * (Y_SIZE) clusters + ////////////////////////////////////////////////////////////// + + TsarLetiCluster* clusters[X_SIZE][Y_SIZE]; + +#if USE_OPENMP +#pragma omp parallel + { +#pragma omp for +#endif + for (size_t i = 0; i < (X_SIZE * (Y_SIZE)); i++) + { + size_t x = i / (Y_SIZE); + size_t y = i % (Y_SIZE); + +#if USE_OPENMP +#pragma omp critical + { +#endif + std::cout << std::endl; + std::cout << "Cluster_" << std::dec << x << "_" << y + << " with cluster_xy = " << std::hex << cluster(x,y) << std::endl; + std::cout << std::endl; + + std::ostringstream cluster_name; + cluster_name << "cluster_" << std::dec << x << "_" << y; + + clusters[x][y] = new TsarLetiCluster + ( + cluster_name.str().c_str(), + NB_PROCS_MAX, + x, + y, + cluster(x,y), + maptabd, + maptabx, + RESET_ADDRESS, + X_WIDTH, + Y_WIDTH, + vci_srcid_width - X_WIDTH - Y_WIDTH, // l_id width, + MEMC_TGTID, + XICU_TGTID, + MTTY_TGTID, + BDEV_TGTID, + disk_name, + MEMC_WAYS, + MEMC_SETS, + L1_IWAYS, + L1_ISETS, + L1_DWAYS, + L1_DSETS, + XRAM_LATENCY, + loader, + frozen_cycles, + trace_from, + trace_proc_ok, + trace_proc_id, + trace_memc_ok, + trace_memc_id + ); + +#if USE_OPENMP + } // end critical +#endif + } // end for +#if USE_OPENMP + } +#endif + + ////////////////////////////////////////////////////////////////// + // IO bus and external peripherals in cluster[X_SIZE-1,Y_SIZE] + // - 6 local targets : FBF, TTY, CMA, NIC, PIC, IOC + // - 3 local initiators : IOC, CMA, PIC + // There is no PROC, no MEMC and no XICU in this cluster, + // but the crossbar has (NB_PROCS_MAX + 3) intiators and + // 8 targets, in order to use the same SRCID and TGTID space + // (same mapping table for the internal components, + // and for the external peripherals) + ////////////////////////////////////////////////////////////////// + + std::cout << std::endl; + std::cout << " Building IO cluster (external peripherals)" << std::endl; + std::cout << std::endl; + + size_t cluster_io = cluster(X_SIZE-1, Y_SIZE); + + //////////// vci_local_crossbar + VciLocalCrossbar* + iobus = new VciLocalCrossbar( + "iobus", + maptabd, // mapping table + cluster_io, // cluster_xy + NB_PROCS_MAX + 3, // number of local initiators + 8, // number of local targets + BDEV_TGTID ); // default target index + + //////////// vci_framebuffer + VciFrameBuffer* + fbuf = new VciFrameBuffer( + "fbuf", + IntTab(cluster_io, FBUF_TGTID), + maptabd, + FBUF_X_SIZE, FBUF_Y_SIZE ); + + //////////// vci_block_device + VciBlockDeviceTsar* + bdev = new VciBlockDeviceTsar( + "bdev", + maptabd, + IntTab(cluster_io, BDEV_SRCID), + IntTab(cluster_io, BDEV_TGTID), + disk_name, + 512, // block size + 64 ); // burst size + + //////////// vci_multi_nic + VciMultiNic* + mnic = new VciMultiNic( + "mnic", + IntTab(cluster_io, MNIC_TGTID), + maptabd, + NB_NIC_CHANNELS, + NIC_MAC4, + NIC_MAC2, + NIC_RX_NAME, + NIC_TX_NAME ); + + ///////////// vci_chbuf_dma + VciChbufDma* + cdma = new VciChbufDma( + "cdma", + maptabd, + IntTab(cluster_io, CDMA_SRCID), + IntTab(cluster_io, CDMA_TGTID), + 64, // burst size + NB_CMA_CHANNELS ); + + ////////////// vci_multi_tty + std::vector vect_names; + for (size_t id = 0; id < NB_TTY_CHANNELS; id++) + { + std::ostringstream term_name; + term_name << "ext_" << id; + vect_names.push_back(term_name.str().c_str()); + } + + VciMultiTty* + mtty = new VciMultiTty( + "mtty", + IntTab(cluster_io, MTTY_TGTID), + maptabd, + vect_names ); + + ///////////// vci_iopic + VciIopic* + iopic = new VciIopic( + "iopic", + maptabd, + IntTab(cluster_io, IOPI_SRCID), + IntTab(cluster_io, IOPI_TGTID), + 32, + 5000 ); + + ////////////// vci_dspin wrappers + VciDspinTargetWrapper* + wt_iobus = new VciDspinTargetWrapper( + "wt_bdev", + vci_srcid_width ); + + VciDspinInitiatorWrapper* + wi_iobus = new VciDspinInitiatorWrapper( + "wi_bdev", + vci_srcid_width ); + + /////////////////////////////////////////////////////////////// + // Net-list + /////////////////////////////////////////////////////////////// + + // iobus + iobus->p_clk (signal_clk); + iobus->p_resetn (signal_resetn); + + iobus->p_target_to_up (signal_vci_cmd_from_noc); + iobus->p_initiator_to_up (signal_vci_cmd_to_noc); + + iobus->p_to_target[MEMC_TGTID] (signal_vci_tgt_memc); + iobus->p_to_target[XICU_TGTID] (signal_vci_tgt_xicu); + iobus->p_to_target[MTTY_TGTID] (signal_vci_tgt_mtty); + iobus->p_to_target[FBUF_TGTID] (signal_vci_tgt_fbuf); + iobus->p_to_target[MNIC_TGTID] (signal_vci_tgt_mnic); + iobus->p_to_target[BDEV_TGTID] (signal_vci_tgt_bdev); + iobus->p_to_target[CDMA_TGTID] (signal_vci_tgt_cdma); + iobus->p_to_target[IOPI_TGTID] (signal_vci_tgt_iopi); + + for( size_t p=0 ; pp_to_initiator[p] (signal_vci_ini_proc[p]); + } + iobus->p_to_initiator[BDEV_SRCID] (signal_vci_ini_bdev); + iobus->p_to_initiator[CDMA_SRCID] (signal_vci_ini_cdma); + iobus->p_to_initiator[IOPI_SRCID] (signal_vci_ini_iopi); + + std::cout << " - IOBUS connected" << std::endl; + + // block_device + bdev->p_clk (signal_clk); + bdev->p_resetn (signal_resetn); + bdev->p_vci_target (signal_vci_tgt_bdev); + bdev->p_vci_initiator (signal_vci_ini_bdev); + bdev->p_irq (signal_irq_bdev); + + std::cout << " - BDEV connected" << std::endl; + + // frame_buffer + fbuf->p_clk (signal_clk); + fbuf->p_resetn (signal_resetn); + fbuf->p_vci (signal_vci_tgt_fbuf); + + std::cout << " - FBUF connected" << std::endl; + + // multi_nic + mnic->p_clk (signal_clk); + mnic->p_resetn (signal_resetn); + mnic->p_vci (signal_vci_tgt_mnic); + for ( size_t i=0 ; ip_rx_irq[i] (signal_irq_mnic_rx[i]); + mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]); + } + + std::cout << " - MNIC connected" << std::endl; + + // chbuf_dma + cdma->p_clk (signal_clk); + cdma->p_resetn (signal_resetn); + cdma->p_vci_target (signal_vci_tgt_cdma); + cdma->p_vci_initiator (signal_vci_ini_cdma); + for ( size_t i=0 ; ip_irq[i] (signal_irq_cdma[i]); + } + + std::cout << " - CDMA connected" << std::endl; + + // multi_tty + mtty->p_clk (signal_clk); + mtty->p_resetn (signal_resetn); + mtty->p_vci (signal_vci_tgt_mtty); + for ( size_t i=0 ; ip_irq[i] (signal_irq_mtty_rx[i]); + } + + std::cout << " - MTTY connected" << std::endl; + + // iopic + // NB_NIC_CHANNELS <= 2 + // NB_CMA_CHANNELS <= 4 + // NB_TTY_CHANNELS <= 8 + iopic->p_clk (signal_clk); + iopic->p_resetn (signal_resetn); + iopic->p_vci_target (signal_vci_tgt_iopi); + iopic->p_vci_initiator (signal_vci_ini_iopi); + for ( size_t i=0 ; i<32 ; i++) + { + if (i < NB_NIC_CHANNELS) iopic->p_hwi[i] (signal_irq_mnic_rx[i]); + else if(i < 2 ) iopic->p_hwi[i] (signal_irq_false); + else if(i < 2+NB_NIC_CHANNELS) iopic->p_hwi[i] (signal_irq_mnic_tx[i-2]); + else if(i < 4 ) iopic->p_hwi[i] (signal_irq_false); + else if(i < 4+NB_CMA_CHANNELS) iopic->p_hwi[i] (signal_irq_cdma[i-4]); + else if(i < 8) iopic->p_hwi[i] (signal_irq_false); + else if(i == 8) iopic->p_hwi[i] (signal_irq_bdev); + else if(i < 16) iopic->p_hwi[i] (signal_irq_false); + else if(i < 16+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_mtty_rx[i-16]); + else if(i < 24) iopic->p_hwi[i] (signal_irq_false); + else if(i < 24+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_false); +// else if(i < 24+NB_TTY_CHANNELS) iopic->p_hwi[i] (signal_irq_mtty_tx[i-24]); + else iopic->p_hwi[i] (signal_irq_false); + } + + std::cout << " - IOPIC connected" << std::endl; + + // vci/dspin wrappers + wi_iobus->p_clk (signal_clk); + wi_iobus->p_resetn (signal_resetn); + wi_iobus->p_vci (signal_vci_cmd_to_noc); + wi_iobus->p_dspin_cmd (signal_dspin_bound_cmd_in[X_SIZE-1][Y_SIZE-1][NORTH]); + wi_iobus->p_dspin_rsp (signal_dspin_bound_rsp_out[X_SIZE-1][Y_SIZE-1][NORTH]); + + // vci/dspin wrappers + wt_iobus->p_clk (signal_clk); + wt_iobus->p_resetn (signal_resetn); + wt_iobus->p_vci (signal_vci_cmd_from_noc); + wt_iobus->p_dspin_cmd (signal_dspin_bound_cmd_out[X_SIZE-1][Y_SIZE-1][NORTH]); + wt_iobus->p_dspin_rsp (signal_dspin_bound_rsp_in[X_SIZE-1][Y_SIZE-1][NORTH]); + + // Clock & RESET for clusters + for (size_t x = 0; x < (X_SIZE); x++) + { + for (size_t y = 0; y < (Y_SIZE); y++) + { + clusters[x][y]->p_clk (signal_clk); + clusters[x][y]->p_resetn (signal_resetn); + } + } + + // Inter Clusters horizontal connections + if (X_SIZE > 1) + { + for (size_t x = 0; x < (X_SIZE-1); x++) + { + for (size_t y = 0; y < (Y_SIZE); y++) + { + clusters[x][y]->p_cmd_out[EAST] (signal_dspin_h_cmd_inc[x][y]); + clusters[x+1][y]->p_cmd_in[WEST] (signal_dspin_h_cmd_inc[x][y]); + clusters[x][y]->p_cmd_in[EAST] (signal_dspin_h_cmd_dec[x][y]); + clusters[x+1][y]->p_cmd_out[WEST] (signal_dspin_h_cmd_dec[x][y]); + + clusters[x][y]->p_rsp_out[EAST] (signal_dspin_h_rsp_inc[x][y]); + clusters[x+1][y]->p_rsp_in[WEST] (signal_dspin_h_rsp_inc[x][y]); + clusters[x][y]->p_rsp_in[EAST] (signal_dspin_h_rsp_dec[x][y]); + clusters[x+1][y]->p_rsp_out[WEST] (signal_dspin_h_rsp_dec[x][y]); + + clusters[x][y]->p_m2p_out[EAST] (signal_dspin_h_m2p_inc[x][y]); + clusters[x+1][y]->p_m2p_in[WEST] (signal_dspin_h_m2p_inc[x][y]); + clusters[x][y]->p_m2p_in[EAST] (signal_dspin_h_m2p_dec[x][y]); + clusters[x+1][y]->p_m2p_out[WEST] (signal_dspin_h_m2p_dec[x][y]); + + clusters[x][y]->p_p2m_out[EAST] (signal_dspin_h_p2m_inc[x][y]); + clusters[x+1][y]->p_p2m_in[WEST] (signal_dspin_h_p2m_inc[x][y]); + clusters[x][y]->p_p2m_in[EAST] (signal_dspin_h_p2m_dec[x][y]); + clusters[x+1][y]->p_p2m_out[WEST] (signal_dspin_h_p2m_dec[x][y]); + + clusters[x][y]->p_cla_out[EAST] (signal_dspin_h_cla_inc[x][y]); + clusters[x+1][y]->p_cla_in[WEST] (signal_dspin_h_cla_inc[x][y]); + clusters[x][y]->p_cla_in[EAST] (signal_dspin_h_cla_dec[x][y]); + clusters[x+1][y]->p_cla_out[WEST] (signal_dspin_h_cla_dec[x][y]); + } + } + } + std::cout << std::endl << "Horizontal connections done" << std::endl; + + // Inter Clusters vertical connections + if (Y_SIZE > 1) + { + for (size_t y = 0; y < (Y_SIZE-1); y++) + { + for (size_t x = 0; x < X_SIZE; x++) + { + clusters[x][y]->p_cmd_out[NORTH] (signal_dspin_v_cmd_inc[x][y]); + clusters[x][y+1]->p_cmd_in[SOUTH] (signal_dspin_v_cmd_inc[x][y]); + clusters[x][y]->p_cmd_in[NORTH] (signal_dspin_v_cmd_dec[x][y]); + clusters[x][y+1]->p_cmd_out[SOUTH] (signal_dspin_v_cmd_dec[x][y]); + + clusters[x][y]->p_rsp_out[NORTH] (signal_dspin_v_rsp_inc[x][y]); + clusters[x][y+1]->p_rsp_in[SOUTH] (signal_dspin_v_rsp_inc[x][y]); + clusters[x][y]->p_rsp_in[NORTH] (signal_dspin_v_rsp_dec[x][y]); + clusters[x][y+1]->p_rsp_out[SOUTH] (signal_dspin_v_rsp_dec[x][y]); + + clusters[x][y]->p_m2p_out[NORTH] (signal_dspin_v_m2p_inc[x][y]); + clusters[x][y+1]->p_m2p_in[SOUTH] (signal_dspin_v_m2p_inc[x][y]); + clusters[x][y]->p_m2p_in[NORTH] (signal_dspin_v_m2p_dec[x][y]); + clusters[x][y+1]->p_m2p_out[SOUTH] (signal_dspin_v_m2p_dec[x][y]); + + clusters[x][y]->p_p2m_out[NORTH] (signal_dspin_v_p2m_inc[x][y]); + clusters[x][y+1]->p_p2m_in[SOUTH] (signal_dspin_v_p2m_inc[x][y]); + clusters[x][y]->p_p2m_in[NORTH] (signal_dspin_v_p2m_dec[x][y]); + clusters[x][y+1]->p_p2m_out[SOUTH] (signal_dspin_v_p2m_dec[x][y]); + + clusters[x][y]->p_cla_out[NORTH] (signal_dspin_v_cla_inc[x][y]); + clusters[x][y+1]->p_cla_in[SOUTH] (signal_dspin_v_cla_inc[x][y]); + clusters[x][y]->p_cla_in[NORTH] (signal_dspin_v_cla_dec[x][y]); + clusters[x][y+1]->p_cla_out[SOUTH] (signal_dspin_v_cla_dec[x][y]); + } + } + } + std::cout << std::endl << "Vertical connections done" << std::endl; + + // East & West boundary cluster connections + for (size_t y = 0; y < (Y_SIZE); y++) + { + clusters[0][y]->p_cmd_in[WEST] (signal_dspin_bound_cmd_in[0][y][WEST]); + clusters[0][y]->p_cmd_out[WEST] (signal_dspin_bound_cmd_out[0][y][WEST]); + clusters[X_SIZE-1][y]->p_cmd_in[EAST] (signal_dspin_bound_cmd_in[X_SIZE-1][y][EAST]); + clusters[X_SIZE-1][y]->p_cmd_out[EAST] (signal_dspin_bound_cmd_out[X_SIZE-1][y][EAST]); + + clusters[0][y]->p_rsp_in[WEST] (signal_dspin_bound_rsp_in[0][y][WEST]); + clusters[0][y]->p_rsp_out[WEST] (signal_dspin_bound_rsp_out[0][y][WEST]); + clusters[X_SIZE-1][y]->p_rsp_in[EAST] (signal_dspin_bound_rsp_in[X_SIZE-1][y][EAST]); + clusters[X_SIZE-1][y]->p_rsp_out[EAST] (signal_dspin_bound_rsp_out[X_SIZE-1][y][EAST]); + + clusters[0][y]->p_m2p_in[WEST] (signal_dspin_bound_m2p_in[0][y][WEST]); + clusters[0][y]->p_m2p_out[WEST] (signal_dspin_bound_m2p_out[0][y][WEST]); + clusters[X_SIZE-1][y]->p_m2p_in[EAST] (signal_dspin_bound_m2p_in[X_SIZE-1][y][EAST]); + clusters[X_SIZE-1][y]->p_m2p_out[EAST] (signal_dspin_bound_m2p_out[X_SIZE-1][y][EAST]); + + clusters[0][y]->p_p2m_in[WEST] (signal_dspin_bound_p2m_in[0][y][WEST]); + clusters[0][y]->p_p2m_out[WEST] (signal_dspin_bound_p2m_out[0][y][WEST]); + clusters[X_SIZE-1][y]->p_p2m_in[EAST] (signal_dspin_bound_p2m_in[X_SIZE-1][y][EAST]); + clusters[X_SIZE-1][y]->p_p2m_out[EAST] (signal_dspin_bound_p2m_out[X_SIZE-1][y][EAST]); + + clusters[0][y]->p_cla_in[WEST] (signal_dspin_bound_cla_in[0][y][WEST]); + clusters[0][y]->p_cla_out[WEST] (signal_dspin_bound_cla_out[0][y][WEST]); + clusters[X_SIZE-1][y]->p_cla_in[EAST] (signal_dspin_bound_cla_in[X_SIZE-1][y][EAST]); + clusters[X_SIZE-1][y]->p_cla_out[EAST] (signal_dspin_bound_cla_out[X_SIZE-1][y][EAST]); + } + + std::cout << std::endl << "West & East boundaries connections done" << std::endl; + + // North & South boundary clusters connections + for (size_t x = 0; x < X_SIZE; x++) + { + clusters[x][0]->p_cmd_in[SOUTH] (signal_dspin_bound_cmd_in[x][0][SOUTH]); + clusters[x][0]->p_cmd_out[SOUTH] (signal_dspin_bound_cmd_out[x][0][SOUTH]); + clusters[x][Y_SIZE-1]->p_cmd_in[NORTH] (signal_dspin_bound_cmd_in[x][Y_SIZE-1][NORTH]); + clusters[x][Y_SIZE-1]->p_cmd_out[NORTH] (signal_dspin_bound_cmd_out[x][Y_SIZE-1][NORTH]); + + clusters[x][0]->p_rsp_in[SOUTH] (signal_dspin_bound_rsp_in[x][0][SOUTH]); + clusters[x][0]->p_rsp_out[SOUTH] (signal_dspin_bound_rsp_out[x][0][SOUTH]); + clusters[x][Y_SIZE-1]->p_rsp_in[NORTH] (signal_dspin_bound_rsp_in[x][Y_SIZE-1][NORTH]); + clusters[x][Y_SIZE-1]->p_rsp_out[NORTH] (signal_dspin_bound_rsp_out[x][Y_SIZE-1][NORTH]); + + clusters[x][0]->p_m2p_in[SOUTH] (signal_dspin_bound_m2p_in[x][0][SOUTH]); + clusters[x][0]->p_m2p_out[SOUTH] (signal_dspin_bound_m2p_out[x][0][SOUTH]); + clusters[x][Y_SIZE-1]->p_m2p_in[NORTH] (signal_dspin_bound_m2p_in[x][Y_SIZE-1][NORTH]); + clusters[x][Y_SIZE-1]->p_m2p_out[NORTH] (signal_dspin_bound_m2p_out[x][Y_SIZE-1][NORTH]); + + clusters[x][0]->p_p2m_in[SOUTH] (signal_dspin_bound_p2m_in[x][0][SOUTH]); + clusters[x][0]->p_p2m_out[SOUTH] (signal_dspin_bound_p2m_out[x][0][SOUTH]); + clusters[x][Y_SIZE-1]->p_p2m_in[NORTH] (signal_dspin_bound_p2m_in[x][Y_SIZE-1][NORTH]); + clusters[x][Y_SIZE-1]->p_p2m_out[NORTH] (signal_dspin_bound_p2m_out[x][Y_SIZE-1][NORTH]); + + clusters[x][0]->p_cla_in[SOUTH] (signal_dspin_bound_cla_in[x][0][SOUTH]); + clusters[x][0]->p_cla_out[SOUTH] (signal_dspin_bound_cla_out[x][0][SOUTH]); + clusters[x][Y_SIZE-1]->p_cla_in[NORTH] (signal_dspin_bound_cla_in[x][Y_SIZE-1][NORTH]); + clusters[x][Y_SIZE-1]->p_cla_out[NORTH] (signal_dspin_bound_cla_out[x][Y_SIZE-1][NORTH]); + } + + std::cout << std::endl << "North & South boundaries connections done" << std::endl; + + std::cout << std::endl; + + //////////////////////////////////////////////////////// + // Simulation + /////////////////////////////////////////////////////// + + sc_start(sc_core::sc_time(0, SC_NS)); + signal_resetn = false; + signal_irq_false = false; + + // set network boundaries signals default values + // for all boundary clusters but the IO cluster + for (size_t x = 0; x < X_SIZE ; x++) + { + for (size_t y = 0; y < Y_SIZE ; y++) + { + for (size_t face = 0; face < 4; face++) + { + if ( (x != X_SIZE-1) or (y != Y_SIZE-1) or (face != NORTH) ) + { + signal_dspin_bound_cmd_in [x][y][face].write = false; + signal_dspin_bound_cmd_in [x][y][face].read = true; + signal_dspin_bound_cmd_out[x][y][face].write = false; + signal_dspin_bound_cmd_out[x][y][face].read = true; + + signal_dspin_bound_rsp_in [x][y][face].write = false; + signal_dspin_bound_rsp_in [x][y][face].read = true; + signal_dspin_bound_rsp_out[x][y][face].write = false; + signal_dspin_bound_rsp_out[x][y][face].read = true; + } + + signal_dspin_bound_m2p_in [x][y][face].write = false; + signal_dspin_bound_m2p_in [x][y][face].read = true; + signal_dspin_bound_m2p_out[x][y][face].write = false; + signal_dspin_bound_m2p_out[x][y][face].read = true; + + signal_dspin_bound_p2m_in [x][y][face].write = false; + signal_dspin_bound_p2m_in [x][y][face].read = true; + signal_dspin_bound_p2m_out[x][y][face].write = false; + signal_dspin_bound_p2m_out[x][y][face].read = true; + + signal_dspin_bound_cla_in [x][y][face].write = false; + signal_dspin_bound_cla_in [x][y][face].read = true; + signal_dspin_bound_cla_out[x][y][face].write = false; + signal_dspin_bound_cla_out[x][y][face].read = true; + } + } + } + + // set default values for VCI signals connected to unused ports on iobus + signal_vci_tgt_memc.rspval = false; + signal_vci_tgt_xicu.rspval = false; + for ( size_t p = 0 ; p < NB_PROCS_MAX ; p++ ) signal_vci_ini_proc[p].cmdval = false; + + sc_start(sc_core::sc_time(1, SC_NS)); + signal_resetn = true; + + if (gettimeofday(&t1, NULL) != 0) + { + perror("gettimeofday"); + return EXIT_FAILURE; + } + + // variable used for IRQ trace + bool prev_irq_bdev = false; + bool prev_irq_mtty_rx[8]; + bool prev_irq_proc[16][16][4]; + + for( size_t x = 0 ; x<8 ; x++ ) prev_irq_mtty_rx[x] = false; + + for( size_t x = 0 ; x<16 ; x++ ) + for( size_t y = 0 ; y<16 ; y++ ) + for( size_t i = 0 ; i<4 ; i++ ) prev_irq_proc[x][y][i] = false; + + for (uint64_t n = 1; n < ncycles && !stop_called; n++) + { + // Monitor a specific address for L1 & L2 caches + // clusters[0][0]->proc[0]->cache_monitor(0x110002C078ULL); + // clusters[1][1]->memc->cache_monitor(0x110002c078ULL); + + // stats display + if( (n % 5000000) == 0) + { + + if (gettimeofday(&t2, NULL) != 0) + { + perror("gettimeofday"); + return EXIT_FAILURE; + } + + ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000; + ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000; + std::cerr << "platform clock frequency " + << (double) 5000000 / (double) (ms2 - ms1) << "Khz" << std::endl; + + if (gettimeofday(&t1, NULL) != 0) + { + perror("gettimeofday"); + return EXIT_FAILURE; + } + } + + // trace display + if ( trace_ok and (n > trace_from) ) + { + std::cout << "****************** cycle " << std::dec << n ; + std::cout << " ************************************************" << std::endl; + + size_t l = 0; + size_t x = 0; + size_t y = 0; + + if ( trace_proc_ok ) + { + l = trace_proc_id % NB_PROCS_MAX ; + x = (trace_proc_id / NB_PROCS_MAX) >> Y_WIDTH ; + y = (trace_proc_id / NB_PROCS_MAX) & ((1<proc[l]->print_trace(1); + clusters[x][y]->signal_vci_ini_proc[l].print_trace(proc_signame.str()); + + std::ostringstream xicu_signame; + xicu_signame << "[SIG]XICU_" << x << "_" << y ; + clusters[x][y]->xicu->print_trace(0); + clusters[x][y]->signal_vci_tgt_xicu.print_trace(xicu_signame.str()); + } + + if ( trace_memc_ok ) + { + x = trace_memc_id >> Y_WIDTH; + y = trace_memc_id & ((1<memc->print_trace(); + clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str()); + clusters[x][y]->signal_vci_xram.print_trace(sxram.str()); + } + + // trace coherence signals + // clusters[0][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_0]"); + // clusters[0][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_0_1]"); + // clusters[1][0]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_0]"); + // clusters[1][1]->signal_dspin_m2p_proc[0].print_trace("[CC_M2P_1_1]"); + + // clusters[0][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_0]"); + // clusters[0][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_0_1]"); + // clusters[1][0]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_0]"); + // clusters[1][1]->signal_dspin_p2m_proc[0].print_trace("[CC_P2M_1_1]"); + + // trace xbar(s) m2p + // clusters[0][0]->xbar_m2p->print_trace(); + // clusters[1][0]->xbar_m2p->print_trace(); + // clusters[0][1]->xbar_m2p->print_trace(); + // clusters[1][1]->xbar_m2p->print_trace(); + + // trace router(s) m2p + // clusters[0][0]->router_m2p->print_trace(); + // clusters[1][0]->router_m2p->print_trace(); + // clusters[0][1]->router_m2p->print_trace(); + // clusters[1][1]->router_m2p->print_trace(); + + // trace external ioc + bdev->print_trace(); + signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT"); + signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); + + // trace external iopic + iopic->print_trace(); + signal_vci_tgt_iopi.print_trace("[SIG]IOPI_TGT"); + signal_vci_ini_iopi.print_trace("[SIG]IOPI_INI"); + + // trace internal tty + // clusters[0][0]->mtty->print_trace(); + // clusters[0][0]->signal_vci_tgt_mtty.print_trace("[SIG]MTTY"); + + } // end trace + + if (0) + { + // trace BDV interrupts events + if ( signal_irq_bdev.read() != prev_irq_bdev ) + { + prev_irq_bdev = signal_irq_bdev.read(); + std::cout << std::dec << "@@@ IRQ_BDEV = " << signal_irq_bdev.read() + << " at cycle " << n << std::endl; + } + + // trace TTY interrupts events + for ( size_t x = 0 ; x < 8 ; x++ ) + { + if ( signal_irq_mtty_rx[x].read() != prev_irq_mtty_rx[x] ) + { + prev_irq_mtty_rx[x] = signal_irq_mtty_rx[x].read(); + std::cout << std::dec << "@@@ IRQ_MTTY["<signal_proc_irq[i] != prev_irq_proc[x][y][i] ) + { + prev_irq_proc[x][y][i] = clusters[x][y]->signal_proc_irq[i]; + std::cout << std::dec << "@@@ IRQ_PROC["<signal_proc_irq[i] + << " at cycle " << n << std::endl; + } + } + + // trace VCI transactions on IOPIC and XCU(0,0) + signal_vci_tgt_iopi.print_trace("@@@ IOPI_TGT"); + signal_vci_ini_iopi.print_trace("@@@ IOPI_INI"); + clusters[0][0]->signal_vci_tgt_xicu.print_trace("@@@ XCU_0_0"); + } + + sc_start(sc_core::sc_time(1, SC_NS)); + } + // Free memory + for (size_t i = 0 ; i < (X_SIZE * Y_SIZE) ; i++) + { + size_t x = i / (Y_SIZE); + size_t y = i % (Y_SIZE); + delete clusters[x][y]; + } + + return EXIT_SUCCESS; +} + + +void handler(int dummy = 0) +{ + stop_called = true; + sc_stop(); +} + +void voidhandler(int dummy = 0) {} + +int sc_main (int argc, char *argv[]) +{ + signal(SIGINT, handler); + signal(SIGPIPE, voidhandler); + + try { + return _main(argc, argv); + } catch (std::exception &e) { + std::cout << e.what() << std::endl; + } catch (...) { + std::cout << "Unknown exception occured" << std::endl; + throw; + } + return 1; +} + + +// Local Variables: +// tab-width: 3 +// c-basic-offset: 3 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 Index: /branches/fault_tolerance/platforms/tsar_generic_leti/top.desc =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_leti/top.desc (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_leti/top.desc (revision 724) @@ -0,0 +1,78 @@ + +# -*- python -*- + +# internal VCI parameters values +vci_cell_size_int = 4 +vci_cell_size_ext = 8 + +vci_plen_size = 8 +vci_addr_size = 40 +vci_rerror_size = 1 +vci_clen_size = 1 +vci_rflag_size = 1 +vci_srcid_size = 14 +vci_pktid_size = 4 +vci_trdid_size = 4 +vci_wrplen_size = 1 + +# DSPIN network parameters values +dspin_cmd_flit_size = 39 +dspin_rsp_flit_size = 32 + +todo = Platform('caba', 'top.cpp', + + uses = [ + Uses('caba:tsar_leti_cluster', + vci_data_width_int = vci_cell_size_int, + vci_data_width_ext = vci_cell_size_ext, + dspin_cmd_width = dspin_cmd_flit_size, + dspin_rsp_width = dspin_rsp_flit_size), + + Uses('caba:vci_dspin_target_wrapper', + cell_size = vci_cell_size_int, + dspin_cmd_width = dspin_cmd_flit_size, + dspin_rsp_width = dspin_rsp_flit_size), + + Uses('caba:vci_dspin_initiator_wrapper', + cell_size = vci_cell_size_int, + dspin_cmd_width = dspin_cmd_flit_size, + dspin_rsp_width = dspin_rsp_flit_size), + + Uses('caba:vci_local_crossbar', + cell_size = vci_cell_size_int), + + Uses('caba:vci_framebuffer', + cell_size = vci_cell_size_int), + + Uses('caba:vci_multi_nic', + cell_size = vci_cell_size_int), + + Uses('caba:vci_chbuf_dma', + cell_size = vci_cell_size_int), + + Uses('caba:vci_block_device_tsar', + cell_size = vci_cell_size_int), + + Uses('caba:vci_multi_tty', + cell_size = vci_cell_size_int), + + Uses('caba:vci_iopic', + cell_size = vci_cell_size_int), + + Uses('common:elf_file_loader'), + + Uses('common:plain_file_loader'), + ], + + # default VCI parameters (global variables) + cell_size = vci_cell_size_int, + plen_size = vci_plen_size, + addr_size = vci_addr_size, + rerror_size = vci_rerror_size, + clen_size = vci_clen_size, + rflag_size = vci_rflag_size, + srcid_size = vci_srcid_size, + pktid_size = vci_pktid_size, + trdid_size = vci_trdid_size, + wrplen_size = vci_wrplen_size, +) Index: /branches/fault_tolerance/platforms/tsar_generic_leti/tsar_leti_cluster/caba/metadata/tsar_leti_cluster.sd =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_leti/tsar_leti_cluster/caba/metadata/tsar_leti_cluster.sd (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_leti/tsar_leti_cluster/caba/metadata/tsar_leti_cluster.sd (revision 724) @@ -0,0 +1,106 @@ + +# -*- python -*- + +Module('caba:tsar_leti_cluster', + classname = 'soclib::caba::TsarLetiCluster', + tmpl_parameters = [ + parameter.Int('dspin_cmd_width'), + parameter.Int('dspin_rsp_width'), + parameter.Module('vci_param_int', default = 'caba:vci_param', + cell_size = parameter.Reference('vci_data_width_int')), + parameter.Module('vci_param_ext', default = 'caba:vci_param', + cell_size = parameter.Reference('vci_data_width_ext')), + ], + + header_files = [ '../source/include/tsar_leti_cluster.h', + ], + + implementation_files = [ '../source/src/tsar_leti_cluster.cpp', + ], + + uses = [ + Uses('caba:base_module'), + Uses('common:mapping_table'), + Uses('common:iss2'), + + Uses('caba:vci_cc_vcache_wrapper', + cell_size = parameter.Reference('vci_data_width_int'), + dspin_in_width = parameter.Reference('dspin_cmd_width'), + dspin_out_width = parameter.Reference('dspin_rsp_width'), + iss_t = 'common:gdb_iss', + gdb_iss_t = 'common:mips32el'), + + Uses('caba:vci_mem_cache', + memc_cell_size_int = parameter.Reference('vci_data_width_int'), + memc_cell_size_ext = parameter.Reference('vci_data_width_ext'), + dspin_in_width = parameter.Reference('dspin_rsp_width'), + dspin_out_width = parameter.Reference('dspin_cmd_width')), + + Uses('caba:vci_simple_ram', + cell_size = parameter.Reference('vci_data_width_ext')), + + Uses('caba:vci_xicu', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_local_crossbar', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:dspin_local_crossbar', + flit_width = parameter.Reference('dspin_cmd_width')), + + Uses('caba:dspin_local_crossbar', + flit_width = parameter.Reference('dspin_rsp_width')), + + Uses('caba:dspin_router', + flit_width = parameter.Reference('dspin_cmd_width')), + + Uses('caba:dspin_router', + flit_width = parameter.Reference('dspin_rsp_width')), + + Uses('caba:vci_multi_tty', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_block_device_tsar', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_dspin_target_wrapper', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_dspin_initiator_wrapper', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('common:elf_file_loader'), + ], + + ports = [ + Port('caba:bit_in', 'p_resetn', auto = 'resetn'), + Port('caba:clock_in', 'p_clk', auto = 'clock'), + + Port('caba:dspin_output', 'p_cmd_out', [4], + dspin_data_size = parameter.Reference('dspin_cmd_width')), + Port('caba:dspin_input', 'p_cmd_in', [4], + dspin_data_size = parameter.Reference('dspin_cmd_width')), + + Port('caba:dspin_output', 'p_rsp_out', [4], + dspin_data_size = parameter.Reference('dspin_rsp_width')), + Port('caba:dspin_input', 'p_rsp_in', [4], + dspin_data_size = parameter.Reference('dspin_rsp_width')), + + Port('caba:dspin_output', 'p_m2p_out', [4], + dspin_data_size = parameter.Reference('dspin_cmd_width')), + Port('caba:dspin_input', 'p_m2p_in', [4], + dspin_data_size = parameter.Reference('dspin_cmd_width')), + + Port('caba:dspin_output', 'p_p2m_out', [4], + dspin_data_size = parameter.Reference('dspin_rsp_width')), + Port('caba:dspin_input', 'p_p2m_in', [4], + dspin_data_size = parameter.Reference('dspin_rsp_width')), + + Port('caba:dspin_output', 'p_cla_out', [4], + dspin_data_size = parameter.Reference('dspin_cmd_width')), + Port('caba:dspin_input', 'p_cla_in', [4], + dspin_data_size = parameter.Reference('dspin_cmd_width')), + ], +) + + Index: /branches/fault_tolerance/platforms/tsar_generic_leti/tsar_leti_cluster/caba/source/include/tsar_leti_cluster.h =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_leti/tsar_leti_cluster/caba/source/include/tsar_leti_cluster.h (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_leti/tsar_leti_cluster/caba/source/include/tsar_leti_cluster.h (revision 724) @@ -0,0 +1,193 @@ +////////////////////////////////////////////////////////////////////////////// +// File: tsar_leti_cluster.h +// Author: Alain Greiner +// Copyright: UPMC/LIP6 +// Date : march 2013 +// This program is released under the GNU public license +////////////////////////////////////////////////////////////////////////////// + +#ifndef SOCLIB_CABA_TSAR_LETI_CLUSTER_H +#define SOCLIB_CABA_TSAR_LETI_CLUSTER_H + +#include +#include +#include +#include +#include +#include + +#include "gdbserver.h" +#include "mapping_table.h" +#include "mips32.h" +#include "vci_simple_ram.h" +#include "vci_xicu.h" +#include "vci_local_crossbar.h" +#include "dspin_local_crossbar.h" +#include "vci_dspin_initiator_wrapper.h" +#include "vci_dspin_target_wrapper.h" +#include "dspin_router.h" +#include "vci_multi_tty.h" +#include "vci_block_device_tsar.h" +#include "vci_mem_cache.h" +#include "vci_cc_vcache_wrapper.h" + +namespace soclib { namespace caba { + +/////////////////////////////////////////////////////////////////////////// +template class TsarLetiCluster +/////////////////////////////////////////////////////////////////////////// + : public soclib::caba::BaseModule +{ + public: + + // Used in destructor + size_t m_nprocs; + + // Ports + sc_in p_clk; + sc_in p_resetn; + + soclib::caba::DspinOutput *p_cmd_out; + soclib::caba::DspinInput *p_cmd_in; + + soclib::caba::DspinOutput *p_rsp_out; + soclib::caba::DspinInput *p_rsp_in; + + soclib::caba::DspinOutput *p_m2p_out; + soclib::caba::DspinInput *p_m2p_in; + + soclib::caba::DspinOutput *p_p2m_out; + soclib::caba::DspinInput *p_p2m_in; + + soclib::caba::DspinOutput *p_cla_out; + soclib::caba::DspinInput *p_cla_in; + + // interrupt signals + sc_signal signal_false; + sc_signal signal_proc_irq[16]; + sc_signal signal_irq_mtty; + sc_signal signal_irq_memc; + sc_signal signal_irq_bdev; + + // DSPIN signals between DSPIN routers and local_crossbars + DspinSignals signal_dspin_cmd_l2g_d; + DspinSignals signal_dspin_cmd_g2l_d; + DspinSignals signal_dspin_rsp_l2g_d; + DspinSignals signal_dspin_rsp_g2l_d; + DspinSignals signal_dspin_m2p_l2g_c; + DspinSignals signal_dspin_m2p_g2l_c; + DspinSignals signal_dspin_clack_l2g_c; + DspinSignals signal_dspin_clack_g2l_c; + DspinSignals signal_dspin_p2m_l2g_c; + DspinSignals signal_dspin_p2m_g2l_c; + + // Direct VCI signals + VciSignals signal_vci_ini_proc[4]; + VciSignals signal_vci_ini_mdma; + VciSignals signal_vci_ini_bdev; + VciSignals signal_vci_ini_chbuf; + + VciSignals signal_vci_tgt_memc; + VciSignals signal_vci_tgt_xicu; + VciSignals signal_vci_tgt_mdma; + VciSignals signal_vci_tgt_mtty; + VciSignals signal_vci_tgt_bdev; + VciSignals signal_vci_tgt_fbuf; + VciSignals signal_vci_tgt_mnic; + VciSignals signal_vci_tgt_chbuf; + VciSignals signal_vci_tgt_simh; + + VciSignals signal_vci_g2l; + VciSignals signal_vci_l2g; + + // Coherence DSPIN signals to local crossbar + DspinSignals signal_dspin_m2p_memc; + DspinSignals signal_dspin_clack_memc; + DspinSignals signal_dspin_p2m_memc; + DspinSignals signal_dspin_m2p_proc[4]; + DspinSignals signal_dspin_clack_proc[4]; + DspinSignals signal_dspin_p2m_proc[4]; + + // external RAM to MEMC VCI signal + VciSignals signal_vci_xram; + + // Components + + VciCcVCacheWrapper >* proc[4]; + + VciMemCache* memc; + + VciXicu* xicu; + + VciSimpleRam* xram; + + VciMultiTty* mtty; + + VciBlockDeviceTsar* bdev; + + VciLocalCrossbar* xbar_cmd; + + VciDspinInitiatorWrapper* wi_gate; + + VciDspinTargetWrapper* wt_gate; + + DspinLocalCrossbar* xbar_m2p; + DspinLocalCrossbar* xbar_p2m; + DspinLocalCrossbar* xbar_cla; + + DspinRouter* router_cmd; + DspinRouter* router_rsp; + DspinRouter* router_m2p; + DspinRouter* router_p2m; + DspinRouter* router_cla; + + TsarLetiCluster( sc_module_name insname, + size_t nb_procs, // processors + size_t x, // x coordinate + size_t y, // y coordinate + size_t cluster, // y + ymax*x + const soclib::common::MappingTable &mtd, // internal + const soclib::common::MappingTable &mtx, // external + uint32_t reset_address, // boot address + size_t x_width, // x field bits + size_t y_width, // y field bits + size_t l_width, // l field bits + size_t tgtid_memc, + size_t tgtid_xicu, + size_t tgtid_mtty, + size_t tgtid_bdev, + const char* disk_pathname, + size_t memc_ways, + size_t memc_sets, + size_t l1_i_ways, + size_t l1_i_sets, + size_t l1_d_ways, + size_t l1_d_sets, + size_t xram_latency, // external ram + const Loader &loader, + uint32_t frozen_cycles, + uint32_t trace_start_cycle, + bool trace_proc_ok, + uint32_t trace_proc_id, + bool trace_memc_ok, + uint32_t trace_memc_id ); + + ~TsarLetiCluster(); + +}; +}} + +#endif Index: /branches/fault_tolerance/platforms/tsar_generic_leti/tsar_leti_cluster/caba/source/src/tsar_leti_cluster.cpp =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_leti/tsar_leti_cluster/caba/source/src/tsar_leti_cluster.cpp (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_leti/tsar_leti_cluster/caba/source/src/tsar_leti_cluster.cpp (revision 724) @@ -0,0 +1,588 @@ +////////////////////////////////////////////////////////////////////////////// +// File: tsar_leti_cluster.cpp +// Author: Alain Greiner +// Copyright: UPMC/LIP6 +// Date : february 2014 +// This program is released under the GNU public license +////////////////////////////////////////////////////////////////////////////// + +#include "../include/tsar_leti_cluster.h" + +namespace soclib { +namespace caba { + +//////////////////////////////////////////////////////////////////////////////////// +template TsarLetiCluster::TsarLetiCluster( +//////////////////////////////////////////////////////////////////////////////////// + sc_module_name insname, + size_t nb_procs, + size_t x_id, + size_t y_id, + size_t cluster_xy, + const soclib::common::MappingTable &mtd, + const soclib::common::MappingTable &mtx, + uint32_t reset_address, + size_t x_width, + size_t y_width, + size_t l_width, + size_t tgtid_memc, + size_t tgtid_xicu, + size_t tgtid_mtty, + size_t tgtid_bdev, + const char* disk_pathname, + size_t memc_ways, + size_t memc_sets, + size_t l1_i_ways, + size_t l1_i_sets, + size_t l1_d_ways, + size_t l1_d_sets, + size_t xram_latency, + const Loader &loader, + uint32_t frozen_cycles, + uint32_t trace_start_cycle, + bool trace_proc_ok, + uint32_t trace_proc_id, + bool trace_memc_ok, + uint32_t trace_memc_id ) + : soclib::caba::BaseModule(insname), + m_nprocs(nb_procs), + p_clk("clk"), + p_resetn("resetn") + +{ + ///////////////////////////////////////////////////////////////////////////// + // Vectors of ports definition and allocation + ///////////////////////////////////////////////////////////////////////////// + + p_cmd_in = alloc_elems > ("p_cmd_in", 4); + p_cmd_out = alloc_elems > ("p_cmd_out", 4); + + p_rsp_in = alloc_elems > ("p_rsp_in", 4); + p_rsp_out = alloc_elems > ("p_rsp_out", 4); + + p_m2p_in = alloc_elems > ("p_m2p_in", 4); + p_m2p_out = alloc_elems > ("p_m2p_out", 4); + + p_p2m_in = alloc_elems > ("p_p2m_in", 4); + p_p2m_out = alloc_elems > ("p_p2m_out", 4); + + p_cla_in = alloc_elems > ("p_cla_in", 4); + p_cla_out = alloc_elems > ("p_cla_out", 4); + + ///////////////////////////////////////////////////////////////////////////// + // Components definition and allocation + ///////////////////////////////////////////////////////////////////////////// + + // The processor is a MIPS32 wrapped in the GDB server + // the reset address is defined by the reset_address argument + typedef GdbServer mips_iss; + mips_iss::setResetAddress( reset_address ); + + for (size_t p = 0; p < nb_procs; p++) + { + uint32_t global_proc_id = cluster_xy * nb_procs + p; + uint32_t global_cc_id = (cluster_xy << l_width) + p; + bool trace_ok = trace_proc_ok and (trace_proc_id == global_proc_id); + + std::ostringstream sproc; + sproc << "proc_" << x_id << "_" << y_id << "_" << p; + proc[p] = new VciCcVCacheWrapper( + sproc.str().c_str(), + global_proc_id, // GLOBAL PROC_ID + mtd, // Mapping Table + IntTab(cluster_xy,p), // SRCID + global_cc_id, // GLOBAL_CC_ID + 8, // ITLB ways + 8, // ITLB sets + 8, // DTLB ways + 8, // DTLB sets + l1_i_ways,l1_i_sets, 16, // ICACHE size + l1_d_ways,l1_d_sets, 16, // DCACHE size + 4, // WBUF nlines + 4, // WBUF nwords + x_width, + y_width, + frozen_cycles, // max frozen cycles + trace_start_cycle, + trace_ok ); + } + + ///////////////////////////////////////////////////////////////////////////// + bool trace_ok = trace_memc_ok and (trace_memc_id == cluster_xy); + std::ostringstream smemc; + smemc << "memc_" << x_id << "_" << y_id; + memc = new VciMemCache( + smemc.str().c_str(), + mtd, // Mapping Table direct space + mtx, // Mapping Table external space + IntTab(cluster_xy), // SRCID external space + IntTab(cluster_xy, tgtid_memc), // TGTID direct space + x_width, // Number of x bits in platform + y_width, // Number of y bits in platform + memc_ways, memc_sets, 16, // CACHE SIZE + 3, // MAX NUMBER OF COPIES + 4096, // HEAP SIZE + 8, // TRANSACTION TABLE DEPTH + 8, // UPDATE TABLE DEPTH + 8, // INVALIDATE TABLE DEPTH + trace_start_cycle, + trace_ok ); + + ///////////////////////////////////////////////////////////////////////////// + std::ostringstream sxram; + sxram << "xram_" << x_id << "_" << y_id; + xram = new VciSimpleRam( + sxram.str().c_str(), + IntTab(cluster_xy), + mtx, + loader, + xram_latency); + + ///////////////////////////////////////////////////////////////////////////// + std::ostringstream sxicu; + sxicu << "xicu_" << x_id << "_" << y_id; + xicu = new VciXicu( + sxicu.str().c_str(), + mtd, // mapping table + IntTab(cluster_xy, tgtid_xicu), // TGTID_D + 16, // number of timer IRQs + 16, // number of hard IRQs + 16, // number of soft IRQs + 16 ); // number of output IRQs + + ///////////////////////////////////////////////////////////////////////////// + size_t nb_initiators = nb_procs; + size_t nb_targets = 2; + + if ((x_id == 0) and (y_id == 0)) // cluster(0,0) + { + nb_initiators = nb_procs + 1; + nb_targets = 4; + } + + std::ostringstream s_xbar_cmd; + xbar_cmd = new VciLocalCrossbar( + s_xbar_cmd.str().c_str(), + mtd, // mapping table + cluster_xy, // cluster id + nb_initiators, // number of local initiators + nb_targets, // number of local targets + 0 ); // default target + + wi_gate = new VciDspinInitiatorWrapper( + "wi_gate", + x_width + y_width + l_width); + + wt_gate = new VciDspinTargetWrapper( + "wt_gate", + x_width + y_width + l_width); + + ///////////////////////////////////////////////////////////////////////////// + std::ostringstream s_xbar_m2p; + s_xbar_m2p << "xbar_m2p_" << x_id << "_" << y_id; + xbar_m2p = new DspinLocalCrossbar( + s_xbar_m2p.str().c_str(), + mtd, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, l_width, + 1, // number of local sources + nb_procs, // number of local dests + 2, 2, // fifo depths + true, // CMD + false, // don't use local routing table + true ); // broadcast + + ///////////////////////////////////////////////////////////////////////////// + std::ostringstream s_xbar_p2m; + s_xbar_p2m << "xbar_p2m_" << x_id << "_" << y_id; + xbar_p2m = new DspinLocalCrossbar( + s_xbar_p2m.str().c_str(), + mtd, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, 0, // l_width unused on p2m network + nb_procs, // number of local sources + 1, // number of local dests + 2, 2, // fifo depths + false, // RSP + false, // don't use local routing table + false ); // no broadcast + + ///////////////////////////////////////////////////////////////////////////// + std::ostringstream s_xbar_cla; + s_xbar_cla << "xbar_cla_" << x_id << "_" << y_id; + xbar_cla = new DspinLocalCrossbar( + s_xbar_cla.str().c_str(), + mtd, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, l_width, + 1, // number of local sources + nb_procs, // number of local dests + 2, 2, // fifo depths + true, // CMD + false, // don't use local routing table + false); // no broadcast + + ///////////////////////////////////////////////////////////////////////////// + std::ostringstream s_router_cmd; + s_router_cmd << "router_cmd_" << x_id << "_" << y_id; + router_cmd = new DspinRouter( + s_router_cmd.str().c_str(), + x_id,y_id, // coordinate in the mesh + x_width, y_width, // x & y fields width + 4,4); // input & output fifo depths + + ///////////////////////////////////////////////////////////////////////////// + std::ostringstream s_router_rsp; + s_router_rsp << "router_rsp_" << x_id << "_" << y_id; + router_rsp = new DspinRouter( + s_router_rsp.str().c_str(), + x_id,y_id, // coordinates in mesh + x_width, y_width, // x & y fields width + 4,4); // input & output fifo depths + + ///////////////////////////////////////////////////////////////////////////// + std::ostringstream s_router_m2p; + s_router_m2p << "router_m2p_" << x_id << "_" << y_id; + router_m2p = new DspinRouter( + s_router_m2p.str().c_str(), + x_id,y_id, // coordinate in the mesh + x_width, y_width, // x & y fields width + 4,4, // input & output fifo depths + true); // broadcast supported + + ///////////////////////////////////////////////////////////////////////////// + std::ostringstream s_router_p2m; + s_router_p2m << "router_p2m_" << x_id << "_" << y_id; + router_p2m = new DspinRouter( + s_router_p2m.str().c_str(), + x_id,y_id, // coordinates in mesh + x_width, y_width, // x & y fields width + 4,4); // input & output fifo depths + + ///////////////////////////////////////////////////////////////////////////// + std::ostringstream s_router_cla; + s_router_cla << "router_cla_" << x_id << "_" << y_id; + router_cla = new DspinRouter( + s_router_cla.str().c_str(), + x_id,y_id, // coordinate in the mesh + x_width, y_width, // x & y fields width + 4,4); // input & output fifo depths + + // backup BDV and TTY peripherals in cluster(0,0) + bdev = NULL; + mtty = NULL; + if ((x_id == 0) and (y_id == 0)) + { + ///////////////////////////////////////////// + bdev = new VciBlockDeviceTsar( + "bdev", + mtd, + IntTab(cluster_xy, nb_procs), + IntTab(cluster_xy, tgtid_bdev), + disk_pathname, + 512, + 64 ); // burst size + + ///////////////////////////////////////////// + mtty = new VciMultiTty( + "mtty", + IntTab(cluster_xy, tgtid_mtty), + mtd, + "tty_backup", NULL ); + } + + std::cout << std::endl; + + //////////////////////////////////// + // Connections are defined here + //////////////////////////////////// + + //////////////////////// ROUTERS + router_cmd->p_clk (this->p_clk); + router_cmd->p_resetn (this->p_resetn); + router_rsp->p_clk (this->p_clk); + router_rsp->p_resetn (this->p_resetn); + router_m2p->p_clk (this->p_clk); + router_m2p->p_resetn (this->p_resetn); + router_p2m->p_clk (this->p_clk); + router_p2m->p_resetn (this->p_resetn); + router_cla->p_clk (this->p_clk); + router_cla->p_resetn (this->p_resetn); + + // loop on N/S/E/W ports + for (size_t i = 0; i < 4; i++) + { + router_cmd->p_out[i] (this->p_cmd_out[i]); + router_cmd->p_in[i] (this->p_cmd_in[i]); + + router_rsp->p_out[i] (this->p_rsp_out[i]); + router_rsp->p_in[i] (this->p_rsp_in[i]); + + router_m2p->p_out[i] (this->p_m2p_out[i]); + router_m2p->p_in[i] (this->p_m2p_in[i]); + + router_p2m->p_out[i] (this->p_p2m_out[i]); + router_p2m->p_in[i] (this->p_p2m_in[i]); + + router_cla->p_out[i] (this->p_cla_out[i]); + router_cla->p_in[i] (this->p_cla_in[i]); + } + + router_cmd->p_out[4] (signal_dspin_cmd_g2l_d); + router_cmd->p_in[4] (signal_dspin_cmd_l2g_d); + + router_rsp->p_out[4] (signal_dspin_rsp_g2l_d); + router_rsp->p_in[4] (signal_dspin_rsp_l2g_d); + + router_m2p->p_out[4] (signal_dspin_m2p_g2l_c); + router_m2p->p_in[4] (signal_dspin_m2p_l2g_c); + + router_p2m->p_out[4] (signal_dspin_p2m_g2l_c); + router_p2m->p_in[4] (signal_dspin_p2m_l2g_c); + + router_cla->p_out[4] (signal_dspin_clack_g2l_c); + router_cla->p_in[4] (signal_dspin_clack_l2g_c); + + std::cout << " - routers connected" << std::endl; + + ///////////////////// CMD DSPIN local crossbar direct + xbar_cmd->p_clk (this->p_clk); + xbar_cmd->p_resetn (this->p_resetn); + xbar_cmd->p_initiator_to_up (signal_vci_l2g); + xbar_cmd->p_target_to_up (signal_vci_g2l); + + xbar_cmd->p_to_target[tgtid_memc] (signal_vci_tgt_memc); + xbar_cmd->p_to_target[tgtid_xicu] (signal_vci_tgt_xicu); + + for (size_t p = 0; p < nb_procs; p++) + xbar_cmd->p_to_initiator[p] (signal_vci_ini_proc[p]); + + if ((x_id == 0) and (y_id == 0)) // cluster(0,0) + { + xbar_cmd->p_to_target[tgtid_mtty] (signal_vci_tgt_mtty); + xbar_cmd->p_to_target[tgtid_bdev] (signal_vci_tgt_bdev); + xbar_cmd->p_to_initiator[nb_procs] (signal_vci_ini_bdev); + } + + wi_gate->p_clk (this->p_clk); + wi_gate->p_resetn (this->p_resetn); + wi_gate->p_vci (signal_vci_l2g); + wi_gate->p_dspin_cmd (signal_dspin_cmd_l2g_d); + wi_gate->p_dspin_rsp (signal_dspin_rsp_g2l_d); + + wt_gate->p_clk (this->p_clk); + wt_gate->p_resetn (this->p_resetn); + wt_gate->p_vci (signal_vci_g2l); + wt_gate->p_dspin_cmd (signal_dspin_cmd_g2l_d); + wt_gate->p_dspin_rsp (signal_dspin_rsp_l2g_d); + + std::cout << " - CMD & RSP Direct crossbar connected" << std::endl; + + ////////////////////// M2P DSPIN local crossbar coherence + xbar_m2p->p_clk (this->p_clk); + xbar_m2p->p_resetn (this->p_resetn); + xbar_m2p->p_global_out (signal_dspin_m2p_l2g_c); + xbar_m2p->p_global_in (signal_dspin_m2p_g2l_c); + xbar_m2p->p_local_in[0] (signal_dspin_m2p_memc); + for (size_t p = 0; p < nb_procs; p++) + xbar_m2p->p_local_out[p] (signal_dspin_m2p_proc[p]); + + std::cout << " - M2P Coherence crossbar connected" << std::endl; + + ////////////////////////// P2M DSPIN local crossbar coherence + xbar_p2m->p_clk (this->p_clk); + xbar_p2m->p_resetn (this->p_resetn); + xbar_p2m->p_global_out (signal_dspin_p2m_l2g_c); + xbar_p2m->p_global_in (signal_dspin_p2m_g2l_c); + xbar_p2m->p_local_out[0] (signal_dspin_p2m_memc); + for (size_t p = 0; p < nb_procs; p++) + xbar_p2m->p_local_in[p] (signal_dspin_p2m_proc[p]); + + std::cout << " - P2M Coherence crossbar connected" << std::endl; + + ////////////////////// CLACK DSPIN local crossbar coherence + xbar_cla->p_clk (this->p_clk); + xbar_cla->p_resetn (this->p_resetn); + xbar_cla->p_global_out (signal_dspin_clack_l2g_c); + xbar_cla->p_global_in (signal_dspin_clack_g2l_c); + xbar_cla->p_local_in[0] (signal_dspin_clack_memc); + for (size_t p = 0; p < nb_procs; p++) + xbar_cla->p_local_out[p] (signal_dspin_clack_proc[p]); + + std::cout << " - CLA Coherence crossbar connected" << std::endl; + + //////////////////////////////////// Processors + for (size_t p = 0; p < nb_procs; p++) + { + proc[p]->p_clk (this->p_clk); + proc[p]->p_resetn (this->p_resetn); + proc[p]->p_vci (signal_vci_ini_proc[p]); + proc[p]->p_dspin_m2p (signal_dspin_m2p_proc[p]); + proc[p]->p_dspin_p2m (signal_dspin_p2m_proc[p]); + proc[p]->p_dspin_clack (signal_dspin_clack_proc[p]); + + for ( size_t j = 0 ; j < 6 ; j++) + { + if ( j < 4 ) proc[p]->p_irq[j] (signal_proc_irq[4*p + j]); + else proc[p]->p_irq[j] (signal_false); + } + } + + std::cout << " - Processors connected" << std::endl; + + ///////////////////////////////////// XICU + xicu->p_clk (this->p_clk); + xicu->p_resetn (this->p_resetn); + xicu->p_vci (signal_vci_tgt_xicu); + + for (size_t i = 0 ; i < 16 ; i++) + { + xicu->p_irq[i] (signal_proc_irq[i]); + } + + for (size_t i = 0; i < 16; i++) + { + if ((x_id == 0) and (y_id == 0)) // cluster (0,0) + { + if (i == 8) xicu->p_hwi[i] (signal_irq_memc); + else if (i == 9) xicu->p_hwi[i] (signal_irq_bdev); + else if (i == 10) xicu->p_hwi[i] (signal_irq_mtty); + else xicu->p_hwi[i] (signal_false); + } + else // other clusters + { + if (i == 1) xicu->p_hwi[i] (signal_irq_memc); + else xicu->p_hwi[i] (signal_false); + } + } + + std::cout << " - XICU connected" << std::endl; + + //////////////////////////////////////////////// MEMC + memc->p_clk (this->p_clk); + memc->p_resetn (this->p_resetn); + memc->p_irq (signal_irq_memc); + memc->p_vci_ixr (signal_vci_xram); + memc->p_vci_tgt (signal_vci_tgt_memc); + memc->p_dspin_p2m (signal_dspin_p2m_memc); + memc->p_dspin_m2p (signal_dspin_m2p_memc); + memc->p_dspin_clack (signal_dspin_clack_memc); + + std::cout << " - MEMC connected" << std::endl; + + /////////////////////////////////////////////// XRAM + xram->p_clk (this->p_clk); + xram->p_resetn (this->p_resetn); + xram->p_vci (signal_vci_xram); + + std::cout << " - XRAM connected" << std::endl; + + /////////////////////////////// Extra Components in cluster(0,0) + + if ((x_id == 0) and (y_id == 0)) + { + // BDEV + bdev->p_clk (this->p_clk); + bdev->p_resetn (this->p_resetn); + bdev->p_irq (signal_irq_bdev); + bdev->p_vci_target (signal_vci_tgt_bdev); + bdev->p_vci_initiator (signal_vci_ini_bdev); + + std::cout << " - BDEV connected" << std::endl; + + // MTTY (single channel) + mtty->p_clk (this->p_clk); + mtty->p_resetn (this->p_resetn); + mtty->p_vci (signal_vci_tgt_mtty); + mtty->p_irq[0] (signal_irq_mtty); + + std::cout << " - MTTY connected" << std::endl; + } +} // end constructor + + + +template TsarLetiCluster::~TsarLetiCluster() { + + dealloc_elems > (p_cmd_in, 4); + dealloc_elems >(p_cmd_out, 4); + + dealloc_elems > (p_rsp_in, 4); + dealloc_elems >(p_rsp_out, 4); + + dealloc_elems > (p_m2p_in, 4); + dealloc_elems >(p_m2p_out, 4); + + dealloc_elems > (p_p2m_in, 4); + dealloc_elems >(p_p2m_out, 4); + + dealloc_elems > (p_cla_in, 4); + dealloc_elems >(p_cla_out, 4); + + for (size_t p = 0; p < m_nprocs ; p++) + { + if ( proc[p] ) delete proc[p]; + } + + delete memc; + delete xram; + delete xicu; + delete xbar_cmd; + delete xbar_m2p; + delete xbar_p2m; + delete xbar_cla; + delete router_cmd; + delete router_rsp; + delete router_m2p; + delete router_p2m; + delete router_cla; + delete wi_gate; + delete wt_gate; + + if ( bdev ) + { + delete bdev; + } + + if ( mtty ) + { + delete mtty; + } +} + + +}} + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + + + Index: /branches/fault_tolerance/platforms/tsar_generic_xbar/Makefile =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_xbar/Makefile (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_xbar/Makefile (revision 724) @@ -0,0 +1,8 @@ +simul.x: top.cpp top.desc + soclib-cc -P -p top.desc -I. -o simul.x + +clean: + soclib-cc -x -p top.desc -I. + rm -rf *.o *.x term* + +.PHONY: simul.x Index: /branches/fault_tolerance/platforms/tsar_generic_xbar/scripts/counter_defs.py =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_xbar/scripts/counter_defs.py (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_xbar/scripts/counter_defs.py (revision 724) @@ -0,0 +1,177 @@ + +individual_metrics = [ 'req_trig_update', 'local_update', 'remote_update', 'update_cost', 'req_trig_m_inv', 'local_m_inv', 'remote_m_inv', 'm_inv_cost', 'broadcast', 'total_update', 'total_m_inv' ] +grouped_metrics = [ 'update_cost', 'm_inv_cost' ] +stacked_metrics = [ 'nonwrite_broadcast', 'write_broadcast', 'local_m_inv', 'remote_m_inv', 'local_update', 'remote_update' ] + +m_app_name = {} +m_app_name['mandel'] = "Mandelbrot" +m_app_name['filter'] = "Filter" +m_app_name['filt_ga'] = "Filter (opt.)" +m_app_name['histogram'] = "Histogram" +m_app_name['kmeans'] = "Kmeans" +m_app_name['barnes'] = "Barnes" +m_app_name['fmm'] = "FMM" +m_app_name['ocean'] = "Ocean" +m_app_name['raytrace'] = "Raytrace" +m_app_name['radiosity'] = "Radiosity" +m_app_name['waters'] = "Water Sp." +m_app_name['watern'] = "Water Nsq." +m_app_name['cholesky'] = "Cholesky" +m_app_name['lu'] = "LU" +m_app_name['fft'] = "FFT" +m_app_name['radix'] = "Radix" +m_app_name['fft_ga'] = "FFT" +m_app_name['radix_ga'] = "Radix" + +m_metric_id = {} +m_metric_tag = {} +m_metric_tag['counter_reset'] = "[000]" +m_metric_tag['ncycles'] = "[001]" +m_metric_tag['local_read'] = "[002]" +m_metric_tag['remote_read'] = "[003]" +m_metric_tag['read_cost'] = "[004]" +m_metric_tag['local_write'] = "[005]" +m_metric_tag['remote_write'] = "[006]" +m_metric_tag['write_flits_local'] = "[007]" +m_metric_tag['write_flits_remote'] = "[008]" +m_metric_tag['write_cost'] = "[009]" +m_metric_tag['local_ll'] = "[010]" +m_metric_tag['remote_ll'] = "[011]" +m_metric_tag['ll_cost'] = "[012]" +m_metric_tag['local_sc'] = "[013]" +m_metric_tag['remote_sc'] = "[014]" +m_metric_tag['sc_cost'] = "[015]" +m_metric_tag['local_cas'] = "[016]" +m_metric_tag['remote_cas'] = "[017]" +m_metric_tag['cas_cost'] = "[018]" +m_metric_tag['req_trig_update'] = "[019]" +m_metric_tag['local_update'] = "[020]" +m_metric_tag['remote_update'] = "[021]" +m_metric_tag['update_cost'] = "[022]" +m_metric_tag['req_trig_m_inv'] = "[023]" +m_metric_tag['local_m_inv'] = "[024]" +m_metric_tag['remote_m_inv'] = "[025]" +m_metric_tag['m_inv_cost'] = "[026]" +m_metric_tag['broadcast'] = "[027]" +m_metric_tag['local_cleanup'] = "[028]" +m_metric_tag['remote_cleanup'] = "[029]" +m_metric_tag['cleanup_cost'] = "[030]" +m_metric_tag['nb_read_miss'] = "[031]" +m_metric_tag['write_miss'] = "[032]" +m_metric_tag['write_dirty'] = "[033]" +m_metric_tag['read_hit_trt'] = "[034]" # Reads blocked by a hit in the TRT +m_metric_tag['trans_full_trt'] = "[035]" # Transactions blocked because the TRT is full +m_metric_tag['put'] = "[036]" +m_metric_tag['get'] = "[037]" +m_metric_tag['write_broadcast'] = "[038]" + +m_metric_tag['total_read'] = "[040]" +m_metric_tag['total_write'] = "[041]" +m_metric_tag['total_ll'] = "[042]" +m_metric_tag['total_sc'] = "[043]" +m_metric_tag['total_cas'] = "[044]" +m_metric_tag['total_update'] = "[045]" +m_metric_tag['total_m_inv'] = "[046]" +m_metric_tag['total_cleanup'] = "[047]" +m_metric_tag['total_direct'] = "[048]" + +m_metric_tag['nonwrite_broadcast'] = "[050]" +m_metric_tag['broadcast_cost'] = "[051]" +m_metric_tag['direct_cost'] = "[052]" +m_metric_tag['total_stacked'] = "|060]" + +all_metrics = m_metric_tag.keys() +all_tags = m_metric_tag.values() + +m_metric_name = {} +m_metric_name['counter_reset'] = "Counters reset at cycle" +m_metric_name['ncycles'] = "Number of Cycles" +m_metric_name['local_read'] = "Number of Local Reads (Miss in L1)" +m_metric_name['remote_read'] = "Number of Remote Reads (Miss in L1)" +m_metric_name['read_cost'] = "Read Cost" +m_metric_name['local_write'] = "Number of Local Writes" +m_metric_name['remote_write'] = "Number of Remote Writes" +m_metric_name['write_flits_local'] = "Number of Local Write Flits" +m_metric_name['write_flits_remote'] = "Number of Remote Write Flits" +m_metric_name['write_cost'] = "Write Cost" +m_metric_name['local_ll'] = "Number of Local LL" +m_metric_name['remote_ll'] = "Number of Remote LL" +m_metric_name['ll_cost'] = "LL Cost" +m_metric_name['local_sc'] = "Number of Local SC" +m_metric_name['remote_sc'] = "Number of Remote SC" +m_metric_name['sc_cost'] = "SC Cost" +m_metric_name['local_cas'] = "Number of Local CAS" +m_metric_name['remote_cas'] = "Number of Remote CAS" +m_metric_name['cas_cost'] = "CAS Cost" +m_metric_name['req_trig_update'] = "Number of Requests Triggering an Update" +m_metric_name['local_update'] = "Number of Local Updates" +m_metric_name['remote_update'] = "Number of Remote Updates" +m_metric_name['update_cost'] = "Update Cost" +m_metric_name['req_trig_m_inv'] = "Number of Requests Triggering a M.inv" +m_metric_name['local_m_inv'] = "Number of Local Multi Inval" +m_metric_name['remote_m_inv'] = "Number of Remote Multi Inval" +m_metric_name['m_inv_cost'] = "Multi Inval Cost" +m_metric_name['broadcast'] = "Number of Broadcasts" +m_metric_name['broadcast'] = "Total Number of Broadcasts" +m_metric_name['local_cleanup'] = "Number of Local Cleanups" +m_metric_name['remote_cleanup'] = "Number of Remote Cleanups" +m_metric_name['cleanup_cost'] = "Cleanup Cost" +m_metric_name['nb_read_miss'] = "Number of Read Miss (in L2)" +m_metric_name['write_miss'] = "Number of Write Miss (in L2)" +m_metric_name['write_dirty'] = "Number of Write Dirty (from L2 to Memory)" +m_metric_name['read_hit_trt'] = "Number of Reads Blocked by a Hit in TRT" # Reads blocked by a hit in the TRT +m_metric_name['trans_full_trt'] = "Number of Transactions Blocked because the TRT is Full" # Transactions blocked because the TRT is full +m_metric_name['put'] = "Number of PUT to Memory" +m_metric_name['get'] = "Number of GET from Memory" +m_metric_name['write_broadcast'] = "Number of Broadcasts Trig. by Writes" + +m_metric_name['total_read'] = "Total Number of Reads" +m_metric_name['total_write'] = "Total Number of Writes" +m_metric_name['total_ll'] = "Total Number of LL" +m_metric_name['total_sc'] = "Total Number of SC" +m_metric_name['total_cas'] = "Total Number of CAS" +m_metric_name['total_update'] = "Total Number of Updates" +m_metric_name['total_m_inv'] = "Total Number of Multi Inval" +m_metric_name['total_cleanup'] = "Total Number of Cleanups" +m_metric_name['total_direct'] = "Total Number of Direct Requests" +m_metric_name['nonwrite_broadcast'] = "Number of Broadcasts not Trig. by Writes" +m_metric_name['broadcast_cost'] = "Broadcast Cost" +m_metric_name['direct_cost'] = "Direct Requests Cost" +m_metric_name['total_stacked'] = "??" # Normalization factor + + + +m_metric_norm = {} # "N" (None), P (#procs), C (#cycles), W (#writes), R (#reads), D (#direct req -- R ou W), n (value with n proc(s)) +m_metric_norm['req_trig_update'] = "C" +m_metric_norm['local_update'] = "C" +m_metric_norm['remote_update'] = "C" +m_metric_norm['update_cost'] = "C" +m_metric_norm['req_trig_m_inv'] = "C" +m_metric_norm['local_m_inv'] = "C" +m_metric_norm['remote_m_inv'] = "C" +m_metric_norm['m_inv_cost'] = "C" +m_metric_norm['broadcast'] = "C" +m_metric_norm['total_update'] = "C" +m_metric_norm['total_m_inv'] = "C" + +m_norm_factor_name = {} +m_norm_factor_name['N'] = "" +m_norm_factor_name['P'] = "Normalized w.r.t.\\nthe Number of Processors" +m_norm_factor_name['C'] = "Normalized w.r.t.\\nthe Number of Cycles (x 1000)" +m_norm_factor_name['W'] = "Normalized w.r.t.\\nthe Number of Writes" +m_norm_factor_name['R'] = "Normalized w.r.t.\\nthe Number of Reads" +m_norm_factor_name['D'] = "Normalized w.r.t.\\nthe Number of Direct Requests" +m_norm_factor_name['1'] = "Normalized w.r.t.\\nthe Value on 1 Processor" +m_norm_factor_name['4'] = "Normalized w.r.t.\\nthe Value on 4 Processors" +m_norm_factor_name['8'] = "Normalized w.r.t.\\nthe Value on 8 Processors" +m_norm_factor_name['16'] = "Normalized w.r.t.\\nthe Value on 16 Processors" +m_norm_factor_name['32'] = "Normalized w.r.t.\\nthe Value on 32 Processors" +m_norm_factor_name['64'] = "Normalized w.r.t.\\nthe Value on 64 Processors" +m_norm_factor_name['128'] = "Normalized w.r.t.\\nthe Value on 128 Processors" +m_norm_factor_name['256'] = "Normalized w.r.t.\\nthe Value on 256 Processors" + + + +colors = [ "\"#008000\"", "\"#000080\"", "\"#BADC98\"", "\"#BA98DC\"", "\"#98DCBA\"", "\"#98BADC\"", "\"#BA9876\"", "\"#BA7698\"", "\"#98BA76\"", "\"#9876BA\"", "\"#76BA98\"", "\"#7698BA\"" ] + + Index: /branches/fault_tolerance/platforms/tsar_generic_xbar/scripts/create_graphs.py =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_xbar/scripts/create_graphs.py (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_xbar/scripts/create_graphs.py (revision 724) @@ -0,0 +1,527 @@ +#!/usr/bin/python + +import subprocess +import os +import re + + + +apps = [ 'histogram', 'mandel', 'filter', 'radix_ga', 'fft_ga', 'kmeans' ] +nb_procs = [ 1, 4, 8, 16, 32, 64, 128, 256 ] + +top_path = os.path.join(os.path.dirname(os.path.realpath(__file__)), "..") +scripts_path = os.path.join(top_path, 'scripts') +counter_defs_name = os.path.join(scripts_path, "counter_defs.py") + +exec(file(counter_defs_name)) + +gen_dir = 'generated' +graph_dir = 'graph' +template_dir = 'templates' +data_dir = 'data' + +log_init_name = 'log_init_' +log_term_name = 'log_term_' + +coherence_tmpl = os.path.join(scripts_path, template_dir, 'coherence_template.gp') # 1 graph per appli +speedup_tmpl = os.path.join(scripts_path, template_dir, 'speedup_template.gp') +metric_tmpl = os.path.join(scripts_path, template_dir, 'metric_template.gp') # 1 graph per metric +stacked_tmpl = os.path.join(scripts_path, template_dir, 'stacked_template.gp') + + + +def create_file(name, content): + file = open(name, 'w') + file.write(content) + file.close() + +def is_numeric(s): + try: + float(s) + return True + except ValueError: + return False + +def get_x_y(nb_procs): + x = 1 + y = 1 + to_x = True + while (x * y * 4 < nb_procs): + if to_x: + x = x * 2 + else: + y = y * 2 + to_x = not to_x + return x, y + + + +# We first fill the m_metric_id table +for metric in all_metrics: + for tag in all_tags: + if m_metric_tag[metric] == tag: + m_metric_id[tag] = metric + break + + +# We start by processing all the log files +# Term files are processed for exec time only +# Init files are processed for all metrics +exec_time = {} +metrics_val = {} +for app in apps: + exec_time[app] = {} + metrics_val[app] = {} + for i in nb_procs: + metrics_val[app][i] = {} + log_init_file = os.path.join(scripts_path, data_dir, app + '_' + log_init_name + str(i)) + log_term_file = os.path.join(scripts_path, data_dir, app + '_' + log_term_name + str(i)) + + # Term + lines = open(log_term_file, 'r') + for line in lines: + tokens = line[:-1].split() + if len(tokens) > 0 and tokens[0] == "[ELAPSED2]": + exec_time[app][i] = int(tokens[len(tokens) - 1]) + + # Init files + lines = open(log_init_file, 'r') + for line in lines: + tokens = line[:-1].split() + if len(tokens) == 0: + continue + tag = tokens[0] + value = tokens[len(tokens) - 1] + pattern = re.compile('\[0[0-9][0-9]\]') + if pattern.match(tag): + metric = m_metric_id[tag] + if (not metrics_val[app][i].has_key(metric) or tag == "[000]" or tag == "[001]"): + # We don't add cycles of all Memcaches (they must be the same for all) + metrics_val[app][i][metric] = int(value) + else: + metrics_val[app][i][metric] += int(value) + +# We make a 2nd pass to fill the derived fields, e.g. nb_total_updates +for app in apps: + for i in nb_procs: + x, y = get_x_y(i) + metrics_val[app][i]['total_read'] = metrics_val[app][i]['local_read'] + metrics_val[app][i]['remote_read'] + metrics_val[app][i]['total_write'] = metrics_val[app][i]['local_write'] + metrics_val[app][i]['remote_write'] + metrics_val[app][i]['total_ll'] = metrics_val[app][i]['local_ll'] + metrics_val[app][i]['remote_ll'] + metrics_val[app][i]['total_sc'] = metrics_val[app][i]['local_sc'] + metrics_val[app][i]['remote_sc'] + metrics_val[app][i]['total_cas'] = metrics_val[app][i]['local_cas'] + metrics_val[app][i]['remote_cas'] + metrics_val[app][i]['total_update'] = metrics_val[app][i]['local_update'] + metrics_val[app][i]['remote_update'] + metrics_val[app][i]['total_m_inv'] = metrics_val[app][i]['local_m_inv'] + metrics_val[app][i]['remote_m_inv'] + metrics_val[app][i]['total_cleanup'] = metrics_val[app][i]['local_cleanup'] + metrics_val[app][i]['remote_cleanup'] + metrics_val[app][i]['total_direct'] = metrics_val[app][i]['total_read'] + metrics_val[app][i]['total_write'] + metrics_val[app][i]['direct_cost'] = metrics_val[app][i]['read_cost'] + metrics_val[app][i]['write_cost'] + metrics_val[app][i]['broadcast_cost'] = metrics_val[app][i]['broadcast'] * (x * y - 1) + if metrics_val[app][i]['broadcast'] < metrics_val[app][i]['write_broadcast']: + # test to patch a bug in mem_cache + metrics_val[app][i]['nonwrite_broadcast'] = 0 + else: + metrics_val[app][i]['nonwrite_broadcast'] = metrics_val[app][i]['broadcast'] - metrics_val[app][i]['write_broadcast'] + + metrics_val[app][i]['total_stacked'] = 0 + for stacked_metric in stacked_metrics: + metrics_val[app][i]['total_stacked'] += metrics_val[app][i][stacked_metric] + + +print "mkdir -p", os.path.join(scripts_path, gen_dir) +subprocess.call([ 'mkdir', '-p', os.path.join(scripts_path, gen_dir) ]) + +print "mkdir -p", os.path.join(scripts_path, graph_dir) +subprocess.call([ 'mkdir', '-p', os.path.join(scripts_path, graph_dir) ]) + +############################################################ +### Graph 1 : Coherence traffic Cost per application ### +############################################################ + +for app in apps: + + data_coherence_name = os.path.join(scripts_path, gen_dir, app + '_coherence.dat') + gp_coherence_name = os.path.join(scripts_path, gen_dir, app + '_coherence.gp') + + # Creating the data file + width = 15 + content = "" + + for metric in [ '#nb_procs' ] + grouped_metrics: + content += metric + " " + nb_spaces = width - len(metric) + content += nb_spaces * ' ' + content += "\n" + + for i in nb_procs: + content += "%-15d " % i + for metric in grouped_metrics: + val = float(metrics_val[app][i][metric]) / exec_time[app][i] * 1000 + content += "%-15f " % val + content += "\n" + + create_file(data_coherence_name, content) + + # Creating the gp file + template_file = open(coherence_tmpl, 'r') + template = template_file.read() + + plot_str = "" + col = 2 + for metric in grouped_metrics: + if metric != grouped_metrics[0]: + plot_str += ", \\\n " + plot_str += "\"" + data_coherence_name + "\" using ($1):($" + str(col) + ") lc rgb " + colors[col - 2] + " title \"" + m_metric_name[metric] + "\" with linespoint" + col += 1 + gp_commands = template % dict(app_name = m_app_name[app], nb_procs = nb_procs[-1] + 1, plot_str = plot_str, svg_name = os.path.join(graph_dir, app + '_coherence')) + + create_file(gp_coherence_name, gp_commands) + + # Calling gnuplot + print "gnuplot", gp_coherence_name + subprocess.call([ 'gnuplot', gp_coherence_name ]) + + +############################################################ +### Graph 2 : Speedup per Application ### +############################################################ + +for app in apps: + + data_speedup_name = os.path.join(scripts_path, gen_dir, app + '_speedup.dat') + gp_speedup_name = os.path.join(scripts_path, gen_dir, app + '_speedup.gp') + + # Creating data file + width = 15 + content = "#nb_procs" + nb_spaces = width - len(content) + content += nb_spaces * ' ' + content += "speedup\n" + + for i in nb_procs: + content += "%-15d " % i + val = exec_time[app][i] + content += "%-15f\n" % (exec_time[app][1] / float(val)) + + plot_str = "\"" + data_speedup_name + "\" using ($1):($2) lc rgb \"#654387\" title \"Speedup\" with linespoint" + + create_file(data_speedup_name, content) + + # Creating the gp file + template_file = open(speedup_tmpl, 'r') + template = template_file.read() + + gp_commands = template % dict(appli = m_app_name[app], nb_procs = nb_procs[-1] + 1, plot_str = plot_str, svg_name = os.path.join(graph_dir, app + '_speedup')) + + create_file(gp_speedup_name, gp_commands) + + # Calling gnuplot + print "gnuplot", gp_speedup_name + subprocess.call([ 'gnuplot', gp_speedup_name ]) + + +############################################################ +### Graph 3 : All speedups on the same Graph ### +############################################################ + +# This graph uses the same template as the graph 2 + +data_speedup_name = os.path.join(scripts_path, gen_dir, 'all_speedup.dat') +gp_speedup_name = os.path.join(scripts_path, gen_dir, 'all_speedup.gp') + +# Creating data file +width = 15 +content = "#nb_procs" +nb_spaces = width - len(content) +content += (nb_spaces + 1) * ' ' +for app in apps: + content += app + " " + content += (width - len(app)) * " " +content += "\n" + +for i in nb_procs: + content += "%-15d " % i + for app in apps: + val = exec_time[app][i] + content += "%-15f " % (exec_time[app][1] / float(val)) + content += "\n" + +create_file(data_speedup_name, content) + +# Creating gp file +template_file = open(speedup_tmpl, 'r') +template = template_file.read() + +plot_str = "" +col = 2 +for app in apps: + if app != apps[0]: + plot_str += ", \\\n " + plot_str += "\"" + data_speedup_name + "\" using ($1):($" + str(col) + ") lc rgb %s title \"" % (colors[col - 2]) + m_app_name[app] + "\" with linespoint" + col += 1 + +gp_commands = template % dict(appli = "All Applications", nb_procs = nb_procs[-1] + 1, plot_str = plot_str, svg_name = os.path.join(graph_dir, 'all_speedup')) + +create_file(gp_speedup_name, gp_commands) + +# Calling gnuplot +print "gnuplot", gp_speedup_name +subprocess.call([ 'gnuplot', gp_speedup_name ]) + + +############################################################ +### Graph 4 : Graph per metric ### +############################################################ + +# The following section creates the graphs grouped by measure (e.g. #broadcasts) +# The template file cannot be easily created otherwise it would not be generic +# in many ways. This is why it is mainly created here. +# Graphs are created for metric in the "individual_metrics" list + +for metric in individual_metrics: + data_metric_name = os.path.join(scripts_path, gen_dir, metric + '.dat') + gp_metric_name = os.path.join(scripts_path, gen_dir, metric + '.gp') + + # Creating the gp file + # Setting xtics, i.e. number of procs for each application + xtics_str = "(" + first = True + xpos = 1 + app_labels = "" + for num_appli in range(0, len(apps)): + for i in nb_procs: + if not first: + xtics_str += ", " + first = False + if i == nb_procs[0]: + xpos_first = xpos + xtics_str += "\"%d\" %.1f" % (i, xpos) + xpos_last = xpos + xpos += 1.5 + xpos += 0.5 + app_name_xpos = float((xpos_first + xpos_last)) / 2 + app_labels += "set label \"%s\" at first %f,character 1 center font\"Times,12\"\n" % (m_app_name[apps[num_appli]], app_name_xpos) + xtics_str += ")" + + xmax_val = xpos + 0.5 + + # Writing the lines of "plot" + plot_str = "" + xpos = 0 + first = True + column = 2 + for i in range(0, len(nb_procs)): + if not first: + plot_str += ", \\\n " + first = False + plot_str += "\"%s\" using ($1+%.1f):($%d) lc rgb %s notitle with boxes" % (data_metric_name, xpos, column, colors[i]) + column += 1 + xpos += 1.5 + + template_file = open(metric_tmpl, 'r') + template = template_file.read() + + gp_commands = template % dict(xtics_str = xtics_str, app_labels = app_labels, ylabel_str = m_metric_name[metric], norm_factor_str = m_norm_factor_name[m_metric_norm[metric]], xmax_val = xmax_val, plot_str = plot_str, svg_name = os.path.join(graph_dir, metric)) + + create_file(gp_metric_name, gp_commands) + + # Creating the data file + width = 15 + content = "#x_pos" + nb_spaces = width - len(content) + content += nb_spaces * ' ' + for i in nb_procs: + content += "%-15d" % i + content += "\n" + + x_pos = 1 + for app in apps: + # Computation of x_pos + content += "%-15f" % x_pos + x_pos += len(nb_procs) * 1.5 + 0.5 + for i in nb_procs: + if m_metric_norm[metric] == "N": + content += "%-15d" % (metrics_val[app][i][metric]) + elif m_metric_norm[metric] == "P": + content += "%-15f" % (float(metrics_val[app][i][metric]) / i) + elif m_metric_norm[metric] == "C": + content += "%-15f" % (float(metrics_val[app][i][metric]) / exec_time[app][i] * 1000) + elif m_metric_norm[metric] == "W": + content += "%-15f" % (float(metrics_val[app][i][metric]) / float(metrics_val[app][i]['total_write'])) # Number of writes + elif m_metric_norm[metric] == "R": + content += "%-15f" % (float(metrics_val[app][i][metric]) / float(metrics_val[app][i]['total_read'])) # Number of reads + elif m_metric_norm[metric] == "D": + content += "%-15f" % (float(metrics_val[app][i][metric]) / float(metrics_val[app][i]['total_direct'])) # Number of req. + elif is_numeric(m_metric_norm[metric]): + content += "%-15f" % (float(metrics_val[app][i][metric]) / float(metrics_val[app][int(m_metric_norm[metric])][metric])) + else: + assert(False) + + app_name = m_app_name[app] + content += "#" + app_name + "\n" + + create_file(data_metric_name, content) + + # Calling gnuplot + print "gnuplot", gp_metric_name + subprocess.call([ 'gnuplot', gp_metric_name ]) + + +############################################################ +### Graph 5 : Stacked histogram with counters ### +############################################################ + +# The following section creates a stacked histogram containing +# the metrics in the "stacked_metric" list +# It is normalized per application w.r.t the values on 256 procs + +data_stacked_name = os.path.join(scripts_path, gen_dir, 'stacked.dat') +gp_stacked_name = os.path.join(scripts_path, gen_dir, 'stacked.gp') + +norm_factor_value = 256 + +# Creating the gp file +template_file = open(stacked_tmpl, 'r') +template = template_file.read() + +xtics_str = "(" +first = True +xpos = 1 +app_labels = "" +for num_appli in range(0, len(apps)): + for i in nb_procs: + if not first: + xtics_str += ", " + first = False + if i == nb_procs[0]: + xpos_first = xpos + xtics_str += "\"%d\" %d -1" % (i, xpos) + xpos_last = xpos + xpos += 1 + xpos += 1 + app_name_xpos = float((xpos_first + xpos_last)) / 2 + app_labels += "set label \"%s\" at first %f,character 1 center font\"Times,12\"\n" % (m_app_name[apps[num_appli]], app_name_xpos) +xtics_str += ")" + +plot_str = "newhistogram \"\"" +n = 1 +for stacked_metric in stacked_metrics: + plot_str += ", \\\n " + "'" + data_stacked_name + "'" + " using " + str(n) + " lc rgb " + colors[n] + " title \"" + m_metric_name[stacked_metric] + "\"" + n += 1 + +ylabel_str = "Breakdown of Coherence Traffic Normalized w.r.t. \\nthe Values on %d Processors" % norm_factor_value +content = template % dict(svg_name = os.path.join(graph_dir, 'stacked'), xtics_str = xtics_str, plot_str = plot_str, ylabel_str = ylabel_str, app_labels = app_labels) + +create_file(gp_stacked_name, content) + +# Creating the data file +# Values are normalized by application, w.r.t. the number of requests for a given number of procs +content = "#" +for stacked_metric in stacked_metrics: + content += stacked_metric + content += ' ' + ' ' * (15 - len(stacked_metric)) +content += "\n" +for app in apps: + if app != apps[0]: + for i in range(0, len(stacked_metrics)): + content += "%-15f" % 0.0 + content += "\n" + for i in nb_procs: + for stacked_metric in stacked_metrics: + content += "%-15f" % (float(metrics_val[app][i][stacked_metric]) / metrics_val[app][norm_factor_value]['total_stacked']) + content += "\n" + +create_file(data_stacked_name, content) +# Calling gnuplot +print "gnuplot", gp_stacked_name +subprocess.call([ 'gnuplot', gp_stacked_name ]) + + + +################################################################################# +### Graph 6 : Stacked histogram with coherence cost compared to r/w cost ### +################################################################################# + +# The following section creates pairs of stacked histograms, normalized w.r.t. the first one. +# The first one contains the cost of reads and writes, the second contains the cost +# of m_inv, m_up and broadcasts (extrapolated) + +data_cost_filename = os.path.join(scripts_path, gen_dir, 'relative_cost.dat') +gp_cost_filename = os.path.join(scripts_path, gen_dir, 'relative_cost.gp') + +direct_cost_metrics = [ 'read_cost', 'write_cost' ] +coherence_cost_metrics = ['update_cost', 'm_inv_cost', 'broadcast_cost' ] + +# Creating the gp file +template_file = open(stacked_tmpl, 'r') +template = template_file.read() + +xtics_str = "(" +first = True +xpos = 1.5 +app_labels = "" +for num_appli in range(0, len(apps)): + first_proc = True + for i in nb_procs: + if i > 4: + if not first: + xtics_str += ", " + first = False + if first_proc: + first_proc = False + xpos_first = xpos + xtics_str += "\"%d\" %f -1" % (i, xpos) + xpos_last = xpos + xpos += 3 + app_name_xpos = float((xpos_first + xpos_last)) / 2 + app_labels += "set label \"%s\" at first %f,character 1 center font\"Times,12\"\n" % (m_app_name[apps[num_appli]], app_name_xpos) + xpos += 1 +xtics_str += ")" + +plot_str = "newhistogram \"\"" +n = 1 +for cost_metric in direct_cost_metrics + coherence_cost_metrics: + plot_str += ", \\\n " + "'" + data_cost_filename + "'" + " using " + str(n) + " lc rgb " + colors[n] + " title \"" + m_metric_name[cost_metric] + "\"" + n += 1 + +ylabel_str = "Coherence Cost Compared to Direct Requests Cost,\\nNormalized per Application for each Number of Processors" +content = template % dict(svg_name = os.path.join(graph_dir, 'rel_cost'), xtics_str = xtics_str, plot_str = plot_str, ylabel_str = ylabel_str, app_labels = app_labels) + +create_file(gp_cost_filename, content) + +# Creating the data file +# Values are normalized by application, w.r.t. the number of requests for a given number of procs +content = "#" +for cost_metric in direct_cost_metrics: + content += cost_metric + content += ' ' + ' ' * (15 - len(cost_metric)) +for cost_metric in coherence_cost_metrics: + content += cost_metric + content += ' ' + ' ' * (15 - len(cost_metric)) +content += "\n" +for app in apps: + if app != apps[0]: + for i in range(0, len(direct_cost_metrics) + len(coherence_cost_metrics)): + content += "%-15f" % 0.0 + content += "\n" + for i in nb_procs: + if i > 4: + for cost_metric in direct_cost_metrics: + content += "%-15f" % (float(metrics_val[app][i][cost_metric]) / metrics_val[app][i]['direct_cost']) + for cost_metric in coherence_cost_metrics: + content += "%-15f" % 0.0 + content += "\n" + for cost_metric in direct_cost_metrics: + content += "%-15f" % 0.0 + for cost_metric in coherence_cost_metrics: + content += "%-15f" % (float(metrics_val[app][i][cost_metric]) / metrics_val[app][i]['direct_cost']) + content += "\n" + for i in range(0, len(direct_cost_metrics) + len(coherence_cost_metrics)): + content += "%-15f" % 0.0 + content += "\n" + +create_file(data_cost_filename, content) +# Calling gnuplot +print "gnuplot", gp_cost_filename +subprocess.call([ 'gnuplot', gp_cost_filename ]) + + Index: /branches/fault_tolerance/platforms/tsar_generic_xbar/scripts/gen_arch_info_large.sh =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_xbar/scripts/gen_arch_info_large.sh (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_xbar/scripts/gen_arch_info_large.sh (revision 724) @@ -0,0 +1,236 @@ +#! /bin/bash + +#-------------------------------------------------------------------- +# File : gen_arch_info_large.sh +#-------------------------------------------------------------------- + +NB_TTY=4 +TTY_CHANNEL_SIZE=0x10 +TTY_SIZE=0x1000 + +DMA_SIZE=0x1000 +XICU_SIZE=0x1000 +BDEV_SIZE=0x1000 +# FrameBuffer size +#FB_SIZE=0x80000 +FB_SIZE=0x200000 + +MEMC_TGTID=0 +XICU_TGTID=1 +MDMA_TGTID=2 +MTTY_TGTID=3 +BDEV_TGTID=4 +MNIC_TGTID=5 +BROM_TGTID=6 +CDMA_TGTID=7 +SIMH_TGTID=8 +FBUF_TGTID=9 + + +# Physical address width +ADDR_WIDTH=32 + +# Default values +DEFAULT_X_MAX=8 +DEFAULT_Y_MAX=8 +DEFAULT_CPU_PER_CLUSTER=4 + +function mymin() +{ + if test $1 -lt $2 ; then + echo "$1" + else + echo "$2" + fi +} + +#------------------------ + +X_MAX=${1-$DEFAULT_X_MAX} +Y_MAX=${2-$DEFAULT_Y_MAX} +NPROCS=$DEFAULT_CPU_PER_CLUSTER + +#------------------------ +CLUSTER_INC=$((0x80000000 / (X_MAX * Y_MAX) * 2)) +MAX_MEMC_SIZE=$((0x40000000 / (X_MAX * Y_MAX))) +size=$(mymin $MAX_MEMC_SIZE $((0x04000000))) +MEMC_SIZE=$(printf "0x%X" $size) + + +print_comments() +{ + date=$(date "+%c") + echo "# TSAR hardware description in BIB (Boot Information Block) format" + echo "# This file is autogenerated by the command: $0 $X_MAX $Y_MAX $NPROCS $BSCPU" + echo "# It is ready to be passed to info2bib utility so the binary format can be generated" + echo " " + echo "# $USER on $HOSTNAME $date" + echo " " + echo " " +} + +print_header() +{ + echo "[HEADER]" + echo " REVISION=1" + echo " ARCH=SOCLIB-TSAR" + echo " XMAX=$X_MAX" + echo " YMAX=$Y_MAX" + echo " CPU_NR=$NPROCS" + echo " BSCPU=$BSCPU" + echo " BSTTY=$BSTTY" + echo " BSDMA=$BSDMA" + echo " " + echo " " +} + +print_cluster() +{ + offset=$1 + cid=$2 + memc_base=$(printf "0x%X" $offset) + memc_size=$(printf "0x%X" $MEMC_SIZE) + xicu_base=$(printf "0x%X" $((offset + (CLUSTER_INC / 2) + (XICU_TGTID << 19)))) + dma_base=$(printf "0x%X" $((offset + (CLUSTER_INC / 2) + (MDMA_TGTID << 19)))) + + echo "[CLUSTER]" + echo " CID="$cid + echo " CPU_NR="$NPROCS + echo " DEV_NR=3" + echo " DEVID=RAM BASE=$memc_base SIZE=$memc_size IRQ=-1" + echo " DEVID=XICU BASE=$xicu_base SIZE=$DMA_SIZE IRQ=-1" + echo " DEVID=DMA BASE=$dma_base SIZE=$XICU_SIZE IRQ=8" + echo " " + echo " " +} + +print_io_cluster() +{ + offset=$1 + cid=$2 + memc_base=$(printf "0x%X" $offset) + memc_size=$(printf "0x%X" $MEMC_SIZE) + xicu_base=$(printf "0x%X" $((offset + (CLUSTER_INC / 2) + (XICU_TGTID << 19)))) + dma_base=$(printf "0x%X" $((offset + (CLUSTER_INC / 2) + (MDMA_TGTID << 19)))) + bdev_base=$(printf "0x%X" $((offset + (CLUSTER_INC / 2) + (BDEV_TGTID << 19)))) + tty_base=$(printf "0x%X" $((offset + (CLUSTER_INC / 2) + (MTTY_TGTID << 19)))) + fbf_base=$(printf "0x%X" $((offset + (CLUSTER_INC / 2) + (FBUF_TGTID << 19)))) + + echo "[CLUSTER]" + echo " CID="$cid + echo " CPU_NR="$NPROCS + echo " DEV_NR=9" + echo " DEVID=RAM BASE=$memc_base SIZE=$memc_size IRQ=-1" + echo " DEVID=XICU BASE=$xicu_base SIZE=$XICU_SIZE IRQ=-1" + echo " DEVID=DMA BASE=$dma_base SIZE=$DMA_SIZE IRQ=8" + echo " DEVID=BLKDEV BASE=$bdev_base SIZE=$BDEV_SIZE IRQ=31" + ntty=0 + irq=16 + while test $ntty -lt $NB_TTY + do + tty_base_i=$(printf "0x%X" $((tty_base + ntty * TTY_CHANNEL_SIZE))) + echo " DEVID=TTY BASE=$tty_base_i SIZE=$TTY_CHANNEL_SIZE IRQ=$irq" + irq=$((irq + 1)) + ntty=$((ntty + 1)) + done + echo " DEVID=FB BASE=$fbf_base SIZE=$FB_SIZE IRQ=-1" + echo " " + echo " " +} + +# Derive X_WIDTH form X_MAX +case $X_MAX in + 1) X_WIDTH=0 + ;; + + 2) X_WIDTH=1 + ;; + + [3-4]) X_WIDTH=2 + ;; + + [5-8]) X_WIDTH=3 + ;; + + *) X_WIDTH=4 + ;; +esac + +# Derive Y_WIDTH form Y_MAX +case $Y_MAX in + 1) Y_WIDTH=0 + ;; + + + 2) Y_WIDTH=1 + ;; + + [3-4]) Y_WIDTH=2 + ;; + + [5-8]) Y_WIDTH=3 + ;; + + *) Y_WIDTH=4 + ;; +esac + +x=0; y=0 +io_cid=$((0xbf >> (8 - X_WIDTH - Y_WIDTH))) +BSCPU=$(($io_cid * $NPROCS)) + +break_loop=0 +while test $x -lt $X_MAX +do + while test $y -lt $Y_MAX + do + cid=$((x * Y_MAX + y)) + offset=$((cid << (ADDR_WIDTH - X_WIDTH - Y_WIDTH))) + + if [ $cid -eq $io_cid ] + then + BSDMA=$(printf "0x%X" $((offset + (CLUSTER_INC / 2) + (MDMA_TGTID << 19)))) + BSTTY=$(printf "0x%X" $((offset + (CLUSTER_INC / 2) + (MTTY_TGTID << 19)))) + break_loop=1 + break + else + BSDMA="error" + fi + + y=$((y + 1)) + done + if test $break_loop -eq 1 ; then + break + fi + y=0 + x=$((x + 1)) +done + +# Generate the description +print_comments "$0" +print_header + +x=0; y=0 +while test $x -lt $X_MAX +do + while test $y -lt $Y_MAX + do + cid=$((x * Y_MAX + y)) + offset=$((cid << (ADDR_WIDTH - X_WIDTH - Y_WIDTH))) + + if [ $cid -eq $io_cid ] + then + print_io_cluster $offset $cid + else + print_cluster $offset $cid + fi + + y=$((y + 1)) + done + y=0 + x=$((x + 1)) +done + +#-------------------------------------------------------------------------# +# End of script # +#-------------------------------------------------------------------------# Index: /branches/fault_tolerance/platforms/tsar_generic_xbar/scripts/run_simus.py =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_xbar/scripts/run_simus.py (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_xbar/scripts/run_simus.py (revision 724) @@ -0,0 +1,351 @@ +#!/usr/bin/python + +import subprocess +import os +import sys + +#TODO: recopier les fichiers d'entrees dans le script en fonction de l'appli selectionnee +# Par exemple, tk14.O pour LU, img.raw pour ep_filter, etc. + +data_dir = 'data' +log_init_name = 'log_init_' +log_term_name = 'log_term_' + + +nb_procs = [ 4 ] +#nb_procs = [ 1, 4, 8, 16, 32, 64, 128, 256 ] +rerun_stats = True +use_omp = False + +#apps = [ 'histogram', 'mandel', 'filter', 'radix_ga', 'fft_ga', 'kmeans' ] +#apps = [ 'histogram', 'mandel', 'filter', 'radix_ga', 'fft_ga' ] +apps = [ 'filt_ga' ] + + +all_apps = [ 'mandel', 'filter', 'filt_ga', 'histogram', 'kmeans', 'barnes', 'fmm', 'ocean', 'raytrace', 'radiosity', 'waters', 'watern', 'cholesky', 'lu', 'fft', 'radix', 'fft_ga', 'radix_ga', 'kmeans' ] +splash2 = [ 'barnes', 'fmm', 'ocean', 'radiosity', 'raytrace', 'watern', 'waters', 'cholesky', 'lu', 'fft', 'radix' ] +splash2_ga = [ 'radix_ga', 'fft_ga' ] + + +config_name = os.path.join(os.path.dirname(os.path.realpath(__file__)), "config.py") +if not os.path.isfile(config_name): + help_str = ''' +You should create a file named config.py in this directory with the following definitions: + - apps_dir: path to almos-tsar-mipsel/apps directory + - almos_src_dir: path to almos source directory (for kernel and bootloader binaries) + - hdd_img_name: path to the hdd image to use +*** Stopping execution +''' + print help_str + sys.exit() + +exec(file(config_name)) + +top_path = os.path.join(os.path.dirname(os.path.realpath(__file__)), "..") + +splash2_dir = os.path.join(apps_dir, 'splash2/codes') +splash2_ga_dir = os.path.join(apps_dir, 'splash2_ga') + +scripts_path = os.path.join(top_path, 'scripts') +almos_path = os.path.join(top_path, 'almos') +arch_info_name = os.path.join(almos_path, "arch-info-gen.info") +arch_info_bib_name = os.path.join(almos_path, 'arch-info.bib') +hdd_img_file_name = os.path.join(almos_path, "hdd-img.bin") +shrc_file_name = os.path.join(almos_path, "shrc") +hard_config_name = os.path.join(almos_path, "hard_config.h") + +topcell_name = "top.cpp" + + +splash_app_dir = {} +splash_app_dir['barnes'] = 'apps/barnes' +splash_app_dir['fmm'] = 'apps/fmm' +splash_app_dir['ocean'] = 'apps/ocean/contiguous_partitions' +splash_app_dir['raytrace'] = 'apps/raytrace' +splash_app_dir['radiosity'] = 'apps/radiosity' +#splash_app_dir['volrend'] = 'apps/volrend' +splash_app_dir['watern'] = 'apps/water-nsquared' +splash_app_dir['waters'] = 'apps/water-spatial' + +splash_app_dir['cholesky'] = 'kernels/cholesky' +splash_app_dir['fft'] = 'kernels/fft' +splash_app_dir['lu'] = 'kernels/lu/contiguous_blocks' +splash_app_dir['radix'] = 'kernels/radix' + +splash_ga_app_dir = {} +splash_ga_app_dir['radix_ga'] = 'apps/radix' +splash_ga_app_dir['fft_ga'] = 'apps/fft' + + +def get_x_y(nb_procs): + x = 1 + y = 1 + to_x = True + while (x * y * 4 < nb_procs): + if to_x: + x = x * 2 + else: + y = y * 2 + to_x = not to_x + return x, y + + + +def gen_hard_config(x, y, hard_config): + header = ''' +/* Generated from run_simus.py */ + +#ifndef _HD_CONFIG_H +#define _HD_CONFIG_H + +#define X_SIZE %(x)d +#define Y_SIZE %(y)d +#define NB_CLUSTERS %(nb_clus)d +#define NB_PROCS_MAX 4 +#define NB_TASKS_MAX 8 + +#define NB_TIM_CHANNELS 32 +#define NB_DMA_CHANNELS 1 + +#define NB_TTY_CHANNELS 4 +#define NB_IOC_CHANNELS 1 +#define NB_NIC_CHANNELS 0 +#define NB_CMA_CHANNELS 0 + +#define USE_XICU 1 +#define IOMMU_ACTIVE 0 + +#define IRQ_PER_PROCESSOR 1 + +#endif //_HD_CONFIG_H +''' % dict(x = x, y = y, nb_clus = x * y) + file = open(hard_config, 'w') + file.write(header) + file.close() + + +def gen_arch_info(x, y, arch_info, arch_info_bib): + old_path = os.getcwd() + print "cd", scripts_path + os.chdir(scripts_path) + print "./gen_arch_info_large.sh", str(x), str(y), ">", arch_info + output = subprocess.Popen([ './gen_arch_info_large.sh', str(x), str(y) ], stdout = subprocess.PIPE).communicate()[0] + os.chdir(almos_path) + file = open(arch_info, 'w') + file.write(output) + file.close() + print "./info2bib -i", arch_info, "-o", arch_info_bib + subprocess.call([ './info2bib', '-i', arch_info, '-o', arch_info_bib ]) + print "cd", old_path + os.chdir(old_path) + + +def gen_sym_links(): + old_path = os.getcwd() + print "cd", almos_path + os.chdir(almos_path) + + target = os.path.join(almos_src_dir, 'tools/soclib-bootloader/bootloader-tsar-mipsel.bin') + link_name = 'bootloader-tsar-mipsel.bin' + if not os.path.isfile(link_name): + print "ln -s", target, link_name + os.symlink(target, link_name) + + target = os.path.join(almos_src_dir, 'kernel/obj.tsar/almix-tsar-mipsel.bin') + link_name = 'kernel-soclib.bin' + if not os.path.isfile(link_name): + print "ln -s", target, link_name + os.symlink(target, link_name) + + target = hdd_img_name + link_name = 'hdd-img.bin' + if not os.path.isfile(link_name): + print "ln -s", target, link_name + os.symlink(target, link_name) + + os.chdir(old_path) + + + +def compile_app(app_name, nprocs): + + if app_name in splash2: + app_dir_name = os.path.join(splash2_dir, splash_app_dir[app_name]) + elif app_name in splash2_ga: + app_dir_name = os.path.join(splash2_ga_dir, splash_ga_app_dir[app_name]) + else: + app_dir_name = os.path.join(apps_dir, app_name) + + old_path = os.getcwd() + print "cd", app_dir_name + os.chdir(app_dir_name) + + # Compilation process is different in splash and other apps + if app_name in splash2: + print "make clean" + subprocess.call([ 'make', 'clean' ]) + + print "rm Makefile" + subprocess.call([ 'rm', 'Makefile' ]) + + print "ln -s Makefile.soclib Makefile" + subprocess.call([ 'ln', '-s', 'Makefile.soclib', 'Makefile' ]) + + print "make" + subprocess.call([ 'make' ]) + + elif app_name in splash2_ga: + print "make clean" + subprocess.call([ 'make', 'clean' ]) + + print "make" + subprocess.call([ 'make' ]) + + else: + print "make clean" + subprocess.call([ 'make', 'clean' ]) + + print "make TARGET=tsar" + subprocess.call([ 'make', 'TARGET=tsar' ]) + + # Creation/Modification du shrc de almos + if (app_name == "boot_only"): + shrc = "exec -p 0 /bin/boot_onl\n" + elif (app_name == "mandel"): + shrc = "exec -p 0 /bin/mandel -n%(nproc)d\n" % dict(nproc = nprocs) + elif (app_name == "filter"): + #shrc = "exec -p 0 /bin/filter /etc/imgs.raw 512 512\n" + shrc = "exec -p 0 /bin/filter -l1024 -c1024 -n%(nproc)d /etc/img.raw\n" % dict(nproc = nprocs) + elif (app_name == "filt_ga"): + shrc = "exec -p 0 /bin/filt_ga -n%(nproc)d -i /etc/img.raw\n" % dict(nproc = nprocs) + elif (app_name == "histogram"): + shrc = "exec -p 0 /bin/histogra -n%(nproc)d /etc/histo.bmp\n" % dict(nproc = nprocs) + elif (app_name == "kmeans"): + shrc = "exec -p 0 /bin/kmeans -n %(nproc)d -p %(npoints)d\n" % dict(nproc = nprocs, npoints = 10000) # default npoints = 100000 + elif (app_name == "showimg"): + shrc = "exec -p 0 /bin/showimg -p1 -i /etc/lena.sgi -o /dev/fb0\n" + elif (app_name == "barnes"): + shrc = "exec -p 0 /bin/barnes -n%(nproc)d -b%(nbody)d\n" % dict(nproc = nprocs, nbody = 1024) + elif (app_name == "fmm"): + shrc = "exec -p 0 /bin/fmm -n%(nproc)d -p%(nparticles)d\n" % dict(nproc = nprocs, nparticles = 1024) + elif (app_name == "ocean"): + shrc = "exec -p 0 /bin/ocean -n%(nproc)d -m%(gridsize)d\n" % dict(nproc = nprocs, gridsize = 66) + elif (app_name == "radiosity"): + shrc = "exec -p 0 /bin/radiosit -n %(nproc)d -batch\n" % dict(nproc = nprocs) + elif (app_name == "raytrace"): + shrc = "exec -p 0 /bin/raytrace -n%(nproc)d /etc/tea.env\n" % dict(nproc = nprocs) + elif (app_name == "watern"): + shrc = "exec -p 0 /bin/watern -n%(nproc)d -m512\n" % dict(nproc = nprocs) + elif (app_name == "waters"): + shrc = "exec -p 0 /bin/waters -n%(nproc)d -m512\n" % dict(nproc = nprocs) + elif (app_name == "cholesky"): + shrc = "exec -p 0 /bin/cholesky -n%(nproc)d /etc/tk14.O\n" % dict(nproc = nprocs) + elif (app_name == "fft"): + shrc = "exec -p 0 /bin/fft -n%(nproc)d -m10\n" % dict(nproc = nprocs) + elif (app_name == "lu"): + shrc = "exec -p 0 /bin/lu -n%(nproc)d -m512\n" % dict(nproc = nprocs) + elif (app_name == "radix"): + shrc = "exec -p 0 /bin/radix -n%(nproc)d -k1024\n" % dict(nproc = nprocs) # test : 1024 ; simu : 65536 + elif (app_name == "radix_ga"): + shrc = "exec -p 0 /bin/radix_ga -p%(nproc)d -n262144\n" % dict(nproc = nprocs) # p = proc, n = num_keys + elif (app_name == "fft_ga"): + shrc = "exec -p 0 /bin/fft_ga -P%(nproc)d -M16\n" % dict(nproc = nprocs) + else: + assert(False) + + file = open(shrc_file_name, 'w') + file.write(shrc) + file.close() + + # Copie du binaire et du shrc dans l'image disque + print "mcopy -o -i", hdd_img_file_name, shrc_file_name, "::/etc/" + subprocess.call([ 'mcopy', '-o', '-i', hdd_img_file_name, shrc_file_name, '::/etc/' ]) + print "mcopy -o -i", hdd_img_file_name, app_name, "::/bin/" + subprocess.call([ 'mcopy', '-o', '-i', hdd_img_file_name, app_name, '::/bin/' ]) + + print "cd", old_path + os.chdir(old_path) +# end of compile_app + + +print "mkdir -p", os.path.join(scripts_path, data_dir) +subprocess.call([ 'mkdir', '-p', os.path.join(scripts_path, data_dir) ]) + +gen_sym_links() + +for i in nb_procs: + x, y = get_x_y(i) + nthreads = min(4, x * y) + gen_hard_config(x, y, hard_config_name) + gen_arch_info(x, y, arch_info_name, arch_info_bib_name) + + print "cd", top_path + os.chdir(top_path) + print "touch", topcell_name + subprocess.call([ 'touch', topcell_name ]) + print "make" + subprocess.call([ 'make' ]) + + for app in apps: + print "cd", top_path + os.chdir(top_path) + + compile_app(app, i) + + # Launch simulation + if use_omp: + print "./simul.x -THREADS", nthreads, ">", os.path.join(scripts_path, data_dir, app + '_' + log_init_name + str(i)) + output = subprocess.Popen([ './simul.x', '-THREADS', str(nthreads) ], stdout = subprocess.PIPE).communicate()[0] + else: + print "./simul.x >", os.path.join(scripts_path, data_dir, app + '_' + log_init_name + str(i)) + output = subprocess.Popen([ './simul.x' ], stdout = subprocess.PIPE).communicate()[0] + + + # Write simulation results to data directory + print "cd", scripts_path + os.chdir(scripts_path) + filename = os.path.join(data_dir, app + '_' + log_init_name + str(i)) + file = open(filename, 'w') + file.write(output) + file.close() + + filename = os.path.join(scripts_path, data_dir, app + '_' + log_term_name + str(i)) + print "mv", os.path.join(top_path, 'term1'), filename + subprocess.call([ 'mv', os.path.join(top_path, 'term1'), filename ]) + + if rerun_stats: + start2_found = False + end_found = False + for line in open(filename): + if "[START2]" in line: + start2 = line.split()[-1] + start2_found = True + if "[END]" in line: + end = line.split()[-1] + end_found = True + assert(start2_found and end_found) + + print "cd", top_path + os.chdir(top_path) + + # Relauching simulation with reset and dump of counters + if use_omp: + print "./simul.x -THREADS", nthreads, "--reset-counters %s --dump-counters %s >" % (start2, end), os.path.join(scripts_path, data_dir, app + '_' + log_init_name + str(i)) + output = subprocess.Popen([ './simul.x', '-THREADS', str(nthreads), '--reset-counters', start2, '--dump-counters', end ], stdout = subprocess.PIPE).communicate()[0] + else: + print "./simul.x --reset-counters %s --dump-counters %s >" % (start2, end), os.path.join(scripts_path, data_dir, app + '_' + log_init_name + str(i)) + output = subprocess.Popen([ './simul.x', '--reset-counters', start2, '--dump-counters', end ], stdout = subprocess.PIPE).communicate()[0] + + # Write simulation results (counters) to data directory + print "cd", scripts_path + os.chdir(scripts_path) + filename = os.path.join(data_dir, app + '_' + log_init_name + str(i)) + file = open(filename, 'w') + file.write(output) + file.close() + + +## End of simulations + + + Index: /branches/fault_tolerance/platforms/tsar_generic_xbar/scripts/templates/coherence_template.gp =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_xbar/scripts/templates/coherence_template.gp (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_xbar/scripts/templates/coherence_template.gp (revision 724) @@ -0,0 +1,24 @@ + +set terminal svg size 500 400 fixed +set output "%(svg_name)s.svg" + +set ylabel "Coherence Cost for Application %(app_name)s\nNormalized w.r.t. the Number of Cycles (x 1000)" font "Times,12" +set xlabel "Number of Cores" font "Times,12" + +set grid noxtics +set grid nomxtics +set grid nomx2tics +set grid ytics +set grid mytics + +#set logscale x 2 +#set logscale y 2 +set xrange [8:256] +#set yrange [0:30] + +set key inside left top Left reverse + + +plot %(plot_str)s + + Index: /branches/fault_tolerance/platforms/tsar_generic_xbar/scripts/templates/metric_template.gp =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_xbar/scripts/templates/metric_template.gp (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_xbar/scripts/templates/metric_template.gp (revision 724) @@ -0,0 +1,34 @@ + +set terminal svg size 1000 400 fixed +set output "%(svg_name)s.svg" + +set xtics nomirror out scale 0,0 rotate by 0 font "Times,10" + +set xtics %(xtics_str)s +# Creates something like: +#set xtics ("1" 1, "4" 2, "8" 3, "16" 4, "32" 5, "64" 6, "128" 7, "256" 8, "1" 9.5, "4" 10.5, "8" 11.5, "16" 12.5, "32" 13.5, "64" 14.5, "128" 15.5, "256" 16.5, "1" 18, ...) + +set ylabel "%(ylabel_str)s %(norm_factor_str)s" font "Times,12" +set xlabel " " + +%(app_labels)s + +set xrange [0:%(xmax_val)d] + +#set mytics 0.1 + +set grid noxtics +set grid nomxtics +set grid nomx2tics +set grid ytics +set grid mytics + + +set key inside left top Left reverse + +set boxwidth 1 +set style fill solid border -1 + +plot %(plot_str)s + + Index: /branches/fault_tolerance/platforms/tsar_generic_xbar/scripts/templates/speedup_template.gp =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_xbar/scripts/templates/speedup_template.gp (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_xbar/scripts/templates/speedup_template.gp (revision 724) @@ -0,0 +1,24 @@ + +set terminal svg size 500 400 fixed +set output "%(svg_name)s.svg" + +set ylabel "Speedup for %(appli)s" font "Times,12" +set xlabel "Number of Cores" font "Times,12" + +set xrange [1:%(nb_procs)d] +set yrange [1:130] + +set grid noxtics +set grid nomxtics +set grid nomx2tics +set grid ytics +set grid mytics + +set logscale x 2 +set logscale y 2 + +set key inside left top Left reverse + +plot %(plot_str)s + + Index: /branches/fault_tolerance/platforms/tsar_generic_xbar/scripts/templates/stacked_template.gp =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_xbar/scripts/templates/stacked_template.gp (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_xbar/scripts/templates/stacked_template.gp (revision 724) @@ -0,0 +1,37 @@ + +set terminal svg size 1500 500 fixed +set output "%(svg_name)s.svg" + +# border 3 -> bords en bas et a gauche (2 derniers bits à 1) +set border 3 front linetype -1 linewidth 1.000 +set boxwidth 1 absolute +set style fill solid 1.00 border -1 + +# front : devant les autres objets (courbes) ; fc : fillcolor +#set style rectangle front fc lt -3 fillstyle solid 1.00 border -1 +set style rectangle front fc lt 2 fillstyle solid 1.00 border -1 +set grid noxtics nomxtics ytics mytics noztics nomztics nox2tics nomx2tics noy2tics nomy2tics nocbtics nomcbtics + +# Lignes derriere le graphique. 2e type de ligne pour les lignes verticales ? +set grid layerdefault linetype 0 linewidth 1.000, linetype 0 linewidth 1.000 + +# Legende des traits ou batons +set key outside right Left reverse invert center +#set key inside vertical left Left reverse invert enhanced autotitles columnhead nobox +set style histogram rowstacked title offset character 2, 0.25, 0 +set datafile missing '-' +set style data histograms + +# border : ne croise pas l'axe ; in : a l'interieur ; scale : taille (major,minor) ; offset : offset du texte +set xtics border in scale 0.0,0.0 nomirror rotate by 0 offset character 0,0 font "Times,10" +set ytics border out scale 1,0.5 nomirror norotate offset character 0,0 + +set xtics %(xtics_str)s + +set xlabel " " +set ylabel "%(ylabel_str)s" font "Times,14" + +%(app_labels)s + +plot %(plot_str)s + Index: /branches/fault_tolerance/platforms/tsar_generic_xbar/soclib.conf =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_xbar/soclib.conf (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_xbar/soclib.conf (revision 724) @@ -0,0 +1,1 @@ + Index: /branches/fault_tolerance/platforms/tsar_generic_xbar/top.cpp =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_xbar/top.cpp (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_xbar/top.cpp (revision 724) @@ -0,0 +1,1140 @@ +///////////////////////////////////////////////////////////////////////// +// File: top.cpp +// Author: Alain Greiner +// Copyright: UPMC/LIP6 +// Date : may 2013 +// This program is released under the GNU public license +///////////////////////////////////////////////////////////////////////// +// This file define a generic TSAR architecture. +// The physical address space is 40 bits. +// +// The number of clusters cannot be larger than 256. +// The number of processors per cluster cannot be larger than 8. +// +// - It uses four dspin_local_crossbar per cluster as local interconnect +// - It uses two virtual_dspin routers per cluster as global interconnect +// - It uses the vci_cc_vcache_wrapper +// - It uses the vci_mem_cache +// - It contains one vci_xicu per cluster. +// - It contains one vci_multi_dma per cluster. +// - It contains one vci_simple_ram per cluster to model the L3 cache. +// +// The communication between the MemCache and the Xram is 64 bits. +// +// All clusters are identical, but the cluster 0 (called io_cluster), +// contains 6 extra components: +// - the boot rom (BROM) +// - the disk controller (BDEV) +// - the multi-channel network controller (MNIC) +// - the multi-channel chained buffer dma controller (CDMA) +// - the multi-channel tty controller (MTTY) +// - the frame buffer controller (FBUF) +// +// It is build with one single component implementing a cluster, +// defined in files tsar_xbar_cluster.* (with * = cpp, h, sd) +// +// The IRQs are connected to XICUs as follow: +// - The IRQ_IN[0] to IRQ_IN[7] ports are not used in all clusters. +// - The DMA IRQs are connected to IRQ_IN[8] to IRQ_IN[15] in all clusters. +// - The TTY IRQs are connected to IRQ_IN[16] to IRQ_IN[30] in I/O cluster. +// - The BDEV IRQ is connected to IRQ_IN[31] in I/O cluster. +// +// Some hardware parameters are used when compiling the OS, and are used +// by this top.cpp file. They must be defined in the hard_config.h file : +// - CLUSTER_X : number of clusters in a row (power of 2) +// - CLUSTER_Y : number of clusters in a column (power of 2) +// - CLUSTER_SIZE : size of the segment allocated to a cluster +// - NB_PROCS_MAX : number of processors per cluster (power of 2) +// - NB_DMA_CHANNELS : number of DMA channels per cluster (< 9) +// - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (< 16) +// - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (< 9) +// +// Some other hardware parameters are not used when compiling the OS, +// and can be directly defined in this top.cpp file: +// - XRAM_LATENCY : external ram latency +// - MEMC_WAYS : L2 cache number of ways +// - MEMC_SETS : L2 cache number of sets +// - L1_IWAYS +// - L1_ISETS +// - L1_DWAYS +// - L1_DSETS +// - FBUF_X_SIZE : width of frame buffer (pixels) +// - FBUF_Y_SIZE : heigth of frame buffer (lines) +// - BDEV_SECTOR_SIZE : block size for block drvice +// - BDEV_IMAGE_NAME : file pathname for block device +// - NIC_RX_NAME : file pathname for NIC received packets +// - NIC_TX_NAME : file pathname for NIC transmited packets +// - NIC_TIMEOUT : max number of cycles before closing a container +///////////////////////////////////////////////////////////////////////// +// General policy for 40 bits physical address decoding: +// All physical segments base addresses are multiple of 1 Mbytes +// (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) +// The (x_width + y_width) MSB bits (left aligned) define +// the cluster index, and the LADR bits define the local index: +// | X_ID | Y_ID |---| LADR | OFFSET | +// |x_width|y_width|---| 8 | 24 | +///////////////////////////////////////////////////////////////////////// +// General policy for 14 bits SRCID decoding: +// Each component is identified by (x_id, y_id, l_id) tuple. +// | X_ID | Y_ID |---| L_ID | +// |x_width|y_width|---| 6 | +///////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include +#include +#include +#include + +#include "gdbserver.h" +#include "mapping_table.h" +#include "alloc_elems.h" +#include "tsar_xbar_cluster.h" + +#define USE_ALMOS 1 +//#define USE_GIET + +#ifdef USE_ALMOS +#ifdef USE_GIET +#error "Can't use Two different OS" +#endif +#endif + +#ifndef USE_ALMOS +#ifndef USE_GIET +#error "You need to specify one OS" +#endif +#endif + +#ifdef USE_ALMOS + #define PREFIX_OS "almos/" + #include "almos/hard_config.h" +#endif +#ifdef USE_GIET + #define PREFIX_OS "giet_vm/" +#endif + +/////////////////////////////////////////////////// +// Parallelisation +/////////////////////////////////////////////////// + +#define USE_OPENMP 0 + +#if USE_OPENMP +#include +#endif + +// cluster index (computed from x,y coordinates) +#ifdef USE_ALMOS + #define cluster(x,y) (y + x * Y_SIZE) +#else + #define cluster(x,y) (y + (x << Y_WIDTH)) +#endif + + +#define min(x, y) (x < y ? x : y) + +/////////////////////////////////////////////////////////// +// DSPIN parameters +/////////////////////////////////////////////////////////// + +#define dspin_cmd_width 39 +#define dspin_rsp_width 32 + +/////////////////////////////////////////////////////////// +// VCI parameters +/////////////////////////////////////////////////////////// + +#define vci_cell_width_int 4 +#define vci_cell_width_ext 8 + +#ifdef USE_ALMOS +#define vci_address_width 32 +#endif +#ifdef USE_GIET +#define vci_address_width 40 +#endif +#define vci_plen_width 8 +#define vci_rerror_width 1 +#define vci_clen_width 1 +#define vci_rflag_width 1 +#define vci_srcid_width 14 +#define vci_pktid_width 4 +#define vci_trdid_width 4 +#define vci_wrplen_width 1 + +//////////////////////////////////////////////////////////// +// Secondary Hardware Parameters +//////////////////////i///////////////////////////////////// + + +#define XRAM_LATENCY 0 + +#define MEMC_WAYS 16 +#define MEMC_SETS 256 + +#define L1_IWAYS 4 +#define L1_ISETS 64 + +#define L1_DWAYS 4 +#define L1_DSETS 64 + +#ifdef USE_ALMOS +#define FBUF_X_SIZE 1024 +#define FBUF_Y_SIZE 1024 +#endif +#ifdef USE_GIET +#define FBUF_X_SIZE 128 +#define FBUF_Y_SIZE 128 +#endif + +#ifdef USE_GIET +#define BDEV_SECTOR_SIZE 512 +#define BDEV_IMAGE_NAME PREFIX_OS"display/images.raw" +#endif +#ifdef USE_ALMOS +#define BDEV_SECTOR_SIZE 4096 +#define BDEV_IMAGE_NAME PREFIX_OS"hdd-img.bin" +#endif + +#define NIC_RX_NAME PREFIX_OS"nic/rx_packets.txt" +#define NIC_TX_NAME PREFIX_OS"nic/tx_packets.txt" +#define NIC_TIMEOUT 10000 + +#define NORTH 0 +#define SOUTH 1 +#define EAST 2 +#define WEST 3 + +//////////////////////////////////////////////////////////// +// Software to be loaded in ROM & RAM +//////////////////////i///////////////////////////////////// + +#ifdef USE_ALMOS +#define soft_name PREFIX_OS"bootloader-tsar-mipsel.bin",\ + PREFIX_OS"kernel-soclib.bin@0xbfc10000:D",\ + PREFIX_OS"arch-info.bib@0xBFC08000:D" +#endif +#ifdef USE_GIET +#define soft_pathname PREFIX_OS"soft.elf" +#endif + +//////////////////////////////////////////////////////////// +// DEBUG Parameters default values +//////////////////////i///////////////////////////////////// + +#define MAX_FROZEN_CYCLES 100000000 + + +//////////////////////////////////////////////////////////////////// +// TGTID definition in direct space +// For all components: global TGTID = global SRCID = cluster_index +//////////////////////////////////////////////////////////////////// + +#define MEMC_TGTID 0 +#define XICU_TGTID 1 +#define MDMA_TGTID 2 +#define MTTY_TGTID 3 +#define BDEV_TGTID 4 +#define MNIC_TGTID 5 +#define BROM_TGTID 6 +#define CDMA_TGTID 7 +#define SIMH_TGTID 8 +#define FBUF_TGTID 9 + + +///////////////////////////////////////////////////////// +// Physical segments definition +///////////////////////////////////////////////////////// +// There is 3 segments replicated in all clusters +// and 5 specific segments in the "IO" cluster +// (containing address 0xBF000000) +///////////////////////////////////////////////////////// + +#ifdef USE_GIET + // specific segments in "IO" cluster : absolute physical address + #define BROM_BASE 0x00BFC00000 + #define BROM_SIZE 0x0000100000 // 1 Mbytes + + #define FBUF_BASE 0x00B2000000 + #define FBUF_SIZE (FBUF_X_SIZE * FBUF_Y_SIZE * 2) + + #define BDEV_BASE 0x00B3000000 + #define BDEV_SIZE 0x0000001000 // 4 Kbytes + + #define MTTY_BASE 0x00B4000000 + #define MTTY_SIZE 0x0000001000 // 4 Kbytes + + #define MNIC_BASE 0x00B5000000 + #define MNIC_SIZE 0x0000080000 // 512 Kbytes (for 8 channels) + + #define CDMA_BASE 0x00B6000000 + #define CDMA_SIZE 0x0000004000 * NB_CMA_CHANNELS + + // replicated segments : address is incremented by a cluster offset + // offset = cluster(x,y) << (address_width-x_width-y_width); + + #define MEMC_BASE 0x0000000000 + #define MEMC_SIZE 0x0010000000 // 256 Mbytes per cluster + + #define XICU_BASE 0x00B0000000 + #define XICU_SIZE 0x0000001000 // 4 Kbytes + + #define MDMA_BASE 0x00B1000000 + #define MDMA_SIZE 0x0000001000 * NB_DMA_CHANNELS // 4 Kbytes per channel + + #define SIMH_BASE 0x00B7000000 + #define SIMH_SIZE 0x0000001000 +#endif + +#ifdef USE_ALMOS + // 2^19 is the offset for the local id (8 bits for global ID : + // 1 bit for Memcache or Peripheral, 4 for local peripheral id) + // (Almos supports 32 bits physical addresses) + + #define CLUSTER_INC (0x80000000ULL / (X_SIZE * Y_SIZE) * 2) + + #define CLUSTER_IO_INC (cluster_io_id * CLUSTER_INC) + #define MEMC_MAX_SIZE (0x40000000 / (X_SIZE * Y_SIZE)) // 0x40000000 : valeur totale souhaitée (ici : 1Go) + + #define BROM_BASE 0x00BFC00000 + #define BROM_SIZE 0x0000100000 // 1 Mbytes + + #define MEMC_BASE 0x0000000000 + #define MEMC_SIZE min(0x04000000, MEMC_MAX_SIZE) + + #define XICU_BASE (CLUSTER_INC >> 1) + (XICU_TGTID << 19) + #define XICU_SIZE 0x0000001000 // 4 Kbytes + + #define MDMA_BASE (CLUSTER_INC >> 1) + (MDMA_TGTID << 19) + #define MDMA_SIZE (0x0000001000 * NB_DMA_CHANNELS) // 4 Kbytes per channel + + #define BDEV_BASE (CLUSTER_INC >> 1) + (BDEV_TGTID << 19) + (CLUSTER_IO_INC) + #define BDEV_SIZE 0x0000001000 // 4 Kbytes + + #define MTTY_BASE (CLUSTER_INC >> 1) + (MTTY_TGTID << 19) + (CLUSTER_IO_INC) + #define MTTY_SIZE 0x0000001000 // 4 Kbytes + + #define FBUF_BASE (CLUSTER_INC >> 1) + (FBUF_TGTID << 19) + (CLUSTER_IO_INC) + #define FBUF_SIZE (FBUF_X_SIZE * FBUF_Y_SIZE * 2) // Should be 0x80000 + + #define MNIC_BASE (CLUSTER_INC >> 1) + (MNIC_TGTID << 19) + (CLUSTER_IO_INC) + #define MNIC_SIZE 0x0000080000 + + #define CDMA_BASE (CLUSTER_INC >> 1) + (CDMA_TGTID << 19) + (CLUSTER_IO_INC) + #define CDMA_SIZE (0x0000004000 * NB_CMA_CHANNELS) + + #define SIMH_BASE (CLUSTER_INC >> 1) + (SIMH_TGTID << 19) + (CLUSTER_IO_INC) + #define SIMH_SIZE 0x0000001000 +#endif + +bool stop_called = false; + +///////////////////////////////// +int _main(int argc, char *argv[]) +{ + using namespace sc_core; + using namespace soclib::caba; + using namespace soclib::common; + +#ifdef USE_GIET + char soft_name[256] = soft_pathname; // pathname to binary code +#endif + const int64_t max_cycles = 5000000; // Maximum number of cycles simulated in one sc_start call + int64_t ncycles = 0x7FFFFFFFFFFFFFFF; // simulated cycles + char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image + char nic_rx_name[256] = NIC_RX_NAME; // pathname to the rx packets file + char nic_tx_name[256] = NIC_TX_NAME; // pathname to the tx packets file + ssize_t threads_nr = 1; // simulator's threads number + bool debug_ok = false; // trace activated + size_t debug_period = 1; // trace period + size_t debug_memc_id = 0; // index of memc to be traced + size_t debug_proc_id = 0; // index of proc to be traced + int64_t debug_from = 0; // trace start cycle + int64_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor + size_t cluster_io_id; // index of cluster containing IOs + int64_t reset_counters = -1; + int64_t dump_counters = -1; + bool do_reset_counters = false; + bool do_dump_counters = false; + struct timeval t1, t2; + uint64_t ms1, ms2; + + ////////////// command line arguments ////////////////////// + if (argc > 1) + { + for (int n = 1; n < argc; n = n + 2) + { + if ((strcmp(argv[n], "-NCYCLES") == 0) && (n + 1 < argc)) + { + ncycles = (int64_t) strtol(argv[n + 1], NULL, 0); + } + else if ((strcmp(argv[n], "-SOFT") == 0) && (n + 1 < argc)) + { +#ifdef USE_ALMOS + assert( 0 && "Can't define almos soft name" ); +#endif +#ifdef USE_GIET + strcpy(soft_name, argv[n + 1]); +#endif + } + else if ((strcmp(argv[n],"-DISK") == 0) && (n + 1 < argc)) + { + strcpy(disk_name, argv[n + 1]); + } + else if ((strcmp(argv[n],"-DEBUG") == 0) && (n + 1 < argc)) + { + debug_ok = true; + debug_from = (int64_t) strtol(argv[n + 1], NULL, 0); + } + else if ((strcmp(argv[n], "-MEMCID") == 0) && (n + 1 < argc)) + { + debug_memc_id = (size_t) strtol(argv[n + 1], NULL, 0); +#ifdef USE_ALMOS + assert((debug_memc_id < (X_SIZE * Y_SIZE)) && + "debug_memc_id larger than X_SIZE * Y_SIZE" ); +#else + size_t x = debug_memc_id >> Y_WIDTH; + size_t y = debug_memc_id & ((1<> Y_WIDTH; + size_t y = cluster_xy & ((1<> (vci_address_width - x_width - y_width); + + + ///////////////////// + // Mapping Tables + ///////////////////// + + // internal network + MappingTable maptabd(vci_address_width, + IntTab(x_width + y_width, 16 - x_width - y_width), + IntTab(x_width + y_width, vci_srcid_width - x_width - y_width), + 0x00FF800000); + + for (size_t x = 0; x < X_SIZE; x++) + { + for (size_t y = 0; y < Y_SIZE; y++) + { + sc_uint offset; + offset = (sc_uint)cluster(x,y) + << (vci_address_width-x_width-y_width); + + std::ostringstream si; + si << "seg_xicu_" << x << "_" << y; + maptabd.add(Segment(si.str(), XICU_BASE + offset, XICU_SIZE, + IntTab(cluster(x,y),XICU_TGTID), false)); + + std::ostringstream sd; + sd << "seg_mdma_" << x << "_" << y; + maptabd.add(Segment(sd.str(), MDMA_BASE + offset, MDMA_SIZE, + IntTab(cluster(x,y),MDMA_TGTID), false)); + + std::ostringstream sh; + sh << "seg_memc_" << x << "_" << y; + maptabd.add(Segment(sh.str(), MEMC_BASE + offset, MEMC_SIZE, + IntTab(cluster(x,y),MEMC_TGTID), true)); + + if ( cluster(x,y) == cluster_io_id ) + { + maptabd.add(Segment("seg_mtty", MTTY_BASE, MTTY_SIZE, + IntTab(cluster(x,y),MTTY_TGTID), false)); + maptabd.add(Segment("seg_fbuf", FBUF_BASE, FBUF_SIZE, + IntTab(cluster(x,y),FBUF_TGTID), false)); + maptabd.add(Segment("seg_bdev", BDEV_BASE, BDEV_SIZE, + IntTab(cluster(x,y),BDEV_TGTID), false)); + maptabd.add(Segment("seg_brom", BROM_BASE, BROM_SIZE, + IntTab(cluster(x,y),BROM_TGTID), true)); + maptabd.add(Segment("seg_mnic", MNIC_BASE, MNIC_SIZE, + IntTab(cluster(x,y),MNIC_TGTID), false)); + maptabd.add(Segment("seg_cdma", CDMA_BASE, CDMA_SIZE, + IntTab(cluster(x,y),CDMA_TGTID), false)); + maptabd.add(Segment("seg_simh", SIMH_BASE, SIMH_SIZE, + IntTab(cluster(x,y),SIMH_TGTID), false)); + } + } + } + std::cout << maptabd << std::endl; + + // external network + MappingTable maptabx(vci_address_width, + IntTab(x_width+y_width), + IntTab(x_width+y_width), + 0xFFFF000000ULL); + + for (size_t x = 0; x < X_SIZE; x++) + { + for (size_t y = 0; y < Y_SIZE ; y++) + { + + sc_uint offset; + offset = (sc_uint)cluster(x,y) + << (vci_address_width-x_width-y_width); + + std::ostringstream sh; + sh << "x_seg_memc_" << x << "_" << y; + + maptabx.add(Segment(sh.str(), MEMC_BASE + offset, + MEMC_SIZE, IntTab(cluster(x,y)), false)); + } + } + std::cout << maptabx << std::endl; + + //////////////////// + // Signals + /////////////////// + + sc_clock signal_clk("clk"); + sc_signal signal_resetn("resetn"); + + // Horizontal inter-clusters DSPIN signals + DspinSignals*** signal_dspin_h_cmd_inc = + alloc_elems >("signal_dspin_h_cmd_inc", X_SIZE-1, Y_SIZE, 3); + DspinSignals*** signal_dspin_h_cmd_dec = + alloc_elems >("signal_dspin_h_cmd_dec", X_SIZE-1, Y_SIZE, 3); + DspinSignals*** signal_dspin_h_rsp_inc = + alloc_elems >("signal_dspin_h_rsp_inc", X_SIZE-1, Y_SIZE, 2); + DspinSignals*** signal_dspin_h_rsp_dec = + alloc_elems >("signal_dspin_h_rsp_dec", X_SIZE-1, Y_SIZE, 2); + + // Vertical inter-clusters DSPIN signals + DspinSignals*** signal_dspin_v_cmd_inc = + alloc_elems >("signal_dspin_v_cmd_inc", X_SIZE, Y_SIZE-1, 3); + DspinSignals*** signal_dspin_v_cmd_dec = + alloc_elems >("signal_dspin_v_cmd_dec", X_SIZE, Y_SIZE-1, 3); + DspinSignals*** signal_dspin_v_rsp_inc = + alloc_elems >("signal_dspin_v_rsp_inc", X_SIZE, Y_SIZE-1, 2); + DspinSignals*** signal_dspin_v_rsp_dec = + alloc_elems >("signal_dspin_v_rsp_dec", X_SIZE, Y_SIZE-1, 2); + + // Mesh boundaries DSPIN signals + DspinSignals**** signal_dspin_false_cmd_in = + alloc_elems >("signal_dspin_false_cmd_in" , X_SIZE, Y_SIZE, 4, 3); + DspinSignals**** signal_dspin_false_cmd_out = + alloc_elems >("signal_dspin_false_cmd_out", X_SIZE, Y_SIZE, 4, 3); + DspinSignals**** signal_dspin_false_rsp_in = + alloc_elems >("signal_dspin_false_rsp_in" , X_SIZE, Y_SIZE, 4, 2); + DspinSignals**** signal_dspin_false_rsp_out = + alloc_elems >("signal_dspin_false_rsp_out", X_SIZE, Y_SIZE, 4, 2); + + + //////////////////////////// + // Loader + //////////////////////////// + + soclib::common::Loader loader(soft_name); + + typedef soclib::common::GdbServer proc_iss; + proc_iss::set_loader(loader); + + //////////////////////////// + // Clusters construction + //////////////////////////// + + TsarXbarCluster* clusters[X_SIZE][Y_SIZE]; + +#if USE_OPENMP +#pragma omp parallel + { +#pragma omp for +#endif + for (size_t i = 0; i < (X_SIZE * Y_SIZE); i++) + { + size_t x = i / Y_SIZE; + size_t y = i % Y_SIZE; + +#if USE_OPENMP +#pragma omp critical + { +#endif + std::cout << std::endl; + std::cout << "Cluster_" << x << "_" << y << std::endl; + std::cout << std::endl; + + std::ostringstream sc; + sc << "cluster_" << x << "_" << y; + clusters[x][y] = new TsarXbarCluster + ( + sc.str().c_str(), + NB_PROCS_MAX, + NB_TTY_CHANNELS, + NB_DMA_CHANNELS, + x, + y, + cluster(x,y), + maptabd, + maptabx, + x_width, + y_width, + vci_srcid_width - x_width - y_width, // l_id width, + MEMC_TGTID, + XICU_TGTID, + MDMA_TGTID, + FBUF_TGTID, + MTTY_TGTID, + BROM_TGTID, + MNIC_TGTID, + CDMA_TGTID, + BDEV_TGTID, + SIMH_TGTID, + MEMC_WAYS, + MEMC_SETS, + L1_IWAYS, + L1_ISETS, + L1_DWAYS, + L1_DSETS, + IRQ_PER_PROCESSOR, + XRAM_LATENCY, + (cluster(x,y) == cluster_io_id), + FBUF_X_SIZE, + FBUF_Y_SIZE, + disk_name, + BDEV_SECTOR_SIZE, + NB_NIC_CHANNELS, + nic_rx_name, + nic_tx_name, + NIC_TIMEOUT, + NB_CMA_CHANNELS, + loader, + frozen_cycles, + debug_from, + debug_ok and (cluster(x,y) == debug_memc_id), + debug_ok and (cluster(x,y) == debug_proc_id) + ); + +#if USE_OPENMP + } // end critical +#endif + } // end for +#if USE_OPENMP + } +#endif + + /////////////////////////////////////////////////////////////// + // Net-list + /////////////////////////////////////////////////////////////// + + // Clock & RESET + for (size_t x = 0; x < (X_SIZE); x++){ + for (size_t y = 0; y < Y_SIZE; y++){ + clusters[x][y]->p_clk (signal_clk); + clusters[x][y]->p_resetn (signal_resetn); + } + } + + // Inter Clusters horizontal connections + if (X_SIZE > 1){ + for (size_t x = 0; x < (X_SIZE-1); x++){ + for (size_t y = 0; y < Y_SIZE; y++){ + for (size_t k = 0; k < 3; k++){ + clusters[x][y]->p_cmd_out[EAST][k] (signal_dspin_h_cmd_inc[x][y][k]); + clusters[x+1][y]->p_cmd_in[WEST][k] (signal_dspin_h_cmd_inc[x][y][k]); + clusters[x][y]->p_cmd_in[EAST][k] (signal_dspin_h_cmd_dec[x][y][k]); + clusters[x+1][y]->p_cmd_out[WEST][k] (signal_dspin_h_cmd_dec[x][y][k]); + } + + for (size_t k = 0; k < 2; k++){ + clusters[x][y]->p_rsp_out[EAST][k] (signal_dspin_h_rsp_inc[x][y][k]); + clusters[x+1][y]->p_rsp_in[WEST][k] (signal_dspin_h_rsp_inc[x][y][k]); + clusters[x][y]->p_rsp_in[EAST][k] (signal_dspin_h_rsp_dec[x][y][k]); + clusters[x+1][y]->p_rsp_out[WEST][k] (signal_dspin_h_rsp_dec[x][y][k]); + } + } + } + } + std::cout << std::endl << "Horizontal connections established" << std::endl; + + // Inter Clusters vertical connections + if (Y_SIZE > 1) { + for (size_t y = 0; y < (Y_SIZE-1); y++){ + for (size_t x = 0; x < X_SIZE; x++){ + for (size_t k = 0; k < 3; k++){ + clusters[x][y]->p_cmd_out[NORTH][k] (signal_dspin_v_cmd_inc[x][y][k]); + clusters[x][y+1]->p_cmd_in[SOUTH][k] (signal_dspin_v_cmd_inc[x][y][k]); + clusters[x][y]->p_cmd_in[NORTH][k] (signal_dspin_v_cmd_dec[x][y][k]); + clusters[x][y+1]->p_cmd_out[SOUTH][k] (signal_dspin_v_cmd_dec[x][y][k]); + } + + for (size_t k = 0; k < 2; k++){ + clusters[x][y]->p_rsp_out[NORTH][k] (signal_dspin_v_rsp_inc[x][y][k]); + clusters[x][y+1]->p_rsp_in[SOUTH][k] (signal_dspin_v_rsp_inc[x][y][k]); + clusters[x][y]->p_rsp_in[NORTH][k] (signal_dspin_v_rsp_dec[x][y][k]); + clusters[x][y+1]->p_rsp_out[SOUTH][k] (signal_dspin_v_rsp_dec[x][y][k]); + } + } + } + } + std::cout << "Vertical connections established" << std::endl; + + // East & West boundary cluster connections + for (size_t y = 0; y < Y_SIZE; y++) + { + for (size_t k = 0; k < 3; k++) + { + clusters[0][y]->p_cmd_in[WEST][k] (signal_dspin_false_cmd_in[0][y][WEST][k]); + clusters[0][y]->p_cmd_out[WEST][k] (signal_dspin_false_cmd_out[0][y][WEST][k]); + clusters[X_SIZE-1][y]->p_cmd_in[EAST][k] (signal_dspin_false_cmd_in[X_SIZE-1][y][EAST][k]); + clusters[X_SIZE-1][y]->p_cmd_out[EAST][k] (signal_dspin_false_cmd_out[X_SIZE-1][y][EAST][k]); + } + + for (size_t k = 0; k < 2; k++) + { + clusters[0][y]->p_rsp_in[WEST][k] (signal_dspin_false_rsp_in[0][y][WEST][k]); + clusters[0][y]->p_rsp_out[WEST][k] (signal_dspin_false_rsp_out[0][y][WEST][k]); + clusters[X_SIZE-1][y]->p_rsp_in[EAST][k] (signal_dspin_false_rsp_in[X_SIZE-1][y][EAST][k]); + clusters[X_SIZE-1][y]->p_rsp_out[EAST][k] (signal_dspin_false_rsp_out[X_SIZE-1][y][EAST][k]); + } + } + + // North & South boundary clusters connections + for (size_t x = 0; x < X_SIZE; x++) + { + for (size_t k = 0; k < 3; k++) + { + clusters[x][0]->p_cmd_in[SOUTH][k] (signal_dspin_false_cmd_in[x][0][SOUTH][k]); + clusters[x][0]->p_cmd_out[SOUTH][k] (signal_dspin_false_cmd_out[x][0][SOUTH][k]); + clusters[x][Y_SIZE-1]->p_cmd_in[NORTH][k] (signal_dspin_false_cmd_in[x][Y_SIZE-1][NORTH][k]); + clusters[x][Y_SIZE-1]->p_cmd_out[NORTH][k] (signal_dspin_false_cmd_out[x][Y_SIZE-1][NORTH][k]); + } + + for (size_t k = 0; k < 2; k++) + { + clusters[x][0]->p_rsp_in[SOUTH][k] (signal_dspin_false_rsp_in[x][0][SOUTH][k]); + clusters[x][0]->p_rsp_out[SOUTH][k] (signal_dspin_false_rsp_out[x][0][SOUTH][k]); + clusters[x][Y_SIZE-1]->p_rsp_in[NORTH][k] (signal_dspin_false_rsp_in[x][Y_SIZE-1][NORTH][k]); + clusters[x][Y_SIZE-1]->p_rsp_out[NORTH][k] (signal_dspin_false_rsp_out[x][Y_SIZE-1][NORTH][k]); + } + } + std::cout << "North, South, West, East connections established" << std::endl; + std::cout << std::endl; + + + //////////////////////////////////////////////////////// + // Simulation + /////////////////////////////////////////////////////// + + sc_start(sc_core::sc_time(0, SC_NS)); + signal_resetn = false; + + // network boundaries signals + for (size_t x = 0; x < X_SIZE ; x++){ + for (size_t y = 0; y < Y_SIZE ; y++){ + for (size_t a = 0; a < 4; a++){ + for (size_t k = 0; k < 3; k++){ + signal_dspin_false_cmd_in [x][y][a][k].write = false; + signal_dspin_false_cmd_in [x][y][a][k].read = true; + signal_dspin_false_cmd_out[x][y][a][k].write = false; + signal_dspin_false_cmd_out[x][y][a][k].read = true; + } + + for (size_t k = 0; k < 2; k++){ + signal_dspin_false_rsp_in [x][y][a][k].write = false; + signal_dspin_false_rsp_in [x][y][a][k].read = true; + signal_dspin_false_rsp_out[x][y][a][k].write = false; + signal_dspin_false_rsp_out[x][y][a][k].read = true; + } + } + } + } + + sc_start(sc_core::sc_time(1, SC_NS)); + signal_resetn = true; + + if (debug_ok) { + #if USE_OPENMP + assert(false && "OPEN MP should not be used with debug because of its traces"); + #endif + + if (gettimeofday(&t1, NULL) != 0) { + perror("gettimeofday"); + return EXIT_FAILURE; + } + + for (int64_t n = 1; n < ncycles && !stop_called; n++) + { + // Monitor a specific address for L1 & L2 caches + //clusters[0][0]->proc[0]->cache_monitor(0x800002c000ULL); + //clusters[1][0]->memc->copies_monitor(0x800002C000ULL); + + if ((n % max_cycles) == 0) + { + + if (gettimeofday(&t2, NULL) != 0) + { + perror("gettimeofday"); + return EXIT_FAILURE; + } + + ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000; + ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000; + std::cerr << "platform clock frequency " << (double) 5000000 / (double) (ms2 - ms1) << "Khz" << std::endl; + + if (gettimeofday(&t1, NULL) != 0) + { + perror("gettimeofday"); + return EXIT_FAILURE; + } + } + + + if (n == reset_counters) { + for (size_t x = 0; x < (X_SIZE); x++) { + for (size_t y = 0; y < Y_SIZE; y++) { + clusters[x][y]->memc->reset_counters(); + } + } + } + + if (n == dump_counters) { + for (size_t x = 0; x < (X_SIZE); x++) { + for (size_t y = 0; y < Y_SIZE; y++) { + clusters[x][y]->memc->print_stats(true, false); + } + } + } + + if (debug_ok and (n > debug_from) and (n % debug_period == 0)) + { + std::cout << "****************** cycle " << std::dec << n ; + std::cout << " ************************************************" << std::endl; + + // trace proc[debug_proc_id] + size_t l = debug_proc_id % NB_PROCS_MAX ; + size_t y = (debug_proc_id / NB_PROCS_MAX) % Y_SIZE ; + size_t x = debug_proc_id / (Y_SIZE * NB_PROCS_MAX) ; + + std::ostringstream proc_signame; + proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; + std::ostringstream p2m_signame; + p2m_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " P2M" ; + std::ostringstream m2p_signame; + m2p_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " M2P" ; + + //clusters[x][y]->signal_vci_ini_proc[l].print_trace(proc_signame.str()); + //clusters[x][y]->signal_dspin_p2m_proc[l].print_trace(p2m_signame.str()); + //clusters[x][y]->signal_dspin_m2p_proc[l].print_trace(m2p_signame.str()); + + //clusters[x][y]->signal_dspin_cmd_l2g_d.print_trace("[SIG]L2G CMD"); + //clusters[x][y]->signal_dspin_cmd_g2l_d.print_trace("[SIG]G2L CMD"); + //clusters[x][y]->signal_dspin_rsp_l2g_d.print_trace("[SIG]L2G RSP"); + //clusters[x][y]->signal_dspin_rsp_g2l_d.print_trace("[SIG]G2L RSP"); + + // trace memc[debug_memc_id] + x = debug_memc_id / Y_SIZE; + y = debug_memc_id % Y_SIZE; + + std::ostringstream smemc; + smemc << "[SIG]MEMC_" << x << "_" << y; + std::ostringstream sxram; + sxram << "[SIG]XRAM_" << x << "_" << y; + std::ostringstream sm2p; + sm2p << "[SIG]MEMC_" << x << "_" << y << " M2P" ; + std::ostringstream sp2m; + sp2m << "[SIG]MEMC_" << x << "_" << y << " P2M" ; + + //clusters[x][y]->memc->print_trace(); + //clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str()); + //clusters[x][y]->signal_vci_xram.print_trace(sxram.str()); + //clusters[x][y]->signal_dspin_p2m_memc.print_trace(sp2m.str()); + //clusters[x][y]->signal_dspin_m2p_memc.print_trace(sm2p.str()); + + // trace replicated peripherals + //clusters[1][1]->mdma->print_trace(); + //clusters[1][1]->signal_vci_tgt_mdma.print_trace("[SIG]MDMA_TGT_1_1"); + //clusters[1][1]->signal_vci_ini_mdma.print_trace("[SIG]MDMA_INI_1_1"); + + + // trace external peripherals + //size_t io_x = cluster_io_id / Y_SIZE; + //size_t io_y = cluster_io_id % Y_SIZE; + + //clusters[io_x][io_y]->brom->print_trace(); + //clusters[io_x][io_y]->signal_vci_tgt_brom.print_trace("[SIG]BROM"); + + //clusters[io_x][io_y]->bdev->print_trace(); + //clusters[io_x][io_y]->signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT"); + //clusters[io_x][io_y]->signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); + } + + sc_start(sc_core::sc_time(1, SC_NS)); + } + } + else { + int64_t n = 0; + while (!stop_called) { + if (gettimeofday(&t1, NULL) != 0) { + perror("gettimeofday"); + return EXIT_FAILURE; + } + int64_t nb_cycles = max_cycles; + if (do_reset_counters) { + nb_cycles = min(nb_cycles, reset_counters - n); + } + if (do_dump_counters) { + nb_cycles = min(nb_cycles, dump_counters - n); + } + + sc_start(sc_core::sc_time(nb_cycles, SC_NS)); + n += nb_cycles; + + if (do_reset_counters && n == reset_counters) { + // Reseting counters + for (size_t x = 0; x < (X_SIZE); x++) { + for (size_t y = 0; y < Y_SIZE; y++) { + clusters[x][y]->memc->reset_counters(); + } + } + do_reset_counters = false; + } + + if (do_dump_counters && n == dump_counters) { + // Dumping counters + for (size_t x = 0; x < (X_SIZE); x++) { + for (size_t y = 0; y < Y_SIZE; y++) { + clusters[x][y]->memc->print_stats(true, false); + } + } + do_dump_counters = false; + } + + + if (gettimeofday(&t2, NULL) != 0) { + perror("gettimeofday"); + return EXIT_FAILURE; + } + ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000; + ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000; + std::cerr << std::dec << "cycle " << n << " platform clock frequency " << (double) nb_cycles / (double) (ms2 - ms1) << "Khz" << std::endl; + } + } + + + // Free memory + for (size_t i = 0; i < (X_SIZE * Y_SIZE); i++) + { + size_t x = i / Y_SIZE; + size_t y = i % Y_SIZE; + delete clusters[x][y]; + } + + dealloc_elems >(signal_dspin_h_cmd_inc, X_SIZE - 1, Y_SIZE, 3); + dealloc_elems >(signal_dspin_h_cmd_dec, X_SIZE - 1, Y_SIZE, 3); + dealloc_elems >(signal_dspin_h_rsp_inc, X_SIZE - 1, Y_SIZE, 2); + dealloc_elems >(signal_dspin_h_rsp_dec, X_SIZE - 1, Y_SIZE, 2); + dealloc_elems >(signal_dspin_v_cmd_inc, X_SIZE, Y_SIZE - 1, 3); + dealloc_elems >(signal_dspin_v_cmd_dec, X_SIZE, Y_SIZE - 1, 3); + dealloc_elems >(signal_dspin_v_rsp_inc, X_SIZE, Y_SIZE - 1, 2); + dealloc_elems >(signal_dspin_v_rsp_dec, X_SIZE, Y_SIZE - 1, 2); + dealloc_elems >(signal_dspin_false_cmd_in, X_SIZE, Y_SIZE, 4, 3); + dealloc_elems >(signal_dspin_false_cmd_out, X_SIZE, Y_SIZE, 4, 3); + dealloc_elems >(signal_dspin_false_rsp_in, X_SIZE, Y_SIZE, 4, 2); + dealloc_elems >(signal_dspin_false_rsp_out, X_SIZE, Y_SIZE, 4, 2); + + return EXIT_SUCCESS; +} + + +void handler(int dummy = 0) { + stop_called = true; + sc_stop(); +} + +void voidhandler(int dummy = 0) {} + +int sc_main (int argc, char *argv[]) +{ + signal(SIGINT, handler); + signal(SIGPIPE, voidhandler); + + try { + return _main(argc, argv); + } catch (std::exception &e) { + std::cout << e.what() << std::endl; + } catch (...) { + std::cout << "Unknown exception occured" << std::endl; + throw; + } + return 1; +} + + +// Local Variables: +// tab-width: 3 +// c-basic-offset: 3 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 Index: /branches/fault_tolerance/platforms/tsar_generic_xbar/top.desc =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_xbar/top.desc (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_xbar/top.desc (revision 724) @@ -0,0 +1,46 @@ + +# -*- python -*- + +# internal VCI parameters values +vci_cell_size_int = 4 +vci_cell_size_ext = 8 + +vci_plen_size = 8 +vci_addr_size = 32 +vci_rerror_size = 1 +vci_clen_size = 1 +vci_rflag_size = 1 +vci_srcid_size = 14 +vci_pktid_size = 4 +vci_trdid_size = 4 +vci_wrplen_size = 1 + +# DSPIN network parameters values +dspin_cmd_flit_size = 39 +dspin_rsp_flit_size = 32 + +todo = Platform('caba', 'top.cpp', + + uses = [ + Uses('caba:tsar_xbar_cluster', + vci_data_width_int = vci_cell_size_int, + vci_data_width_ext = vci_cell_size_ext, + dspin_cmd_width = dspin_cmd_flit_size, + dspin_rsp_width = dspin_rsp_flit_size), + + Uses('common:elf_file_loader'), + Uses('common:plain_file_loader'), + ], + + # default VCI parameters (global variables) + cell_size = vci_cell_size_int, + plen_size = vci_plen_size, + addr_size = vci_addr_size, + rerror_size = vci_rerror_size, + clen_size = vci_clen_size, + rflag_size = vci_rflag_size, + srcid_size = vci_srcid_size, + pktid_size = vci_pktid_size, + trdid_size = vci_trdid_size, + wrplen_size = vci_wrplen_size, +) Index: /branches/fault_tolerance/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd (revision 724) @@ -0,0 +1,110 @@ + +# -*- python -*- + +Module('caba:tsar_xbar_cluster', + classname = 'soclib::caba::TsarXbarCluster', + tmpl_parameters = [ + parameter.Int('dspin_cmd_width'), + parameter.Int('dspin_rsp_width'), + parameter.Module('vci_param_int', default = 'caba:vci_param', + cell_size = parameter.Reference('vci_data_width_int')), + parameter.Module('vci_param_ext', default = 'caba:vci_param', + cell_size = parameter.Reference('vci_data_width_ext')), + ], + + header_files = [ '../source/include/tsar_xbar_cluster.h', + ], + + implementation_files = [ '../source/src/tsar_xbar_cluster.cpp', + ], + + uses = [ + Uses('caba:base_module'), + Uses('common:mapping_table'), + Uses('common:iss2'), + + Uses('caba:vci_cc_vcache_wrapper', + cell_size = parameter.Reference('vci_data_width_int'), + dspin_in_width = parameter.Reference('dspin_cmd_width'), + dspin_out_width = parameter.Reference('dspin_rsp_width'), + iss_t = 'common:gdb_iss', + gdb_iss_t = 'common:mips32el'), + + Uses('caba:vci_mem_cache', + memc_cell_size_int = parameter.Reference('vci_data_width_int'), + memc_cell_size_ext = parameter.Reference('vci_data_width_ext'), + dspin_in_width = parameter.Reference('dspin_rsp_width'), + dspin_out_width = parameter.Reference('dspin_cmd_width')), + + Uses('caba:vci_simple_rom', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_simple_ram', + cell_size = parameter.Reference('vci_data_width_ext')), + + Uses('caba:vci_simple_ram', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_xicu', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_local_crossbar', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:dspin_local_crossbar', + flit_width = parameter.Reference('dspin_cmd_width')), + + Uses('caba:dspin_local_crossbar', + flit_width = parameter.Reference('dspin_rsp_width')), + + Uses('caba:virtual_dspin_router', + flit_width = parameter.Reference('dspin_cmd_width')), + + Uses('caba:virtual_dspin_router', + flit_width = parameter.Reference('dspin_rsp_width')), + + Uses('caba:vci_multi_tty', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_framebuffer', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_multi_nic', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_chbuf_dma', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_block_device_tsar', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_multi_dma', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_dspin_target_wrapper', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_dspin_initiator_wrapper', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_simhelper', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('common:elf_file_loader'), + ], + + ports = [ + Port('caba:bit_in', 'p_resetn', auto = 'resetn'), + Port('caba:clock_in', 'p_clk', auto = 'clock'), + Port('caba:dspin_output', 'p_cmd_out', [4, 3], + dspin_data_size = parameter.Reference('dspin_cmd_width')), + Port('caba:dspin_input', 'p_cmd_in', [4, 3], + dspin_data_size = parameter.Reference('dspin_cmd_width')), + Port('caba:dspin_output', 'p_rsp_out', [4, 2], + dspin_data_size = parameter.Reference('dspin_rsp_width')), + Port('caba:dspin_input', 'p_rsp_in', [4, 2], + dspin_data_size = parameter.Reference('dspin_rsp_width')), + ], +) + + Index: /branches/fault_tolerance/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/include/tsar_xbar_cluster.h (revision 724) @@ -0,0 +1,217 @@ +////////////////////////////////////////////////////////////////////////////// +// File: tsar_xbar_cluster.h +// Author: Alain Greiner +// Copyright: UPMC/LIP6 +// Date : march 2013 +// This program is released under the GNU public license +////////////////////////////////////////////////////////////////////////////// + +#ifndef SOCLIB_CABA_TSAR_XBAR_CLUSTER_H +#define SOCLIB_CABA_TSAR_XBAR_CLUSTER_H + +#include +#include +#include +#include +#include +#include + +#include "gdbserver.h" +#include "mapping_table.h" +#include "mips32.h" +#include "vci_simple_ram.h" +#include "vci_simple_rom.h" +#include "vci_xicu.h" +#include "dspin_local_crossbar.h" +#include "vci_local_crossbar.h" +#include "vci_dspin_initiator_wrapper.h" +#include "vci_dspin_target_wrapper.h" +#include "virtual_dspin_router.h" +#include "vci_multi_tty.h" +#include "vci_multi_nic.h" +#include "vci_chbuf_dma.h" +#include "vci_block_device_tsar.h" +#include "vci_framebuffer.h" +#include "vci_multi_dma.h" +#include "vci_mem_cache.h" +#include "vci_cc_vcache_wrapper.h" +#include "vci_simhelper.h" + +namespace soclib { namespace caba { + +/////////////////////////////////////////////////////////////////////////// +template class TsarXbarCluster +/////////////////////////////////////////////////////////////////////////// + : public soclib::caba::BaseModule +{ + public: + + // Used in destructor + size_t n_procs; + + // Ports + sc_in p_clk; + sc_in p_resetn; + soclib::caba::DspinOutput **p_cmd_out; + soclib::caba::DspinInput **p_cmd_in; + soclib::caba::DspinOutput **p_rsp_out; + soclib::caba::DspinInput **p_rsp_in; + + // interrupt signals + sc_signal signal_false; + sc_signal signal_proc_it[8 * 6]; // 6 = Number of IRQs in the MIPS + sc_signal signal_irq_mdma[8]; + sc_signal signal_irq_mtty[23]; + sc_signal signal_irq_mnic_rx[8]; // unused + sc_signal signal_irq_mnic_tx[8]; // unused + sc_signal signal_irq_chbuf[8]; // unused + sc_signal signal_irq_memc; + sc_signal signal_irq_bdev; + + // DSPIN signals between DSPIN routers and local_crossbars + DspinSignals signal_dspin_cmd_l2g_d; + DspinSignals signal_dspin_cmd_g2l_d; + DspinSignals signal_dspin_m2p_l2g_c; + DspinSignals signal_dspin_m2p_g2l_c; + DspinSignals signal_dspin_clack_l2g_c; + DspinSignals signal_dspin_clack_g2l_c; + DspinSignals signal_dspin_rsp_l2g_d; + DspinSignals signal_dspin_rsp_g2l_d; + DspinSignals signal_dspin_p2m_l2g_c; + DspinSignals signal_dspin_p2m_g2l_c; + + // Direct VCI signals to VCI/DSPIN wrappers + VciSignals signal_vci_g2l_d; + VciSignals signal_vci_l2g_d; + + VciSignals signal_vci_ini_proc[8]; + VciSignals signal_vci_ini_mdma; + VciSignals signal_vci_ini_bdev; + VciSignals signal_vci_ini_chbuf; + + VciSignals signal_vci_tgt_memc; + VciSignals signal_vci_tgt_xicu; + VciSignals signal_vci_tgt_mdma; + VciSignals signal_vci_tgt_mtty; + VciSignals signal_vci_tgt_bdev; + VciSignals signal_vci_tgt_brom; + VciSignals signal_vci_tgt_fbuf; + VciSignals signal_vci_tgt_mnic; + VciSignals signal_vci_tgt_chbuf; + VciSignals signal_vci_tgt_simh; + + + // Coherence DSPIN signals to local crossbar + DspinSignals signal_dspin_m2p_memc; + DspinSignals signal_dspin_clack_memc; + DspinSignals signal_dspin_p2m_memc; + DspinSignals signal_dspin_m2p_proc[8]; + DspinSignals signal_dspin_clack_proc[8]; + DspinSignals signal_dspin_p2m_proc[8]; + + // external RAM to MEMC VCI signal + VciSignals signal_vci_xram; + + // Components + + VciCcVCacheWrapper >* proc[8]; + + + VciMemCache* memc; + + VciXicu* xicu; + + VciMultiDma* mdma; + + VciSimpleRam* xram; + + VciSimpleRom* brom; + + VciMultiTty* mtty; + + VciSimhelper* simhelper; + + VciFrameBuffer* fbuf; + + VciMultiNic* mnic; + + VciChbufDma* chbuf; + + VciBlockDeviceTsar* bdev; + + VciLocalCrossbar* xbar_d; + VciDspinInitiatorWrapper* wi_xbar_d; + VciDspinTargetWrapper* wt_xbar_d; + + DspinLocalCrossbar* xbar_m2p_c; + DspinLocalCrossbar* xbar_p2m_c; + DspinLocalCrossbar* xbar_clack_c; + + VirtualDspinRouter* router_cmd; + VirtualDspinRouter* router_rsp; + + TsarXbarCluster( sc_module_name insname, + size_t nb_procs, // processors + size_t nb_ttys, // TTY terminals + size_t nb_dmas, // DMA channels + size_t x, // x coordinate + size_t y, // y coordinate + size_t cluster, // y + ymax*x + const soclib::common::MappingTable &mtd, // internal + const soclib::common::MappingTable &mtx, // external + size_t x_width, // x field bits + size_t y_width, // y field bits + size_t l_width, // l field bits + size_t tgtid_memc, + size_t tgtid_xicu, + size_t tgtid_mdma, + size_t tgtid_fbuf, + size_t tgtid_mtty, + size_t tgtid_brom, + size_t tgtid_mnic, + size_t tgtid_chbuf, + size_t tgtid_bdev, + size_t tgtid_simh, + size_t memc_ways, + size_t memc_sets, + size_t l1_i_ways, + size_t l1_i_sets, + size_t l1_d_ways, + size_t l1_d_sets, + size_t irq_per_processor, + size_t xram_latency, // external ram + bool io, // I/O cluster + size_t xfb, // fbf pixels + size_t yfb, // fbf lines + char* disk_name, // virtual disk + size_t block_size, // block size + size_t nic_channels, // number channels + char* nic_rx_name, // filename rx + char* nic_tx_name, // filename tx + uint32_t nic_timeout, // cycles + size_t chbufdma_channels, // number channels + const Loader &loader, + uint32_t frozen_cycles, + uint32_t start_debug_cycle, + bool memc_debug_ok, + bool proc_debug_ok); + + ~TsarXbarCluster(); + +}; +}} + +#endif Index: /branches/fault_tolerance/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp =================================================================== --- /branches/fault_tolerance/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp (revision 724) +++ /branches/fault_tolerance/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp (revision 724) @@ -0,0 +1,683 @@ +////////////////////////////////////////////////////////////////////////////// +// File: tsar_xbar_cluster.cpp +// Author: Alain Greiner +// Copyright: UPMC/LIP6 +// Date : march 2011 +// This program is released under the GNU public license +////////////////////////////////////////////////////////////////////////////// +// This file define a TSAR cluster architecture with virtual memory: +// - It uses two virtual_dspin_router as distributed global interconnect +// - It uses four dspin_local_crossbar as local interconnect +// - It uses the vci_cc_vcache_wrapper +// - It uses the vci_mem_cache +// - It contains a private RAM with a variable latency to emulate the L3 cache +// - It can contains 1, 2 or 4 processors +// - Each processor has a private dma channel (vci_multi_dma) +// - It uses the vci_xicu interrupt controller +// - The peripherals MTTY, BDEV, FBUF, MNIC and BROM are in cluster (0,0) +// - The Multi-TTY component controls up to 15 terminals. +// - Each Multi-DMA component controls up to 8 DMA channels. +// - The DMA IRQs are connected to IRQ_IN[8]...IRQ_IN[15] +// - The TTY IRQs are connected to IRQ_IN[16]...IRQ_IN[30] +// - The BDEV IRQ is connected to IRQ_IN[31] +////////////////////////////////////////////////////////////////////////////////// + +#include "../include/tsar_xbar_cluster.h" + + +namespace soclib { +namespace caba { + +//////////////////////////////////////////////////////////////////////////////////// +template TsarXbarCluster::TsarXbarCluster( +//////////////////////////////////////////////////////////////////////////////////// + sc_module_name insname, + size_t nb_procs, + size_t nb_ttys, + size_t nb_dmas, + size_t x_id, + size_t y_id, + size_t cluster_id, + const soclib::common::MappingTable &mtd, + const soclib::common::MappingTable &mtx, + size_t x_width, + size_t y_width, + size_t l_width, + size_t tgtid_memc, + size_t tgtid_xicu, + size_t tgtid_mdma, + size_t tgtid_fbuf, + size_t tgtid_mtty, + size_t tgtid_brom, + size_t tgtid_mnic, + size_t tgtid_chbuf, + size_t tgtid_bdev, + size_t tgtid_simh, + size_t memc_ways, + size_t memc_sets, + size_t l1_i_ways, + size_t l1_i_sets, + size_t l1_d_ways, + size_t l1_d_sets, + size_t irq_per_processor, + size_t xram_latency, + bool io, + size_t xfb, + size_t yfb, + char* disk_name, + size_t block_size, + size_t nic_channels, + char* nic_rx_name, + char* nic_tx_name, + uint32_t nic_timeout, + size_t chbufdma_channels, + const Loader & loader, + uint32_t frozen_cycles, + uint32_t debug_start_cycle, + bool memc_debug_ok, + bool proc_debug_ok) + : soclib::caba::BaseModule(insname), + p_clk("clk"), + p_resetn("resetn") + +{ + + n_procs = nb_procs; + + // Vectors of ports definition + p_cmd_in = alloc_elems > ("p_cmd_in", 4, 3); + p_cmd_out = alloc_elems > ("p_cmd_out", 4, 3); + p_rsp_in = alloc_elems > ("p_rsp_in", 4, 2); + p_rsp_out = alloc_elems > ("p_rsp_out", 4, 2); + + ///////////////////////////////////////////////////////////////////////////// + // Components definition + ///////////////////////////////////////////////////////////////////////////// + + for (size_t p = 0; p < nb_procs; p++) + { + std::ostringstream sproc; + sproc << "proc_" << x_id << "_" << y_id << "_" << p; + proc[p] = new VciCcVCacheWrapper >( + sproc.str().c_str(), + cluster_id * nb_procs + p, // GLOBAL PROC_ID + mtd, // Mapping Table + IntTab(cluster_id,p), // SRCID + (cluster_id << l_width) + p, // CC_GLOBAL_ID + 8, // ITLB ways + 8, // ITLB sets + 8, // DTLB ways + 8, // DTLB sets + l1_i_ways,l1_i_sets, 16, // ICACHE size + l1_d_ways,l1_d_sets, 16, // DCACHE size + 4, // WBUF nlines + 4, // WBUF nwords + x_width, + y_width, + frozen_cycles, // max frozen cycles + debug_start_cycle, + proc_debug_ok); + + } + + ///////////////////////////////////////////////////////////////////////////// + std::ostringstream smemc; + smemc << "memc_" << x_id << "_" << y_id; + memc = new VciMemCache( + smemc.str().c_str(), + mtd, // Mapping Table direct space + mtx, // Mapping Table external space + IntTab(cluster_id), // SRCID external space + IntTab(cluster_id, tgtid_memc), // TGTID direct space + //(cluster_id << l_width) + nb_procs, // CC_GLOBAL_ID + x_width, // Number of x bits in platform + y_width, // Number of y bits in platform + memc_ways, memc_sets, 16, // CACHE SIZE + 3, // MAX NUMBER OF COPIES + 4096, // HEAP SIZE + 8, // TRANSACTION TABLE DEPTH + 8, // UPDATE TABLE DEPTH + 8, // INVALIDATE TABLE DEPTH + debug_start_cycle, + memc_debug_ok); + + + ///////////////////////////////////////////////////////////////////////////// + std::ostringstream sxram; + sxram << "xram_" << x_id << "_" << y_id; + xram = new VciSimpleRam( + sxram.str().c_str(), + IntTab(cluster_id), + mtx, + loader, + xram_latency); + + ///////////////////////////////////////////////////////////////////////////// + std::ostringstream sxicu; + sxicu << "xicu_" << x_id << "_" << y_id; + xicu = new VciXicu( + sxicu.str().c_str(), + mtd, // mapping table + IntTab(cluster_id, tgtid_xicu), // TGTID_D + nb_procs, // number of timer IRQs + 32, // number of hard IRQs + 32, // number of soft IRQs + nb_procs*irq_per_processor); // number of output IRQs + + + ///////////////////////////////////////////////////////////////////////////// + std::ostringstream smdma; + smdma << "mdma_" << x_id << "_" << y_id; + mdma = new VciMultiDma( + smdma.str().c_str(), + mtd, + IntTab(cluster_id, nb_procs), // SRCID + IntTab(cluster_id, tgtid_mdma), // TGTID + 64, // burst size + nb_dmas); // number of IRQs + + + ///////////////////////////////////////////////////////////////////////////// + size_t nb_direct_initiators = nb_procs + 1; + size_t nb_direct_targets = 3; + if (io) + { + nb_direct_initiators = nb_procs + 3; + nb_direct_targets = 10; + } + + std::ostringstream sxbar; + sxbar << "xbar_" << x_id << "_" << y_id; + xbar_d = new VciLocalCrossbar( + sxbar.str().c_str(), + mtd, // mapping table + //x_id, y_id, // cluster coordinates + cluster_id, + nb_direct_initiators, // number of local of sources + nb_direct_targets, // number of local dests + tgtid_memc); // Default target + + ////////////// vci_dspin wrappers + std::ostringstream swtxbar; + swtxbar << "wt_xbar_" << x_id << "_" << y_id; + wt_xbar_d = new VciDspinTargetWrapper( + swtxbar.str().c_str(), + x_width + y_width + l_width ); + + std::ostringstream swixbar; + swixbar << "wi_xbar_" << x_id << "_" << y_id; + wi_xbar_d = new VciDspinInitiatorWrapper( + swixbar.str().c_str(), + x_width + y_width + l_width ); + + ///////////////////////////////////////////////////////////////////////////// + xbar_m2p_c = new DspinLocalCrossbar( + "xbar_m2p_c", + mtd, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, l_width, + 1, // number of local sources + nb_procs, // number of local targets + 2, 2, // fifo depths + true, // CMD + false, // don't use local routing table + true ); // broadcast + + ///////////////////////////////////////////////////////////////////////////// + xbar_p2m_c = new DspinLocalCrossbar( + "xbar_p2m_c", + mtd, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, 0, // l_width unused on p2m network + nb_procs, // number of local sources + 1, // number of local dests + 2, 2, // fifo depths + false, // RSP + false, // don't use local routing table + false ); // no broadcast + + ///////////////////////////////////////////////////////////////////////////// + xbar_clack_c = new DspinLocalCrossbar( + "xbar_clack_c", + mtd, // mapping table + x_id, y_id, // cluster coordinates + x_width, y_width, l_width, + 1, // number of local sources + nb_procs, // number of local targets + 1, 1, // fifo depths + true, // CMD + false, // don't use local routing table + false); // broadcast + + ///////////////////////////////////////////////////////////////////////////// + router_cmd = new VirtualDspinRouter( + "router_cmd", + x_id,y_id, // coordinate in the mesh + x_width, y_width, // x & y fields width + 3, // nb virtual channels + 4,4); // input & output fifo depths + + ///////////////////////////////////////////////////////////////////////////// + router_rsp = new VirtualDspinRouter( + "router_rsp", + x_id,y_id, // coordinates in mesh + x_width, y_width, // x & y fields width + 2, // nb virtual channels + 4,4); // input & output fifo depths + + // IO cluster components + if (io) + { + ///////////////////////////////////////////// + brom = new VciSimpleRom( + "brom", + IntTab(cluster_id, tgtid_brom), + mtd, + loader); + + ///////////////////////////////////////////// + fbuf = new VciFrameBuffer( + "fbuf", + IntTab(cluster_id, tgtid_fbuf), + mtd, + xfb, yfb); + + ///////////////////////////////////////////// + bdev = new VciBlockDeviceTsar( + "bdev", + mtd, + IntTab(cluster_id, nb_procs + 1), + IntTab(cluster_id, tgtid_bdev), + disk_name, + block_size, + 64); // burst size + + int mac = 0xBEEF0000; + mnic = new VciMultiNic( + "mnic", + IntTab(cluster_id, tgtid_mnic), + mtd, + nic_channels, + mac, // mac_4 address + 0xBABE, // mac_2 address + nic_rx_name, + nic_tx_name); + + + + ///////////////////////////////////////////// + chbuf = new VciChbufDma( + "chbuf_dma", + mtd, + IntTab(cluster_id, nb_procs + 2), + IntTab(cluster_id, tgtid_chbuf), + 64, + chbufdma_channels); + + ///////////////////////////////////////////// + std::vector vect_names; + for (size_t tid = 0; tid < nb_ttys; tid++) + { + std::ostringstream term_name; + term_name << "term" << tid; + vect_names.push_back(term_name.str().c_str()); + } + mtty = new VciMultiTty( + "mtty", + IntTab(cluster_id, tgtid_mtty), + mtd, + vect_names); + + simhelper = new VciSimhelper( + "sim_helper", + IntTab(cluster_id, tgtid_simh), + mtd); + } + + //////////////////////////////////// + // Connections are defined here + //////////////////////////////////// + + //////////////////////// CMD ROUTER and RSP ROUTER + router_cmd->p_clk (this->p_clk); + router_cmd->p_resetn (this->p_resetn); + router_rsp->p_clk (this->p_clk); + router_rsp->p_resetn (this->p_resetn); + + for (int i = 0; i < 4; i++) + { + for (int k = 0; k < 3; k++) + { + router_cmd->p_out[i][k] (this->p_cmd_out[i][k]); + router_cmd->p_in[i][k] (this->p_cmd_in[i][k]); + } + + for (int k = 0; k < 2; k++) + { + router_rsp->p_out[i][k] (this->p_rsp_out[i][k]); + router_rsp->p_in[i][k] (this->p_rsp_in[i][k]); + } + } + + router_cmd->p_out[4][0] (signal_dspin_cmd_g2l_d); + router_cmd->p_out[4][1] (signal_dspin_m2p_g2l_c); + router_cmd->p_out[4][2] (signal_dspin_clack_g2l_c); + router_cmd->p_in[4][0] (signal_dspin_cmd_l2g_d); + router_cmd->p_in[4][1] (signal_dspin_m2p_l2g_c); + router_cmd->p_in[4][2] (signal_dspin_clack_l2g_c); + + router_rsp->p_out[4][0] (signal_dspin_rsp_g2l_d); + router_rsp->p_out[4][1] (signal_dspin_p2m_g2l_c); + router_rsp->p_in[4][0] (signal_dspin_rsp_l2g_d); + router_rsp->p_in[4][1] (signal_dspin_p2m_l2g_c); + + + std::cout << " - CMD & RSP routers connected" << std::endl; + + wi_xbar_d->p_clk (this->p_clk); + wi_xbar_d->p_resetn (this->p_resetn); + wi_xbar_d->p_vci (signal_vci_l2g_d); + wi_xbar_d->p_dspin_cmd (signal_dspin_cmd_l2g_d); + wi_xbar_d->p_dspin_rsp (signal_dspin_rsp_g2l_d); + + std::cout << " - Wrapper Ini VCI2DSPIN Direct connected" << std::endl; + + wt_xbar_d->p_clk (this->p_clk); + wt_xbar_d->p_resetn (this->p_resetn); + wt_xbar_d->p_vci (signal_vci_g2l_d); + wt_xbar_d->p_dspin_cmd (signal_dspin_cmd_g2l_d); + wt_xbar_d->p_dspin_rsp (signal_dspin_rsp_l2g_d); + + std::cout << " - Wrapper Tgt VCI2DSPIN Direct connected" << std::endl; + + ///////////////////// CMD VCI local crossbar direct + xbar_d->p_clk (this->p_clk); + xbar_d->p_resetn (this->p_resetn); + xbar_d->p_target_to_up (signal_vci_g2l_d); + xbar_d->p_initiator_to_up (signal_vci_l2g_d); + + xbar_d->p_to_target[tgtid_memc] (signal_vci_tgt_memc); + xbar_d->p_to_target[tgtid_xicu] (signal_vci_tgt_xicu); + xbar_d->p_to_target[tgtid_mdma] (signal_vci_tgt_mdma); + + xbar_d->p_to_initiator[nb_procs] (signal_vci_ini_mdma); + + for (size_t p = 0; p < nb_procs; p++) + xbar_d->p_to_initiator[p] (signal_vci_ini_proc[p]); + + if (io) + { + xbar_d->p_to_target[tgtid_mtty] (signal_vci_tgt_mtty); + xbar_d->p_to_target[tgtid_brom] (signal_vci_tgt_brom); + xbar_d->p_to_target[tgtid_bdev] (signal_vci_tgt_bdev); + xbar_d->p_to_target[tgtid_fbuf] (signal_vci_tgt_fbuf); + xbar_d->p_to_target[tgtid_mnic] (signal_vci_tgt_mnic); + xbar_d->p_to_target[tgtid_chbuf] (signal_vci_tgt_chbuf); + xbar_d->p_to_target[tgtid_simh] (signal_vci_tgt_simh); + + xbar_d->p_to_initiator[nb_procs + 1] (signal_vci_ini_bdev); + xbar_d->p_to_initiator[nb_procs + 2] (signal_vci_ini_chbuf); + } + + std::cout << " - Direct crossbar connected" << std::endl; + + ////////////////////// M2P DSPIN local crossbar coherence + xbar_m2p_c->p_clk (this->p_clk); + xbar_m2p_c->p_resetn (this->p_resetn); + xbar_m2p_c->p_global_out (signal_dspin_m2p_l2g_c); + xbar_m2p_c->p_global_in (signal_dspin_m2p_g2l_c); + xbar_m2p_c->p_local_in[0] (signal_dspin_m2p_memc); + for (size_t p = 0; p < nb_procs; p++) + xbar_m2p_c->p_local_out[p] (signal_dspin_m2p_proc[p]); + + std::cout << " - M2P Coherence crossbar connected" << std::endl; + + ////////////////////// CLACK DSPIN local crossbar coherence + xbar_clack_c->p_clk (this->p_clk); + xbar_clack_c->p_resetn (this->p_resetn); + xbar_clack_c->p_global_out (signal_dspin_clack_l2g_c); + xbar_clack_c->p_global_in (signal_dspin_clack_g2l_c); + xbar_clack_c->p_local_in[0] (signal_dspin_clack_memc); + for (size_t p = 0; p < nb_procs; p++) + xbar_clack_c->p_local_out[p] (signal_dspin_clack_proc[p]); + + std::cout << " - Clack Coherence crossbar connected" << std::endl; + + ////////////////////////// P2M DSPIN local crossbar coherence + xbar_p2m_c->p_clk (this->p_clk); + xbar_p2m_c->p_resetn (this->p_resetn); + xbar_p2m_c->p_global_out (signal_dspin_p2m_l2g_c); + xbar_p2m_c->p_global_in (signal_dspin_p2m_g2l_c); + xbar_p2m_c->p_local_out[0] (signal_dspin_p2m_memc); + for (size_t p = 0; p < nb_procs; p++) + xbar_p2m_c->p_local_in[p] (signal_dspin_p2m_proc[p]); + + std::cout << " - P2M Coherence crossbar connected" << std::endl; + + + //////////////////////////////////// Processors + for (size_t p = 0; p < nb_procs; p++) + { + proc[p]->p_clk (this->p_clk); + proc[p]->p_resetn (this->p_resetn); + proc[p]->p_vci (signal_vci_ini_proc[p]); + proc[p]->p_dspin_m2p (signal_dspin_m2p_proc[p]); + proc[p]->p_dspin_p2m (signal_dspin_p2m_proc[p]); + proc[p]->p_dspin_clack (signal_dspin_clack_proc[p]); + + for ( size_t i = 0; i < irq_per_processor; i++) + { + proc[p]->p_irq[i] (signal_proc_it[p*irq_per_processor + i]); + } + for ( size_t j = irq_per_processor; j < 6; j++) // 6 = number of irqs in the MIPS + { + proc[p]->p_irq[j] (signal_false); + } + + } + + std::cout << " - Processors connected" << std::endl; + + ///////////////////////////////////// XICU + xicu->p_clk (this->p_clk); + xicu->p_resetn (this->p_resetn); + xicu->p_vci (signal_vci_tgt_xicu); + for (size_t p = 0; p < nb_procs * irq_per_processor; p++) + { + xicu->p_irq[p] (signal_proc_it[p]); + } + for (size_t i = 0; i < 32; i++) + { + if (io) // I/O cluster + { + if (i < 8) xicu->p_hwi[i] (signal_false); + else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i - 8]); + else if (i < 16) xicu->p_hwi[i] (signal_false); + else if (i < (16 + nb_ttys)) xicu->p_hwi[i] (signal_irq_mtty[i - 16]); + else if (i < 30) xicu->p_hwi[i] (signal_false); + else if (i < 31) xicu->p_hwi[i] (signal_irq_memc); + else xicu->p_hwi[i] (signal_irq_bdev); + } + else // other clusters + { + if (i < 8) xicu->p_hwi[i] (signal_false); + else if (i < (8 + nb_dmas)) xicu->p_hwi[i] (signal_irq_mdma[i - 8]); + else if (i < 30) xicu->p_hwi[i] (signal_false); + else if (i < 31) xicu->p_hwi[i] (signal_irq_memc); + else xicu->p_hwi[i] (signal_false); + } + } + + std::cout << " - XICU connected" << std::endl; + + //////////////////////////////////////////////// MEMC + memc->p_clk (this->p_clk); + memc->p_resetn (this->p_resetn); + memc->p_irq (signal_irq_memc); + memc->p_vci_ixr (signal_vci_xram); + memc->p_vci_tgt (signal_vci_tgt_memc); + memc->p_dspin_p2m (signal_dspin_p2m_memc); + memc->p_dspin_m2p (signal_dspin_m2p_memc); + memc->p_dspin_clack (signal_dspin_clack_memc); + + std::cout << " - MEMC connected" << std::endl; + + /////////////////////////////////////////////// XRAM + xram->p_clk (this->p_clk); + xram->p_resetn (this->p_resetn); + xram->p_vci (signal_vci_xram); + + std::cout << " - XRAM connected" << std::endl; + + ////////////////////////////////////////////// MDMA + mdma->p_clk (this->p_clk); + mdma->p_resetn (this->p_resetn); + mdma->p_vci_target (signal_vci_tgt_mdma); + mdma->p_vci_initiator (signal_vci_ini_mdma); + for (size_t i = 0; i < nb_dmas; i++) + mdma->p_irq[i] (signal_irq_mdma[i]); + + std::cout << " - MDMA connected" << std::endl; + + /////////////////////////////// Components in I/O cluster + + if (io) + { + // BDEV + bdev->p_clk (this->p_clk); + bdev->p_resetn (this->p_resetn); + bdev->p_irq (signal_irq_bdev); + bdev->p_vci_target (signal_vci_tgt_bdev); + bdev->p_vci_initiator (signal_vci_ini_bdev); + + std::cout << " - BDEV connected" << std::endl; + + // FBUF + fbuf->p_clk (this->p_clk); + fbuf->p_resetn (this->p_resetn); + fbuf->p_vci (signal_vci_tgt_fbuf); + + std::cout << " - FBUF connected" << std::endl; + + // MNIC + mnic->p_clk (this->p_clk); + mnic->p_resetn (this->p_resetn); + mnic->p_vci (signal_vci_tgt_mnic); + for (size_t i = 0; i < nic_channels; i++) + { + mnic->p_rx_irq[i] (signal_irq_mnic_rx[i]); + mnic->p_tx_irq[i] (signal_irq_mnic_tx[i]); + } + + std::cout << " - MNIC connected" << std::endl; + + // CHBUF + chbuf->p_clk (this->p_clk); + chbuf->p_resetn (this->p_resetn); + chbuf->p_vci_target (signal_vci_tgt_chbuf); + chbuf->p_vci_initiator (signal_vci_ini_chbuf); + for (size_t i = 0; i < chbufdma_channels; i++) + { + chbuf->p_irq[i] (signal_irq_chbuf[i]); + } + + std::cout << " - CHBUF connected" << std::endl; + + // BROM + brom->p_clk (this->p_clk); + brom->p_resetn (this->p_resetn); + brom->p_vci (signal_vci_tgt_brom); + + std::cout << " - BROM connected" << std::endl; + + // MTTY + mtty->p_clk (this->p_clk); + mtty->p_resetn (this->p_resetn); + mtty->p_vci (signal_vci_tgt_mtty); + for (size_t i = 0; i < nb_ttys; i++) + { + mtty->p_irq[i] (signal_irq_mtty[i]); + } + + std::cout << " - MTTY connected" << std::endl; + + + // Sim Helper + simhelper->p_clk (this->p_clk); + simhelper->p_resetn (this->p_resetn); + simhelper->p_vci (signal_vci_tgt_simh); + + std::cout << " - SIMH connected" << std::endl; + } +} // end constructor + + + +template TsarXbarCluster::~TsarXbarCluster() { + + dealloc_elems > (p_cmd_in, 4, 3); + dealloc_elems >(p_cmd_out, 4, 3); + dealloc_elems > (p_rsp_in, 4, 2); + dealloc_elems >(p_rsp_out, 4, 2); + + for (size_t p = 0; p < n_procs; p++) + { + delete proc[p]; + } + + delete memc; + delete xram; + delete xicu; + delete mdma; + delete xbar_d; + delete wt_xbar_d; + delete wi_xbar_d; + delete xbar_m2p_c; + delete xbar_p2m_c; + delete xbar_clack_c; + delete router_cmd; + delete router_rsp; + if (brom != NULL) + { + delete brom; + delete fbuf; + delete bdev; + delete mnic; + delete chbuf; + delete mtty; + delete simhelper; + } +} + + +}} + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + + + Index: /branches/fault_tolerance/platforms/tsar_mono_mmu/Makefile =================================================================== --- /branches/fault_tolerance/platforms/tsar_mono_mmu/Makefile (revision 724) +++ /branches/fault_tolerance/platforms/tsar_mono_mmu/Makefile (revision 724) @@ -0,0 +1,7 @@ +simul.x: top.cpp top.desc + soclib-cc -j8 -P -p top.desc -I. -o simul.x + +clean: + soclib-cc -x -p top.desc -I. + rm -rf *.o *.x tty* + Index: /branches/fault_tolerance/platforms/tsar_mono_mmu/top.cpp =================================================================== --- /branches/fault_tolerance/platforms/tsar_mono_mmu/top.cpp (revision 724) +++ /branches/fault_tolerance/platforms/tsar_mono_mmu/top.cpp (revision 724) @@ -0,0 +1,531 @@ + +#include +#include +#include +#include +#include +#ifdef _OPENMP +#include +#endif + +#include "mapping_table.h" +#include "mips32.h" +#include "vci_simple_ram.h" +#include "vci_multi_tty.h" +#include "vci_mem_cache.h" +#include "vci_cc_vcache_wrapper.h" +#include "vci_logger.h" +#include "vci_xicu.h" +#include "vci_multi_dma.h" +#include "vci_simhelper.h" +#include "dspin_local_crossbar.h" +#include "vci_dspin_initiator_wrapper.h" +#include "vci_dspin_target_wrapper.h" + + // Define VCI parameters +#define cell_width 4 +#define cell_width_ext 8 +#define address_width 32 +#define plen_width 8 +#define error_width 1 +#define clen_width 1 +#define rflag_width 1 +#define srcid_width 14 +#define pktid_width 4 +#define trdid_width 4 +#define wrplen_width 1 + +#define dspin_cmd_width 39 +#define dspin_rsp_width 32 +// segments definition in direct space + +#define XICU_BASE 0xd8200000 +#define XICU_SIZE 0x00001000 + +#define MDMA_BASE 0xe8000000 +#define MDMA_SIZE 0x00000014 + +#define MTTY_BASE 0xd0200000 +#define MTTY_SIZE 0x00000010 + +#define EXIT_BASE 0xe0000000 +#define EXIT_SIZE 0x00000010 + +#define BOOT_BASE 0xbfc00000 +#define BOOT_SIZE 0x00040000 + +#define MEMC_BASE 0x00000000 +#define MEMC_SIZE 0x02000000 + +int _main(int argc, char *argv[]) +{ + using namespace sc_core; + // Avoid repeating these everywhere + using soclib::common::IntTab; + using soclib::common::Segment; + using namespace soclib::caba; +#ifdef _OPENMP + omp_set_dynamic(false); + omp_set_num_threads(1); + std::cerr << "Built with openmp version " << _OPENMP << std::endl; +#endif + char soft_name[256] = "test.elf"; // pathname to binary code + size_t ncycles = 1000000000; // max number of simulation cycles + + bool trace_ok = false; + size_t from_cycle = 0; // debug start cycle + size_t max_frozen = 100000; // max number of frozen cycles + + /////////////// command line arguments //////////////// + if (argc > 1) + { + for( int n=1 ; n vci_param; + typedef soclib::caba::VciParams vci_param_ext; + typedef soclib::common::Mips32ElIss proc_iss; + + // Direct DSPIN signals to local crossbars + DspinSignals signal_dspin_cmd_proc0_i; + DspinSignals signal_dspin_rsp_proc0_i; + DspinSignals signal_dspin_cmd_dma_i; + DspinSignals signal_dspin_rsp_dma_i; + + DspinSignals signal_dspin_cmd_memc_t; + DspinSignals signal_dspin_rsp_memc_t; + DspinSignals signal_dspin_cmd_xicu_t; + DspinSignals signal_dspin_rsp_xicu_t; + DspinSignals signal_dspin_cmd_dma_t; + DspinSignals signal_dspin_rsp_dma_t; + DspinSignals signal_dspin_cmd_tty_t; + DspinSignals signal_dspin_rsp_tty_t; + DspinSignals signal_dspin_cmd_rom_t; + DspinSignals signal_dspin_rsp_rom_t; + DspinSignals signal_dspin_cmd_simh_t; + DspinSignals signal_dspin_rsp_simh_t; + + // Coherence DSPIN signals to local crossbar + DspinSignals signal_dspin_cmd_l2g_c; + DspinSignals signal_dspin_cmd_g2l_c; + DspinSignals signal_dspin_rsp_l2g_c; + DspinSignals signal_dspin_rsp_g2l_c; + DspinSignals signal_dspin_m2p_l2g_c; + DspinSignals signal_dspin_m2p_g2l_c; + DspinSignals signal_dspin_p2m_l2g_c; + DspinSignals signal_dspin_p2m_g2l_c; + DspinSignals signal_dspin_clack_l2g_c; + DspinSignals signal_dspin_clack_g2l_c; + + DspinSignals signal_dspin_m2p_memc; + DspinSignals signal_dspin_clack_memc; + DspinSignals signal_dspin_p2m_memc; + DspinSignals signal_dspin_m2p_proc[1]; + DspinSignals signal_dspin_clack_proc[1]; + DspinSignals signal_dspin_p2m_proc[1]; + + // Mapping table + + soclib::common::MappingTable maptabp(32, IntTab(0, 16), IntTab(0, srcid_width), 0xF0000000); + + maptabp.add(Segment("mc_m" , MEMC_BASE , MEMC_SIZE , IntTab(0, 0), true)); + maptabp.add(Segment("boot", BOOT_BASE, BOOT_SIZE, IntTab(0, 1), true)); + maptabp.add(Segment("tty" , MTTY_BASE , MTTY_SIZE , IntTab(0, 2), false)); + maptabp.add(Segment("xicu" , XICU_BASE , XICU_SIZE , IntTab(0, 3), false)); + maptabp.add(Segment("dma", MDMA_BASE, MDMA_SIZE, IntTab(0, 4), false)); + maptabp.add(Segment("simh", EXIT_BASE, EXIT_SIZE, IntTab(0, 5), false)); + + std::cout << maptabp << std::endl; + + soclib::common::MappingTable maptabx(32, IntTab(8), IntTab(8), 0x30000000); + maptabx.add(Segment("xram" , MEMC_BASE , MEMC_SIZE , IntTab(0), false)); + + + std::cout << maptabx << std::endl; + + // Signals + + sc_clock signal_clk ("clk"); + sc_signal signal_resetn("resetn"); + + sc_signal signal_proc0_it0("signal_proc0_it0"); + sc_signal signal_proc0_it1("signal_proc0_it1"); + sc_signal signal_proc0_it2("signal_proc0_it2"); + sc_signal signal_proc0_it3("signal_proc0_it3"); + sc_signal signal_proc0_it4("signal_proc0_it4"); + sc_signal signal_proc0_it5("signal_proc0_it5"); + + soclib::caba::VciSignals signal_vci_ini_rw_proc0 + ("vci_ini_rw_proc0"); + soclib::caba::VciSignals signal_vci_tty + ("signal_vci_tty"); + soclib::caba::VciSignals signal_vci_simh + ("signal_vci_simh"); + + soclib::caba::VciSignals signal_vci_xicu + ("signal_vci_xicu"); + soclib::caba::VciSignals signal_vci_dmai + ("signal_vci_dmai"); + soclib::caba::VciSignals signal_vci_dmat + ("signal_vci_dmat"); + soclib::caba::VciSignals signal_vci_tgt_rom + ("vci_tgt_rom"); + + soclib::caba::VciSignals signal_vci_ixr_memc + ("vci_ixr_memc"); + soclib::caba::VciSignals signal_vci_tgt_memc + ("vci_tgt_memc"); + sc_signal signal_icu_irq0("signal_icu_irq0"); + sc_signal signal_icu_irq1("signal_icu_irq1"); + sc_signal signal_icu_irq2("signal_icu_irq2"); + + soclib::common::Loader loader("test.elf"); + + // init_rw init_c tgt + soclib::caba::VciCcVCacheWrapper *proc0; + soclib::caba::VciSimpleRam *rom; + soclib::caba::VciSimpleRam *xram; + soclib::caba::VciMemCache *memc; + soclib::caba::VciXicu *vcixicu; + soclib::caba::VciMultiTty *vcitty; + soclib::caba::VciSimhelper *vcisimh; + soclib::caba::VciMultiDma *vcidma; + DspinLocalCrossbar* xbar_cmd_d; + DspinLocalCrossbar* xbar_rsp_d; + DspinLocalCrossbar* xbar_m2p_c; + DspinLocalCrossbar* xbar_p2m_c; + DspinLocalCrossbar* xbar_clack_c; + + proc0 = new soclib::caba::VciCcVCacheWrapper + ("proc0", 0, maptabp, IntTab(0, 0), 0, + 8,8,8,8,4,64,16,4,64,16,4, 4, 0, 0, max_frozen, from_cycle, trace_ok); + VciDspinInitiatorWrapper + wi_proc0("wi_proc0", srcid_width); + + vcisimh = new soclib::caba::VciSimhelper + ("vcisimh", IntTab(0, 5), maptabp); + VciDspinTargetWrapper + wt_simh("wt_simh", srcid_width); + + vcidma = new soclib::caba::VciMultiDma + ("vcidma", maptabp, IntTab(0, 1), IntTab(0, 4), 64, 1);//(1<<(vci_param::K-1))); + VciDspinInitiatorWrapper + wi_dma("wi_dma", srcid_width); + VciDspinTargetWrapper + wt_dma("wt_dma", srcid_width); + + vcitty = new soclib::caba::VciMultiTty + ("vcitty", IntTab(0, 2), maptabp, "vcitty0", NULL); + VciDspinTargetWrapper + wt_tty("wt_tty", srcid_width); + + rom = new soclib::caba::VciSimpleRam + ("rom", IntTab(0, 1), maptabp, loader); + VciDspinTargetWrapper + wt_rom("wt_rom", srcid_width); + + vcixicu = new soclib::caba::VciXicu + ("vcixicu", maptabp, IntTab(0, 3), 4 /* npti */, 2 /* nhwi */, 4 /* nwti */, 6 /* nirq */); + VciDspinTargetWrapper + wt_xicu("wt_xicu", srcid_width); + + xram = new soclib::caba::VciSimpleRam + ("xram", IntTab(0), maptabx, loader); + memc = new soclib::caba::VciMemCache + ("memc",maptabp,maptabx,IntTab(0),IntTab(0, 0), 0, 0,16,256,16, 3, 4096, 8, 8, 8, from_cycle, trace_ok); + VciDspinTargetWrapper + wt_memc("wt_memc", srcid_width); + + xbar_cmd_d = new DspinLocalCrossbar( + "xbar_cmd_d", + maptabp, // mapping table + 0, 0, // cluster coordinates + 0, 0, srcid_width, + 2, // number of local of sources + 6, // number of local dests + 2, 2, // fifo depths + true, // CMD + true, // use local routing table + false ); // no broadcast + + xbar_rsp_d = new DspinLocalCrossbar( + "xbar_rsp_d", + maptabp, // mapping table + 0, 0, // cluster coordinates + 0, 0, srcid_width, + 6, // number of local sources + 2, // number of local dests + 2, 2, // fifo depths + false, // RSP + false, // don't use local routing table + false ); // no broadcast + + xbar_m2p_c = new DspinLocalCrossbar( + "xbar_m2p_c", maptabp, 0, 0, 0, 0, srcid_width, + 1, 1, 2, 2, true, false, true); + xbar_p2m_c = new DspinLocalCrossbar( + "xbar_p2m_c", maptabp, 0, 0, 0, 0, 0, + 1, 1, 2, 2, false, false, false); + xbar_clack_c = new DspinLocalCrossbar( + "xbar_clack_c", maptabp, 0, 0, 0, 0, srcid_width, + 1, 1, 1, 1, true, false, false); +#ifdef VCI_LOGGER_ON_L1 + soclib::caba::VciLogger vci_logger0("vci_logger0",maptabp); +#endif +#ifdef VCI_LOGGER_ON_ROM + soclib::caba::VciLogger vci_logger1("vci_logger1",maptabp); +#endif +#ifdef VCI_LOGGER_ON_L1_TGT + soclib::caba::VciLogger vci_logger2("vci_logger2",maptabp); +#endif + proc0->p_clk(signal_clk); + proc0->p_resetn(signal_resetn); + proc0->p_irq[0](signal_proc0_it0); + proc0->p_irq[1](signal_proc0_it1); + proc0->p_irq[2](signal_proc0_it2); + proc0->p_irq[3](signal_proc0_it3); + proc0->p_irq[4](signal_proc0_it4); + proc0->p_irq[5](signal_proc0_it5); + proc0->p_vci(signal_vci_ini_rw_proc0); + proc0->p_dspin_m2p(signal_dspin_m2p_proc[0]); + proc0->p_dspin_p2m(signal_dspin_p2m_proc[0]); + proc0->p_dspin_clack(signal_dspin_clack_proc[0]); + wi_proc0.p_clk(signal_clk); + wi_proc0.p_resetn(signal_resetn); + wi_proc0.p_vci(signal_vci_ini_rw_proc0); + wi_proc0.p_dspin_cmd(signal_dspin_cmd_proc0_i); + wi_proc0.p_dspin_rsp(signal_dspin_rsp_proc0_i); + + rom->p_clk(signal_clk); + rom->p_resetn(signal_resetn); + rom->p_vci(signal_vci_tgt_rom); + wt_rom.p_clk(signal_clk); + wt_rom.p_resetn(signal_resetn); + wt_rom.p_vci(signal_vci_tgt_rom); + wt_rom.p_dspin_cmd(signal_dspin_cmd_rom_t); + wt_rom.p_dspin_rsp(signal_dspin_rsp_rom_t); + + vcixicu->p_resetn(signal_resetn); + vcixicu->p_clk(signal_clk); + vcixicu->p_vci(signal_vci_xicu); + vcixicu->p_hwi[0](signal_icu_irq0); + vcixicu->p_hwi[1](signal_icu_irq1); + vcixicu->p_hwi[2](signal_icu_irq2); + vcixicu->p_irq[0](signal_proc0_it0); + vcixicu->p_irq[1](signal_proc0_it1); + vcixicu->p_irq[2](signal_proc0_it2); + vcixicu->p_irq[3](signal_proc0_it3); + vcixicu->p_irq[4](signal_proc0_it4); + vcixicu->p_irq[5](signal_proc0_it5); + wt_xicu.p_clk(signal_clk); + wt_xicu.p_resetn(signal_resetn); + wt_xicu.p_vci(signal_vci_xicu); + wt_xicu.p_dspin_cmd(signal_dspin_cmd_xicu_t); + wt_xicu.p_dspin_rsp(signal_dspin_rsp_xicu_t); + + vcidma->p_clk(signal_clk); + vcidma->p_resetn(signal_resetn); + vcidma->p_irq[0](signal_icu_irq1); + vcidma->p_vci_target(signal_vci_dmat); + vcidma->p_vci_initiator(signal_vci_dmai); + wt_dma.p_clk(signal_clk); + wt_dma.p_resetn(signal_resetn); + wt_dma.p_vci(signal_vci_dmat); + wt_dma.p_dspin_cmd(signal_dspin_cmd_dma_t); + wt_dma.p_dspin_rsp(signal_dspin_rsp_dma_t); + wi_dma.p_clk(signal_clk); + wi_dma.p_resetn(signal_resetn); + wi_dma.p_vci(signal_vci_dmai); + wi_dma.p_dspin_cmd(signal_dspin_cmd_dma_i); + wi_dma.p_dspin_rsp(signal_dspin_rsp_dma_i); + + +#ifdef VCI_LOGGER_ON_L1 + vci_logger0.p_clk(signal_clk); + vci_logger0.p_resetn(signal_resetn); + vci_logger0.p_vci(signal_vci_ini_rw_proc0); +#endif + +#ifdef VCI_LOGGER_ON_ROM + vci_logger1.p_clk(signal_clk); + vci_logger1.p_resetn(signal_resetn); + vci_logger1.p_vci(signal_vci_tgt_rom); +#endif + +#ifdef VCI_LOGGER_ON_L1_TGT + vci_logger2.p_clk(signal_clk); + vci_logger2.p_resetn(signal_resetn); +#endif + + vcitty->p_clk(signal_clk); + vcitty->p_resetn(signal_resetn); + vcitty->p_vci(signal_vci_tty); + vcitty->p_irq[0](signal_icu_irq0); + wt_tty.p_clk(signal_clk); + wt_tty.p_resetn(signal_resetn); + wt_tty.p_vci(signal_vci_tty); + wt_tty.p_dspin_cmd(signal_dspin_cmd_tty_t); + wt_tty.p_dspin_rsp(signal_dspin_rsp_tty_t); + + vcisimh->p_clk(signal_clk); + vcisimh->p_resetn(signal_resetn); + vcisimh->p_vci(signal_vci_simh); + wt_simh.p_clk(signal_clk); + wt_simh.p_resetn(signal_resetn); + wt_simh.p_vci(signal_vci_simh); + wt_simh.p_dspin_cmd(signal_dspin_cmd_simh_t); + wt_simh.p_dspin_rsp(signal_dspin_rsp_simh_t); + + memc->p_clk(signal_clk); + memc->p_resetn(signal_resetn); + memc->p_irq(signal_icu_irq2); + memc->p_vci_tgt(signal_vci_tgt_memc); + memc->p_dspin_p2m(signal_dspin_p2m_memc); + memc->p_dspin_m2p(signal_dspin_m2p_memc); + memc->p_dspin_clack(signal_dspin_clack_memc); + memc->p_vci_ixr(signal_vci_ixr_memc); + wt_memc.p_clk(signal_clk); + wt_memc.p_resetn(signal_resetn); + wt_memc.p_vci(signal_vci_tgt_memc); + wt_memc.p_dspin_cmd(signal_dspin_cmd_memc_t); + wt_memc.p_dspin_rsp(signal_dspin_rsp_memc_t); + + xram->p_clk(signal_clk); + xram->p_resetn(signal_resetn); + xram->p_vci(signal_vci_ixr_memc); + + + xbar_cmd_d->p_clk(signal_clk); + xbar_cmd_d->p_resetn(signal_resetn); + xbar_rsp_d->p_clk(signal_clk); + xbar_rsp_d->p_resetn(signal_resetn); + xbar_m2p_c->p_clk(signal_clk); + xbar_m2p_c->p_resetn(signal_resetn); + xbar_clack_c->p_clk(signal_clk); + xbar_clack_c->p_resetn(signal_resetn); + xbar_p2m_c->p_clk(signal_clk); + xbar_p2m_c->p_resetn(signal_resetn); + + xbar_cmd_d->p_global_out(signal_dspin_cmd_l2g_c); + xbar_cmd_d->p_global_in(signal_dspin_cmd_g2l_c); + xbar_rsp_d->p_global_out(signal_dspin_rsp_l2g_c); + xbar_rsp_d->p_global_in(signal_dspin_rsp_g2l_c); + xbar_m2p_c->p_global_out(signal_dspin_m2p_l2g_c); + xbar_m2p_c->p_global_in(signal_dspin_m2p_g2l_c); + xbar_clack_c->p_global_out(signal_dspin_clack_l2g_c); + xbar_clack_c->p_global_in(signal_dspin_clack_g2l_c); + xbar_p2m_c->p_global_out(signal_dspin_p2m_l2g_c); + xbar_p2m_c->p_global_in(signal_dspin_p2m_g2l_c); + + xbar_cmd_d->p_local_in[0](signal_dspin_cmd_proc0_i); + xbar_cmd_d->p_local_in[1](signal_dspin_cmd_dma_i); + xbar_cmd_d->p_local_out[0](signal_dspin_cmd_memc_t); + xbar_cmd_d->p_local_out[1](signal_dspin_cmd_rom_t); + xbar_cmd_d->p_local_out[2](signal_dspin_cmd_tty_t); + xbar_cmd_d->p_local_out[3](signal_dspin_cmd_xicu_t); + xbar_cmd_d->p_local_out[4](signal_dspin_cmd_dma_t); + xbar_cmd_d->p_local_out[5](signal_dspin_cmd_simh_t); + + xbar_rsp_d->p_local_out[0](signal_dspin_rsp_proc0_i); + xbar_rsp_d->p_local_out[1](signal_dspin_rsp_dma_i); + xbar_rsp_d->p_local_in[0](signal_dspin_rsp_memc_t); + xbar_rsp_d->p_local_in[1](signal_dspin_rsp_rom_t); + xbar_rsp_d->p_local_in[2](signal_dspin_rsp_tty_t); + xbar_rsp_d->p_local_in[3](signal_dspin_rsp_xicu_t); + xbar_rsp_d->p_local_in[4](signal_dspin_rsp_dma_t); + xbar_rsp_d->p_local_in[5](signal_dspin_rsp_simh_t); + + xbar_m2p_c->p_local_in[0](signal_dspin_m2p_memc); + xbar_m2p_c->p_local_out[0](signal_dspin_m2p_proc[0]); + + xbar_clack_c->p_local_in[0](signal_dspin_clack_memc); + xbar_clack_c->p_local_out[0](signal_dspin_clack_proc[0]); + + xbar_p2m_c->p_local_out[0](signal_dspin_p2m_memc); + xbar_p2m_c->p_local_in[0](signal_dspin_p2m_proc[0]); + + sc_start(sc_core::sc_time(0, SC_NS)); + signal_resetn = false; + + sc_start(sc_core::sc_time(1, SC_NS)); + signal_resetn = true; + + + for ( size_t n=1 ; n from_cycle) ) + { + std::cout << "****************** cycle " << std::dec << n + << " ************************************************" << std::endl; + proc0->print_trace(); + memc->print_trace(); + signal_vci_ini_rw_proc0.print_trace("signal_vci_ini_rw_proc0"); + signal_vci_tgt_memc.print_trace("signal_vci_tgt_memc"); + signal_vci_ixr_memc.print_trace("signal_vci_ixr_memc"); + } + sc_start(sc_core::sc_time(1, SC_NS)); + } + return EXIT_FAILURE; + +} + +int sc_main (int argc, char *argv[]) +{ + try { + return _main(argc, argv); + } catch (std::exception &e) { + std::cout << e.what() << std::endl; + } catch (...) { + std::cout << "Unknown exception occured" << std::endl; + throw; + } + return 1; +} + Index: /branches/fault_tolerance/platforms/tsar_mono_mmu/top.desc =================================================================== --- /branches/fault_tolerance/platforms/tsar_mono_mmu/top.desc (revision 724) +++ /branches/fault_tolerance/platforms/tsar_mono_mmu/top.desc (revision 724) @@ -0,0 +1,53 @@ + +# -*- python -*- + +dspin_cmd_flit_size = 39 +dspin_rsp_flit_size = 32 +cell_size = 4 + +todo = Platform('caba', 'top.cpp', + uses = [ + Uses('caba:vci_cc_vcache_wrapper', + dspin_in_width = dspin_cmd_flit_size, + dspin_out_width = dspin_rsp_flit_size, + iss_t = 'common:mips32el'), + Uses('caba:vci_simple_ram'), + Uses('caba:vci_simple_ram', cell_size = 8), + Uses('caba:vci_multi_tty'), + Uses('caba:vci_xicu'), + Uses('caba:vci_multi_dma'), + Uses('caba:vci_simhelper'), + Uses('caba:vci_logger'), + Uses('caba:vci_mem_cache', + memc_cell_size_int = cell_size, + memc_cell_size_ext = 8, + dspin_out_width = dspin_cmd_flit_size, + dspin_in_width = dspin_rsp_flit_size, + ), + Uses('caba:dspin_local_crossbar', + flit_width = dspin_cmd_flit_size), + Uses('caba:dspin_local_crossbar', + flit_width = dspin_rsp_flit_size), + Uses('caba:vci_dspin_target_wrapper', + dspin_cmd_width = dspin_cmd_flit_size, + dspin_rsp_width = dspin_rsp_flit_size, + cell_size = cell_size), + Uses('caba:vci_dspin_initiator_wrapper', + dspin_cmd_width = dspin_cmd_flit_size, + dspin_rsp_width = dspin_rsp_flit_size, + cell_size = cell_size), + Uses('common:elf_file_loader'), + + ], + cell_size = cell_size, + plen_size = 8, + addr_size = 32, + rerror_size = 1, + clen_size = 1, + rflag_size = 1, + srcid_size = 14, + pktid_size = 4, + trdid_size = 4, + wrplen_size = 1 +) + Index: /branches/fault_tolerance/softs/giet_tsar/block_device.h =================================================================== --- /branches/fault_tolerance/softs/giet_tsar/block_device.h (revision 724) +++ /branches/fault_tolerance/softs/giet_tsar/block_device.h (revision 724) @@ -0,0 +1,68 @@ +/* + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, Asim + * Nicolas Pouillon , 2007 + * + * Maintainers: nipo + */ +#ifndef BLOCK_DEVICE_REGS_H +#define BLOCK_DEVICE_REGS_H + +enum SoclibBlockDeviceRegisters { + BLOCK_DEVICE_BUFFER, + BLOCK_DEVICE_LBA, + BLOCK_DEVICE_COUNT, + BLOCK_DEVICE_OP, + BLOCK_DEVICE_STATUS, + BLOCK_DEVICE_IRQ_ENABLE, + BLOCK_DEVICE_SIZE, + BLOCK_DEVICE_BLOCK_SIZE, + BLOCK_DEVICE_BUFFER_EXT, +}; + +enum SoclibBlockDeviceOp { + BLOCK_DEVICE_NOOP, + BLOCK_DEVICE_READ, + BLOCK_DEVICE_WRITE, +}; + +enum SoclibBlockDeviceStatus { + BLOCK_DEVICE_IDLE, + BLOCK_DEVICE_BUSY, + BLOCK_DEVICE_READ_SUCCESS, + BLOCK_DEVICE_WRITE_SUCCESS, + BLOCK_DEVICE_READ_ERROR, + BLOCK_DEVICE_WRITE_ERROR, + BLOCK_DEVICE_ERROR, +}; + +#endif /* BLOCK_DEVICE_REGS_H */ + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: /branches/fault_tolerance/softs/giet_tsar/giet.S =================================================================== --- /branches/fault_tolerance/softs/giet_tsar/giet.S (revision 724) +++ /branches/fault_tolerance/softs/giet_tsar/giet.S (revision 724) @@ -0,0 +1,445 @@ +/******************************************************************************** +* File : giet.S +* Author : Alain Greiner +* Date : 15/01/2014 +********************************************************************************* +* This is a very simple Interrupts/Exception/Traps handler for a generic +* multi-clusters / multi-processors TSAR architecture (up to 256 clusters, +* up to 4 processors per cluster). +* The physical address is 40 bits, and the 8 MSB bits A[39:32] define the +* cluster index. +********************************************************************************/ + +#include "hard_config.h" + + .section .giet,"ax",@progbits + .align 2 + .global _interrupt_vector + + .extern seg_xcu_base + .extern seg_tty_base + + .extern _procid + .extern _proctime + .extern _tty_write + .extern _tty_read + .extern _tty_read_irq + .extern _locks_read + .extern _locks_write + .extern _exit + .extern _fb_sync_write + .extern _fb_sync_read + .extern _ioc_write + .extern _ioc_read + .extern _ioc_completed + .extern _itoa_hex + .extern _barrier_init + .extern _barrier_wait + + .ent _giet + +/**************************************************************** +* Cause Table (indexed by the Cause register) +****************************************************************/ +tab_causes: + .word _int_handler /* 0000 : external interrupt */ + .word _cause_ukn /* 0001 : undefined exception */ + .word _cause_ukn /* 0010 : undefined exception */ + .word _cause_ukn /* 0011 : undefined exception */ + .word _cause_adel /* 0100 : illegal address read exception */ + .word _cause_ades /* 0101 : illegal address write exception */ + .word _cause_ibe /* 0110 : instruction bus error exception */ + .word _cause_dbe /* 0111 : data bus error exception */ + .word _sys_handler /* 1000 : system call */ + .word _cause_bp /* 1001 : breakpoint exception */ + .word _cause_ri /* 1010 : illegal codop exception */ + .word _cause_cpu /* 1011 : illegal coprocessor access */ + .word _cause_ovf /* 1100 : arithmetic overflow exception */ + .word _cause_ukn /* 1101 : undefined exception */ + .word _cause_ukn /* 1110 : undefined exception */ + .word _cause_ukn /* 1111 : undefined exception */ + + .space 320 + +/**************************************************************** +* Entry point (base + 0x180) +****************************************************************/ +_giet: + mfc0 $27, $13 /* Cause Register analysis */ + la $26, seg_kcode_base /* $26 <= tab_causes */ + andi $27, $27, 0x3c + addu $26, $26, $27 /* $26 <= &tab_causes[XCODE] */ + lw $26, ($26) + jr $26 /* Jump to tab_causes[XCODE] */ + + .end _giet + +/**************************************************************** +* System Call Handler +* +* As the GIET_TSAR does not support system calls, +* an error message is displayed on TTY0, the program is killed. +****************************************************************/ + .ent _sys_handler + +_sys_handler: + la $4, _msg_uknsyscall /* $4 <= message address */ + li $5, 36 /* $5 <= message length */ + li $6, 0 /* $6 <= TTY0 */ + jal _tty_write /* print unknown message */ + nop + + la $4, _msg_epc /* $4 <= message address */ + li $5, 8 /* $5 <= message length */ + li $6, 0 /* $6 <= TTY0 */ + jal _tty_write /* print EPC message */ + nop + + mfc0 $4, $14 /* $4 <= EPC */ + la $5, _itoa_buffer /* $5 <= buffer address */ + addiu $5, $5, 2 /* skip the 0x prefix */ + jal _itoa_hex /* fill the buffer */ + nop + + la $4, _itoa_buffer /* $4 <= buffer address */ + li $5, 10 /* $5 <= buffer length */ + li $6, 0 /* $6 <= TTY0 */ + jal _tty_write /* print EPC value */ + nop + + j _exit /* end of program */ + +_itoa_buffer: .ascii "0x00000000" + + .align 2 + + .end _sys_handler + +/**************************************************************** +* Interrupt Handler +* This simple interrupt handler cannot be interrupted. +* It uses the SoCLib VCI_XICU component. +* It makes the assumption that there is only one interrupt per +* entry in the interrupt vector (it can be PTI, HWI, or WTI). +* In case of a multi-clusters architecture, it exist one XCU +* per cluster, and the base address of the ICU segment depends +* on both the cluster_xy and the proc_id: +* - base_address = seg_xcu_base + (32*local_id) + (4G*cluster_xy) +* - cluster_xy = proc_id / NB_PROCS_MAX +* - local_id = proc_id % NB_PROCS_MAX +* If no active interrupt is found in the PRIO register, +* nothing is done. +* The interrupt vector (32 ISR addresses array stored at +* _interrupt_vector address) is initialised with the default +* ISR address. The actual ISR addresses are supposed to be written +* in the interrupt vector array by the boot code. +* All non persistant registers, such as $1 to $15, and $24 to $25, +* as well as register $31 and EPC, are saved in the interrupted +* program stack, before calling the Interrupt Service Routine. +* These registers can be used by the ISR code. +***************************************************************/ + .ent _int_handler + +_int_handler: + addiu $29, $29, -23*4 /* stack space reservation */ + .set noat + sw $1, 4*4($29) /* save $1 */ + .set at + sw $2, 4*5($29) /* save $2 */ + sw $3, 4*6($29) /* save $3 */ + sw $4, 4*7($29) /* save $4 */ + sw $5, 4*8($29) /* save $5 */ + sw $6, 4*9($29) /* save $6 */ + sw $7, 4*10($29) /* save $7 */ + sw $8, 4*11($29) /* save $8 */ + sw $9, 4*12($29) /* save $9 */ + sw $10, 4*13($29) /* save $10 */ + sw $11, 4*14($29) /* save $11 */ + sw $12, 4*15($29) /* save $12 */ + sw $13, 4*16($29) /* save $13 */ + sw $14, 4*17($29) /* save $14 */ + sw $15, 4*18($29) /* save $15 */ + sw $24, 4*19($29) /* save $24 */ + sw $25, 4*20($29) /* save $25 */ + sw $31, 4*21($29) /* save $31 */ + mfc0 $27, $14 + sw $27, 4*22($29) /* save EPC */ + + /* XICU PRIO register address computation */ + /* It depends on both the cluster_xy & local_id, */ + /* and we must use the physical address extension */ + mfc0 $10, $15, 1 /* $10 <= proc_id */ + andi $10, $10, 0x3FF /* at most 1024 processors */ + li $11, NB_PROCS_MAX + divu $10, $11 + mflo $12 /* $12 <= cluster_xy */ + mfhi $13 /* $13 <= local_id */ + la $14, seg_xcu_base /* $14 <= seg_xcu_base */ + + li $7, 0b011110000000 /* $7 <= PRIO offset */ + sll $8, $13, 2 /* $8 <= local_id*4 */ + addu $9, $7, $8 /* $9 <= PRIO offset + local_id*4 */ + addu $26, $9, $14 /* $26 <= seg_icu_base + PRIO offset + local_id*4 */ + + /* XCU[cluster_xy] access to get PRIO register value */ + mtc2 $12, $24 /* set PADDR extension */ + lw $15, ($26) /* $15 <= PRIO register value */ + mtc2 $0, $24 /* reset PADDR extension */ + + /* test PTI, then HWI, then WTI */ + andi $27, $15, 0x1 /* test bit T in PRIO register */ + bne $27, $0, _int_PTI /* branch to PTI handler */ + andi $27, $15, 0x2 /* test bit W in PRIO register */ + bne $27, $0, _int_HWI /* branch to HWI handler */ + andi $27, $15, 0x4 /* test bit W in PRIO register */ + bne $27, $0, _int_WTI /* branch to WTI handler */ + + /* exit interrupt handler: restore registers */ +_int_restore: + .set noat + lw $1, 4*4($29) + .set at + lw $2, 4*5($29) + lw $3, 4*6($29) + lw $4, 4*7($29) + lw $5, 4*8($29) + lw $6, 4*9($29) + lw $7, 4*10($29) + lw $8, 4*11($29) + lw $9, 4*12($29) + lw $10, 4*13($29) + lw $11, 4*14($29) + lw $12, 4*15($29) + lw $13, 4*16($29) + lw $14, 4*17($29) + lw $15, 4*18($29) + lw $24, 4*19($29) + lw $25, 4*20($29) + lw $31, 4*21($29) + lw $27, 4*22($29) /* get EPC */ + addiu $29, $29, 23*4 /* restore SP */ + mtc0 $27, $14 /* restore EPC */ + eret /* exit GIET */ + + /* The PTI handler get PTI index, */ + /* acknowledge the PTI register */ + /* and call the corresponding ISR */ +_int_PTI: + srl $26, $15, 6 /* $26 <= PRIO >> 6 */ + andi $26, $26, 0x7C /* $26 <= PTI_INDEX * 4 */ + addi $27, $14, 0x180 /* $27 <= &PTI_ACK[0] */ + add $27, $27, $26 /* $27 <= &PTI_ACK[PTI_INDEX] */ + lw $0, ($27) /* acknowledge XICU PTI */ + la $27, _interrupt_vector + addu $26, $26, $27 + lw $26, ($26) /* read ISR address */ + jalr $26 /* call ISR */ + nop + j _int_restore /* return from INT handler */ + nop + + /* The HWI handler get HWI index */ + /* and call the corresponding ISR */ +_int_HWI: + srl $26, $15, 14 /* $26 <= PRIO >> 14 */ + andi $26, $26, 0x7C /* $26 <= HWI_INDEX * 4 */ + la $27, _interrupt_vector + addu $26, $26, $27 /* $26 <= &ISR[HWI_INDEX */ + lw $26, ($26) /* read ISR address */ + jalr $26 /* call ISR */ + nop + j _int_restore /* return from INT handler */ + nop + + /* The WTI handler get WTI index, */ + /* acknowledge the WTI register */ + /* and call the corresponding ISR */ +_int_WTI: + srl $26, $15, 22 /* $26 <= PRIO >> 22 */ + andi $26, $26, 0x7C /* $26 <= WTI_INDEX * 4 */ + add $27, $14, $26 /* $27 <= &WTI_REG[WTI_INDEX] */ + lw $0, ($27) /* acknowledge XICU WTI */ + la $27, _interrupt_vector + addu $26, $26, $27 /* $26 <= &ISR[WTI_INDEX] */ + lw $26, ($26) /* read ISR address */ + jalr $26 /* call ISR */ + nop + j _int_restore /* return from INT handler */ + nop + +/* The default ISR is called when no specific ISR has been installed */ +/* in the interrupt vector. It simply displays a message on TTY0 */ + +isr_default: + addiu $29, $29, -20 /* get space in stack */ + sw $31, 16($29) /* to save the return address */ + la $4, _msg_default /* $4 <= string address */ + addi $5, $0, 36 /* $5 <= string length */ + li $6, 0 /* $6 <= TTY0 */ + jal _tty_write + lw $31, 16($29) /* restore return address */ + addiu $29, $29, 20 /* free space */ + jr $31 /* returns to interrupt handler */ + +/**************************************************************** +* Interrupt Vector Table (indexed by interrupt index) +* 32 words corresponding to 32 ISR addresses +****************************************************************/ +_interrupt_vector: + .word isr_default /* ISR 0 */ + .word isr_default /* ISR 1 */ + .word isr_default /* ISR 2 */ + .word isr_default /* ISR 3 */ + .word isr_default /* ISR 4 */ + .word isr_default /* ISR 5 */ + .word isr_default /* ISR 6 */ + .word isr_default /* ISR 7 */ + .word isr_default /* ISR 8 */ + .word isr_default /* ISR 9 */ + .word isr_default /* ISR 10 */ + .word isr_default /* ISR 11 */ + .word isr_default /* ISR 12 */ + .word isr_default /* ISR 13 */ + .word isr_default /* ISR 14 */ + .word isr_default /* ISR 15 */ + .word isr_default /* ISR 16 */ + .word isr_default /* ISR 17 */ + .word isr_default /* ISR 18 */ + .word isr_default /* ISR 19 */ + .word isr_default /* ISR 20 */ + .word isr_default /* ISR 21 */ + .word isr_default /* ISR 22 */ + .word isr_default /* ISR 23 */ + .word isr_default /* ISR 24 */ + .word isr_default /* ISR 25 */ + .word isr_default /* ISR 26 */ + .word isr_default /* ISR 27 */ + .word isr_default /* ISR 28 */ + .word isr_default /* ISR 29 */ + .word isr_default /* ISR 30 */ + .word isr_default /* ISR 31 */ + + .end _int_handler + +/**************************************************************** +* Exception Handler +* Same code for all fatal exceptions : +* Print the exception type and the values of EPC & BAR +* on the TTY correspondintg to the processor PROCID, +* and the user program is killed. +****************************************************************/ + .ent _exc_handler + +_exc_handler: +_cause_bp: +_cause_ukn: +_cause_ri: +_cause_ovf: +_cause_adel: +_cause_ades: +_cause_ibe: +_cause_dbe: +_cause_cpu: + mfc0 $26, $13 /* $26 <= CR */ + andi $26, $26, 0x3C /* $26 <= _cause_index * 4 */ + la $27, _mess_causes /* mess_cause table base address */ + addu $27, $26, $27 /* $26 <= message base address */ + + /* take the lock on TTY0 */ + li $4, 0 + jal _tty_get_lock + nop + + /* display exception type */ + lw $4, ($27) /* $4 <= message address */ + li $5, 36 /* $5 <= message length */ + li $6, 0 /* $6 <= TTY0 */ + jal _tty_write + nop + + /* display EPC value */ + la $4, _msg_epc /* $4 <= message address */ + li $5, 8 /* $5 <= message length */ + li $6, 0 /* $6 <= TTY0 */ + jal _tty_write + nop + + mfc0 $4, $14 /* $4 <= EPC value */ + la $5, _itoa_buffer /* $5 <= buffer address */ + addiu $5, $5, 2 /* skip 0x prefix */ + jal _itoa_hex /* fill buffer */ + nop + + la $4, _itoa_buffer /* $4 <= buffer address */ + li $5, 10 /* $5 <= buffer length */ + li $6, 0 /* $6 <= TTY0 */ + jal _tty_write + nop + + /* display BAR value */ + la $4, _msg_bar /* $4 <= message address */ + li $5, 8 /* $5 <= message length */ + li $6, 0 /* $6 <= TTY0 */ + jal _tty_write + nop + + mfc0 $4, $8 /* $4 <= BAR value */ + la $5, _itoa_buffer /* $5 <= buffer address */ + addiu $5, $5, 2 /* skip 0x prefix */ + jal _itoa_hex /* fill buffer */ + nop + + la $4, _itoa_buffer /* $4 <= message address */ + li $5, 10 /* $5 <= message length */ + li $6, 0 /* $6 <= TTY0 */ + jal _tty_write + nop + + + /* release the lock on TTY0 */ + li $4, 0 + jal _tty_get_lock + nop + + j _exit /* kill user program */ + +/* Exceptions Messages table (indexed by XCODE) */ +_mess_causes: + .word _msg_ukncause + .word _msg_ukncause + .word _msg_ukncause + .word _msg_ukncause + .word _msg_adel + .word _msg_ades + .word _msg_ibe + .word _msg_dbe + .word _msg_ukncause + .word _msg_bp + .word _msg_ri + .word _msg_cpu + .word _msg_ovf + .word _msg_ukncause + .word _msg_ukncause + .word _msg_ukncause + +/******************************************************************** +* All messages +* Messages length are fixed : 8 or 36 characters... +********************************************************************/ +_msg_bar: .asciiz "\nBAR = " +_msg_epc: .asciiz "\nEPC = " +_msg_default: .asciiz "\n\n !!! Default ISR !!! \n" +_msg_uknsyscall: .asciiz "\n\n !!! Undefined System Call !!! \n" +_msg_ukncause: .asciiz "\n\nException : strange unknown cause\n" +_msg_adel: .asciiz "\n\nException : illegal read address \n" +_msg_ades: .asciiz "\n\nException : illegal write address\n" +_msg_ibe: .asciiz "\n\nException : inst bus error \n" +_msg_dbe: .asciiz "\n\nException : data bus error \n" +_msg_bp: .asciiz "\n\nException : breakpoint \n" +_msg_ri: .asciiz "\n\nException : reserved instruction \n" +_msg_ovf: .asciiz "\n\nException : arithmetic overflow \n" +_msg_cpu: .asciiz "\n\nException : illegal coproc access\n" + + .end _exc_handler + + Index: /branches/fault_tolerance/softs/giet_tsar/mips32_registers.h =================================================================== --- /branches/fault_tolerance/softs/giet_tsar/mips32_registers.h (revision 724) +++ /branches/fault_tolerance/softs/giet_tsar/mips32_registers.h (revision 724) @@ -0,0 +1,91 @@ +/********************************************************************************/ +/* File : mips32_registers.h */ +/* Author : Alain Greiner */ +/* Date : 26/03/2012 */ +/********************************************************************************/ +/* We define mnemonics for MIPS32 registers */ +/********************************************************************************/ + +#ifndef _MIPS32_REGISTER_H +#define _MIPS32_REGISTER_H + +/* processor registers */ + +#define zero $0 +#define at $1 +#define v0 $2 +#define v1 $3 +#define a0 $4 +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define s0 $16 +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 +#define t9 $25 +#define k0 $26 +#define k1 $27 +#define gp $28 +#define sp $29 +#define fp $30 +#define ra $31 + +/* CP0 registers */ + +#define CP0_BVAR $8 +#define CP0_TIME $9 +#define CP0_SR $12 +#define CP0_CR $13 +#define CP0_EPC $14 +#define CP0_PROCID $15,1 +#define CP0_EBASE $15,1 +#define CP0_SCHED $4,2 + +/* CP2 registers */ + +#define CP2_PTPR $0 +#define CP2_MODE $1 +#define CP2_ICACHE_FLUSH $2 +#define CP2_DCACHE_FLUSH $3 +#define CP2_ITLB_INVAL $4 +#define CP2_DTLB_INVAL $5 +#define CP2_ICACHE_INVAL $6 +#define CP2_DCACHE_INVAL $7 +#define CP2_ICACHE_PREFETCH $8 +#define CP2_DCACHE_PREFETCH $9 +#define CP2_SYNC $10 +#define CP2_IETR $11 +#define CP2_DETR $12 +#define CP2_IBVAR $13 +#define CP2_DBVAR $14 +#define CP2_PARAMS $15 +#define CP2_RELEASE $16 +#define CP2_DATA_LO $17 +#define CP2_DATA_HI $18 +#define CP2_ICACHE_INVAL_PA $19 +#define CP2_DCACHE_INVAL_PA $20 +#define CP2_PADDR_EXT $24 +#endif + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: +// vim: filetype=c:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: /branches/fault_tolerance/softs/giet_tsar/reset.S =================================================================== --- /branches/fault_tolerance/softs/giet_tsar/reset.S (revision 724) +++ /branches/fault_tolerance/softs/giet_tsar/reset.S (revision 724) @@ -0,0 +1,152 @@ +/******************************************************************************** +* File : reset.S +* Author : Alain Greiner +* Date : 15/01/2014 +********************************************************************************* +* This is a boot code for a generic multi-clusters / multi-processors +* TSAR architecture (up to 256 clusters / up to 4 processors per cluster). +* The physical address is 40 bits, and the 8 MSB bits A[39:32] define the +* cluster index. +* +* As we don't want to use the virtual memory, the physical address is +* equal to the virtual address (identity mapping) and all processors stacks +* and code segments are allocated in the physical memory bank in cluster 0. +* +* Both the reset base address and the kernel base address must be redefined +* to use a physical memory bank smaller than 2 Gbytes. +* +* There is one XCU iand one MMC per cluster. +* +* There is one IOPIC component in cluster_io. +* +* There is two sets of peripherals: +* +* 1) A block device and a single channel TTY controller are available +* in cluster(0,0). +* +* 2) Other peripherals (including another Blockdevice, a multi-channels TTY +* contrÃŽler, a Frame buffer) are located in cluster_io. +* For those externals peripherals, hardware interrupts (HWI) are translated +* to software interrupts (WTI) by and IOPIC component, that is programmed +* to route all SWI to to processor 0 in cluster (0,0). +* +* The boot sequence is the following: +* - Each processor initializes the stack pointer ($29) depending on proc_id. +* - Each processor initializes the CP0 EBASE register +* - Only processor 0 initializes the Interrupt vector. +* - Only processor 0 initializes the IOPIC component. +* - Each processor initializes its private XCU mask. +* - Each processor initializes the Status Register (SR) +* - Each processor jumps to the same main address in kernel mode... +********************************************************************************/ + +#include "hard_config.h" +#include "mips32_registers.h" + + .section .reset,"ax",@progbits + + .extern seg_stack_base + .extern seg_xcu_base + .extern seg_pic_base + .extern seg_kcode_base + .extern _interrupt_vector + .extern _ioc_isr + .extern _mmc_isr + .extern _tty_isr + .extern main + + .globl reset + .ent reset + .align 2 + +reset: + .set noreorder + +/* each proc computes proc_id, lpid, cluster_xy */ + mfc0 $26, CP0_PROCID + andi $26, $26, 0x3FF /* at most 1024 processors */ + move $10, $26 /* $10 <= proc_id */ + li $27, NB_PROCS_MAX + divu $26, $27 + mfhi $11 /* $11 <= lpid */ + mflo $12 /* $12 <= cluster_xy */ + +/* each proc initializes stack pointer (64K per processor) */ + la $27, seg_stack_base + addi $26, $10, 1 /* $26 <= (proc_id + 1) */ + sll $26, $26, 14 /* $26 <= (proc_id + 1) * 16K */ + addu $29, $27, $26 /* $29 <= seg_stack_base(proc_id) */ + +/* each proc initializes CP0 EBASE register */ + la $26, seg_kcode_base + mtc0 $26, CP0_EBASE /* CP0_EBASE <= seg_kcode_base */ + +/* only proc (0,0,0) initializes interrupt vector for IOC, TTY, MMC */ + bne $10, $0, reset_xcu + nop + + la $26, _interrupt_vector /* interrupt vector address */ + la $27, _mmc_isr + sw $27, 32($26) /* interrupt_vector[8] <= _mmc_isr */ + la $27, _ioc_isr + sw $27, 36($26) /* interrupt_vector[9] <= _ioc_isr */ + la $27, _tty_isr + sw $27, 40($26) /* interrupt_vector[10] <= _tty_isr */ + +/* only proc (0,0,0) initializes IOPIC : IOPIC_ADDRESS[i] <= &XICU[0].WTI_REG[i] */ + + li $26, USE_EXT_IO + beq $26, $0, reset_xcu /* IOPIC not initialised if not USE_EXT_IO */ + + li $20, X_SIZE + addi $20, $20, -1 + sll $20, $20, 4 + li $21, Y_SIZE + add $22, $20, $21 /* $22 <= cluster(X_SIZE-1, Y_SIZE) */ + + mtc2 $22, CP2_PADDR_EXT /* CP2_PADDR_EXT <= cluster_io */ + + li $24, 16 /* $24 iteration (de)counter */ + la $27, seg_xcu_base /* $27 <= &(XICU[0].WTI_REG[0]) */ + la $26, seg_pic_base /* $26 <= &IOPIC_ADDRESS[0] */ + +reset_loop: + sw $27, 0($26) /* IOPIC_ADDRESS[i] <= &XICU[0].WTI_REG[i] */ + addi $24, $24, -1 /* decrement iteration index */ + addi $27, $27, 4 /* $27 <= &(XICU[0].WTI_REG[i++] */ + addi $26, $26, 16 /* $26 <= &IOPIC_ADDRESS[i++] */ + bne $24, $0, reset_loop + nop + + mtc2 $0, CP2_PADDR_EXT /* CP2_PADDR_EXT <= zero */ + +reset_xcu: + +/* only proc (x,y,0) receive IRQs and initialise HWI and WTI XICU masks */ + bne $11, $0, reset_end + nop + la $26, seg_xcu_base + li $27, 0b010010000000 /* offset for MSK_HWI_ENABLE[lpid == 0] */ + addu $24, $26, $27 /* $24 <= &HWI_MASK */ + li $25, 0x0700 /* TTY:HWI[10] IOC:HWI[9] MEMC:HWI[8] */ + sw $25, 0($24) /* set HWI mask */ + + li $27, 0b011010000000 /* offset for MSK_WTI_ENABLE[lpid == 0] */ + addu $24, $26, $27 /* $24 <= $WTI_MASK */ + li $25, 0xFFFFFFFF /* all WTI enabled */ + sw $25, 0($24) /* set WTI mask */ + +reset_end: + +/* initializes SR register */ + li $26, 0x0000FF01 + mtc0 $26, $12 /* SR <= kernel mode / IRQ enable */ + +/* jumps to main in kernel mode */ + la $26, main + jr $26 + nop + + .end reset + + .set reorder Index: /branches/fault_tolerance/softs/giet_tsar/stdio.c =================================================================== --- /branches/fault_tolerance/softs/giet_tsar/stdio.c (revision 724) +++ /branches/fault_tolerance/softs/giet_tsar/stdio.c (revision 724) @@ -0,0 +1,1346 @@ +//////////////////////////////////////////////////////////////////////////////////////// +// File : stdio.c +// Written by Alain Greiner +// Date : janvier 2014 +// +// This file defines various functions that can be used by applications to access +// peripherals, for the TSAR multi-processors multi_clusters architecture. +// There is NO separation between application code and system code, as the +// application are running in kernel mode without system calls. +// This basic GIET does not support virtual memory, and does not support multi-tasking. +// +// The supported peripherals are: +// - the SoClib multi_tty +// - The SoCLib frame_buffer +// - The SoCLib block_device +// +// The following parameters must be defined in the hard_config.h file. +// - X_SIZE : number of clusters in a row +// - Y_SIZE : number of clusters in a column +// - X_WIDTH : number of bits for X field in proc_id +// - Y_WIDTH : number of bits for Y field in proc_id +// - NB_PROCS_MAX : max number of processor per cluster +// - NB_TTY_CHANNELS : max number of TTY channels +// - USE_EXT_IO : use external peripherals if not zero +// +// The follobing base addresses must be defined in the ldscript +// - seg_tty_base +// - seg_fbf_base +// - seg_ioc_base +//////////////////////////////////////////////////////////////////////////////////////// + +#include "stdio.h" + +#if !defined(NB_PROCS_MAX) +#error: you must define NB_PROCS_MAX in the hard_config.h file +#endif + +#if !defined(USE_EXT_IO) +#error: you must define USE_EXT_IO in the hard_config.h file +#endif + +#if !defined(X_SIZE) +#error: you must define X_SIZE in the hard_config.h file +#endif + +#if !defined(Y_SIZE) +#error: you must define Y_SIZE in the hard_config.h file +#endif + +#if !defined(X_WIDTH) +#error: you must define X_WIDTH in the hard_config.h file +#endif + +#if (X_WIDTH != 4) +#error: The X_WIDTH parameter must be equal to 4 +#endif + +#if !defined(Y_WIDTH) +#error: you must define X_WIDTH in the hard_config.h file +#endif + +#if (X_WIDTH != 4) +#error: The Y_WIDTH parameter must be equal to 4 +#endif + +#if !defined(NB_TTY_CHANNELS) +#error: you must define NB_TTY_CHANNELS in the hard_config.h file +#endif + + + + +#define NB_LOCKS 256 +#define NB_BARRIERS 16 + +#define in_drivers __attribute__((section (".drivers"))) +#define in_unckdata __attribute__((section (".unckdata"))) + +////////////////////////////////////////////////////////////// +// various informations that must be defined in ldscript +////////////////////////////////////////////////////////////// + +struct plouf; + +extern struct plouf seg_tty_base; +extern struct plouf seg_fbf_base; +extern struct plouf seg_ioc_base; +extern struct plouf seg_mmc_base; +extern struct plouf seg_ramdisk_base; + +//////////////////////////////////////////////////////////////////////////////////////// +// Global uncachable variables for synchronization between drivers and ISRs +//////////////////////////////////////////////////////////////////////////////////////// + +in_unckdata int volatile _ioc_lock = 0; +in_unckdata int volatile _ioc_done = 0; +in_unckdata int volatile _ioc_status; + +in_unckdata char volatile _tty_get_buf[NB_TTY_CHANNELS]; +in_unckdata int volatile _tty_get_full[NB_TTY_CHANNELS] = { [0 ... NB_TTY_CHANNELS-1] = 0 }; + +//////////////////////////////////////////////////////////////////////////////////////// +// Global uncachable variables for inter-task barriers +//////////////////////////////////////////////////////////////////////////////////////// + +in_unckdata int volatile _barrier_value[NB_BARRIERS] = { [0 ... NB_BARRIERS-1] = 0 }; +in_unckdata int volatile _barrier_count[NB_BARRIERS] = { [0 ... NB_BARRIERS-1] = 0 }; +in_unckdata int volatile _barrier_lock[NB_BARRIERS] = { [0 ... NB_BARRIERS-1] = 0 }; + +//////////////////////////////////////////////////////////////////////////////////////// +// Global uncachable variables for spin_locks using LL/C instructions +//////////////////////////////////////////////////////////////////////////////////////// + +in_unckdata int volatile _spin_lock[NB_LOCKS] = { [0 ... NB_LOCKS-1] = 0 }; + +//////////////////////////////////////////////////////////////////////////////////////// +// Memcopy taken from MutekH. +//////////////////////////////////////////////////////////////////////////////////////// +in_drivers void* _memcpy( void* _dst, + const void* _src, + unsigned int size ) +{ + unsigned int *dst = _dst; + const unsigned int *src = _src; + if ( ! ((unsigned int)dst & 3) && ! ((unsigned int)src & 3) ) + { + while (size > 3) + { + *dst++ = *src++; + size -= 4; + } + } + + unsigned char *cdst = (unsigned char*)dst; + unsigned char *csrc = (unsigned char*)src; + + while (size--) + { + *cdst++ = *csrc++; + } + return _dst; +} +//////////////////////////////////////////////////////////////////////////////////////// +// Memcopy using extended addresses +//////////////////////////////////////////////////////////////////////////////////////// +in_drivers void _extended_memcpy( unsigned int dst_cluster, + unsigned int dst_address, + unsigned int src_cluster, + unsigned int src_address, + unsigned int length ) +{ + if ( (dst_address & 0x3) || (src_address & 0x3) || (length & 0x3) ) + { + _tty_get_lock( 0 ); + _tty_puts( "ERROR in _extended_memcpy()" ); + _tty_release_lock( 0 ); + _exit(); + } + + unsigned int i; + unsigned int word; + + for ( i = 0 ; i < length ; i = i+4 ) + { + word = _word_extended_read( src_cluster, (src_address + i) ); + _word_extended_write( dst_cluster, (dst_address + i), word ); + } +} +//////////////////////////////////////////////////////////////////////////////////////// +// Access CP0 and returns processor ident +// No more than 1024 processors... +//////////////////////////////////////////////////////////////////////////////////////// +in_drivers unsigned int _procid() +{ + unsigned int ret; + asm volatile( "mfc0 %0, $15, 1": "=r"(ret) ); + return (ret & 0x3FF); +} +//////////////////////////////////////////////////////////////////////////////////////// +// Access CP0 and returns processor time +//////////////////////////////////////////////////////////////////////////////////////// +in_drivers unsigned int _proctime() +{ + unsigned int ret; + asm volatile( "mfc0 %0, $9": "=r"(ret) ); + return ret; +} +//////////////////////////////////////////////////////////////////////////////////////// +// Returns the number of processsors controled by the GIET +//////////////////////////////////////////////////////////////////////////////////////// +in_drivers unsigned int _procnumber() +{ + return (unsigned int)(NB_PROCS_MAX * X_SIZE * Y_SIZE); +} +//////////////////////////////////////////////////////////////////////////////////////// +// Returns pseudo-random number +//////////////////////////////////////////////////////////////////////////////////////// +in_drivers unsigned int _rand() +{ + unsigned int x = _proctime(); + if((x & 0xF) > 7) + return (x*x & 0xFFFF); + else + return (x*x*x & 0xFFFF); +} +//////////////////////////////////////////////////////////////////////////////////////// +// Access CP0 and mask IRQs +//////////////////////////////////////////////////////////////////////////////////////// +in_drivers void _it_mask() +{ + int tmp; + asm volatile("mfc0 %0, $12" : "=r" (tmp) ); + asm volatile("ori %0, %0, 1" : "=r" (tmp) ); + asm volatile("mtc0 %0, $12" : "=r" (tmp) ); +} +//////////////////////////////////////////////////////////////////////////////////////// +// Access CP0 and enable IRQs +//////////////////////////////////////////////////////////////////////////////////////// +in_drivers void _it_enable() +{ + int tmp; + asm volatile("mfc0 %0, $12" : "=r" (tmp) ); + asm volatile("addi %0, %0, -1" : "=r" (tmp) ); + asm volatile("mtc0 %0, $12" : "=r" (tmp) ); +} +////////////////////////////////////////////////////////////////////// +// Invalidate all cache lines corresponding to a memory buffer. +// This is used by the block_device driver. +///////////////////////////////////////////////////////////////////////// +in_drivers void _dcache_buf_invalidate(const void * buffer, size_t size) +{ + size_t i; + size_t dcache_line_size; + + // retrieve dcache line size from config register (bits 12:10) + asm volatile("mfc0 %0, $16, 1" : "=r" (dcache_line_size)); + + dcache_line_size = 2 << ((dcache_line_size>>10) & 0x7); + + // iterate on lines to invalidate each one of them + for ( i=0; i> Y_WIDTH; + unsigned int y = (proc_id / NB_PROCS_MAX) & ((1<> 4; + } + _tty_puts( buf ); +} + +/////////////////////////////////////////////////////////////////////////////// +// This function displays a 32 bits unsigned int as a decimal string on TTY0. +/////////////////////////////////////////////////////////////////////////////// +in_drivers void _tty_putd( unsigned int val ) +{ + static const char DecTab[] = "0123456789"; + char buf[11]; + unsigned int i; + unsigned int first; + + buf[10] = 0; + + for (i = 0; i < 10; i++) + { + if ((val != 0) || (i == 0)) + { + buf[9 - i] = DecTab[val % 10]; + first = 9 - i; + } + else + { + break; + } + val /= 10; + } + _tty_puts( &buf[first] ); +} + +////////////////////////////////////////////////////////////////////////////// +// This function try to take the hardwired lock protecting exclusive access +// to TTY terminal identified by the channel argument. +// It returns only when the lock has been successfully taken. +////////////////////////////////////////////////////////////////////////////// +in_drivers void _tty_get_lock( unsigned int channel ) +{ + if ( USE_EXT_IO ) // extended addressing to cluster_io + { + unsigned int cluster_io = ((X_SIZE-1)<> Y_WIDTH; + y = (proc_id / NB_PROCS_MAX) & ((1<= NB_TTY_CHANNELS ) + { + _tty_get_lock( 0 ); + _tty_puts( "ERROR in _tty_getc(): TTY index too large\n" ); + _tty_release_lock( 0 ); + _exit(); + } + + while( _tty_read( buf, channel ) == 0 ) asm volatile("nop"); +} + +////////////////////////////////////////////////////////////////////////////// +// Fetch a string of decimal characters (most significant digit first) +// to build a 32 bits unsigned int. +// The terminal index is implicitely defined by the processor ID. +// This is a blocking function. +// The decimal characters are written in a 32 characters buffer +// until a or character is read. +// The character is interpreted, and previous characters can be +// cancelled. All others characters are ignored. +// When the or character is received, the string is converted +// to an unsigned int value. If the number of decimal digit is too large +// for the 32 bits range, the zero value is returned. +////////////////////////////////////////////////////////////////////////////// +in_drivers void _tty_getw( unsigned int* word_buffer ) +{ + char buf[32]; + char byte; + char cancel_string[3] = { 0x08, 0x20, 0x08 }; + char zero = 0x30; + unsigned int save = 0; + unsigned int val = 0; + unsigned int done = 0; + unsigned int overflow = 0; + unsigned int max = 0; + unsigned int proc_id = _procid(); + unsigned int i; + unsigned int channel; + unsigned int x; + unsigned int y; + unsigned int l; + + // check TTY channel + l = (proc_id % NB_PROCS_MAX); + x = (proc_id / NB_PROCS_MAX) >> Y_WIDTH; + y = (proc_id / NB_PROCS_MAX) & ((1<= NB_TTY_CHANNELS ) + { + _tty_get_lock( 0 ); + _tty_puts( "ERROR in _tty_getw(): TTY index too large\n" ); + _tty_release_lock( 0 ); + _exit(); + } + + while( done == 0 ) + { + _tty_read( &byte, channel ); + + if (( byte > 0x2F) && (byte < 0x3A)) // decimal character + { + buf[max] = byte; + max++; + _tty_write( &byte, 1, channel ); + } + else if ( (byte == 0x0A) || (byte == 0x0D) ) // LF or CR character + { + done = 1; + } + else if ( byte == 0x7F ) // DEL character + { + if (max > 0) + { + max--; // cancel the character + _tty_write( cancel_string, 3, channel ); + } + } + } // end while + + // string conversion + for( i=0 ; i> Y_WIDTH; + y = (proc_id / NB_PROCS_MAX) & ((1<= NB_LOCKS ) + { + _tty_get_lock( 0 ); + _tty_puts( "ERROR in _release_lock()" ); + _tty_release_lock( 0 ); + _exit(); + } + + _spin_lock[index] = 0; +} + +/////////////////////////////////////////////////////////////////////////////////////// +// Try to take a software spin-lock. +// This is a blocking call, as there is a busy-waiting loop, +// until the lock is granted to the requester. +// There is an internal delay of about 100 cycles between +// two successive lock read, to avoid bus saturation. +/////////////////////////////////////////////////////////////////////////////////////// +in_drivers void _get_lock(size_t index) +{ + if( index >= NB_LOCKS ) + { + _tty_get_lock( 0 ); + _tty_puts( "ERROR in _get_lock()" ); + _tty_release_lock( 0 ); + _exit(); + } + + register int delay = ((_proctime() +_procid()) & 0xF) << 4; + register int * plock = (int *) &_spin_lock[index]; + + asm volatile ("_locks_llsc: \n" + "ll $2, 0(%0) \n" // $2 <= _locks_lock + "bnez $2, _locks_delay \n" // random delay if busy + "li $3, 1 \n" // prepare argument for sc + "sc $3, 0(%0) \n" // try to set _locks_busy + "bnez $3, _locks_ok \n" // exit if atomic + "_locks_delay: \n" + "move $4, %1 \n" // $4 <= delay + "_locks_loop: \n" + "addi $4, $4, -1 \n" // $4 <= $4 - 1 + "beqz $4, _locks_loop \n" // test end delay + "j _locks_llsc \n" // retry + "_locks_ok: \n" + ::"r"(plock),"r"(delay):"$2","$3","$4"); +} + + +////////////////////////////////////////////////////////////////////////////////////// +// This function makes a cooperative initialisation of the barrier: +// - barrier_count[index] <= N +// - barrier_lock[index] <= 0 +// All tasks try to initialize the barrier, but the initialisation +// is done by only one task, using LL/SC instructions. +// This cooperative initialisation is questionnable, +// because the barrier can ony be initialised once... +////////////////////////////////////////////////////////////////////////////////////// +in_drivers void _barrier_init(unsigned int index, unsigned int value) +{ + + register int* pinit = (int*)&_barrier_value[index]; + register int* pcount = (int*)&_barrier_count[index]; + register int* plock = (int*)&_barrier_lock[index]; + + if ( index >= NB_BARRIERS ) + { + _tty_get_lock( 0 ); + _tty_puts( "ERROR in _barrier_init()" ); + _tty_release_lock( 0 ); + _exit(); + } + + // parallel initialisation using atomic instructions LL/SC + asm volatile ("_barrier_init_test: \n" + "ll $2, 0(%0) \n" // read barrier_value + "bnez $2, _barrier_init_done \n" + "move $3, %3 \n" + "sc $3, 0(%0) \n" // try to write barrier_value + "beqz $3, _barrier_init_test \n" + "move $3, %3 \n" + "sw $3, 0(%1) \n" // barrier_count <= barrier_value + "move $3, $0 \n" // + "sw $3, 0(%2) \n" // barrier_lock <= 0 + "_barrier_init_done: \n" + ::"r"(pinit),"r"(pcount),"r"(plock),"r"(value):"$2","$3"); +} + +////////////////////////////////////////////////////////////////////////////////////// +// This blocking function uses a busy_wait technics (on the barrier_lock value), +// because the GIET does not support dynamic scheduling/descheduling of tasks. +// The barrier state is actually defined by two variables: +// _barrier_count[index] define the number of particpants that are waiting +// _barrier_lock[index] define the bool variable whose value is polled +// The last participant change the value of _barrier_lock[index] to release the barrier... +// There is at most 16 independant barriers, and an error is returned +// if the barrier index is larger than 15. +////////////////////////////////////////////////////////////////////////////////////// +in_drivers void _barrier_wait(unsigned int index) +{ + register int* pcount = (int*)&_barrier_count[index]; + register int count; + + int lock = _barrier_lock[index]; + + if ( index >= NB_BARRIERS ) + { + _tty_get_lock( 0 ); + _tty_puts( "ERROR in _barrier_wait()" ); + _tty_release_lock( 0 ); + _exit(); + } + + // parallel decrement _barrier_count[index] using atomic instructions LL/SC + // input : pointer on _barrier_count[index] + // output : count = _barrier_count[index] (before decrementation) + asm volatile ("_barrier_decrement: \n" + "ll %0, 0(%1) \n" + "addi $3, %0, -1 \n" + "sc $3, 0(%1) \n" + "beqz $3, _barrier_decrement \n" + :"=&r"(count) + :"r"(pcount) + :"$2","$3"); + + // the last task re-initializes the barrier_ count variable + // and the barrier_lock variable, waking up all other waiting tasks + + if ( count == 1 ) // last task + { + _barrier_count[index] = _barrier_value[index]; + asm volatile( "sync" ); + _barrier_lock[index] = (lock == 0) ? 1 : 0; + } + else // other tasks + { + while ( lock == _barrier_lock[index] ) asm volatile("nop"); + } +} + + +// Local Variables: +// tab-width: 4; +// c-basic-offset: 4; +// c-file-offsets:((innamespace . 0)(inline-open . 0)); +// indent-tabs-mode: nil; +// End: +// +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: /branches/fault_tolerance/softs/giet_tsar/stdio.h =================================================================== --- /branches/fault_tolerance/softs/giet_tsar/stdio.h (revision 724) +++ /branches/fault_tolerance/softs/giet_tsar/stdio.h (revision 724) @@ -0,0 +1,137 @@ +//////////////////////////////////////////////////////////////////////////////////////// +// File : stdio.h +// Written by Alain Greiner +// Date : 17/01/2014 +// +// This file define varions functions that can be used by applications to access +// peripherals, or other ressources such as processor registers, spin_locks +// or synchronisation barriers. +// It is dedicated for the TSAR multi-processors multi_clusters architecture. +// There is NO separation between application code and system code. +// This basic GIET does not use the virtual memory, and does nort support multi-tasking. +// +//The supported peripherals are: +//- the SoClib multi_tty +//- The SoCLib frame_buffer +//- The SoCLib block_device +// +//The following parameters must be defined in the hard_config.h file. +//- X_SIZE : number of clusters in a row +//- Y_SIZE : number of clusters in a column +//- X_WIDTH : number of bits for X field in proc_id +//- Y_WIDTH : number of bits for Y field in proc_id +//- NB_PROCS_MAX : max number of processor per cluster +//- NB_TTY_CHANNELS : max number of TTY channels +// +//The follobing base addresses must be defined in the ldscript +//- seg_tty_base +//- seg_fbf_base +//- seg_ioc_base +//////////////////////////////////////////////////////////////////////////////////////// + +#ifndef _GIET_STDIO_H_ +#define _GIET_STDIO_H_ + +#include "tty.h" +#include "block_device.h" +#include "hard_config.h" +#include + +typedef unsigned int size_t; + +// global variables defined in stdio.c + +extern int volatile _ioc_lock; +extern int volatile _ioc_done; +extern int volatile _ioc_status; + +extern char volatile _tty_get_buf[]; +extern int volatile _tty_get_full[]; + +extern int volatile _barrier_value[]; +extern int volatile _barrier_count[]; +extern int volatile _barrier_lock[]; + +extern int volatile _spin_lock[]; + +// functions defined in stdio.c + +void* _memcpy( void* dst, const void* src, size_t size ); + +void _extended_memcpy( unsigned int dst_cluster, + unsigned int dst_address, + unsigned int src_cluster, + unsigned int src_address, + unsigned int length ); +unsigned int _procid(); +unsigned int _proctime(); +unsigned int _procnumber(); + +unsigned int _rand(); + +void _it_mask(); +void _it_enable(); + +void _dcache_buf_invalidate( const void* buffer, size_t size ); + +void _exit(); + +void _itoa_dec( unsigned int val, char* buf ); +void _itoa_hex( unsigned int val, char* buf ); + +int _tty_write( char* buffer, size_t length, size_t channel ); +int _tty_read( char* buffer, size_t channel ); +void _tty_puts( char* string ); +void _tty_putd( unsigned int val ); +void _tty_putx( unsigned int val ); +void _tty_get_lock( size_t channel ); +void _tty_release_lock( size_t channel ); +void _tty_getc( char* buffer ); +void _tty_getw( unsigned int* buffer ); +void _tty_printf( char* format, ... ); +void _tty_isr(); + +void _ioc_get_lock(); +void _ioc_write( size_t lba, void* buffer, size_t count, size_t ext ); +void _ioc_read (size_t lba, void* buffer, size_t count, size_t ext ); +void _ioc_completed(); +void _ioc_isr(); + +void _mmc_isr(); + +void _fb_sync_write( unsigned int offset, + unsigned int buffer, + unsigned int length, + unsigned int ext ); +void _fb_sync_read( unsigned int offset, + unsigned int buffer, + unsigned int length, + unsigned int ext ); + +void _release_lock( size_t lock_index ); +void _get_lock( size_t lock_index ); + +void _barrier_init(size_t index, size_t count); +void _barrier_wait(size_t index); + +unsigned char _byte_extended_read( unsigned int cluster, + unsigned int address ); +unsigned int _word_extended_read( unsigned int cluster, + unsigned int address ); +void _word_extended_write( unsigned int cluster, + unsigned int address, + unsigned int word ); +void _byte_extended_write( unsigned int cluster, + unsigned int address, + unsigned char byte ); +#endif + +// Local Variables: +// tab-width: 4; +// c-basic-offset: 4; +// c-file-offsets:((innamespace . 0)(inline-open . 0)); +// indent-tabs-mode: nil; +// End: +// +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: /branches/fault_tolerance/softs/giet_tsar/tty.h =================================================================== --- /branches/fault_tolerance/softs/giet_tsar/tty.h (revision 724) +++ /branches/fault_tolerance/softs/giet_tsar/tty.h (revision 724) @@ -0,0 +1,23 @@ +#ifndef TTY_REGS_H +#define TTY_REGS_H + +enum SoclibTtyRegisters { + TTY_WRITE = 0, + TTY_STATUS = 1, + TTY_READ = 2, + TTY_CONFIG = 3, + /**/ + TTY_SPAN = 4, +}; + +#endif + +// Local Variables: +// tab-width: 4; +// c-basic-offset: 4; +// c-file-offsets:((innamespace . 0)(inline-open . 0)); +// indent-tabs-mode: nil; +// End: +// +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: /branches/fault_tolerance/softs/soft_filter_giet/Makefile =================================================================== --- /branches/fault_tolerance/softs/soft_filter_giet/Makefile (revision 724) +++ /branches/fault_tolerance/softs/soft_filter_giet/Makefile (revision 724) @@ -0,0 +1,47 @@ + +LD = mipsel-unknown-elf-ld +CC = mipsel-unknown-elf-gcc +AS = mipsel-unknown-elf-as +DU = mipsel-unknown-elf-objdump + +OBJS = reset.o \ + giet.o \ + isr.o \ + drivers.o \ + stdio.o \ + main.o + +CFLAGS = -Wall -g -mno-gpopt -ffreestanding -fomit-frame-pointer -mips32 -ggdb + +GIET = ../giet_tsar + +bin.soft: $(OBJS) ldscript + $(LD) -o $@ -T ldscript $(OBJS) + $(DU) -D $@ > $@.txt + +reset.o: $(GIET)/reset.s + $(AS) -g -mips32 -o $@ $< + $(DU) -D $@ > $@.txt + +giet.o: $(GIET)/giet.s + $(AS) -g -mips32 -o $@ $< + $(DU) -D $@ > $@.txt + +isr.o: $(GIET)/isr.c + $(CC) $(CFLAGS) -c -o $@ $< + $(DU) -D $@ > $@.txt + +stdio.o: $(GIET)/stdio.c + $(CC) $(CFLAGS) -c -o $@ $< + $(DU) -D $@ > $@.txt + +drivers.o: $(GIET)/drivers.c + $(CC) $(CFLAGS) -c -o $@ $< + $(DU) -D $@ > $@.txt + +main.o: main.c + $(CC) $(CFLAGS) -I$(GIET) -c -o $@ $< + $(DU) -D $@ > $@.txt + +clean: + rm -f *.o bin.soft *.txt core *~ proc* term* temp Index: /branches/fault_tolerance/softs/soft_filter_giet/ldscript =================================================================== --- /branches/fault_tolerance/softs/soft_filter_giet/ldscript (revision 724) +++ /branches/fault_tolerance/softs/soft_filter_giet/ldscript (revision 724) @@ -0,0 +1,90 @@ +/********************************************************** + File : ldscript + Author : Alain Greiner + Date : March 2011 +**********************************************************/ + +/* definition of various hardware parameters. +These variables are referenced in the drivers.c file, +and must be defined, even if the corresponding +peripherals are not present in the architecture */ + +NB_CLUSTERS = 4; /* number of clusters */ +NB_PROCS = 4; /* number of processors per cluster */ +NB_TASKS = 1; /* number of tasks per processor */ +NB_TIMERS = 1; /* max number of timers per processor */ +NB_LOCKS = 8; /* number of spin_locks */ + +/* definition of the base address for all segments +The peripherals base addresses are referenced by the +software drivers and must be defined, even if the +peripherals are not present in the architecture */ + +seg_code_base = 0x00000000; /* le code utilisateur */ +seg_data_base = 0x00100000; /* les données utilisateur */ + +seg_heap_base = 0x00300000; /* le tas utilisateur */ +seg_stack_base = 0x00800000; /* la pile utilisateur */ + +seg_kcode_base = 0x80000000; /* le code du système */ +seg_kdata_base = 0x80100000; /* les donnees du système */ +seg_kunc_base = 0x80200000; /* les données non cachées du système */ + +seg_icu_base = 0x00F00000; /* controleur ICU */ +seg_tty_base = 0xBFF20000; /* controleur TTY */ +seg_dma_base = 0x00F30000; /* controleur DMA */ + +seg_reset_base = 0xBFC00000; /* le code de boot */ +seg_fb_base = 0xBFD00000; /* controleur FRAME BUFFER */ +seg_ioc_base = 0xBFF10000; /* controleur I/O */ + +seg_timer_base = 0x00F0000; /* controleur TIMER */ +seg_gcd_base = 0xBFF50000; /* controleur GCD */ + +/* Grouping sections into segments */ + +SECTIONS +{ + . = seg_kcode_base; + seg_kcode : { + *(.giet) + *(.switch) + *(.drivers) + *(.isr) + } + . = seg_kdata_base; + seg_kdata : { + *(.kdata) + } + . = seg_kunc_base; + seg_kunc : { + *(.unckdata) + } + . = seg_kdata_base; + seg_kdata : { + *(.ksave) + } + . = seg_code_base; + seg_code : { + *(.text) + } + . = seg_reset_base; + seg_reset : { + *(.reset) + } + . = seg_data_base; + seg_data : { + *(.rodata) + . = ALIGN(4); + *(.rodata.*) + . = ALIGN(4); + *(.data) + . = ALIGN(4); + *(.sdata) + . = ALIGN(4); + *(.bss) + *(COMMON) + *(.sbss) + } +} + Index: /branches/fault_tolerance/softs/soft_filter_giet/main.c =================================================================== --- /branches/fault_tolerance/softs/soft_filter_giet/main.c (revision 724) +++ /branches/fault_tolerance/softs/soft_filter_giet/main.c (revision 724) @@ -0,0 +1,631 @@ + +#include "limits.h" +#include "stdio.h" + +#include "../giet_tsar/block_device.h" + +//////////////////////////////////// +// Image parameters + +#define NB_CLUSTER_MAX 256 +#define PIXEL_SIZE 2 +#define NL 1024 +#define NP 1024 + +#define NB_PIXELS ((NP) * (NL)) +#define FRAME_SIZE ((NB_PIXELS) * (PIXEL_SIZE)) + +#define PRINTF(...) ({ if (proc_id == 0) { tty_printf(__VA_ARGS__); } }) + +#define TA(c,l,p) (A[c][((NP) * (l)) + (p)]) +#define TB(c,p,l) (B[c][((NL) * (p)) + (l)]) +#define TC(c,l,p) (C[c][((NP) * (l)) + (p)]) +#define TD(c,l,p) (D[c][((NP) * (l)) + (p)]) +#define TZ(c,l,p) (Z[c][((NP) * (l)) + (p)]) + +#define max(x,y) ((x) > (y) ? (x) : (y)) +#define min(x,y) ((x) < (y) ? (x) : (y)) + +/////////////////////////////////////////// +// tricks to read parameters from ldscript +/////////////////////////////////////////// + +struct plaf; + +extern struct plouf seg_ioc_base; +extern struct plaf seg_heap_base; +extern struct plaf NB_PROCS; +extern struct plaf NB_CLUSTERS; + + +// Required when initializing an array all at once +static void *memcpy(void *_dst, const void *_src, unsigned int size){ + unsigned int *dst = _dst; + const unsigned int *src = _src; + if (! ((unsigned int)dst & 3) && ! ((unsigned int)src & 3)){ + while (size > 3){ + *dst++ = *src++; + size -= 4; + } + } + + unsigned char *cdst = (unsigned char*)dst; + unsigned char *csrc = (unsigned char*)src; + + while (size--){ + *cdst++ = *csrc++; + } + return _dst; +} + + + + + + + + +void main(){ + + ////////////////////////////////// + // convolution kernel parameters + // The content of this section is + // Philips proprietary information. + /////////////////////////////////// + + int vnorm = 115; + int vf[35] = { 1, 1, 2, 2, 2, + 2, 3, 3, 3, 4, + 4, 4, 4, 5, 5, + 5, 5, 5, 5, 5, + 5, 5, 4, 4, 4, + 4, 3, 3, 3, 2, + 2, 2, 2, 1, 1 }; + + int hrange = 100; + int hnorm = 201; + + unsigned int date = 0; + + int c; // cluster index for loops + int l; // line index for loops + int p; // pixel index for loops + int x; // filter index for loops + + const unsigned int proc_id = procid(); // processor id + const unsigned int nlocal_procs = (int) &NB_PROCS; // number of processors per cluster + const unsigned int nclusters = (int) &NB_CLUSTERS; // number of clusters + const unsigned int local_id = proc_id % nlocal_procs; // local task id + const unsigned int cluster_id = proc_id / nlocal_procs; // cluster task id + const unsigned int base = (unsigned int) &seg_heap_base; // base address for shared buffers + const unsigned int increment = 0x80000000 / nclusters * 2; // cluster increment + const unsigned int nglobal_procs = nclusters * nlocal_procs; // number of tasks + const unsigned int npixels = NB_PIXELS; // Number of pixel per frame + const unsigned int frame_size = FRAME_SIZE; // Size of 1 frame (in bytes) + const unsigned int * ioc_address = (unsigned int *) &seg_ioc_base; + const unsigned int block_size = ioc_address[BLOCK_DEVICE_BLOCK_SIZE]; + const unsigned int nblocks = frame_size / block_size; // number of blocks per frame + + const unsigned int lines_per_task = NL / nglobal_procs; // number of lines per task + const unsigned int lines_per_cluster = NL / nclusters; // number of lines per cluster + const unsigned int pixels_per_task = NP / nglobal_procs; // number of columns per task + const unsigned int pixels_per_cluster = NP / nclusters; // number of columns per cluster + + int first, last; + + PRINTF("\n*** Processor %d entering main at cycle %d ***\n\n", proc_id, proctime()); + + + ///////////////////////// + // parameters checking // + ///////////////////////// + + + if ((nlocal_procs != 1) && (nlocal_procs != 2) && (nlocal_procs != 4)){ + PRINTF("NB_PROCS must be 1, 2 or 4\n"); + exit(); + } + + //////////////////////////////////////////////////////////////////////// + // Warning: NB_CLUSTERS must be at least 4 because of the heap size; // + // if there are less clusters, the heap mixes with the stack // + // (the total heap size must be at least 0x01000000) // + //////////////////////////////////////////////////////////////////////// + if ((nclusters != 4) && (nclusters != 8) && (nclusters != 16) && + (nclusters != 32) && (nclusters != 64) && (nclusters !=128) && (nclusters != 256)){ + PRINTF("NB_CLUSTERS must be a power of 2 between 4 and 256\n"); + exit(); + } + + if (proc_id >= nglobal_procs){ + PRINTF("processor id %d larger than NB_CLUSTERS*NB_PROCS\n", proc_id); + exit(); + } + + if (NL % nclusters != 0){ + PRINTF("NB_CLUSTERS must be a divider of NL"); + exit(); + } + + if (NP % nclusters != 0){ + PRINTF("NB_CLUSTERS must be a divider of NP"); + exit(); + } + + + // Arrays of pointers on the shared, distributed buffers + // containing the images (sized for the worst case : 256 clusters) + unsigned short * A[NB_CLUSTER_MAX]; + int * B[NB_CLUSTER_MAX]; + int * C[NB_CLUSTER_MAX]; + int * D[NB_CLUSTER_MAX]; + unsigned char * Z[NB_CLUSTER_MAX]; + + // Arrays of pointers on the instrumentation arrays + // These arrays are indexed by the cluster index (sized for the worst case : 256 clusters) + // each pointer points on the base adress of an array of 4 (NPROCS max) unsigned int + unsigned int * LOAD_START[NB_CLUSTER_MAX]; + unsigned int * LOAD_END[NB_CLUSTER_MAX]; + unsigned int * VERT_START[NB_CLUSTER_MAX]; + unsigned int * VERT_END[NB_CLUSTER_MAX]; + unsigned int * HORI_START[NB_CLUSTER_MAX]; + unsigned int * HORI_END[NB_CLUSTER_MAX]; + unsigned int * DISP_START[NB_CLUSTER_MAX]; + unsigned int * DISP_END[NB_CLUSTER_MAX]; + + // The shared, distributed buffers addresses are computed + // from the seg_heap_base value defined in the ldscript file + // and from the cluster increment = 4Gbytes/nclusters. + // These arrays of pointers are identical and + // replicated in the stack of each task + for (c = 0; c < nclusters; c++){ + unsigned int offset = base + increment * c; + A[c] = (unsigned short *) (offset); + B[c] = (int *) (offset + frame_size * 1 / nclusters); // We increment by 2 * frame_size + C[c] = (int *) (offset + frame_size * 3 / nclusters); // because sizeof(int) = 2*sizeof(short) + D[c] = (int *) (offset + frame_size * 5 / nclusters); // so an array of frame_size elements of type + Z[c] = (unsigned char *) (offset + frame_size * 7 / nclusters); // int can contain the equivalent of 2 frames + + offset = base + increment * c + frame_size * 8 / nclusters; + LOAD_START[c] = (unsigned int *) (offset + nlocal_procs * sizeof(unsigned int) * 0); + LOAD_END[c] = (unsigned int *) (offset + nlocal_procs * sizeof(unsigned int) * 1); + VERT_START[c] = (unsigned int *) (offset + nlocal_procs * sizeof(unsigned int) * 2); + VERT_END[c] = (unsigned int *) (offset + nlocal_procs * sizeof(unsigned int) * 3); + HORI_START[c] = (unsigned int *) (offset + nlocal_procs * sizeof(unsigned int) * 4); + HORI_END[c] = (unsigned int *) (offset + nlocal_procs * sizeof(unsigned int) * 5); + DISP_START[c] = (unsigned int *) (offset + nlocal_procs * sizeof(unsigned int) * 6); + DISP_END[c] = (unsigned int *) (offset + nlocal_procs * sizeof(unsigned int) * 7); + } + + PRINTF("NB_CLUSTERS = %d\n", nclusters); + PRINTF("NB_LOCAL_PROCS = %d\n", nlocal_procs); + PRINTF("NB_GLOBAL_PROCS = %d\n", nglobal_procs); + PRINTF("NB_PIXELS = %d\n", npixels); + PRINTF("PIXEL_SIZE = %d\n", PIXEL_SIZE); + PRINTF("FRAME_SIZE = %d\n", frame_size); + PRINTF("BLOCK_SIZE = %d\n", block_size); + PRINTF("NB_BLOCKS = %d\n\n", nblocks); + + + PRINTF("*** Starting barrier init at cycle %d ***\n", proctime()); + + // barriers initialization + barrier_init(0, nglobal_procs); + barrier_init(1, nglobal_procs); + barrier_init(2, nglobal_procs); + barrier_init(3, nglobal_procs); + + PRINTF("*** Completing barrier init at cycle %d ***\n", proctime()); + + + //////////////////////////////////////////////////////// + // pseudo parallel load from disk to A[c] buffers + // only task running on processor with (local_id==0) does it + // nblocks/nclusters are loaded in each cluster + //////////////////////////////////////////////////////// + + if (local_id == 0){ + int p; + date = proctime(); + PRINTF("\n*** Starting load at cycle %d\n", date); + for (p = 0; p < nlocal_procs; p++){ + LOAD_START[cluster_id][p] = date; + } + + if (ioc_read(nblocks*cluster_id/nclusters, A[cluster_id], nblocks/nclusters)){ + PRINTF("echec ioc_read\n"); + exit(1); + } + if (ioc_completed()){ + PRINTF("echec ioc_completed\n"); + exit(1); + } + + date = proctime(); + PRINTF("*** Completing load at cycle %d\n", date); + for (p = 0; p < nlocal_procs; p++){ + LOAD_END[cluster_id][p] = date; + } + } + + barrier_wait(0); + + + //////////////////////////////////////////////////////// + // parallel horizontal filter : + // B <= transpose(FH(A)) + // D <= A - FH(A) + // Each task computes (NL/nglobal_procs) lines + // The image must be extended : + // if (z<0) TA(cluster_id,l,z) == TA(cluster_id,l,0) + // if (z>NP-1) TA(cluster_id,l,z) == TA(cluster_id,l,NP-1) + //////////////////////////////////////////////////////// + + date = proctime(); + PRINTF("\n*** Starting horizontal filter at cycle %d\n", date); + HORI_START[cluster_id][local_id] = date; + + // l = absolute line index / p = absolute pixel index + // first & last define which lines are handled by a given task(cluster_id,local_id) + + first = (cluster_id * nlocal_procs + local_id) * lines_per_task; + last = first + lines_per_task; + + for (l = first; l < last; l++){ + // src_c and src_l are the cluster index and the line index for A & D + int src_c = l / lines_per_cluster; + int src_l = l % lines_per_cluster; + + // We use the specific values of the horizontal ep-filter for optimisation: + // sum(p) = sum(p-1) + TA[p+hrange] - TA[p-hrange-1] + // To minimize the number of tests, the loop on pixels is split in three domains + + int sum_p = (hrange + 2) * TA(src_c, src_l, 0); + for (x = 1; x < hrange; x++){ + sum_p = sum_p + TA(src_c, src_l, x); + } + + // first domain : from 0 to hrange + for (p = 0; p < hrange + 1; p++){ + // dst_c and dst_p are the cluster index and the pixel index for B + int dst_c = p / pixels_per_cluster; + int dst_p = p % pixels_per_cluster; + sum_p = sum_p + (int) TA(src_c, src_l, p + hrange) - (int) TA(src_c, src_l, 0); + TB(dst_c, dst_p, l) = sum_p / hnorm; + TD(src_c, src_l, p) = (int) TA(src_c, src_l, p) - sum_p / hnorm; + } + // second domain : from (hrange+1) to (NP-hrange-1) + for (p = hrange + 1; p < NP - hrange; p++){ + // dst_c and dst_p are the cluster index and the pixel index for B + int dst_c = p / pixels_per_cluster; + int dst_p = p % pixels_per_cluster; + sum_p = sum_p + (int) TA(src_c, src_l, p + hrange) - (int) TA(src_c, src_l, p - hrange - 1); + TB(dst_c, dst_p, l) = sum_p / hnorm; + TD(src_c, src_l, p) = (int) TA(src_c, src_l, p) - sum_p / hnorm; + } + // third domain : from (NP-hrange) to (NP-1) + for (p = NP - hrange; p < NP; p++){ + // dst_c and dst_p are the cluster index and the pixel index for B + int dst_c = p / pixels_per_cluster; + int dst_p = p % pixels_per_cluster; + sum_p = sum_p + (int) TA(src_c, src_l, NP - 1) - (int) TA(src_c, src_l, p - hrange - 1); + TB(dst_c, dst_p, l) = sum_p / hnorm; + TD(src_c, src_l, p) = (int) TA(src_c, src_l, p) - sum_p / hnorm; + } + + PRINTF(" - line %d computed at cycle %d\n", l, proctime()); + } + + date = proctime(); + PRINTF("*** Completing horizontal filter at cycle %d\n", date); + HORI_END[cluster_id][local_id] = date; + + barrier_wait(1); + + + ////////////////////////////////////////////////////////// + // parallel vertical filter : + // C <= transpose(FV(B)) + // Each task computes (NP/nglobal_procs) columns + // The image must be extended : + // if (l<0) TB(cluster_id,p,x) == TB(cluster_id,p,0) + // if (l>NL-1) TB(cluster_id,p,x) == TB(cluster_id,p,NL-1) + ////////////////////////////////////////////////////////// + + date = proctime(); + PRINTF("\n*** starting vertical filter at cycle %d\n", date); + VERT_START[cluster_id][local_id] = date; + + // l = absolute line index / p = absolute pixel index + // first & last define which pixels are handled by a given task(cluster_id,local_id) + + first = (cluster_id * nlocal_procs + local_id) * pixels_per_task; + last = first + pixels_per_task; + + for (p = first; p < last; p++){ + // src_c and src_p are the cluster index and the pixel index for B + int src_c = p / pixels_per_cluster; + int src_p = p % pixels_per_cluster; + + int sum_l; + + // We use the specific values of the vertical ep-filter + // To minimize the number of tests, the NL lines are split in three domains + + // first domain : explicit computation for the first 18 values + for (l = 0; l < 18; l++){ + // dst_c and dst_l are the cluster index and the line index for C + int dst_c = l / lines_per_cluster; + int dst_l = l % lines_per_cluster; + + for (x = 0, sum_l = 0; x < 35; x++){ + sum_l = sum_l + vf[x] * TB(src_c, src_p, max(l - 17 + x,0) ); + } + TC(dst_c, dst_l, p) = sum_l / vnorm; + } + // second domain + for (l = 18; l < NL - 17; l++){ + // dst_c and dst_l are the cluster index and the line index for C + int dst_c = l / lines_per_cluster; + int dst_l = l % lines_per_cluster; + + sum_l = sum_l + TB(src_c, src_p, l + 4) + + TB(src_c, src_p, l + 8) + + TB(src_c, src_p, l + 11) + + TB(src_c, src_p, l + 15) + + TB(src_c, src_p, l + 17) + - TB(src_c, src_p, l - 5) + - TB(src_c, src_p, l - 9) + - TB(src_c, src_p, l - 12) + - TB(src_c, src_p, l - 16) + - TB(src_c, src_p, l - 18); + TC(dst_c, dst_l, p) = sum_l / vnorm; + } + // third domain + for (l = NL - 17; l < NL; l++){ + // dst_c and dst_l are the cluster index and the line index for C + int dst_c = l / lines_per_cluster; + int dst_l = l % lines_per_cluster; + + sum_l = sum_l + TB(src_c, src_p, min(l + 4, NL - 1)) + + TB(src_c, src_p, min(l + 8, NL - 1)) + + TB(src_c, src_p, min(l + 11, NL - 1)) + + TB(src_c, src_p, min(l + 15, NL - 1)) + + TB(src_c, src_p, min(l + 17, NL - 1)) + - TB(src_c, src_p, l - 5) + - TB(src_c, src_p, l - 9) + - TB(src_c, src_p, l - 12) + - TB(src_c, src_p, l - 16) + - TB(src_c, src_p, l - 18); + TC(dst_c, dst_l, p) = sum_l / vnorm; + } + PRINTF(" - column %d computed at cycle %d\n", p, proctime()); + } + + date = proctime(); + PRINTF("*** Completing vertical filter at cycle %d\n", date); + VERT_END[cluster_id][local_id] = date; + + barrier_wait(2); + + + //////////////////////////////////////////////////////////////// + // final computation and parallel display + // Z <= D + C + // Each processor use its private DMA channel to display + // the resulting image, line per line (one byte per pixel). + // Eah processor computes & displays (NL/nglobal_procs) lines. + //////////////////////////////////////////////////////////////// + + date = proctime(); + PRINTF("\n*** Starting display at cycle %d\n", date); + DISP_START[cluster_id][local_id] = date; + + first = local_id * lines_per_task; + last = first + lines_per_task; + + for (l = first; l < last; l++){ + for (p = 0; p < NP; p++){ + TZ(cluster_id,l,p) = (unsigned char) (((TD(cluster_id,l,p) + TC(cluster_id,l,p)) >> 8) & 0xFF); + } + fb_write(NP * (cluster_id * lines_per_cluster + l), &TZ(cluster_id,l,0), NP); + } + + date = proctime(); + PRINTF("*** Completing display at cycle %d\n", date); + DISP_END[cluster_id][local_id] = date; + + barrier_wait(3); + + + ///////////////////////////////////////////////////////// + // Instrumentation (done by processor 0 in cluster 0) + ///////////////////////////////////////////////////////// + + if (proc_id == 0){ + date = proctime(); + PRINTF("\n*** Starting Instrumentation at cycle %d\n\n", date); + + int cc, pp; + unsigned int min_load_start = INT_MAX; + unsigned int max_load_start = 0; + unsigned int min_load_ended = INT_MAX; + unsigned int max_load_ended = 0; + + unsigned int min_hori_start = INT_MAX; + unsigned int max_hori_start = 0; + unsigned int min_hori_ended = INT_MAX; + unsigned int max_hori_ended = 0; + + unsigned int min_vert_start = INT_MAX; + unsigned int max_vert_start = 0; + unsigned int min_vert_ended = INT_MAX; + unsigned int max_vert_ended = 0; + + unsigned int min_disp_start = INT_MAX; + unsigned int max_disp_start = 0; + unsigned int min_disp_ended = INT_MAX; + unsigned int max_disp_ended = 0; + + for (cc = 0; cc < nclusters; cc++){ + for (pp = 0; pp < nlocal_procs; pp++ ){ + if (LOAD_START[cc][pp] < min_load_start){ + min_load_start = LOAD_START[cc][pp]; + } + if (LOAD_START[cc][pp] > max_load_start){ + max_load_start = LOAD_START[cc][pp]; + } + if (LOAD_END[cc][pp] < min_load_ended){ + min_load_ended = LOAD_END[cc][pp]; + } + if (LOAD_END[cc][pp] > max_load_ended){ + max_load_ended = LOAD_END[cc][pp]; + } + + if (HORI_START[cc][pp] < min_hori_start){ + min_hori_start = HORI_START[cc][pp]; + } + if (HORI_START[cc][pp] > max_hori_start){ + max_hori_start = HORI_START[cc][pp]; + } + if (HORI_END[cc][pp] < min_hori_ended){ + min_hori_ended = HORI_END[cc][pp]; + } + if (HORI_END[cc][pp] > max_hori_ended){ + max_hori_ended = HORI_END[cc][pp]; + } + + if (VERT_START[cc][pp] < min_vert_start){ + min_vert_start = VERT_START[cc][pp]; + } + if (VERT_START[cc][pp] > max_vert_start){ + max_vert_start = VERT_START[cc][pp]; + } + if (VERT_END[cc][pp] < min_vert_ended){ + min_vert_ended = VERT_END[cc][pp]; + } + if (VERT_END[cc][pp] > max_vert_ended){ + max_vert_ended = VERT_END[cc][pp]; + } + + if (DISP_START[cc][pp] < min_disp_start){ + min_disp_start = DISP_START[cc][pp]; + } + if (DISP_START[cc][pp] > max_disp_start){ + max_disp_start = DISP_START[cc][pp]; + } + if (DISP_END[cc][pp] < min_disp_ended){ + min_disp_ended = DISP_END[cc][pp]; + } + if (DISP_END[cc][pp] > max_disp_ended){ + max_disp_ended = DISP_END[cc][pp]; + } + } + } + PRINTF(" - LOAD_START : min = %d / max = %d / med = %d / delta = %d\n", + min_load_start, max_load_start, (min_load_start+max_load_start) / 2, max_load_start-min_load_start); + PRINTF(" - LOAD_END : min = %d / max = %d / med = %d / delta = %d\n", + min_load_ended, max_load_ended, (min_load_ended+max_load_ended) / 2, max_load_ended-min_load_ended); + + PRINTF(" - HORI_START : min = %d / max = %d / med = %d / delta = %d\n", + min_hori_start, max_hori_start, (min_hori_start+max_hori_start) / 2, max_hori_start-min_hori_start); + PRINTF(" - HORI_END : min = %d / max = %d / med = %d / delta = %d\n", + min_hori_ended, max_hori_ended, (min_hori_ended+max_hori_ended) / 2, max_hori_ended-min_hori_ended); + + PRINTF(" - VERT_START : min = %d / max = %d / med = %d / delta = %d\n", + min_vert_start, max_vert_start, (min_vert_start+max_vert_start) / 2, max_vert_start-min_vert_start); + PRINTF(" - VERT_END : min = %d / max = %d / med = %d / delta = %d\n", + min_vert_ended, max_vert_ended, (min_vert_ended+max_vert_ended) / 2, max_vert_ended-min_vert_ended); + + PRINTF(" - DISP_START : min = %d / max = %d / med = %d / delta = %d\n", + min_disp_start, max_disp_start, (min_disp_start+max_disp_start) / 2, max_disp_start-min_disp_start); + PRINTF(" - DISP_END : min = %d / max = %d / med = %d / delta = %d\n", + min_disp_ended, max_disp_ended, (min_disp_ended+max_disp_ended) / 2, max_disp_ended-min_disp_ended); + + PRINTF(" - BARRIER LOAD/HORI = %d\n", min_hori_start - max_load_ended); + PRINTF(" - BARRIER HORI/VERT = %d\n", min_vert_start - max_hori_ended); + PRINTF(" - BARRIER VERT/DISP = %d\n", min_disp_start - max_vert_ended); + + PRINTF(" - LOAD = %d\n", max_load_ended); + PRINTF(" - FILTER = %d\n", max_vert_ended - max_load_ended); + PRINTF(" - DISPLAY = %d\n", max_disp_ended - max_vert_ended); + + PRINTF("\nBEGIN LOAD_START\n"); + for (cc = 0; cc < nclusters; cc++){ + for (pp = 0; pp < nlocal_procs; pp++){ + PRINTF("cluster= %d proc= %d date= %d\n", cc, pp, LOAD_START[cc][pp]); + } + } + PRINTF("END\n"); + + PRINTF("\nBEGIN LOAD_END\n"); + for (cc = 0; cc < nclusters; cc++){ + for (pp = 0; pp < nlocal_procs; pp++){ + PRINTF("cluster= %d proc= %d date= %d\n", cc, pp, LOAD_END[cc][pp]); + } + } + PRINTF("END\n"); + + PRINTF("\nBEGIN HORI_START\n"); + for (cc = 0; cc < nclusters; cc++){ + for (pp = 0; pp < nlocal_procs; pp++){ + PRINTF("cluster= %d proc= %d date= %d\n", cc, pp, HORI_START[cc][pp]); + } + } + PRINTF("END\n"); + + PRINTF("\nBEGIN HORI_END\n"); + for (cc = 0; cc < nclusters; cc++){ + for (pp = 0; pp < nlocal_procs; pp++){ + PRINTF("cluster= %d proc= %d date= %d\n", cc, pp, HORI_END[cc][pp]); + } + } + PRINTF("END\n"); + + PRINTF("\nBEGIN VERT_START\n"); + for (cc = 0; cc < nclusters; cc++){ + for (pp = 0; pp < nlocal_procs; pp++){ + PRINTF("cluster= %d proc= %d date= %d\n", cc, pp, VERT_START[cc][pp]); + } + } + PRINTF("END\n"); + + PRINTF("\nBEGIN VERT_END\n"); + for (cc = 0; cc < nclusters; cc++){ + for (pp = 0; pp < nlocal_procs; pp++ ){ + PRINTF("cluster= %d proc= %d date= %d\n", cc, pp, VERT_END[cc][pp]); + } + } + PRINTF("END\n"); + + PRINTF("\nBEGIN DISP_START\n"); + for (cc = 0; cc < nclusters; cc++){ + for (pp = 0; pp < nlocal_procs; pp++){ + PRINTF("cluster= %d proc= %d date= %d\n", cc, pp, DISP_START[cc][pp]); + } + } + PRINTF("END\n"); + + PRINTF("\nBEGIN DISP_END\n"); + for (cc = 0; cc < nclusters; cc++){ + for (pp = 0; pp < nlocal_procs; pp++){ + PRINTF("cluster= %d proc= %d date= %d\n", cc, pp, DISP_END[cc][pp]); + } + } + PRINTF("END\n"); + } + + while(1); + +} // end main() + +// Local Variables: +// tab-width: 3 +// c-basic-offset: 3 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 + + Index: /branches/fault_tolerance/softs/soft_filter_giet/philips_image.raw =================================================================== --- /branches/fault_tolerance/softs/soft_filter_giet/philips_image.raw (revision 724) +++ /branches/fault_tolerance/softs/soft_filter_giet/philips_image.raw (revision 724) @@ -0,0 +1,55839 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +  + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +  + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +  + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + # +! +  +! + + ! +! + + + + + + + + + !" + + +" +  + " + ! + +!! ! %# ! + + + + + + + + + + + + + + +! + + + + + + + +  ! + + + + + + ##!#&(" + +$$ + +" + + + +!  + + !! +!! + +!" + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +!! + + + + + + + + +! + + + + + + +! + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +$"(''$!#$$$"$$(%!&$$%)'$'#!$$'))"&&#%'$%&#%%$$)'!#$$$&%'$$"&))',%',)##$#$!"$#! ###$ !!#("$%%$%$%##!#"$%#%$#"$'()'$'&%'((('&'*++'**')&#'$"(((%&($&&)'#$&&"'"$$)(((%%%$#&#$%$" + ##!# "#!## +!$ #"!""%"%!"" + + + +%$!! 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/* boot code */ + +seg_kcode_base = 0x00010000; /* kernel code */ +seg_kdata_base = 0x00020000; /* kernel cacheable data */ +seg_kunc_base = 0x00030000; /* kernel uncacheable data */ + +seg_code_base = 0x00040000; /* application code */ +seg_data_base = 0x00050000; /* application data */ + +seg_heap_base = 0x00100000; /* heaps for applications */ +seg_stack_base = 0x00300000; /* stacks ifor applications */ + +seg_ramdisk_base = 0x00800000; /* virtual disk */ + +seg_xcu_base = 0xF0000000; /* controler XCU */ +seg_tty_base = 0xF4000000; /* controler TTY */ +seg_fbf_base = 0xF3000000; /* controler FBF */ +seg_ioc_base = 0xF2000000; /* controler IOC */ +seg_nic_base = 0xF7000000; /* controler NIC */ +seg_cma_base = 0xF8000000; /* controler CMA */ +seg_pic_base = 0xF9000000; /* controler PIC */ +seg_mmc_base = 0xE0000000; /* config MMC */ + + +/* Grouping sections into segments */ + +SECTIONS +{ + . = seg_kcode_base; + seg_kcode : { + *(.giet) + *(.switch) + *(.drivers) + *(.isr) + } + . = seg_kdata_base; + seg_kdata : { + *(.kdata) + } + . = seg_kunc_base; + seg_kunc : { + *(.unckdata) + } + . = seg_kdata_base; + seg_kdata : { + *(.ksave) + } + . = seg_code_base; + seg_code : { + *(.text) + } + . = seg_reset_base; + seg_reset : { + *(.reset) + } + . = seg_data_base; + seg_data : { + *(.rodata) + . = ALIGN(4); + *(.rodata.*) + . = ALIGN(4); + *(.data) + . = ALIGN(4); + *(.sdata) + . = ALIGN(4); + *(.bss) + *(COMMON) + *(.sbss) + } +} + Index: /branches/fault_tolerance/softs/soft_hello_giet/main.c =================================================================== --- /branches/fault_tolerance/softs/soft_hello_giet/main.c (revision 724) +++ /branches/fault_tolerance/softs/soft_hello_giet/main.c (revision 724) @@ -0,0 +1,29 @@ +#include "hard_config.h" +#include "stdio.h" + +void main() +{ + char c; + unsigned int proc_id = _procid(); + unsigned int l = (proc_id % NB_PROCS_MAX); + unsigned int x = (proc_id / NB_PROCS_MAX) >> Y_WIDTH; + unsigned int y = (proc_id / NB_PROCS_MAX) & ((1< $@.txt + +reset.o: $(GIET)/reset.S hard_config.h + $(CC) -I. $(CFLAGS) -c -o $@ $< + $(DU) -D $@ > $@.txt + +giet.o: $(GIET)/giet.S hard_config.h + $(CC) -I. $(CFLAGS) -c -o $@ $< + $(DU) -D $@ > $@.txt + +stdio.o: $(GIET)/stdio.c hard_config.h + $(CC) -I. $(CFLAGS) -c -o $@ $< + $(DU) -D $@ > $@.txt + +main.o: main.c hard_config.h + $(CC) -I. $(CFLAGS) -I$(GIET) -c -o $@ $< + $(DU) -D $@ > $@.txt + +clean: + rm -f *.o bin.soft *.txt core term* temp Index: /branches/fault_tolerance/softs/soft_sort_giet/hard_config.h =================================================================== --- /branches/fault_tolerance/softs/soft_sort_giet/hard_config.h (revision 724) +++ /branches/fault_tolerance/softs/soft_sort_giet/hard_config.h (revision 724) @@ -0,0 +1,26 @@ +/*******************************************************************/ +/* This file define various hardware parameters that are used by */ +/* both the giet_tsar OS and by the hardware (top.cpp file) */ +/*******************************************************************/ + +#ifndef _HARD_CONFIG_H +#define _HARD_CONFIG_H + +#define X_SIZE 2 +#define Y_SIZE 2 +#define X_WIDTH 4 +#define Y_WIDTH 4 + +#define NB_PROCS_MAX 1 + +#define USE_RAMDISK 1 +#define USE_EXT_IO 0 + +#define NB_DMA_CHANNELS 0 +#define NB_HBA_CHANNELS 0 +#define NB_NIC_CHANNELS 0 +#define NB_CMA_CHANNELS 0 + +#define NB_TTY_CHANNELS 1 + +#endif //_HARD_CONFIG_H Index: /branches/fault_tolerance/softs/soft_sort_giet/ldscript =================================================================== --- /branches/fault_tolerance/softs/soft_sort_giet/ldscript (revision 724) +++ /branches/fault_tolerance/softs/soft_sort_giet/ldscript (revision 724) @@ -0,0 +1,82 @@ +/********************************************************** + File : ldscript + Author : Alain Greiner + Date : January 2014 +**********************************************************/ + +/* definition of the base address for all segments +The peripherals base addresses are referenced by the +software drivers and must be defined, even if the +peripherals are not present in the architecture */ + +seg_reset_base = 0x00000000; /* boot code */ + +seg_kcode_base = 0x00010000; /* kernel code */ +seg_kdata_base = 0x00020000; /* kernel cacheable data */ +seg_kunc_base = 0x00030000; /* kernel uncacheable data */ + +seg_code_base = 0x00040000; /* application code */ +seg_data_base = 0x00050000; /* application data */ + +seg_heap_base = 0x00100000; /* heaps for applications */ +seg_stack_base = 0x00300000; /* stacks ifor applications */ + +seg_ramdisk_base = 0x00800000; /* virtual disk */ + +seg_xcu_base = 0xF0000000; /* controler XCU */ +seg_tty_base = 0xF4000000; /* controler TTY */ +seg_fbf_base = 0xF3000000; /* controler FBF */ +seg_ioc_base = 0xF2000000; /* controler IOC */ +seg_nic_base = 0xF7000000; /* controler NIC */ +seg_cma_base = 0xF8000000; /* controler CMA */ +seg_pic_base = 0xF9000000; /* controler PIC */ +seg_mmc_base = 0xE0000000; /* config MMC */ + + +/* Grouping sections into segments */ + +SECTIONS +{ + . = seg_kcode_base; + seg_kcode : { + *(.giet) + *(.switch) + *(.drivers) + *(.isr) + } + . = seg_kdata_base; + seg_kdata : { + *(.kdata) + } + . = seg_kunc_base; + seg_kunc : { + *(.unckdata) + } + . = seg_kdata_base; + seg_kdata : { + *(.ksave) + } + . = seg_code_base; + seg_code : { + *(.text) + } + . = seg_reset_base; + seg_reset : { + *(.reset) + } + . = seg_data_base; + seg_data : { + *(.rodata) + . = ALIGN(4); + *(.rodata.*) + . = ALIGN(4); + *(.data) + . = ALIGN(4); + *(.sdata) + . = ALIGN(4); + *(.bss) + *(COMMON) + *(.sbss) + } +} + Index: /branches/fault_tolerance/softs/soft_sort_giet/main.c =================================================================== --- /branches/fault_tolerance/softs/soft_sort_giet/main.c (revision 724) +++ /branches/fault_tolerance/softs/soft_sort_giet/main.c (revision 724) @@ -0,0 +1,225 @@ +//================================================================================================= +// File : main.c +// +// Date : 08/2011 +// +// Author : Cesar Fuguet Tortolero +// : +// +// Description: Sort application using the GIET operating system. +// This application uses the barrier routines to apply a sort algorithm +// in several stages. +//================================================================================================= + +#include "stdio.h" +#include "hard_config.h" + +#define ARRAY_LENGTH (1 << 10) // 1024 ITEMS +#define IPP (ARRAY_LENGTH / total_procs) // ITEMS PER PROCESSOR +#define VERBOSE 1 + +#if (VERBOSE == 1) +#define printf(...) _tty_printf(__VA_ARGS__) +#define puts(...) _tty_puts(__VA_ARGS__) +#else +#define printf(...) +#define puts(...) +#endif + +#define task0_printf(...) if(thread_id == 0) _tty_printf(__VA_ARGS__) + +int array0[ARRAY_LENGTH]; +int array1[ARRAY_LENGTH]; + +volatile int init_ok = 0; + +void bubbleSort(int * array, unsigned int length, unsigned int init_pos); +void merge(int * array, int * result, int length, int init_pos_a, int init_pos_b, int init_pos_result); + +void main() +{ + int total_procs = NB_PROCS_MAX * X_SIZE * Y_SIZE; + int proc_id = _procid(); + int lid = proc_id % NB_PROCS_MAX; + int cluster_xy = proc_id / NB_PROCS_MAX; + int x = (cluster_xy >> Y_WIDTH); + int y = (cluster_xy ) & ((1 << Y_WIDTH) - 1); + + int thread_id = ((x * Y_SIZE) + y) * NB_PROCS_MAX + lid; + + int * src_array; + int * dst_array; + int i; + + while((thread_id != 0) && (init_ok == 0)); + + /**************************************************************************/ + /* Hello World */ + + task0_printf("\n[ PROC_%d_%d_%d ] Starting SORT application\n",x,y,lid); + + task0_printf("[ PROC_%d_%d_%d ] MESH %d x %d x %d processors\n", + x,y,lid, X_SIZE, Y_SIZE, NB_PROCS_MAX); + + /**************************************************************************/ + /* Barriers Initialisation */ + + if (thread_id == 0) + { + for (i = 0; i < __builtin_ctz(total_procs); i++) + { + printf("[ PROC_%d_%d_%d ] Initializing barrier %d with %d\n", + x,y,lid, i, total_procs >> i); + + _barrier_init(i, total_procs >> i); + } + printf("\n"); + asm volatile ("sync"); + init_ok = 1; + } + + /**************************************************************************/ + /* Array Initialisation */ + + for (i = IPP * thread_id; i < IPP * (thread_id + 1); i++) + { + array0[i] = _rand(); + } + + asm volatile ("sync"); + _barrier_wait(0); + + /**************************************************************************/ + /* Parallel sorting of array pieces */ + + printf("[ PROC_%d_%d_%d ] Stage 0: Starting...\n\r", x,y,lid); + bubbleSort(array0, IPP, IPP * thread_id); + printf("[ PROC_%d_%d_%d ] Stage 0: Finishing...\n\r", x,y,lid); + + for (i = 0; i < __builtin_ctz(total_procs); i++) + { + asm volatile ("sync"); + _barrier_wait(i); + + if((thread_id % (2 << i)) != 0) _exit(); + + printf("[ PROC_%d_%d_%d ] Stage %d: Starting...\n\r", x,y,lid, i+1); + + if((i % 2) == 0) + { + src_array = &array0[0]; + dst_array = &array1[0]; + } + else + { + src_array = &array1[0]; + dst_array = &array0[0]; + } + + merge(src_array, dst_array + , IPP << i + , IPP * thread_id + , IPP * (thread_id + (1 << i)) + , IPP * thread_id + ); + + printf("[ PROC_%d_%d_%d ] Stage %d: Finishing...\n\r", x,y,lid, i+1); + } + + int success; + int failure_index; + + if(thread_id == 0) + { + success = 1; + + for(i=0; i<(ARRAY_LENGTH-1); i++) + { + if(dst_array[i] > dst_array[i+1]) + { + + success = 0; + failure_index = i; + break; + } + } + + if (success) + { + printf("[ PROC_%d_%d_%d ] Success!!\n\r", x,y,lid); + } + else + { + printf("Failure!! Incorrect element: %d\n\r", failure_index); + + + for(i=0; i array[j + 1]) + { + aux = array[j + 1]; + array[j + 1] = array[j]; + array[j] = aux; + } + } + } +} + +void merge(int * array, int * result, int length, int init_pos_a, int init_pos_b, int init_pos_result) +{ + int i; + int j; + int k; + + i = 0; + j = 0; + k = init_pos_result; + + while((i < length) || (j < length)) + { + if((i < length) && (j < length)) + { + if(array[init_pos_a + i] < array[init_pos_b + j]) + { + result[k++] = array[init_pos_a + i]; + i++; + } + else + { + result[k++] = array[init_pos_b + j]; + j++; + } + } + else if(i < length) + { + result[k++] = array[init_pos_a + i]; + i++; + } + else + { + result[k++] = array[init_pos_b + j]; + j++; + } + } +} + +/* vim: tabstop=4 : shiftwidth=4 : expandtab +*/ Index: /branches/fault_tolerance/softs/soft_transpose_giet/Makefile =================================================================== --- /branches/fault_tolerance/softs/soft_transpose_giet/Makefile (revision 724) +++ /branches/fault_tolerance/softs/soft_transpose_giet/Makefile (revision 724) @@ -0,0 +1,36 @@ +LD = mipsel-unknown-elf-ld +CC = mipsel-unknown-elf-gcc +AS = mipsel-unknown-elf-as +DU = mipsel-unknown-elf-objdump + +OBJS = reset.o \ + giet.o \ + stdio.o \ + main.o + +CFLAGS = -Wall -mno-gpopt -ffreestanding -fomit-frame-pointer -mips32 -ggdb + +GIET = ../giet_tsar + +bin.soft: $(OBJS) ldscript + $(LD) -o $@ -T ldscript $(OBJS) + $(DU) -D $@ > $@.txt + +reset.o: $(GIET)/reset.S hard_config.h + $(CC) -I. $(CFLAGS) -c -o $@ $< + $(DU) -D $@ > $@.txt + +giet.o: $(GIET)/giet.S hard_config.h + $(CC) -I. $(CFLAGS) -c -o $@ $< + $(DU) -D $@ > $@.txt + +stdio.o: $(GIET)/stdio.c hard_config.h + $(CC) -I. $(CFLAGS) -c -o $@ $< + $(DU) -D $@ > $@.txt + +main.o: main.c hard_config.h + $(CC) -I. $(CFLAGS) -I$(GIET) -c -o $@ $< + $(DU) -D $@ > $@.txt + +clean: + rm -f *.o bin.soft *.txt core term* temp Index: /branches/fault_tolerance/softs/soft_transpose_giet/bridge256.raw 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"##$$$$'&((&'++'&&'''()-./00.+*+*)'''((020/0/-- + + + + + + + + + + + + + + + + + + + + !!!""###""##"""$$####""######"#$$###""#$%"!""#### !$#%$&%(&))&'*)&&&&')))-//..-,(,,*)('''/2332/-, + + + + + + + + + + + + + + + + + + + + +  +  !#$$$$###"!!!!!####""###$$$###"%$#"""#"$###$$##"#&#%"%$%%()'),+%%%%&&'(*+,-++*)-+*('&&'+.35320- + + + + + + + + + + + + + + + + +! + + + + + + + +!$%$#"#""!!!!!####""##$$%%$###%#!""##"$$#######"&!%!%$%$()))+)%&%&%&&&'*))*+--+*)'&%%%$)06552, + + + + + + + + + + + + + + + + + ! + + + + + + + + !#$"!##"!!!!!"!""""""#$$%%%%%%#!!!#$%""""""""#"&!&"'&%$')()(&'&'&''&%))))),--*)(''&&%$&-3465- + + + + + + + + + + + + + + + +! + + + + + + + !!! "!!! !!""""""##$%%&'(*'#! #$ !!!!"""&$(!&!'&#"&(()(''&%%%%%%-+)'),-,*)(''''')',.0570 + + + + + + + + + + + + + + + + + + + + + + + + + + + +  + !! !!"!!"""!!$%#%('**&! + "! ! ##!""%!(" >8##%&''''&&%%%$$$%$(%(&)K++)())((***-/674 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +   + + +!!!"!!""""""#"#$$$'')*'" + ""!"#""$$ $#%@=#$$&''('&&%%$$##$$(&(')?+,*))((())))+2:: + + + + + + + + + + + + + + + + + + + + + + + + + + +  ! +! !"" "# "#"#&&)(% "" +!! "#"#'('((!'!#$$%'(((&&%%$####%%&((*0++)()(((((*'&.6: + + + + + + + + + + + + + + + + + + + + + +! + + !!  + + +!  !! #""'"&(%#""" ! """$$#%$)''%#$$%''''&%%%$$$##$#&'&*'*)()'''''(*)%)15 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +!! !! + + +! + """& $'&$"! '$!#$! %(%&!''%(#$%&&&'&%%%%%%%%$# %&$*&**)('''&'(*)%&+- + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +!!!!!!"# + + !!" + +! #"%%&$#!$"!"#!"& %"(($&$%%&&&&&%%%%%%%%$# $%#)()))(('''(()(%&*+ + + + + + + + + + + + + + + + + + + + + + + + + +! + + + +""!  + !!#%$" +# +!#!  "#&&$! +"#""!"%%#&"%%$%$$%&&&%%&&&&%%%%##!#$$'())))))''('('$%)* + + + + + + + + + + + + + + + + + + + + +! + + + + +!!  +"$#%(&#!(% &)$  #$"'*$!#"!"#"$#$#$$%&&&&%&&&&%$$$!##"$&%'***))(''('('$$'( Index: /branches/fault_tolerance/softs/soft_transpose_giet/ldscript =================================================================== --- /branches/fault_tolerance/softs/soft_transpose_giet/ldscript (revision 724) +++ /branches/fault_tolerance/softs/soft_transpose_giet/ldscript (revision 724) @@ -0,0 +1,82 @@ +/********************************************************** + File : ldscript + Author : Alain Greiner + Date : January 2014 +**********************************************************/ + +/* definition of the base address for all segments +The peripherals base addresses are referenced by the +software drivers and must be defined, even if the +peripherals are not present in the architecture */ + +seg_reset_base = 0x00000000; /* boot code */ + +seg_kcode_base = 0x00010000; /* kernel code */ +seg_kdata_base = 0x00020000; /* kernel cacheable data */ +seg_kunc_base = 0x00030000; /* kernel uncacheable data */ + +seg_code_base = 0x00040000; /* application code */ +seg_data_base = 0x00050000; /* application data */ + +seg_heap_base = 0x00100000; /* heaps for applications */ +seg_stack_base = 0x00300000; /* stacks ifor applications */ + +seg_ramdisk_base = 0x00800000; /* virtual disk */ + +seg_xcu_base = 0xF0000000; /* controler XCU */ +seg_tty_base = 0xF4000000; /* controler TTY */ +seg_fbf_base = 0xF3000000; /* controler FBF */ +seg_ioc_base = 0xF2000000; /* controler IOC */ +seg_nic_base = 0xF7000000; /* controler NIC */ +seg_cma_base = 0xF8000000; /* controler CMA */ +seg_pic_base = 0xF9000000; /* controler PIC */ +seg_mmc_base = 0xE0000000; /* config MMC */ + + +/* Grouping sections into segments */ + +SECTIONS +{ + . = seg_kcode_base; + seg_kcode : { + *(.giet) + *(.switch) + *(.drivers) + *(.isr) + } + . = seg_kdata_base; + seg_kdata : { + *(.kdata) + } + . = seg_kunc_base; + seg_kunc : { + *(.unckdata) + } + . = seg_kdata_base; + seg_kdata : { + *(.ksave) + } + . = seg_code_base; + seg_code : { + *(.text) + } + . = seg_reset_base; + seg_reset : { + *(.reset) + } + . = seg_data_base; + seg_data : { + *(.rodata) + . = ALIGN(4); + *(.rodata.*) + . = ALIGN(4); + *(.data) + . = ALIGN(4); + *(.sdata) + . = ALIGN(4); + *(.bss) + *(COMMON) + *(.sbss) + } +} + Index: /branches/fault_tolerance/softs/soft_transpose_giet/main.c =================================================================== --- /branches/fault_tolerance/softs/soft_transpose_giet/main.c (revision 724) +++ /branches/fault_tolerance/softs/soft_transpose_giet/main.c (revision 724) @@ -0,0 +1,360 @@ + +#include "hard_config.h" +#include "stdio.h" +#include "limits.h" +#include "../giet_tsar/block_device.h" + +#define NL 128 +#define NP 128 +#define NB_IMAGES 5 + +// Only processor 0 in each cluster access TTY +#define PRINTF(...) ({ if (lpid == 0) { _tty_printf(__VA_ARGS__); } }) + +#define DISPLAY_OK 1 // enable display on frame buffer when non zero +#define CHECK_VERBOSE 1 // display a detailed check on TTY when non zero +#define INSTRUMENTATION_OK 0 // display statistcs on TTY when non zero + +// tricks to read some addresses from ldscript +extern struct plaf seg_ioc_base; +extern struct plaf seg_heap_base; + +// global variables stored in seg_data (cluster 0) + +// instrumentation counters (for each processor) +unsigned int LOAD_START[256][4]; +unsigned int LOAD_END [256][4]; +unsigned int TRSP_START[256][4]; +unsigned int TRSP_END [256][4]; +unsigned int DISP_START[256][4]; +unsigned int DISP_END [256][4]; + +// checksum variables (used by proc(0,0,0) only +unsigned check_line_before[NL]; +unsigned check_line_after[NL]; + +///////////// +void main() +{ + unsigned int image = 0; + + unsigned int l; // line index for loops + unsigned int p; // pixel index for loops + + unsigned int * ioc_address = (unsigned int *) &seg_ioc_base; + unsigned int block_size = ioc_address[BLOCK_DEVICE_BLOCK_SIZE]; + + unsigned int proc_id = _procid(); // processor id + unsigned int nclusters = X_SIZE*Y_SIZE; // number of clusters + unsigned int lpid = proc_id % NB_PROCS_MAX; // local processor id + unsigned int cluster_xy = proc_id / NB_PROCS_MAX; // cluster index (8 bits format) + unsigned int x = cluster_xy >> Y_WIDTH; // x coordinate + unsigned int y = cluster_xy & ((1<>8) & 0x000000FF); + unsigned char byte2 = (unsigned char)((word>>16) & 0x000000FF); + unsigned char byte3 = (unsigned char)((word>>24) & 0x000000FF); + + // compute checksum + check_line_before[l] = check_line_before[l] + byte0 + byte1 + byte2 + byte3; + + // write four bytes with extended address to four remote buffers + dst_cluster = (((p / npix_clusters) / Y_SIZE) << Y_WIDTH) + + ((p / npix_clusters) % Y_SIZE); + dst_index = (p % npix_clusters) * NL + l; + _byte_extended_write( dst_cluster, + (unsigned int)&buf_out[dst_index], + byte0 ); + + dst_cluster = ((((p+1) / npix_clusters) / Y_SIZE) << Y_WIDTH) + + (((p+1) / npix_clusters) % Y_SIZE); + dst_index = ((p+1) % npix_clusters) * NL + l; + _byte_extended_write( dst_cluster, + (unsigned int)&buf_out[dst_index], + byte1 ); + + dst_cluster = ((((p+2) / npix_clusters) / Y_SIZE) << Y_WIDTH) + + (((p+2) / npix_clusters) % Y_SIZE); + dst_index = ((p+2) % npix_clusters) * NL + l; + _byte_extended_write( dst_cluster, + (unsigned int)&buf_out[dst_index], + byte2 ); + + dst_cluster = ((((p+3) / npix_clusters) / Y_SIZE) << Y_WIDTH) + + (((p+3) / npix_clusters) % Y_SIZE); + dst_index = ((p+3) % npix_clusters) * NL + l; + _byte_extended_write( dst_cluster, + (unsigned int)&buf_out[dst_index], + byte3 ); + } + } + + PRINTF("*** proc [%d,%d,0] complete transpose for image %d at cycle %d\n", + x, y, image, _proctime() ); + + TRSP_END[cluster_id][lpid] = _proctime(); + + _barrier_wait(1); + + // optional parallel display from local buf_out to frame buffer + + if ( DISPLAY_OK ) + { + PRINTF("\n*** proc [%d,%d,0] starts display for image %d at cycle %d\n", + x, y, image, _proctime() ); + + DISP_START[cluster_id][lpid] = _proctime(); + + unsigned int npxt = npixels / ntasks; // number of pixels per task + unsigned int buffer = (unsigned int)buf_out + npxt*lpid; + + _fb_sync_write( npxt * task_id, buffer, npxt, cluster_xy ); + + PRINTF("*** Proc [%d,%d,0] completes display for image %d at cycle %d\n", + x, y, image, _proctime() ); + + DISP_END[cluster_id][lpid] = _proctime(); + + _barrier_wait(2); + } + + // checksum (done by processor 0 in each cluster) + + if ( lpid == 0 ) + { + PRINTF("\n*** Proc [%d,%d,0] starts checks for image %d at cycle %d\n\n", + x, y, image, _proctime() ); + + unsigned int success = 1; + unsigned int start = cluster_id * (NL / nclusters); + unsigned int stop = start + (NL / nclusters); + + for ( l = start ; l < stop ; l++ ) + { + check_line_after[l] = 0; + + for ( p = 0 ; p < NP ; p++ ) + { + // read one byte in remote buffer + src_cluster = (((p / npix_clusters) / Y_SIZE) << Y_WIDTH) + + ((p / npix_clusters) % Y_SIZE); + src_index = (p % npix_clusters) * NL + l; + + unsigned char byte = _byte_extended_read( src_cluster, + (unsigned int)&buf_out[src_index] ); + + check_line_after[l] = check_line_after[l] + byte; + } + + if( CHECK_VERBOSE ) + { + PRINTF(" - l = %d / before = %d / after = %d \n", + l, check_line_before[l], check_line_after[l] ); + } + + if ( check_line_before[l] != check_line_after[l] ) success = 0; + } + + if ( success ) PRINTF("\n*** proc [%d,%d,0] : CHECKSUM OK \n\n", x, y); + else PRINTF("\n*** proc [%d,%d,0] : CHECKSUM KO \n\n", x, y); + } + + // instrumentation ( done by processor [0,0,0] + + if ( (proc_id == 0) && INSTRUMENTATION_OK ) + { + int cc, pp; + unsigned int min_load_start = INT_MAX; + unsigned int max_load_start = 0; + unsigned int min_load_ended = INT_MAX; + unsigned int max_load_ended = 0; + unsigned int min_trsp_start = INT_MAX; + unsigned int max_trsp_start = 0; + unsigned int min_trsp_ended = INT_MAX; + unsigned int max_trsp_ended = 0; + unsigned int min_disp_start = INT_MAX; + unsigned int max_disp_start = 0; + unsigned int min_disp_ended = INT_MAX; + unsigned int max_disp_ended = 0; + + for (cc = 0; cc < nclusters; cc++) + { + for (pp = 0; pp < NB_PROCS_MAX; pp++) + { + if (LOAD_START[cc][pp] < min_load_start) min_load_start = LOAD_START[cc][pp]; + if (LOAD_START[cc][pp] > max_load_start) max_load_start = LOAD_START[cc][pp]; + if (LOAD_END[cc][pp] < min_load_ended) min_load_ended = LOAD_END[cc][pp]; + if (LOAD_END[cc][pp] > max_load_ended) max_load_ended = LOAD_END[cc][pp]; + if (TRSP_START[cc][pp] < min_trsp_start) min_trsp_start = TRSP_START[cc][pp]; + if (TRSP_START[cc][pp] > max_trsp_start) max_trsp_start = TRSP_START[cc][pp]; + if (TRSP_END[cc][pp] < min_trsp_ended) min_trsp_ended = TRSP_END[cc][pp]; + if (TRSP_END[cc][pp] > max_trsp_ended) max_trsp_ended = TRSP_END[cc][pp]; + if (DISP_START[cc][pp] < min_disp_start) min_disp_start = DISP_START[cc][pp]; + if (DISP_START[cc][pp] > max_disp_start) max_disp_start = DISP_START[cc][pp]; + if (DISP_END[cc][pp] < min_disp_ended) min_disp_ended = DISP_END[cc][pp]; + if (DISP_END[cc][pp] > max_disp_ended) max_disp_ended = DISP_END[cc][pp]; + } + } + + PRINTF(" - LOAD_START : min = %d / max = %d / med = %d / delta = %d\n", + min_load_start, max_load_start, (min_load_start+max_load_start)/2, + max_load_start-min_load_start); + + PRINTF(" - LOAD_END : min = %d / max = %d / med = %d / delta = %d\n", + min_load_ended, max_load_ended, (min_load_ended+max_load_ended)/2, + max_load_ended-min_load_ended); + + PRINTF(" - TRSP_START : min = %d / max = %d / med = %d / delta = %d\n", + min_trsp_start, max_trsp_start, (min_trsp_start+max_trsp_start)/2, + max_trsp_start-min_trsp_start); + + PRINTF(" - TRSP_END : min = %d / max = %d / med = %d / delta = %d\n", + min_trsp_ended, max_trsp_ended, (min_trsp_ended+max_trsp_ended)/2, + max_trsp_ended-min_trsp_ended); + + PRINTF(" - DISP_START : min = %d / max = %d / med = %d / delta = %d\n", + min_disp_start, max_disp_start, (min_disp_start+max_disp_start)/2, + max_disp_start-min_disp_start); + + PRINTF(" - DISP_END : min = %d / max = %d / med = %d / delta = %d\n", + min_disp_ended, max_disp_ended, (min_disp_ended+max_disp_ended)/2, + max_disp_ended-min_disp_ended); + } + + image++; + + _barrier_wait( 3 ); + } // end while image + + + _exit(); + +} // end main() + +// Local Variables: +// tab-width: 3 +// c-basic-offset: 3 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 + + + Index: /branches/fault_tolerance/softs/test_llsc/Makefile =================================================================== --- /branches/fault_tolerance/softs/test_llsc/Makefile (revision 724) +++ /branches/fault_tolerance/softs/test_llsc/Makefile (revision 724) @@ -0,0 +1,6 @@ +simul.x: top.cpp top.desc + soclib-cc -P -p top.desc -I. -o simul.x + +clean: + soclib-cc -x -p top.desc -I. + rm -rf *.o *.x term* Index: /branches/fault_tolerance/softs/test_llsc/README =================================================================== --- /branches/fault_tolerance/softs/test_llsc/README (revision 724) +++ /branches/fault_tolerance/softs/test_llsc/README (revision 724) @@ -0,0 +1,11 @@ + +This directory contains a script aiming at using intensively the LL/SC table, making a lot of concurrent increments on some shared variables. + +For each test generated, a sequential native version is made and executed, so as to have a reference result of the test. It is then diff'ed with the output of the simulated version. + +The main script to execute is run_simus.sh in the scripts/ directory. Some of its parameters can be set inside it (e.g. the number of processors). + +The sub-directory LLSCTestGenerator contains the tool which generates the source files (1 for native sequential execution, 2 for simulated execution). + +The simulated application is compiled using DSX-VM. + Index: /branches/fault_tolerance/softs/test_llsc/scripts/LLSCTestGenerator/Genere_Tests.cpp =================================================================== --- /branches/fault_tolerance/softs/test_llsc/scripts/LLSCTestGenerator/Genere_Tests.cpp (revision 724) +++ /branches/fault_tolerance/softs/test_llsc/scripts/LLSCTestGenerator/Genere_Tests.cpp (revision 724) @@ -0,0 +1,58 @@ +/* + * Outil pour la génération de test de la table LL/SC + * @Author QM + */ + +#include "Program.hpp" +#include "config.h" + +#include +#include +#include +#include + +int main(int argc, char** argv){ + + if (argc != 9){ + printf("usage: genere_test \n"); + exit(1); + } + + srand(time(NULL)); + + FILE * native_file; + FILE * main_task_file; + FILE * task_no_tty_file; + + native_file = fopen(argv[6], "w"); + main_task_file = fopen(argv[7], "w"); + task_no_tty_file = fopen(argv[8], "w"); + + const int nb_procs = atoi(argv[1]); + const int nb_max_incr = atoi(argv[2]); + const int nb_locks = atoi(argv[3]); + + const bool lock_horizontal = atoi(argv[4]); + const bool vars_horizontal = atoi(argv[5]); + + const int line_size = LINE_SIZE; + + Program prog(nb_procs, nb_locks, nb_max_incr, line_size, lock_horizontal, vars_horizontal); + + string s = prog.write_output(); + fprintf(native_file, "%s", s.c_str()); + fclose(native_file); + + s = prog.write_main_task(); + fprintf(main_task_file, "%s", s.c_str()); + fclose(main_task_file); + + s = prog.write_task_no_tty(); + fprintf(task_no_tty_file, "%s", s.c_str()); + fclose(task_no_tty_file); + + return 0; +} + + + Index: /branches/fault_tolerance/softs/test_llsc/scripts/LLSCTestGenerator/Increment.hpp =================================================================== --- /branches/fault_tolerance/softs/test_llsc/scripts/LLSCTestGenerator/Increment.hpp (revision 724) +++ /branches/fault_tolerance/softs/test_llsc/scripts/LLSCTestGenerator/Increment.hpp (revision 724) @@ -0,0 +1,53 @@ + +#ifndef _increment_hpp_ +#define _increment_hpp_ + + +#include +#include +#include +#include + +#include "functions.h" + +using namespace std; + +class Increment { + int lock_index; + int var_index; + int line_size; + + public: + + Increment(int nb_locks, int line_size, bool lock_in_line, bool vars_in_line){ + this->line_size = line_size; + + int index = randint(0, nb_locks - 1); + int lock_size = (lock_in_line ? ceil((float) nb_locks / line_size) * line_size : nb_locks * line_size); + + lock_index = (lock_in_line ? index : index * line_size); + var_index = (vars_in_line ? lock_size + index : lock_size + index * line_size); + } + + ~Increment() {} + + string write_output() { + stringstream res; + res << " tab[" << var_index << "]++;" << endl; + + return res.str(); + } + + string write_task() { + stringstream res; + res << " take_lock(&tab[" << lock_index << "]);" << endl; + res << " tab[" << var_index << "]++;" << endl; + res << " release_lock(&tab[" << lock_index << "]);" << endl; + + return res.str(); + } + +}; + +#endif + Index: /branches/fault_tolerance/softs/test_llsc/scripts/LLSCTestGenerator/Makefile =================================================================== --- /branches/fault_tolerance/softs/test_llsc/scripts/LLSCTestGenerator/Makefile (revision 724) +++ /branches/fault_tolerance/softs/test_llsc/scripts/LLSCTestGenerator/Makefile (revision 724) @@ -0,0 +1,11 @@ + +HPP_FILES = $(wildcard *.hpp) + + +all: generate_test + +generate_test: Genere_Tests.cpp $(HPP_FILES) config.h + g++ -o $@ $< + +clean: + rm -f generate_test Index: /branches/fault_tolerance/softs/test_llsc/scripts/LLSCTestGenerator/Program.hpp =================================================================== --- /branches/fault_tolerance/softs/test_llsc/scripts/LLSCTestGenerator/Program.hpp (revision 724) +++ /branches/fault_tolerance/softs/test_llsc/scripts/LLSCTestGenerator/Program.hpp (revision 724) @@ -0,0 +1,261 @@ + +#ifndef _program_hpp_ +#define _program_hpp_ + +#include +#include +#include + +#include "config.h" +#include "TestThread.hpp" + + +using namespace std; + +class Program { + + int nb_threads; + int nb_max_incr; + int nb_locks; + int nb_vars; + int line_size; + bool lock_in_line, vars_in_line; + int tab_size; + TestThread ** threads; + + public: + + Program(int nb_procs, int nb_locks, int nb_max_accesses, int line_size, bool lock_in_line, bool vars_in_line){ + this->nb_threads = nb_procs; + this->nb_max_incr = nb_max_accesses; + this->nb_locks = nb_locks; + this->nb_vars = nb_locks; + this->line_size = line_size; + this->lock_in_line = lock_in_line; + this->vars_in_line = vars_in_line; + this->tab_size = (lock_in_line ? ceil((float) nb_locks / line_size) * line_size : nb_locks * line_size) + (vars_in_line ? ceil((float) nb_vars / line_size) * line_size : nb_vars * line_size); + this->threads = new TestThread * [nb_threads]; + + for (int i = 0; i < nb_threads; i++){ + threads[i] = new TestThread(nb_locks, nb_max_accesses, line_size, lock_in_line, vars_in_line, i); + } + } + + ~Program(){ + for (int i = 0; i < nb_threads; i++){ + delete threads[i]; + } + delete [] threads; + } + + + string write_main_task() { + stringstream res; + res << "#include \"srl.h\"" << endl; + res << "#include \"stdio.h\"" << endl; + res << "#include \"test_llsc_main_proto.h\"" << endl; + res << "#include \"functions.h\"" << endl; + res << endl; + res << "/*" << endl; + res << " * Test generated for a dsx_vm compilation" << endl; + res << " * NB_LOCKS : " << nb_locks << endl; + res << " * NB_VARS : " << nb_vars << endl; + if (lock_in_line) { + res << " * LOCKS PLACEMENT : horizontal" << endl; + } + else { + res << " * LOCKS PLACEMENT : vertical" << endl; + } + if (vars_in_line) { + res << " * VARS PLACEMENT : horizontal" << endl; + } + else { + res << " * VARS PLACEMENT : vertical" << endl; + } + res << " * NB_MAX_INCRS : " << nb_max_incr << endl; + res << " * LINE_SIZE : " << LINE_SIZE << endl; + res << " */" << endl; + res << endl; + res << "int * tab;" << endl; + res << endl; + res << threads[0]->write_task(); + res << endl; + res << endl; + res << "FUNC(test_llsc_main_func) {" << endl; + res << endl; + res << " int i;" << endl; + res << endl; + res << " srl_memspace_t memspace = SRL_GET_MEMSPACE(table);" << endl; + res << " tab = (int *) SRL_MEMSPACE_ADDR(memspace);" << endl; + res << " srl_barrier_t barrier = SRL_GET_BARRIER(barrier);" << endl; + res << " srl_barrier_t barrier2 = SRL_GET_BARRIER(barrier2);" << endl; + res << endl; + res << " // Initialisation du tableau" << endl; + res << " for (i = 0; i < " << tab_size << "; i++) {" << endl; + res << " tab[i] = 0;" << endl; + res << " }" << endl; + res << endl; + res << " barrier_wait(barrier);" << endl; + res << endl; + res << " run0();" << endl; + res << endl; + res << " barrier_wait(barrier2);" << endl; + res << endl; + res << " for (i = 0; i < " << tab_size << "; i++) {" << endl; + res << " if (tab[i] != 0) {" << endl; + res << " giet_tty_printf(\"tab[%d] final : %d\\n\", i, tab[i]);" << endl; + res << " }" << endl; + res << " }" << endl; + res << endl; + res << " giet_raise_sigint();" << endl; + res << endl; + res << " srl_exit();" << endl; + res << "}" << endl; + res << endl; + + return res.str(); + } + + + string write_task_no_tty() { + stringstream res; + res << "#include \"srl.h\"" << endl; + res << "#include \"stdio.h\"" << endl; + res << "#include \"test_llsc_no_tty_proto.h\"" << endl; + res << "#include \"functions.h\"" << endl; + res << endl; + res << "/*" << endl; + res << " * Test generated for a dsx_vm compilation" << endl; + res << " * NB_LOCKS : " << nb_locks << endl; + res << " * NB_VARS : " << nb_vars << endl; + if (lock_in_line) { + res << " * LOCKS PLACEMENT : horizontal" << endl; + } + else { + res << " * LOCKS PLACEMENT : vertical" << endl; + } + if (vars_in_line) { + res << " * VARS PLACEMENT : horizontal" << endl; + } + else { + res << " * VARS PLACEMENT : vertical" << endl; + } + res << " * NB_MAX_INCRS : " << nb_max_incr << endl; + res << " * LINE_SIZE : " << LINE_SIZE << endl; + res << " */" << endl; + res << endl; + res << "int * tab;" << endl; + res << endl; + + for (int i = 1; i < nb_threads; i++) { + res << threads[i]->write_task(); + } + + res << endl; + res << endl; + res << "FUNC(test_llsc_no_tty_func) {" << endl; + res << endl; + res << " srl_memspace_t memspace = SRL_GET_MEMSPACE(table);" << endl; + res << " tab = (int *) SRL_MEMSPACE_ADDR(memspace);" << endl; + res << " srl_barrier_t barrier = SRL_GET_BARRIER(barrier);" << endl; + res << " srl_barrier_t barrier2 = SRL_GET_BARRIER(barrier2);" << endl; + res << " int thread_id = SRL_GET_CONST(id);" << endl; + res << endl; + res << " barrier_wait(barrier);" << endl; + res << endl; + res << " if (thread_id == 1) {" << endl; + res << " run1();" << endl; + res << " }" << endl; + for (int i = 2; i < nb_threads; i++) { + res << " else if (thread_id == " << i << ") {" << endl; + res << " run" << i << "();" << endl; + res << " }" << endl; + } + res << " else {" << endl; + res << " srl_assert(0);" << endl; + res << " }" << endl; + res << endl; + res << " barrier_wait(barrier2);" << endl; + res << endl; + res << " srl_exit();" << endl; + res << endl; + res << "}" << endl; + res << endl; + + return res.str(); + } + + + string write_output() { + cout << tab_size; + stringstream res; + res << endl; + res << "#include " << endl; + res << "#include " << endl; + res << endl; + res << "/*" << endl; + res << " * Test generated for a posix execution" << endl; + res << " * NB_LOCKS : " << nb_locks << endl; + res << " * NB_VARS : " << nb_vars << endl; + if (lock_in_line) { + res << " * LOCKS PLACEMENT : horizontal" << endl; + } + else { + res << " * LOCKS PLACEMENT : vertical" << endl; + } + if (vars_in_line) { + res << " * VARS PLACEMENT : horizontal" << endl; + } + else { + res << " * VARS PLACEMENT : vertical" << endl; + } + res << " * NB_MAX_INCRS : " << nb_max_incr << endl; + res << " * LINE_SIZE : " << LINE_SIZE << endl; + res << " */" << endl; + res << endl; + res << "volatile int tab[" << tab_size << "];" << endl; + res << endl; + res << endl; + + + for (int i = 0; i < nb_threads; i++) { + res << threads[i]->write_output(); + } + + res << "int main() {" << endl; + res << endl; + res << " int i;" << endl; + res << endl; + res << " /* Version native séquentielle */" << endl; + res << endl; + res << " // Initialisation du tableau" << endl; + res << " for (i = 0; i < " << tab_size << "; i++) {" << endl; + res << " tab[i] = 0;" << endl; + res << " }" << endl; + res << endl; + res << " run0();" << endl; + for (int i = 1; i < nb_threads; i++){ + res << " run" << i << "();" << endl; + } + res << endl; + res << " for (i = 0; i < " << tab_size << "; i++) {" << endl; + res << " if (tab[i] != 0) {" << endl; + res << " printf(\"tab[%d] final : %d\\n\", i, tab[i]);" << endl; + res << " }" << endl; + res << " }" << endl; + res << endl; + res << " return 0;" << endl; + res << "}" << endl; + res << endl; + + return res.str(); + } + +}; + +#endif + + + + + Index: /branches/fault_tolerance/softs/test_llsc/scripts/LLSCTestGenerator/TestThread.hpp =================================================================== --- /branches/fault_tolerance/softs/test_llsc/scripts/LLSCTestGenerator/TestThread.hpp (revision 724) +++ /branches/fault_tolerance/softs/test_llsc/scripts/LLSCTestGenerator/TestThread.hpp (revision 724) @@ -0,0 +1,70 @@ + +#ifndef _testthread_hpp_ +#define _testthread_hpp_ + +#include +#include +#include + +#include "Increment.hpp" + +using namespace std; + +class TestThread { + + int proc_id; + std::list requests; + + public: + + TestThread(int nb_locks, int nb_max_accesses, int line_size, bool lock_in_line, bool vars_in_line, int proc_id) { + this->proc_id = proc_id; + const int nb_accesses = randint(1, nb_max_accesses); + for (int i = 0; i < nb_accesses; i++) { + Increment * t; + t = new Increment(nb_locks, line_size, lock_in_line, vars_in_line); + requests.push_back(t); + } + } + + ~TestThread() { + std::list::iterator it; + for (it = requests.begin(); it != requests.end(); it++) { + delete (*it); + } + requests.clear(); + } + + string write_output() { + stringstream res; + res << "void run" << proc_id << "() {" << endl; + + std::list::iterator it; + for (it = requests.begin(); it != requests.end(); it++) { + res << (*it)->write_output(); + } + + res << "}" << endl; + res << endl; + + return res.str(); + } + + + string write_task() { + stringstream res; + res << "__attribute__((constructor)) void run" << proc_id << "() {" << endl; + + std::list::iterator it; + for (it = requests.begin(); it != requests.end(); it++) { + res << (*it)->write_task(); + } + + res << "}" << endl; + res << endl; + + return res.str(); + } +}; + +#endif Index: /branches/fault_tolerance/softs/test_llsc/scripts/LLSCTestGenerator/config.h =================================================================== --- /branches/fault_tolerance/softs/test_llsc/scripts/LLSCTestGenerator/config.h (revision 724) +++ /branches/fault_tolerance/softs/test_llsc/scripts/LLSCTestGenerator/config.h (revision 724) @@ -0,0 +1,8 @@ + +#ifndef _CONFIG_H_ +#define _CONFIG_H_ + +#define LINE_SIZE 16 + +#endif + Index: /branches/fault_tolerance/softs/test_llsc/scripts/LLSCTestGenerator/functions.h =================================================================== --- /branches/fault_tolerance/softs/test_llsc/scripts/LLSCTestGenerator/functions.h (revision 724) +++ /branches/fault_tolerance/softs/test_llsc/scripts/LLSCTestGenerator/functions.h (revision 724) @@ -0,0 +1,43 @@ + +#ifndef _functions_h_ +#define _functions_h_ + +#include +#include +#include + +static int mylog2(size_t v) { + static const size_t b[] = { 0x2, 0xC, 0xF0, 0xFF00, 0xFFFF0000 }; + static const size_t S[] = { 1, 2, 4, 8, 16 }; + int i; + register size_t r = 0; + for (i = 4; i >= 0; i--) { + if (v & b[i]) { + v >>= S[i]; + r |= S[i]; + } + } + return r + 1; +} + +/*int randint(int a,int b){ + int range = b - a + 1; + int length = (int) ceil(log2(range)); + int mask = (int) pow(2,length) - 1; + printf("mask : %d\n",mask); + int res; + do { + res = rand() & mask; + } + while (res >= range); + return (res + a); +}*/ + +int randint(int a, int b){ + int range = b - a + 1; + int res = rand() % range; + return res + a; +} + + +#endif Index: /branches/fault_tolerance/softs/test_llsc/scripts/Makefile.nat =================================================================== --- /branches/fault_tolerance/softs/test_llsc/scripts/Makefile.nat (revision 724) +++ /branches/fault_tolerance/softs/test_llsc/scripts/Makefile.nat (revision 724) @@ -0,0 +1,6 @@ + +all: test_natif + +test_natif: test_llsc.c + gcc -o $@ $< + Index: /branches/fault_tolerance/softs/test_llsc/scripts/functions.c =================================================================== --- /branches/fault_tolerance/softs/test_llsc/scripts/functions.c (revision 724) +++ /branches/fault_tolerance/softs/test_llsc/scripts/functions.c (revision 724) @@ -0,0 +1,29 @@ + +#include "functions.h" + +void take_lock(volatile int * plock) { + volatile int * _plock = plock; + __asm__ __volatile__ ( + "move $16, %0 \n" + "giet_lock_try : \n" + "lw $2, 0($16) \n" + "ll $2, 0($16) \n" + "bnez $2, giet_lock_try \n" + "li $3, 1 \n" + "sc $3, 0($16) \n" + "beqz $3, giet_lock_try \n" + "nop \n" + "giet_lock_ok: \n" + "nop \n" + : + :"r" (_plock) + :"$2", "$3", "$4", "$16"); +} + + +void release_lock(volatile int * plock) { + asm volatile("\tsync\n"); + *plock = 0; +} + + Index: /branches/fault_tolerance/softs/test_llsc/scripts/functions.h =================================================================== --- /branches/fault_tolerance/softs/test_llsc/scripts/functions.h (revision 724) +++ /branches/fault_tolerance/softs/test_llsc/scripts/functions.h (revision 724) @@ -0,0 +1,8 @@ +#ifndef _FUNCTIONS_H_ +#define _FUNCTIONS_H_ + + +void take_lock(volatile int * plock); +void release_lock(volatile int * plock); + +#endif Index: /branches/fault_tolerance/softs/test_llsc/scripts/run_simus.py =================================================================== --- /branches/fault_tolerance/softs/test_llsc/scripts/run_simus.py (revision 724) +++ /branches/fault_tolerance/softs/test_llsc/scripts/run_simus.py (revision 724) @@ -0,0 +1,121 @@ +#!/usr/bin/python + +import subprocess +import os +import random + +data_dir = 'data' +gen_dir = 'generated' +test_gen_tool_dir = 'LLSCTestGenerator' + +test_gen_binary = 'generate_test' + +log_init_name = 'log_init_' +log_term_name = 'log_term_' + +generated_test = 'test_llsc.c' +main_task = 'test_llsc_main.c' +task_no_tty = 'test_llsc_no_tty.c' + +res_natif = 'res_natif.txt' + +# Parametres des tests +nb_locks = 20 +nb_max_incr = 2000 +nb_procs = 64 + + +os.chdir(os.path.dirname(__file__)) + +scripts_path = os.path.abspath(".") +top_path = os.path.abspath("../") + +topcell_name = "top.cpp" + + +random.seed() + + +def get_x_y(nb_procs): + x = 1 + y = 1 + to_x = True + while (x * y * 4 < nb_procs): + if to_x: + x = x * 2 + else: + y = y * 2 + to_x = not to_x + return x, y + + +print "make -C", test_gen_tool_dir +subprocess.call([ 'make', '-C', test_gen_tool_dir ]) + +print "cp", os.path.join(test_gen_tool_dir, test_gen_binary), os.path.join(scripts_path, test_gen_binary) +subprocess.call([ 'cp', os.path.join(test_gen_tool_dir, test_gen_binary), os.path.join(scripts_path, test_gen_binary)]) + +print "mkdir -p", os.path.join(scripts_path, data_dir) +subprocess.call([ 'mkdir', '-p', os.path.join(scripts_path, data_dir) ]) + +while True: + x, y = get_x_y(nb_procs) + + b0 = random.randint(0, 1) + b1 = random.randint(0, 1) + + print test_gen_binary, nb_procs, nb_max_incr, nb_locks, b0, b1, generated_test, main_task, task_no_tty + tab_size = subprocess.Popen([ os.path.join(scripts_path, test_gen_binary), str(nb_procs), str(nb_max_incr), str(nb_locks), str(b0), str(b1), generated_test, main_task, task_no_tty ], stdout = subprocess.PIPE).communicate()[0] + + print "make -f Makefile.nat" + subprocess.call([ 'make', '-f', 'Makefile.nat' ]) + + print "./test_natif >", os.path.join(data_dir, res_natif) + output = subprocess.Popen([ './test_natif' ], stdout = subprocess.PIPE).communicate()[0] + file = open(os.path.join(data_dir, res_natif), 'w') + file.write(output) + file.close() + + print "./test_llsc.py", str(x), str(y), tab_size + subprocess.call([ './test_llsc.py', str(x), str(y), tab_size ]) + + print "cd", top_path + os.chdir(top_path) + print "touch", topcell_name + subprocess.call([ 'touch', topcell_name ]) + print "make" + subprocess.call([ 'make' ]) + + # Launch simulation + print "./simul.x >", os.path.join(scripts_path, data_dir, log_init_name + str(nb_procs)) + output = subprocess.Popen([ './simul.x' ], stdout = subprocess.PIPE).communicate()[0] + + # Write simulation results to data directory + print "cd", scripts_path + os.chdir(scripts_path) + filename = os.path.join(data_dir, log_init_name + str(nb_procs)) + file = open(filename, 'w') + file.write(output) + file.close() + + term_filename = os.path.join(scripts_path, data_dir, log_term_name + str(nb_procs)) + print "mv", os.path.join(top_path, 'term1'), term_filename + subprocess.call([ 'mv', os.path.join(top_path, 'term1'), term_filename ]) + + # Quit if results obtained by simulation are incorrect + print "diff", term_filename, os.path.join(data_dir, res_natif) + output = subprocess.Popen([ 'diff', term_filename, os.path.join(data_dir, res_natif) ], stdout = subprocess.PIPE).communicate()[0] + if output != "": + break; + + +## Enf of simulations + + + + + + + + + Index: /branches/fault_tolerance/softs/test_llsc/scripts/test_llsc.py =================================================================== --- /branches/fault_tolerance/softs/test_llsc/scripts/test_llsc.py (revision 724) +++ /branches/fault_tolerance/softs/test_llsc/scripts/test_llsc.py (revision 724) @@ -0,0 +1,108 @@ +#!/usr/bin/env python + +import sys +import dsx +from tsarch import TSArch +from dsx.mapper.mapper import Mapper +from dsx import * + + + +if len(sys.argv) < 4 or sys.argv[1] == '' or sys.argv[2] == '': + print "Usage: ", sys.argv[0], " " + exit() + +cluster_x = int(sys.argv[1]) +cluster_y = int(sys.argv[2]) +memspace_size = int(sys.argv[3]) * 4 + +nb_procs = 4 +nb_total_procs = nb_procs * cluster_x * cluster_y + +hd = TSArch(cluster_x = cluster_x, cluster_y = cluster_y, nb_proc = nb_procs, nb_tty = 4) + +test_llsc = TaskModel( + 'test_llsc_main', + ports = { + 'table': MemspacePort(), + 'barrier': BarrierPort(), + 'barrier2': BarrierPort(), + }, + impls = [ + SwTask('test_llsc_main_func', + stack_size = 2048, + sources = ['test_llsc_main.c', 'functions.c'], + headers = ['functions.h'], + defines = []) + ], + uses = ['tty'] + ) + + +test_llsc_no_tty = TaskModel( + 'test_llsc_no_tty', + ports = { + 'table': MemspacePort(), + 'barrier': BarrierPort(), + 'barrier2': BarrierPort(), + 'id' : ConstPort(), + }, + impls = [ + SwTask('test_llsc_no_tty_func', + stack_size = 2048, + sources = ['test_llsc_no_tty.c', 'functions.c'], + headers = ['functions.h'], + defines = []) + ], + ) + + +barrier = Barrier('barrier') +barrier2 = Barrier('barrier2') +memspace = Memspace('memspace', memspace_size) + +tasks = () + + +tasks += Task('task_llsc_main', 'test_llsc_main', + { + 'table' : memspace, + 'barrier' : barrier, + 'barrier2' : barrier2, + }, + defines = {} ), + + +for i in range(1, nb_total_procs): + tasks += Task('task_llsc_no_tty_%d' % i, 'test_llsc_no_tty', + { + 'table' : memspace, + 'barrier' : barrier, + 'barrier2' : barrier2, + 'id' : i, + }, + defines = {} ), + +tcg = dsx.Tcg('test_llsc', *tasks) + +mpr = Mapper(hd, tcg) + +mpr.map('task_llsc_main', cluster = 0, proc = 0, stack = "PSEG_RAM_0") + +for i in range(1, nb_total_procs): + #print "cluster = %d - proc = %d" % (int(i) / 4, i % 4) + mpr.map('task_llsc_no_tty_%d' % i, cluster = int(i) / 4, proc = int(i) % 4, stack = "PSEG_RAM_%d" % (int(i) / 4)) + +for const in tcg.nodesOfType('const'): + mpr.map(const, pseg = 'PSEG_RAM_0') + + +mpr.map('memspace', pseg = "PSEG_RAM_0") +mpr.map('barrier', pseg = "PSEG_RAM_0") +mpr.map('barrier2', pseg = "PSEG_RAM_0") + +mpr.map(tcg, code = 'PSEG_RAM_0', data = 'PSEG_RAM_0', ptab = "PSEG_RAM_0") +mpr.map('system', boot = 'PSEG_RAM_0', kernel = 'PSEG_RAM_0', scheduler = True) + +mpr.generate(dsx.Giet(outdir = '.', vaddr_replicated_peri_inc = 0x2000, debug = False)) + Index: /branches/fault_tolerance/softs/test_llsc/scripts/tsarch.py =================================================================== --- /branches/fault_tolerance/softs/test_llsc/scripts/tsarch.py (revision 724) +++ /branches/fault_tolerance/softs/test_llsc/scripts/tsarch.py (revision 724) @@ -0,0 +1,41 @@ +#!/usr/bin/env python + +from dsx.hard.hard import * + + +def TSArch(cluster_x, cluster_y, nb_proc = 1, nb_tty = 8, wcoproc = False): + + nb_cluster = cluster_x * cluster_y + + hd = Hardware(cluster_x, cluster_y , addr_size = 40, nb_proc = nb_proc, ccoherence = True) #nb_proc : proc by cluster + + + ######### peripherals ########## + hd.add(Tty('PSEG_TTY', pbase = 0xB4000000, channel_size = 16, nb_channel = nb_tty)) + hd.add(Fbf('PSEG_FBF', pbase = 0xB2000000, channel_size = 352 * 288 * 2, nb_channel = 1)) + hd.add(Ioc('PSEG_IOC', pbase = 0xB3000000, channel_size = 32, nb_channel = 1)) + hd.add(SimH('PSEG_SIMH', pbase = 0xB7000000, channel_size = 32, nb_channel = 1)) # 6 mapped registers + + hd.add(Xicu('PSEG_XICU', pbase = 0xB0000000, channel_size = 32, nb_channel = nb_proc, replicated = True)) # name suffixed with "_" + hd.add(Dma('PSEG_DMA', pbase = 0xB1000000, channel_size = 32, nb_channel = nb_proc, replicated = True)) + + ############## MEMORY ########### + for cl in range(nb_cluster): + hd.add(RAM('PSEG_RAM_%d'%cl, pbase = 0x00000000 + (cl * hd.cluster_span), size = 0x00C00000)) + + ############## IRQ ############ + hd.add(Irq(cluster_id = 0, proc_id = 0, icu_irq_id = 31, peri = Ioc, channel_id = 0)) + for j in range(16, 31): + hd.add(Irq(cluster_id = 0, proc_id = 0, icu_irq_id = j, peri = Tty, channel_id = j - 16)) + + for cl in range(nb_cluster): + for p in xrange(nb_proc): + hd.add(Irq(cluster_id = cl, proc_id = p, icu_irq_id = p + 8, peri = Dma, channel_id = p)) + hd.add(Irq(cluster_id = cl, proc_id = p, icu_irq_id = p, peri = Xicu, channel_id = p)) + + + ############# ROM ############ + hd.add(ROM("PSEG_ROM", pbase = 0xbfc00000, size = 0x00100000)) + + return hd + Index: /branches/fault_tolerance/softs/test_llsc/top.cpp =================================================================== --- /branches/fault_tolerance/softs/test_llsc/top.cpp (revision 724) +++ /branches/fault_tolerance/softs/test_llsc/top.cpp (revision 724) @@ -0,0 +1,1049 @@ +///////////////////////////////////////////////////////////////////////// +// File: top.cpp +// Author: Alain Greiner +// Copyright: UPMC/LIP6 +// Date : may 2013 +// This program is released under the GNU public license +///////////////////////////////////////////////////////////////////////// +// This file define a generic TSAR architecture. +// The physical address space is 40 bits. +// +// The number of clusters cannot be larger than 256. +// The number of processors per cluster cannot be larger than 8. +// +// - It uses four dspin_local_crossbar per cluster as local interconnect +// - It uses two virtual_dspin routers per cluster as global interconnect +// - It uses the vci_cc_vcache_wrapper +// - It uses the vci_mem_cache +// - It contains one vci_xicu per cluster. +// - It contains one vci_multi_dma per cluster. +// - It contains one vci_simple_ram per cluster to model the L3 cache. +// +// The communication between the MemCache and the Xram is 64 bits. +// +// All clusters are identical, but the cluster 0 (called io_cluster), +// contains 6 extra components: +// - the boot rom (BROM) +// - the disk controller (BDEV) +// - the multi-channel network controller (MNIC) +// - the multi-channel chained buffer dma controller (CDMA) +// - the multi-channel tty controller (MTTY) +// - the frame buffer controller (FBUF) +// +// It is build with one single component implementing a cluster, +// defined in files tsar_xbar_cluster.* (with * = cpp, h, sd) +// +// The IRQs are connected to XICUs as follow: +// - The IRQ_IN[0] to IRQ_IN[7] ports are not used in all clusters. +// - The DMA IRQs are connected to IRQ_IN[8] to IRQ_IN[15] in all clusters. +// - The TTY IRQs are connected to IRQ_IN[16] to IRQ_IN[30] in I/O cluster. +// - The BDEV IRQ is connected to IRQ_IN[31] in I/O cluster. +// +// Some hardware parameters are used when compiling the OS, and are used +// by this top.cpp file. They must be defined in the hard_config.h file : +// - CLUSTER_X : number of clusters in a row (power of 2) +// - CLUSTER_Y : number of clusters in a column (power of 2) +// - CLUSTER_SIZE : size of the segment allocated to a cluster +// - NB_PROCS_MAX : number of processors per cluster (power of 2) +// - NB_DMA_CHANNELS : number of DMA channels per cluster (< 9) +// - NB_TTY_CHANNELS : number of TTY channels in I/O cluster (< 16) +// - NB_NIC_CHANNELS : number of NIC channels in I/O cluster (< 9) +// +// Some other hardware parameters are not used when compiling the OS, +// and can be directly defined in this top.cpp file: +// - XRAM_LATENCY : external ram latency +// - MEMC_WAYS : L2 cache number of ways +// - MEMC_SETS : L2 cache number of sets +// - L1_IWAYS +// - L1_ISETS +// - L1_DWAYS +// - L1_DSETS +// - FBUF_X_SIZE : width of frame buffer (pixels) +// - FBUF_Y_SIZE : heigth of frame buffer (lines) +// - BDEV_SECTOR_SIZE : block size for block drvice +// - BDEV_IMAGE_NAME : file pathname for block device +// - NIC_RX_NAME : file pathname for NIC received packets +// - NIC_TX_NAME : file pathname for NIC transmited packets +// - NIC_TIMEOUT : max number of cycles before closing a container +///////////////////////////////////////////////////////////////////////// +// General policy for 40 bits physical address decoding: +// All physical segments base addresses are multiple of 1 Mbytes +// (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) +// The (x_width + y_width) MSB bits (left aligned) define +// the cluster index, and the LADR bits define the local index: +// | X_ID | Y_ID |---| LADR | OFFSET | +// |x_width|y_width|---| 8 | 24 | +///////////////////////////////////////////////////////////////////////// +// General policy for 14 bits SRCID decoding: +// Each component is identified by (x_id, y_id, l_id) tuple. +// | X_ID | Y_ID |---| L_ID | +// |x_width|y_width|---| 6 | +///////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include +#include +#include +#include + +#include "gdbserver.h" +#include "mapping_table.h" +#include "tsar_xbar_cluster.h" +#include "alloc_elems.h" + +/////////////////////////////////////////////////// +// OS +/////////////////////////////////////////////////// + +//#define USE_ALMOS +#define USE_GIET + +#ifdef USE_ALMOS +#ifdef USE_GIET +#error "Can't use Two different OS" +#endif +#endif + +#ifndef USE_ALMOS +#ifndef USE_GIET +#error "You need to specify one OS" +#endif +#endif + +/////////////////////////////////////////////////// +// Parallelisation +/////////////////////////////////////////////////// +#define USE_OPENMP 0 + +#if USE_OPENMP +#include +#endif + +// cluster index (computed from x,y coordinates) +#define cluster(x,y) (y + YMAX * x) + +#define min(x, y) (x < y ? x : y) + +/////////////////////////////////////////////////////////// +// DSPIN parameters +/////////////////////////////////////////////////////////// + +#define dspin_cmd_width 39 +#define dspin_rsp_width 32 + +/////////////////////////////////////////////////////////// +// VCI parameters +/////////////////////////////////////////////////////////// + +#define vci_cell_width_int 4 +#define vci_cell_width_ext 8 + +#ifdef USE_ALMOS +#define vci_address_width 32 +#endif +#ifdef USE_GIET +#define vci_address_width 40 +#endif +#define vci_plen_width 8 +#define vci_rerror_width 1 +#define vci_clen_width 1 +#define vci_rflag_width 1 +#define vci_srcid_width 14 +#define vci_pktid_width 4 +#define vci_trdid_width 4 +#define vci_wrplen_width 1 + +//////////////////////////////////////////////////////////// +// Main Hardware Parameters values +//////////////////////i///////////////////////////////////// + +#ifdef USE_ALMOS +#include "almos/hard_config.h" +#define PREFIX_OS "almos/" +#endif +#ifdef USE_GIET +#include "scripts/soft/hard_config.h" +#define PREFIX_OS "giet_vm/" +#endif + +//////////////////////////////////////////////////////////// +// Secondary Hardware Parameters +//////////////////////i///////////////////////////////////// + +#define XMAX CLUSTER_X +#define YMAX CLUSTER_Y + +#define XRAM_LATENCY 0 + +#define MEMC_WAYS 16 +#define MEMC_SETS 256 + +#define L1_IWAYS 4 +#define L1_ISETS 64 + +#define L1_DWAYS 4 +#define L1_DSETS 64 + +#ifdef USE_ALMOS +#define FBUF_X_SIZE 512 +#define FBUF_Y_SIZE 512 +#endif +#ifdef USE_GIET +#define FBUF_X_SIZE 128 +#define FBUF_Y_SIZE 128 +#endif + +#ifdef USE_GIET +#define BDEV_SECTOR_SIZE 512 +#define BDEV_IMAGE_NAME PREFIX_OS"display/images.raw" +#endif +#ifdef USE_ALMOS +#define BDEV_SECTOR_SIZE 4096 +#define BDEV_IMAGE_NAME PREFIX_OS"hdd-img.bin" +#endif + +#define NIC_RX_NAME PREFIX_OS"nic/rx_packets.txt" +#define NIC_TX_NAME PREFIX_OS"nic/tx_packets.txt" +#define NIC_TIMEOUT 10000 + +#define NORTH 0 +#define SOUTH 1 +#define EAST 2 +#define WEST 3 + +//////////////////////////////////////////////////////////// +// Software to be loaded in ROM & RAM +//////////////////////i///////////////////////////////////// + +#ifdef USE_ALMOS +#define soft_name PREFIX_OS"bootloader.bin",\ + PREFIX_OS"kernel-soclib.bin@0xbfc10000:D",\ + PREFIX_OS"arch-info.bib@0xBFC08000:D" +#endif +#ifdef USE_GIET +#define soft_pathname "scripts/soft/soft.elf" +#endif + +//////////////////////////////////////////////////////////// +// DEBUG Parameters default values +//////////////////////i///////////////////////////////////// + +#define MAX_FROZEN_CYCLES 100000000 + +///////////////////////////////////////////////////////// +// Physical segments definition +///////////////////////////////////////////////////////// +// There is 3 segments replicated in all clusters +// and 5 specific segments in the "IO" cluster +// (containing address 0xBF000000) +///////////////////////////////////////////////////////// + +#ifdef USE_GIET + // specific segments in "IO" cluster : absolute physical address + #define BROM_BASE 0x00BFC00000 + #define BROM_SIZE 0x0000100000 // 1 Mbytes + + #define FBUF_BASE 0x00B2000000 + #define FBUF_SIZE (FBUF_X_SIZE * FBUF_Y_SIZE * 2) + + #define BDEV_BASE 0x00B3000000 + #define BDEV_SIZE 0x0000001000 // 4 Kbytes + + #define MTTY_BASE 0x00B4000000 + #define MTTY_SIZE 0x0000001000 // 4 Kbytes + + #define MNIC_BASE 0x00B5000000 + #define MNIC_SIZE 0x0000080000 // 512 Kbytes (for 8 channels) + + #define CDMA_BASE 0x00B6000000 + #define CDMA_SIZE 0x0000004000 * NB_CMA_CHANNELS + + // replicated segments : address is incremented by a cluster offset + // offset = cluster(x,y) << (address_width-x_width-y_width); + + #define MEMC_BASE 0x0000000000 + #define MEMC_SIZE 0x0010000000 // 256 Mbytes per cluster + + #define XICU_BASE 0x00B0000000 + #define XICU_SIZE 0x0000001000 // 4 Kbytes + + #define MDMA_BASE 0x00B1000000 + #define MDMA_SIZE 0x0000001000 * NB_DMA_CHANNELS // 4 Kbytes per channel + + #define SIMH_BASE 0x00B7000000 + #define SIMH_SIZE 0x0000001000 +#endif + +#ifdef USE_ALMOS + #define CLUSTER_INC (0x80000000ULL / (XMAX * YMAX) * 2) + + #define MEMC_BASE 0x0000000000 + #define MEMC_SIZE min(0x02000000, (0x80000000 / (XMAX * YMAX))) + + #define BROM_BASE 0x00BFC00000 + #define BROM_SIZE 0x0000100000 // 1 Mbytes + + #define XICU_BASE (MEMC_SIZE) + #define XICU_SIZE 0x0000001000 // 4 Kbytes + + #define MDMA_BASE (XICU_BASE + XICU_SIZE) + #define MDMA_SIZE 0x0000001000 * NB_DMA_CHANNELS // 4 Kbytes per channel + + #define BDEV_BASE ((cluster_io_id * (CLUSTER_INC)) + MDMA_BASE + MDMA_SIZE) + #define BDEV_SIZE 0x0000001000 // 4 Kbytes + + #define MTTY_BASE (BDEV_BASE + BDEV_SIZE) + #define MTTY_SIZE 0x0000001000 // 4 Kbytes + + #define FBUF_BASE (MTTY_BASE + MTTY_SIZE) + #define FBUF_SIZE (FBUF_X_SIZE * FBUF_Y_SIZE * 2) // Should be 0x80000 + + // Unused in almos + #define MNIC_BASE (FBUF_BASE + FBUF_SIZE) + #define MNIC_SIZE 0x0000001000 + + #define CDMA_BASE (MNIC_BASE + MNIC_SIZE) + #define CDMA_SIZE 0x0000004000 * NB_CMA_CHANNELS + +#endif + + +//////////////////////////////////////////////////////////////////// +// TGTID definition in direct space +// For all components: global TGTID = global SRCID = cluster_index +//////////////////////////////////////////////////////////////////// + +#define MEMC_TGTID 0 +#define XICU_TGTID 1 +#define MDMA_TGTID 2 +#define MTTY_TGTID 3 +#define FBUF_TGTID 4 +#define BDEV_TGTID 5 +#define MNIC_TGTID 6 +#define BROM_TGTID 7 +#define CDMA_TGTID 8 +#define SIMH_TGTID 9 + +bool stop_called = false; + +///////////////////////////////// +int _main(int argc, char *argv[]) +{ + using namespace sc_core; + using namespace soclib::caba; + using namespace soclib::common; + +#ifdef USE_GIET + char soft_name[256] = soft_pathname; // pathname to binary code +#endif + uint64_t ncycles = 0xFFFFFFFFFFFFFFFF; // simulated cycles + char disk_name[256] = BDEV_IMAGE_NAME; // pathname to the disk image + char nic_rx_name[256] = NIC_RX_NAME; // pathname to the rx packets file + char nic_tx_name[256] = NIC_TX_NAME; // pathname to the tx packets file + ssize_t threads_nr = 1; // simulator's threads number + bool debug_ok = false; // trace activated + size_t debug_period = 1; // trace period + size_t debug_memc_id = 0; // index of memc to be traced + size_t debug_proc_id = 0; // index of proc to be traced + uint32_t debug_from = 0; // trace start cycle + uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor + size_t cluster_io_id; // index of cluster containing IOs + struct timeval t1,t2; + uint64_t ms1,ms2; + + ////////////// command line arguments ////////////////////// + if (argc > 1) + { + for (int n = 1; n < argc; n = n + 2) + { + if ((strcmp(argv[n], "-NCYCLES") == 0) && (n + 1 < argc)) + { + ncycles = atoi(argv[n + 1]); + } + else if ((strcmp(argv[n], "-SOFT") == 0) && (n + 1 < argc)) + { +#ifdef USE_ALMOS + assert( 0 && "Can't define almos soft name" ); +#endif +#ifdef USE_GIET + strcpy(soft_name, argv[n + 1]); +#endif + } + else if ((strcmp(argv[n],"-DISK") == 0) && (n + 1 < argc)) + { + strcpy(disk_name, argv[n + 1]); + } + else if ((strcmp(argv[n],"-DEBUG") == 0) && (n + 1 < argc)) + { + debug_ok = true; + debug_from = atoi(argv[n + 1]); + } + else if ((strcmp(argv[n], "-MEMCID") == 0) && (n + 1 < argc)) + { + debug_memc_id = atoi(argv[n + 1]); + assert((debug_memc_id < (XMAX * YMAX)) && + "debug_memc_id larger than XMAX * YMAX" ); + } + else if ((strcmp(argv[n], "-PROCID") == 0) && (n + 1 < argc)) + { + debug_proc_id = atoi(argv[n + 1]); + assert((debug_proc_id < (XMAX * YMAX * NB_PROCS_MAX)) && + "debug_proc_id larger than XMAX * YMAX * NB_PROCS"); + } + else if ((strcmp(argv[n], "-THREADS") == 0) && ((n + 1) < argc)) + { + threads_nr = atoi(argv[n + 1]); + threads_nr = (threads_nr < 1) ? 1 : threads_nr; + } + else if ((strcmp(argv[n], "-FROZEN") == 0) && (n + 1 < argc)) + { + frozen_cycles = atoi(argv[n + 1]); + } + else if ((strcmp(argv[n], "-PERIOD") == 0) && (n + 1 < argc)) + { + debug_period = atoi(argv[n + 1]); + } + else + { + std::cout << " Arguments are (key,value) couples." << std::endl; + std::cout << " The order is not important." << std::endl; + std::cout << " Accepted arguments are :" << std::endl << std::endl; + std::cout << " -SOFT pathname_for_embedded_soft" << std::endl; + std::cout << " -DISK pathname_for_disk_image" << std::endl; + std::cout << " -NCYCLES number_of_simulated_cycles" << std::endl; + std::cout << " -DEBUG debug_start_cycle" << std::endl; + std::cout << " -THREADS simulator's threads number" << std::endl; + std::cout << " -FROZEN max_number_of_lines" << std::endl; + std::cout << " -PERIOD number_of_cycles between trace" << std::endl; + std::cout << " -MEMCID index_memc_to_be_traced" << std::endl; + std::cout << " -PROCID index_proc_to_be_traced" << std::endl; + exit(0); + } + } + } + + // checking hardware parameters + assert( ( (XMAX == 1) or (XMAX == 2) or (XMAX == 4) or + (XMAX == 8) or (XMAX == 16) ) and + "The XMAX parameter must be 1, 2, 4, 8 or 16" ); + + assert( ( (YMAX == 1) or (YMAX == 2) or (YMAX == 4) or + (YMAX == 8) or (YMAX == 16) ) and + "The YMAX parameter must be 1, 2, 4, 8 or 16" ); + + assert( ( (NB_PROCS_MAX == 1) or (NB_PROCS_MAX == 2) or + (NB_PROCS_MAX == 4) or (NB_PROCS_MAX == 8) ) and + "The NB_PROCS_MAX parameter must be 1, 2, 4 or 8" ); + + assert( (NB_DMA_CHANNELS < 9) and + "The NB_DMA_CHANNELS parameter must be smaller than 9" ); + + assert( (NB_TTY_CHANNELS < 15) and + "The NB_TTY_CHANNELS parameter must be smaller than 15" ); + + assert( (NB_NIC_CHANNELS < 9) and + "The NB_NIC_CHANNELS parameter must be smaller than 9" ); + +#ifdef USE_GIET + assert( (vci_address_width == 40) and + "VCI address width with the GIET must be 40 bits" ); +#endif + +#ifdef USE_ALMOS + assert( (vci_address_width == 32) and + "VCI address width with ALMOS must be 32 bits" ); +#endif + + + std::cout << std::endl; + std::cout << " - XMAX = " << XMAX << std::endl; + std::cout << " - YMAX = " << YMAX << std::endl; + std::cout << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl; + std::cout << " - NB_DMA_CHANNELS = " << NB_DMA_CHANNELS << std::endl; + std::cout << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl; + std::cout << " - NB_NIC_CHANNELS = " << NB_NIC_CHANNELS << std::endl; + std::cout << " - MEMC_WAYS = " << MEMC_WAYS << std::endl; + std::cout << " - MEMC_SETS = " << MEMC_SETS << std::endl; + std::cout << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl; + std::cout << " - MAX_FROZEN = " << frozen_cycles << std::endl; + std::cout << "[PROCS] " << NB_PROCS_MAX * XMAX * YMAX << std::endl; + + std::cout << std::endl; + // Internal and External VCI parameters definition + typedef soclib::caba::VciParams vci_param_int; + + typedef soclib::caba::VciParams vci_param_ext; + +#if USE_OPENMP + omp_set_dynamic(false); + omp_set_num_threads(threads_nr); + std::cerr << "Built with openmp version " << _OPENMP << std::endl; +#endif + + // Define parameters depending on mesh size + size_t x_width; + size_t y_width; + + if (XMAX == 1) x_width = 0; + else if (XMAX == 2) x_width = 1; + else if (XMAX <= 4) x_width = 2; + else if (XMAX <= 8) x_width = 3; + else x_width = 4; + + if (YMAX == 1) y_width = 0; + else if (YMAX == 2) y_width = 1; + else if (YMAX <= 4) y_width = 2; + else if (YMAX <= 8) y_width = 3; + else y_width = 4; + + +#ifdef USE_ALMOS + cluster_io_id = 0xbfc00000 >> (vci_address_width - x_width - y_width); // index of cluster containing IOs +#else + cluster_io_id = 0; +#endif + + ///////////////////// + // Mapping Tables + ///////////////////// + + // internal network + MappingTable maptabd(vci_address_width, + IntTab(x_width + y_width, 20 - x_width - y_width), + IntTab(x_width + y_width, vci_srcid_width - x_width - y_width), + 0x00FF800000); + + for (size_t x = 0; x < XMAX; x++) + { + for (size_t y = 0; y < YMAX; y++) + { + sc_uint offset; + offset = (sc_uint)cluster(x,y) + << (vci_address_width-x_width-y_width); + + std::ostringstream si; + si << "seg_xicu_" << x << "_" << y; + maptabd.add(Segment(si.str(), XICU_BASE + offset, XICU_SIZE, + IntTab(cluster(x,y),XICU_TGTID), false)); + + std::ostringstream sd; + sd << "seg_mdma_" << x << "_" << y; + maptabd.add(Segment(sd.str(), MDMA_BASE + offset, MDMA_SIZE, + IntTab(cluster(x,y),MDMA_TGTID), false)); + + std::ostringstream sh; + sh << "seg_memc_" << x << "_" << y; + maptabd.add(Segment(sh.str(), MEMC_BASE + offset, MEMC_SIZE, + IntTab(cluster(x,y),MEMC_TGTID), true)); + + if ( cluster(x,y) == cluster_io_id ) + { + maptabd.add(Segment("seg_mtty", MTTY_BASE, MTTY_SIZE, + IntTab(cluster(x,y),MTTY_TGTID), false)); + maptabd.add(Segment("seg_fbuf", FBUF_BASE, FBUF_SIZE, + IntTab(cluster(x,y),FBUF_TGTID), false)); + maptabd.add(Segment("seg_bdev", BDEV_BASE, BDEV_SIZE, + IntTab(cluster(x,y),BDEV_TGTID), false)); + maptabd.add(Segment("seg_brom", BROM_BASE, BROM_SIZE, + IntTab(cluster(x,y),BROM_TGTID), true)); + maptabd.add(Segment("seg_mnic", MNIC_BASE, MNIC_SIZE, + IntTab(cluster(x,y),MNIC_TGTID), false)); + maptabd.add(Segment("seg_cdma", CDMA_BASE, CDMA_SIZE, + IntTab(cluster(x,y),CDMA_TGTID), false)); + maptabd.add(Segment("seg_simh", SIMH_BASE, SIMH_SIZE, + IntTab(cluster(x,y),SIMH_TGTID), false)); + } + } + } + std::cout << maptabd << std::endl; + + // external network + MappingTable maptabx(vci_address_width, + IntTab(x_width+y_width), + IntTab(x_width+y_width), + 0xFFFF000000ULL); + + for (size_t x = 0; x < XMAX; x++) + { + for (size_t y = 0; y < YMAX ; y++) + { + + sc_uint offset; + offset = (sc_uint)cluster(x,y) + << (vci_address_width-x_width-y_width); + + std::ostringstream sh; + sh << "x_seg_memc_" << x << "_" << y; + + maptabx.add(Segment(sh.str(), MEMC_BASE + offset, + MEMC_SIZE, IntTab(cluster(x,y)), false)); + } + + } + std::cout << maptabx << std::endl; + + //////////////////// + // Signals + /////////////////// + + sc_clock signal_clk("clk"); + sc_signal signal_resetn("resetn"); + + // Horizontal inter-clusters DSPIN signals + DspinSignals*** signal_dspin_h_cmd_inc = + alloc_elems >("signal_dspin_h_cmd_inc", XMAX-1, YMAX, 3); + DspinSignals*** signal_dspin_h_cmd_dec = + alloc_elems >("signal_dspin_h_cmd_dec", XMAX-1, YMAX, 3); + DspinSignals*** signal_dspin_h_rsp_inc = + alloc_elems >("signal_dspin_h_rsp_inc", XMAX-1, YMAX, 2); + DspinSignals*** signal_dspin_h_rsp_dec = + alloc_elems >("signal_dspin_h_rsp_dec", XMAX-1, YMAX, 2); + + // Vertical inter-clusters DSPIN signals + DspinSignals*** signal_dspin_v_cmd_inc = + alloc_elems >("signal_dspin_v_cmd_inc", XMAX, YMAX-1, 3); + DspinSignals*** signal_dspin_v_cmd_dec = + alloc_elems >("signal_dspin_v_cmd_dec", XMAX, YMAX-1, 3); + DspinSignals*** signal_dspin_v_rsp_inc = + alloc_elems >("signal_dspin_v_rsp_inc", XMAX, YMAX-1, 2); + DspinSignals*** signal_dspin_v_rsp_dec = + alloc_elems >("signal_dspin_v_rsp_dec", XMAX, YMAX-1, 2); + + // Mesh boundaries DSPIN signals + DspinSignals**** signal_dspin_false_cmd_in = + alloc_elems >("signal_dspin_false_cmd_in" , XMAX, YMAX, 4, 3); + DspinSignals**** signal_dspin_false_cmd_out = + alloc_elems >("signal_dspin_false_cmd_out", XMAX, YMAX, 4, 3); + DspinSignals**** signal_dspin_false_rsp_in = + alloc_elems >("signal_dspin_false_rsp_in" , XMAX, YMAX, 4, 2); + DspinSignals**** signal_dspin_false_rsp_out = + alloc_elems >("signal_dspin_false_rsp_out", XMAX, YMAX, 4, 2); + + + //////////////////////////// + // Loader + //////////////////////////// + + soclib::common::Loader loader(soft_name); + + typedef soclib::common::GdbServer proc_iss; + proc_iss::set_loader(loader); + + //////////////////////////// + // Clusters construction + //////////////////////////// + + TsarXbarCluster* clusters[XMAX][YMAX]; + +#if USE_OPENMP +#pragma omp parallel + { +#pragma omp for +#endif + for (size_t i = 0; i < (XMAX * YMAX); i++) + { + size_t x = i / YMAX; + size_t y = i % YMAX; + +#if USE_OPENMP +#pragma omp critical + { +#endif + std::cout << std::endl; + std::cout << "Cluster_" << x << "_" << y << std::endl; + std::cout << std::endl; + + std::ostringstream sc; + sc << "cluster_" << x << "_" << y; + clusters[x][y] = new TsarXbarCluster + ( + sc.str().c_str(), + NB_PROCS_MAX, + NB_TTY_CHANNELS, + NB_DMA_CHANNELS, + x, + y, + cluster(x,y), + maptabd, + maptabx, + x_width, + y_width, + vci_srcid_width - x_width - y_width, // l_id width, + MEMC_TGTID, + XICU_TGTID, + MDMA_TGTID, + FBUF_TGTID, + MTTY_TGTID, + BROM_TGTID, + MNIC_TGTID, + CDMA_TGTID, + BDEV_TGTID, + SIMH_TGTID, + MEMC_WAYS, + MEMC_SETS, + L1_IWAYS, + L1_ISETS, + L1_DWAYS, + L1_DSETS, + XRAM_LATENCY, + (cluster(x,y) == cluster_io_id), + FBUF_X_SIZE, + FBUF_Y_SIZE, + disk_name, + BDEV_SECTOR_SIZE, + NB_NIC_CHANNELS, + nic_rx_name, + nic_tx_name, + NIC_TIMEOUT, + NB_CMA_CHANNELS, + loader, + frozen_cycles, + debug_from, + debug_ok and (cluster(x,y) == debug_memc_id), + debug_ok and (cluster(x,y) == debug_proc_id) + ); + +#if USE_OPENMP + } // end critical +#endif + } // end for +#if USE_OPENMP + } +#endif + + /////////////////////////////////////////////////////////////// + // Net-list + /////////////////////////////////////////////////////////////// + + // Clock & RESET + for (size_t x = 0; x < (XMAX); x++){ + for (size_t y = 0; y < YMAX; y++){ + clusters[x][y]->p_clk (signal_clk); + clusters[x][y]->p_resetn (signal_resetn); + } + } + + // Inter Clusters horizontal connections + if (XMAX > 1){ + for (size_t x = 0; x < (XMAX-1); x++){ + for (size_t y = 0; y < YMAX; y++){ + for (size_t k = 0; k < 3; k++){ + clusters[x][y]->p_cmd_out[EAST][k] (signal_dspin_h_cmd_inc[x][y][k]); + clusters[x+1][y]->p_cmd_in[WEST][k] (signal_dspin_h_cmd_inc[x][y][k]); + clusters[x][y]->p_cmd_in[EAST][k] (signal_dspin_h_cmd_dec[x][y][k]); + clusters[x+1][y]->p_cmd_out[WEST][k] (signal_dspin_h_cmd_dec[x][y][k]); + } + + for (size_t k = 0; k < 2; k++){ + clusters[x][y]->p_rsp_out[EAST][k] (signal_dspin_h_rsp_inc[x][y][k]); + clusters[x+1][y]->p_rsp_in[WEST][k] (signal_dspin_h_rsp_inc[x][y][k]); + clusters[x][y]->p_rsp_in[EAST][k] (signal_dspin_h_rsp_dec[x][y][k]); + clusters[x+1][y]->p_rsp_out[WEST][k] (signal_dspin_h_rsp_dec[x][y][k]); + } + } + } + } + std::cout << std::endl << "Horizontal connections established" << std::endl; + + // Inter Clusters vertical connections + if (YMAX > 1) { + for (size_t y = 0; y < (YMAX-1); y++){ + for (size_t x = 0; x < XMAX; x++){ + for (size_t k = 0; k < 3; k++){ + clusters[x][y]->p_cmd_out[NORTH][k] (signal_dspin_v_cmd_inc[x][y][k]); + clusters[x][y+1]->p_cmd_in[SOUTH][k] (signal_dspin_v_cmd_inc[x][y][k]); + clusters[x][y]->p_cmd_in[NORTH][k] (signal_dspin_v_cmd_dec[x][y][k]); + clusters[x][y+1]->p_cmd_out[SOUTH][k] (signal_dspin_v_cmd_dec[x][y][k]); + } + + for (size_t k = 0; k < 2; k++){ + clusters[x][y]->p_rsp_out[NORTH][k] (signal_dspin_v_rsp_inc[x][y][k]); + clusters[x][y+1]->p_rsp_in[SOUTH][k] (signal_dspin_v_rsp_inc[x][y][k]); + clusters[x][y]->p_rsp_in[NORTH][k] (signal_dspin_v_rsp_dec[x][y][k]); + clusters[x][y+1]->p_rsp_out[SOUTH][k] (signal_dspin_v_rsp_dec[x][y][k]); + } + } + } + } + std::cout << "Vertical connections established" << std::endl; + + // East & West boundary cluster connections + for (size_t y = 0; y < YMAX; y++) + { + for (size_t k = 0; k < 3; k++) + { + clusters[0][y]->p_cmd_in[WEST][k] (signal_dspin_false_cmd_in[0][y][WEST][k]); + clusters[0][y]->p_cmd_out[WEST][k] (signal_dspin_false_cmd_out[0][y][WEST][k]); + clusters[XMAX-1][y]->p_cmd_in[EAST][k] (signal_dspin_false_cmd_in[XMAX-1][y][EAST][k]); + clusters[XMAX-1][y]->p_cmd_out[EAST][k] (signal_dspin_false_cmd_out[XMAX-1][y][EAST][k]); + } + + for (size_t k = 0; k < 2; k++) + { + clusters[0][y]->p_rsp_in[WEST][k] (signal_dspin_false_rsp_in[0][y][WEST][k]); + clusters[0][y]->p_rsp_out[WEST][k] (signal_dspin_false_rsp_out[0][y][WEST][k]); + clusters[XMAX-1][y]->p_rsp_in[EAST][k] (signal_dspin_false_rsp_in[XMAX-1][y][EAST][k]); + clusters[XMAX-1][y]->p_rsp_out[EAST][k] (signal_dspin_false_rsp_out[XMAX-1][y][EAST][k]); + } + } + + // North & South boundary clusters connections + for (size_t x = 0; x < XMAX; x++) + { + for (size_t k = 0; k < 3; k++) + { + clusters[x][0]->p_cmd_in[SOUTH][k] (signal_dspin_false_cmd_in[x][0][SOUTH][k]); + clusters[x][0]->p_cmd_out[SOUTH][k] (signal_dspin_false_cmd_out[x][0][SOUTH][k]); + clusters[x][YMAX-1]->p_cmd_in[NORTH][k] (signal_dspin_false_cmd_in[x][YMAX-1][NORTH][k]); + clusters[x][YMAX-1]->p_cmd_out[NORTH][k] (signal_dspin_false_cmd_out[x][YMAX-1][NORTH][k]); + } + + for (size_t k = 0; k < 2; k++) + { + clusters[x][0]->p_rsp_in[SOUTH][k] (signal_dspin_false_rsp_in[x][0][SOUTH][k]); + clusters[x][0]->p_rsp_out[SOUTH][k] (signal_dspin_false_rsp_out[x][0][SOUTH][k]); + clusters[x][YMAX-1]->p_rsp_in[NORTH][k] (signal_dspin_false_rsp_in[x][YMAX-1][NORTH][k]); + clusters[x][YMAX-1]->p_rsp_out[NORTH][k] (signal_dspin_false_rsp_out[x][YMAX-1][NORTH][k]); + } + } + std::cout << "North, South, West, East connections established" << std::endl; + std::cout << std::endl; + + + //////////////////////////////////////////////////////// + // Simulation + /////////////////////////////////////////////////////// + + sc_start(sc_core::sc_time(0, SC_NS)); + signal_resetn = false; + + // network boundaries signals + for (size_t x = 0; x < XMAX ; x++){ + for (size_t y = 0; y < YMAX ; y++){ + for (size_t a = 0; a < 4; a++){ + for (size_t k = 0; k < 3; k++){ + signal_dspin_false_cmd_in [x][y][a][k].write = false; + signal_dspin_false_cmd_in [x][y][a][k].read = true; + signal_dspin_false_cmd_out[x][y][a][k].write = false; + signal_dspin_false_cmd_out[x][y][a][k].read = true; + } + + for (size_t k = 0; k < 2; k++){ + signal_dspin_false_rsp_in [x][y][a][k].write = false; + signal_dspin_false_rsp_in [x][y][a][k].read = true; + signal_dspin_false_rsp_out[x][y][a][k].write = false; + signal_dspin_false_rsp_out[x][y][a][k].read = true; + } + } + } + } + + sc_start(sc_core::sc_time(1, SC_NS)); + signal_resetn = true; + + if (gettimeofday(&t1, NULL) != 0) + { + perror("gettimeofday"); + return EXIT_FAILURE; + } + + for (uint64_t n = 1; n < ncycles && !stop_called; n++) + { + // Monitor a specific address for L1 & L2 caches + //clusters[0][0]->proc[0]->cache_monitor(0x800002c000ULL); + //clusters[1][0]->memc->copies_monitor(0x800002C000ULL); + + if( (n % 5000000) == 0) + { + + if (gettimeofday(&t2, NULL) != 0) + { + perror("gettimeofday"); + return EXIT_FAILURE; + } + + ms1 = (uint64_t) t1.tv_sec * 1000ULL + (uint64_t) t1.tv_usec / 1000; + ms2 = (uint64_t) t2.tv_sec * 1000ULL + (uint64_t) t2.tv_usec / 1000; + std::cerr << "platform clock frequency " << (double) 5000000 / (double) (ms2 - ms1) << "Khz" << std::endl; + + if (gettimeofday(&t1, NULL) != 0) + { + perror("gettimeofday"); + return EXIT_FAILURE; + } + } + + if (debug_ok and (n > debug_from) and (n % debug_period == 0)) + { + std::cout << "****************** cycle " << std::dec << n ; + std::cout << " ************************************************" << std::endl; + + // trace proc[debug_proc_id] + size_t l = debug_proc_id % NB_PROCS_MAX ; + size_t y = (debug_proc_id / NB_PROCS_MAX) % YMAX ; + size_t x = debug_proc_id / (YMAX * NB_PROCS_MAX) ; + + std::ostringstream proc_signame; + proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; + std::ostringstream p2m_signame; + p2m_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " P2M" ; + std::ostringstream m2p_signame; + m2p_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " M2P" ; + std::ostringstream p_cmd_signame; + p_cmd_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " CMD" ; + std::ostringstream p_rsp_signame; + p_rsp_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " RSP" ; + + for (int _x = 0, _y = 0; _x != XMAX; (_y == YMAX - 1 ? _x++, _y = 0 : _y++)) { + for (int _l = 0; _l < NB_PROCS_MAX; _l++) { + clusters[_x][_y]->proc[_l]->print_trace(); + } + } + //clusters[x][y]->wi_proc[l]->print_trace(); + //clusters[x][y]->signal_vci_ini_proc[l].print_trace(proc_signame.str()); + //clusters[x][y]->signal_dspin_p2m_proc[l].print_trace(p2m_signame.str()); + //clusters[x][y]->signal_dspin_m2p_proc[l].print_trace(m2p_signame.str()); + //clusters[x][y]->signal_dspin_cmd_proc_i[l].print_trace(p_cmd_signame.str()); + //clusters[x][y]->signal_dspin_rsp_proc_i[l].print_trace(p_rsp_signame.str()); + + //clusters[x][y]->xbar_rsp_d->print_trace(); + //clusters[x][y]->xbar_cmd_d->print_trace(); + //clusters[x][y]->signal_dspin_cmd_l2g_d.print_trace("[SIG]L2G CMD"); + //clusters[x][y]->signal_dspin_cmd_g2l_d.print_trace("[SIG]G2L CMD"); + //clusters[x][y]->signal_dspin_rsp_l2g_d.print_trace("[SIG]L2G RSP"); + //clusters[x][y]->signal_dspin_rsp_g2l_d.print_trace("[SIG]G2L RSP"); + + // trace memc[debug_memc_id] + x = debug_memc_id / YMAX; + y = debug_memc_id % YMAX; + + std::ostringstream smemc; + smemc << "[SIG]MEMC_" << x << "_" << y; + std::ostringstream sxram; + sxram << "[SIG]XRAM_" << x << "_" << y; + std::ostringstream sm2p; + sm2p << "[SIG]MEMC_" << x << "_" << y << " M2P" ; + std::ostringstream sp2m; + sp2m << "[SIG]MEMC_" << x << "_" << y << " P2M" ; + std::ostringstream m_cmd_signame; + m_cmd_signame << "[SIG]MEMC_" << x << "_" << y << " CMD" ; + std::ostringstream m_rsp_signame; + m_rsp_signame << "[SIG]MEMC_" << x << "_" << y << " RSP" ; + + clusters[x][y]->memc->print_trace(); + //clusters[x][y]->wt_memc->print_trace(); + //clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str()); + //clusters[x][y]->signal_vci_xram.print_trace(sxram.str()); + //clusters[x][y]->signal_dspin_p2m_memc.print_trace(sp2m.str()); + //clusters[x][y]->signal_dspin_m2p_memc.print_trace(sm2p.str()); + //clusters[x][y]->signal_dspin_cmd_memc_t.print_trace(m_cmd_signame.str()); + //clusters[x][y]->signal_dspin_rsp_memc_t.print_trace(m_rsp_signame.str()); + + // trace replicated peripherals + //clusters[1][1]->mdma->print_trace(); + //clusters[1][1]->signal_vci_tgt_mdma.print_trace("[SIG]MDMA_TGT_1_1"); + //clusters[1][1]->signal_vci_ini_mdma.print_trace("[SIG]MDMA_INI_1_1"); + + + // trace external peripherals + //size_t io_x = cluster_io_id / YMAX; + //size_t io_y = cluster_io_id % YMAX; + + //clusters[io_x][io_y]->brom->print_trace(); + //clusters[io_x][io_y]->wt_brom->print_trace(); + //clusters[io_x][io_y]->signal_vci_tgt_brom.print_trace("[SIG]BROM"); + //clusters[io_x][io_y]->signal_dspin_cmd_brom_t.print_trace("[SIG]BROM CMD"); + //clusters[io_x][io_y]->signal_dspin_rsp_brom_t.print_trace("[SIG]BROM RSP"); + + //clusters[io_x][io_y]->bdev->print_trace(); + //clusters[io_x][io_y]->signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT"); + //clusters[io_x][io_y]->signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); + } + + sc_start(sc_core::sc_time(1, SC_NS)); + } + + + // Free memory + for (size_t i = 0; i < (XMAX * YMAX); i++) + { + size_t x = i / YMAX; + size_t y = i % YMAX; + delete clusters[x][y]; + } + + dealloc_elems >(signal_dspin_h_cmd_inc, XMAX - 1, YMAX, 3); + dealloc_elems >(signal_dspin_h_cmd_dec, XMAX - 1, YMAX, 3); + dealloc_elems >(signal_dspin_h_rsp_inc, XMAX - 1, YMAX, 2); + dealloc_elems >(signal_dspin_h_rsp_dec, XMAX - 1, YMAX, 2); + dealloc_elems >(signal_dspin_v_cmd_inc, XMAX, YMAX - 1, 3); + dealloc_elems >(signal_dspin_v_cmd_dec, XMAX, YMAX - 1, 3); + dealloc_elems >(signal_dspin_v_rsp_inc, XMAX, YMAX - 1, 2); + dealloc_elems >(signal_dspin_v_rsp_dec, XMAX, YMAX - 1, 2); + dealloc_elems >(signal_dspin_false_cmd_in, XMAX, YMAX, 4, 3); + dealloc_elems >(signal_dspin_false_cmd_out, XMAX, YMAX, 4, 3); + dealloc_elems >(signal_dspin_false_rsp_in, XMAX, YMAX, 4, 2); + dealloc_elems >(signal_dspin_false_rsp_out, XMAX, YMAX, 4, 2); + + return EXIT_SUCCESS; +} + + +void handler(int dummy = 0) { + stop_called = true; + sc_stop(); +} + +void voidhandler(int dummy = 0) {} + +int sc_main (int argc, char *argv[]) +{ + signal(SIGINT, handler); + signal(SIGPIPE, voidhandler); + + try { + return _main(argc, argv); + } catch (std::exception &e) { + std::cout << e.what() << std::endl; + } catch (...) { + std::cout << "Unknown exception occured" << std::endl; + throw; + } + return 1; +} + + +// Local Variables: +// tab-width: 3 +// c-basic-offset: 3 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 Index: /branches/fault_tolerance/softs/test_llsc/top.desc =================================================================== --- /branches/fault_tolerance/softs/test_llsc/top.desc (revision 724) +++ /branches/fault_tolerance/softs/test_llsc/top.desc (revision 724) @@ -0,0 +1,46 @@ + +# -*- python -*- + +# internal VCI parameters values +vci_cell_size_int = 4 +vci_cell_size_ext = 8 + +vci_plen_size = 8 +vci_addr_size = 40 +vci_rerror_size = 1 +vci_clen_size = 1 +vci_rflag_size = 1 +vci_srcid_size = 14 +vci_pktid_size = 4 +vci_trdid_size = 4 +vci_wrplen_size = 1 + +# DSPIN network parameters values +dspin_cmd_flit_size = 39 +dspin_rsp_flit_size = 32 + +todo = Platform('caba', 'top.cpp', + + uses = [ + Uses('caba:tsar_xbar_cluster', + vci_data_width_int = vci_cell_size_int, + vci_data_width_ext = vci_cell_size_ext, + dspin_cmd_width = dspin_cmd_flit_size, + dspin_rsp_width = dspin_rsp_flit_size), + + Uses('common:elf_file_loader'), + Uses('common:plain_file_loader'), + ], + + # default VCI parameters (global variables) + cell_size = vci_cell_size_int, + plen_size = vci_plen_size, + addr_size = vci_addr_size, + rerror_size = vci_rerror_size, + clen_size = vci_clen_size, + rflag_size = vci_rflag_size, + srcid_size = vci_srcid_size, + pktid_size = vci_pktid_size, + trdid_size = vci_trdid_size, + wrplen_size = vci_wrplen_size, +) Index: /branches/fault_tolerance/softs/tests_cc_vcache/Makefile.inc =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/Makefile.inc (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/Makefile.inc (revision 724) @@ -0,0 +1,27 @@ +all: test.elf + +COMMON= ../common +LDSCRIPT?= ../common/ldscript + +CC= mipsel-unknown-elf-gcc +LD= mipsel-unknown-elf-ld +DU= mipsel-unknown-elf-objdump + +CFLAGS= -mips32 -nostdinc -I. -I${COMMON} -mno-abicalls +### LDFLAGS=-mips32 -nostdlib -Wl,-T${LDSCRIPT} -Ttext=0xbfc00000 + +#### object files generation +test.o: test.S + ${CC} ${CFLAGS} -c -o $@ $< + ${DU} -D $@ > $@.txt + +subr.o: ${COMMON}/subr.S + ${CC} ${CFLAGS} -c -o $@ $< + ${DU} -D $@ > $@.txt + +### linking : test.o has to be the first object +test.elf: test.o subr.o ${EXTRA_OBJ} + ${LD} -o $@ -T ${LDSCRIPT} -Ttext 0xbfc00000 $^ + ${DU} -D $@ > $@.txt +clean: + rm -f *.o test.elf *.txt run.out temp Index: /branches/fault_tolerance/softs/tests_cc_vcache/README =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/README (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/README (revision 724) @@ -0,0 +1,46 @@ +This is a very basic framework for running regression tests against +a mips32+ccvcache TSAR platform. Here's the layout of this directory: + +../../../platforms/tsarv4_mono_mmu + contains the soclib platform description and simulation executable. + It should be compiled before starting tests. + it uses the vci_simhelper component, used to stop the simulation + with an exit value. The framework uses this exit status + (with other things, see below) to determine if a test + is successfull. The simulator will exit with a non-0 exit status + after 100000 cycles (and a message to stderr), so the tests are + expected to be simple. + The platform has a tty, which is redirected to a file along with + the simlulator's output. The test framework may search for specific + strings in this file to determine if a test was successfull. +common/ + Some common functions, ldscripts, etc ... used by the tests. + It has a subr.S which holds usefull subroutines, such as + print() and printx(). +Makefile.inc + included from the test's Makefiles. Basic stuff to compile a + mips32 ELF executable for a test. It expects a test.S, + add the subr.S from common and eventually additionnal object + files. +test_*/ + these directories holds the test themselves. They have a run + script which does what is needed to compile and run a test, + print "test failed" or "test passed" on stdout, and clean the + directory if it's successfull. A sample script will call + make, then run the simulator with srdout/stderr redirected + to a file. If the simulator exists with a 0 status, this + script search for some strings in the output (that the + test program would have printed). This is an additionnal way + to check that all worked properly. + Tests are written in assembly; as we're testing for very specific + conditions (such as an instruction in a branch's delay slot on + a page boundary), we don't want the compiler to optimise things + or otherwise reorder instructions. + If the test was successfull, the 'run' script cleanups the + directory. Otherwise the 'run.out' file is available to + start looking at what's wrong. +run_tests + runs all the test_*/run scripts - the goal being that + all of them print "test passsed" :). Directories are explicitely + listed in the run_tests script (order does matter to have a readable + output) Index: /branches/fault_tolerance/softs/tests_cc_vcache/common/common.sh =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/common/common.sh (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/common/common.sh (revision 724) @@ -0,0 +1,3 @@ +SIMUL=../../../platforms/tsar_mono_mmu/simul.x + +#SIMUL=../../../../soclib-svn-june-2009/soclib/soclib/platform/topcells/caba_vgsb_almo_mmu/simul.x Index: /branches/fault_tolerance/softs/tests_cc_vcache/common/ldscript =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/common/ldscript (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/common/ldscript (revision 724) @@ -0,0 +1,65 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ + +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /branches/fault_tolerance/softs/tests_cc_vcache/common/misc.h =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/common/misc.h (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/common/misc.h (revision 724) @@ -0,0 +1,56 @@ +/* multi-tty definitions */ +#define TTY_BASE 0xd0200000 +#define TTY_WRITE 0 +#define TTY_STATUS 1 +#define TTY_READ 2 + +/* vci_exit definitions */ +#define EXIT_BASE 0xe0000000 + +#define BOOT_ADDRESS 0xbfc00000 +#define EXCEP_ADDRESS 0xbfc00380 + +/* vci dma */ +#define DMA_BASE 0xe8000000 +#define DMA_SRC 0 +#define DMA_DST 4 +#define DMA_LEN 8 +#define DMA_RESET 12 + +/* cop0 definitions */ +#define COP_0_BADVADDR $8 +#define COP0_STATUS $12 +#define COP0_CAUSE $13 +#define COP0_EXPC $14 + +/* easy print macros */ +#define PRINT(str) \ + la a0, str;\ + jal print; \ + nop + +#define PRINT_SYNC(str) \ + la a0, str;\ + jal print_sync; \ + nop + + + +#define PRINTX \ + jal printx;\ + nop + +#define PUTCHAR(c) li a0, c; sb a0, 0(k0) + +#define EXIT(a) \ + li a0, a; \ + sw a0, 4(k1); \ + 1: j 1b; \ + nop + +/* some magic numers to test */ +#define MAGIC1 0xdead +#define MAGIC2 0xbeef +#define MAGIC3 0x900d +#define MAGIC4 0xf00d + Index: /branches/fault_tolerance/softs/tests_cc_vcache/common/registers.h =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/common/registers.h (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/common/registers.h (revision 724) @@ -0,0 +1,32 @@ +#define zero $0 +#define at $at +#define v0 $2 +#define v1 $3 +#define a0 $4 +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define s0 $16 +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 +#define t9 $25 +#define k0 $26 +#define k1 $27 +#define gp $28 +#define sp $29 +#define fp $30 +#define ra $31 Index: /branches/fault_tolerance/softs/tests_cc_vcache/common/subr.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/common/subr.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/common/subr.S (revision 724) @@ -0,0 +1,78 @@ +#include +/* test common subroutines + + .text +/* + * void print(char *): print a string to the multitty. + * assumes k0 points to the tty base. + */ + .globl print +print: + .set noreorder + move t0, a0 +1: + lb t1, 0(t0); + beq t1, zero, end + nop + sb t1, 0(k0) + addiu t0, t0, 1 + j 1b + nop +end: + jr ra + nop + +/* + * void print_sync(char *): print a string to the multitty with a sync instruction for each character. + * assumes k0 points to the tty base. + */ + .globl print_sync +print_sync: + .set noreorder + move t0, a0 +1: + lb t1, 0(t0); + beq t1, zero, end_print_sync + nop + sb t1, 0(k0) + sync + addiu t0, t0, 1 + j 1b + nop +end_print_sync: + jr ra + nop + + +/* + * void printx(uint32_t): print a number in hex to the multitty + * assumes points to the tty base. + */ + .globl printx +printx: + .set noreorder + move t0, a0 + li t1, '0' + sb t1, 0(k0) + li t1, 'x' + sb t1, 0(k0) + li t1, 8 +1: + lui t2, 0xf000; + and t2, t0, t2 + srl t2, t2, 28 + slti t3, t2, 0xa + beq t3, zero, 2f /* in range A-F */ + nop + addi t2, t2, '0' + j 3f + nop +2: + addi t2, t2, 'A' - 0xa +3: + sb t2, 0(k0) + addi t1, t1, -1 + bgtz t1, 1b + sll t0, t0, 4 + jr ra + nop Index: /branches/fault_tolerance/softs/tests_cc_vcache/common/vcache.h =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/common/vcache.h (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/common/vcache.h (revision 724) @@ -0,0 +1,66 @@ +/* cop2/vcache definitions */ +#define VC_PTPR $0 /* set Page Table Pointer Register */ +#define VC_TLB_EN $1 /* set Data & Inst TLBs Mode Register */ +#define VC_TLB_EN_ITLB 0x8 /* enable instruction TLB */ +#define VC_TLB_EN_DTLB 0x4 /* enable data TLB */ +#define VC_TLB_EN_ICACHE 0x2 /* enable instruction cache */ +#define VC_TLB_EN_DCACHE 0x1 /* enable data cache */ +#define VC_ICACHE_FLUSH $2 /* Instruction Cache flush */ +#define VC_DCACHE_FLUSH $3 /* Data Cache flush */ +#define VC_ITLB_INVAL $4 /* Instruction TLB line invalidate */ +#define VC_DTLB_INVAL $5 /* Data TLB line invalidate */ +#define VC_ICACHE_INVAL $6 /* Instruction Cache line invalidate */ +#define VC_DCACHE_INVAL $7 /* Data Cache line invalidate */ +#define VC_ICACHE_PREFETCH $8 /* Instruction Cache line prefetch */ +#define VC_DCACHE_PREFETCH $9 /* Data Cache line prefetch */ +#define VC_SYNC $10 /* Complete pending writes */ +#define VC_IERR_TYPE $11 /* Instruction Exception type Register */ +#define VC_DERR_TYPE $12 /* Data Exception type Register */ +#define VC_DATA_LO $17 /* misc register low */ +#define VC_DATA_HI $18 /* misc register hight */ +#define VC_ICACHE_INVAL_PA $19 /* misc register hight */ +#define VC_DCACHE_INVAL_PA $20 /* misc register hight */ +#define VC_ERR_PT1_UNMAPPED 0x001 /* Page fault on Table1 (invalid PTE) */ +#define VC_ERR_PT2_UNMAPPED 0x002 /* Page fault on Table 2 (invalid PTE) */ +#define VC_ERR_PRIVILEGE_VIOLATION 0x004 /* Protected access in user mode */ +#define VC_ERR_WRITE_VIOLATION 0x008 /* Write access to a non write page */ +#define VC_ERR_EXEC_VIOLATION 0x010 /* Exec access to a non exec page */ +#define VC_ERR_UNDEFINED_XTN 0x020 /* Undefined external access address */ +#define VC_ERR_PT1_ILLEGAL_ACCESS 0x040 /* Bus Error in Table1 access */ +#define VC_ERR_PT2_ILLEGAL_ACCESS 0x080 /* Bus Error in Table2 access */ +#define VC_ERR_CACHE_ILLEGAL_ACCESS 0x100 /* Bus Error during the cache access */ +#define VC_I_BAD_VADDR $13 /* Instruction Bad Virtual Address Register */ +#define VC_D_BAD_VADDR $14 /* Data Bad Virtual Address Register */ +#define VC_DATA_L $17 /* cache parameters */ +#define VC_DATA_H $18 /* cache parameters */ +#define VC_ICACHE_INVAL_PA $19 /* icache inval per physical address */ +#define VC_DCACHE_INVAL_PA $20 /* dcache inval per physical address */ + +/* vcache page level 1 format */ +#define PTE1_V (1 << 31) /* entry valid */ +#define PTE1_T (1 << 30) /* 0 == entry is a PTE1 (maps a 2M page) */ +#define PTE1_L (1 << 29) /* accessed by local CPU */ +#define PTE1_R (1 << 28) /* accessed by remote CPU */ +#define PTE1_C (1 << 27) /* cachable */ +#define PTE1_W (1 << 26) /* writable */ +#define PTE1_X (1 << 25) /* executable */ +#define PTE1_U (1 << 24) /* user-accessible */ +#define PTE1_G (1 << 23) /* global */ +#define PTE1_D (1 << 22) /* dirty */ + +/* vcache page level 2 format: same as level 1, PTE1_T */ +#define PTE2_V (1 << 31) /* entry valid */ + /* reserved, 0 */ +#define PTE2_L (1 << 29) /* accessed by local CPU */ +#define PTE2_R (1 << 28) /* accessed by remote CPU */ +#define PTE2_C (1 << 27) /* cachable */ +#define PTE2_W (1 << 26) /* writable */ +#define PTE2_X (1 << 25) /* executable */ +#define PTE2_U (1 << 24) /* user-accessible */ +#define PTE2_G (1 << 23) /* global */ +#define PTE2_D (1 << 22) /* dirty */ +#define PTE2_os 0xff /* OS-reserved bits */ + +#define PTE2_SHIFT 12 +#define PTE2_MASK 0x0001ff000 +#define VADDR_TO_PTE2I(va) (((va) & PTE2_MASK) >> PTE2_SHIFT) Index: /branches/fault_tolerance/softs/tests_cc_vcache/common/xicu.h =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/common/xicu.h (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/common/xicu.h (revision 724) @@ -0,0 +1,96 @@ +#define XICU_BASE 0xd8200000 +#define __XICU_FUNC_SHIFT 7 +#define __XICU_IDX_SHIFT 2 +#define __XICU_RIDX(func, idx) \ + ((((func) & 0x1f) << __XICU_FUNC_SHIFT) + \ + (((idx) & 0x1f) << __XICU_IDX_SHIFT)) + +/* triggers the wtiidx interrupt. R/W */ +#define XICU_WTI_REG_FUNC 0x00 +#define XICU_WTI_REG(wtiidx) __XICU_RIDX(XICU_WTI_REG_FUNC, wtiidx) + +/* Timer period R/W */ +#define XICU_PTI_PER_FUNC 0x01 +#define XICU_PTI_PER(ptiidx) __XICU_RIDX(XICU_PTI_PER_FUNC, ptiidx) + +/* timer value R/W */ +#define XICU_PTI_VAL_FUNC 0x02 +#define XICU_PTI_VAL(ptiidx) __XICU_RIDX(XICU_PTI_VAL_FUNC, ptiidx) + +/* Timer interrupt acknowledge. R */ +#define XICU_PTI_ACK_FUNC 0x03 +#define XICU_PTI_ACK(ptiidx) __XICU_RIDX(XICU_PTI_ACK_FUNC, ptiidx) + +/* + * remaining registers define the way interrupt sources are mutiplexed to + * the output lines. Indexed by output line number. + */ +/* + * Multiplex timers to output lines: + * XICU_MSK_PTI mask register for outidx line (bit to 1 enable interrupt) + * XICU_MSK_PTI_E atomically add a set of bits to XICU_MSK_PTI + * XICU_MSK_PTI_D atomically clear a set of bits from XICU_MSK_PTI + * XICU_PTI_ACT get active PTI lines for this output line + */ +#define XICU_MSK_PTI_FUNC 0x04 /* R/W */ +#define XICU_MSK_PTI(outidx) __XICU_RIDX(XICU_MSK_PTI_FUNC, outidx) + +#define XICU_MSK_PTI_E_FUNC 0x05 /* W */ +#define XICU_MSK_PTI_E(outidx) __XICU_RIDX(XICU_MSK_PTI_E_FUNC, outidx) + +#define XICU_MSK_PTI_D_FUNC 0x06 /* W */ +#define XICU_MSK_PTI_D(outidx) __XICU_RIDX(XICU_MSK_PTI_D_FUNC, outidx) + +#define XICU_PTI_ACT_FUNC 0x06 /* R */ +#define XICU_PTI_ACT(outidx) __XICU_RIDX(XICU_PTI_ACT_FUNC, outidx) + +/* + * Multiplex hardware input lines to output lines: + * XICU_MSK_HWI mask register for outidx line (bit to 1 enable interrupt) + * XICU_MSK_HWI_E atomically add a set of bits to XICU_MSK_HWI + * XICU_MSK_HWI_D atomically clear a set of bits from XICU_MSK_HWI + * XICU_HWI_ACT get active HWI lines for this output line + */ +#define XICU_MSK_HWI_FUNC 0x08 /* R/W */ +#define XICU_MSK_HWI(outidx) __XICU_RIDX(XICU_MSK_HWI_FUNC, outidx) + +#define XICU_MSK_HWI_E_FUNC 0x09 /* W */ +#define XICU_MSK_HWI_E(outidx) __XICU_RIDX(XICU_MSK_HWI_E_FUNC, outidx) + +#define XICU_MSK_HWI_D_FUNC 0x0a /* W */ +#define XICU_MSK_HWI_D(outidx) __XICU_RIDX(XICU_MSK_HWI_D_FUNC, outidx) + +#define XICU_HWI_ACT_FUNC 0x0a /* R */ +#define XICU_HWI_ACT(outidx) __XICU_RIDX(XICU_HWI_ACT_FUNC, outidx) + +/* + * Multiplex hardware input lines to output lines: + * XICU_MSK_WTI mask register for outidx line (bit to 1 enable interrupt) + * XICU_MSK_WTI_E atomically add a set of bits to XICU_MSK_WTI + * XICU_MSK_WTI_D atomically clear a set of bits from XICU_MSK_WTI + * XICU_WTI_ACT get active WTI lines for this output line + */ +#define XICU_MSK_WTI_FUNC 0x0c /* R/W */ +#define XICU_MSK_WTI(outidx) __XICU_RIDX(XICU_MSK_WTI_FUNC, outidx) + +#define XICU_MSK_WTI_E_FUNC 0x0d /* W */ +#define XICU_MSK_WTI_E(outidx) __XICU_RIDX(XICU_MSK_WTI_E_FUNC, outidx) + +#define XICU_MSK_WTI_D_FUNC 0x0e /* W */ +#define XICU_MSK_WTI_D(outidx) __XICU_RIDX(XICU_MSK_WTI_D_FUNC, outidx) + +#define XICU_WTI_ACT_FUNC 0x0e /* R */ +#define XICU_WTI_ACT(outidx) __XICU_RIDX(XICU_WTI_ACT_FUNC, outidx) + +/* source priority encoder for outpout lines */ +#define XICU_PRIO_FUNC 0x0f +#define XICU_PRIO(outidx) __XICU_RIDX(XICU_PRIO_FUNC, outidx) + +#define XICU_PRIO_PTI 0x00000001 /* Timer interrrupt pending */ +#define XICU_PRIO_PTII(val) ((val) >> 8 & 0x1f) /* first PTI pending */ +#define XICU_PRIO_HWI 0x00000002 /* Hardware interrrupt pending */ +#define XICU_PRIO_HWII(val) ((val) >> 16 & 0x1f) /* first HWI pending */ +#define XICU_PRIO_WTI 0x00000004 /* write-triggered interrrupt pending */ +#define XICU_PRIO_WTII(val) ((val) >> 24 & 0x1f) /* first WTI pending */ + +#define XICU_PRIO_PENDING (XICU_PRIO_PTI|XICU_PRIO_HWI|XICU_PRIO_WTI) Index: /branches/fault_tolerance/softs/tests_cc_vcache/run_tests =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/run_tests (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/run_tests (revision 724) @@ -0,0 +1,36 @@ +#!/bin/sh + +PATH=${PATH}:/dsk/l1/misc/bouyer/tmp/tsarmips/obj/netbsd-5/tooldir/bin +export PATH +SOCLIB_TTY=TERM +export SOCLIB_TTY + +for dir in test_sanity test_exceptions test_mmu_basic \ + test_excep_ls test_excep_ls_delayslot test_excep_ls_llsc \ + test_excep_if test_excep_if_delayslot test_excep_if_llsc \ + test_exception_epc_modify \ + test_dtlb_inval test_dtlb_inval2 test_dtlb_inval3 \ + test_itlb_inval test_itlb_inval2 \ + test_idtlb_inval test_idtlb_inval2 test_idtlb_inval3 test_idtlb_inval4 \ + test_dtlb_ptprinval test_itlb_ptprinval test_idtlb_ptprinval \ + test_sync \ + test_llsc test_sc_no_ll test_sc_update_cache test_pte_llsc \ + test_interrupt \ + test_interrupt_epc_modify \ + test_xicu_timer \ + test_interrupt_delayslot \ + test_interrupt_mask \ + test_interrupt_external_mask \ + test_excep_cop test_excep_cop_delayslot test_excep_cop1 \ + test_syscall test_syscall_delayslot \ + test_breakpoint test_breakpoint_delayslot \ + test_ri test_ri_delayslot \ + test_ao test_ao_delayslot \ + test_trap test_trap_delayslot \ + test_dcache_inval_pa test_icache_inval_pa \ + test_pte2i_ref test_pte2lw_ref test_pte2ll_ref test_pte2sw_dirty test_pte2sc_dirty \ + test_dma_basic test_dma_unaligned \ + ; do + echo -n ${dir}": " + (cd $dir && ./run) +done Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_ao/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_ao/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_ao/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_ao/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_ao/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_ao/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400002 cause 0x00000030 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_ao/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_ao/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_ao/test.S (revision 724) @@ -0,0 +1,63 @@ +/* + * arithmetic overflow test: check that a add can generates an exception + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + la a0, 0x7fffffff + li a1, 0x02 + add a0, a0, a1 + EXIT(2) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') +#we should end there + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +usrstr: .ascii "usrmode\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_ao_delayslot/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_ao_delayslot/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_ao_delayslot/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_ao_delayslot/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_ao_delayslot/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_ao_delayslot/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400002 cause 0x80000030 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_ao_delayslot/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_ao_delayslot/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_ao_delayslot/test.S (revision 724) @@ -0,0 +1,84 @@ +/* + * arithmetic overflow test: check that a overflow in a delay slot is + * properly handled + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + la a0, 0x7fffffff + li a1, 0x02 + j exit + add a0, a0, a1 + /* we should not get there, */ + EXIT(2) + .globl exit +exit: + move a0, v0 + PRINTX + PUTCHAR(' ') + move a0, v1 + PRINTX + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') + la a0, exit + mtc0 a0, COP0_EXPC + li v0, MAGIC1 + li v1, MAGIC2 + li a3, 1 + eret + nop + +#we should not end there + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +usrstr: .ascii "usrmode\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_breakpoint/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_breakpoint/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_breakpoint/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_breakpoint/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_breakpoint/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_breakpoint/run (revision 724) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400002 cause 0x00000024 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^0x0000DEAD 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_breakpoint/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_breakpoint/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_breakpoint/test.S (revision 724) @@ -0,0 +1,86 @@ +/* + * breakpoint test: check that a breakpoint generates an exception, and we can + * return + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + nop + nop + nop + break + bne a3, zero, exit + nop + /* we should not get there, a3 is not 0 */ + EXIT(2) +exit: + move a0, v0 + PRINTX + PUTCHAR(' ') + move a0, v1 + PRINTX + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') + mfc0 a0, COP0_EXPC + addiu a0, a0, 4 + mtc0 a0, COP0_EXPC + li v0, MAGIC1 + li v1, MAGIC2 + li a3, 1 + eret + nop + +#we should not end there + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +usrstr: .ascii "usrmode\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_breakpoint_delayslot/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_breakpoint_delayslot/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_breakpoint_delayslot/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_breakpoint_delayslot/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_breakpoint_delayslot/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_breakpoint_delayslot/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400002 cause 0x80000024 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_breakpoint_delayslot/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_breakpoint_delayslot/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_breakpoint_delayslot/test.S (revision 724) @@ -0,0 +1,85 @@ +/* + * breakpoint test: check that a breakpoint in a delay slot is properly handled + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + nop + nop + nop + j exit + break + nop + /* we should not get there, */ + EXIT(2) + .globl exit +exit: + move a0, v0 + PRINTX + PUTCHAR(' ') + move a0, v1 + PRINTX + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') + la a0, exit + mtc0 a0, COP0_EXPC + li v0, MAGIC1 + li v1, MAGIC2 + li a3, 1 + eret + nop + +#we should not end there + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +usrstr: .ascii "usrmode\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_dcache_inval_pa/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_dcache_inval_pa/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_dcache_inval_pa/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_dcache_inval_pa/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_dcache_inval_pa/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_dcache_inval_pa/run (revision 724) @@ -0,0 +1,38 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started before DMA 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^mmu started after DMA 0x0000F00D$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^mmu started after FLUSH 0x0000F00D$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 3 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_dcache_inval_pa/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_dcache_inval_pa/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_dcache_inval_pa/test.S (revision 724) @@ -0,0 +1,136 @@ +/* + * cache inval test: check that VC_DCACHE_INVAL_PA does the job + * on a cc_vcache, the cache invalidation/update should be done by hardware + * and VC_DCACHE_INVAL_PA should not be needed. + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr_a) + la t0, testval + lw a0, 0(t0); + PRINTX + PUTCHAR('\n') + la a1, DMA_BASE + la a0, testval2 + sw a0, DMA_SRC(a1) + la a0, testval + sw a0, DMA_DST(a1) + li a0, 4 + sw a0, DMA_LEN(a1) /* start DMA */ +loop: + lw a0, DMA_LEN(a1) + bne a0, zero, loop; + nop + + PRINT(mmustr_b) + la t0, testval + lw a0, 0(t0); + PRINTX + PUTCHAR('\n') + + la a0, testval + mtc2 a0, VC_DATA_LO + mtc2 zero, VC_DATA_HI + mtc2 zero, VC_DCACHE_INVAL_PA + nop + + PRINT(mmustr_c) + la t0, testval + lw a0, 0(t0); + PRINTX + PUTCHAR('\n') + + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(3) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr_a: .ascii "mmu started before DMA \0" +mmustr_b: .ascii "mmu started after DMA \0" +mmustr_c: .ascii "mmu started after FLUSH \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data +data_a: + .word MAGIC1 +testval: + .word MAGIC2 +data_b: + .word MAGIC3 +testval2: + .word MAGIC4 + .globl pte2_a + +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word 0x0000 >> 12 /* check real value of data_a */ + .org pte2_a + 4092 + .word 0 + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_T | (0x2000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */ + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + (DMA_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (DMA_BASE >> 21) /* map PA 0xe8000000 at VA 0xe0000000 */ Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_dma_basic/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_dma_basic/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_dma_basic/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_dma_basic/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_dma_basic/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_dma_basic/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^after DMA 0x0000F00D 0x0000F00D 0x0000BEEF 0x0000DEAD 0x0000DEAD$" run.out > /dev/null + if [ $? -eq 0 ]; then + return 0; + fi + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_dma_basic/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_dma_basic/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_dma_basic/test.S (revision 724) @@ -0,0 +1,135 @@ +/* + * basic DMA check: check that the DMA engine works and and doens't + * clobbers memory + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(mmustr_a) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la t0, testval + lw a0, 0(t0); + PRINTX + PUTCHAR(' ') + la t0, testval2 + lw a0, 0(t0); + PRINTX + PUTCHAR('\n') + la t0, testval + la t1, testval3 + lw a0, 0(t0); + sw a0, 0(t1) + + la a1, DMA_BASE + la a0, tstsrc + sw a0, DMA_SRC(a1) + la a0, tstdst + sw a0, DMA_DST(a1) + la a0, 0x18 + sw a0, DMA_LEN(a1) /* start DMA */ +loop: + lw a0, DMA_LEN(a1) + bne a0, zero, loop; + nop + sw a0, DMA_RESET(a1) /* reset DMA */ + + la a0, testval2 + sw a0, DMA_SRC(a1) + la a0, testval + sw a0, DMA_DST(a1) + la a0, 0x4 + sw a0, DMA_LEN(a1) /* start DMA */ +loop2: + lw a0, DMA_LEN(a1) + bne a0, zero, loop2; + nop + sw a0, DMA_RESET(a1) /* reset DMA */ + + PRINT(mmustr_b) + la t0, testval + lw a0, 0(t0); + PRINTX + PUTCHAR(' ') + la t0, testval2 + lw a0, 0(t0); + PRINTX + PUTCHAR(' ') + la t0, testval3 + lw a0, 0(t0); + PRINTX + PUTCHAR(' ') + la t0, tstsrc + lw a0, 0(t0); + PRINTX + PUTCHAR(' ') + la t0, tstdst + lw a0, 0(t0); + PRINTX + PUTCHAR('\n') + + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(3) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr_a: .ascii "before DMA \0" +mmustr_b: .ascii "after DMA \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data +testval: + .word MAGIC2 +testval2: + .word MAGIC4 +testval3: + .word MAGIC4 +tstdst: + .word 0 + .org 0x1000 + .word 0 +tstsrc: + .word MAGIC1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_dma_unaligned/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_dma_unaligned/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_dma_unaligned/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_dma_unaligned/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_dma_unaligned/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_dma_unaligned/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^after DMA this is the test string unaligned and more than 64 chars long abcdefghijklmnopqrstuvwxyz ABCDEFGHIJKLMNOPQRSTUVWXYZ 123456789 abcdefghijklmnopqrstuvwxyz$" run.out > /dev/null + if [ $? -eq 0 ]; then + return 0; + fi + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_dma_unaligned/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_dma_unaligned/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_dma_unaligned/test.S (revision 724) @@ -0,0 +1,96 @@ +/* + * basic DMA check: check that the DMA engine works and and doens't + * clobbers memory + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(mmustr_a) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la t0, tstdst + sw zero, 0(t0); + PRINT(tstdst) + PUTCHAR('E') + PUTCHAR('\n') + + la a1, DMA_BASE + la a0, tstsrc + sw a0, DMA_SRC(a1) + la a0, tstdst + sw a0, DMA_DST(a1) + la a0, 160 #strlen(tstsrc) + sw a0, DMA_LEN(a1) /* start DMA */ +loop: + lw a0, DMA_LEN(a1) + bne a0, zero, loop; + nop + + PRINT(mmustr_b) + PRINT(tstdst) + + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(3) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr_a: .ascii "before DMA \0" +mmustr_b: .ascii "after DMA \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data +testval: + .word MAGIC2 +testval2: + .word MAGIC4 +testval3: + .word MAGIC4 +tstdst: + .word 0 + .org 0x1000 +testval4: + .word MAGIC1 +tstsrc: + .ascii "this is the test string unaligned and more than 64 chars long abcdefghijklmnopqrstuvwxyz ABCDEFGHIJKLMNOPQRSTUVWXYZ 123456789 abcdefghijklmnopqrstuvwxyz\n\0" Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_inval/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_inval/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_inval/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_inval/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_inval/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_inval/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started 0x0000BEEF status 0x00400002 cause 0x0000001C pc 0xBFC00080 badva 0x00200004$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_inval/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_inval/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_inval/test.S (revision 724) @@ -0,0 +1,117 @@ +/* + * dtlb inval: a write to VC_DTLB_INVAL should invalidate the corresponding + * dtlb entry. On a ccvcache, VC_DTLB_INVAL should not be needed, and + * the first access after clearing pte2_a should fail + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + la t0, testval + 0x00200000 + lw a0, 0(t0); + PRINTX + PUTCHAR(' ') + la a0, pte2_a + sw zero, 0(a0) /* invalidate PTE2 entry */ + sync + la t0, testval + 0x00200000 + lw a0, 0(t0); /* TLB entry not invalidated yet, we can do this */ + PRINTX + PUTCHAR('\n') + la t0, testval + 0x00200000 + mtc2 t0, VC_DTLB_INVAL /* invalidate VA */ + lw a0, 0(t0); /* now this should fail */ + PRINTX + PUTCHAR('\n') + + /* we should not get there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data + /* first 2 pages is data that will be switched my mmu switch */ +data_a: + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2_a +/* + * one PD with a level 2 PTP: we invalidate an entry in the PTP and + * check that the VA is no longer accessible + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word 0x0000 >> 12 /* check real value of data_a */ + .org pte2_a + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */ + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_inval2/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_inval2/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_inval2/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_inval2/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_inval2/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_inval2/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started 0x0000BEEF 0x0000DEAD$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_inval2/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_inval2/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_inval2/test.S (revision 724) @@ -0,0 +1,121 @@ +/* + * dtlb inval: a write to a PTE2 should invalidate the corresponding + * dtlb entry. + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + la t0, testval + 0x00200000 + lw a0, 0(t0); + PRINTX + PUTCHAR(' ') + la t0, pte2_a + la a0, 0x1000 >> 12 + sw a0, 4(t0) /* swap PTE2 entry */ +1: + ll a0, 0(t0) + la a0, PTE2_V | PTE2_C | PTE2_X + sc a0, 0(t0) + beqz a0, 1b + nop + + la t0, testval + 0x00200000 + lw a0, 0(t0); /* should get MAGIC1 */ + PRINTX + PUTCHAR('\n') + + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data + /* first 2 pages is data that will be switched my mmu switch */ +data_a: + .word MAGIC1 +testval: + .word MAGIC2 + .align 12 + .word MAGIC2 + .word MAGIC1 + .globl pte2_a +/* + * one PD with a level 2 PTP: we switch an entry in the PTP and + * check that the dtlb is invalidated + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word 0x0000 >> 12 /* check real value of data_a */ + .org pte2_a + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_T | (0x2000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */ + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_inval3/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_inval3/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_inval3/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_inval3/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_inval3/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_inval3/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "mmu started 0x0000BEEF 0xAC400000 0x0000900D status 0x00400002 cause 0x0000001C pc 0xBFC000D4 badva 0x00200004" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_inval3/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_inval3/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_inval3/test.S (revision 724) @@ -0,0 +1,128 @@ +/* + * dtlb inval: a write to a PTE2 should invalidate the corresponding + * dtlb entry. Check that this is true is we change only the write flag + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + la t0, testval + 0x00200000 + lw a0, 0(t0); + PRINTX + PUTCHAR(' ') + la t0, testval + 0x00200000 + la a0, MAGIC3 + sw a0, 0(t0) + la t0, pte2_a +1: + ll a0, 0(t0) + la a1, ~PTE2_W + and a1, a0, a1 + sc a1, 0(t0) + beqz a1, 1b + nop + PRINTX + PUTCHAR(' ') + + la t0, testval + 0x00200000 + lw a0, 0(t0); /* should get MAGIC3 */ + PRINTX + PUTCHAR(' ') + la t0, testval + 0x00200000 + la a0, MAGIC1 + sw a0, 0(t0) + + /* we should not get there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data + /* first 2 pages is data that will be switched my mmu switch */ +data_a: + .word MAGIC1 +testval: + .word MAGIC2 + .align 12 + .word MAGIC2 + .word MAGIC1 + .globl pte2_a +/* + * one PD with a level 2 PTP: we switch an entry in the PTP and + * check that the dtlb is invalidated + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_W + .word 0x0000 >> 12 /* check real value of data_a */ + .org pte2_a + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_T | (0x2000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */ + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_ptprinval/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_ptprinval/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_ptprinval/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_ptprinval/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_ptprinval/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_ptprinval/run (revision 724) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started ptpr_b 0x0000F00D$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^mmu started ptpr_a 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_ptprinval/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_ptprinval/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_dtlb_ptprinval/test.S (revision 724) @@ -0,0 +1,145 @@ +/* + * dtlb inval on PTPR write: check that no stale entry exists in the dtlb + * after MMU context swicth + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_b + srl a0, a0, 13 + mtc2 a0, VC_PTPR # PTPR <= pte1_b + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr_b) + la t0, testval + 0x00200000 + lw a0, 0(t0); + PRINTX # print MAGIC3 + PUTCHAR('\n') + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR # PTPR <= pte1_a + nop + PRINT(mmustr_a) + la t0, testval + 0x00200000 + lw a0, 0(t0); + PRINTX # print MAGIC1 + PUTCHAR('\n') + + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(3) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr_a: .ascii "mmu started ptpr_a \0" +mmustr_b: .ascii "mmu started ptpr_b \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data + /* first 2 pages is data that will be switched my mmu switch */ +data_a: + .word MAGIC1 +testval: + .word MAGIC2 + .org data_a + 0x1000 +data_b: + .word MAGIC3 + .word MAGIC4 + +/* + * two PD with two different PTE2 for code: check that dtlb points to + * the right one by loading 2 different data at the same virtual address + */ + .globl pte2_a +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word 0x0000 >> 12 /* check real value of data_a */ + + .org pte2_a + 4092 + .word 0 + .globl pte2_b +pte2_b: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word 0x1000 >> 12 /* check real value of data_b */ + + .org pte2_b + 4092 + .word 0 + + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_T | (0x2000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */ + + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 + .globl pte1_b +pte1_b: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_T | (0x3000 >> 12) /* map PA 0x1000 at VA 0x00200000 via pte2_b */ + .org pte1_b + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1_b + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_b + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_b + 8188 + .word 0 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_cop/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_cop/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_cop/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_cop/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_cop/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_cop/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400002 cause 0x1000002C pc 0xBFC0002C badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_cop/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_cop/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_cop/test.S (revision 724) @@ -0,0 +1,71 @@ +/* + * coproc unusable exception test: we take an exception on COP1 use + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + li t3, MAGIC1 + mtc1 t3,$f2 + mfc1 a0,$f2 + PRINTX + PUTCHAR('\n') + nop + nop + nop + nop + +1: + /* we should not get there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') + + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_cop1/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_cop1/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_cop1/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_cop1/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_cop1/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_cop1/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400002 cause 0x1000002C pc 0xBFC00030 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_cop1/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_cop1/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_cop1/test.S (revision 724) @@ -0,0 +1,71 @@ +/* + * trap test: check that we get a trap on FPU access though [ls][dw]c1 + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV), enable cop1 */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, div1; + lwc1 $f0, 0(a0) + PRINTX + PUTCHAR('\n') + EXIT(2) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') +#we should end there + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +usrstr: .ascii "usrmode\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl div1 +div1: + .float 10.0 + .globl div2 +div2: + .float 0.0 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_cop_delayslot/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_cop_delayslot/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_cop_delayslot/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_cop_delayslot/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_cop_delayslot/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_cop_delayslot/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400002 cause 0x9000002C pc 0xBFC00028 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_cop_delayslot/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_cop_delayslot/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_cop_delayslot/test.S (revision 724) @@ -0,0 +1,65 @@ +/* + * coproc unusable exception test: 0x80000000 bit is set in cause register + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + j 1f + mtc1 t3,$f2 + nop + +1: + /* we should not get there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') + + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if/Makefile (revision 724) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if/ldscript =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if/ldscript (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if/ldscript (revision 724) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if/run (revision 724) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^0x00000004: 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^status 0x00400002 cause 0x00000018 pc 0xBFC01000 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if/test.S (revision 724) @@ -0,0 +1,135 @@ +/* + * ifetch bus fault exception test: we can restart the faulting instruction + * We use the MMU to cause fault. + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00200000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + + move a1, zero + la s0, testval + jal doload + move a0, s0 + PRINTX + PUTCHAR(':') + PUTCHAR(' ') + move a0, a1 + PRINTX + PUTCHAR('\n') + + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + /* don't clobber a0 and ra */ + addiu sp, sp, -8 + sw a0, 4(sp) + sw ra, 8(sp) + + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* map VA 0xbfc01000 at PA 0xbfc01000 */ + la t0, pte2 + VADDR_TO_PTE2I(0xbfc01000) * 8 + la a0, (0xbfc01000 >> PTE2_SHIFT) + sw a0, 4(t0) + la a0, (PTE2_V | PTE2_C | PTE2_X) + sw a0, 0(t0) + /* la a0, 0xbfc01000 + mtc2 a0, VC_ITLB_INVAL */ + + lw a0, 4(sp) + lw ra, 8(sp) + addiu sp, sp, 8 + eret + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started\n\0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + /* + * we use a ldscript trick here, to load this function at + * the appropriate address + */ + .section .text2, "ax" + .globl doload +doload: + jr ra + lw a1, 0(s0) /* this should trigger the exception */ + + /* we should not get there */ + nop + nop + EXIT(1) + + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2 +pte2: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .org pte2 + 4092 + .globl pte1 +pte1: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word 0x0 + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of PTE2 !!! */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if_delayslot/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if_delayslot/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if_delayslot/Makefile (revision 724) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if_delayslot/ldscript =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if_delayslot/ldscript (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if_delayslot/ldscript (revision 724) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000) - 4; + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if_delayslot/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if_delayslot/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if_delayslot/run (revision 724) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^0x00000004: 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^status 0x00400002 cause 0x80000018 pc 0xBFC00FFC badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if_delayslot/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if_delayslot/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if_delayslot/test.S (revision 724) @@ -0,0 +1,135 @@ +/* + * ifetch bus fault exception test: we can restart the faulting instruction + * when the fault occurs in the branch delay slot. + * We use the MMU to cause fault. + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00200000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + + move a1, zero + la s0, testval + jal doload + move a0, s0 + PRINTX + PUTCHAR(':') + PUTCHAR(' ') + move a0, a1 + PRINTX + PUTCHAR('\n') + + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + /* don't clobber a0 and ra */ + addiu sp, sp, -8 + sw a0, 4(sp) + sw ra, 8(sp) + + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* map VA 0xbfc01000 at PA 0xbfc01000 */ + la t0, pte2 + VADDR_TO_PTE2I(0xbfc01000) * 8 + la a0, (0xbfc01000 >> PTE2_SHIFT) + sw a0, 4(t0) + la a0, (PTE2_V | PTE2_C | PTE2_X) + sw a0, 0(t0) + /* la a0, 0xbfc01000 + mtc2 a0, VC_ITLB_INVAL */ + + lw a0, 4(sp) + lw ra, 8(sp) + addiu sp, sp, 8 + eret + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started\n\0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + /* + * we use a ldscript trick here, to load this function at + * the appropriate address + */ + .section .text2, "ax" + .globl doload +doload: + jr ra + lw a1, 0(s0) /* this should trigger the exception */ + + /* we should not get there */ + nop + nop + EXIT(1) + + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2 +pte2: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .org pte2 + 4092 + .globl pte1 +pte1: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word 0x0 + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of PTE2 !!! */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if_llsc/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if_llsc/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if_llsc/Makefile (revision 724) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if_llsc/ldscript =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if_llsc/ldscript (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if_llsc/ldscript (revision 724) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if_llsc/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if_llsc/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if_llsc/run (revision 724) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^0x00000004: 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^status 0x00400002 cause 0x00000018 pc 0xBFC01000 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if_llsc/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if_llsc/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_if_llsc/test.S (revision 724) @@ -0,0 +1,136 @@ +/* + * ifetch bus fault exception test: we can restart the faulting instruction + * We use the MMU to cause fault. + * Match what NetBSD does for page table update: sw for ppn, ll/sc for flags + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00200000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + + move a1, zero + la s0, testval + jal doload + move a0, s0 + PRINTX + PUTCHAR(':') + PUTCHAR(' ') + move a0, a1 + PRINTX + PUTCHAR('\n') + + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + /* don't clobber a0 and ra */ + addiu sp, sp, -8 + sw a0, 4(sp) + sw ra, 8(sp) + + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* map VA 0xbfc01000 at PA 0xbfc01000 */ + la t0, pte2 + VADDR_TO_PTE2I(0xbfc01000) * 8 + la a0, (0xbfc01000 >> PTE2_SHIFT) + sw a0, 4(t0) +1: + ll a0, 0(t0) + la a0, (PTE2_V | PTE2_C | PTE2_X) + sc a0, 0(t0) + beqz a0, 1b + + lw a0, 4(sp) + lw ra, 8(sp) + addiu sp, sp, 8 + eret + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started\n\0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + /* + * we use a ldscript trick here, to load this function at + * the appropriate address + */ + .section .text2, "ax" + .globl doload +doload: + jr ra + lw a1, 0(s0) /* this should trigger the exception */ + /* we should not get there */ + nop + nop + EXIT(1) + + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2 +pte2: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .org pte2 + 4092 + .globl pte1 +pte1: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word 0x0 + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of PTE2 !!! */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_intr/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_intr/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_intr/Makefile (revision 724) @@ -0,0 +1,3 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc +CFLAGS+= -DINTERRUPT_DELAY=${INTERRUPT_DELAY} Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_intr/ldscript =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_intr/ldscript (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_intr/ldscript (revision 724) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_intr/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_intr/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_intr/run (revision 724) @@ -0,0 +1,44 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^end 0x0000BEEF 0x00000001$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^status 0x00400403 cause 0x00000018 pc 0x80000000 badva 0x00000000 xicu 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^status 0x00400403 cause 0x00000400 pc 0x80000000 badva 0x00000000 xicu 0x00000001$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 3 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} +echo +i=1180 +while true; do + echo -n " DELAY=$i: " + make INTERRUPT_DELAY=$i --quiet || exit 1 + ${SIMUL} > run.out 2>&1 + if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + else + echo "test FAILED" + exit 1 + fi + else + echo "test FAILED" + exit 1 + fi + i=$((i+1)) +done + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_intr/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_intr/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_intr/test.S (revision 724) @@ -0,0 +1,201 @@ +/* + * Check interrupt while in trap handler. + * Cache is enabled so we have one instruction/cycle + */ +#include +#include +#include +#include + +#define DOLOAD_ADDR 0x80000000 + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00200000 - 16 + + /* reset cause, make sure IV is off */ + mtc0 zero, COP0_CAUSE + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(startstr) + + /* program xicu */ + la t0, XICU_BASE + /* clear pending interrupt */ + lw a0, XICU_PTI_ACK(0)(t0) + /* route PTI0 to irq 0 */ + li a0, 1 << 0 + sw a0, XICU_MSK_PTI_E(0)(t0) + /* init s0 */ + li s0, MAGIC2 + /* + * interrupt in INTERRUPT_DELAY cycles. + */ + li a0, INTERRUPT_DELAY + sw a0, XICU_PTI_PER(0)(t0) + /* clear pending interrupt */ + lw a0, XICU_PTI_ACK(0)(t0) + /* reset cop0 status (keep BEV), enable interrupt 0 */ + lui a0, 0x0040; + addiu a0, 0x0401; + mtc0 a0, COP0_STATUS + nop + nop + nop + nop + nop + + nop + move a1, zero + la s0, DOLOAD_ADDR + jalr s0 + nop + j end + nop + /* we should not end there */ + EXIT(1) + +end: + PRINT(endstr) + move a0, a1 + PRINTX + PUTCHAR(' ') + la a0, myvar + lw a0, 0(a0) + PRINTX + PUTCHAR('\n') + EXIT(0) + + .globl excep +excep: + .set noreorder + /* don't clobber a0 and ra */ + addiu sp, sp, -8 + sw a0, 4(sp) + sw ra, 8(sp) + + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + move s0, a0 + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PRINT(xicustr) + la t0, XICU_BASE + lw a0, XICU_PRIO(0)(t0) + PRINTX + PUTCHAR('\n') + /* map VA DOLOAD_ADDR at PA 0xbfc01000 */ + la t0, pte22 + VADDR_TO_PTE2I(DOLOAD_ADDR) * 8 + la a0, (0xbfc01000 >> PTE2_SHIFT) + sw a0, 4(t0) + la a0, (PTE2_V | PTE2_C | PTE2_X) + sw a0, 0(t0) + mtc2 zero, VC_DCACHE_FLUSH /* flush the whole data cache */ + + andi a0, s0, 0xff00 + beq a0, zero, notintr + nop + + /* disable timer0 */ + la t0, XICU_BASE + sw zero, XICU_PTI_PER(0)(t0) +notintr: + la a1, myvar + la a0, 0(a1) + beq a0, zero, noex + nop + EXIT(2) +noex: + li a0, 1 + sw a0, 0(a1) + lw a0, 4(sp) + lw ra, 8(sp) + addiu sp, sp, 8 + eret + /* we should not end there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +xicustr: .ascii " xicu \0" +startstr: .ascii "start\n\0" +endstr: .ascii "end \0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + /* + * we use a ldscript trick here, to load this function at + * the appropriate address + */ + .section .text2, "ax" + .globl doload +doload: + la s0, testval + jr ra + lw a1, 0(s0) /* this should trigger the exception */ + /* we should not get there */ + EXIT(1) + nop + .data +myvar: .word 0 +testval: + .word MAGIC2 + .globl pte2 +pte2: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .org pte2 + 4092 + .globl pte22 +pte22: + .align 12 + .word 0 + .word 0 + .org pte22 + 4092 + .globl pte1 +pte1: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .org pte1 + (DOLOAD_ADDR >> 21) * 4 + .word PTE1_V | PTE1_T | (0x2000 >> 12) /* map VA DOLOAD_ADDR with 4k page: check real address of PTE22 !!! */ + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of PTE2 !!! */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1 + (XICU_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (XICU_BASE >> 21) /* map PA 0xd2000000 at VA 0xd2000000 */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 + .word 0 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_ls/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_ls/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_ls/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_ls/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_ls/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_ls/run (revision 724) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^0x00000004: 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^status 0x00400002 cause 0x0000001C pc 0xBFC00058 badva 0x00000004$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_ls/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_ls/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_ls/test.S (revision 724) @@ -0,0 +1,103 @@ +/* + * load/store bus fault exception test: we can restart the faulting instruction + * We use the MMU to cause fault + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + + /* 0x00000000 not mapped yet: we fault, load the MMU and retry */ + move a1, zero + la s0, testval + lw a1, 0(s0) /* this should trigger the exception */ + move a0, s0 + PRINTX + PUTCHAR(':') + PUTCHAR(' ') + move a0, a1 + PRINTX + PUTCHAR('\n') + + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* map VA 0 at PA 0: just copy entry for 0x00200000 */ + la t0, pte1 + 0x00200000 + lw a0, 4(t0) + sw a0, 0(t0) + /* mtc2 zero, VC_DTLB_INVAL */ + eret + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started\n\0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte1 +pte1: + .align 13 + .word 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0x00200000 */ + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 + .word 0 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_ls_delayslot/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_ls_delayslot/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_ls_delayslot/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_ls_delayslot/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_ls_delayslot/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_ls_delayslot/run (revision 724) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^0x00000004: 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^status 0x00400002 cause 0x8000001C pc 0xBFC000AC badva 0x00000004$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_ls_delayslot/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_ls_delayslot/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_ls_delayslot/test.S (revision 724) @@ -0,0 +1,123 @@ +/* + * load/store bus fault exception test: we can restart the jump when the + * instruction in the delay slot takes a fault. + * We use the MMU to cause fault + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + + /* 0x00000000 not mapped yet: we fault, load the MMU and retry */ + move a1, zero + la s0, testval + jal doload + move a0, s0 + PRINTX + PUTCHAR(':') + PUTCHAR(' ') + move a0, a1 + PRINTX + PUTCHAR('\n') + + /* we should get there */ + EXIT(0) + + .globl doload +doload: + nop + nop + jr ra + lw a1, 0(s0) /* this should trigger the exception */ + + /* we should not get there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + /* don't clobber a0 and ra */ + addiu sp, sp, -8 + sw a0, 4(sp) + sw ra, 8(sp) + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* map VA 0 at PA 0: just copy entry for 0x00200000 */ + la t0, pte1 + 0x00200000 + lw a0, 4(t0) + sw a0, 0(t0) + /* mtc2 zero, VC_DTLB_INVAL */ + lw a0, 4(sp) + lw ra, 8(sp) + addiu sp, sp, 8 + eret + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started\n\0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte1 +pte1: + .align 13 + .word 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0x00200000 */ + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 + .word 0 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_ls_llsc/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_ls_llsc/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_ls_llsc/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_ls_llsc/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_ls_llsc/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_ls_llsc/run (revision 724) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^0x00000004: 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^status 0x00400002 cause 0x0000001C pc 0xBFC00058 badva 0x00000004$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_ls_llsc/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_ls_llsc/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_excep_ls_llsc/test.S (revision 724) @@ -0,0 +1,107 @@ +/* + * load/store bus fault exception test: we can restart the faulting instruction + * We use the MMU to cause fault + * Match what NetBSD does for page table update: sw for ppn, ll/sc for flags + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + + /* 0x00000000 not mapped yet: we fault, load the MMU and retry */ + move a1, zero + la s0, testval + lw a1, 0(s0) /* this should trigger the exception */ + move a0, s0 + PRINTX + PUTCHAR(':') + PUTCHAR(' ') + move a0, a1 + PRINTX + PUTCHAR('\n') + + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* map VA 0 at PA 0: just copy entry for 0x00200000 */ + la t0, pte1 + 0x00200000 +1: + ll a0, 0(t0) + lw a0, 4(t0) + sc a0, 0(t0) + beqz a0, 1b + /* mtc2 zero, VC_DTLB_INVAL */ + eret + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started\n\0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte1 +pte1: + .align 13 + .word 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0x00200000 */ + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 + .word 0 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_exception_epc_modify/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_exception_epc_modify/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_exception_epc_modify/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_exception_epc_modify/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_exception_epc_modify/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_exception_epc_modify/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^eret$" run.out > /dev/null + if [ $? -eq 0 ]; then + return 0; + fi + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_exception_epc_modify/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_exception_epc_modify/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_exception_epc_modify/test.S (revision 724) @@ -0,0 +1,71 @@ +/* + * Check that on return from exception the modified EPC is handled. + * We use a load to an unaligned address to trigger the exception. + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + li a0, 1 + lw a0, 0(a0) /* fault */ + + /* we shouldn't get there */ + EXIT(1) + + .globl exret + +exret: + PRINT(eretstr) + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + la a0, exret + mtc0 a0, COP0_EXPC + eret + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +eretstr: .ascii "eret\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data +myvar: .word 0 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_exceptions/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_exceptions/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_exceptions/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_exceptions/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_exceptions/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_exceptions/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400006 cause 0x00000010 pc 0xBFC0001C badva 0x00000001$" run.out > /dev/null + if [ $? -eq 0 ]; then + return 0; + fi + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_exceptions/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_exceptions/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_exceptions/test.S (revision 724) @@ -0,0 +1,60 @@ +/* + * Check that the exeption vector is called on exception. + * We use a load to an unaligned address to trigger the exception. + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + li a0, 1 + lw a0, 0(a0) /* fault */ + + /* we shouldn't get there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + li a0, '\n' + sb a0, 0(k0) + + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data +myvar: .word 0 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_fpe_delayslot/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_fpe_delayslot/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_fpe_delayslot/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_fpe_delayslot/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_fpe_delayslot/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_fpe_delayslot/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400002 cause 0x80000034 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_fpe_delayslot/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_fpe_delayslot/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_fpe_delayslot/test.S (revision 724) @@ -0,0 +1,92 @@ +/* + * trap test: check that a trap in a delay slot is + * properly handled + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV), enable cop1 */ + lui a0, 0x2040; + mtc0 a0, COP0_STATUS + + la a0, div1 + lwc1 $f2, 0(a0) + la a0, div2 + lwc1 $f0, 0(a0) + j exit + div.s $f0, $f0, $f2 + /* we should not get there, */ + EXIT(2) + .globl exit +exit: + move a0, v0 + PRINTX + PUTCHAR(' ') + move a0, v1 + PRINTX + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') + la a0, exit + mtc0 a0, COP0_EXPC + li v0, MAGIC1 + li v1, MAGIC2 + li a3, 1 + eret + nop + +#we should not end there + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +usrstr: .ascii "usrmode\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 +div1: + .float 10.0 + .globl div2 +div2: + .float 0.0 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_fpediv/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_fpediv/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_fpediv/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_fpediv/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_fpediv/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_fpediv/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400002 cause 0x00000038 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_fpediv/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_fpediv/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_fpediv/test.S (revision 724) @@ -0,0 +1,81 @@ +/* + * trap test: check that a we can generate a trap from FPE instruction + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV), enable cop1 */ + lui a0, 0x2040; + mtc0 a0, COP0_STATUS + /* enable COP1 exceptions */ + li a0, 0x0f80 + ctc1 a0, $31 +#if 0 + li a0, 0xf000 + ctc1 a0, $26 +#endif + la a0, div1 + lwc1 $f2, 0(a0) + la a0, div2 + lwc1 $f0, 0(a0) + div.s $f0, $f2, $f0 + cfc1 a0, $31 + PRINTX + PUTCHAR('\n') + EXIT(2) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') +#we should end there + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +usrstr: .ascii "usrmode\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl div1 +div1: + .float 10.0 + .globl div2 +div2: + .float 0.0 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_icache_inval_pa/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_icache_inval_pa/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_icache_inval_pa/Makefile (revision 724) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_icache_inval_pa/ldscript =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_icache_inval_pa/ldscript (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_icache_inval_pa/ldscript (revision 724) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_icache_inval_pa/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_icache_inval_pa/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_icache_inval_pa/run (revision 724) @@ -0,0 +1,38 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started before DMA 0x0000DEAD$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^mmu started after DMA 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^mmu started after FLUSH 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 3 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_icache_inval_pa/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_icache_inval_pa/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_icache_inval_pa/test.S (revision 724) @@ -0,0 +1,167 @@ +/* + * cache inval test: check that VC_ICACHE_INVAL_PA does the job + * on a cc_vcache, the cache invalidation/update should be done by hardware + * and VC_ICACHE_INVAL_PA should not be needed. + */ +#include +#include +#include + +#define TEST_ADDRESS 0x200000 + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr_a) + #copy 'doload' to TEST_ADDRESS + la a1, DMA_BASE + la a0, doload + sw a0, DMA_SRC(a1) + la a0, TEST_ADDRESS + sw a0, DMA_DST(a1) + li a0, 8 + sw a0, DMA_LEN(a1) /* start DMA */ +loop1: + lw a0, DMA_LEN(a1) + bne a0, zero, loop1; + nop + sw zero, DMA_RESET(a1) + + la a0, TEST_ADDRESS + jalr a0 + nop + PRINTX + PUTCHAR('\n') + #copy 'doload2' to TEST_ADDRESS + la a1, DMA_BASE + la a0, doload2 + sw a0, DMA_SRC(a1) + la a0, TEST_ADDRESS + sw a0, DMA_DST(a1) + li a0, 8 + sw a0, DMA_LEN(a1) /* start DMA */ +loop2: + lw a0, DMA_LEN(a1) + bne a0, zero, loop2; + nop + sw zero, DMA_RESET(a1) + + PRINT(mmustr_b) + la a0, TEST_ADDRESS + jalr a0 + nop + PRINTX + PUTCHAR('\n') + + la a0, TEST_ADDRESS + mtc2 a0, VC_DATA_LO + mtc2 zero, VC_DATA_HI + mtc2 zero, VC_ICACHE_INVAL_PA + addi a0, a0, 4 + mtc2 a0, VC_DATA_LO + mtc2 zero, VC_DATA_HI + mtc2 zero, VC_ICACHE_INVAL_PA + nop + + PRINT(mmustr_c) + la a0, TEST_ADDRESS + jalr a0 + nop + PRINTX + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .globl doload +doload: + jr ra + li a0, MAGIC1 + /* we should not get there */ + EXIT(1) + nop + + .globl doload2 +doload2: + jr ra + li a0, MAGIC2 + /* we should not get there */ + EXIT(2) + nop + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(3) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr_a: .ascii "mmu started before DMA \0" +mmustr_b: .ascii "mmu started after DMA \0" +mmustr_c: .ascii "mmu started after FLUSH \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data + .word MAGIC1 +testval: + .word MAGIC2 + + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .org pte1_a + (TEST_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (TEST_ADDRESS >> 21) /* map PA 0x200000 at VA 0x200000, read-only/exec */ + .word 0x0 + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + (DMA_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (DMA_BASE >> 21) /* map PA 0xe8000000 at VA 0xe0000000 */ Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval/Makefile (revision 724) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval/ldscript =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval/ldscript (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval/ldscript (revision 724) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started 0x0000BEEF 0x0000DEAD 0x0000DEAD 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval/test.S (revision 724) @@ -0,0 +1,158 @@ +/* + * itlb inval: a write to a PTE2 should invalidate the corresponding + * itlb and dtlb entries. + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + /* cause a DTLB miss */ + la t0, roval + lw a0, 0(t0) + PRINTX + PUTCHAR(' ') + + /* cause a itlb miss */ + jal doload + nop + PRINTX + PUTCHAR(' ') + + la t0, pte2_a + la a0, (BOOT_ADDRESS+0x2000) >> 12 + sw a0, 12(t0) /* change PTE2 */ + sync +1: + ll a0, 8(t0) + la a0, PTE2_V | PTE2_C | PTE2_X + sc a0, 8(t0) + beqz a0, 1b + nop + + /* now we should get the second values */ + la t0, roval + lw a0, 0(t0) + PRINTX + PUTCHAR(' ') + + jal doload + nop + PRINTX + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + /* + * code that will be switched by MMU switch. + * we use a ldscript trick here, to load this function at + * the appropriate address + */ + .section .text2, "ax" + .globl doload +doload: + jr ra + li a0, MAGIC1 + /* we should not get there */ + EXIT(1) + nop +roval: .word MAGIC2 + .align 12 + .globl doload2 +doload2: + jr ra + li a0, MAGIC2 + /* we should not get there */ + EXIT(1) + nop +roval2: .word MAGIC1 + + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2_a + +/* + * one PD with a level 2 PTP: we change an entry in the PTP and + * check that the ITLB has been invalidated + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .word PTE2_V | PTE2_C | PTE2_X + .word (BOOT_ADDRESS+0x1000) >> 12 + .org pte2_a + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word 0x0 + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval2/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval2/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval2/Makefile (revision 724) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval2/ldscript =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval2/ldscript (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval2/ldscript (revision 724) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval2/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval2/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval2/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started 0x0000BEEF 0x0000DEAD 0x0000DEAD 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval2/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval2/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval2/test.S (revision 724) @@ -0,0 +1,160 @@ +/* + * itlb inval: a write to a PTE2 should invalidate the corresponding + * itlb and dtlb entries. + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + /* cause a DTLB miss */ + la t0, roval + lw a0, 0(t0) + PRINTX + PUTCHAR(' ') + + /* cause a itlb miss */ + jal doload + nop + PRINTX + PUTCHAR(' ') + + la t0, pte2_a + mtc2 t0, VC_DTLB_INVAL /* force tlb miss on write */ + la a0, (BOOT_ADDRESS+0x2000) >> 12 + sw a0, 12(t0) /* change PTE2 */ + sync +1: + ll a0, 8(t0) + mtc2 t0, VC_DTLB_INVAL /* force tlb miss on write */ + la a0, PTE2_V | PTE2_C | PTE2_X + sc a0, 8(t0) + beqz a0, 1b + nop + + /* now we should get the second values */ + la t0, roval + lw a0, 0(t0) + PRINTX + PUTCHAR(' ') + + jal doload + nop + PRINTX + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + /* + * code that will be switched by MMU switch. + * we use a ldscript trick here, to load this function at + * the appropriate address + */ + .section .text2, "ax" + .globl doload +doload: + jr ra + li a0, MAGIC1 + /* we should not get there */ + EXIT(1) + nop +roval: .word MAGIC2 + .align 12 + .globl doload2 +doload2: + jr ra + li a0, MAGIC2 + /* we should not get there */ + EXIT(1) + nop +roval2: .word MAGIC1 + + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2_a + +/* + * one PD with a level 2 PTP: we change an entry in the PTP and + * check that the ITLB has been invalidated + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .word PTE2_V | PTE2_C | PTE2_X + .word (BOOT_ADDRESS+0x1000) >> 12 + .org pte2_a + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word 0x0 + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval3/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval3/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval3/Makefile (revision 724) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval3/ldscript =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval3/ldscript (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval3/ldscript (revision 724) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval3/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval3/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval3/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started 0x0000BEEF 0x0000DEAD 0x0000DEAD 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval3/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval3/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval3/test.S (revision 724) @@ -0,0 +1,162 @@ +/* + * itlb inval: a write to a PTE2 should invalidate the corresponding + * itlb and dtlb entries. + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + /* cause a DTLB miss */ + la t0, roval + lw a0, 0(t0) + PRINTX + PUTCHAR(' ') + + /* cause a itlb miss */ + jal doload + nop + PRINTX + PUTCHAR(' ') + + la t0, pte2_a + mtc2 t0, VC_DATA_L /* force dcache miss on write */ + mtc2 zero, VC_DATA_H + mtc2 zero, VC_DCACHE_INVAL_PA + la a0, (BOOT_ADDRESS+0x2000) >> 12 + sw a0, 12(t0) /* change PTE2 */ + sync +1: + ll a0, 8(t0) + mtc2 t0, VC_DTLB_INVAL /* force tlb miss on write */ + la a0, PTE2_V | PTE2_C | PTE2_X + sc a0, 8(t0) + beqz a0, 1b + nop + + /* now we should get the second values */ + la t0, roval + lw a0, 0(t0) + PRINTX + PUTCHAR(' ') + + jal doload + nop + PRINTX + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + /* + * code that will be switched by MMU switch. + * we use a ldscript trick here, to load this function at + * the appropriate address + */ + .section .text2, "ax" + .globl doload +doload: + jr ra + li a0, MAGIC1 + /* we should not get there */ + EXIT(1) + nop +roval: .word MAGIC2 + .align 12 + .globl doload2 +doload2: + jr ra + li a0, MAGIC2 + /* we should not get there */ + EXIT(1) + nop +roval2: .word MAGIC1 + + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2_a + +/* + * one PD with a level 2 PTP: we change an entry in the PTP and + * check that the ITLB has been invalidated + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .word PTE2_V | PTE2_C | PTE2_X + .word (BOOT_ADDRESS+0x1000) >> 12 + .org pte2_a + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word 0x0 + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval4/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval4/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval4/Makefile (revision 724) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval4/ldscript =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval4/ldscript (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval4/ldscript (revision 724) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval4/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval4/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval4/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started 0x0000BEEF 0x0000DEAD 0x0000DEAD 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval4/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval4/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_inval4/test.S (revision 724) @@ -0,0 +1,166 @@ +/* + * itlb inval: a write to a PTD1 should invalidate the corresponding + * itlb and dtlb entries. + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + /* cause a DTLB miss */ + la t0, roval + lw a0, 0(t0) + PRINTX + PUTCHAR(' ') + + /* cause a itlb miss */ + jal doload + nop + PRINTX + PUTCHAR(' ') + + la t0, pte1_ac +1: + ll a0, 0(t0) + la a0, (0x2000 >> 12) | PTE1_V | PTE1_T /* check real address of pet2_b */ + sc a0, 0(t0) /* change PTD1 */ + beqz a0, 1b + nop + + /* now we should get the second values */ + la t0, roval + lw a0, 0(t0) + PRINTX + PUTCHAR(' ') + + jal doload + nop + PRINTX + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + /* + * code that will be switched by MMU switch. + * we use a ldscript trick here, to load this function at + * the appropriate address + */ + .section .text2, "ax" + .globl doload +doload: + jr ra + li a0, MAGIC1 + /* we should not get there */ + EXIT(1) + nop +roval: .word MAGIC2 + .align 12 + .globl doload2 +doload2: + jr ra + li a0, MAGIC2 + /* we should not get there */ + EXIT(1) + nop +roval2: .word MAGIC1 + + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2_a + +/* + * one PD with a level 2 PTP: we change an entry in the PD and + * check that the TLBs has been invalidated + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .word PTE2_V | PTE2_C | PTE2_X + .word (BOOT_ADDRESS+0x1000) >> 12 /* address of doload */ + .org pte2_a + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte2_b: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .word PTE2_V | PTE2_C | PTE2_X + .word (BOOT_ADDRESS+0x2000) >> 12 /* address of doload2 */ + .org pte2_b + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word 0x0 + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 +pte1_ac: + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_ptprinval/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_ptprinval/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_ptprinval/Makefile (revision 724) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_ptprinval/ldscript =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_ptprinval/ldscript (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_ptprinval/ldscript (revision 724) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_ptprinval/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_ptprinval/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_ptprinval/run (revision 724) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started ptpr_b 0x0000DEAD 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^mmu started ptpr_a 0x0000BEEF 0x0000DEAD$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_ptprinval/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_ptprinval/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_idtlb_ptprinval/test.S (revision 724) @@ -0,0 +1,173 @@ +/* + * itlb inval on PTPR write: check that no stale entry exists in the itlb + * after MMU context swicth + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_b + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr_b) + la t0, rodata + lw a0, 0(t0) + PRINTX + PUTCHAR(' ') + jal doload + nop + PRINTX + PUTCHAR('\n') + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop +#if 0 /* works with this - this shows the old pte2 address is cached */ + la a0, pte2_a + lw a1, 12(a0) + la a0, pte2_b + sw a1, 12(a0) +#endif + PRINT(mmustr_a) + la t0, rodata + lw a0, 0(t0) + PRINTX + PUTCHAR(' ') + jal doload + nop + PRINTX + PUTCHAR('\n') + + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(3) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr_a: .ascii "mmu started ptpr_a \0" +mmustr_b: .ascii "mmu started ptpr_b \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + /* + * code that will be switched by MMU switch. + * we use a ldscript trick here, to load this function at + * the appropriate address + */ + .section .text2, "ax" + .globl doload +doload: + jr ra + li a0, MAGIC1 + /* we should not get there */ + EXIT(1) + nop +rodata: + .word MAGIC2 + .org doload + 0x1000 /* in the second page, mapped by pte1_b */ + jr ra + li a0, MAGIC2 + /* we should not get there */ + EXIT(2) + nop + .word MAGIC1 + + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2_a + +/* + * two PD with two different PTE2 for code: check that itlb points to + * the right one by executing 2 different code at the same address + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .word PTE2_V | PTE2_C | PTE2_X + .word (BOOT_ADDRESS+0x1000) >> 12 + .org pte2_a + 4092 + .word 0 + .globl pte2_b +pte2_b: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .word PTE2_V | PTE2_C | PTE2_X + .word (BOOT_ADDRESS+0x2000) >> 12 + .org pte2_b + 4092 + .word 0 + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word 0x0 + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 + .globl pte1_b +pte1_b: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word 0x0 + .org pte1_b + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_T | (0x2000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_b !!! */ + .org pte1_b + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_b + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_b + 8188 + .word 0 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt/run (revision 724) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^0x0000DEAD$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^status 0x00400103 cause 0x00000100 pc 0xBFC00038 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt/test.S (revision 724) @@ -0,0 +1,80 @@ +/* + * Check that we can take an interrupt, and return from it. + * We use a software-triggerted interrupt. + */ +#include +#include + + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + /* reset cop0 status (keep BEV), enbale soft interrupt 0 */ + lui a0, 0x0040; + addiu a0, 0x0101; + mtc0 a0, COP0_STATUS + + /* reset cause, make sure IV is off */ + mtc0 zero, COP0_CAUSE + + PRINT(startstr) + + /* generate an interrupt */ + mfc0 a0, COP0_CAUSE + nop + ori a0, 0x0100 + mtc0 a0, COP0_CAUSE + li a0, MAGIC1 + PRINTX + PUTCHAR('\n') + /* we should end here after taking the exeption */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* clear interrupt */ + mfc0 a0, COP0_CAUSE + xori a0, 0x100 + mtc0 a0, COP0_CAUSE + nop + eret + /* we should not end there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +eretstr: .ascii "eret\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data +myvar: .word 0 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_delayslot/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_delayslot/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_delayslot/Makefile (revision 724) @@ -0,0 +1,2 @@ +include ../Makefile.inc +CFLAGS+= -DINTERRUPT_DELAY=${INTERRUPT_DELAY} Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_delayslot/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_delayslot/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_delayslot/run (revision 724) @@ -0,0 +1,36 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^end 0x0000DEAD$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^status 0x00400403 cause 0x80000000 pc 0xBFC00054 badva 0x00000000 xicu 0x[01][0-9A-F][01][0-9A-F][01][0-9A-F]00$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + + +for i in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70; do + make clean --quiet + make INTERRUPT_DELAY=$i --quiet || exit 1 + ${SIMUL} > run.out 2>&1 + if [ $? -eq 0 ]; then + if check_output; then + echo "test $i passed"; + make --quiet clean + exit 0; + fi + else + echo "test FAILED" + exit 1 + fi +done +echo "test FAILED" Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_delayslot/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_delayslot/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_delayslot/test.S (revision 724) @@ -0,0 +1,112 @@ +/* + * Check that we can take an interrupt from the xicu timer0 + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + /* reset cause, make sure IV is off */ + mtc0 zero, COP0_CAUSE + + PRINT(startstr) + + /* program xicu */ + la t0, XICU_BASE + /* clear pending interrupt */ + lw a0, XICU_PTI_ACK(0)(t0) + /* route PTI0 to irq 0 */ + li a0, 1 << 0 + sw a0, XICU_MSK_PTI_E(0)(t0) + /* init s0 */ + li s0, MAGIC2 + /* + * interrupt in INTERRUPT_DELAY cycles. + * Without cache this takes us to the delay slot of the jump. + */ + + li a0, INTERRUPT_DELAY + //li a0, 38 + sw a0, XICU_PTI_PER(0)(t0) + /* clear pending interrupt */ + lw a0, XICU_PTI_ACK(0)(t0) + /* reset cop0 status (keep BEV), enable interrupt 0 */ + lui a0, 0x0040; + addiu a0, 0x0401; + mtc0 a0, COP0_STATUS + + nop + nop + nop + j end + li s0, MAGIC1 + nop + /* we should not end there */ + EXIT(1) + +end: + PRINT(endstr) + move a0, s0 + PRINTX + PUTCHAR('\n') + EXIT(0) + + .globl excep +excep: + .set noreorder + /* disable timer0 */ + la t0, XICU_BASE + sw zero, XICU_PTI_PER(0)(t0) + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PRINT(xicustr) + la t0, XICU_BASE + lw a0, XICU_PRIO(0)(t0) + PRINTX + + PUTCHAR('\n') + /* clear interrupt */ + mfc0 a0, COP0_CAUSE + andi t0, a0, 0xff00 + xor a0, a0, t0 + mtc0 a0, COP0_CAUSE + eret + /* we should not end there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +xicustr: .ascii " xicu \0" +startstr: .ascii "start\n\0" +endstr: .ascii "end \0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data +myvar: .word 0 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_epc_modify/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_epc_modify/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_epc_modify/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_epc_modify/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_epc_modify/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_epc_modify/run (revision 724) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^eret$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^status 0x00400103 cause 0x00000100 pc 0xBFC00038 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_epc_modify/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_epc_modify/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_epc_modify/test.S (revision 724) @@ -0,0 +1,85 @@ +/* + * Check that we can take an interrupt, and return to a different address. + * We use a software-triggerted interrupt. + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + /* reset cop0 status (keep BEV), enbale soft interrupt 0 */ + lui a0, 0x0040; + addiu a0, 0x0101; + mtc0 a0, COP0_STATUS + + /* reset cause, make sure IV is off */ + mtc0 zero, COP0_CAUSE + + PRINT(startstr) + + /* generate an interrupt */ + mfc0 a0, COP0_CAUSE + nop + ori a0, 0x0100 + mtc0 a0, COP0_CAUSE + nop + /* we should not end there */ + EXIT(1) + +exret: + PRINT(eretstr) + EXIT(0) + + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* clear interrupt */ + mfc0 a0, COP0_CAUSE + xori a0, 0x100 + mtc0 a0, COP0_CAUSE + nop + la a0, exret + mtc0 a0, COP0_EXPC + nop + eret + /* we should not end there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +eretstr: .ascii "eret\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data +myvar: .word 0 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_extended/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_extended/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_extended/Makefile (revision 724) @@ -0,0 +1,2 @@ +include ../Makefile.inc +CFLAGS+= -DINTERRUPT_DELAY=${INTERRUPT_DELAY} Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_extended/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_extended/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_extended/run (revision 724) @@ -0,0 +1,31 @@ +#!/bin/sh + +check_output() +{ + egrep "^end 0x0000DEAE$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep ^status run.out + return 0; +} +echo +for i in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70; do + echo -n " DELAY=$i: " + make INTERRUPT_DELAY=$i --quiet || exit 1 + ../platform/simulation.x > run.out 2>&1 + if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + else + echo "test FAILED" + exit 1 + fi + else + echo "test FAILED" + exit 1 + fi +done + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_extended/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_extended/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_extended/test.S (revision 724) @@ -0,0 +1,137 @@ +/* + * Check interrupt/return with interrup occuring at various points in + * the software. Cache is enabled to we have on interrupt/cycle + */ +#include +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + /* reset cause, make sure IV is off */ + mtc0 zero, COP0_CAUSE + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(startstr) + + /* program xicu */ + la t0, XICU_BASE + /* clear pending interrupt */ + lw a0, XICU_PTI_ACK(0)(t0) + /* route PTI0 to irq 0 */ + li a0, 1 << 0 + sw a0, XICU_MSK_PTI_E(0)(t0) + /* init s0 */ + li s0, MAGIC2 + /* + * interrupt in INTERRUPT_DELAY cycles. + */ + li a0, INTERRUPT_DELAY + sw a0, XICU_PTI_PER(0)(t0) + /* clear pending interrupt */ + lw a0, XICU_PTI_ACK(0)(t0) + /* reset cop0 status (keep BEV), enable interrupt 0 */ + lui a0, 0x0040; + addiu a0, 0x0401; + mtc0 a0, COP0_STATUS + + li s0, MAGIC1 + addiu s0, s0, -1 + addiu s0, s0, -1 + addiu s0, s0, -1 + addiu s0, s0, -1 + nop + j end + addiu s0, s0, 5 + nop + /* we should not end there */ + EXIT(1) + +end: + PRINT(endstr) + move a0, s0 + PRINTX + PUTCHAR('\n') + EXIT(0) + + .globl excep +excep: + .set noreorder + /* disable timer0 */ + la t0, XICU_BASE + sw zero, XICU_PTI_PER(0)(t0) + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PRINT(xicustr) + la t0, XICU_BASE + lw a0, XICU_PRIO(0)(t0) + PRINTX + + PUTCHAR('\n') + /* clear interrupt */ + mfc0 a0, COP0_CAUSE + andi t0, a0, 0xff00 + xor a0, a0, t0 + mtc0 a0, COP0_CAUSE + eret + /* we should not end there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +xicustr: .ascii " xicu \0" +startstr: .ascii "start\n\0" +endstr: .ascii "end \0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data +myvar: .word 0 +pte1: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1 + (XICU_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (XICU_BASE >> 21) /* map PA 0xd2000000 at VA 0xd2000000 */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 + .word 0 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_extended2/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_extended2/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_extended2/Makefile (revision 724) @@ -0,0 +1,2 @@ +include ../Makefile.inc +CFLAGS+= -DINTERRUPT_DELAY=${INTERRUPT_DELAY} Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_extended2/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_extended2/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_extended2/run (revision 724) @@ -0,0 +1,31 @@ +#!/bin/sh + +check_output() +{ + egrep "^end 0x0000DEAD 0x0000BEF0$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^status 0x00400403" run.out + return 0; +} +echo +for i in 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99; do + echo -n " DELAY=$i: " + make INTERRUPT_DELAY=$i --quiet || exit 1 + ../platform/simulation.x > run.out 2>&1 + if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + else + echo "test FAILED" + exit 1 + fi + else + echo "test FAILED" + exit 1 + fi +done + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_extended2/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_extended2/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_extended2/test.S (revision 724) @@ -0,0 +1,181 @@ +/* + * Check interrupt/return with interrup occuring at various points in + * the software. Cache is enabled to we have on interrupt/cycle + */ +#include +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + /* reset cause, make sure IV is off */ + mtc0 zero, COP0_CAUSE + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(startstr) + + /* program xicu */ + la t0, XICU_BASE + /* clear pending interrupt */ + lw a0, XICU_PTI_ACK(0)(t0) + /* route PTI0 to irq 0 */ + li a0, 1 << 0 + sw a0, XICU_MSK_PTI_E(0)(t0) + /* init s0 */ + li s0, MAGIC2 + + /* reset cop0 status (keep BEV), enable soft interrupt 0 */ + lui a0, 0x0040; + addiu a0, 0x0101; + mtc0 a0, COP0_STATUS +#if 1 + /* trigger soft interrupt, so that exept is in cache */ + mfc0 a0, COP0_CAUSE + ori a0, 0x0100 + mtc0 a0, COP0_CAUSE + nop +#endif + + /* + * interrupt in INTERRUPT_DELAY cycles. + */ + la t0, XICU_BASE + li a0, INTERRUPT_DELAY + sw a0, XICU_PTI_PER(0)(t0) + /* clear pending interrupt */ + lw a0, XICU_PTI_ACK(0)(t0) + /* reset cop0 status (keep BEV), enable interrupt 0 */ + lui a0, 0x0040; + addiu a0, 0x0401; + mtc0 a0, COP0_STATUS + + li s0, MAGIC1 + li s1, MAGIC2 + addiu s0, s0, -1 + jal incr + nop + addiu s0, s0, -1 + jal incr + nop + addiu s0, s0, -1 + jal incr + nop + addiu s0, s0, -1 + jal incr + nop + j end + addiu s1, s1, 5 + nop + /* we should not end there */ + EXIT(1) + + .align 6 + nop +incr: + addiu s1, s1, -1 + j ra + addiu s0, s0, 1 + + .align 6 +end: + PRINT(endstr) + move a0, s0 + PRINTX + PUTCHAR(' ') + move a0, s1 + PRINTX + PUTCHAR('\n') + EXIT(0) +fail: + EXIT(4) + + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +xicustr: .ascii " xicu \0" +startstr: .ascii "start\n\0" +endstr: .ascii "end \0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl excep +excep: + .set noreorder + move s2, ra + mfc0 a0, COP0_CAUSE + andi a0, a0, 0x0400 + beq a0, zero, softint + nop + /* disable timer0 */ + la t0, XICU_BASE + sw zero, XICU_PTI_PER(0)(t0) + + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PRINT(xicustr) + la t0, XICU_BASE + lw a0, XICU_PRIO(0)(t0) + PRINTX + + PUTCHAR('\n') +softint: + /* clear interrupt */ + mfc0 a0, COP0_CAUSE + andi t0, a0, 0xff00 + xor a0, a0, t0 + mtc0 a0, COP0_CAUSE + /* fluch cache line of incr */ + la a0, incr + mtc2 a0, VC_ICACHE_INVAL + //mtc2 a0, VC_ITLB_INVAL + move ra, s2 + la s2, fail + eret + /* we should not end there */ + EXIT(3) + .data +myvar: .word 0 +pte1: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1 + (XICU_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (XICU_BASE >> 21) /* map PA 0xd2000000 at VA 0xd2000000 */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 + .word 0 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_external_mask/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_external_mask/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_external_mask/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_external_mask/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_external_mask/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_external_mask/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x0040CC03 cause 0x00000400 pc 0xBFC00088 badva 0x00000000 xicu 0x[01][0-9A-F][01][0-9A-F]0001$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_external_mask/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_external_mask/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_external_mask/test.S (revision 724) @@ -0,0 +1,110 @@ +/* + * Check that we can mask an external interrupt + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + /* reset cop0 status (keep BEV), enable interrupt 0 */ + lui a0, 0x0040; + ori a0, 0xc801; + mtc0 a0, COP0_STATUS + + /* reset cause, make sure IV is off */ + mtc0 zero, COP0_CAUSE + + PRINT(startstr) + + /* program xicu */ + la t0, XICU_BASE + /* clear pending interrupt */ + lw a0, XICU_PTI_ACK(0)(t0) + /* route PTI0 to irq 0 */ + li a0, 1 << 0 + sw a0, XICU_MSK_PTI_E(0)(t0) + /* interrupt in 10 cycles */ + li a0, 10 + sw a0, XICU_PTI_PER(0)(t0) + /* interrupts still disabled at the MIPS level */ + li a0, MAGIC1 + PRINTX + PUTCHAR('\n') + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + /* enable interrupt from timer0 */ + mfc0 a0, COP0_STATUS + ori a0, 0x0400 + mtc0 a0, COP0_STATUS + + nop + nop + +1: j 1b + nop + /* we should not end there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PRINT(xicustr) + la t0, XICU_BASE + lw a0, XICU_PRIO(0)(t0) + PRINTX + + PUTCHAR('\n') + /* clear interrupt */ + mfc0 a0, COP0_CAUSE + andi t0, a0, 0xff00 + xor a0, a0, t0 + mtc0 a0, COP0_CAUSE + /* we should end there */ + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +xicustr: .ascii " xicu \0" +startstr: .ascii "start\n\0" +eretstr: .ascii "eret\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data +myvar: .word 0 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_loop_tmp/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_loop_tmp/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_loop_tmp/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_loop_tmp/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_loop_tmp/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_loop_tmp/run (revision 724) @@ -0,0 +1,12 @@ +#!/bin/sh + +make --quiet || exit 1 +../platform/simulation.x > run.out 2>&1 +if [ $? -eq 0 ]; then + echo "test passsed"; + make --quiet clean + exit 0; +fi +echo "test failed" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_loop_tmp/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_loop_tmp/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_loop_tmp/test.S (revision 724) @@ -0,0 +1,166 @@ +/* + * Check interrupt/return with interrup occuring at various points in + * the software. Cache is enabled to we have on interrupt/cycle + */ +#include +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + /* reset cause, make sure IV is off */ + mtc0 zero, COP0_CAUSE + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(startstr) + + /* program xicu */ + la t0, XICU_BASE + /* clear pending interrupt */ + lw a0, XICU_PTI_ACK(0)(t0) + /* route PTI0 to irq 0 */ + li a0, 1 << 0 + sw a0, XICU_MSK_PTI_E(0)(t0) + /* init s0 */ + li s0, MAGIC2 + /* + * interrupt in INTERRUPT_DELAY cycles. + */ + li s2, 1 + sw s2, XICU_PTI_PER(0)(t0) + /* clear pending interrupt */ + lw a0, XICU_PTI_ACK(0)(t0) + /* reset cop0 status (keep BEV), enable interrupt 0 */ + lui a0, 0x0040; + addiu a0, 0x0401; + mtc0 a0, COP0_STATUS + + nop + li s0, MAGIC1 + addiu s0, s0, -1 +loop: + addiu s0, s0, -1 + addiu s0, s0, -1 + addiu s0, s0, -1 + j bla + addiu s0, s0, 5 + EXIT(1) + addiu s0, s0, -1 + .align 6 +bla: + addiu s0, s0, -1 + li s1, MAGIC1 + beq s0, s1, loop + addiu s0, s0, -1 + + /* we should not end there */ + EXIT(1) + + .align 6 +end: + PRINT(endstr) + move a0, s0 + PRINTX + PUTCHAR('\n') + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +xicustr: .ascii " xicu \0" +startstr: .ascii "start\n\0" +perstr: .ascii " period \0" +endstr: .ascii "end \0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl excep +excep: + .set noreorder + addiu s0, s0, -10 + /* disable timer0 */ + la t0, XICU_BASE + sw zero, XICU_PTI_PER(0)(t0) + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PRINT(xicustr) + la t0, XICU_BASE + lw a0, XICU_PRIO(0)(t0) + PRINTX + +// PRINT(perstr) +// move a0, s2 +// PRINTX +// + PUTCHAR('\n') + +#if 0 + andi s3, s2, 1 + beqz s3, noflush +#endif + addiu s0, s0, 10 + +#if 1 + // Flush cache of jump routine + la s3, bla + mtc2 s3, VC_ICACHE_INVAL + mtc2 s3, VC_ITLB_INVAL +#endif + +noflush: + addiu s2, s2, 1 + li s3, 194*2 + beq s2, s3, end2 + srl s3, s2, 1 + la t0, XICU_BASE + sw s3, XICU_PTI_PER(0)(t0) + eret + /* we should not end there */ + EXIT(1) +end2: + EXIT(0) + + .data +myvar: .word 0 +pte1: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1 + (XICU_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (XICU_BASE >> 21) /* map PA 0xd2000000 at VA 0xd2000000 */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 + .word 0 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_mask/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_mask/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_mask/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_mask/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_mask/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_mask/run (revision 724) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^status 0x0040FF03 cause 0x00000100 pc 0xBFC00074 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_mask/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_mask/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_interrupt_mask/test.S (revision 724) @@ -0,0 +1,95 @@ +/* + * Check that the interrupt mask in status is properly handled: + * we generate a software-triggerted interrupt with interrupt enabled but + * the software interrupt masked. Later we unmask it. + */ +#include +#include + + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + /* reset cop0 status (keep BEV), enbale interrupts but mask IM0 */ + lui a0, 0x0040; + ori a0, 0xfe01; + mtc0 a0, COP0_STATUS + + /* reset cause, make sure IV is off */ + mtc0 zero, COP0_CAUSE + + PRINT(startstr) + + /* generate an interrupt */ + mfc0 a0, COP0_CAUSE + nop + ori a0, 0x0100 + mtc0 a0, COP0_CAUSE + li a0, MAGIC1 + PRINTX + PUTCHAR('\n') + nop + nop + nop + nop + nop + nop + /* unmask the interrupt */ + mfc0 a0, COP0_STATUS + nop + ori a0, 0x0100 + mtc0 a0, COP0_STATUS + /* we should end here after taking the exeption */ + li a0, MAGIC2 + PRINTX + PUTCHAR('\n') + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* clear interrupt */ + mfc0 a0, COP0_CAUSE + xori a0, 0x100 + mtc0 a0, COP0_CAUSE + nop + eret + /* we should not end there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +eretstr: .ascii "eret\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data +myvar: .word 0 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_inval/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_inval/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_inval/Makefile (revision 724) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_inval/ldscript =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_inval/ldscript (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_inval/ldscript (revision 724) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_inval/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_inval/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_inval/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started 0x0000DEAD status 0x00400002 cause 0x00000018 pc 0xBFC01000 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_inval/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_inval/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_inval/test.S (revision 724) @@ -0,0 +1,135 @@ +/* + * itlb inval: a write to VC_ITLB_INVAL should invalidate the corresponding + * itlb entry. On a ccvcache, VC_ITLB_INVAL should not be needed, and + * the first access after clearing pte2_a should fail + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + jal doload + nop + PRINTX + PUTCHAR(' ') + la a0, pte2_a + sw zero, 8(a0) /* invalidate PTE2 */ + sync + la a0, pte2_a /* make the sync synchronous */ + jal doload /* TLB entry not invalidated yet, we can do this */ + nop + PRINTX + PUTCHAR('\n') + la a0, doload + mtc2 a0, VC_ITLB_INVAL /* invalidate VA */ + jal doload /* this should fail now */ + nop + PRINTX + PUTCHAR('\n') + + /* we should not get there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + /* + * code that will be switched by MMU switch. + * we use a ldscript trick here, to load this function at + * the appropriate address + */ + .section .text2, "ax" + .globl doload +doload: + jr ra + li a0, MAGIC1 + /* we should not get there */ + EXIT(1) + nop + + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2_a + +/* + * one PD with a level 2 PTP: we invalidate an entry in the PTP and + * check that the VA is no longer accessible + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .word PTE2_V | PTE2_C | PTE2_X + .word (BOOT_ADDRESS+0x1000) >> 12 + .org pte2_a + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word 0x0 + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_inval2/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_inval2/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_inval2/Makefile (revision 724) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_inval2/ldscript =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_inval2/ldscript (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_inval2/ldscript (revision 724) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_inval2/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_inval2/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_inval2/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started 0x0000DEAD 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_inval2/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_inval2/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_inval2/test.S (revision 724) @@ -0,0 +1,142 @@ +/* + * itlb inval: a write to a PTE2 should invalidate the corresponding + * itlb entry. + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + jal doload + nop + PRINTX + PUTCHAR(' ') + la t0, pte2_a + la a0, (BOOT_ADDRESS+0x2000) >> 12 + sw a0, 12(t0) /* change PTE2 */ + sync +1: + ll a0, 8(t0) + la a0, PTE2_V | PTE2_C | PTE2_X + sc a0, 8(t0) + beqz a0, 1b + nop + + jal doload /* now we should get the second value */ + nop + PRINTX + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + /* + * code that will be switched by MMU switch. + * we use a ldscript trick here, to load this function at + * the appropriate address + */ + .section .text2, "ax" + .globl doload +doload: + jr ra + li a0, MAGIC1 + /* we should not get there */ + EXIT(1) + nop + .align 12 + .globl doload2 +doload2: + jr ra + li a0, MAGIC2 + /* we should not get there */ + EXIT(1) + nop + + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2_a + +/* + * one PD with a level 2 PTP: we change an entry in the PTP and + * check that the ITLB has been invalidated + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .word PTE2_V | PTE2_C | PTE2_X + .word (BOOT_ADDRESS+0x1000) >> 12 + .org pte2_a + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word 0x0 + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_ptprinval/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_ptprinval/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_ptprinval/Makefile (revision 724) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_ptprinval/ldscript =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_ptprinval/ldscript (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_ptprinval/ldscript (revision 724) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_ptprinval/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_ptprinval/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_ptprinval/run (revision 724) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started ptpr_b 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^mmu started ptpr_a 0x0000DEAD$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_ptprinval/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_ptprinval/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_itlb_ptprinval/test.S (revision 724) @@ -0,0 +1,162 @@ +/* + * itlb inval on PTPR write: check that no stale entry exists in the itlb + * after MMU context swicth + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_b + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr_b) + jal doload + nop + PRINTX + PUTCHAR('\n') + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop +#if 0 /* works with this - this shows the old pte2 address is cached */ + la a0, pte2_a + lw a1, 12(a0) + la a0, pte2_b + sw a1, 12(a0) +#endif + PRINT(mmustr_a) + jal doload + nop + PRINTX + PUTCHAR('\n') + + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(3) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr_a: .ascii "mmu started ptpr_a \0" +mmustr_b: .ascii "mmu started ptpr_b \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + /* + * code that will be switched by MMU switch. + * we use a ldscript trick here, to load this function at + * the appropriate address + */ + .section .text2, "ax" + .globl doload +doload: + jr ra + li a0, MAGIC1 + /* we should not get there */ + EXIT(1) + nop + .org doload + 0x1000 /* in the second page, mapped by pte1_b */ + jr ra + li a0, MAGIC2 + /* we should not get there */ + EXIT(2) + nop + + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2_a + +/* + * two PD with two different PTE2 for code: check that itlb points to + * the right one by executing 2 different code at the same address + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .word PTE2_V | PTE2_C | PTE2_X + .word (BOOT_ADDRESS+0x1000) >> 12 + .org pte2_a + 4092 + .word 0 + .globl pte2_b +pte2_b: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .word PTE2_V | PTE2_C | PTE2_X + .word (BOOT_ADDRESS+0x2000) >> 12 + .org pte2_b + 4092 + .word 0 + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word 0x0 + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 + .globl pte1_b +pte1_b: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word 0x0 + .org pte1_b + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_T | (0x2000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_b !!! */ + .org pte1_b + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_b + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_b + 8188 + .word 0 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_llsc/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_llsc/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_llsc/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_llsc/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_llsc/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_llsc/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^0x0000DEAD 0x0000DEAD 0x0000BEEF 0x0000DEAD$" run.out > /dev/null + if [ $? -eq 0 ]; then + return 0; + fi + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_llsc/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_llsc/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_llsc/test.S (revision 724) @@ -0,0 +1,113 @@ +/* + * Check interraction between cached read/write and ll/sc + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + /* make sure myvar is in cache */ + la s1, myvar + lw a0, 0(s1) + PRINTX + PUTCHAR(' ') + + /* now write to myvar via ll/sc */ + la s1, myvar +1: + ll a0, 0(s1) + li a1, MAGIC2 + sc a1, 0(s1) + beqz a1, 1b + nop + + PRINTX /* print what we read with ll */ + PUTCHAR(' ') + + la s1, myvar + lw a0, 0(s1) /* print the new value */ + PRINTX + PUTCHAR(' ') + + /* restore myvar value via normal write */ + la s1, myvar + li a1, MAGIC1 + sw a1, 0(s1) + + /* read myvar */ + lw a0, 0(s1) + PRINTX + PUTCHAR('\n'); + + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +value: .word 0x1234abcd +string: .ascii "hello world \0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data +myvar: .word MAGIC1 + .globl pte1 +pte1: + .align 13 + .word PTE1_V | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 + .word 0 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_mmu_basic/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_mmu_basic/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_mmu_basic/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_mmu_basic/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_mmu_basic/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_mmu_basic/run (revision 724) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^0x00200000: 0x0000DEAD$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^0x00000000: status 0x00400006 cause 0x0000001C pc 0xBFC00098 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_mmu_basic/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_mmu_basic/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_mmu_basic/test.S (revision 724) @@ -0,0 +1,102 @@ +/* + * Basic MMU checks: we can read mapped addresses, we can't read unmapped + * addresses + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + + /* we can read our magic number at 0x00200000 */ + la s0, 0x00200000 + move a0, s0 + PRINTX + PUTCHAR(':') + PUTCHAR(' ') + lw a0, 0(s0) + PRINTX + PUTCHAR('\n') + /* but not at 0x00000000 */ + la s0, 0x00000000 + move a0, s0 + PRINTX + PUTCHAR(':') + PUTCHAR(' ') + lw a0, 0(s0) /* this should trigger the exception */ + PRINTX + + /* we shouldn't get there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + li a0, '\n' + sb a0, 0(k0) + + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started\n\0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data +testval: + .word MAGIC1 + .align 13 + .globl pte1 +pte1: + .word 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0x00200000 */ + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 + .word 0 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2i_ref/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2i_ref/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2i_ref/Makefile (revision 724) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2i_ref/ldscript =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2i_ref/ldscript (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2i_ref/ldscript (revision 724) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2i_ref/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2i_ref/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2i_ref/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started 0x8A000000 0xAA000000 0xAA000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2i_ref/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2i_ref/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2i_ref/test.S (revision 724) @@ -0,0 +1,144 @@ +/* + * instruction fetch causes the PTE_L bit to be set + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + la s0, pte2_a + lw s1, 8(s0) + move a0, s1 + PRINTX + PUTCHAR(' ') + la a1, PTE2_L + and a0, s1, a1 + beq a0, a1, fail /* PTE2_L already set, not good */ + nop + jal doload /* cause page to be referenced */ + nop + lw s1, 8(s0) + move a0, s1 + PRINTX + PUTCHAR(' ') + la a1, PTE2_L + and a0, s1, a1 + bne a0, a1, fail /* PTE2_L not set not good */ + nop + /* check again, using ll */ + ll s1, 8(s0) + move a0, s1 + PRINTX + PUTCHAR('\n') + la a1, PTE2_L + and a0, s1, a1 + bne a0, a1, fail /* PTE2_L not set not good */ + nop + EXIT(0) +fail: + /* we should not get there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + /* + * code that will be switched by MMU switch. + * we use a ldscript trick here, to load this function at + * the appropriate address + */ + .section .text2, "ax" + .globl doload +doload: + jr ra + li a0, MAGIC1 + /* we should not get there */ + EXIT(1) + nop + + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2_a + +/* + * one PD with a level 2 PTP: we invalidate an entry in the PTP and + * check that the VA is no longer accessible + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word BOOT_ADDRESS >> 12 + .word PTE2_V | PTE2_C | PTE2_X + .word (BOOT_ADDRESS+0x1000) >> 12 + .org pte2_a + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word 0x0 + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0xbfc00000 at VA 0xbfc00000 with 4k page: check real address of pte2_a !!! */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2ll_ref/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2ll_ref/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2ll_ref/Makefile (revision 724) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2ll_ref/ldscript =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2ll_ref/ldscript (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2ll_ref/ldscript (revision 724) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2ll_ref/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2ll_ref/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2ll_ref/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started 0x8A000000 0xAA000000 0xAA000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2ll_ref/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2ll_ref/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2ll_ref/test.S (revision 724) @@ -0,0 +1,132 @@ +/* + * pte2d_ref: a ll to data should set referenced bit in PTE + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + la s0, pte2_a + lw s1, 0(s0) /* get PTE */ + move a0, s1 + PRINTX + PUTCHAR(' ') + la a1, PTE2_L + and a0, s1, a1 + beq a0, a1, fail /* PTE2_L already set, not good */ + nop + + la t0, testval + 0x00200000 + ll a0, 0(t0); /* cause page to be referenced */ + + lw s1, 0(s0) /* get PTE */ + move a0, s1 + PRINTX + PUTCHAR(' ') + la a1, PTE2_L + and a0, s1, a1 + bne a0, a1, fail /* PTE2_L not set, not good */ + nop + + /* check again, using ll */ + ll s1, 0(s0) /* get PTE */ + move a0, s1 + PRINTX + PUTCHAR('\n') + la a1, PTE2_L + and a0, s1, a1 + bne a0, a1, fail /* PTE2_L not set, not good */ + nop + + EXIT(0) +fail: + /* we should not get there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data + /* first 2 pages is data that will be switched my mmu switch */ +data_a: + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2_a +/* + * one PD with a level 2 PTP: we invalidate an entry in the PTP and + * check that the VA is no longer accessible + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word 0x0000 >> 12 /* check real value of data_a */ + .org pte2_a + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */ + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2lw_ref/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2lw_ref/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2lw_ref/Makefile (revision 724) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2lw_ref/ldscript =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2lw_ref/ldscript (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2lw_ref/ldscript (revision 724) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2lw_ref/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2lw_ref/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2lw_ref/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started 0x8A000000 0xAA000000 0xAA000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2lw_ref/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2lw_ref/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2lw_ref/test.S (revision 724) @@ -0,0 +1,132 @@ +/* + * pte2d_ref: a lw to data should set referenced bit in PTE + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + la s0, pte2_a + lw s1, 0(s0) /* get PTE */ + move a0, s1 + PRINTX + PUTCHAR(' ') + la a1, PTE2_L + and a0, s1, a1 + beq a0, a1, fail /* PTE2_L already set, not good */ + nop + + la t0, testval + 0x00200000 + lw a0, 0(t0); /* cause page to be referenced */ + + lw s1, 0(s0) /* get PTE */ + move a0, s1 + PRINTX + PUTCHAR(' ') + la a1, PTE2_L + and a0, s1, a1 + bne a0, a1, fail /* PTE2_L not set, not good */ + nop + + /* check again, using ll */ + ll s1, 0(s0) /* get PTE */ + move a0, s1 + PRINTX + PUTCHAR('\n') + la a1, PTE2_L + and a0, s1, a1 + bne a0, a1, fail /* PTE2_L not set, not good */ + nop + + EXIT(0) +fail: + /* we should not get there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data + /* first 2 pages is data that will be switched my mmu switch */ +data_a: + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2_a +/* + * one PD with a level 2 PTP: we invalidate an entry in the PTP and + * check that the VA is no longer accessible + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X + .word 0x0000 >> 12 /* check real value of data_a */ + .org pte2_a + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */ + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2sc_dirty/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2sc_dirty/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2sc_dirty/Makefile (revision 724) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2sc_dirty/ldscript =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2sc_dirty/ldscript (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2sc_dirty/ldscript (revision 724) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2sc_dirty/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2sc_dirty/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2sc_dirty/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started 0x8E000000 0xAE400000 0xAE400000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2sc_dirty/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2sc_dirty/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2sc_dirty/test.S (revision 724) @@ -0,0 +1,137 @@ +/* + * pte2d_ref: a sc to data should set the dirty bits in PTE + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + la s0, pte2_a + lw s1, 0(s0) /* get PTE */ + move a0, s1 + PRINTX + PUTCHAR(' ') + la a1, (PTE2_L | PTE2_D) + and a0, s1, a1 + bne a0, zero, fail /* PTE2_L or PTE2_D already set, not good */ + nop + + la t0, testval + 0x00200000 + la a1, MAGIC3 +1: + ll a0, 0(t0) + sc a1, 0(t0); /* cause page to be referenced and dirty */ + beqz a1, 1b + nop + + lw s1, 0(s0) /* get PTE */ + move a0, s1 + PRINTX + PUTCHAR(' ') + la a1, (PTE2_L | PTE2_D) + and a0, s1, a1 + bne a0, a1, fail /* PTE2_L not set, not good */ + nop + + /* check again, using ll */ + ll s1, 0(s0) /* get PTE */ + move a0, s1 + PRINTX + PUTCHAR('\n') + la a1, (PTE2_L | PTE2_D) + and a0, s1, a1 + bne a0, a1, fail /* PTE2_L not set, not good */ + nop + + EXIT(0) +fail: + /* we should not get there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data + /* first 2 pages is data that will be switched my mmu switch */ +data_a: + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2_a +/* + * one PD with a level 2 PTP: we invalidate an entry in the PTP and + * check that the VA is no longer accessible + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X | PTE2_W + .word 0x0000 >> 12 /* check real value of data_a */ + .org pte2_a + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */ + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2sw_dirty/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2sw_dirty/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2sw_dirty/Makefile (revision 724) @@ -0,0 +1,2 @@ +LDSCRIPT=./ldscript +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2sw_dirty/ldscript =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2sw_dirty/ldscript (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2sw_dirty/ldscript (revision 724) @@ -0,0 +1,67 @@ +/* + * + * SOCLIB_GPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU GPLv2. + * + * SoCLib is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + * SOCLIB_GPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, SoC + * Nicolas Pouillon , 2006-2007 + * + * Maintainers: abdelmalek.si-merabet@lip6.fr + */ +ENTRY(_start) + +SECTIONS +{ + . = 0xbfc00000; + .text : { + *(.text) +/* load .text2 one page after .text */ + . = ALIGN(0x1000); + *(.text2) + } + .rodata : { + *(.rodata) + . = ALIGN(4); + } + . = 0x00000000; + .data : { + *(.data) + } + .sdata : { + *(.lit8) + *(.lit4) + *(.sdata) + } + _gp = .; + . = ALIGN(4); + _edata = .; + .sbss : { + *(.sbss) + *(.scommon) + } + .bss : { + *(.bss) + *(COMMON) + } + . = ALIGN(4); + _end = .; + _heap = .; + _stack = 0x00400000-16; +} Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2sw_dirty/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2sw_dirty/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2sw_dirty/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^mmu started 0x8E000000 0xAE400000 0xAE400000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2sw_dirty/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2sw_dirty/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_pte2sw_dirty/test.S (revision 724) @@ -0,0 +1,132 @@ +/* + * pte2d_ref: a sw to data should set referenced and dirty bits in PTE + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1_a + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT(mmustr) + la s0, pte2_a + lw s1, 0(s0) /* get PTE */ + move a0, s1 + PRINTX + PUTCHAR(' ') + la a1, (PTE2_L | PTE2_D) + and a0, s1, a1 + bne a0, zero, fail /* PTE2_L or PTE2_D already set, not good */ + nop + + la t0, testval + 0x00200000 + sw a0, 0(t0); /* cause page to be referenced and dirty */ + + lw s1, 0(s0) /* get PTE */ + move a0, s1 + PRINTX + PUTCHAR(' ') + la a1, (PTE2_L | PTE2_D) + and a0, s1, a1 + bne a0, a1, fail /* PTE2_L not set, not good */ + nop + + /* check again, using ll */ + ll s1, 0(s0) /* get PTE */ + move a0, s1 + PRINTX + PUTCHAR('\n') + la a1, (PTE2_L | PTE2_D) + and a0, s1, a1 + bne a0, a1, fail /* PTE2_L not set, not good */ + nop + + EXIT(0) +fail: + /* we should not get there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started \0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data + /* first 2 pages is data that will be switched my mmu switch */ +data_a: + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte2_a +/* + * one PD with a level 2 PTP: we invalidate an entry in the PTP and + * check that the VA is no longer accessible + */ +pte2_a: + .align 12 + .word PTE2_V | PTE2_C | PTE2_X | PTE2_W + .word 0x0000 >> 12 /* check real value of data_a */ + .org pte2_a + 4092 + .word 0 + .globl pte2_b + .globl pte1_a +pte1_a: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2_a */ + .org pte1_a + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1_a + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1_a + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1_a + 8192 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_pte_llsc/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_pte_llsc/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_pte_llsc/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_pte_llsc/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_pte_llsc/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_pte_llsc/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^0x00000000 0xAC4000FF 0xAC4000FF 0x00000000$" run.out > /dev/null + if [ $? -eq 0 ]; then + return 0; + fi + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_pte_llsc/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_pte_llsc/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_pte_llsc/test.S (revision 724) @@ -0,0 +1,124 @@ +/* + * Check that the MMU doens't clobber the OS bits in PTEs, and interraction + * with ll/sc + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + /* do a swap of pte2[0] to make the entry valid */ + la s0, pte2 + 0x00200000 +1: la a1, PTE2_V | PTE2_C | PTE2_W | PTE2_os + ll a0, 0(s0) + sc a1, 0(s0) + beqz a1, 1b + nop + PRINTX + PUTCHAR(' ') + /* now write to myvar via pte2[0] */ + li a0, MAGIC2 + la s1, myvar + 0x00200000 + sw a0, 0(s1) + /* + * and invalidate pte2[0], again using a swap + * check that we get the same value with lw and ll + */ + lw s1, 0(s0) +2: + move a1, zero + ll a0, 0(s0) + sc a1, 0(s0) + beqz a1, 2b + PRINTX + PUTCHAR(' ') + move a0, s1 + PRINTX + PUTCHAR(' ') + /* finally check what lw tells us now */ + lw a0, 0(s0) + PRINTX + PUTCHAR('\n') + + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +value: .word 0x1234abcd +string: .ascii "hello world \0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data +myvar: .word MAGIC1 + .globl pte1 +pte2: + .align 12 + .word 0 /* invalid for now */ + .word 0x0000 >> 12 /* check real value of myvar */ + .word PTE2_V | PTE2_C | PTE2_W | PTE2_os /* map pte2 too */ + .word 0x1000 >> 12 /* check real address of pte2 */ + .org pte2 + 4092 + .word 0 + .globl pte1 +pte1: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .word PTE1_V | PTE1_T | (0x1000 >> 12) /* map PA 0x0 at VA 0x00200000 via pte2 */ + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 + .word 0 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_ri/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_ri/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_ri/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_ri/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_ri/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_ri/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400002 cause 0x00000028 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_ri/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_ri/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_ri/test.S (revision 724) @@ -0,0 +1,65 @@ +/* + * reserved instruction exception test: check that a reserved instruction + * generates an exception. + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + nop + nop + nop + .word 0x60000000 + EXIT(2) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') +#we should end there + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +usrstr: .ascii "usrmode\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_ri_delayslot/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_ri_delayslot/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_ri_delayslot/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_ri_delayslot/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_ri_delayslot/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_ri_delayslot/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400002 cause 0x80000028 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_ri_delayslot/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_ri_delayslot/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_ri_delayslot/test.S (revision 724) @@ -0,0 +1,86 @@ +/* + * reserved instruction exception test: check that a reserved instruction + * in a delay slot is properly handled + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + nop + nop + nop + j exit + .word 0x60000000 + nop + /* we should not get there, */ + EXIT(2) + .globl exit +exit: + move a0, v0 + PRINTX + PUTCHAR(' ') + move a0, v1 + PRINTX + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') + la a0, exit + mtc0 a0, COP0_EXPC + li v0, MAGIC1 + li v1, MAGIC2 + li a3, 1 + eret + nop + +#we should not end there + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +usrstr: .ascii "usrmode\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_sanity/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_sanity/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_sanity/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_sanity/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_sanity/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_sanity/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^hello world 0x1234ABCD$" run.out > /dev/null + if [ $? -eq 0 ]; then + return 0; + fi + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_sanity/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_sanity/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_sanity/test.S (revision 724) @@ -0,0 +1,42 @@ +/* + * Basic sanity checks: + * we can run a program + * we can write to ram + * we can write to the tty + * we can make the simulator exit + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + la t0, value + lw t0, 0(t0) + la t1, myvar + sw t0, 0(t1) + + la a0, string + jal print + nop + + la t1, myvar + lw a0, 0(t1) + jal printx + nop + + li a0, '\n' + sb a0, 0(k0) + + EXIT(0) + + .rodata: +value: .word 0x1234abcd +string: .ascii "hello world \0" + + .data +myvar: .word 0 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_sc_no_ll/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_sc_no_ll/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_sc_no_ll/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_sc_no_ll/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_sc_no_ll/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_sc_no_ll/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^0x0000DEAD 0x00000000$" run.out > /dev/null + if [ $? -eq 0 ]; then + return 0; + fi + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_sc_no_ll/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_sc_no_ll/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_sc_no_ll/test.S (revision 724) @@ -0,0 +1,104 @@ +/* + * check that a sc without ll does fail + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + /* make sure myvar is in cache */ + la s1, myvar + lw a0, 0(s1) + PRINTX + PUTCHAR(' ') + + /* now write to myvar with sc, without ll first */ + la s1, myvar +1: + li a1, MAGIC2 + sc a1, 0(s1) + beqz a1, 2f + nop + + move a0, a1 + PRINTX + /* we should not get there */ + EXIT(1) + +2: + /* we jump here when the sc failed */ + move a0, a1 + PRINTX + PUTCHAR('\n'); + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +value: .word 0x1234abcd +string: .ascii "hello world \0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data +myvar: .word MAGIC1 + .globl pte1 +pte1: + .align 13 + .word PTE1_V | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 + .word 0 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_sc_update_cache/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_sc_update_cache/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_sc_update_cache/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_sc_update_cache/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_sc_update_cache/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_sc_update_cache/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^0x0000DEAD 0x0000BEEF$" run.out > /dev/null + if [ $? -eq 0 ]; then + return 0; + fi + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_sc_update_cache/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_sc_update_cache/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_sc_update_cache/test.S (revision 724) @@ -0,0 +1,80 @@ +/* + * Check that lc also updates the local L1 cache. + */ +#include +#include +#include + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + /* enable caches */ + li a0, VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + /* fetch data in cache */ + la s0, myvar + lw a0, 0(s0) + /* write magic value */ + li a0, MAGIC1 + sw a0, 0(s0) + /* ll/sc another value on the same address */ +2: + ll a0, 0(s0) + PRINTX + PUTCHAR(' ') + li a0, MAGIC2 + sc a0, 0(s0) + beqz a0, 2b + /* now check that we got the right value in cache */ + lw a0, 0(s0) + PRINTX + PUTCHAR('\n') + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +value: .word 0x1234abcd +string: .ascii "hello world \0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + + .data +myvar: .word 0 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_sync/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_sync/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_sync/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_sync/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_sync/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_sync/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^@@@@@@$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_sync/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_sync/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_sync/test.S (revision 724) @@ -0,0 +1,101 @@ +/* + * sync test: we map the tty cached. If sync doesn't work some chars will be + * lost because writes are combined in the write buffer. + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + PRINT_SYNC(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + + la a0, pte1 + srl a0, a0, 13 + mtc2 a0, VC_PTPR + nop + + li a0, VC_TLB_EN_ITLB | VC_TLB_EN_DTLB | VC_TLB_EN_ICACHE | VC_TLB_EN_DCACHE + mtc2 a0, VC_TLB_EN + + PRINT_SYNC(mmustr) + + /* + * print several chars quickly: without sync not all of them will + * show up + */ +#define WRITE_TTY sb a0, 0(k0); sync + la a0, '@' + WRITE_TTY + WRITE_TTY + WRITE_TTY + WRITE_TTY + WRITE_TTY + WRITE_TTY + PUTCHAR('\n') + + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PUTCHAR('\n') + /* we should not get there */ + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +mmustr: .ascii "mmu started\n\0" +startstr: .ascii "start\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 + .globl pte1 +pte1: + .align 13 + .word PTE1_V | PTE1_C | PTE1_W | 0x0 /* map PA 0 at VA 0 */ + .org pte1 + (BOOT_ADDRESS >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_X | (BOOT_ADDRESS >> 21) /* map PA 0xbfc00000 at VA 0xbfc00000 */ + .org pte1 + (TTY_BASE >> 21) * 4 + .word PTE1_V | PTE1_C | PTE1_W | (TTY_BASE >> 21) /* map PA 0xd0200000 at VA 0xd0200000 *cached!* */ + .org pte1 + (EXIT_BASE >> 21) * 4 + .word PTE1_V | PTE1_W | (EXIT_BASE >> 21) /* map PA 0xe0000000 at VA 0xe0000000 */ + .org pte1 + 8192 + .word 0 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_syscall/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_syscall/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_syscall/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_syscall/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_syscall/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_syscall/run (revision 724) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400012 cause 0x00000020 pc 0xBFC00050 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^0x0000DEAD 0x0000BEEF$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_syscall/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_syscall/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_syscall/test.S (revision 724) @@ -0,0 +1,91 @@ +/* + * syscall test: check that a syscall generates an exception, and we can + * return + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + /* switch to user mode */ + mfc0 a0, COP0_STATUS + ori a0, 0x10 + mtc0 a0, COP0_STATUS + nop + nop + nop + PRINT(usrstr) + syscall + bne a3, zero, exit + nop + /* we should not get there, a3 is not 0 */ + EXIT(2) +exit: + move a0, v0 + PRINTX + PUTCHAR(' ') + move a0, v1 + PRINTX + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') + mfc0 a0, COP0_EXPC + addiu a0, a0, 4 + mtc0 a0, COP0_EXPC + li v0, MAGIC1 + li v1, MAGIC2 + li a3, 1 + eret + nop + +#we should not end there + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +usrstr: .ascii "usrmode\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_syscall_delayslot/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_syscall_delayslot/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_syscall_delayslot/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_syscall_delayslot/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_syscall_delayslot/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_syscall_delayslot/run (revision 724) @@ -0,0 +1,33 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400012 cause 0x80000020 pc 0xBFC00050 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + egrep "^usrmode$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 2 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_syscall_delayslot/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_syscall_delayslot/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_syscall_delayslot/test.S (revision 724) @@ -0,0 +1,90 @@ +/* + * syscall test: check that a syscall in a delay slot is properly handled + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + /* switch to user mode */ + mfc0 a0, COP0_STATUS + ori a0, 0x10 + mtc0 a0, COP0_STATUS + nop + nop + nop + PRINT(usrstr) + j exit + syscall + nop + /* we should not get there, */ + EXIT(2) + .globl exit +exit: + move a0, v0 + PRINTX + PUTCHAR(' ') + move a0, v1 + PRINTX + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') + la a0, exit + mtc0 a0, COP0_EXPC + li v0, MAGIC1 + li v1, MAGIC2 + li a3, 1 + eret + nop + +#we should not end there + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +usrstr: .ascii "usrmode\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_trap/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_trap/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_trap/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_trap/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_trap/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_trap/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400002 cause 0x00000034 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_trap/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_trap/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_trap/test.S (revision 724) @@ -0,0 +1,64 @@ +/* + * trap test: check that a we can generate a trap + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + nop + nop + nop + teq zero, zero + EXIT(2) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') +#we should end there + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +usrstr: .ascii "usrmode\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_trap_delayslot/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_trap_delayslot/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_trap_delayslot/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_trap_delayslot/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_trap_delayslot/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_trap_delayslot/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400002 cause 0x80000034 pc 0xBFC00034 badva 0x00000000$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string 1 in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_trap_delayslot/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_trap_delayslot/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_trap_delayslot/test.S (revision 724) @@ -0,0 +1,85 @@ +/* + * trap test: check that a trap in a delay slot is + * properly handled + */ +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + la sp, 0x00400000 - 16 + + PRINT(startstr) + + /* reset cop0 status (keep BEV) */ + lui a0, 0x0040; + mtc0 a0, COP0_STATUS + nop + nop + nop + j exit + teq zero, zero + /* we should not get there, */ + EXIT(2) + .globl exit +exit: + move a0, v0 + PRINTX + PUTCHAR(' ') + move a0, v1 + PRINTX + PUTCHAR('\n') + /* we should get there */ + EXIT(0) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + PUTCHAR('\n') + la a0, exit + mtc0 a0, COP0_EXPC + li v0, MAGIC1 + li v1, MAGIC2 + li a3, 1 + eret + nop + +#we should not end there + EXIT(1) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +startstr: .ascii "start\n\0" +usrstr: .ascii "usrmode\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data + .word MAGIC1 +testval: + .word MAGIC2 Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_xicu_timer/Makefile =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_xicu_timer/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_xicu_timer/Makefile (revision 724) @@ -0,0 +1,1 @@ +include ../Makefile.inc Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_xicu_timer/run =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_xicu_timer/run (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_xicu_timer/run (revision 724) @@ -0,0 +1,28 @@ +#!/bin/sh + +. ../common/common.sh + +check_output() +{ + egrep "^status 0x00400403 cause 0x[08]0000400 pc 0xBFC00040 badva 0x00000000 xicu 0x[01][0-9A-F][01][0-9A-F]0001$" run.out > /dev/null + if [ $? -ne 0 ]; then + echo "couldn't find string in output - mtty not working ?" >> run.out + return 1 + fi + return 0; +} + +make --quiet || exit 1 +${SIMUL} > run.out 2>&1 +if [ $? -eq 0 ]; then + if check_output; then + echo "test passsed"; + make --quiet clean + exit 0; + fi + echo "test FAILED" + exit 1 +fi +echo "test FAILED" +exit 1 + Index: /branches/fault_tolerance/softs/tests_cc_vcache/test_xicu_timer/test.S =================================================================== --- /branches/fault_tolerance/softs/tests_cc_vcache/test_xicu_timer/test.S (revision 724) +++ /branches/fault_tolerance/softs/tests_cc_vcache/test_xicu_timer/test.S (revision 724) @@ -0,0 +1,89 @@ +/* + * Check that we can take an interrupt from the xicu timer0 + */ +#include +#include +#include + + .text + .globl _start +_start: + .set noreorder + la k0, TTY_BASE + la k1, EXIT_BASE + + /* reset cop0 status (keep BEV), enable interrupt 0 */ + lui a0, 0x0040; + addiu a0, 0x0401; + mtc0 a0, COP0_STATUS + + /* reset cause, make sure IV is off */ + mtc0 zero, COP0_CAUSE + + PRINT(startstr) + + /* program xicu */ + la t0, XICU_BASE + /* clear pending interrupt */ + lw a0, XICU_PTI_ACK(0)(t0) + /* route PTI0 to irq 0 */ + li a0, 1 << 0 + sw a0, XICU_MSK_PTI_E(0)(t0) + /* interrupt in 10 cycles */ + li a0, 10 + sw a0, XICU_PTI_PER(0)(t0) + +1: j 1b + nop + /* we should not end there */ + EXIT(1) + + .globl excep +excep: + .set noreorder + PRINT(statusstr) + mfc0 a0, COP0_STATUS + PRINTX + + PRINT(causestr) + mfc0 a0, COP0_CAUSE + PRINTX + + PRINT(pcstr) + mfc0 a0, COP0_EXPC + PRINTX + + PRINT(badvastr) + mfc0 a0, COP_0_BADVADDR + PRINTX + + PRINT(xicustr) + la t0, XICU_BASE + lw a0, XICU_PRIO(0)(t0) + PRINTX + + PUTCHAR('\n') + /* clear interrupt */ + mfc0 a0, COP0_CAUSE + andi t0, a0, 0xff00 + xor a0, a0, t0 + mtc0 a0, COP0_CAUSE + /* we should end there */ + EXIT(0) + + .rodata: +statusstr: .ascii "status \0" +causestr: .ascii " cause \0" +pcstr: .ascii " pc \0" +badvastr: .ascii " badva \0" +xicustr: .ascii " xicu \0" +startstr: .ascii "start\n\0" +eretstr: .ascii "eret\n\0" + + .org EXCEP_ADDRESS - BOOT_ADDRESS + .globl evect +evect: + j excep + nop + .data +myvar: .word 0 Index: /branches/fault_tolerance/softs/tsar_boot/Doxyfile =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/Doxyfile (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/Doxyfile (revision 724) @@ -0,0 +1,1869 @@ +# Doxyfile 1.8.3.1 + +# This file describes the settings to be used by the documentation system +# doxygen (www.doxygen.org) for a project. +# +# All text after a hash (#) is considered a comment and will be ignored. +# The format is: +# TAG = value [value, ...] +# For lists items can also be appended using: +# TAG += value [value, ...] +# Values that contain spaces should be placed between quotes (" "). + +#--------------------------------------------------------------------------- +# Project related configuration options +#--------------------------------------------------------------------------- + +# This tag specifies the encoding used for all characters in the config file +# that follow. The default is UTF-8 which is also the encoding used for all +# text before the first occurrence of this tag. Doxygen uses libiconv (or the +# iconv built into libc) for the transcoding. See +# http://www.gnu.org/software/libiconv for the list of possible encodings. + +DOXYFILE_ENCODING = UTF-8 + +# The PROJECT_NAME tag is a single word (or sequence of words) that should +# identify the project. Note that if you do not use Doxywizard you need +# to put quotes around the project name if it contains spaces. + +PROJECT_NAME = "TSAR Pre-loader" + +# The PROJECT_NUMBER tag can be used to enter a project or revision number. +# This could be handy for archiving the generated documentation or +# if some version control system is used. + +PROJECT_NUMBER = + +# Using the PROJECT_BRIEF tag one can provide an optional one line description +# for a project that appears at the top of each page and should give viewer +# a quick idea about the purpose of the project. Keep the description short. + +PROJECT_BRIEF = + +# With the PROJECT_LOGO tag one can specify an logo or icon that is +# included in the documentation. The maximum height of the logo should not +# exceed 55 pixels and the maximum width should not exceed 200 pixels. +# Doxygen will copy the logo to the output directory. + +PROJECT_LOGO = + +# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) +# base path where the generated documentation will be put. +# If a relative path is entered, it will be relative to the location +# where doxygen was started. If left blank the current directory will be used. + +OUTPUT_DIRECTORY = doc + +# If the CREATE_SUBDIRS tag is set to YES, then doxygen will create +# 4096 sub-directories (in 2 levels) under the output directory of each output +# format and will distribute the generated files over these directories. +# Enabling this option can be useful when feeding doxygen a huge amount of +# source files, where putting all generated files in the same directory would +# otherwise cause performance problems for the file system. + +CREATE_SUBDIRS = NO + +# The OUTPUT_LANGUAGE tag is used to specify the language in which all +# documentation generated by doxygen is written. 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Constructors, destructors and assignment +# operators of the base classes will not be shown. + +INLINE_INHERITED_MEMB = NO + +# If the FULL_PATH_NAMES tag is set to YES then Doxygen will prepend the full +# path before files name in the file list and in the header files. If set +# to NO the shortest path that makes the file name unique will be used. + +FULL_PATH_NAMES = YES + +# If the FULL_PATH_NAMES tag is set to YES then the STRIP_FROM_PATH tag +# can be used to strip a user-defined part of the path. Stripping is +# only done if one of the specified strings matches the left-hand part of +# the path. The tag can be used to show relative paths in the file list. +# If left blank the directory from which doxygen is run is used as the +# path to strip. Note that you specify absolute paths here, but also +# relative paths, which will be relative from the directory where doxygen is +# started. + +STRIP_FROM_PATH = + +# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of +# the path mentioned in the documentation of a class, which tells +# the reader which header file to include in order to use a class. +# If left blank only the name of the header file containing the class +# definition is used. Otherwise one should specify the include paths that +# are normally passed to the compiler using the -I flag. + +STRIP_FROM_INC_PATH = + +# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter +# (but less readable) file names. This can be useful if your file system +# doesn't support long names like on DOS, Mac, or CD-ROM. + +SHORT_NAMES = NO + +# If the JAVADOC_AUTOBRIEF tag is set to YES then Doxygen +# will interpret the first line (until the first dot) of a JavaDoc-style +# comment as the brief description. If set to NO, the JavaDoc +# comments will behave just like regular Qt-style comments +# (thus requiring an explicit @brief command for a brief description.) + +JAVADOC_AUTOBRIEF = NO + +# If the QT_AUTOBRIEF tag is set to YES then Doxygen will +# interpret the first line (until the first dot) of a Qt-style +# comment as the brief description. If set to NO, the comments +# will behave just like regular Qt-style comments (thus requiring +# an explicit \brief command for a brief description.) + +QT_AUTOBRIEF = NO + +# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make Doxygen +# treat a multi-line C++ special comment block (i.e. a block of //! or /// +# comments) as a brief description. This used to be the default behaviour. +# The new default is to treat a multi-line C++ comment block as a detailed +# description. Set this tag to YES if you prefer the old behaviour instead. + +MULTILINE_CPP_IS_BRIEF = NO + +# If the INHERIT_DOCS tag is set to YES (the default) then an undocumented +# member inherits the documentation from any documented member that it +# re-implements. + +INHERIT_DOCS = YES + +# If the SEPARATE_MEMBER_PAGES tag is set to YES, then doxygen will produce +# a new page for each member. If set to NO, the documentation of a member will +# be part of the file/class/namespace that contains it. + +SEPARATE_MEMBER_PAGES = NO + +# The TAB_SIZE tag can be used to set the number of spaces in a tab. +# Doxygen uses this value to replace tabs by spaces in code fragments. + +TAB_SIZE = 4 + +# This tag can be used to specify a number of aliases that acts +# as commands in the documentation. An alias has the form "name=value". +# For example adding "sideeffect=\par Side Effects:\n" will allow you to +# put the command \sideeffect (or @sideeffect) in the documentation, which +# will result in a user-defined paragraph with heading "Side Effects:". +# You can put \n's in the value part of an alias to insert newlines. + +ALIASES = + +# This tag can be used to specify a number of word-keyword mappings (TCL only). +# A mapping has the form "name=value". For example adding +# "class=itcl::class" will allow you to use the command class in the +# itcl::class meaning. + +TCL_SUBST = + +# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C +# sources only. Doxygen will then generate output that is more tailored for C. +# For instance, some of the names that are used will be different. The list +# of all members will be omitted, etc. + +OPTIMIZE_OUTPUT_FOR_C = NO + +# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java +# sources only. Doxygen will then generate output that is more tailored for +# Java. For instance, namespaces will be presented as packages, qualified +# scopes will look different, etc. + +OPTIMIZE_OUTPUT_JAVA = NO + +# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran +# sources only. Doxygen will then generate output that is more tailored for +# Fortran. + +OPTIMIZE_FOR_FORTRAN = NO + +# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL +# sources. Doxygen will then generate output that is tailored for +# VHDL. + +OPTIMIZE_OUTPUT_VHDL = NO + +# Doxygen selects the parser to use depending on the extension of the files it +# parses. With this tag you can assign which parser to use for a given +# extension. Doxygen has a built-in mapping, but you can override or extend it +# using this tag. The format is ext=language, where ext is a file extension, +# and language is one of the parsers supported by doxygen: IDL, Java, +# Javascript, CSharp, C, C++, D, PHP, Objective-C, Python, Fortran, VHDL, C, +# C++. For instance to make doxygen treat .inc files as Fortran files (default +# is PHP), and .f files as C (default is Fortran), use: inc=Fortran f=C. Note +# that for custom extensions you also need to set FILE_PATTERNS otherwise the +# files are not read by doxygen. + +EXTENSION_MAPPING = + +# If MARKDOWN_SUPPORT is enabled (the default) then doxygen pre-processes all +# comments according to the Markdown format, which allows for more readable +# documentation. See http://daringfireball.net/projects/markdown/ for details. +# The output of markdown processing is further processed by doxygen, so you +# can mix doxygen, HTML, and XML commands with Markdown formatting. +# Disable only in case of backward compatibilities issues. + +MARKDOWN_SUPPORT = YES + +# When enabled doxygen tries to link words that correspond to documented classes, +# or namespaces to their corresponding documentation. Such a link can be +# prevented in individual cases by by putting a % sign in front of the word or +# globally by setting AUTOLINK_SUPPORT to NO. + +AUTOLINK_SUPPORT = YES + +# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want +# to include (a tag file for) the STL sources as input, then you should +# set this tag to YES in order to let doxygen match functions declarations and +# definitions whose arguments contain STL classes (e.g. func(std::string); v.s. +# func(std::string) {}). This also makes the inheritance and collaboration +# diagrams that involve STL classes more complete and accurate. + +BUILTIN_STL_SUPPORT = NO + +# If you use Microsoft's C++/CLI language, you should set this option to YES to +# enable parsing support. + +CPP_CLI_SUPPORT = NO + +# Set the SIP_SUPPORT tag to YES if your project consists of sip sources only. +# Doxygen will parse them like normal C++ but will assume all classes use public +# instead of private inheritance when no explicit protection keyword is present. + +SIP_SUPPORT = NO + +# For Microsoft's IDL there are propget and propput attributes to indicate +# getter and setter methods for a property. Setting this option to YES (the +# default) will make doxygen replace the get and set methods by a property in +# the documentation. This will only work if the methods are indeed getting or +# setting a simple type. If this is not the case, or you want to show the +# methods anyway, you should set this option to NO. + +IDL_PROPERTY_SUPPORT = YES + +# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC +# tag is set to YES, then doxygen will reuse the documentation of the first +# member in the group (if any) for the other members of the group. By default +# all members of a group must be documented explicitly. + +DISTRIBUTE_GROUP_DOC = NO + +# Set the SUBGROUPING tag to YES (the default) to allow class member groups of +# the same type (for instance a group of public functions) to be put as a +# subgroup of that type (e.g. under the Public Functions section). Set it to +# NO to prevent subgrouping. Alternatively, this can be done per class using +# the \nosubgrouping command. + +SUBGROUPING = YES + +# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and +# unions are shown inside the group in which they are included (e.g. using +# @ingroup) instead of on a separate page (for HTML and Man pages) or +# section (for LaTeX and RTF). + +INLINE_GROUPED_CLASSES = NO + +# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and +# unions with only public data fields will be shown inline in the documentation +# of the scope in which they are defined (i.e. file, namespace, or group +# documentation), provided this scope is documented. If set to NO (the default), +# structs, classes, and unions are shown on a separate page (for HTML and Man +# pages) or section (for LaTeX and RTF). + +INLINE_SIMPLE_STRUCTS = NO + +# When TYPEDEF_HIDES_STRUCT is enabled, a typedef of a struct, union, or enum +# is documented as struct, union, or enum with the name of the typedef. So +# typedef struct TypeS {} TypeT, will appear in the documentation as a struct +# with name TypeT. When disabled the typedef will appear as a member of a file, +# namespace, or class. And the struct will be named TypeS. This can typically +# be useful for C code in case the coding convention dictates that all compound +# types are typedef'ed and only the typedef is referenced, never the tag name. + +TYPEDEF_HIDES_STRUCT = NO + +# The SYMBOL_CACHE_SIZE determines the size of the internal cache use to +# determine which symbols to keep in memory and which to flush to disk. +# When the cache is full, less often used symbols will be written to disk. +# For small to medium size projects (<1000 input files) the default value is +# probably good enough. For larger projects a too small cache size can cause +# doxygen to be busy swapping symbols to and from disk most of the time +# causing a significant performance penalty. +# If the system has enough physical memory increasing the cache will improve the +# performance by keeping more symbols in memory. Note that the value works on +# a logarithmic scale so increasing the size by one will roughly double the +# memory usage. The cache size is given by this formula: +# 2^(16+SYMBOL_CACHE_SIZE). The valid range is 0..9, the default is 0, +# corresponding to a cache size of 2^16 = 65536 symbols. + +SYMBOL_CACHE_SIZE = 0 + +# Similar to the SYMBOL_CACHE_SIZE the size of the symbol lookup cache can be +# set using LOOKUP_CACHE_SIZE. This cache is used to resolve symbols given +# their name and scope. Since this can be an expensive process and often the +# same symbol appear multiple times in the code, doxygen keeps a cache of +# pre-resolved symbols. If the cache is too small doxygen will become slower. +# If the cache is too large, memory is wasted. The cache size is given by this +# formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range is 0..9, the default is 0, +# corresponding to a cache size of 2^16 = 65536 symbols. + +LOOKUP_CACHE_SIZE = 0 + +#--------------------------------------------------------------------------- +# Build related configuration options +#--------------------------------------------------------------------------- + +# If the EXTRACT_ALL tag is set to YES doxygen will assume all entities in +# documentation are documented, even if no documentation was available. +# Private class members and static file members will be hidden unless +# the EXTRACT_PRIVATE and EXTRACT_STATIC tags are set to YES + +EXTRACT_ALL = NO + +# If the EXTRACT_PRIVATE tag is set to YES all private members of a class +# will be included in the documentation. + +EXTRACT_PRIVATE = NO + +# If the EXTRACT_PACKAGE tag is set to YES all members with package or internal +# scope will be included in the documentation. + +EXTRACT_PACKAGE = NO + +# If the EXTRACT_STATIC tag is set to YES all static members of a file +# will be included in the documentation. + +EXTRACT_STATIC = NO + +# If the EXTRACT_LOCAL_CLASSES tag is set to YES classes (and structs) +# defined locally in source files will be included in the documentation. +# If set to NO only classes defined in header files are included. + +EXTRACT_LOCAL_CLASSES = YES + +# This flag is only useful for Objective-C code. When set to YES local +# methods, which are defined in the implementation section but not in +# the interface are included in the documentation. +# If set to NO (the default) only methods in the interface are included. + +EXTRACT_LOCAL_METHODS = NO + +# If this flag is set to YES, the members of anonymous namespaces will be +# extracted and appear in the documentation as a namespace called +# 'anonymous_namespace{file}', where file will be replaced with the base +# name of the file that contains the anonymous namespace. By default +# anonymous namespaces are hidden. + +EXTRACT_ANON_NSPACES = NO + +# If the HIDE_UNDOC_MEMBERS tag is set to YES, Doxygen will hide all +# undocumented members of documented classes, files or namespaces. +# If set to NO (the default) these members will be included in the +# various overviews, but no documentation section is generated. +# This option has no effect if EXTRACT_ALL is enabled. + +HIDE_UNDOC_MEMBERS = NO + +# If the HIDE_UNDOC_CLASSES tag is set to YES, Doxygen will hide all +# undocumented classes that are normally visible in the class hierarchy. +# If set to NO (the default) these classes will be included in the various +# overviews. This option has no effect if EXTRACT_ALL is enabled. + +HIDE_UNDOC_CLASSES = NO + +# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, Doxygen will hide all +# friend (class|struct|union) declarations. +# If set to NO (the default) these declarations will be included in the +# documentation. + +HIDE_FRIEND_COMPOUNDS = NO + +# If the HIDE_IN_BODY_DOCS tag is set to YES, Doxygen will hide any +# documentation blocks found inside the body of a function. +# If set to NO (the default) these blocks will be appended to the +# function's detailed documentation block. + +HIDE_IN_BODY_DOCS = NO + +# The INTERNAL_DOCS tag determines if documentation +# that is typed after a \internal command is included. If the tag is set +# to NO (the default) then the documentation will be excluded. +# Set it to YES to include the internal documentation. + +INTERNAL_DOCS = NO + +# If the CASE_SENSE_NAMES tag is set to NO then Doxygen will only generate +# file names in lower-case letters. If set to YES upper-case letters are also +# allowed. This is useful if you have classes or files whose names only differ +# in case and if your file system supports case sensitive file names. Windows +# and Mac users are advised to set this option to NO. + +CASE_SENSE_NAMES = NO + +# If the HIDE_SCOPE_NAMES tag is set to NO (the default) then Doxygen +# will show members with their full class and namespace scopes in the +# documentation. If set to YES the scope will be hidden. + +HIDE_SCOPE_NAMES = NO + +# If the SHOW_INCLUDE_FILES tag is set to YES (the default) then Doxygen +# will put a list of the files that are included by a file in the documentation +# of that file. + +SHOW_INCLUDE_FILES = YES + +# If the FORCE_LOCAL_INCLUDES tag is set to YES then Doxygen +# will list include files with double quotes in the documentation +# rather than with sharp brackets. + +FORCE_LOCAL_INCLUDES = NO + +# If the INLINE_INFO tag is set to YES (the default) then a tag [inline] +# is inserted in the documentation for inline members. + +INLINE_INFO = YES + +# If the SORT_MEMBER_DOCS tag is set to YES (the default) then doxygen +# will sort the (detailed) documentation of file and class members +# alphabetically by member name. If set to NO the members will appear in +# declaration order. + +SORT_MEMBER_DOCS = YES + +# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the +# brief documentation of file, namespace and class members alphabetically +# by member name. If set to NO (the default) the members will appear in +# declaration order. + +SORT_BRIEF_DOCS = NO + +# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen +# will sort the (brief and detailed) documentation of class members so that +# constructors and destructors are listed first. If set to NO (the default) +# the constructors will appear in the respective orders defined by +# SORT_MEMBER_DOCS and SORT_BRIEF_DOCS. +# This tag will be ignored for brief docs if SORT_BRIEF_DOCS is set to NO +# and ignored for detailed docs if SORT_MEMBER_DOCS is set to NO. + +SORT_MEMBERS_CTORS_1ST = NO + +# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the +# hierarchy of group names into alphabetical order. If set to NO (the default) +# the group names will appear in their defined order. + +SORT_GROUP_NAMES = NO + +# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be +# sorted by fully-qualified names, including namespaces. If set to +# NO (the default), the class list will be sorted only by class name, +# not including the namespace part. +# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES. +# Note: This option applies only to the class list, not to the +# alphabetical list. + +SORT_BY_SCOPE_NAME = NO + +# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to +# do proper type resolution of all parameters of a function it will reject a +# match between the prototype and the implementation of a member function even +# if there is only one candidate or it is obvious which candidate to choose +# by doing a simple string match. By disabling STRICT_PROTO_MATCHING doxygen +# will still accept a match between prototype and implementation in such cases. + +STRICT_PROTO_MATCHING = NO + +# The GENERATE_TODOLIST tag can be used to enable (YES) or +# disable (NO) the todo list. This list is created by putting \todo +# commands in the documentation. + +GENERATE_TODOLIST = YES + +# The GENERATE_TESTLIST tag can be used to enable (YES) or +# disable (NO) the test list. This list is created by putting \test +# commands in the documentation. + +GENERATE_TESTLIST = YES + +# The GENERATE_BUGLIST tag can be used to enable (YES) or +# disable (NO) the bug list. This list is created by putting \bug +# commands in the documentation. + +GENERATE_BUGLIST = YES + +# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or +# disable (NO) the deprecated list. This list is created by putting +# \deprecated commands in the documentation. + +GENERATE_DEPRECATEDLIST= YES + +# The ENABLED_SECTIONS tag can be used to enable conditional +# documentation sections, marked by \if section-label ... \endif +# and \cond section-label ... \endcond blocks. + +ENABLED_SECTIONS = + +# The MAX_INITIALIZER_LINES tag determines the maximum number of lines +# the initial value of a variable or macro consists of for it to appear in +# the documentation. If the initializer consists of more lines than specified +# here it will be hidden. Use a value of 0 to hide initializers completely. +# The appearance of the initializer of individual variables and macros in the +# documentation can be controlled using \showinitializer or \hideinitializer +# command in the documentation regardless of this setting. + +MAX_INITIALIZER_LINES = 30 + +# Set the SHOW_USED_FILES tag to NO to disable the list of files generated +# at the bottom of the documentation of classes and structs. If set to YES the +# list will mention the files that were used to generate the documentation. + +SHOW_USED_FILES = YES + +# Set the SHOW_FILES tag to NO to disable the generation of the Files page. +# This will remove the Files entry from the Quick Index and from the +# Folder Tree View (if specified). The default is YES. + +SHOW_FILES = YES + +# Set the SHOW_NAMESPACES tag to NO to disable the generation of the +# Namespaces page. +# This will remove the Namespaces entry from the Quick Index +# and from the Folder Tree View (if specified). The default is YES. + +SHOW_NAMESPACES = YES + +# The FILE_VERSION_FILTER tag can be used to specify a program or script that +# doxygen should invoke to get the current version for each file (typically from +# the version control system). Doxygen will invoke the program by executing (via +# popen()) the command , where is the value of +# the FILE_VERSION_FILTER tag, and is the name of an input file +# provided by doxygen. Whatever the program writes to standard output +# is used as the file version. See the manual for examples. + +FILE_VERSION_FILTER = + +# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed +# by doxygen. The layout file controls the global structure of the generated +# output files in an output format independent way. To create the layout file +# that represents doxygen's defaults, run doxygen with the -l option. +# You can optionally specify a file name after the option, if omitted +# DoxygenLayout.xml will be used as the name of the layout file. + +LAYOUT_FILE = + +# The CITE_BIB_FILES tag can be used to specify one or more bib files +# containing the references data. This must be a list of .bib files. The +# .bib extension is automatically appended if omitted. Using this command +# requires the bibtex tool to be installed. See also +# http://en.wikipedia.org/wiki/BibTeX for more info. For LaTeX the style +# of the bibliography can be controlled using LATEX_BIB_STYLE. To use this +# feature you need bibtex and perl available in the search path. Do not use +# file names with spaces, bibtex cannot handle them. + +CITE_BIB_FILES = + +#--------------------------------------------------------------------------- +# configuration options related to warning and progress messages +#--------------------------------------------------------------------------- + +# The QUIET tag can be used to turn on/off the messages that are generated +# by doxygen. Possible values are YES and NO. If left blank NO is used. + +QUIET = NO + +# The WARNINGS tag can be used to turn on/off the warning messages that are +# generated by doxygen. Possible values are YES and NO. If left blank +# NO is used. + +WARNINGS = YES + +# If WARN_IF_UNDOCUMENTED is set to YES, then doxygen will generate warnings +# for undocumented members. If EXTRACT_ALL is set to YES then this flag will +# automatically be disabled. + +WARN_IF_UNDOCUMENTED = YES + +# If WARN_IF_DOC_ERROR is set to YES, doxygen will generate warnings for +# potential errors in the documentation, such as not documenting some +# parameters in a documented function, or documenting parameters that +# don't exist or using markup commands wrongly. + +WARN_IF_DOC_ERROR = YES + +# The WARN_NO_PARAMDOC option can be enabled to get warnings for +# functions that are documented, but have no documentation for their parameters +# or return value. If set to NO (the default) doxygen will only warn about +# wrong or incomplete parameter documentation, but not about the absence of +# documentation. + +WARN_NO_PARAMDOC = NO + +# The WARN_FORMAT tag determines the format of the warning messages that +# doxygen can produce. The string should contain the $file, $line, and $text +# tags, which will be replaced by the file and line number from which the +# warning originated and the warning text. Optionally the format may contain +# $version, which will be replaced by the version of the file (if it could +# be obtained via FILE_VERSION_FILTER) + +WARN_FORMAT = "$file:$line: $text" + +# The WARN_LOGFILE tag can be used to specify a file to which warning +# and error messages should be written. If left blank the output is written +# to stderr. + +WARN_LOGFILE = + +#--------------------------------------------------------------------------- +# configuration options related to the input files +#--------------------------------------------------------------------------- + +# The INPUT tag can be used to specify the files and/or directories that contain +# documented source files. You may enter file names like "myfile.cpp" or +# directories like "/usr/src/myproject". Separate the files or directories +# with spaces. + +INPUT = . + +# This tag can be used to specify the character encoding of the source files +# that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is +# also the default input encoding. Doxygen uses libiconv (or the iconv built +# into libc) for the transcoding. See http://www.gnu.org/software/libiconv for +# the list of possible encodings. + +INPUT_ENCODING = UTF-8 + +# If the value of the INPUT tag contains directories, you can use the +# FILE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp +# and *.h) to filter out the source-files in the directories. If left +# blank the following patterns are tested: +# *.c *.cc *.cxx *.cpp *.c++ *.d *.java *.ii *.ixx *.ipp *.i++ *.inl *.h *.hh +# *.hxx *.hpp *.h++ *.idl *.odl *.cs *.php *.php3 *.inc *.m *.mm *.dox *.py +# *.f90 *.f *.for *.vhd *.vhdl + +FILE_PATTERNS = + +# The RECURSIVE tag can be used to turn specify whether or not subdirectories +# should be searched for input files as well. Possible values are YES and NO. +# If left blank NO is used. + +RECURSIVE = YES + +# The EXCLUDE tag can be used to specify files and/or directories that should be +# excluded from the INPUT source files. This way you can easily exclude a +# subdirectory from a directory tree whose root is specified with the INPUT tag. +# Note that relative paths are relative to the directory from which doxygen is +# run. + +EXCLUDE = + +# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or +# directories that are symbolic links (a Unix file system feature) are excluded +# from the input. + +EXCLUDE_SYMLINKS = NO + +# If the value of the INPUT tag contains directories, you can use the +# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude +# certain files from those directories. Note that the wildcards are matched +# against the file with absolute path, so to exclude all test directories +# for example use the pattern */test/* + +EXCLUDE_PATTERNS = + +# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names +# (namespaces, classes, functions, etc.) that should be excluded from the +# output. The symbol name can be a fully qualified name, a word, or if the +# wildcard * is used, a substring. Examples: ANamespace, AClass, +# AClass::ANamespace, ANamespace::*Test + +EXCLUDE_SYMBOLS = + +# The EXAMPLE_PATH tag can be used to specify one or more files or +# directories that contain example code fragments that are included (see +# the \include command). + +EXAMPLE_PATH = + +# If the value of the EXAMPLE_PATH tag contains directories, you can use the +# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp +# and *.h) to filter out the source-files in the directories. If left +# blank all files are included. + +EXAMPLE_PATTERNS = + +# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be +# searched for input files to be used with the \include or \dontinclude +# commands irrespective of the value of the RECURSIVE tag. +# Possible values are YES and NO. If left blank NO is used. + +EXAMPLE_RECURSIVE = NO + +# The IMAGE_PATH tag can be used to specify one or more files or +# directories that contain image that are included in the documentation (see +# the \image command). + +IMAGE_PATH = + +# The INPUT_FILTER tag can be used to specify a program that doxygen should +# invoke to filter for each input file. Doxygen will invoke the filter program +# by executing (via popen()) the command , where +# is the value of the INPUT_FILTER tag, and is the name of an +# input file. Doxygen will then use the output that the filter program writes +# to standard output. +# If FILTER_PATTERNS is specified, this tag will be +# ignored. + +INPUT_FILTER = + +# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern +# basis. +# Doxygen will compare the file name with each pattern and apply the +# filter if there is a match. +# The filters are a list of the form: +# pattern=filter (like *.cpp=my_cpp_filter). See INPUT_FILTER for further +# info on how filters are used. If FILTER_PATTERNS is empty or if +# non of the patterns match the file name, INPUT_FILTER is applied. + +FILTER_PATTERNS = + +# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using +# INPUT_FILTER) will be used to filter the input files when producing source +# files to browse (i.e. when SOURCE_BROWSER is set to YES). + +FILTER_SOURCE_FILES = NO + +# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file +# pattern. A pattern will override the setting for FILTER_PATTERN (if any) +# and it is also possible to disable source filtering for a specific pattern +# using *.ext= (so without naming a filter). This option only has effect when +# FILTER_SOURCE_FILES is enabled. + +FILTER_SOURCE_PATTERNS = + +# If the USE_MD_FILE_AS_MAINPAGE tag refers to the name of a markdown file that +# is part of the input, its contents will be placed on the main page (index.html). +# This can be useful if you have a project on for instance GitHub and want reuse +# the introduction page also for the doxygen output. + +USE_MDFILE_AS_MAINPAGE = + +#--------------------------------------------------------------------------- +# configuration options related to source browsing +#--------------------------------------------------------------------------- + +# If the SOURCE_BROWSER tag is set to YES then a list of source files will +# be generated. Documented entities will be cross-referenced with these sources. +# Note: To get rid of all source code in the generated output, make sure also +# VERBATIM_HEADERS is set to NO. + +SOURCE_BROWSER = NO + +# Setting the INLINE_SOURCES tag to YES will include the body +# of functions and classes directly in the documentation. + +INLINE_SOURCES = NO + +# Setting the STRIP_CODE_COMMENTS tag to YES (the default) will instruct +# doxygen to hide any special comment blocks from generated source code +# fragments. Normal C, C++ and Fortran comments will always remain visible. + +STRIP_CODE_COMMENTS = YES + +# If the REFERENCED_BY_RELATION tag is set to YES +# then for each documented function all documented +# functions referencing it will be listed. + +REFERENCED_BY_RELATION = NO + +# If the REFERENCES_RELATION tag is set to YES +# then for each documented function all documented entities +# called/used by that function will be listed. + +REFERENCES_RELATION = NO + +# If the REFERENCES_LINK_SOURCE tag is set to YES (the default) +# and SOURCE_BROWSER tag is set to YES, then the hyperlinks from +# functions in REFERENCES_RELATION and REFERENCED_BY_RELATION lists will +# link to the source code. +# Otherwise they will link to the documentation. + +REFERENCES_LINK_SOURCE = YES + +# If the USE_HTAGS tag is set to YES then the references to source code +# will point to the HTML generated by the htags(1) tool instead of doxygen +# built-in source browser. The htags tool is part of GNU's global source +# tagging system (see http://www.gnu.org/software/global/global.html). You +# will need version 4.8.6 or higher. + +USE_HTAGS = NO + +# If the VERBATIM_HEADERS tag is set to YES (the default) then Doxygen +# will generate a verbatim copy of the header file for each class for +# which an include is specified. Set to NO to disable this. + +VERBATIM_HEADERS = YES + +#--------------------------------------------------------------------------- +# configuration options related to the alphabetical class index +#--------------------------------------------------------------------------- + +# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index +# of all compounds will be generated. Enable this if the project +# contains a lot of classes, structs, unions or interfaces. + +ALPHABETICAL_INDEX = YES + +# If the alphabetical index is enabled (see ALPHABETICAL_INDEX) then +# the COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns +# in which this list will be split (can be a number in the range [1..20]) + +COLS_IN_ALPHA_INDEX = 5 + +# In case all classes in a project start with a common prefix, all +# classes will be put under the same header in the alphabetical index. +# The IGNORE_PREFIX tag can be used to specify one or more prefixes that +# should be ignored while generating the index headers. + +IGNORE_PREFIX = + +#--------------------------------------------------------------------------- +# configuration options related to the HTML output +#--------------------------------------------------------------------------- + +# If the GENERATE_HTML tag is set to YES (the default) Doxygen will +# generate HTML output. + +GENERATE_HTML = YES + +# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `html' will be used as the default path. + +HTML_OUTPUT = html + +# The HTML_FILE_EXTENSION tag can be used to specify the file extension for +# each generated HTML page (for example: .htm,.php,.asp). If it is left blank +# doxygen will generate files with .html extension. + +HTML_FILE_EXTENSION = .html + +# The HTML_HEADER tag can be used to specify a personal HTML header for +# each generated HTML page. If it is left blank doxygen will generate a +# standard header. Note that when using a custom header you are responsible +# for the proper inclusion of any scripts and style sheets that doxygen +# needs, which is dependent on the configuration options used. +# It is advised to generate a default header using "doxygen -w html +# header.html footer.html stylesheet.css YourConfigFile" and then modify +# that header. Note that the header is subject to change so you typically +# have to redo this when upgrading to a newer version of doxygen or when +# changing the value of configuration settings such as GENERATE_TREEVIEW! + +HTML_HEADER = + +# The HTML_FOOTER tag can be used to specify a personal HTML footer for +# each generated HTML page. If it is left blank doxygen will generate a +# standard footer. + +HTML_FOOTER = + +# The HTML_STYLESHEET tag can be used to specify a user-defined cascading +# style sheet that is used by each HTML page. It can be used to +# fine-tune the look of the HTML output. If left blank doxygen will +# generate a default style sheet. Note that it is recommended to use +# HTML_EXTRA_STYLESHEET instead of this one, as it is more robust and this +# tag will in the future become obsolete. + +HTML_STYLESHEET = + +# The HTML_EXTRA_STYLESHEET tag can be used to specify an additional +# user-defined cascading style sheet that is included after the standard +# style sheets created by doxygen. Using this option one can overrule +# certain style aspects. This is preferred over using HTML_STYLESHEET +# since it does not replace the standard style sheet and is therefor more +# robust against future updates. Doxygen will copy the style sheet file to +# the output directory. + +HTML_EXTRA_STYLESHEET = + +# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or +# other source files which should be copied to the HTML output directory. Note +# that these files will be copied to the base HTML output directory. Use the +# $relpath$ marker in the HTML_HEADER and/or HTML_FOOTER files to load these +# files. In the HTML_STYLESHEET file, use the file name only. Also note that +# the files will be copied as-is; there are no commands or markers available. + +HTML_EXTRA_FILES = + +# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. +# Doxygen will adjust the colors in the style sheet and background images +# according to this color. Hue is specified as an angle on a colorwheel, +# see http://en.wikipedia.org/wiki/Hue for more information. +# For instance the value 0 represents red, 60 is yellow, 120 is green, +# 180 is cyan, 240 is blue, 300 purple, and 360 is red again. +# The allowed range is 0 to 359. + +HTML_COLORSTYLE_HUE = 220 + +# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of +# the colors in the HTML output. For a value of 0 the output will use +# grayscales only. A value of 255 will produce the most vivid colors. + +HTML_COLORSTYLE_SAT = 100 + +# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to +# the luminance component of the colors in the HTML output. Values below +# 100 gradually make the output lighter, whereas values above 100 make +# the output darker. The value divided by 100 is the actual gamma applied, +# so 80 represents a gamma of 0.8, The value 220 represents a gamma of 2.2, +# and 100 does not change the gamma. + +HTML_COLORSTYLE_GAMMA = 80 + +# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML +# page will contain the date and time when the page was generated. Setting +# this to NO can help when comparing the output of multiple runs. + +HTML_TIMESTAMP = YES + +# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML +# documentation will contain sections that can be hidden and shown after the +# page has loaded. + +HTML_DYNAMIC_SECTIONS = NO + +# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of +# entries shown in the various tree structured indices initially; the user +# can expand and collapse entries dynamically later on. Doxygen will expand +# the tree to such a level that at most the specified number of entries are +# visible (unless a fully collapsed tree already exceeds this amount). +# So setting the number of entries 1 will produce a full collapsed tree by +# default. 0 is a special value representing an infinite number of entries +# and will result in a full expanded tree by default. + +HTML_INDEX_NUM_ENTRIES = 100 + +# If the GENERATE_DOCSET tag is set to YES, additional index files +# will be generated that can be used as input for Apple's Xcode 3 +# integrated development environment, introduced with OSX 10.5 (Leopard). +# To create a documentation set, doxygen will generate a Makefile in the +# HTML output directory. Running make will produce the docset in that +# directory and running "make install" will install the docset in +# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find +# it at startup. +# See http://developer.apple.com/tools/creatingdocsetswithdoxygen.html +# for more information. + +GENERATE_DOCSET = NO + +# When GENERATE_DOCSET tag is set to YES, this tag determines the name of the +# feed. A documentation feed provides an umbrella under which multiple +# documentation sets from a single provider (such as a company or product suite) +# can be grouped. + +DOCSET_FEEDNAME = "Doxygen generated docs" + +# When GENERATE_DOCSET tag is set to YES, this tag specifies a string that +# should uniquely identify the documentation set bundle. This should be a +# reverse domain-name style string, e.g. com.mycompany.MyDocSet. Doxygen +# will append .docset to the name. + +DOCSET_BUNDLE_ID = org.doxygen.Project + +# When GENERATE_PUBLISHER_ID tag specifies a string that should uniquely +# identify the documentation publisher. This should be a reverse domain-name +# style string, e.g. com.mycompany.MyDocSet.documentation. + +DOCSET_PUBLISHER_ID = org.doxygen.Publisher + +# The GENERATE_PUBLISHER_NAME tag identifies the documentation publisher. + +DOCSET_PUBLISHER_NAME = Publisher + +# If the GENERATE_HTMLHELP tag is set to YES, additional index files +# will be generated that can be used as input for tools like the +# Microsoft HTML help workshop to generate a compiled HTML help file (.chm) +# of the generated HTML documentation. + +GENERATE_HTMLHELP = NO + +# If the GENERATE_HTMLHELP tag is set to YES, the CHM_FILE tag can +# be used to specify the file name of the resulting .chm file. You +# can add a path in front of the file if the result should not be +# written to the html output directory. + +CHM_FILE = + +# If the GENERATE_HTMLHELP tag is set to YES, the HHC_LOCATION tag can +# be used to specify the location (absolute path including file name) of +# the HTML help compiler (hhc.exe). If non-empty doxygen will try to run +# the HTML help compiler on the generated index.hhp. + +HHC_LOCATION = + +# If the GENERATE_HTMLHELP tag is set to YES, the GENERATE_CHI flag +# controls if a separate .chi index file is generated (YES) or that +# it should be included in the master .chm file (NO). + +GENERATE_CHI = NO + +# If the GENERATE_HTMLHELP tag is set to YES, the CHM_INDEX_ENCODING +# is used to encode HtmlHelp index (hhk), content (hhc) and project file +# content. + +CHM_INDEX_ENCODING = + +# If the GENERATE_HTMLHELP tag is set to YES, the BINARY_TOC flag +# controls whether a binary table of contents is generated (YES) or a +# normal table of contents (NO) in the .chm file. + +BINARY_TOC = NO + +# The TOC_EXPAND flag can be set to YES to add extra items for group members +# to the contents of the HTML help documentation and to the tree view. + +TOC_EXPAND = NO + +# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and +# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated +# that can be used as input for Qt's qhelpgenerator to generate a +# Qt Compressed Help (.qch) of the generated HTML documentation. + +GENERATE_QHP = NO + +# If the QHG_LOCATION tag is specified, the QCH_FILE tag can +# be used to specify the file name of the resulting .qch file. +# The path specified is relative to the HTML output folder. + +QCH_FILE = + +# The QHP_NAMESPACE tag specifies the namespace to use when generating +# Qt Help Project output. For more information please see +# http://doc.trolltech.com/qthelpproject.html#namespace + +QHP_NAMESPACE = org.doxygen.Project + +# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating +# Qt Help Project output. For more information please see +# http://doc.trolltech.com/qthelpproject.html#virtual-folders + +QHP_VIRTUAL_FOLDER = doc + +# If QHP_CUST_FILTER_NAME is set, it specifies the name of a custom filter to +# add. For more information please see +# http://doc.trolltech.com/qthelpproject.html#custom-filters + +QHP_CUST_FILTER_NAME = + +# The QHP_CUST_FILT_ATTRS tag specifies the list of the attributes of the +# custom filter to add. For more information please see +# +# Qt Help Project / Custom Filters. + +QHP_CUST_FILTER_ATTRS = + +# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this +# project's +# filter section matches. +# +# Qt Help Project / Filter Attributes. + +QHP_SECT_FILTER_ATTRS = + +# If the GENERATE_QHP tag is set to YES, the QHG_LOCATION tag can +# be used to specify the location of Qt's qhelpgenerator. +# If non-empty doxygen will try to run qhelpgenerator on the generated +# .qhp file. + +QHG_LOCATION = + +# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files +# will be generated, which together with the HTML files, form an Eclipse help +# plugin. To install this plugin and make it available under the help contents +# menu in Eclipse, the contents of the directory containing the HTML and XML +# files needs to be copied into the plugins directory of eclipse. The name of +# the directory within the plugins directory should be the same as +# the ECLIPSE_DOC_ID value. After copying Eclipse needs to be restarted before +# the help appears. + +GENERATE_ECLIPSEHELP = NO + +# A unique identifier for the eclipse help plugin. When installing the plugin +# the directory name containing the HTML and XML files should also have +# this name. + +ECLIPSE_DOC_ID = org.doxygen.Project + +# The DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) +# at top of each HTML page. The value NO (the default) enables the index and +# the value YES disables it. Since the tabs have the same information as the +# navigation tree you can set this option to NO if you already set +# GENERATE_TREEVIEW to YES. + +DISABLE_INDEX = NO + +# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index +# structure should be generated to display hierarchical information. +# If the tag value is set to YES, a side panel will be generated +# containing a tree-like index structure (just like the one that +# is generated for HTML Help). For this to work a browser that supports +# JavaScript, DHTML, CSS and frames is required (i.e. any modern browser). +# Windows users are probably better off using the HTML help feature. +# Since the tree basically has the same information as the tab index you +# could consider to set DISABLE_INDEX to NO when enabling this option. + +GENERATE_TREEVIEW = NO + +# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values +# (range [0,1..20]) that doxygen will group on one line in the generated HTML +# documentation. Note that a value of 0 will completely suppress the enum +# values from appearing in the overview section. + +ENUM_VALUES_PER_LINE = 4 + +# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be +# used to set the initial width (in pixels) of the frame in which the tree +# is shown. + +TREEVIEW_WIDTH = 250 + +# When the EXT_LINKS_IN_WINDOW option is set to YES doxygen will open +# links to external symbols imported via tag files in a separate window. + +EXT_LINKS_IN_WINDOW = NO + +# Use this tag to change the font size of Latex formulas included +# as images in the HTML documentation. The default is 10. Note that +# when you change the font size after a successful doxygen run you need +# to manually remove any form_*.png images from the HTML output directory +# to force them to be regenerated. + +FORMULA_FONTSIZE = 10 + +# Use the FORMULA_TRANPARENT tag to determine whether or not the images +# generated for formulas are transparent PNGs. Transparent PNGs are +# not supported properly for IE 6.0, but are supported on all modern browsers. +# Note that when changing this option you need to delete any form_*.png files +# in the HTML output before the changes have effect. + +FORMULA_TRANSPARENT = YES + +# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax +# (see http://www.mathjax.org) which uses client side Javascript for the +# rendering instead of using prerendered bitmaps. Use this if you do not +# have LaTeX installed or if you want to formulas look prettier in the HTML +# output. When enabled you may also need to install MathJax separately and +# configure the path to it using the MATHJAX_RELPATH option. + +USE_MATHJAX = NO + +# When MathJax is enabled you can set the default output format to be used for +# thA MathJax output. Supported types are HTML-CSS, NativeMML (i.e. MathML) and +# SVG. The default value is HTML-CSS, which is slower, but has the best +# compatibility. + +MATHJAX_FORMAT = HTML-CSS + +# When MathJax is enabled you need to specify the location relative to the +# HTML output directory using the MATHJAX_RELPATH option. The destination +# directory should contain the MathJax.js script. For instance, if the mathjax +# directory is located at the same level as the HTML output directory, then +# MATHJAX_RELPATH should be ../mathjax. The default value points to +# the MathJax Content Delivery Network so you can quickly see the result without +# installing MathJax. +# However, it is strongly recommended to install a local +# copy of MathJax from http://www.mathjax.org before deployment. + +MATHJAX_RELPATH = http://cdn.mathjax.org/mathjax/latest + +# The MATHJAX_EXTENSIONS tag can be used to specify one or MathJax extension +# names that should be enabled during MathJax rendering. + +MATHJAX_EXTENSIONS = + +# When the SEARCHENGINE tag is enabled doxygen will generate a search box +# for the HTML output. The underlying search engine uses javascript +# and DHTML and should work on any modern browser. Note that when using +# HTML help (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets +# (GENERATE_DOCSET) there is already a search function so this one should +# typically be disabled. For large projects the javascript based search engine +# can be slow, then enabling SERVER_BASED_SEARCH may provide a better solution. + +SEARCHENGINE = YES + +# When the SERVER_BASED_SEARCH tag is enabled the search engine will be +# implemented using a web server instead of a web client using Javascript. +# There are two flavours of web server based search depending on the +# EXTERNAL_SEARCH setting. When disabled, doxygen will generate a PHP script for +# searching and an index file used by the script. When EXTERNAL_SEARCH is +# enabled the indexing and searching needs to be provided by external tools. +# See the manual for details. + +SERVER_BASED_SEARCH = NO + +# When EXTERNAL_SEARCH is enabled doxygen will no longer generate the PHP +# script for searching. Instead the search results are written to an XML file +# which needs to be processed by an external indexer. Doxygen will invoke an +# external search engine pointed to by the SEARCHENGINE_URL option to obtain +# the search results. Doxygen ships with an example indexer (doxyindexer) and +# search engine (doxysearch.cgi) which are based on the open source search engine +# library Xapian. See the manual for configuration details. + +EXTERNAL_SEARCH = NO + +# The SEARCHENGINE_URL should point to a search engine hosted by a web server +# which will returned the search results when EXTERNAL_SEARCH is enabled. +# Doxygen ships with an example search engine (doxysearch) which is based on +# the open source search engine library Xapian. See the manual for configuration +# details. + +SEARCHENGINE_URL = + +# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the unindexed +# search data is written to a file for indexing by an external tool. With the +# SEARCHDATA_FILE tag the name of this file can be specified. + +SEARCHDATA_FILE = searchdata.xml + +# When SERVER_BASED_SEARCH AND EXTERNAL_SEARCH are both enabled the +# EXTERNAL_SEARCH_ID tag can be used as an identifier for the project. This is +# useful in combination with EXTRA_SEARCH_MAPPINGS to search through multiple +# projects and redirect the results back to the right project. + +EXTERNAL_SEARCH_ID = + +# The EXTRA_SEARCH_MAPPINGS tag can be used to enable searching through doxygen +# projects other than the one defined by this configuration file, but that are +# all added to the same external search index. Each project needs to have a +# unique id set via EXTERNAL_SEARCH_ID. The search mapping then maps the id +# of to a relative location where the documentation can be found. +# The format is: EXTRA_SEARCH_MAPPINGS = id1=loc1 id2=loc2 ... + +EXTRA_SEARCH_MAPPINGS = + +#--------------------------------------------------------------------------- +# configuration options related to the LaTeX output +#--------------------------------------------------------------------------- + +# If the GENERATE_LATEX tag is set to YES (the default) Doxygen will +# generate Latex output. + +GENERATE_LATEX = YES + +# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `latex' will be used as the default path. + +LATEX_OUTPUT = latex + +# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be +# invoked. If left blank `latex' will be used as the default command name. +# Note that when enabling USE_PDFLATEX this option is only used for +# generating bitmaps for formulas in the HTML output, but not in the +# Makefile that is written to the output directory. + +LATEX_CMD_NAME = latex + +# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to +# generate index for LaTeX. If left blank `makeindex' will be used as the +# default command name. + +MAKEINDEX_CMD_NAME = makeindex + +# If the COMPACT_LATEX tag is set to YES Doxygen generates more compact +# LaTeX documents. This may be useful for small projects and may help to +# save some trees in general. + +COMPACT_LATEX = NO + +# The PAPER_TYPE tag can be used to set the paper type that is used +# by the printer. Possible values are: a4, letter, legal and +# executive. If left blank a4wide will be used. + +PAPER_TYPE = a4 + +# The EXTRA_PACKAGES tag can be to specify one or more names of LaTeX +# packages that should be included in the LaTeX output. + +EXTRA_PACKAGES = + +# The LATEX_HEADER tag can be used to specify a personal LaTeX header for +# the generated latex document. The header should contain everything until +# the first chapter. If it is left blank doxygen will generate a +# standard header. Notice: only use this tag if you know what you are doing! + +LATEX_HEADER = + +# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for +# the generated latex document. The footer should contain everything after +# the last chapter. If it is left blank doxygen will generate a +# standard footer. Notice: only use this tag if you know what you are doing! + +LATEX_FOOTER = + +# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated +# is prepared for conversion to pdf (using ps2pdf). The pdf file will +# contain links (just like the HTML output) instead of page references +# This makes the output suitable for online browsing using a pdf viewer. + +PDF_HYPERLINKS = YES + +# If the USE_PDFLATEX tag is set to YES, pdflatex will be used instead of +# plain latex in the generated Makefile. Set this option to YES to get a +# higher quality PDF documentation. + +USE_PDFLATEX = YES + +# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \\batchmode. +# command to the generated LaTeX files. This will instruct LaTeX to keep +# running if errors occur, instead of asking the user for help. +# This option is also used when generating formulas in HTML. + +LATEX_BATCHMODE = NO + +# If LATEX_HIDE_INDICES is set to YES then doxygen will not +# include the index chapters (such as File Index, Compound Index, etc.) +# in the output. + +LATEX_HIDE_INDICES = NO + +# If LATEX_SOURCE_CODE is set to YES then doxygen will include +# source code with syntax highlighting in the LaTeX output. +# Note that which sources are shown also depends on other settings +# such as SOURCE_BROWSER. + +LATEX_SOURCE_CODE = NO + +# The LATEX_BIB_STYLE tag can be used to specify the style to use for the +# bibliography, e.g. plainnat, or ieeetr. The default style is "plain". See +# http://en.wikipedia.org/wiki/BibTeX for more info. + +LATEX_BIB_STYLE = plain + +#--------------------------------------------------------------------------- +# configuration options related to the RTF output +#--------------------------------------------------------------------------- + +# If the GENERATE_RTF tag is set to YES Doxygen will generate RTF output +# The RTF output is optimized for Word 97 and may not look very pretty with +# other RTF readers or editors. + +GENERATE_RTF = NO + +# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `rtf' will be used as the default path. + +RTF_OUTPUT = rtf + +# If the COMPACT_RTF tag is set to YES Doxygen generates more compact +# RTF documents. This may be useful for small projects and may help to +# save some trees in general. + +COMPACT_RTF = NO + +# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated +# will contain hyperlink fields. The RTF file will +# contain links (just like the HTML output) instead of page references. +# This makes the output suitable for online browsing using WORD or other +# programs which support those fields. +# Note: wordpad (write) and others do not support links. + +RTF_HYPERLINKS = NO + +# Load style sheet definitions from file. Syntax is similar to doxygen's +# config file, i.e. a series of assignments. You only have to provide +# replacements, missing definitions are set to their default value. + +RTF_STYLESHEET_FILE = + +# Set optional variables used in the generation of an rtf document. +# Syntax is similar to doxygen's config file. + +RTF_EXTENSIONS_FILE = + +#--------------------------------------------------------------------------- +# configuration options related to the man page output +#--------------------------------------------------------------------------- + +# If the GENERATE_MAN tag is set to YES (the default) Doxygen will +# generate man pages + +GENERATE_MAN = NO + +# The MAN_OUTPUT tag is used to specify where the man pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `man' will be used as the default path. + +MAN_OUTPUT = man + +# The MAN_EXTENSION tag determines the extension that is added to +# the generated man pages (default is the subroutine's section .3) + +MAN_EXTENSION = .3 + +# If the MAN_LINKS tag is set to YES and Doxygen generates man output, +# then it will generate one additional man file for each entity +# documented in the real man page(s). These additional files +# only source the real man page, but without them the man command +# would be unable to find the correct page. The default is NO. + +MAN_LINKS = NO + +#--------------------------------------------------------------------------- +# configuration options related to the XML output +#--------------------------------------------------------------------------- + +# If the GENERATE_XML tag is set to YES Doxygen will +# generate an XML file that captures the structure of +# the code including all documentation. + +GENERATE_XML = NO + +# The XML_OUTPUT tag is used to specify where the XML pages will be put. +# If a relative path is entered the value of OUTPUT_DIRECTORY will be +# put in front of it. If left blank `xml' will be used as the default path. + +XML_OUTPUT = xml + +# The XML_SCHEMA tag can be used to specify an XML schema, +# which can be used by a validating XML parser to check the +# syntax of the XML files. + +XML_SCHEMA = + +# The XML_DTD tag can be used to specify an XML DTD, +# which can be used by a validating XML parser to check the +# syntax of the XML files. + +XML_DTD = + +# If the XML_PROGRAMLISTING tag is set to YES Doxygen will +# dump the program listings (including syntax highlighting +# and cross-referencing information) to the XML output. Note that +# enabling this will significantly increase the size of the XML output. + +XML_PROGRAMLISTING = YES + +#--------------------------------------------------------------------------- +# configuration options for the AutoGen Definitions output +#--------------------------------------------------------------------------- + +# If the GENERATE_AUTOGEN_DEF tag is set to YES Doxygen will +# generate an AutoGen Definitions (see autogen.sf.net) file +# that captures the structure of the code including all +# documentation. Note that this feature is still experimental +# and incomplete at the moment. + +GENERATE_AUTOGEN_DEF = NO + +#--------------------------------------------------------------------------- +# configuration options related to the Perl module output +#--------------------------------------------------------------------------- + +# If the GENERATE_PERLMOD tag is set to YES Doxygen will +# generate a Perl module file that captures the structure of +# the code including all documentation. Note that this +# feature is still experimental and incomplete at the +# moment. + +GENERATE_PERLMOD = NO + +# If the PERLMOD_LATEX tag is set to YES Doxygen will generate +# the necessary Makefile rules, Perl scripts and LaTeX code to be able +# to generate PDF and DVI output from the Perl module output. + +PERLMOD_LATEX = NO + +# If the PERLMOD_PRETTY tag is set to YES the Perl module output will be +# nicely formatted so it can be parsed by a human reader. +# This is useful +# if you want to understand what is going on. +# On the other hand, if this +# tag is set to NO the size of the Perl module output will be much smaller +# and Perl will parse it just the same. + +PERLMOD_PRETTY = YES + +# The names of the make variables in the generated doxyrules.make file +# are prefixed with the string contained in PERLMOD_MAKEVAR_PREFIX. +# This is useful so different doxyrules.make files included by the same +# Makefile don't overwrite each other's variables. + +PERLMOD_MAKEVAR_PREFIX = + +#--------------------------------------------------------------------------- +# Configuration options related to the preprocessor +#--------------------------------------------------------------------------- + +# If the ENABLE_PREPROCESSING tag is set to YES (the default) Doxygen will +# evaluate all C-preprocessor directives found in the sources and include +# files. + +ENABLE_PREPROCESSING = YES + +# If the MACRO_EXPANSION tag is set to YES Doxygen will expand all macro +# names in the source code. If set to NO (the default) only conditional +# compilation will be performed. Macro expansion can be done in a controlled +# way by setting EXPAND_ONLY_PREDEF to YES. + +MACRO_EXPANSION = NO + +# If the EXPAND_ONLY_PREDEF and MACRO_EXPANSION tags are both set to YES +# then the macro expansion is limited to the macros specified with the +# PREDEFINED and EXPAND_AS_DEFINED tags. + +EXPAND_ONLY_PREDEF = NO + +# If the SEARCH_INCLUDES tag is set to YES (the default) the includes files +# pointed to by INCLUDE_PATH will be searched when a #include is found. + +SEARCH_INCLUDES = YES + +# The INCLUDE_PATH tag can be used to specify one or more directories that +# contain include files that are not input files but should be processed by +# the preprocessor. + +INCLUDE_PATH = + +# You can use the INCLUDE_FILE_PATTERNS tag to specify one or more wildcard +# patterns (like *.h and *.hpp) to filter out the header-files in the +# directories. If left blank, the patterns specified with FILE_PATTERNS will +# be used. + +INCLUDE_FILE_PATTERNS = + +# The PREDEFINED tag can be used to specify one or more macro names that +# are defined before the preprocessor is started (similar to the -D option of +# gcc). The argument of the tag is a list of macros of the form: name +# or name=definition (no spaces). If the definition and the = are +# omitted =1 is assumed. To prevent a macro definition from being +# undefined via #undef or recursively expanded use the := operator +# instead of the = operator. + +PREDEFINED = + +# If the MACRO_EXPANSION and EXPAND_ONLY_PREDEF tags are set to YES then +# this tag can be used to specify a list of macro names that should be expanded. +# The macro definition that is found in the sources will be used. +# Use the PREDEFINED tag if you want to use a different macro definition that +# overrules the definition found in the source code. + +EXPAND_AS_DEFINED = + +# If the SKIP_FUNCTION_MACROS tag is set to YES (the default) then +# doxygen's preprocessor will remove all references to function-like macros +# that are alone on a line, have an all uppercase name, and do not end with a +# semicolon, because these will confuse the parser if not removed. + +SKIP_FUNCTION_MACROS = YES + +#--------------------------------------------------------------------------- +# Configuration::additions related to external references +#--------------------------------------------------------------------------- + +# The TAGFILES option can be used to specify one or more tagfiles. For each +# tag file the location of the external documentation should be added. The +# format of a tag file without this location is as follows: +# +# TAGFILES = file1 file2 ... +# Adding location for the tag files is done as follows: +# +# TAGFILES = file1=loc1 "file2 = loc2" ... +# where "loc1" and "loc2" can be relative or absolute paths +# or URLs. Note that each tag file must have a unique name (where the name does +# NOT include the path). If a tag file is not located in the directory in which +# doxygen is run, you must also specify the path to the tagfile here. + +TAGFILES = + +# When a file name is specified after GENERATE_TAGFILE, doxygen will create +# a tag file that is based on the input files it reads. + +GENERATE_TAGFILE = + +# If the ALLEXTERNALS tag is set to YES all external classes will be listed +# in the class index. If set to NO only the inherited external classes +# will be listed. + +ALLEXTERNALS = NO + +# If the EXTERNAL_GROUPS tag is set to YES all external groups will be listed +# in the modules index. If set to NO, only the current project's groups will +# be listed. + +EXTERNAL_GROUPS = YES + +# The PERL_PATH should be the absolute path and name of the perl script +# interpreter (i.e. the result of `which perl'). + +PERL_PATH = /usr/bin/perl + +#--------------------------------------------------------------------------- +# Configuration options related to the dot tool +#--------------------------------------------------------------------------- + +# If the CLASS_DIAGRAMS tag is set to YES (the default) Doxygen will +# generate a inheritance diagram (in HTML, RTF and LaTeX) for classes with base +# or super classes. Setting the tag to NO turns the diagrams off. Note that +# this option also works with HAVE_DOT disabled, but it is recommended to +# install and use dot, since it yields more powerful graphs. + +CLASS_DIAGRAMS = YES + +# You can define message sequence charts within doxygen comments using the \msc +# command. Doxygen will then run the mscgen tool (see +# http://www.mcternan.me.uk/mscgen/) to produce the chart and insert it in the +# documentation. The MSCGEN_PATH tag allows you to specify the directory where +# the mscgen tool resides. If left empty the tool is assumed to be found in the +# default search path. + +MSCGEN_PATH = + +# If set to YES, the inheritance and collaboration graphs will hide +# inheritance and usage relations if the target is undocumented +# or is not a class. + +HIDE_UNDOC_RELATIONS = YES + +# If you set the HAVE_DOT tag to YES then doxygen will assume the dot tool is +# available from the path. This tool is part of Graphviz, a graph visualization +# toolkit from AT&T and Lucent Bell Labs. The other options in this section +# have no effect if this option is set to NO (the default) + +HAVE_DOT = NO + +# The DOT_NUM_THREADS specifies the number of dot invocations doxygen is +# allowed to run in parallel. When set to 0 (the default) doxygen will +# base this on the number of processors available in the system. You can set it +# explicitly to a value larger than 0 to get control over the balance +# between CPU load and processing speed. + +DOT_NUM_THREADS = 0 + +# By default doxygen will use the Helvetica font for all dot files that +# doxygen generates. When you want a differently looking font you can specify +# the font name using DOT_FONTNAME. You need to make sure dot is able to find +# the font, which can be done by putting it in a standard location or by setting +# the DOTFONTPATH environment variable or by setting DOT_FONTPATH to the +# directory containing the font. + +DOT_FONTNAME = Helvetica + +# The DOT_FONTSIZE tag can be used to set the size of the font of dot graphs. +# The default size is 10pt. + +DOT_FONTSIZE = 10 + +# By default doxygen will tell dot to use the Helvetica font. +# If you specify a different font using DOT_FONTNAME you can use DOT_FONTPATH to +# set the path where dot can find it. + +DOT_FONTPATH = + +# If the CLASS_GRAPH and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for each documented class showing the direct and +# indirect inheritance relations. Setting this tag to YES will force the +# CLASS_DIAGRAMS tag to NO. + +CLASS_GRAPH = YES + +# If the COLLABORATION_GRAPH and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for each documented class showing the direct and +# indirect implementation dependencies (inheritance, containment, and +# class references variables) of the class with other documented classes. + +COLLABORATION_GRAPH = YES + +# If the GROUP_GRAPHS and HAVE_DOT tags are set to YES then doxygen +# will generate a graph for groups, showing the direct groups dependencies + +GROUP_GRAPHS = YES + +# If the UML_LOOK tag is set to YES doxygen will generate inheritance and +# collaboration diagrams in a style similar to the OMG's Unified Modeling +# Language. + +UML_LOOK = NO + +# If the UML_LOOK tag is enabled, the fields and methods are shown inside +# the class node. If there are many fields or methods and many nodes the +# graph may become too big to be useful. The UML_LIMIT_NUM_FIELDS +# threshold limits the number of items for each type to make the size more +# managable. Set this to 0 for no limit. Note that the threshold may be +# exceeded by 50% before the limit is enforced. + +UML_LIMIT_NUM_FIELDS = 10 + +# If set to YES, the inheritance and collaboration graphs will show the +# relations between templates and their instances. + +TEMPLATE_RELATIONS = NO + +# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDE_GRAPH, and HAVE_DOT +# tags are set to YES then doxygen will generate a graph for each documented +# file showing the direct and indirect include dependencies of the file with +# other documented files. + +INCLUDE_GRAPH = YES + +# If the ENABLE_PREPROCESSING, SEARCH_INCLUDES, INCLUDED_BY_GRAPH, and +# HAVE_DOT tags are set to YES then doxygen will generate a graph for each +# documented header file showing the documented files that directly or +# indirectly include this file. + +INCLUDED_BY_GRAPH = YES + +# If the CALL_GRAPH and HAVE_DOT options are set to YES then +# doxygen will generate a call dependency graph for every global function +# or class method. Note that enabling this option will significantly increase +# the time of a run. So in most cases it will be better to enable call graphs +# for selected functions only using the \callgraph command. + +CALL_GRAPH = NO + +# If the CALLER_GRAPH and HAVE_DOT tags are set to YES then +# doxygen will generate a caller dependency graph for every global function +# or class method. Note that enabling this option will significantly increase +# the time of a run. So in most cases it will be better to enable caller +# graphs for selected functions only using the \callergraph command. + +CALLER_GRAPH = NO + +# If the GRAPHICAL_HIERARCHY and HAVE_DOT tags are set to YES then doxygen +# will generate a graphical hierarchy of all classes instead of a textual one. + +GRAPHICAL_HIERARCHY = YES + +# If the DIRECTORY_GRAPH and HAVE_DOT tags are set to YES +# then doxygen will show the dependencies a directory has on other directories +# in a graphical way. The dependency relations are determined by the #include +# relations between the files in the directories. + +DIRECTORY_GRAPH = YES + +# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images +# generated by dot. Possible values are svg, png, jpg, or gif. +# If left blank png will be used. If you choose svg you need to set +# HTML_FILE_EXTENSION to xhtml in order to make the SVG files +# visible in IE 9+ (other browsers do not have this requirement). + +DOT_IMAGE_FORMAT = png + +# If DOT_IMAGE_FORMAT is set to svg, then this option can be set to YES to +# enable generation of interactive SVG images that allow zooming and panning. +# Note that this requires a modern browser other than Internet Explorer. +# Tested and working are Firefox, Chrome, Safari, and Opera. For IE 9+ you +# need to set HTML_FILE_EXTENSION to xhtml in order to make the SVG files +# visible. Older versions of IE do not have SVG support. + +INTERACTIVE_SVG = NO + +# The tag DOT_PATH can be used to specify the path where the dot tool can be +# found. If left blank, it is assumed the dot tool can be found in the path. + +DOT_PATH = + +# The DOTFILE_DIRS tag can be used to specify one or more directories that +# contain dot files that are included in the documentation (see the +# \dotfile command). + +DOTFILE_DIRS = + +# The MSCFILE_DIRS tag can be used to specify one or more directories that +# contain msc files that are included in the documentation (see the +# \mscfile command). + +MSCFILE_DIRS = + +# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of +# nodes that will be shown in the graph. If the number of nodes in a graph +# becomes larger than this value, doxygen will truncate the graph, which is +# visualized by representing a node as a red box. Note that doxygen if the +# number of direct children of the root node in a graph is already larger than +# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note +# that the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH. + +DOT_GRAPH_MAX_NODES = 50 + +# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the +# graphs generated by dot. A depth value of 3 means that only nodes reachable +# from the root by following a path via at most 3 edges will be shown. Nodes +# that lay further from the root node will be omitted. Note that setting this +# option to 1 or 2 may greatly reduce the computation time needed for large +# code bases. Also note that the size of a graph can be further restricted by +# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction. + +MAX_DOT_GRAPH_DEPTH = 0 + +# Set the DOT_TRANSPARENT tag to YES to generate images with a transparent +# background. This is disabled by default, because dot on Windows does not +# seem to support this out of the box. Warning: Depending on the platform used, +# enabling this option may lead to badly anti-aliased labels on the edges of +# a graph (i.e. they become hard to read). + +DOT_TRANSPARENT = NO + +# Set the DOT_MULTI_TARGETS tag to YES allow dot to generate multiple output +# files in one run (i.e. multiple -o and -T options on the command line). This +# makes dot run faster, but since only newer versions of dot (>1.8.10) +# support this, this feature is disabled by default. + +DOT_MULTI_TARGETS = NO + +# If the GENERATE_LEGEND tag is set to YES (the default) Doxygen will +# generate a legend page explaining the meaning of the various boxes and +# arrows in the dot generated graphs. + +GENERATE_LEGEND = YES + +# If the DOT_CLEANUP tag is set to YES (the default) Doxygen will +# remove the intermediate dot files that are used to generate +# the various graphs. + +DOT_CLEANUP = YES Index: /branches/fault_tolerance/softs/tsar_boot/Makefile =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/Makefile (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/Makefile (revision 724) @@ -0,0 +1,145 @@ +# let the user have a default configuration (ie for PLATFORM_DIR and SOCLIB) +-include ./build.mk + +MAKECMDGOALS ?= none +RAMDISK ?= 0 +SOCLIB ?= 0 + +ifneq ($(MAKECMDGOALS),$(filter $(MAKECMDGOALS),clean distclean clean-doc doc)) + ifndef PLATFORM_DIR + $(error please define PLATFORM_DIR 'make PLATFORM_DIR=foo') + else + ifeq ($(SOCLIB),1) + ifeq ($(RAMDISK),1) + DEFS+= -DUSE_RDK + else + DEFS+= -DUSE_BDV + endif + DTS=platform_soclib.dts + $(info Make for $(PLATFORM_DIR), SocLib variant) + else + DEFS+= -DUSE_SPI + DTS=platform_fpga.dts + $(info Make for $(PLATFORM_DIR), FPGA variant) + endif + endif +endif + +LD := mipsel-unknown-elf-ld +CC := mipsel-unknown-elf-gcc +AS := mipsel-unknown-elf-as +DU := mipsel-unknown-elf-objdump +RM := rm -rf +ECHO := @echo +MKDIR := mkdir +DTC := dtc +HEXDUMP := hexdump +DOXYGEN := doxygen + +BUILD_DIR := build +SRCS_DIR := src +INCS_DIR := include + +# ============================================================================= +# Include files paths +# ============================================================================= + +INCLUDE += -I. -I$(INCS_DIR) -I$(PLATFORM_DIR) + +# ============================================================================= +# Paths of sources in another directories +# ============================================================================= + +VPATH += $(SRCS_DIR) +VPATH += $(PLATFORM_DIR) + +# ============================================================================= +# Object files +# ============================================================================= + +CFLAGS := -Wall \ + -mno-gpopt \ + -ffreestanding \ + -fomit-frame-pointer \ + -mips32 \ + -ggdb \ + -mlong-calls \ + -O2 \ + -Werror + +C_SRCS := reset_elf_loader.c \ + reset_ioc.c \ + reset_utils.c \ + reset_tty.c \ + reset_exception.c + +ifeq ($(SOCLIB),0) + C_SRCS += sdcard.c spi.c +endif + +S_SRCS := reset.S + +OBJS := $(subst .c,.o, $(notdir $(C_SRCS))) +OBJS += $(subst .S,.o, $(notdir $(S_SRCS))) +OBJS := $(addprefix $(BUILD_DIR)/, $(OBJS)) + +TARGET := preloader.elf + +USE_DT ?= 1 + +all: $(TARGET) + +$(BUILD_DIR)/version.o: $(BUILD_DIR) $(OBJS) version version.sh + $(ECHO) "[version.sh]" + ./version.sh > $(BUILD_DIR)/version.c + $(ECHO) "[ CC ] $(BUILD_DIR)/version.c" + $(CC) $(DEFS) $(CFLAGS) $(INCLUDE) -c -o $@ $(BUILD_DIR)/version.c + $(DU) -D $@ > $@.txt + +$(TARGET): $(BUILD_DIR) $(BUILD_DIR)/version.o $(OBJS) $(PLATFORM_DIR)/ldscript $(BUILD_DIR)/platform.ld + $(ECHO) "[ LD ] $@" + $(LD) -o $@ -T $(PLATFORM_DIR)/ldscript $(OBJS) $(BUILD_DIR)/version.o + $(DU) -D $@ > $@.txt + +ifeq ($(USE_DT), 1) +$(BUILD_DIR)/platform.ld: $(BUILD_DIR)/platform.dtb + $(ECHO) "[ HEXDUMP ] $(notdir $<)" + $(HEXDUMP) -v -e '"BYTE(0x" 1/1 "%02X" ")\n"' $< > $@ +else +$(BUILD_DIR)/platform.ld: + $(ECHO) "[ TOUCH ] $(notdir $@)" + touch $@ +endif + +$(BUILD_DIR)/platform.dtb: $(DTS) + $(ECHO) "[ DTC ] $(notdir $<)" + ${DTC} -O dtb -o $@ $< &> /dev/null + +$(BUILD_DIR): + $(MKDIR) $@ + +doc: Doxyfile + $(DOXYGEN) Doxyfile + +clean: + $(RM) $(TARGET).txt $(TARGET) *~ $(BUILD_DIR) + +clean-doc: + $(RM) doc + +distclean: clean clean-doc + +# ============================================================================= +# Implicit makefile rules + +$(BUILD_DIR)/%.o: %.c + $(ECHO) "[ CC ] $(notdir $<)" + $(CC) $(DEFS) $(CFLAGS) $(INCLUDE) -c -o $@ $< + $(DU) -D $@ > $@.txt + +$(BUILD_DIR)/%.o: %.S + $(ECHO) "[ AS ] $(notdir $<)" + $(CC) $(DEFS) ${INCLUDE} -g -mips32 -c -o $@ $< + $(DU) -D $@ > $@.txt + +.SILENT: Index: /branches/fault_tolerance/softs/tsar_boot/README =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/README (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/README (revision 724) @@ -0,0 +1,97 @@ +TSAR BOOT LOADER + +Files: +=============================================================================== +src/ Source files + The entry point of this boot loader is the file reset.S + +include/ Header files + +conf/ Platform specific files and ldscript examples. + For each platform, we must define a new directory. + + - defs_platform.h: + + This file is mandatory. This file defines the NB_PROCS per + cluster, the NB_CLUSTERS and the base address of the TTY, IOC, + XICU and MEMC (config) devices. It defines also: + + #define USE_IOB + + This constant is used by the boot_ioc_read function to know + if the buffer used to store the blocks from the block_device + must be invalidated in the memory cache after the transfert + has finished. + + #define CACHE_COHERENCE + + This constant is used by the boot_ioc_read function to know + if the buffer used to store the blocks from the block_device + must be invalidated in the dcache after the transfert has + finished. + + #define CACHE_LINE_SIZE + + This constant is mandatory if CACHE_COHERENCE=0 or USE_IOB=1 + This constant defines the size in bytes of a cache line. + + #define RESET_DEBUG + + Set value to 1 to show some debug messages during loading + + #define IRQ_PER_PROC + + This constant is used to know how many XICU irq outputs are + connected to each processor. + + - platform_soclib.dts: + + Device tree file. It is mandatory if compiling for a SOCLIB + platform and USE_DT=1. + + - platform_fpga.dts: + + Device tree file. It is mandatory if compiling for a FPGA + platform and USE_DT=1. + + - ldscript: + + LD script defining the segments of this boot loader. + We define two segments: + + seg_stack_base: + + Base address of the stack used by processor 0 during the boot + process. read-write data and bss will also be there. + + seg_boot_base: + + Base address of the code and read-only data defined for this + loader + +Makefile Makefile to compile the boot loader. Arguments to pass: + + PLATFORM_DIR= + + Defines the directory where to find the plateform specific + files + + SOCLIB=1 + + If using SOCLIB, define this flag to use the BLOCK DEVICE + driver and to choose the platform_soclib device tree. + + RAMDISK=1 + + If using SOCLIB, define this flag to use a RAMDISK instead of + BLOCK DEVICE (Set this flag when the SOCLIB flag is also set) + + USE_DT=0 + + If a device tree file is not used, set this flag to 0. It is + set by default to 1. + + e.g. make PLATFORM_DIR= \ + SOCLIB=1 \ + USE_DT=0 \ + RAMDISK=0 Index: /branches/fault_tolerance/softs/tsar_boot/VERSION =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/VERSION (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/VERSION (revision 724) @@ -0,0 +1,1 @@ +1.1 Index: /branches/fault_tolerance/softs/tsar_boot/conf/platform_fpga_de2-115/defs_platform.h =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/conf/platform_fpga_de2-115/defs_platform.h (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/conf/platform_fpga_de2-115/defs_platform.h (revision 724) @@ -0,0 +1,20 @@ +#define NB_PROCS 1 +#define NB_CLUSTERS 1 + +#define IRQ_PER_PROC 1 + +#define USE_IOB 0 +#define CACHE_COHERENCE 1 +#define CACHE_LINE_SIZE 64//bytes + +#define RESET_DEBUG 0 + +#define ICU_PADDR_BASE 0xFD000000 +#define MCC_PADDR_BASE 0xFFFFFFFF // not used +#define IOC_PADDR_BASE 0xFB000000 +#define TTY_PADDR_BASE 0xFC000000 +#define RDK_PADDR_BASE 0xFFFFFFFF // not used + +/* Mandatory argument only for FPGA platforms */ + +#define SYSCLK_FREQ 25000000//Hz Index: /branches/fault_tolerance/softs/tsar_boot/conf/platform_fpga_de2-115/ldscript =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/conf/platform_fpga_de2-115/ldscript (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/conf/platform_fpga_de2-115/ldscript (revision 724) @@ -0,0 +1,37 @@ +/********************************************************** + File : ldscript + Author : Cesar Fuguet + Date : June 2011 +**********************************************************/ + +/* Definition of the base address for code segment */ + +seg_reset_code_base = 0xBFC00000; + +seg_reset_stack_base = 0x08000000 - 0x4000;; +seg_reset_stack_size = 0x4000; + +/* Grouping sections into segments */ + +ENTRY(reset) + +SECTIONS +{ + . = seg_reset_code_base; + .text : + { + *(.reset) + *(.rodata) + *(.rodata.*) + . = ALIGN(0x4); + dtb_addr = .; + INCLUDE "build/platform.ld"; + } + + . = seg_reset_stack_base; + .bss ALIGN(0x4) (NOLOAD) : + { + *(.data) + *(.bss) + } +} Index: /branches/fault_tolerance/softs/tsar_boot/conf/platform_fpga_de2-115/platform_fpga.dts =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/conf/platform_fpga_de2-115/platform_fpga.dts (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/conf/platform_fpga_de2-115/platform_fpga.dts (revision 724) @@ -0,0 +1,98 @@ +/dts-v1/; + +/ { + #address-cells = <0x1>; + #size-cells = <0x1>; + + cpus { + #address-cells = <0x1>; + #size-cells = <0x0>; + + Mips,32@0 { + device_type = "cpu"; + icudev_type = "cpu:mips"; + name = "Mips,32"; + reg = <0x00000000>; + }; + }; + + memory@0x00000000 { + cached = <0x1>; + device_type = "memory"; + reg = <0x00000000 0x08000000>; + }; + + memory@0xbfc00000 { + cached = <0x1>; + device_type = "rom"; + reg = <0xbfc00000 0x00010000>; + }; + + tty@0xfc000000 { + device_type = "vci:tty"; + irq = <&{/xicu@0xfd000000} 0x0>; + reg = <0xfc000000 0x00000010>; + tty_count = <0x1>; + }; + + blockdevice@0xfb000000 { + device_type = "vci:ioc"; + irq = <&{/xicu@0xfd000000} 0x1>; + reg = <0xfb000000 0x00000020>; + }; + + fb@0xfa000000 { + device_type = "soclib:frame_buffer"; + reg = <0xfa000000 0x00200000>; + mode = <16>; + width = <640>; + height = <480>; + }; + + vcikbc@0xfe000000 { + device_type = "vci:ps2"; + irq = <&{/xicu@0xfd000000} 0x2>; + reg = <0xfe000000 0x00000020>; + ports = <0x2>; + }; + + + xicu@0xfd000000 { + device_type = "soclib:xicu:root"; + input_lines = <0x2>; + ipis = <0x1>; + reg = <0xfd000000 0x00001000>; + timers = <0x1>; + timer-freq = <25000000>; + + out@0 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@0} 0x0>; + output_line = <0x0>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@1 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@0} 0x1>; + output_line = <0x1>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@2 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@0} 0x2>; + output_line = <0x2>; + parent = <&{/xicu@0xfd000000}>; + }; + }; + + topology { + #address-cells = <2>; + #size-cells = <0>; + cluster@0,0 { + reg = <0 0>; + devices = <&{/cpus/Mips,32@0} &{/xicu@0xfd000000} &{/tty@0xfc000000} &{/blockdevice@0xfb000000} &{/fb@0xfa000000} &{/vcikbc@0xfe000000} >; + }; + }; +}; Index: /branches/fault_tolerance/softs/tsar_boot/conf/platform_fpga_de2-115/platform_soclib.dts =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/conf/platform_fpga_de2-115/platform_soclib.dts (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/conf/platform_fpga_de2-115/platform_soclib.dts (revision 724) @@ -0,0 +1,176 @@ +/dts-v1/; + +/ { + #address-cells = <0x1>; + #size-cells = <0x1>; + + cpus { + #address-cells = <0x1>; + #size-cells = <0x0>; + + Mips,32@0 { + device_type = "cpu"; + icudev_type = "cpu:mips"; + name = "Mips,32"; + reg = <0x00000000>; + }; + + Mips,32@1 { + device_type = "cpu"; + icudev_type = "cpu:mips"; + name = "Mips,32"; + reg = <0x00000001>; + }; + + Mips,32@2 { + device_type = "cpu"; + icudev_type = "cpu:mips"; + name = "Mips,32"; + reg = <0x00000002>; + }; + + Mips,32@3 { + device_type = "cpu"; + icudev_type = "cpu:mips"; + name = "Mips,32"; + reg = <0x00000003>; + }; + }; + + memory@0x00000000 { + cached = <0x1>; + device_type = "memory"; + reg = <0x00000000 0x08000000>; + }; + + memory@0xbfc00000 { + cached = <0x1>; + device_type = "rom"; + reg = <0xbfc00000 0x00400000>; + }; + + tty@0xfc000000 { + device_type = "soclib:tty"; + irq = <&{/xicu@0xfd000000} 0x0>; + reg = <0xfc000000 0x00000010>; + tty_count = <0x1>; + }; + simhelper@0xf1000000 { + device_type = "soclib:simhelper"; + reg = <0xf1000000 0x00000010>; + }; + + blockdevice@0xfb000000 { + device_type = "soclib:blockdevice"; + irq = <&{/xicu@0xfd000000} 0x1>; + reg = <0xfb000000 0x00000020>; + }; + + fb@0xf0000000 { + device_type = "soclib:frame_buffer"; + reg = <0xf0000000 0x400000>; + mode = <32>; + width = <640>; + height = <480>; + }; + + xicu@0xfd000000 { + device_type = "soclib:xicu:root"; + input_lines = <0x2>; + ipis = <0x4>; + reg = <0xfd000000 0x00001000>; + timers = <0x4>; + + out@0 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@0} 0x0>; + output_line = <0x0>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@1 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@0} 0x1>; + output_line = <0x1>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@2 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@0} 0x2>; + output_line = <0x2>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@3 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@1} 0x0>; + output_line = <0x3>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@4 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@1} 0x1>; + output_line = <0x4>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@5 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@1} 0x2>; + output_line = <0x5>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@6 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@2} 0x0>; + output_line = <0x6>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@7 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@2} 0x1>; + output_line = <0x7>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@8 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@2} 0x2>; + output_line = <0x8>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@9 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@3} 0x0>; + output_line = <0x9>; + parent = <&{/xicu@0xfd000000}>; + }; + out@10 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@3} 0x1>; + output_line = <0xa>; + parent = <&{/xicu@0xfd000000}>; + }; + + out@11 { + device_type = "soclib:xicu:filter"; + irq = <&{/cpus/Mips,32@3} 0x2>; + output_line = <0xb>; + parent = <&{/xicu@0xfd000000}>; + }; + + }; + topology { + #address-cells = <2>; + #size-cells = <0>; + cluster@0,0 { + reg = <0 0>; + devices = <&{/cpus/Mips,32@0} &{/cpus/Mips,32@1} &{/cpus/Mips,32@2} &{/cpus/Mips,32@3} &{/xicu@0xfd000000} &{/tty@0xfc000000} &{/simhelper@0xf1000000} &{/blockdevice@0xfb000000} &{/fb@0xf0000000} >; + }; + }; +}; Index: /branches/fault_tolerance/softs/tsar_boot/conf/platform_tsar_generic_iob/defs_platform.h =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/conf/platform_tsar_generic_iob/defs_platform.h (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/conf/platform_tsar_generic_iob/defs_platform.h (revision 724) @@ -0,0 +1,15 @@ +#define NB_PROCS 1 +#define NB_CLUSTERS 4 + +#define IRQ_PER_PROC 1 + +#define USE_IOB 1 +#define CACHE_COHERENCE 1 +#define CACHE_LINE_SIZE 64 // bytes (ie 16 x 32-bit word) +#define RESET_DEBUG 0 + +#define ICU_PADDR_BASE 0xB0000000 +#define MCC_PADDR_BASE 0xB2000000 +#define IOC_PADDR_BASE 0xB3000000 +#define TTY_PADDR_BASE 0xB4000000 +#define RDK_PADDR_BASE 0xFFFFFFFF // not used Index: /branches/fault_tolerance/softs/tsar_boot/conf/platform_tsar_generic_iob/ldscript =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/conf/platform_tsar_generic_iob/ldscript (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/conf/platform_tsar_generic_iob/ldscript (revision 724) @@ -0,0 +1,37 @@ +/********************************************************** + File : ldscript + Author : Cesar Fuguet + Date : June 2011 +**********************************************************/ + +/* Definition of the base address for code segment */ + +seg_reset_code_base = 0xBFC00000; + +seg_reset_stack_base = 0x00060000; +seg_reset_stack_size = 0x00090000; + +/* Grouping sections into segments */ + +ENTRY(reset) + +SECTIONS +{ + . = seg_reset_code_base; + .text : + { + *(.reset) + *(.rodata) + *(.rodata.*) + . = ALIGN(0x4); + dtb_addr = .; + INCLUDE "build/platform.ld"; + } + + . = seg_reset_stack_base; + .bss ALIGN(0x4) (NOLOAD) : + { + *(.data) + *(.bss) + } +} Index: /branches/fault_tolerance/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/defs_platform.h =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/defs_platform.h (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/defs_platform.h (revision 724) @@ -0,0 +1,15 @@ +#define NB_PROCS 1 +#define NB_CLUSTERS 1 + +#define IRQ_PER_PROC 1 + +#define USE_IOB 0 +#define CACHE_COHERENCE 1 +#define CACHE_LINE_SIZE 64 // bytes (ie 16 x 32-bit word) +#define RESET_DEBUG 0 + +#define TTY_PADDR_BASE 0x20000000 +#define ICU_PADDR_BASE 0x30000000 +#define IOC_PADDR_BASE 0x40000000 +#define MCC_PADDR_BASE 0xFFFFFFFF // not used +#define RDK_PADDR_BASE 0xFFFFFFFF // not used Index: /branches/fault_tolerance/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/ldscript =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/ldscript (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/ldscript (revision 724) @@ -0,0 +1,37 @@ +/********************************************************** + File : ldscript + Author : Cesar Fuguet + Date : June 2011 +**********************************************************/ + +/* Definition of the base address for code segment */ + +seg_reset_boot_base = 0xBFC00000; /* le code de boot */ + +seg_reset_stack_base = 0x10000000 - 0x8000 - 0x4; +seg_reset_stack_base = 0x00008000; + +/* Grouping sections into segments */ + +ENTRY(reset) + +SECTIONS +{ + . = seg_reset_code_base; + .text : + { + *(.reset) + *(.rodata) + *(.rodata.*) + . = ALIGN(0x4); + dtb_addr = .; + INCLUDE "build/platform.ld"; + } + + . = seg_reset_stack_base; + .bss ALIGN(0x4) (NOLOAD) : + { + *(.data) + *(.bss) + } +} Index: /branches/fault_tolerance/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/platform_soclib.dts =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/platform_soclib.dts (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/conf/platform_tsarv4_mono_mmu_ioc/platform_soclib.dts (revision 724) @@ -0,0 +1,5 @@ +/dts-v1/; + +/ { +}; + Index: /branches/fault_tolerance/softs/tsar_boot/include/block_device.h =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/include/block_device.h (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/include/block_device.h (revision 724) @@ -0,0 +1,67 @@ +/* + * SOCLIB_LGPL_HEADER_BEGIN + * + * This file is part of SoCLib, GNU LGPLv2.1. + * + * SoCLib is free software; you can redistribute it and/or modify it + * under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; version 2.1 of the License. + * + * SoCLib is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with SoCLib; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301 USA + * + * SOCLIB_LGPL_HEADER_END + * + * Copyright (c) UPMC, Lip6, Asim + * Nicolas Pouillon , 2007 + * + * Maintainers: nipo + */ +#ifndef BLOCK_DEVICE_REGS_H +#define BLOCK_DEVICE_REGS_H + +enum SoclibBlockDeviceRegisters { + BLOCK_DEVICE_BUFFER, + BLOCK_DEVICE_LBA, + BLOCK_DEVICE_COUNT, + BLOCK_DEVICE_OP, + BLOCK_DEVICE_STATUS, + BLOCK_DEVICE_IRQ_ENABLE, + BLOCK_DEVICE_SIZE, + BLOCK_DEVICE_BLOCK_SIZE, +}; + +enum SoclibBlockDeviceOp { + BLOCK_DEVICE_NOOP, + BLOCK_DEVICE_READ, + BLOCK_DEVICE_WRITE, +}; + +enum SoclibBlockDeviceStatus { + BLOCK_DEVICE_IDLE, + BLOCK_DEVICE_BUSY, + BLOCK_DEVICE_READ_SUCCESS, + BLOCK_DEVICE_WRITE_SUCCESS, + BLOCK_DEVICE_READ_ERROR, + BLOCK_DEVICE_WRITE_ERROR, + BLOCK_DEVICE_ERROR, +}; + +#endif /* BLOCK_DEVICE_REGS_H */ + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: /branches/fault_tolerance/softs/tsar_boot/include/defs.h =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/include/defs.h (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/include/defs.h (revision 724) @@ -0,0 +1,15 @@ +#include + +#define RESET_VERSION 0x00010002 + +#define BOOT_LOADER_LBA 2 +#define PHDR_ARRAY_SIZE 16 + +#define BLOCK_SIZE 512 + +#ifndef CLUSTER_IO +# define CLUSTER_IO 0 +#endif + +// vim: tabstop=4 : softtabstop=4 : shiftwidth=4 : expandtab + Index: /branches/fault_tolerance/softs/tsar_boot/include/elf-types.h =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/include/elf-types.h (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/include/elf-types.h (revision 724) @@ -0,0 +1,2645 @@ +/* This file defines standard ELF types, structures, and macros. + Copyright (C) 1995-2003,2004,2005,2006,2007 Free Software Foundation, Inc. + This file is part of the GNU C Library. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, write to the Free + Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + 02111-1307 USA. */ + +#ifndef _ELF_TYPES_H +#define _ELF_TYPES_H + +/* Type for a 16-bit quantity. */ +typedef unsigned short Elf32_Half; +typedef unsigned short Elf64_Half; + +/* Types for signed and unsigned 32-bit quantities. */ +typedef unsigned int Elf32_Word; +typedef int Elf32_Sword; +typedef unsigned int Elf64_Word; +typedef int Elf64_Sword; + +/* Types for signed and unsigned 64-bit quantities. */ +typedef unsigned long Elf32_Xword; +typedef long Elf32_Sxword; +typedef unsigned long Elf64_Xword; +typedef long Elf64_Sxword; + +/* Type of addresses. */ +typedef unsigned int Elf32_Addr; +typedef unsigned long Elf64_Addr; + +/* Type of file offsets. */ +typedef unsigned int Elf32_Off; +typedef unsigned long Elf64_Off; + +/* Type for section indices, which are 16-bit quantities. */ +typedef unsigned short Elf32_Section; +typedef unsigned short Elf64_Section; + +/* Type for version symbol information. */ +typedef Elf32_Half Elf32_Versym; +typedef Elf64_Half Elf64_Versym; + + +/* The ELF file header. This appears at the start of every ELF file. */ + +#define EI_NIDENT (16) + +typedef struct +{ + unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ + Elf32_Half e_type; /* Object file type */ + Elf32_Half e_machine; /* Architecture */ + Elf32_Word e_version; /* Object file version */ + Elf32_Addr e_entry; /* Entry point virtual address */ + Elf32_Off e_phoff; /* Program header table file offset */ + Elf32_Off e_shoff; /* Section header table file offset */ + Elf32_Word e_flags; /* Processor-specific flags */ + Elf32_Half e_ehsize; /* ELF header size in bytes */ + Elf32_Half e_phentsize; /* Program header table entry size */ + Elf32_Half e_phnum; /* Program header table entry count */ + Elf32_Half e_shentsize; /* Section header table entry size */ + Elf32_Half e_shnum; /* Section header table entry count */ + Elf32_Half e_shstrndx; /* Section header string table index */ +} Elf32_Ehdr; + +typedef struct +{ + unsigned char e_ident[EI_NIDENT]; /* Magic number and other info */ + Elf64_Half e_type; /* Object file type */ + Elf64_Half e_machine; /* Architecture */ + Elf64_Word e_version; /* Object file version */ + Elf64_Addr e_entry; /* Entry point virtual address */ + Elf64_Off e_phoff; /* Program header table file offset */ + Elf64_Off e_shoff; /* Section header table file offset */ + Elf64_Word e_flags; /* Processor-specific flags */ + Elf64_Half e_ehsize; /* ELF header size in bytes */ + Elf64_Half e_phentsize; /* Program header table entry size */ + Elf64_Half e_phnum; /* Program header table entry count */ + Elf64_Half e_shentsize; /* Section header table entry size */ + Elf64_Half e_shnum; /* Section header table entry count */ + Elf64_Half e_shstrndx; /* Section header string table index */ +} Elf64_Ehdr; + +/* Fields in the e_ident array. The EI_* macros are indices into the + array. The macros under each EI_* macro are the values the byte + may have. */ + +#define EI_MAG0 0 /* File identification byte 0 index */ +#define ELFMAG0 0x7f /* Magic number byte 0 */ + +#define EI_MAG1 1 /* File identification byte 1 index */ +#define ELFMAG1 'E' /* Magic number byte 1 */ + +#define EI_MAG2 2 /* File identification byte 2 index */ +#define ELFMAG2 'L' /* Magic number byte 2 */ + +#define EI_MAG3 3 /* File identification byte 3 index */ +#define ELFMAG3 'F' /* Magic number byte 3 */ + +/* Conglomeration of the identification bytes, for easy testing as a word. */ +#define ELFMAG "\177ELF" +#define SELFMAG 4 + +#define EI_CLASS 4 /* File class byte index */ +#define ELFCLASSNONE 0 /* Invalid class */ +#define ELFCLASS32 1 /* 32-bit objects */ +#define ELFCLASS64 2 /* 64-bit objects */ +#define ELFCLASSNUM 3 + +#define EI_DATA 5 /* Data encoding byte index */ +#define ELFDATANONE 0 /* Invalid data encoding */ +#define ELFDATA2LSB 1 /* 2's complement, little endian */ +#define ELFDATA2MSB 2 /* 2's complement, big endian */ +#define ELFDATANUM 3 + +#define EI_VERSION 6 /* File version byte index */ + /* Value must be EV_CURRENT */ + +#define EI_OSABI 7 /* OS ABI identification */ +#define ELFOSABI_NONE 0 /* UNIX System V ABI */ +#define ELFOSABI_SYSV 0 /* Alias. */ +#define ELFOSABI_HPUX 1 /* HP-UX */ +#define ELFOSABI_NETBSD 2 /* NetBSD. */ +#define ELFOSABI_LINUX 3 /* Linux. */ +#define ELFOSABI_SOLARIS 6 /* Sun Solaris. */ +#define ELFOSABI_AIX 7 /* IBM AIX. */ +#define ELFOSABI_IRIX 8 /* SGI Irix. */ +#define ELFOSABI_FREEBSD 9 /* FreeBSD. */ +#define ELFOSABI_TRU64 10 /* Compaq TRU64 UNIX. */ +#define ELFOSABI_MODESTO 11 /* Novell Modesto. */ +#define ELFOSABI_OPENBSD 12 /* OpenBSD. */ +#define ELFOSABI_ARM 97 /* ARM */ +#define ELFOSABI_STANDALONE 255 /* Standalone (embedded) application */ + +#define EI_ABIVERSION 8 /* ABI version */ + +#define EI_PAD 9 /* Byte index of padding bytes */ + +/* Legal values for e_type (object file type). */ + +#define ET_NONE 0 /* No file type */ +#define ET_REL 1 /* Relocatable file */ +#define ET_EXEC 2 /* Executable file */ +#define ET_DYN 3 /* Shared object file */ +#define ET_CORE 4 /* Core file */ +#define ET_NUM 5 /* Number of defined types */ +#define ET_LOOS 0xfe00 /* OS-specific range start */ +#define ET_HIOS 0xfeff /* OS-specific range end */ +#define ET_LOPROC 0xff00 /* Processor-specific range start */ +#define ET_HIPROC 0xffff /* Processor-specific range end */ + +/* Legal values for e_machine (architecture). */ + +#define EM_NONE 0 /* No machine */ +#define EM_M32 1 /* AT&T WE 32100 */ +#define EM_SPARC 2 /* SUN SPARC */ +#define EM_386 3 /* Intel 80386 */ +#define EM_68K 4 /* Motorola m68k family */ +#define EM_88K 5 /* Motorola m88k family */ +#define EM_860 7 /* Intel 80860 */ +#define EM_MIPS 8 /* MIPS R3000 big-endian */ +#define EM_S370 9 /* IBM System/370 */ +#define EM_MIPS_RS3_LE 10 /* MIPS R3000 little-endian */ + +#define EM_PARISC 15 /* HPPA */ +#define EM_VPP500 17 /* Fujitsu VPP500 */ +#define EM_SPARC32PLUS 18 /* Sun's "v8plus" */ +#define EM_960 19 /* Intel 80960 */ +#define EM_PPC 20 /* PowerPC */ +#define EM_PPC64 21 /* PowerPC 64-bit */ +#define EM_S390 22 /* IBM S390 */ + +#define EM_V800 36 /* NEC V800 series */ +#define EM_FR20 37 /* Fujitsu FR20 */ +#define EM_RH32 38 /* TRW RH-32 */ +#define EM_RCE 39 /* Motorola RCE */ +#define EM_ARM 40 /* ARM */ +#define EM_FAKE_ALPHA 41 /* Digital Alpha */ +#define EM_SH 42 /* Hitachi SH */ +#define EM_SPARCV9 43 /* SPARC v9 64-bit */ +#define EM_TRICORE 44 /* Siemens Tricore */ +#define EM_ARC 45 /* Argonaut RISC Core */ +#define EM_H8_300 46 /* Hitachi H8/300 */ +#define EM_H8_300H 47 /* Hitachi H8/300H */ +#define EM_H8S 48 /* Hitachi H8S */ +#define EM_H8_500 49 /* Hitachi H8/500 */ +#define EM_IA_64 50 /* Intel Merced */ +#define EM_MIPS_X 51 /* Stanford MIPS-X */ +#define EM_COLDFIRE 52 /* Motorola Coldfire */ +#define EM_68HC12 53 /* Motorola M68HC12 */ +#define EM_MMA 54 /* Fujitsu MMA Multimedia Accelerator*/ +#define EM_PCP 55 /* Siemens PCP */ +#define EM_NCPU 56 /* Sony nCPU embeeded RISC */ +#define EM_NDR1 57 /* Denso NDR1 microprocessor */ +#define EM_STARCORE 58 /* Motorola Start*Core processor */ +#define EM_ME16 59 /* Toyota ME16 processor */ +#define EM_ST100 60 /* STMicroelectronic ST100 processor */ +#define EM_TINYJ 61 /* Advanced Logic Corp. Tinyj emb.fam*/ +#define EM_X86_64 62 /* AMD x86-64 architecture */ +#define EM_PDSP 63 /* Sony DSP Processor */ + +#define EM_FX66 66 /* Siemens FX66 microcontroller */ +#define EM_ST9PLUS 67 /* STMicroelectronics ST9+ 8/16 mc */ +#define EM_ST7 68 /* STmicroelectronics ST7 8 bit mc */ +#define EM_68HC16 69 /* Motorola MC68HC16 microcontroller */ +#define EM_68HC11 70 /* Motorola MC68HC11 microcontroller */ +#define EM_68HC08 71 /* Motorola MC68HC08 microcontroller */ +#define EM_68HC05 72 /* Motorola MC68HC05 microcontroller */ +#define EM_SVX 73 /* Silicon Graphics SVx */ +#define EM_ST19 74 /* STMicroelectronics ST19 8 bit mc */ +#define EM_VAX 75 /* Digital VAX */ +#define EM_CRIS 76 /* Axis Communications 32-bit embedded processor */ +#define EM_JAVELIN 77 /* Infineon Technologies 32-bit embedded processor */ +#define EM_FIREPATH 78 /* Element 14 64-bit DSP Processor */ +#define EM_ZSP 79 /* LSI Logic 16-bit DSP Processor */ +#define EM_MMIX 80 /* Donald Knuth's educational 64-bit processor */ +#define EM_HUANY 81 /* Harvard University machine-independent object files */ +#define EM_PRISM 82 /* SiTera Prism */ +#define EM_AVR 83 /* Atmel AVR 8-bit microcontroller */ +#define EM_FR30 84 /* Fujitsu FR30 */ +#define EM_D10V 85 /* Mitsubishi D10V */ +#define EM_D30V 86 /* Mitsubishi D30V */ +#define EM_V850 87 /* NEC v850 */ +#define EM_M32R 88 /* Mitsubishi M32R */ +#define EM_MN10300 89 /* Matsushita MN10300 */ +#define EM_MN10200 90 /* Matsushita MN10200 */ +#define EM_PJ 91 /* picoJava */ +#define EM_OPENRISC 92 /* OpenRISC 32-bit embedded processor */ +#define EM_ARC_A5 93 /* ARC Cores Tangent-A5 */ +#define EM_XTENSA 94 /* Tensilica Xtensa Architecture */ +#define EM_NUM 95 + +/* If it is necessary to assign new unofficial EM_* values, please + pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the + chances of collision with official or non-GNU unofficial values. */ + +#define EM_ALPHA 0x9026 + +/* Legal values for e_version (version). */ + +#define EV_NONE 0 /* Invalid ELF version */ +#define EV_CURRENT 1 /* Current version */ +#define EV_NUM 2 + +/* Section header. */ + +typedef struct +{ + Elf32_Word sh_name; /* Section name (string tbl index) */ + Elf32_Word sh_type; /* Section type */ + Elf32_Word sh_flags; /* Section flags */ + Elf32_Addr sh_addr; /* Section virtual addr at execution */ + Elf32_Off sh_offset; /* Section file offset */ + Elf32_Word sh_size; /* Section size in bytes */ + Elf32_Word sh_link; /* Link to another section */ + Elf32_Word sh_info; /* Additional section information */ + Elf32_Word sh_addralign; /* Section alignment */ + Elf32_Word sh_entsize; /* Entry size if section holds table */ +} Elf32_Shdr; + +typedef struct +{ + Elf64_Word sh_name; /* Section name (string tbl index) */ + Elf64_Word sh_type; /* Section type */ + Elf64_Xword sh_flags; /* Section flags */ + Elf64_Addr sh_addr; /* Section virtual addr at execution */ + Elf64_Off sh_offset; /* Section file offset */ + Elf64_Xword sh_size; /* Section size in bytes */ + Elf64_Word sh_link; /* Link to another section */ + Elf64_Word sh_info; /* Additional section information */ + Elf64_Xword sh_addralign; /* Section alignment */ + Elf64_Xword sh_entsize; /* Entry size if section holds table */ +} Elf64_Shdr; + +/* Special section indices. */ + +#define SHN_UNDEF 0 /* Undefined section */ +#define SHN_LORESERVE 0xff00 /* Start of reserved indices */ +#define SHN_LOPROC 0xff00 /* Start of processor-specific */ +#define SHN_BEFORE 0xff00 /* Order section before all others + (Solaris). */ +#define SHN_AFTER 0xff01 /* Order section after all others + (Solaris). */ +#define SHN_HIPROC 0xff1f /* End of processor-specific */ +#define SHN_LOOS 0xff20 /* Start of OS-specific */ +#define SHN_HIOS 0xff3f /* End of OS-specific */ +#define SHN_ABS 0xfff1 /* Associated symbol is absolute */ +#define SHN_COMMON 0xfff2 /* Associated symbol is common */ +#define SHN_XINDEX 0xffff /* Index is in extra table. */ +#define SHN_HIRESERVE 0xffff /* End of reserved indices */ + +/* Legal values for sh_type (section type). */ + +#define SHT_NULL 0 /* Section header table entry unused */ +#define SHT_PROGBITS 1 /* Program data */ +#define SHT_SYMTAB 2 /* Symbol table */ +#define SHT_STRTAB 3 /* String table */ +#define SHT_RELA 4 /* Relocation entries with addends */ +#define SHT_HASH 5 /* Symbol hash table */ +#define SHT_DYNAMIC 6 /* Dynamic linking information */ +#define SHT_NOTE 7 /* Notes */ +#define SHT_NOBITS 8 /* Program space with no data (bss) */ +#define SHT_REL 9 /* Relocation entries, no addends */ +#define SHT_SHLIB 10 /* Reserved */ +#define SHT_DYNSYM 11 /* Dynamic linker symbol table */ +#define SHT_INIT_ARRAY 14 /* Array of constructors */ +#define SHT_FINI_ARRAY 15 /* Array of destructors */ +#define SHT_PREINIT_ARRAY 16 /* Array of pre-constructors */ +#define SHT_GROUP 17 /* Section group */ +#define SHT_SYMTAB_SHNDX 18 /* Extended section indeces */ +#define SHT_NUM 19 /* Number of defined types. */ +#define SHT_LOOS 0x60000000 /* Start OS-specific. */ +#define SHT_GNU_HASH 0x6ffffff6 /* GNU-style hash table. */ +#define SHT_GNU_LIBLIST 0x6ffffff7 /* Prelink library list */ +#define SHT_CHECKSUM 0x6ffffff8 /* Checksum for DSO content. */ +#define SHT_LOSUNW 0x6ffffffa /* Sun-specific low bound. */ +#define SHT_SUNW_move 0x6ffffffa +#define SHT_SUNW_COMDAT 0x6ffffffb +#define SHT_SUNW_syminfo 0x6ffffffc +#define SHT_GNU_verdef 0x6ffffffd /* Version definition section. */ +#define SHT_GNU_verneed 0x6ffffffe /* Version needs section. */ +#define SHT_GNU_versym 0x6fffffff /* Version symbol table. */ +#define SHT_HISUNW 0x6fffffff /* Sun-specific high bound. */ +#define SHT_HIOS 0x6fffffff /* End OS-specific type */ +#define SHT_LOPROC 0x70000000 /* Start of processor-specific */ +#define SHT_HIPROC 0x7fffffff /* End of processor-specific */ +#define SHT_LOUSER 0x80000000 /* Start of application-specific */ +#define SHT_HIUSER 0x8fffffff /* End of application-specific */ + +/* Legal values for sh_flags (section flags). */ + +#define SHF_WRITE (1 << 0) /* Writable */ +#define SHF_ALLOC (1 << 1) /* Occupies memory during execution */ +#define SHF_EXECINSTR (1 << 2) /* Executable */ +#define SHF_MERGE (1 << 4) /* Might be merged */ +#define SHF_STRINGS (1 << 5) /* Contains nul-terminated strings */ +#define SHF_INFO_LINK (1 << 6) /* `sh_info' contains SHT index */ +#define SHF_LINK_ORDER (1 << 7) /* Preserve order after combining */ +#define SHF_OS_NONCONFORMING (1 << 8) /* Non-standard OS specific handling + required */ +#define SHF_GROUP (1 << 9) /* Section is member of a group. */ +#define SHF_TLS (1 << 10) /* Section hold thread-local data. */ +#define SHF_MASKOS 0x0ff00000 /* OS-specific. */ +#define SHF_MASKPROC 0xf0000000 /* Processor-specific */ +#define SHF_ORDERED (1 << 30) /* Special ordering requirement + (Solaris). */ +#define SHF_EXCLUDE (1 << 31) /* Section is excluded unless + referenced or allocated (Solaris).*/ + +/* Section group handling. */ +#define GRP_COMDAT 0x1 /* Mark group as COMDAT. */ + +/* Symbol table entry. */ + +typedef struct +{ + Elf32_Word st_name; /* Symbol name (string tbl index) */ + Elf32_Addr st_value; /* Symbol value */ + Elf32_Word st_size; /* Symbol size */ + unsigned char st_info; /* Symbol type and binding */ + unsigned char st_other; /* Symbol visibility */ + Elf32_Section st_shndx; /* Section index */ +} Elf32_Sym; + +typedef struct +{ + Elf64_Word st_name; /* Symbol name (string tbl index) */ + unsigned char st_info; /* Symbol type and binding */ + unsigned char st_other; /* Symbol visibility */ + Elf64_Section st_shndx; /* Section index */ + Elf64_Addr st_value; /* Symbol value */ + Elf64_Xword st_size; /* Symbol size */ +} Elf64_Sym; + +/* The syminfo section if available contains additional information about + every dynamic symbol. */ + +typedef struct +{ + Elf32_Half si_boundto; /* Direct bindings, symbol bound to */ + Elf32_Half si_flags; /* Per symbol flags */ +} Elf32_Syminfo; + +typedef struct +{ + Elf64_Half si_boundto; /* Direct bindings, symbol bound to */ + Elf64_Half si_flags; /* Per symbol flags */ +} Elf64_Syminfo; + +/* Possible values for si_boundto. */ +#define SYMINFO_BT_SELF 0xffff /* Symbol bound to self */ +#define SYMINFO_BT_PARENT 0xfffe /* Symbol bound to parent */ +#define SYMINFO_BT_LOWRESERVE 0xff00 /* Beginning of reserved entries */ + +/* Possible bitmasks for si_flags. */ +#define SYMINFO_FLG_DIRECT 0x0001 /* Direct bound symbol */ +#define SYMINFO_FLG_PASSTHRU 0x0002 /* Pass-thru symbol for translator */ +#define SYMINFO_FLG_COPY 0x0004 /* Symbol is a copy-reloc */ +#define SYMINFO_FLG_LAZYLOAD 0x0008 /* Symbol bound to object to be lazy + loaded */ +/* Syminfo version values. */ +#define SYMINFO_NONE 0 +#define SYMINFO_CURRENT 1 +#define SYMINFO_NUM 2 + + +/* How to extract and insert information held in the st_info field. */ + +#define ELF32_ST_BIND(val) (((unsigned char) (val)) >> 4) +#define ELF32_ST_TYPE(val) ((val) & 0xf) +#define ELF32_ST_INFO(bind, type) (((bind) << 4) + ((type) & 0xf)) + +/* Both Elf32_Sym and Elf64_Sym use the same one-byte st_info field. */ +#define ELF64_ST_BIND(val) ELF32_ST_BIND (val) +#define ELF64_ST_TYPE(val) ELF32_ST_TYPE (val) +#define ELF64_ST_INFO(bind, type) ELF32_ST_INFO ((bind), (type)) + +/* Legal values for ST_BIND subfield of st_info (symbol binding). */ + +#define STB_LOCAL 0 /* Local symbol */ +#define STB_GLOBAL 1 /* Global symbol */ +#define STB_WEAK 2 /* Weak symbol */ +#define STB_NUM 3 /* Number of defined types. */ +#define STB_LOOS 10 /* Start of OS-specific */ +#define STB_HIOS 12 /* End of OS-specific */ +#define STB_LOPROC 13 /* Start of processor-specific */ +#define STB_HIPROC 15 /* End of processor-specific */ + +/* Legal values for ST_TYPE subfield of st_info (symbol type). */ + +#define STT_NOTYPE 0 /* Symbol type is unspecified */ +#define STT_OBJECT 1 /* Symbol is a data object */ +#define STT_FUNC 2 /* Symbol is a code object */ +#define STT_SECTION 3 /* Symbol associated with a section */ +#define STT_FILE 4 /* Symbol's name is file name */ +#define STT_COMMON 5 /* Symbol is a common data object */ +#define STT_TLS 6 /* Symbol is thread-local data object*/ +#define STT_NUM 7 /* Number of defined types. */ +#define STT_LOOS 10 /* Start of OS-specific */ +#define STT_HIOS 12 /* End of OS-specific */ +#define STT_LOPROC 13 /* Start of processor-specific */ +#define STT_HIPROC 15 /* End of processor-specific */ + + +/* Symbol table indices are found in the hash buckets and chain table + of a symbol hash table section. This special index value indicates + the end of a chain, meaning no further symbols are found in that bucket. */ + +#define STN_UNDEF 0 /* End of a chain. */ + + +/* How to extract and insert information held in the st_other field. */ + +#define ELF32_ST_VISIBILITY(o) ((o) & 0x03) + +/* For ELF64 the definitions are the same. */ +#define ELF64_ST_VISIBILITY(o) ELF32_ST_VISIBILITY (o) + +/* Symbol visibility specification encoded in the st_other field. */ +#define STV_DEFAULT 0 /* Default symbol visibility rules */ +#define STV_INTERNAL 1 /* Processor specific hidden class */ +#define STV_HIDDEN 2 /* Sym unavailable in other modules */ +#define STV_PROTECTED 3 /* Not preemptible, not exported */ + + +/* Relocation table entry without addend (in section of type SHT_REL). */ + +typedef struct +{ + Elf32_Addr r_offset; /* Address */ + Elf32_Word r_info; /* Relocation type and symbol index */ +} Elf32_Rel; + +/* I have seen two different definitions of the Elf64_Rel and + Elf64_Rela structures, so we'll leave them out until Novell (or + whoever) gets their act together. */ +/* The following, at least, is used on Sparc v9, MIPS, and Alpha. */ + +typedef struct +{ + Elf64_Addr r_offset; /* Address */ + Elf64_Xword r_info; /* Relocation type and symbol index */ +} Elf64_Rel; + +/* Relocation table entry with addend (in section of type SHT_RELA). */ + +typedef struct +{ + Elf32_Addr r_offset; /* Address */ + Elf32_Word r_info; /* Relocation type and symbol index */ + Elf32_Sword r_addend; /* Addend */ +} Elf32_Rela; + +typedef struct +{ + Elf64_Addr r_offset; /* Address */ + Elf64_Xword r_info; /* Relocation type and symbol index */ + Elf64_Sxword r_addend; /* Addend */ +} Elf64_Rela; + +/* How to extract and insert information held in the r_info field. */ + +#define ELF32_R_SYM(val) ((val) >> 8) +#define ELF32_R_TYPE(val) ((val) & 0xff) +#define ELF32_R_INFO(sym, type) (((sym) << 8) + ((type) & 0xff)) + +#define ELF64_R_SYM(i) ((i) >> 32) +#define ELF64_R_TYPE(i) ((i) & 0xffffffff) +#define ELF64_R_INFO(sym,type) ((((Elf64_Xword) (sym)) << 32) + (type)) + +/* Program segment header. */ + +typedef struct +{ + Elf32_Word p_type; /* Segment type */ + Elf32_Off p_offset; /* Segment file offset */ + Elf32_Addr p_vaddr; /* Segment virtual address */ + Elf32_Addr p_paddr; /* Segment physical address */ + Elf32_Word p_filesz; /* Segment size in file */ + Elf32_Word p_memsz; /* Segment size in memory */ + Elf32_Word p_flags; /* Segment flags */ + Elf32_Word p_align; /* Segment alignment */ +} Elf32_Phdr; + +typedef struct +{ + Elf64_Word p_type; /* Segment type */ + Elf64_Word p_flags; /* Segment flags */ + Elf64_Off p_offset; /* Segment file offset */ + Elf64_Addr p_vaddr; /* Segment virtual address */ + Elf64_Addr p_paddr; /* Segment physical address */ + Elf64_Xword p_filesz; /* Segment size in file */ + Elf64_Xword p_memsz; /* Segment size in memory */ + Elf64_Xword p_align; /* Segment alignment */ +} Elf64_Phdr; + +/* Legal values for p_type (segment type). */ + +#define PT_NULL 0 /* Program header table entry unused */ +#define PT_LOAD 1 /* Loadable program segment */ +#define PT_DYNAMIC 2 /* Dynamic linking information */ +#define PT_INTERP 3 /* Program interpreter */ +#define PT_NOTE 4 /* Auxiliary information */ +#define PT_SHLIB 5 /* Reserved */ +#define PT_PHDR 6 /* Entry for header table itself */ +#define PT_TLS 7 /* Thread-local storage segment */ +#define PT_NUM 8 /* Number of defined types */ +#define PT_LOOS 0x60000000 /* Start of OS-specific */ +#define PT_GNU_EH_FRAME 0x6474e550 /* GCC .eh_frame_hdr segment */ +#define PT_GNU_STACK 0x6474e551 /* Indicates stack executability */ +#define PT_GNU_RELRO 0x6474e552 /* Read-only after relocation */ +#define PT_LOSUNW 0x6ffffffa +#define PT_SUNWBSS 0x6ffffffa /* Sun Specific segment */ +#define PT_SUNWSTACK 0x6ffffffb /* Stack segment */ +#define PT_HISUNW 0x6fffffff +#define PT_HIOS 0x6fffffff /* End of OS-specific */ +#define PT_LOPROC 0x70000000 /* Start of processor-specific */ +#define PT_HIPROC 0x7fffffff /* End of processor-specific */ + +/* Legal values for p_flags (segment flags). */ + +#define PF_X (1 << 0) /* Segment is executable */ +#define PF_W (1 << 1) /* Segment is writable */ +#define PF_R (1 << 2) /* Segment is readable */ +#define PF_MASKOS 0x0ff00000 /* OS-specific */ +#define PF_MASKPROC 0xf0000000 /* Processor-specific */ + +/* Legal values for note segment descriptor types for core files. */ + +#define NT_PRSTATUS 1 /* Contains copy of prstatus struct */ +#define NT_FPREGSET 2 /* Contains copy of fpregset struct */ +#define NT_PRPSINFO 3 /* Contains copy of prpsinfo struct */ +#define NT_PRXREG 4 /* Contains copy of prxregset struct */ +#define NT_TASKSTRUCT 4 /* Contains copy of task structure */ +#define NT_PLATFORM 5 /* String from sysinfo(SI_PLATFORM) */ +#define NT_AUXV 6 /* Contains copy of auxv array */ +#define NT_GWINDOWS 7 /* Contains copy of gwindows struct */ +#define NT_ASRS 8 /* Contains copy of asrset struct */ +#define NT_PSTATUS 10 /* Contains copy of pstatus struct */ +#define NT_PSINFO 13 /* Contains copy of psinfo struct */ +#define NT_PRCRED 14 /* Contains copy of prcred struct */ +#define NT_UTSNAME 15 /* Contains copy of utsname struct */ +#define NT_LWPSTATUS 16 /* Contains copy of lwpstatus struct */ +#define NT_LWPSINFO 17 /* Contains copy of lwpinfo struct */ +#define NT_PRFPXREG 20 /* Contains copy of fprxregset struct */ +#define NT_PRXFPREG 0x46e62b7f /* Contains copy of user_fxsr_struct */ + +/* Legal values for the note segment descriptor types for object files. */ + +#define NT_VERSION 1 /* Contains a version string. */ + + +/* Dynamic section entry. */ + +typedef struct +{ + Elf32_Sword d_tag; /* Dynamic entry type */ + union + { + Elf32_Word d_val; /* Integer value */ + Elf32_Addr d_ptr; /* Address value */ + } d_un; +} Elf32_Dyn; + +typedef struct +{ + Elf64_Sxword d_tag; /* Dynamic entry type */ + union + { + Elf64_Xword d_val; /* Integer value */ + Elf64_Addr d_ptr; /* Address value */ + } d_un; +} Elf64_Dyn; + +/* Legal values for d_tag (dynamic entry type). */ + +#define DT_NULL 0 /* Marks end of dynamic section */ +#define DT_NEEDED 1 /* Name of needed library */ +#define DT_PLTRELSZ 2 /* Size in bytes of PLT relocs */ +#define DT_PLTGOT 3 /* Processor defined value */ +#define DT_HASH 4 /* Address of symbol hash table */ +#define DT_STRTAB 5 /* Address of string table */ +#define DT_SYMTAB 6 /* Address of symbol table */ +#define DT_RELA 7 /* Address of Rela relocs */ +#define DT_RELASZ 8 /* Total size of Rela relocs */ +#define DT_RELAENT 9 /* Size of one Rela reloc */ +#define DT_STRSZ 10 /* Size of string table */ +#define DT_SYMENT 11 /* Size of one symbol table entry */ +#define DT_INIT 12 /* Address of init function */ +#define DT_FINI 13 /* Address of termination function */ +#define DT_SONAME 14 /* Name of shared object */ +#define DT_RPATH 15 /* Library search path (deprecated) */ +#define DT_SYMBOLIC 16 /* Start symbol search here */ +#define DT_REL 17 /* Address of Rel relocs */ +#define DT_RELSZ 18 /* Total size of Rel relocs */ +#define DT_RELENT 19 /* Size of one Rel reloc */ +#define DT_PLTREL 20 /* Type of reloc in PLT */ +#define DT_DEBUG 21 /* For debugging; unspecified */ +#define DT_TEXTREL 22 /* Reloc might modify .text */ +#define DT_JMPREL 23 /* Address of PLT relocs */ +#define DT_BIND_NOW 24 /* Process relocations of object */ +#define DT_INIT_ARRAY 25 /* Array with addresses of init fct */ +#define DT_FINI_ARRAY 26 /* Array with addresses of fini fct */ +#define DT_INIT_ARRAYSZ 27 /* Size in bytes of DT_INIT_ARRAY */ +#define DT_FINI_ARRAYSZ 28 /* Size in bytes of DT_FINI_ARRAY */ +#define DT_RUNPATH 29 /* Library search path */ +#define DT_FLAGS 30 /* Flags for the object being loaded */ +#define DT_ENCODING 32 /* Start of encoded range */ +#define DT_PREINIT_ARRAY 32 /* Array with addresses of preinit fct*/ +#define DT_PREINIT_ARRAYSZ 33 /* size in bytes of DT_PREINIT_ARRAY */ +#define DT_NUM 34 /* Number used */ +#define DT_LOOS 0x6000000d /* Start of OS-specific */ +#define DT_HIOS 0x6ffff000 /* End of OS-specific */ +#define DT_LOPROC 0x70000000 /* Start of processor-specific */ +#define DT_HIPROC 0x7fffffff /* End of processor-specific */ +#define DT_PROCNUM DT_MIPS_NUM /* Most used by any processor */ + +/* DT_* entries which fall between DT_VALRNGHI & DT_VALRNGLO use the + Dyn.d_un.d_val field of the Elf*_Dyn structure. This follows Sun's + approach. */ +#define DT_VALRNGLO 0x6ffffd00 +#define DT_GNU_PRELINKED 0x6ffffdf5 /* Prelinking timestamp */ +#define DT_GNU_CONFLICTSZ 0x6ffffdf6 /* Size of conflict section */ +#define DT_GNU_LIBLISTSZ 0x6ffffdf7 /* Size of library list */ +#define DT_CHECKSUM 0x6ffffdf8 +#define DT_PLTPADSZ 0x6ffffdf9 +#define DT_MOVEENT 0x6ffffdfa +#define DT_MOVESZ 0x6ffffdfb +#define DT_FEATURE_1 0x6ffffdfc /* Feature selection (DTF_*). */ +#define DT_POSFLAG_1 0x6ffffdfd /* Flags for DT_* entries, effecting + the following DT_* entry. */ +#define DT_SYMINSZ 0x6ffffdfe /* Size of syminfo table (in bytes) */ +#define DT_SYMINENT 0x6ffffdff /* Entry size of syminfo */ +#define DT_VALRNGHI 0x6ffffdff +#define DT_VALTAGIDX(tag) (DT_VALRNGHI - (tag)) /* Reverse order! */ +#define DT_VALNUM 12 + +/* DT_* entries which fall between DT_ADDRRNGHI & DT_ADDRRNGLO use the + Dyn.d_un.d_ptr field of the Elf*_Dyn structure. + + If any adjustment is made to the ELF object after it has been + built these entries will need to be adjusted. */ +#define DT_ADDRRNGLO 0x6ffffe00 +#define DT_GNU_HASH 0x6ffffef5 /* GNU-style hash table. */ +#define DT_TLSDESC_PLT 0x6ffffef6 +#define DT_TLSDESC_GOT 0x6ffffef7 +#define DT_GNU_CONFLICT 0x6ffffef8 /* Start of conflict section */ +#define DT_GNU_LIBLIST 0x6ffffef9 /* Library list */ +#define DT_CONFIG 0x6ffffefa /* Configuration information. */ +#define DT_DEPAUDIT 0x6ffffefb /* Dependency auditing. */ +#define DT_AUDIT 0x6ffffefc /* Object auditing. */ +#define DT_PLTPAD 0x6ffffefd /* PLT padding. */ +#define DT_MOVETAB 0x6ffffefe /* Move table. */ +#define DT_SYMINFO 0x6ffffeff /* Syminfo table. */ +#define DT_ADDRRNGHI 0x6ffffeff +#define DT_ADDRTAGIDX(tag) (DT_ADDRRNGHI - (tag)) /* Reverse order! */ +#define DT_ADDRNUM 11 + +/* The versioning entry types. The next are defined as part of the + GNU extension. */ +#define DT_VERSYM 0x6ffffff0 + +#define DT_RELACOUNT 0x6ffffff9 +#define DT_RELCOUNT 0x6ffffffa + +/* These were chosen by Sun. */ +#define DT_FLAGS_1 0x6ffffffb /* State flags, see DF_1_* below. */ +#define DT_VERDEF 0x6ffffffc /* Address of version definition + table */ +#define DT_VERDEFNUM 0x6ffffffd /* Number of version definitions */ +#define DT_VERNEED 0x6ffffffe /* Address of table with needed + versions */ +#define DT_VERNEEDNUM 0x6fffffff /* Number of needed versions */ +#define DT_VERSIONTAGIDX(tag) (DT_VERNEEDNUM - (tag)) /* Reverse order! */ +#define DT_VERSIONTAGNUM 16 + +/* Sun added these machine-independent extensions in the "processor-specific" + range. Be compatible. */ +#define DT_AUXILIARY 0x7ffffffd /* Shared object to load before self */ +#define DT_FILTER 0x7fffffff /* Shared object to get values from */ +#define DT_EXTRATAGIDX(tag) ((Elf32_Word)-((Elf32_Sword) (tag) <<1>>1)-1) +#define DT_EXTRANUM 3 + +/* Values of `d_un.d_val' in the DT_FLAGS entry. */ +#define DF_ORIGIN 0x00000001 /* Object may use DF_ORIGIN */ +#define DF_SYMBOLIC 0x00000002 /* Symbol resolutions starts here */ +#define DF_TEXTREL 0x00000004 /* Object contains text relocations */ +#define DF_BIND_NOW 0x00000008 /* No lazy binding for this object */ +#define DF_STATIC_TLS 0x00000010 /* Module uses the static TLS model */ + +/* State flags selectable in the `d_un.d_val' element of the DT_FLAGS_1 + entry in the dynamic section. */ +#define DF_1_NOW 0x00000001 /* Set RTLD_NOW for this object. */ +#define DF_1_GLOBAL 0x00000002 /* Set RTLD_GLOBAL for this object. */ +#define DF_1_GROUP 0x00000004 /* Set RTLD_GROUP for this object. */ +#define DF_1_NODELETE 0x00000008 /* Set RTLD_NODELETE for this object.*/ +#define DF_1_LOADFLTR 0x00000010 /* Trigger filtee loading at runtime.*/ +#define DF_1_INITFIRST 0x00000020 /* Set RTLD_INITFIRST for this object*/ +#define DF_1_NOOPEN 0x00000040 /* Set RTLD_NOOPEN for this object. */ +#define DF_1_ORIGIN 0x00000080 /* $ORIGIN must be handled. */ +#define DF_1_DIRECT 0x00000100 /* Direct binding enabled. */ +#define DF_1_TRANS 0x00000200 +#define DF_1_INTERPOSE 0x00000400 /* Object is used to interpose. */ +#define DF_1_NODEFLIB 0x00000800 /* Ignore default lib search path. */ +#define DF_1_NODUMP 0x00001000 /* Object can't be dldump'ed. */ +#define DF_1_CONFALT 0x00002000 /* Configuration alternative created.*/ +#define DF_1_ENDFILTEE 0x00004000 /* Filtee terminates filters search. */ +#define DF_1_DISPRELDNE 0x00008000 /* Disp reloc applied at build time. */ +#define DF_1_DISPRELPND 0x00010000 /* Disp reloc applied at run-time. */ + +/* Flags for the feature selection in DT_FEATURE_1. */ +#define DTF_1_PARINIT 0x00000001 +#define DTF_1_CONFEXP 0x00000002 + +/* Flags in the DT_POSFLAG_1 entry effecting only the next DT_* entry. */ +#define DF_P1_LAZYLOAD 0x00000001 /* Lazyload following object. */ +#define DF_P1_GROUPPERM 0x00000002 /* Symbols from next object are not + generally available. */ + +/* Version definition sections. */ + +typedef struct +{ + Elf32_Half vd_version; /* Version revision */ + Elf32_Half vd_flags; /* Version information */ + Elf32_Half vd_ndx; /* Version Index */ + Elf32_Half vd_cnt; /* Number of associated aux entries */ + Elf32_Word vd_hash; /* Version name hash value */ + Elf32_Word vd_aux; /* Offset in bytes to verdaux array */ + Elf32_Word vd_next; /* Offset in bytes to next verdef + entry */ +} Elf32_Verdef; + +typedef struct +{ + Elf64_Half vd_version; /* Version revision */ + Elf64_Half vd_flags; /* Version information */ + Elf64_Half vd_ndx; /* Version Index */ + Elf64_Half vd_cnt; /* Number of associated aux entries */ + Elf64_Word vd_hash; /* Version name hash value */ + Elf64_Word vd_aux; /* Offset in bytes to verdaux array */ + Elf64_Word vd_next; /* Offset in bytes to next verdef + entry */ +} Elf64_Verdef; + + +/* Legal values for vd_version (version revision). */ +#define VER_DEF_NONE 0 /* No version */ +#define VER_DEF_CURRENT 1 /* Current version */ +#define VER_DEF_NUM 2 /* Given version number */ + +/* Legal values for vd_flags (version information flags). */ +#define VER_FLG_BASE 0x1 /* Version definition of file itself */ +#define VER_FLG_WEAK 0x2 /* Weak version identifier */ + +/* Versym symbol index values. */ +#define VER_NDX_LOCAL 0 /* Symbol is local. */ +#define VER_NDX_GLOBAL 1 /* Symbol is global. */ +#define VER_NDX_LORESERVE 0xff00 /* Beginning of reserved entries. */ +#define VER_NDX_ELIMINATE 0xff01 /* Symbol is to be eliminated. */ + +/* Auxialiary version information. */ + +typedef struct +{ + Elf32_Word vda_name; /* Version or dependency names */ + Elf32_Word vda_next; /* Offset in bytes to next verdaux + entry */ +} Elf32_Verdaux; + +typedef struct +{ + Elf64_Word vda_name; /* Version or dependency names */ + Elf64_Word vda_next; /* Offset in bytes to next verdaux + entry */ +} Elf64_Verdaux; + + +/* Version dependency section. */ + +typedef struct +{ + Elf32_Half vn_version; /* Version of structure */ + Elf32_Half vn_cnt; /* Number of associated aux entries */ + Elf32_Word vn_file; /* Offset of filename for this + dependency */ + Elf32_Word vn_aux; /* Offset in bytes to vernaux array */ + Elf32_Word vn_next; /* Offset in bytes to next verneed + entry */ +} Elf32_Verneed; + +typedef struct +{ + Elf64_Half vn_version; /* Version of structure */ + Elf64_Half vn_cnt; /* Number of associated aux entries */ + Elf64_Word vn_file; /* Offset of filename for this + dependency */ + Elf64_Word vn_aux; /* Offset in bytes to vernaux array */ + Elf64_Word vn_next; /* Offset in bytes to next verneed + entry */ +} Elf64_Verneed; + + +/* Legal values for vn_version (version revision). */ +#define VER_NEED_NONE 0 /* No version */ +#define VER_NEED_CURRENT 1 /* Current version */ +#define VER_NEED_NUM 2 /* Given version number */ + +/* Auxiliary needed version information. */ + +typedef struct +{ + Elf32_Word vna_hash; /* Hash value of dependency name */ + Elf32_Half vna_flags; /* Dependency specific information */ + Elf32_Half vna_other; /* Unused */ + Elf32_Word vna_name; /* Dependency name string offset */ + Elf32_Word vna_next; /* Offset in bytes to next vernaux + entry */ +} Elf32_Vernaux; + +typedef struct +{ + Elf64_Word vna_hash; /* Hash value of dependency name */ + Elf64_Half vna_flags; /* Dependency specific information */ + Elf64_Half vna_other; /* Unused */ + Elf64_Word vna_name; /* Dependency name string offset */ + Elf64_Word vna_next; /* Offset in bytes to next vernaux + entry */ +} Elf64_Vernaux; + + +/* Legal values for vna_flags. */ +#define VER_FLG_WEAK 0x2 /* Weak version identifier */ + + +/* Auxiliary vector. */ + +/* This vector is normally only used by the program interpreter. The + usual definition in an ABI supplement uses the name auxv_t. The + vector is not usually defined in a standard file, but it + can't hurt. We rename it to avoid conflicts. The sizes of these + types are an arrangement between the exec server and the program + interpreter, so we don't fully specify them here. */ + +typedef struct +{ + unsigned int a_type; /* Entry type */ + union + { + unsigned int a_val; /* Integer value */ + /* We use to have pointer elements added here. We cannot do that, + though, since it does not work when using 32-bit definitions + on 64-bit platforms and vice versa. */ + } a_un; +} Elf32_auxv_t; + +typedef struct +{ + unsigned long a_type; /* Entry type */ + union + { + unsigned long a_val; /* Integer value */ + /* We use to have pointer elements added here. We cannot do that, + though, since it does not work when using 32-bit definitions + on 64-bit platforms and vice versa. */ + } a_un; +} Elf64_auxv_t; + +/* Legal values for a_type (entry type). */ + +#define AT_NULL 0 /* End of vector */ +#define AT_IGNORE 1 /* Entry should be ignored */ +#define AT_EXECFD 2 /* File descriptor of program */ +#define AT_PHDR 3 /* Program headers for program */ +#define AT_PHENT 4 /* Size of program header entry */ +#define AT_PHNUM 5 /* Number of program headers */ +#define AT_PAGESZ 6 /* System page size */ +#define AT_BASE 7 /* Base address of interpreter */ +#define AT_FLAGS 8 /* Flags */ +#define AT_ENTRY 9 /* Entry point of program */ +#define AT_NOTELF 10 /* Program is not ELF */ +#define AT_UID 11 /* Real uid */ +#define AT_EUID 12 /* Effective uid */ +#define AT_GID 13 /* Real gid */ +#define AT_EGID 14 /* Effective gid */ +#define AT_CLKTCK 17 /* Frequency of times() */ + +/* Some more special a_type values describing the hardware. */ +#define AT_PLATFORM 15 /* String identifying platform. */ +#define AT_HWCAP 16 /* Machine dependent hints about + processor capabilities. */ + +/* This entry gives some information about the FPU initialization + performed by the kernel. */ +#define AT_FPUCW 18 /* Used FPU control word. */ + +/* Cache block sizes. */ +#define AT_DCACHEBSIZE 19 /* Data cache block size. */ +#define AT_ICACHEBSIZE 20 /* Instruction cache block size. */ +#define AT_UCACHEBSIZE 21 /* Unified cache block size. */ + +/* A special ignored value for PPC, used by the kernel to control the + interpretation of the AUXV. Must be > 16. */ +#define AT_IGNOREPPC 22 /* Entry should be ignored. */ + +#define AT_SECURE 23 /* Boolean, was exec setuid-like? */ + +/* Pointer to the global system page used for system calls and other + nice things. */ +#define AT_SYSINFO 32 +#define AT_SYSINFO_EHDR 33 + +/* Shapes of the caches. Bits 0-3 contains associativity; bits 4-7 contains + log2 of line size; mask those to get cache size. */ +#define AT_L1I_CACHESHAPE 34 +#define AT_L1D_CACHESHAPE 35 +#define AT_L2_CACHESHAPE 36 +#define AT_L3_CACHESHAPE 37 + +/* Note section contents. Each entry in the note section begins with + a header of a fixed form. */ + +typedef struct +{ + Elf32_Word n_namesz; /* Length of the note's name. */ + Elf32_Word n_descsz; /* Length of the note's descriptor. */ + Elf32_Word n_type; /* Type of the note. */ +} Elf32_Nhdr; + +typedef struct +{ + Elf64_Word n_namesz; /* Length of the note's name. */ + Elf64_Word n_descsz; /* Length of the note's descriptor. */ + Elf64_Word n_type; /* Type of the note. */ +} Elf64_Nhdr; + +/* Known names of notes. */ + +/* Solaris entries in the note section have this name. */ +#define ELF_NOTE_SOLARIS "SUNW Solaris" + +/* Note entries for GNU systems have this name. */ +#define ELF_NOTE_GNU "GNU" + + +/* Defined types of notes for Solaris. */ + +/* Value of descriptor (one word) is desired pagesize for the binary. */ +#define ELF_NOTE_PAGESIZE_HINT 1 + + +/* Defined note types for GNU systems. */ + +/* ABI information. The descriptor consists of words: + word 0: OS descriptor + word 1: major version of the ABI + word 2: minor version of the ABI + word 3: subminor version of the ABI +*/ +#define NT_GNU_ABI_TAG 1 +#define ELF_NOTE_ABI NT_GNU_ABI_TAG /* Old name. */ + +/* Known OSes. These values can appear in word 0 of an + NT_GNU_ABI_TAG note section entry. */ +#define ELF_NOTE_OS_LINUX 0 +#define ELF_NOTE_OS_GNU 1 +#define ELF_NOTE_OS_SOLARIS2 2 +#define ELF_NOTE_OS_FREEBSD 3 + +/* Synthetic hwcap information. The descriptor begins with two words: + word 0: number of entries + word 1: bitmask of enabled entries + Then follow variable-length entries, one byte followed by a + '\0'-terminated hwcap name string. The byte gives the bit + number to test if enabled, (1U << bit) & bitmask. */ +#define NT_GNU_HWCAP 2 + +/* Build ID bits as generated by ld --build-id. + The descriptor consists of any nonzero number of bytes. */ +#define NT_GNU_BUILD_ID 3 + + +/* Move records. */ +typedef struct +{ + Elf32_Xword m_value; /* Symbol value. */ + Elf32_Word m_info; /* Size and index. */ + Elf32_Word m_poffset; /* Symbol offset. */ + Elf32_Half m_repeat; /* Repeat count. */ + Elf32_Half m_stride; /* Stride info. */ +} Elf32_Move; + +typedef struct +{ + Elf64_Xword m_value; /* Symbol value. */ + Elf64_Xword m_info; /* Size and index. */ + Elf64_Xword m_poffset; /* Symbol offset. */ + Elf64_Half m_repeat; /* Repeat count. */ + Elf64_Half m_stride; /* Stride info. */ +} Elf64_Move; + +/* Macro to construct move records. */ +#define ELF32_M_SYM(info) ((info) >> 8) +#define ELF32_M_SIZE(info) ((unsigned char) (info)) +#define ELF32_M_INFO(sym, size) (((sym) << 8) + (unsigned char) (size)) + +#define ELF64_M_SYM(info) ELF32_M_SYM (info) +#define ELF64_M_SIZE(info) ELF32_M_SIZE (info) +#define ELF64_M_INFO(sym, size) ELF32_M_INFO (sym, size) + + +/* Motorola 68k specific definitions. */ + +/* Values for Elf32_Ehdr.e_flags. */ +#define EF_CPU32 0x00810000 + +/* m68k relocs. */ + +#define R_68K_NONE 0 /* No reloc */ +#define R_68K_32 1 /* Direct 32 bit */ +#define R_68K_16 2 /* Direct 16 bit */ +#define R_68K_8 3 /* Direct 8 bit */ +#define R_68K_PC32 4 /* PC relative 32 bit */ +#define R_68K_PC16 5 /* PC relative 16 bit */ +#define R_68K_PC8 6 /* PC relative 8 bit */ +#define R_68K_GOT32 7 /* 32 bit PC relative GOT entry */ +#define R_68K_GOT16 8 /* 16 bit PC relative GOT entry */ +#define R_68K_GOT8 9 /* 8 bit PC relative GOT entry */ +#define R_68K_GOT32O 10 /* 32 bit GOT offset */ +#define R_68K_GOT16O 11 /* 16 bit GOT offset */ +#define R_68K_GOT8O 12 /* 8 bit GOT offset */ +#define R_68K_PLT32 13 /* 32 bit PC relative PLT address */ +#define R_68K_PLT16 14 /* 16 bit PC relative PLT address */ +#define R_68K_PLT8 15 /* 8 bit PC relative PLT address */ +#define R_68K_PLT32O 16 /* 32 bit PLT offset */ +#define R_68K_PLT16O 17 /* 16 bit PLT offset */ +#define R_68K_PLT8O 18 /* 8 bit PLT offset */ +#define R_68K_COPY 19 /* Copy symbol at runtime */ +#define R_68K_GLOB_DAT 20 /* Create GOT entry */ +#define R_68K_JMP_SLOT 21 /* Create PLT entry */ +#define R_68K_RELATIVE 22 /* Adjust by program base */ +/* Keep this the last entry. */ +#define R_68K_NUM 23 + +/* Intel 80386 specific definitions. */ + +/* i386 relocs. */ + +#define R_386_NONE 0 /* No reloc */ +#define R_386_32 1 /* Direct 32 bit */ +#define R_386_PC32 2 /* PC relative 32 bit */ +#define R_386_GOT32 3 /* 32 bit GOT entry */ +#define R_386_PLT32 4 /* 32 bit PLT address */ +#define R_386_COPY 5 /* Copy symbol at runtime */ +#define R_386_GLOB_DAT 6 /* Create GOT entry */ +#define R_386_JMP_SLOT 7 /* Create PLT entry */ +#define R_386_RELATIVE 8 /* Adjust by program base */ +#define R_386_GOTOFF 9 /* 32 bit offset to GOT */ +#define R_386_GOTPC 10 /* 32 bit PC relative offset to GOT */ +#define R_386_32PLT 11 +#define R_386_TLS_TPOFF 14 /* Offset in static TLS block */ +#define R_386_TLS_IE 15 /* Address of GOT entry for static TLS + block offset */ +#define R_386_TLS_GOTIE 16 /* GOT entry for static TLS block + offset */ +#define R_386_TLS_LE 17 /* Offset relative to static TLS + block */ +#define R_386_TLS_GD 18 /* Direct 32 bit for GNU version of + general dynamic thread local data */ +#define R_386_TLS_LDM 19 /* Direct 32 bit for GNU version of + local dynamic thread local data + in LE code */ +#define R_386_16 20 +#define R_386_PC16 21 +#define R_386_8 22 +#define R_386_PC8 23 +#define R_386_TLS_GD_32 24 /* Direct 32 bit for general dynamic + thread local data */ +#define R_386_TLS_GD_PUSH 25 /* Tag for pushl in GD TLS code */ +#define R_386_TLS_GD_CALL 26 /* Relocation for call to + __tls_get_addr() */ +#define R_386_TLS_GD_POP 27 /* Tag for popl in GD TLS code */ +#define R_386_TLS_LDM_32 28 /* Direct 32 bit for local dynamic + thread local data in LE code */ +#define R_386_TLS_LDM_PUSH 29 /* Tag for pushl in LDM TLS code */ +#define R_386_TLS_LDM_CALL 30 /* Relocation for call to + __tls_get_addr() in LDM code */ +#define R_386_TLS_LDM_POP 31 /* Tag for popl in LDM TLS code */ +#define R_386_TLS_LDO_32 32 /* Offset relative to TLS block */ +#define R_386_TLS_IE_32 33 /* GOT entry for negated static TLS + block offset */ +#define R_386_TLS_LE_32 34 /* Negated offset relative to static + TLS block */ +#define R_386_TLS_DTPMOD32 35 /* ID of module containing symbol */ +#define R_386_TLS_DTPOFF32 36 /* Offset in TLS block */ +#define R_386_TLS_TPOFF32 37 /* Negated offset in static TLS block */ +/* Keep this the last entry. */ +#define R_386_NUM 38 + +/* SUN SPARC specific definitions. */ + +/* Legal values for ST_TYPE subfield of st_info (symbol type). */ + +#define STT_SPARC_REGISTER 13 /* Global register reserved to app. */ + +/* Values for Elf64_Ehdr.e_flags. */ + +#define EF_SPARCV9_MM 3 +#define EF_SPARCV9_TSO 0 +#define EF_SPARCV9_PSO 1 +#define EF_SPARCV9_RMO 2 +#define EF_SPARC_LEDATA 0x800000 /* little endian data */ +#define EF_SPARC_EXT_MASK 0xFFFF00 +#define EF_SPARC_32PLUS 0x000100 /* generic V8+ features */ +#define EF_SPARC_SUN_US1 0x000200 /* Sun UltraSPARC1 extensions */ +#define EF_SPARC_HAL_R1 0x000400 /* HAL R1 extensions */ +#define EF_SPARC_SUN_US3 0x000800 /* Sun UltraSPARCIII extensions */ + +/* SPARC relocs. */ + +#define R_SPARC_NONE 0 /* No reloc */ +#define R_SPARC_8 1 /* Direct 8 bit */ +#define R_SPARC_16 2 /* Direct 16 bit */ +#define R_SPARC_32 3 /* Direct 32 bit */ +#define R_SPARC_DISP8 4 /* PC relative 8 bit */ +#define R_SPARC_DISP16 5 /* PC relative 16 bit */ +#define R_SPARC_DISP32 6 /* PC relative 32 bit */ +#define R_SPARC_WDISP30 7 /* PC relative 30 bit shifted */ +#define R_SPARC_WDISP22 8 /* PC relative 22 bit shifted */ +#define R_SPARC_HI22 9 /* High 22 bit */ +#define R_SPARC_22 10 /* Direct 22 bit */ +#define R_SPARC_13 11 /* Direct 13 bit */ +#define R_SPARC_LO10 12 /* Truncated 10 bit */ +#define R_SPARC_GOT10 13 /* Truncated 10 bit GOT entry */ +#define R_SPARC_GOT13 14 /* 13 bit GOT entry */ +#define R_SPARC_GOT22 15 /* 22 bit GOT entry shifted */ +#define R_SPARC_PC10 16 /* PC relative 10 bit truncated */ +#define R_SPARC_PC22 17 /* PC relative 22 bit shifted */ +#define R_SPARC_WPLT30 18 /* 30 bit PC relative PLT address */ +#define R_SPARC_COPY 19 /* Copy symbol at runtime */ +#define R_SPARC_GLOB_DAT 20 /* Create GOT entry */ +#define R_SPARC_JMP_SLOT 21 /* Create PLT entry */ +#define R_SPARC_RELATIVE 22 /* Adjust by program base */ +#define R_SPARC_UA32 23 /* Direct 32 bit unaligned */ + +/* Additional Sparc64 relocs. */ + +#define R_SPARC_PLT32 24 /* Direct 32 bit ref to PLT entry */ +#define R_SPARC_HIPLT22 25 /* High 22 bit PLT entry */ +#define R_SPARC_LOPLT10 26 /* Truncated 10 bit PLT entry */ +#define R_SPARC_PCPLT32 27 /* PC rel 32 bit ref to PLT entry */ +#define R_SPARC_PCPLT22 28 /* PC rel high 22 bit PLT entry */ +#define R_SPARC_PCPLT10 29 /* PC rel trunc 10 bit PLT entry */ +#define R_SPARC_10 30 /* Direct 10 bit */ +#define R_SPARC_11 31 /* Direct 11 bit */ +#define R_SPARC_64 32 /* Direct 64 bit */ +#define R_SPARC_OLO10 33 /* 10bit with secondary 13bit addend */ +#define R_SPARC_HH22 34 /* Top 22 bits of direct 64 bit */ +#define R_SPARC_HM10 35 /* High middle 10 bits of ... */ +#define R_SPARC_LM22 36 /* Low middle 22 bits of ... */ +#define R_SPARC_PC_HH22 37 /* Top 22 bits of pc rel 64 bit */ +#define R_SPARC_PC_HM10 38 /* High middle 10 bit of ... */ +#define R_SPARC_PC_LM22 39 /* Low miggle 22 bits of ... */ +#define R_SPARC_WDISP16 40 /* PC relative 16 bit shifted */ +#define R_SPARC_WDISP19 41 /* PC relative 19 bit shifted */ +#define R_SPARC_7 43 /* Direct 7 bit */ +#define R_SPARC_5 44 /* Direct 5 bit */ +#define R_SPARC_6 45 /* Direct 6 bit */ +#define R_SPARC_DISP64 46 /* PC relative 64 bit */ +#define R_SPARC_PLT64 47 /* Direct 64 bit ref to PLT entry */ +#define R_SPARC_HIX22 48 /* High 22 bit complemented */ +#define R_SPARC_LOX10 49 /* Truncated 11 bit complemented */ +#define R_SPARC_H44 50 /* Direct high 12 of 44 bit */ +#define R_SPARC_M44 51 /* Direct mid 22 of 44 bit */ +#define R_SPARC_L44 52 /* Direct low 10 of 44 bit */ +#define R_SPARC_REGISTER 53 /* Global register usage */ +#define R_SPARC_UA64 54 /* Direct 64 bit unaligned */ +#define R_SPARC_UA16 55 /* Direct 16 bit unaligned */ +#define R_SPARC_TLS_GD_HI22 56 +#define R_SPARC_TLS_GD_LO10 57 +#define R_SPARC_TLS_GD_ADD 58 +#define R_SPARC_TLS_GD_CALL 59 +#define R_SPARC_TLS_LDM_HI22 60 +#define R_SPARC_TLS_LDM_LO10 61 +#define R_SPARC_TLS_LDM_ADD 62 +#define R_SPARC_TLS_LDM_CALL 63 +#define R_SPARC_TLS_LDO_HIX22 64 +#define R_SPARC_TLS_LDO_LOX10 65 +#define R_SPARC_TLS_LDO_ADD 66 +#define R_SPARC_TLS_IE_HI22 67 +#define R_SPARC_TLS_IE_LO10 68 +#define R_SPARC_TLS_IE_LD 69 +#define R_SPARC_TLS_IE_LDX 70 +#define R_SPARC_TLS_IE_ADD 71 +#define R_SPARC_TLS_LE_HIX22 72 +#define R_SPARC_TLS_LE_LOX10 73 +#define R_SPARC_TLS_DTPMOD32 74 +#define R_SPARC_TLS_DTPMOD64 75 +#define R_SPARC_TLS_DTPOFF32 76 +#define R_SPARC_TLS_DTPOFF64 77 +#define R_SPARC_TLS_TPOFF32 78 +#define R_SPARC_TLS_TPOFF64 79 +/* Keep this the last entry. */ +#define R_SPARC_NUM 80 + +/* For Sparc64, legal values for d_tag of Elf64_Dyn. */ + +#define DT_SPARC_REGISTER 0x70000001 +#define DT_SPARC_NUM 2 + +/* Bits present in AT_HWCAP on SPARC. */ + +#define HWCAP_SPARC_FLUSH 1 /* The CPU supports flush insn. */ +#define HWCAP_SPARC_STBAR 2 +#define HWCAP_SPARC_SWAP 4 +#define HWCAP_SPARC_MULDIV 8 +#define HWCAP_SPARC_V9 16 /* The CPU is v9, so v8plus is ok. */ +#define HWCAP_SPARC_ULTRA3 32 +#define HWCAP_SPARC_BLKINIT 64 /* Sun4v with block-init/load-twin. */ +#define HWCAP_SPARC_N2 128 + +/* MIPS R3000 specific definitions. */ + +/* Legal values for e_flags field of Elf32_Ehdr. */ + +#define EF_MIPS_NOREORDER 1 /* A .noreorder directive was used */ +#define EF_MIPS_PIC 2 /* Contains PIC code */ +#define EF_MIPS_CPIC 4 /* Uses PIC calling sequence */ +#define EF_MIPS_XGOT 8 +#define EF_MIPS_64BIT_WHIRL 16 +#define EF_MIPS_ABI2 32 +#define EF_MIPS_ABI_ON32 64 +#define EF_MIPS_ARCH 0xf0000000 /* MIPS architecture level */ + +/* Legal values for MIPS architecture level. */ + +#define EF_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ +#define EF_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ +#define EF_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ +#define EF_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ +#define EF_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ +#define EF_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ +#define EF_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ + +/* The following are non-official names and should not be used. */ + +#define E_MIPS_ARCH_1 0x00000000 /* -mips1 code. */ +#define E_MIPS_ARCH_2 0x10000000 /* -mips2 code. */ +#define E_MIPS_ARCH_3 0x20000000 /* -mips3 code. */ +#define E_MIPS_ARCH_4 0x30000000 /* -mips4 code. */ +#define E_MIPS_ARCH_5 0x40000000 /* -mips5 code. */ +#define E_MIPS_ARCH_32 0x60000000 /* MIPS32 code. */ +#define E_MIPS_ARCH_64 0x70000000 /* MIPS64 code. */ + +/* Special section indices. */ + +#define SHN_MIPS_ACOMMON 0xff00 /* Allocated common symbols */ +#define SHN_MIPS_TEXT 0xff01 /* Allocated test symbols. */ +#define SHN_MIPS_DATA 0xff02 /* Allocated data symbols. */ +#define SHN_MIPS_SCOMMON 0xff03 /* Small common symbols */ +#define SHN_MIPS_SUNDEFINED 0xff04 /* Small undefined symbols */ + +/* Legal values for sh_type field of Elf32_Shdr. */ + +#define SHT_MIPS_LIBLIST 0x70000000 /* Shared objects used in link */ +#define SHT_MIPS_MSYM 0x70000001 +#define SHT_MIPS_CONFLICT 0x70000002 /* Conflicting symbols */ +#define SHT_MIPS_GPTAB 0x70000003 /* Global data area sizes */ +#define SHT_MIPS_UCODE 0x70000004 /* Reserved for SGI/MIPS compilers */ +#define SHT_MIPS_DEBUG 0x70000005 /* MIPS ECOFF debugging information*/ +#define SHT_MIPS_REGINFO 0x70000006 /* Register usage information */ +#define SHT_MIPS_PACKAGE 0x70000007 +#define SHT_MIPS_PACKSYM 0x70000008 +#define SHT_MIPS_RELD 0x70000009 +#define SHT_MIPS_IFACE 0x7000000b +#define SHT_MIPS_CONTENT 0x7000000c +#define SHT_MIPS_OPTIONS 0x7000000d /* Miscellaneous options. */ +#define SHT_MIPS_SHDR 0x70000010 +#define SHT_MIPS_FDESC 0x70000011 +#define SHT_MIPS_EXTSYM 0x70000012 +#define SHT_MIPS_DENSE 0x70000013 +#define SHT_MIPS_PDESC 0x70000014 +#define SHT_MIPS_LOCSYM 0x70000015 +#define SHT_MIPS_AUXSYM 0x70000016 +#define SHT_MIPS_OPTSYM 0x70000017 +#define SHT_MIPS_LOCSTR 0x70000018 +#define SHT_MIPS_LINE 0x70000019 +#define SHT_MIPS_RFDESC 0x7000001a +#define SHT_MIPS_DELTASYM 0x7000001b +#define SHT_MIPS_DELTAINST 0x7000001c +#define SHT_MIPS_DELTACLASS 0x7000001d +#define SHT_MIPS_DWARF 0x7000001e /* DWARF debugging information. */ +#define SHT_MIPS_DELTADECL 0x7000001f +#define SHT_MIPS_SYMBOL_LIB 0x70000020 +#define SHT_MIPS_EVENTS 0x70000021 /* Event section. */ +#define SHT_MIPS_TRANSLATE 0x70000022 +#define SHT_MIPS_PIXIE 0x70000023 +#define SHT_MIPS_XLATE 0x70000024 +#define SHT_MIPS_XLATE_DEBUG 0x70000025 +#define SHT_MIPS_WHIRL 0x70000026 +#define SHT_MIPS_EH_REGION 0x70000027 +#define SHT_MIPS_XLATE_OLD 0x70000028 +#define SHT_MIPS_PDR_EXCEPTION 0x70000029 + +/* Legal values for sh_flags field of Elf32_Shdr. */ + +#define SHF_MIPS_GPREL 0x10000000 /* Must be part of global data area */ +#define SHF_MIPS_MERGE 0x20000000 +#define SHF_MIPS_ADDR 0x40000000 +#define SHF_MIPS_STRINGS 0x80000000 +#define SHF_MIPS_NOSTRIP 0x08000000 +#define SHF_MIPS_LOCAL 0x04000000 +#define SHF_MIPS_NAMES 0x02000000 +#define SHF_MIPS_NODUPE 0x01000000 + + +/* Symbol tables. */ + +/* MIPS specific values for `st_other'. */ +#define STO_MIPS_DEFAULT 0x0 +#define STO_MIPS_INTERNAL 0x1 +#define STO_MIPS_HIDDEN 0x2 +#define STO_MIPS_PROTECTED 0x3 +#define STO_MIPS_SC_ALIGN_UNUSED 0xff + +/* MIPS specific values for `st_info'. */ +#define STB_MIPS_SPLIT_COMMON 13 + +/* Entries found in sections of type SHT_MIPS_GPTAB. */ + +typedef union +{ + struct + { + Elf32_Word gt_current_g_value; /* -G value used for compilation */ + Elf32_Word gt_unused; /* Not used */ + } gt_header; /* First entry in section */ + struct + { + Elf32_Word gt_g_value; /* If this value were used for -G */ + Elf32_Word gt_bytes; /* This many bytes would be used */ + } gt_entry; /* Subsequent entries in section */ +} Elf32_gptab; + +/* Entry found in sections of type SHT_MIPS_REGINFO. */ + +typedef struct +{ + Elf32_Word ri_gprmask; /* General registers used */ + Elf32_Word ri_cprmask[4]; /* Coprocessor registers used */ + Elf32_Sword ri_gp_value; /* $gp register value */ +} Elf32_RegInfo; + +/* Entries found in sections of type SHT_MIPS_OPTIONS. */ + +typedef struct +{ + unsigned char kind; /* Determines interpretation of the + variable part of descriptor. */ + unsigned char size; /* Size of descriptor, including header. */ + Elf32_Section section; /* Section header index of section affected, + 0 for global options. */ + Elf32_Word info; /* Kind-specific information. */ +} Elf_Options; + +/* Values for `kind' field in Elf_Options. */ + +#define ODK_NULL 0 /* Undefined. */ +#define ODK_REGINFO 1 /* Register usage information. */ +#define ODK_EXCEPTIONS 2 /* Exception processing options. */ +#define ODK_PAD 3 /* Section padding options. */ +#define ODK_HWPATCH 4 /* Hardware workarounds performed */ +#define ODK_FILL 5 /* record the fill value used by the linker. */ +#define ODK_TAGS 6 /* reserve space for desktop tools to write. */ +#define ODK_HWAND 7 /* HW workarounds. 'AND' bits when merging. */ +#define ODK_HWOR 8 /* HW workarounds. 'OR' bits when merging. */ + +/* Values for `info' in Elf_Options for ODK_EXCEPTIONS entries. */ + +#define OEX_FPU_MIN 0x1f /* FPE's which MUST be enabled. */ +#define OEX_FPU_MAX 0x1f00 /* FPE's which MAY be enabled. */ +#define OEX_PAGE0 0x10000 /* page zero must be mapped. */ +#define OEX_SMM 0x20000 /* Force sequential memory mode? */ +#define OEX_FPDBUG 0x40000 /* Force floating point debug mode? */ +#define OEX_PRECISEFP OEX_FPDBUG +#define OEX_DISMISS 0x80000 /* Dismiss invalid address faults? */ + +#define OEX_FPU_INVAL 0x10 +#define OEX_FPU_DIV0 0x08 +#define OEX_FPU_OFLO 0x04 +#define OEX_FPU_UFLO 0x02 +#define OEX_FPU_INEX 0x01 + +/* Masks for `info' in Elf_Options for an ODK_HWPATCH entry. */ + +#define OHW_R4KEOP 0x1 /* R4000 end-of-page patch. */ +#define OHW_R8KPFETCH 0x2 /* may need R8000 prefetch patch. */ +#define OHW_R5KEOP 0x4 /* R5000 end-of-page patch. */ +#define OHW_R5KCVTL 0x8 /* R5000 cvt.[ds].l bug. clean=1. */ + +#define OPAD_PREFIX 0x1 +#define OPAD_POSTFIX 0x2 +#define OPAD_SYMBOL 0x4 + +/* Entry found in `.options' section. */ + +typedef struct +{ + Elf32_Word hwp_flags1; /* Extra flags. */ + Elf32_Word hwp_flags2; /* Extra flags. */ +} Elf_Options_Hw; + +/* Masks for `info' in ElfOptions for ODK_HWAND and ODK_HWOR entries. */ + +#define OHWA0_R4KEOP_CHECKED 0x00000001 +#define OHWA1_R4KEOP_CLEAN 0x00000002 + +/* MIPS relocs. */ + +#define R_MIPS_NONE 0 /* No reloc */ +#define R_MIPS_16 1 /* Direct 16 bit */ +#define R_MIPS_32 2 /* Direct 32 bit */ +#define R_MIPS_REL32 3 /* PC relative 32 bit */ +#define R_MIPS_26 4 /* Direct 26 bit shifted */ +#define R_MIPS_HI16 5 /* High 16 bit */ +#define R_MIPS_LO16 6 /* Low 16 bit */ +#define R_MIPS_GPREL16 7 /* GP relative 16 bit */ +#define R_MIPS_LITERAL 8 /* 16 bit literal entry */ +#define R_MIPS_GOT16 9 /* 16 bit GOT entry */ +#define R_MIPS_PC16 10 /* PC relative 16 bit */ +#define R_MIPS_CALL16 11 /* 16 bit GOT entry for function */ +#define R_MIPS_GPREL32 12 /* GP relative 32 bit */ + +#define R_MIPS_SHIFT5 16 +#define R_MIPS_SHIFT6 17 +#define R_MIPS_64 18 +#define R_MIPS_GOT_DISP 19 +#define R_MIPS_GOT_PAGE 20 +#define R_MIPS_GOT_OFST 21 +#define R_MIPS_GOT_HI16 22 +#define R_MIPS_GOT_LO16 23 +#define R_MIPS_SUB 24 +#define R_MIPS_INSERT_A 25 +#define R_MIPS_INSERT_B 26 +#define R_MIPS_DELETE 27 +#define R_MIPS_HIGHER 28 +#define R_MIPS_HIGHEST 29 +#define R_MIPS_CALL_HI16 30 +#define R_MIPS_CALL_LO16 31 +#define R_MIPS_SCN_DISP 32 +#define R_MIPS_REL16 33 +#define R_MIPS_ADD_IMMEDIATE 34 +#define R_MIPS_PJUMP 35 +#define R_MIPS_RELGOT 36 +#define R_MIPS_JALR 37 +#define R_MIPS_TLS_DTPMOD32 38 /* Module number 32 bit */ +#define R_MIPS_TLS_DTPREL32 39 /* Module-relative offset 32 bit */ +#define R_MIPS_TLS_DTPMOD64 40 /* Module number 64 bit */ +#define R_MIPS_TLS_DTPREL64 41 /* Module-relative offset 64 bit */ +#define R_MIPS_TLS_GD 42 /* 16 bit GOT offset for GD */ +#define R_MIPS_TLS_LDM 43 /* 16 bit GOT offset for LDM */ +#define R_MIPS_TLS_DTPREL_HI16 44 /* Module-relative offset, high 16 bits */ +#define R_MIPS_TLS_DTPREL_LO16 45 /* Module-relative offset, low 16 bits */ +#define R_MIPS_TLS_GOTTPREL 46 /* 16 bit GOT offset for IE */ +#define R_MIPS_TLS_TPREL32 47 /* TP-relative offset, 32 bit */ +#define R_MIPS_TLS_TPREL64 48 /* TP-relative offset, 64 bit */ +#define R_MIPS_TLS_TPREL_HI16 49 /* TP-relative offset, high 16 bits */ +#define R_MIPS_TLS_TPREL_LO16 50 /* TP-relative offset, low 16 bits */ +#define R_MIPS_GLOB_DAT 51 +/* Keep this the last entry. */ +#define R_MIPS_NUM 52 + +/* Legal values for p_type field of Elf32_Phdr. */ + +#define PT_MIPS_REGINFO 0x70000000 /* Register usage information */ +#define PT_MIPS_RTPROC 0x70000001 /* Runtime procedure table. */ +#define PT_MIPS_OPTIONS 0x70000002 + +/* Special program header types. */ + +#define PF_MIPS_LOCAL 0x10000000 + +/* Legal values for d_tag field of Elf32_Dyn. */ + +#define DT_MIPS_RLD_VERSION 0x70000001 /* Runtime linker interface version */ +#define DT_MIPS_TIME_STAMP 0x70000002 /* Timestamp */ +#define DT_MIPS_ICHECKSUM 0x70000003 /* Checksum */ +#define DT_MIPS_IVERSION 0x70000004 /* Version string (string tbl index) */ +#define DT_MIPS_FLAGS 0x70000005 /* Flags */ +#define DT_MIPS_BASE_ADDRESS 0x70000006 /* Base address */ +#define DT_MIPS_MSYM 0x70000007 +#define DT_MIPS_CONFLICT 0x70000008 /* Address of CONFLICT section */ +#define DT_MIPS_LIBLIST 0x70000009 /* Address of LIBLIST section */ +#define DT_MIPS_LOCAL_GOTNO 0x7000000a /* Number of local GOT entries */ +#define DT_MIPS_CONFLICTNO 0x7000000b /* Number of CONFLICT entries */ +#define DT_MIPS_LIBLISTNO 0x70000010 /* Number of LIBLIST entries */ +#define DT_MIPS_SYMTABNO 0x70000011 /* Number of DYNSYM entries */ +#define DT_MIPS_UNREFEXTNO 0x70000012 /* First external DYNSYM */ +#define DT_MIPS_GOTSYM 0x70000013 /* First GOT entry in DYNSYM */ +#define DT_MIPS_HIPAGENO 0x70000014 /* Number of GOT page table entries */ +#define DT_MIPS_RLD_MAP 0x70000016 /* Address of run time loader map. */ +#define DT_MIPS_DELTA_CLASS 0x70000017 /* Delta C++ class definition. */ +#define DT_MIPS_DELTA_CLASS_NO 0x70000018 /* Number of entries in + DT_MIPS_DELTA_CLASS. */ +#define DT_MIPS_DELTA_INSTANCE 0x70000019 /* Delta C++ class instances. */ +#define DT_MIPS_DELTA_INSTANCE_NO 0x7000001a /* Number of entries in + DT_MIPS_DELTA_INSTANCE. */ +#define DT_MIPS_DELTA_RELOC 0x7000001b /* Delta relocations. */ +#define DT_MIPS_DELTA_RELOC_NO 0x7000001c /* Number of entries in + DT_MIPS_DELTA_RELOC. */ +#define DT_MIPS_DELTA_SYM 0x7000001d /* Delta symbols that Delta + relocations refer to. */ +#define DT_MIPS_DELTA_SYM_NO 0x7000001e /* Number of entries in + DT_MIPS_DELTA_SYM. */ +#define DT_MIPS_DELTA_CLASSSYM 0x70000020 /* Delta symbols that hold the + class declaration. */ +#define DT_MIPS_DELTA_CLASSSYM_NO 0x70000021 /* Number of entries in + DT_MIPS_DELTA_CLASSSYM. */ +#define DT_MIPS_CXX_FLAGS 0x70000022 /* Flags indicating for C++ flavor. */ +#define DT_MIPS_PIXIE_INIT 0x70000023 +#define DT_MIPS_SYMBOL_LIB 0x70000024 +#define DT_MIPS_LOCALPAGE_GOTIDX 0x70000025 +#define DT_MIPS_LOCAL_GOTIDX 0x70000026 +#define DT_MIPS_HIDDEN_GOTIDX 0x70000027 +#define DT_MIPS_PROTECTED_GOTIDX 0x70000028 +#define DT_MIPS_OPTIONS 0x70000029 /* Address of .options. */ +#define DT_MIPS_INTERFACE 0x7000002a /* Address of .interface. */ +#define DT_MIPS_DYNSTR_ALIGN 0x7000002b +#define DT_MIPS_INTERFACE_SIZE 0x7000002c /* Size of the .interface section. */ +#define DT_MIPS_RLD_TEXT_RESOLVE_ADDR 0x7000002d /* Address of rld_text_rsolve + function stored in GOT. */ +#define DT_MIPS_PERF_SUFFIX 0x7000002e /* Default suffix of dso to be added + by rld on dlopen() calls. */ +#define DT_MIPS_COMPACT_SIZE 0x7000002f /* (O32)Size of compact rel section. */ +#define DT_MIPS_GP_VALUE 0x70000030 /* GP value for aux GOTs. */ +#define DT_MIPS_AUX_DYNAMIC 0x70000031 /* Address of aux .dynamic. */ +#define DT_MIPS_NUM 0x32 + +/* Legal values for DT_MIPS_FLAGS Elf32_Dyn entry. */ + +#define RHF_NONE 0 /* No flags */ +#define RHF_QUICKSTART (1 << 0) /* Use quickstart */ +#define RHF_NOTPOT (1 << 1) /* Hash size not power of 2 */ +#define RHF_NO_LIBRARY_REPLACEMENT (1 << 2) /* Ignore LD_LIBRARY_PATH */ +#define RHF_NO_MOVE (1 << 3) +#define RHF_SGI_ONLY (1 << 4) +#define RHF_GUARANTEE_INIT (1 << 5) +#define RHF_DELTA_C_PLUS_PLUS (1 << 6) +#define RHF_GUARANTEE_START_INIT (1 << 7) +#define RHF_PIXIE (1 << 8) +#define RHF_DEFAULT_DELAY_LOAD (1 << 9) +#define RHF_REQUICKSTART (1 << 10) +#define RHF_REQUICKSTARTED (1 << 11) +#define RHF_CORD (1 << 12) +#define RHF_NO_UNRES_UNDEF (1 << 13) +#define RHF_RLD_ORDER_SAFE (1 << 14) + +/* Entries found in sections of type SHT_MIPS_LIBLIST. */ + +typedef struct +{ + Elf32_Word l_name; /* Name (string table index) */ + Elf32_Word l_time_stamp; /* Timestamp */ + Elf32_Word l_checksum; /* Checksum */ + Elf32_Word l_version; /* Interface version */ + Elf32_Word l_flags; /* Flags */ +} Elf32_Lib; + +typedef struct +{ + Elf64_Word l_name; /* Name (string table index) */ + Elf64_Word l_time_stamp; /* Timestamp */ + Elf64_Word l_checksum; /* Checksum */ + Elf64_Word l_version; /* Interface version */ + Elf64_Word l_flags; /* Flags */ +} Elf64_Lib; + + +/* Legal values for l_flags. */ + +#define LL_NONE 0 +#define LL_EXACT_MATCH (1 << 0) /* Require exact match */ +#define LL_IGNORE_INT_VER (1 << 1) /* Ignore interface version */ +#define LL_REQUIRE_MINOR (1 << 2) +#define LL_EXPORTS (1 << 3) +#define LL_DELAY_LOAD (1 << 4) +#define LL_DELTA (1 << 5) + +/* Entries found in sections of type SHT_MIPS_CONFLICT. */ + +typedef Elf32_Addr Elf32_Conflict; + + +/* HPPA specific definitions. */ + +/* Legal values for e_flags field of Elf32_Ehdr. */ + +#define EF_PARISC_TRAPNIL 0x00010000 /* Trap nil pointer dereference. */ +#define EF_PARISC_EXT 0x00020000 /* Program uses arch. extensions. */ +#define EF_PARISC_LSB 0x00040000 /* Program expects little endian. */ +#define EF_PARISC_WIDE 0x00080000 /* Program expects wide mode. */ +#define EF_PARISC_NO_KABP 0x00100000 /* No kernel assisted branch + prediction. */ +#define EF_PARISC_LAZYSWAP 0x00400000 /* Allow lazy swapping. */ +#define EF_PARISC_ARCH 0x0000ffff /* Architecture version. */ + +/* Defined values for `e_flags & EF_PARISC_ARCH' are: */ + +#define EFA_PARISC_1_0 0x020b /* PA-RISC 1.0 big-endian. */ +#define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */ +#define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */ + +/* Additional section indeces. */ + +#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tenatively declared + symbols in ANSI C. */ +#define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. */ + +/* Legal values for sh_type field of Elf32_Shdr. */ + +#define SHT_PARISC_EXT 0x70000000 /* Contains product specific ext. */ +#define SHT_PARISC_UNWIND 0x70000001 /* Unwind information. */ +#define SHT_PARISC_DOC 0x70000002 /* Debug info for optimized code. */ + +/* Legal values for sh_flags field of Elf32_Shdr. */ + +#define SHF_PARISC_SHORT 0x20000000 /* Section with short addressing. */ +#define SHF_PARISC_HUGE 0x40000000 /* Section far from gp. */ +#define SHF_PARISC_SBP 0x80000000 /* Static branch prediction code. */ + +/* Legal values for ST_TYPE subfield of st_info (symbol type). */ + +#define STT_PARISC_MILLICODE 13 /* Millicode function entry point. */ + +#define STT_HP_OPAQUE (STT_LOOS + 0x1) +#define STT_HP_STUB (STT_LOOS + 0x2) + +/* HPPA relocs. */ + +#define R_PARISC_NONE 0 /* No reloc. */ +#define R_PARISC_DIR32 1 /* Direct 32-bit reference. */ +#define R_PARISC_DIR21L 2 /* Left 21 bits of eff. address. */ +#define R_PARISC_DIR17R 3 /* Right 17 bits of eff. address. */ +#define R_PARISC_DIR17F 4 /* 17 bits of eff. address. */ +#define R_PARISC_DIR14R 6 /* Right 14 bits of eff. address. */ +#define R_PARISC_PCREL32 9 /* 32-bit rel. address. */ +#define R_PARISC_PCREL21L 10 /* Left 21 bits of rel. address. */ +#define R_PARISC_PCREL17R 11 /* Right 17 bits of rel. address. */ +#define R_PARISC_PCREL17F 12 /* 17 bits of rel. address. */ +#define R_PARISC_PCREL14R 14 /* Right 14 bits of rel. address. */ +#define R_PARISC_DPREL21L 18 /* Left 21 bits of rel. address. */ +#define R_PARISC_DPREL14R 22 /* Right 14 bits of rel. address. */ +#define R_PARISC_GPREL21L 26 /* GP-relative, left 21 bits. */ +#define R_PARISC_GPREL14R 30 /* GP-relative, right 14 bits. */ +#define R_PARISC_LTOFF21L 34 /* LT-relative, left 21 bits. */ +#define R_PARISC_LTOFF14R 38 /* LT-relative, right 14 bits. */ +#define R_PARISC_SECREL32 41 /* 32 bits section rel. address. */ +#define R_PARISC_SEGBASE 48 /* No relocation, set segment base. */ +#define R_PARISC_SEGREL32 49 /* 32 bits segment rel. address. */ +#define R_PARISC_PLTOFF21L 50 /* PLT rel. address, left 21 bits. */ +#define R_PARISC_PLTOFF14R 54 /* PLT rel. address, right 14 bits. */ +#define R_PARISC_LTOFF_FPTR32 57 /* 32 bits LT-rel. function pointer. */ +#define R_PARISC_LTOFF_FPTR21L 58 /* LT-rel. fct ptr, left 21 bits. */ +#define R_PARISC_LTOFF_FPTR14R 62 /* LT-rel. fct ptr, right 14 bits. */ +#define R_PARISC_FPTR64 64 /* 64 bits function address. */ +#define R_PARISC_PLABEL32 65 /* 32 bits function address. */ +#define R_PARISC_PLABEL21L 66 /* Left 21 bits of fdesc address. */ +#define R_PARISC_PLABEL14R 70 /* Right 14 bits of fdesc address. */ +#define R_PARISC_PCREL64 72 /* 64 bits PC-rel. address. */ +#define R_PARISC_PCREL22F 74 /* 22 bits PC-rel. address. */ +#define R_PARISC_PCREL14WR 75 /* PC-rel. address, right 14 bits. */ +#define R_PARISC_PCREL14DR 76 /* PC rel. address, right 14 bits. */ +#define R_PARISC_PCREL16F 77 /* 16 bits PC-rel. address. */ +#define R_PARISC_PCREL16WF 78 /* 16 bits PC-rel. address. */ +#define R_PARISC_PCREL16DF 79 /* 16 bits PC-rel. address. */ +#define R_PARISC_DIR64 80 /* 64 bits of eff. address. */ +#define R_PARISC_DIR14WR 83 /* 14 bits of eff. address. */ +#define R_PARISC_DIR14DR 84 /* 14 bits of eff. address. */ +#define R_PARISC_DIR16F 85 /* 16 bits of eff. address. */ +#define R_PARISC_DIR16WF 86 /* 16 bits of eff. address. */ +#define R_PARISC_DIR16DF 87 /* 16 bits of eff. address. */ +#define R_PARISC_GPREL64 88 /* 64 bits of GP-rel. address. */ +#define R_PARISC_GPREL14WR 91 /* GP-rel. address, right 14 bits. */ +#define R_PARISC_GPREL14DR 92 /* GP-rel. address, right 14 bits. */ +#define R_PARISC_GPREL16F 93 /* 16 bits GP-rel. address. */ +#define R_PARISC_GPREL16WF 94 /* 16 bits GP-rel. address. */ +#define R_PARISC_GPREL16DF 95 /* 16 bits GP-rel. address. */ +#define R_PARISC_LTOFF64 96 /* 64 bits LT-rel. address. */ +#define R_PARISC_LTOFF14WR 99 /* LT-rel. address, right 14 bits. */ +#define R_PARISC_LTOFF14DR 100 /* LT-rel. address, right 14 bits. */ +#define R_PARISC_LTOFF16F 101 /* 16 bits LT-rel. address. */ +#define R_PARISC_LTOFF16WF 102 /* 16 bits LT-rel. address. */ +#define R_PARISC_LTOFF16DF 103 /* 16 bits LT-rel. address. */ +#define R_PARISC_SECREL64 104 /* 64 bits section rel. address. */ +#define R_PARISC_SEGREL64 112 /* 64 bits segment rel. address. */ +#define R_PARISC_PLTOFF14WR 115 /* PLT-rel. address, right 14 bits. */ +#define R_PARISC_PLTOFF14DR 116 /* PLT-rel. address, right 14 bits. */ +#define R_PARISC_PLTOFF16F 117 /* 16 bits LT-rel. address. */ +#define R_PARISC_PLTOFF16WF 118 /* 16 bits PLT-rel. address. */ +#define R_PARISC_PLTOFF16DF 119 /* 16 bits PLT-rel. address. */ +#define R_PARISC_LTOFF_FPTR64 120 /* 64 bits LT-rel. function ptr. */ +#define R_PARISC_LTOFF_FPTR14WR 123 /* LT-rel. fct. ptr., right 14 bits. */ +#define R_PARISC_LTOFF_FPTR14DR 124 /* LT-rel. fct. ptr., right 14 bits. */ +#define R_PARISC_LTOFF_FPTR16F 125 /* 16 bits LT-rel. function ptr. */ +#define R_PARISC_LTOFF_FPTR16WF 126 /* 16 bits LT-rel. function ptr. */ +#define R_PARISC_LTOFF_FPTR16DF 127 /* 16 bits LT-rel. function ptr. */ +#define R_PARISC_LORESERVE 128 +#define R_PARISC_COPY 128 /* Copy relocation. */ +#define R_PARISC_IPLT 129 /* Dynamic reloc, imported PLT */ +#define R_PARISC_EPLT 130 /* Dynamic reloc, exported PLT */ +#define R_PARISC_TPREL32 153 /* 32 bits TP-rel. address. */ +#define R_PARISC_TPREL21L 154 /* TP-rel. address, left 21 bits. */ +#define R_PARISC_TPREL14R 158 /* TP-rel. address, right 14 bits. */ +#define R_PARISC_LTOFF_TP21L 162 /* LT-TP-rel. address, left 21 bits. */ +#define R_PARISC_LTOFF_TP14R 166 /* LT-TP-rel. address, right 14 bits.*/ +#define R_PARISC_LTOFF_TP14F 167 /* 14 bits LT-TP-rel. address. */ +#define R_PARISC_TPREL64 216 /* 64 bits TP-rel. address. */ +#define R_PARISC_TPREL14WR 219 /* TP-rel. address, right 14 bits. */ +#define R_PARISC_TPREL14DR 220 /* TP-rel. address, right 14 bits. */ +#define R_PARISC_TPREL16F 221 /* 16 bits TP-rel. address. */ +#define R_PARISC_TPREL16WF 222 /* 16 bits TP-rel. address. */ +#define R_PARISC_TPREL16DF 223 /* 16 bits TP-rel. address. */ +#define R_PARISC_LTOFF_TP64 224 /* 64 bits LT-TP-rel. address. */ +#define R_PARISC_LTOFF_TP14WR 227 /* LT-TP-rel. address, right 14 bits.*/ +#define R_PARISC_LTOFF_TP14DR 228 /* LT-TP-rel. address, right 14 bits.*/ +#define R_PARISC_LTOFF_TP16F 229 /* 16 bits LT-TP-rel. address. */ +#define R_PARISC_LTOFF_TP16WF 230 /* 16 bits LT-TP-rel. address. */ +#define R_PARISC_LTOFF_TP16DF 231 /* 16 bits LT-TP-rel. address. */ +#define R_PARISC_GNU_VTENTRY 232 +#define R_PARISC_GNU_VTINHERIT 233 +#define R_PARISC_TLS_GD21L 234 /* GD 21-bit left. */ +#define R_PARISC_TLS_GD14R 235 /* GD 14-bit right. */ +#define R_PARISC_TLS_GDCALL 236 /* GD call to __t_g_a. */ +#define R_PARISC_TLS_LDM21L 237 /* LD module 21-bit left. */ +#define R_PARISC_TLS_LDM14R 238 /* LD module 14-bit right. */ +#define R_PARISC_TLS_LDMCALL 239 /* LD module call to __t_g_a. */ +#define R_PARISC_TLS_LDO21L 240 /* LD offset 21-bit left. */ +#define R_PARISC_TLS_LDO14R 241 /* LD offset 14-bit right. */ +#define R_PARISC_TLS_DTPMOD32 242 /* DTP module 32-bit. */ +#define R_PARISC_TLS_DTPMOD64 243 /* DTP module 64-bit. */ +#define R_PARISC_TLS_DTPOFF32 244 /* DTP offset 32-bit. */ +#define R_PARISC_TLS_DTPOFF64 245 /* DTP offset 32-bit. */ +#define R_PARISC_TLS_LE21L R_PARISC_TPREL21L +#define R_PARISC_TLS_LE14R R_PARISC_TPREL14R +#define R_PARISC_TLS_IE21L R_PARISC_LTOFF_TP21L +#define R_PARISC_TLS_IE14R R_PARISC_LTOFF_TP14R +#define R_PARISC_TLS_TPREL32 R_PARISC_TPREL32 +#define R_PARISC_TLS_TPREL64 R_PARISC_TPREL64 +#define R_PARISC_HIRESERVE 255 + +/* Legal values for p_type field of Elf32_Phdr/Elf64_Phdr. */ + +#define PT_HP_TLS (PT_LOOS + 0x0) +#define PT_HP_CORE_NONE (PT_LOOS + 0x1) +#define PT_HP_CORE_VERSION (PT_LOOS + 0x2) +#define PT_HP_CORE_KERNEL (PT_LOOS + 0x3) +#define PT_HP_CORE_COMM (PT_LOOS + 0x4) +#define PT_HP_CORE_PROC (PT_LOOS + 0x5) +#define PT_HP_CORE_LOADABLE (PT_LOOS + 0x6) +#define PT_HP_CORE_STACK (PT_LOOS + 0x7) +#define PT_HP_CORE_SHM (PT_LOOS + 0x8) +#define PT_HP_CORE_MMF (PT_LOOS + 0x9) +#define PT_HP_PARALLEL (PT_LOOS + 0x10) +#define PT_HP_FASTBIND (PT_LOOS + 0x11) +#define PT_HP_OPT_ANNOT (PT_LOOS + 0x12) +#define PT_HP_HSL_ANNOT (PT_LOOS + 0x13) +#define PT_HP_STACK (PT_LOOS + 0x14) + +#define PT_PARISC_ARCHEXT 0x70000000 +#define PT_PARISC_UNWIND 0x70000001 + +/* Legal values for p_flags field of Elf32_Phdr/Elf64_Phdr. */ + +#define PF_PARISC_SBP 0x08000000 + +#define PF_HP_PAGE_SIZE 0x00100000 +#define PF_HP_FAR_SHARED 0x00200000 +#define PF_HP_NEAR_SHARED 0x00400000 +#define PF_HP_CODE 0x01000000 +#define PF_HP_MODIFY 0x02000000 +#define PF_HP_LAZYSWAP 0x04000000 +#define PF_HP_SBP 0x08000000 + + +/* Alpha specific definitions. */ + +/* Legal values for e_flags field of Elf64_Ehdr. */ + +#define EF_ALPHA_32BIT 1 /* All addresses must be < 2GB. */ +#define EF_ALPHA_CANRELAX 2 /* Relocations for relaxing exist. */ + +/* Legal values for sh_type field of Elf64_Shdr. */ + +/* These two are primerily concerned with ECOFF debugging info. */ +#define SHT_ALPHA_DEBUG 0x70000001 +#define SHT_ALPHA_REGINFO 0x70000002 + +/* Legal values for sh_flags field of Elf64_Shdr. */ + +#define SHF_ALPHA_GPREL 0x10000000 + +/* Legal values for st_other field of Elf64_Sym. */ +#define STO_ALPHA_NOPV 0x80 /* No PV required. */ +#define STO_ALPHA_STD_GPLOAD 0x88 /* PV only used for initial ldgp. */ + +/* Alpha relocs. */ + +#define R_ALPHA_NONE 0 /* No reloc */ +#define R_ALPHA_REFLONG 1 /* Direct 32 bit */ +#define R_ALPHA_REFQUAD 2 /* Direct 64 bit */ +#define R_ALPHA_GPREL32 3 /* GP relative 32 bit */ +#define R_ALPHA_LITERAL 4 /* GP relative 16 bit w/optimization */ +#define R_ALPHA_LITUSE 5 /* Optimization hint for LITERAL */ +#define R_ALPHA_GPDISP 6 /* Add displacement to GP */ +#define R_ALPHA_BRADDR 7 /* PC+4 relative 23 bit shifted */ +#define R_ALPHA_HINT 8 /* PC+4 relative 16 bit shifted */ +#define R_ALPHA_SREL16 9 /* PC relative 16 bit */ +#define R_ALPHA_SREL32 10 /* PC relative 32 bit */ +#define R_ALPHA_SREL64 11 /* PC relative 64 bit */ +#define R_ALPHA_GPRELHIGH 17 /* GP relative 32 bit, high 16 bits */ +#define R_ALPHA_GPRELLOW 18 /* GP relative 32 bit, low 16 bits */ +#define R_ALPHA_GPREL16 19 /* GP relative 16 bit */ +#define R_ALPHA_COPY 24 /* Copy symbol at runtime */ +#define R_ALPHA_GLOB_DAT 25 /* Create GOT entry */ +#define R_ALPHA_JMP_SLOT 26 /* Create PLT entry */ +#define R_ALPHA_RELATIVE 27 /* Adjust by program base */ +#define R_ALPHA_TLS_GD_HI 28 +#define R_ALPHA_TLSGD 29 +#define R_ALPHA_TLS_LDM 30 +#define R_ALPHA_DTPMOD64 31 +#define R_ALPHA_GOTDTPREL 32 +#define R_ALPHA_DTPREL64 33 +#define R_ALPHA_DTPRELHI 34 +#define R_ALPHA_DTPRELLO 35 +#define R_ALPHA_DTPREL16 36 +#define R_ALPHA_GOTTPREL 37 +#define R_ALPHA_TPREL64 38 +#define R_ALPHA_TPRELHI 39 +#define R_ALPHA_TPRELLO 40 +#define R_ALPHA_TPREL16 41 +/* Keep this the last entry. */ +#define R_ALPHA_NUM 46 + +/* Magic values of the LITUSE relocation addend. */ +#define LITUSE_ALPHA_ADDR 0 +#define LITUSE_ALPHA_BASE 1 +#define LITUSE_ALPHA_BYTOFF 2 +#define LITUSE_ALPHA_JSR 3 +#define LITUSE_ALPHA_TLS_GD 4 +#define LITUSE_ALPHA_TLS_LDM 5 + +/* Legal values for d_tag of Elf64_Dyn. */ +#define DT_ALPHA_PLTRO (DT_LOPROC + 0) +#define DT_ALPHA_NUM 1 + +/* PowerPC specific declarations */ + +/* Values for Elf32/64_Ehdr.e_flags. */ +#define EF_PPC_EMB 0x80000000 /* PowerPC embedded flag */ + +/* Cygnus local bits below */ +#define EF_PPC_RELOCATABLE 0x00010000 /* PowerPC -mrelocatable flag*/ +#define EF_PPC_RELOCATABLE_LIB 0x00008000 /* PowerPC -mrelocatable-lib + flag */ + +/* PowerPC relocations defined by the ABIs */ +#define R_PPC_NONE 0 +#define R_PPC_ADDR32 1 /* 32bit absolute address */ +#define R_PPC_ADDR24 2 /* 26bit address, 2 bits ignored. */ +#define R_PPC_ADDR16 3 /* 16bit absolute address */ +#define R_PPC_ADDR16_LO 4 /* lower 16bit of absolute address */ +#define R_PPC_ADDR16_HI 5 /* high 16bit of absolute address */ +#define R_PPC_ADDR16_HA 6 /* adjusted high 16bit */ +#define R_PPC_ADDR14 7 /* 16bit address, 2 bits ignored */ +#define R_PPC_ADDR14_BRTAKEN 8 +#define R_PPC_ADDR14_BRNTAKEN 9 +#define R_PPC_REL24 10 /* PC relative 26 bit */ +#define R_PPC_REL14 11 /* PC relative 16 bit */ +#define R_PPC_REL14_BRTAKEN 12 +#define R_PPC_REL14_BRNTAKEN 13 +#define R_PPC_GOT16 14 +#define R_PPC_GOT16_LO 15 +#define R_PPC_GOT16_HI 16 +#define R_PPC_GOT16_HA 17 +#define R_PPC_PLTREL24 18 +#define R_PPC_COPY 19 +#define R_PPC_GLOB_DAT 20 +#define R_PPC_JMP_SLOT 21 +#define R_PPC_RELATIVE 22 +#define R_PPC_LOCAL24PC 23 +#define R_PPC_UADDR32 24 +#define R_PPC_UADDR16 25 +#define R_PPC_REL32 26 +#define R_PPC_PLT32 27 +#define R_PPC_PLTREL32 28 +#define R_PPC_PLT16_LO 29 +#define R_PPC_PLT16_HI 30 +#define R_PPC_PLT16_HA 31 +#define R_PPC_SDAREL16 32 +#define R_PPC_SECTOFF 33 +#define R_PPC_SECTOFF_LO 34 +#define R_PPC_SECTOFF_HI 35 +#define R_PPC_SECTOFF_HA 36 + +/* PowerPC relocations defined for the TLS access ABI. */ +#define R_PPC_TLS 67 /* none (sym+add)@tls */ +#define R_PPC_DTPMOD32 68 /* word32 (sym+add)@dtpmod */ +#define R_PPC_TPREL16 69 /* half16* (sym+add)@tprel */ +#define R_PPC_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ +#define R_PPC_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ +#define R_PPC_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ +#define R_PPC_TPREL32 73 /* word32 (sym+add)@tprel */ +#define R_PPC_DTPREL16 74 /* half16* (sym+add)@dtprel */ +#define R_PPC_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ +#define R_PPC_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ +#define R_PPC_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ +#define R_PPC_DTPREL32 78 /* word32 (sym+add)@dtprel */ +#define R_PPC_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ +#define R_PPC_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ +#define R_PPC_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ +#define R_PPC_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ +#define R_PPC_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ +#define R_PPC_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ +#define R_PPC_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ +#define R_PPC_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ +#define R_PPC_GOT_TPREL16 87 /* half16* (sym+add)@got@tprel */ +#define R_PPC_GOT_TPREL16_LO 88 /* half16 (sym+add)@got@tprel@l */ +#define R_PPC_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ +#define R_PPC_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ +#define R_PPC_GOT_DTPREL16 91 /* half16* (sym+add)@got@dtprel */ +#define R_PPC_GOT_DTPREL16_LO 92 /* half16* (sym+add)@got@dtprel@l */ +#define R_PPC_GOT_DTPREL16_HI 93 /* half16* (sym+add)@got@dtprel@h */ +#define R_PPC_GOT_DTPREL16_HA 94 /* half16* (sym+add)@got@dtprel@ha */ + +/* Keep this the last entry. */ +#define R_PPC_NUM 95 + +/* The remaining relocs are from the Embedded ELF ABI, and are not + in the SVR4 ELF ABI. */ +#define R_PPC_EMB_NADDR32 101 +#define R_PPC_EMB_NADDR16 102 +#define R_PPC_EMB_NADDR16_LO 103 +#define R_PPC_EMB_NADDR16_HI 104 +#define R_PPC_EMB_NADDR16_HA 105 +#define R_PPC_EMB_SDAI16 106 +#define R_PPC_EMB_SDA2I16 107 +#define R_PPC_EMB_SDA2REL 108 +#define R_PPC_EMB_SDA21 109 /* 16 bit offset in SDA */ +#define R_PPC_EMB_MRKREF 110 +#define R_PPC_EMB_RELSEC16 111 +#define R_PPC_EMB_RELST_LO 112 +#define R_PPC_EMB_RELST_HI 113 +#define R_PPC_EMB_RELST_HA 114 +#define R_PPC_EMB_BIT_FLD 115 +#define R_PPC_EMB_RELSDA 116 /* 16 bit relative offset in SDA */ + +/* Diab tool relocations. */ +#define R_PPC_DIAB_SDA21_LO 180 /* like EMB_SDA21, but lower 16 bit */ +#define R_PPC_DIAB_SDA21_HI 181 /* like EMB_SDA21, but high 16 bit */ +#define R_PPC_DIAB_SDA21_HA 182 /* like EMB_SDA21, adjusted high 16 */ +#define R_PPC_DIAB_RELSDA_LO 183 /* like EMB_RELSDA, but lower 16 bit */ +#define R_PPC_DIAB_RELSDA_HI 184 /* like EMB_RELSDA, but high 16 bit */ +#define R_PPC_DIAB_RELSDA_HA 185 /* like EMB_RELSDA, adjusted high 16 */ + +/* GNU relocs used in PIC code sequences. */ +#define R_PPC_REL16 249 /* word32 (sym-.) */ +#define R_PPC_REL16_LO 250 /* half16 (sym-.)@l */ +#define R_PPC_REL16_HI 251 /* half16 (sym-.)@h */ +#define R_PPC_REL16_HA 252 /* half16 (sym-.)@ha */ + +/* This is a phony reloc to handle any old fashioned TOC16 references + that may still be in object files. */ +#define R_PPC_TOC16 255 + +/* PowerPC specific values for the Dyn d_tag field. */ +#define DT_PPC_GOT (DT_LOPROC + 0) +#define DT_PPC_NUM 1 + +/* PowerPC64 relocations defined by the ABIs */ +#define R_PPC64_NONE R_PPC_NONE +#define R_PPC64_ADDR32 R_PPC_ADDR32 /* 32bit absolute address */ +#define R_PPC64_ADDR24 R_PPC_ADDR24 /* 26bit address, word aligned */ +#define R_PPC64_ADDR16 R_PPC_ADDR16 /* 16bit absolute address */ +#define R_PPC64_ADDR16_LO R_PPC_ADDR16_LO /* lower 16bits of address */ +#define R_PPC64_ADDR16_HI R_PPC_ADDR16_HI /* high 16bits of address. */ +#define R_PPC64_ADDR16_HA R_PPC_ADDR16_HA /* adjusted high 16bits. */ +#define R_PPC64_ADDR14 R_PPC_ADDR14 /* 16bit address, word aligned */ +#define R_PPC64_ADDR14_BRTAKEN R_PPC_ADDR14_BRTAKEN +#define R_PPC64_ADDR14_BRNTAKEN R_PPC_ADDR14_BRNTAKEN +#define R_PPC64_REL24 R_PPC_REL24 /* PC-rel. 26 bit, word aligned */ +#define R_PPC64_REL14 R_PPC_REL14 /* PC relative 16 bit */ +#define R_PPC64_REL14_BRTAKEN R_PPC_REL14_BRTAKEN +#define R_PPC64_REL14_BRNTAKEN R_PPC_REL14_BRNTAKEN +#define R_PPC64_GOT16 R_PPC_GOT16 +#define R_PPC64_GOT16_LO R_PPC_GOT16_LO +#define R_PPC64_GOT16_HI R_PPC_GOT16_HI +#define R_PPC64_GOT16_HA R_PPC_GOT16_HA + +#define R_PPC64_COPY R_PPC_COPY +#define R_PPC64_GLOB_DAT R_PPC_GLOB_DAT +#define R_PPC64_JMP_SLOT R_PPC_JMP_SLOT +#define R_PPC64_RELATIVE R_PPC_RELATIVE + +#define R_PPC64_UADDR32 R_PPC_UADDR32 +#define R_PPC64_UADDR16 R_PPC_UADDR16 +#define R_PPC64_REL32 R_PPC_REL32 +#define R_PPC64_PLT32 R_PPC_PLT32 +#define R_PPC64_PLTREL32 R_PPC_PLTREL32 +#define R_PPC64_PLT16_LO R_PPC_PLT16_LO +#define R_PPC64_PLT16_HI R_PPC_PLT16_HI +#define R_PPC64_PLT16_HA R_PPC_PLT16_HA + +#define R_PPC64_SECTOFF R_PPC_SECTOFF +#define R_PPC64_SECTOFF_LO R_PPC_SECTOFF_LO +#define R_PPC64_SECTOFF_HI R_PPC_SECTOFF_HI +#define R_PPC64_SECTOFF_HA R_PPC_SECTOFF_HA +#define R_PPC64_ADDR30 37 /* word30 (S + A - P) >> 2 */ +#define R_PPC64_ADDR64 38 /* doubleword64 S + A */ +#define R_PPC64_ADDR16_HIGHER 39 /* half16 #higher(S + A) */ +#define R_PPC64_ADDR16_HIGHERA 40 /* half16 #highera(S + A) */ +#define R_PPC64_ADDR16_HIGHEST 41 /* half16 #highest(S + A) */ +#define R_PPC64_ADDR16_HIGHESTA 42 /* half16 #highesta(S + A) */ +#define R_PPC64_UADDR64 43 /* doubleword64 S + A */ +#define R_PPC64_REL64 44 /* doubleword64 S + A - P */ +#define R_PPC64_PLT64 45 /* doubleword64 L + A */ +#define R_PPC64_PLTREL64 46 /* doubleword64 L + A - P */ +#define R_PPC64_TOC16 47 /* half16* S + A - .TOC */ +#define R_PPC64_TOC16_LO 48 /* half16 #lo(S + A - .TOC.) */ +#define R_PPC64_TOC16_HI 49 /* half16 #hi(S + A - .TOC.) */ +#define R_PPC64_TOC16_HA 50 /* half16 #ha(S + A - .TOC.) */ +#define R_PPC64_TOC 51 /* doubleword64 .TOC */ +#define R_PPC64_PLTGOT16 52 /* half16* M + A */ +#define R_PPC64_PLTGOT16_LO 53 /* half16 #lo(M + A) */ +#define R_PPC64_PLTGOT16_HI 54 /* half16 #hi(M + A) */ +#define R_PPC64_PLTGOT16_HA 55 /* half16 #ha(M + A) */ + +#define R_PPC64_ADDR16_DS 56 /* half16ds* (S + A) >> 2 */ +#define R_PPC64_ADDR16_LO_DS 57 /* half16ds #lo(S + A) >> 2 */ +#define R_PPC64_GOT16_DS 58 /* half16ds* (G + A) >> 2 */ +#define R_PPC64_GOT16_LO_DS 59 /* half16ds #lo(G + A) >> 2 */ +#define R_PPC64_PLT16_LO_DS 60 /* half16ds #lo(L + A) >> 2 */ +#define R_PPC64_SECTOFF_DS 61 /* half16ds* (R + A) >> 2 */ +#define R_PPC64_SECTOFF_LO_DS 62 /* half16ds #lo(R + A) >> 2 */ +#define R_PPC64_TOC16_DS 63 /* half16ds* (S + A - .TOC.) >> 2 */ +#define R_PPC64_TOC16_LO_DS 64 /* half16ds #lo(S + A - .TOC.) >> 2 */ +#define R_PPC64_PLTGOT16_DS 65 /* half16ds* (M + A) >> 2 */ +#define R_PPC64_PLTGOT16_LO_DS 66 /* half16ds #lo(M + A) >> 2 */ + +/* PowerPC64 relocations defined for the TLS access ABI. */ +#define R_PPC64_TLS 67 /* none (sym+add)@tls */ +#define R_PPC64_DTPMOD64 68 /* doubleword64 (sym+add)@dtpmod */ +#define R_PPC64_TPREL16 69 /* half16* (sym+add)@tprel */ +#define R_PPC64_TPREL16_LO 70 /* half16 (sym+add)@tprel@l */ +#define R_PPC64_TPREL16_HI 71 /* half16 (sym+add)@tprel@h */ +#define R_PPC64_TPREL16_HA 72 /* half16 (sym+add)@tprel@ha */ +#define R_PPC64_TPREL64 73 /* doubleword64 (sym+add)@tprel */ +#define R_PPC64_DTPREL16 74 /* half16* (sym+add)@dtprel */ +#define R_PPC64_DTPREL16_LO 75 /* half16 (sym+add)@dtprel@l */ +#define R_PPC64_DTPREL16_HI 76 /* half16 (sym+add)@dtprel@h */ +#define R_PPC64_DTPREL16_HA 77 /* half16 (sym+add)@dtprel@ha */ +#define R_PPC64_DTPREL64 78 /* doubleword64 (sym+add)@dtprel */ +#define R_PPC64_GOT_TLSGD16 79 /* half16* (sym+add)@got@tlsgd */ +#define R_PPC64_GOT_TLSGD16_LO 80 /* half16 (sym+add)@got@tlsgd@l */ +#define R_PPC64_GOT_TLSGD16_HI 81 /* half16 (sym+add)@got@tlsgd@h */ +#define R_PPC64_GOT_TLSGD16_HA 82 /* half16 (sym+add)@got@tlsgd@ha */ +#define R_PPC64_GOT_TLSLD16 83 /* half16* (sym+add)@got@tlsld */ +#define R_PPC64_GOT_TLSLD16_LO 84 /* half16 (sym+add)@got@tlsld@l */ +#define R_PPC64_GOT_TLSLD16_HI 85 /* half16 (sym+add)@got@tlsld@h */ +#define R_PPC64_GOT_TLSLD16_HA 86 /* half16 (sym+add)@got@tlsld@ha */ +#define R_PPC64_GOT_TPREL16_DS 87 /* half16ds* (sym+add)@got@tprel */ +#define R_PPC64_GOT_TPREL16_LO_DS 88 /* half16ds (sym+add)@got@tprel@l */ +#define R_PPC64_GOT_TPREL16_HI 89 /* half16 (sym+add)@got@tprel@h */ +#define R_PPC64_GOT_TPREL16_HA 90 /* half16 (sym+add)@got@tprel@ha */ +#define R_PPC64_GOT_DTPREL16_DS 91 /* half16ds* (sym+add)@got@dtprel */ +#define R_PPC64_GOT_DTPREL16_LO_DS 92 /* half16ds (sym+add)@got@dtprel@l */ +#define R_PPC64_GOT_DTPREL16_HI 93 /* half16 (sym+add)@got@dtprel@h */ +#define R_PPC64_GOT_DTPREL16_HA 94 /* half16 (sym+add)@got@dtprel@ha */ +#define R_PPC64_TPREL16_DS 95 /* half16ds* (sym+add)@tprel */ +#define R_PPC64_TPREL16_LO_DS 96 /* half16ds (sym+add)@tprel@l */ +#define R_PPC64_TPREL16_HIGHER 97 /* half16 (sym+add)@tprel@higher */ +#define R_PPC64_TPREL16_HIGHERA 98 /* half16 (sym+add)@tprel@highera */ +#define R_PPC64_TPREL16_HIGHEST 99 /* half16 (sym+add)@tprel@highest */ +#define R_PPC64_TPREL16_HIGHESTA 100 /* half16 (sym+add)@tprel@highesta */ +#define R_PPC64_DTPREL16_DS 101 /* half16ds* (sym+add)@dtprel */ +#define R_PPC64_DTPREL16_LO_DS 102 /* half16ds (sym+add)@dtprel@l */ +#define R_PPC64_DTPREL16_HIGHER 103 /* half16 (sym+add)@dtprel@higher */ +#define R_PPC64_DTPREL16_HIGHERA 104 /* half16 (sym+add)@dtprel@highera */ +#define R_PPC64_DTPREL16_HIGHEST 105 /* half16 (sym+add)@dtprel@highest */ +#define R_PPC64_DTPREL16_HIGHESTA 106 /* half16 (sym+add)@dtprel@highesta */ + +/* Keep this the last entry. */ +#define R_PPC64_NUM 107 + +/* PowerPC64 specific values for the Dyn d_tag field. */ +#define DT_PPC64_GLINK (DT_LOPROC + 0) +#define DT_PPC64_OPD (DT_LOPROC + 1) +#define DT_PPC64_OPDSZ (DT_LOPROC + 2) +#define DT_PPC64_NUM 3 + + +/* ARM specific declarations */ + +/* Processor specific flags for the ELF header e_flags field. */ +#define EF_ARM_RELEXEC 0x01 +#define EF_ARM_HASENTRY 0x02 +#define EF_ARM_INTERWORK 0x04 +#define EF_ARM_APCS_26 0x08 +#define EF_ARM_APCS_FLOAT 0x10 +#define EF_ARM_PIC 0x20 +#define EF_ARM_ALIGN8 0x40 /* 8-bit structure alignment is in use */ +#define EF_ARM_NEW_ABI 0x80 +#define EF_ARM_OLD_ABI 0x100 + +/* Other constants defined in the ARM ELF spec. version B-01. */ +/* NB. These conflict with values defined above. */ +#define EF_ARM_SYMSARESORTED 0x04 +#define EF_ARM_DYNSYMSUSESEGIDX 0x08 +#define EF_ARM_MAPSYMSFIRST 0x10 +#define EF_ARM_EABIMASK 0XFF000000 + +#define EF_ARM_EABI_VERSION(flags) ((flags) & EF_ARM_EABIMASK) +#define EF_ARM_EABI_UNKNOWN 0x00000000 +#define EF_ARM_EABI_VER1 0x01000000 +#define EF_ARM_EABI_VER2 0x02000000 + +/* Additional symbol types for Thumb */ +#define STT_ARM_TFUNC 0xd + +/* ARM-specific values for sh_flags */ +#define SHF_ARM_ENTRYSECT 0x10000000 /* Section contains an entry point */ +#define SHF_ARM_COMDEF 0x80000000 /* Section may be multiply defined + in the input to a link step */ + +/* ARM-specific program header flags */ +#define PF_ARM_SB 0x10000000 /* Segment contains the location + addressed by the static base */ + +/* Processor specific values for the Phdr p_type field. */ +#define PT_ARM_EXIDX 0x70000001 /* .ARM.exidx segment */ + +/* ARM relocs. */ + +#define R_ARM_NONE 0 /* No reloc */ +#define R_ARM_PC24 1 /* PC relative 26 bit branch */ +#define R_ARM_ABS32 2 /* Direct 32 bit */ +#define R_ARM_REL32 3 /* PC relative 32 bit */ +#define R_ARM_PC13 4 +#define R_ARM_ABS16 5 /* Direct 16 bit */ +#define R_ARM_ABS12 6 /* Direct 12 bit */ +#define R_ARM_THM_ABS5 7 +#define R_ARM_ABS8 8 /* Direct 8 bit */ +#define R_ARM_SBREL32 9 +#define R_ARM_THM_PC22 10 +#define R_ARM_THM_PC8 11 +#define R_ARM_AMP_VCALL9 12 +#define R_ARM_SWI24 13 +#define R_ARM_THM_SWI8 14 +#define R_ARM_XPC25 15 +#define R_ARM_THM_XPC22 16 +#define R_ARM_TLS_DTPMOD32 17 /* ID of module containing symbol */ +#define R_ARM_TLS_DTPOFF32 18 /* Offset in TLS block */ +#define R_ARM_TLS_TPOFF32 19 /* Offset in static TLS block */ +#define R_ARM_COPY 20 /* Copy symbol at runtime */ +#define R_ARM_GLOB_DAT 21 /* Create GOT entry */ +#define R_ARM_JUMP_SLOT 22 /* Create PLT entry */ +#define R_ARM_RELATIVE 23 /* Adjust by program base */ +#define R_ARM_GOTOFF 24 /* 32 bit offset to GOT */ +#define R_ARM_GOTPC 25 /* 32 bit PC relative offset to GOT */ +#define R_ARM_GOT32 26 /* 32 bit GOT entry */ +#define R_ARM_PLT32 27 /* 32 bit PLT address */ +#define R_ARM_ALU_PCREL_7_0 32 +#define R_ARM_ALU_PCREL_15_8 33 +#define R_ARM_ALU_PCREL_23_15 34 +#define R_ARM_LDR_SBREL_11_0 35 +#define R_ARM_ALU_SBREL_19_12 36 +#define R_ARM_ALU_SBREL_27_20 37 +#define R_ARM_GNU_VTENTRY 100 +#define R_ARM_GNU_VTINHERIT 101 +#define R_ARM_THM_PC11 102 /* thumb unconditional branch */ +#define R_ARM_THM_PC9 103 /* thumb conditional branch */ +#define R_ARM_TLS_GD32 104 /* PC-rel 32 bit for global dynamic + thread local data */ +#define R_ARM_TLS_LDM32 105 /* PC-rel 32 bit for local dynamic + thread local data */ +#define R_ARM_TLS_LDO32 106 /* 32 bit offset relative to TLS + block */ +#define R_ARM_TLS_IE32 107 /* PC-rel 32 bit for GOT entry of + static TLS block offset */ +#define R_ARM_TLS_LE32 108 /* 32 bit offset relative to static + TLS block */ +#define R_ARM_RXPC25 249 +#define R_ARM_RSBREL32 250 +#define R_ARM_THM_RPC22 251 +#define R_ARM_RREL32 252 +#define R_ARM_RABS22 253 +#define R_ARM_RPC24 254 +#define R_ARM_RBASE 255 +/* Keep this the last entry. */ +#define R_ARM_NUM 256 + +/* IA-64 specific declarations. */ + +/* Processor specific flags for the Ehdr e_flags field. */ +#define EF_IA_64_MASKOS 0x0000000f /* os-specific flags */ +#define EF_IA_64_ABI64 0x00000010 /* 64-bit ABI */ +#define EF_IA_64_ARCH 0xff000000 /* arch. version mask */ + +/* Processor specific values for the Phdr p_type field. */ +#define PT_IA_64_ARCHEXT (PT_LOPROC + 0) /* arch extension bits */ +#define PT_IA_64_UNWIND (PT_LOPROC + 1) /* ia64 unwind bits */ +#define PT_IA_64_HP_OPT_ANOT (PT_LOOS + 0x12) +#define PT_IA_64_HP_HSL_ANOT (PT_LOOS + 0x13) +#define PT_IA_64_HP_STACK (PT_LOOS + 0x14) + +/* Processor specific flags for the Phdr p_flags field. */ +#define PF_IA_64_NORECOV 0x80000000 /* spec insns w/o recovery */ + +/* Processor specific values for the Shdr sh_type field. */ +#define SHT_IA_64_EXT (SHT_LOPROC + 0) /* extension bits */ +#define SHT_IA_64_UNWIND (SHT_LOPROC + 1) /* unwind bits */ + +/* Processor specific flags for the Shdr sh_flags field. */ +#define SHF_IA_64_SHORT 0x10000000 /* section near gp */ +#define SHF_IA_64_NORECOV 0x20000000 /* spec insns w/o recovery */ + +/* Processor specific values for the Dyn d_tag field. */ +#define DT_IA_64_PLT_RESERVE (DT_LOPROC + 0) +#define DT_IA_64_NUM 1 + +/* IA-64 relocations. */ +#define R_IA64_NONE 0x00 /* none */ +#define R_IA64_IMM14 0x21 /* symbol + addend, add imm14 */ +#define R_IA64_IMM22 0x22 /* symbol + addend, add imm22 */ +#define R_IA64_IMM64 0x23 /* symbol + addend, mov imm64 */ +#define R_IA64_DIR32MSB 0x24 /* symbol + addend, data4 MSB */ +#define R_IA64_DIR32LSB 0x25 /* symbol + addend, data4 LSB */ +#define R_IA64_DIR64MSB 0x26 /* symbol + addend, data8 MSB */ +#define R_IA64_DIR64LSB 0x27 /* symbol + addend, data8 LSB */ +#define R_IA64_GPREL22 0x2a /* @gprel(sym + add), add imm22 */ +#define R_IA64_GPREL64I 0x2b /* @gprel(sym + add), mov imm64 */ +#define R_IA64_GPREL32MSB 0x2c /* @gprel(sym + add), data4 MSB */ +#define R_IA64_GPREL32LSB 0x2d /* @gprel(sym + add), data4 LSB */ +#define R_IA64_GPREL64MSB 0x2e /* @gprel(sym + add), data8 MSB */ +#define R_IA64_GPREL64LSB 0x2f /* @gprel(sym + add), data8 LSB */ +#define R_IA64_LTOFF22 0x32 /* @ltoff(sym + add), add imm22 */ +#define R_IA64_LTOFF64I 0x33 /* @ltoff(sym + add), mov imm64 */ +#define R_IA64_PLTOFF22 0x3a /* @pltoff(sym + add), add imm22 */ +#define R_IA64_PLTOFF64I 0x3b /* @pltoff(sym + add), mov imm64 */ +#define R_IA64_PLTOFF64MSB 0x3e /* @pltoff(sym + add), data8 MSB */ +#define R_IA64_PLTOFF64LSB 0x3f /* @pltoff(sym + add), data8 LSB */ +#define R_IA64_FPTR64I 0x43 /* @fptr(sym + add), mov imm64 */ +#define R_IA64_FPTR32MSB 0x44 /* @fptr(sym + add), data4 MSB */ +#define R_IA64_FPTR32LSB 0x45 /* @fptr(sym + add), data4 LSB */ +#define R_IA64_FPTR64MSB 0x46 /* @fptr(sym + add), data8 MSB */ +#define R_IA64_FPTR64LSB 0x47 /* @fptr(sym + add), data8 LSB */ +#define R_IA64_PCREL60B 0x48 /* @pcrel(sym + add), brl */ +#define R_IA64_PCREL21B 0x49 /* @pcrel(sym + add), ptb, call */ +#define R_IA64_PCREL21M 0x4a /* @pcrel(sym + add), chk.s */ +#define R_IA64_PCREL21F 0x4b /* @pcrel(sym + add), fchkf */ +#define R_IA64_PCREL32MSB 0x4c /* @pcrel(sym + add), data4 MSB */ +#define R_IA64_PCREL32LSB 0x4d /* @pcrel(sym + add), data4 LSB */ +#define R_IA64_PCREL64MSB 0x4e /* @pcrel(sym + add), data8 MSB */ +#define R_IA64_PCREL64LSB 0x4f /* @pcrel(sym + add), data8 LSB */ +#define R_IA64_LTOFF_FPTR22 0x52 /* @ltoff(@fptr(s+a)), imm22 */ +#define R_IA64_LTOFF_FPTR64I 0x53 /* @ltoff(@fptr(s+a)), imm64 */ +#define R_IA64_LTOFF_FPTR32MSB 0x54 /* @ltoff(@fptr(s+a)), data4 MSB */ +#define R_IA64_LTOFF_FPTR32LSB 0x55 /* @ltoff(@fptr(s+a)), data4 LSB */ +#define R_IA64_LTOFF_FPTR64MSB 0x56 /* @ltoff(@fptr(s+a)), data8 MSB */ +#define R_IA64_LTOFF_FPTR64LSB 0x57 /* @ltoff(@fptr(s+a)), data8 LSB */ +#define R_IA64_SEGREL32MSB 0x5c /* @segrel(sym + add), data4 MSB */ +#define R_IA64_SEGREL32LSB 0x5d /* @segrel(sym + add), data4 LSB */ +#define R_IA64_SEGREL64MSB 0x5e /* @segrel(sym + add), data8 MSB */ +#define R_IA64_SEGREL64LSB 0x5f /* @segrel(sym + add), data8 LSB */ +#define R_IA64_SECREL32MSB 0x64 /* @secrel(sym + add), data4 MSB */ +#define R_IA64_SECREL32LSB 0x65 /* @secrel(sym + add), data4 LSB */ +#define R_IA64_SECREL64MSB 0x66 /* @secrel(sym + add), data8 MSB */ +#define R_IA64_SECREL64LSB 0x67 /* @secrel(sym + add), data8 LSB */ +#define R_IA64_REL32MSB 0x6c /* data 4 + REL */ +#define R_IA64_REL32LSB 0x6d /* data 4 + REL */ +#define R_IA64_REL64MSB 0x6e /* data 8 + REL */ +#define R_IA64_REL64LSB 0x6f /* data 8 + REL */ +#define R_IA64_LTV32MSB 0x74 /* symbol + addend, data4 MSB */ +#define R_IA64_LTV32LSB 0x75 /* symbol + addend, data4 LSB */ +#define R_IA64_LTV64MSB 0x76 /* symbol + addend, data8 MSB */ +#define R_IA64_LTV64LSB 0x77 /* symbol + addend, data8 LSB */ +#define R_IA64_PCREL21BI 0x79 /* @pcrel(sym + add), 21bit inst */ +#define R_IA64_PCREL22 0x7a /* @pcrel(sym + add), 22bit inst */ +#define R_IA64_PCREL64I 0x7b /* @pcrel(sym + add), 64bit inst */ +#define R_IA64_IPLTMSB 0x80 /* dynamic reloc, imported PLT, MSB */ +#define R_IA64_IPLTLSB 0x81 /* dynamic reloc, imported PLT, LSB */ +#define R_IA64_COPY 0x84 /* copy relocation */ +#define R_IA64_SUB 0x85 /* Addend and symbol difference */ +#define R_IA64_LTOFF22X 0x86 /* LTOFF22, relaxable. */ +#define R_IA64_LDXMOV 0x87 /* Use of LTOFF22X. */ +#define R_IA64_TPREL14 0x91 /* @tprel(sym + add), imm14 */ +#define R_IA64_TPREL22 0x92 /* @tprel(sym + add), imm22 */ +#define R_IA64_TPREL64I 0x93 /* @tprel(sym + add), imm64 */ +#define R_IA64_TPREL64MSB 0x96 /* @tprel(sym + add), data8 MSB */ +#define R_IA64_TPREL64LSB 0x97 /* @tprel(sym + add), data8 LSB */ +#define R_IA64_LTOFF_TPREL22 0x9a /* @ltoff(@tprel(s+a)), imm2 */ +#define R_IA64_DTPMOD64MSB 0xa6 /* @dtpmod(sym + add), data8 MSB */ +#define R_IA64_DTPMOD64LSB 0xa7 /* @dtpmod(sym + add), data8 LSB */ +#define R_IA64_LTOFF_DTPMOD22 0xaa /* @ltoff(@dtpmod(sym + add)), imm22 */ +#define R_IA64_DTPREL14 0xb1 /* @dtprel(sym + add), imm14 */ +#define R_IA64_DTPREL22 0xb2 /* @dtprel(sym + add), imm22 */ +#define R_IA64_DTPREL64I 0xb3 /* @dtprel(sym + add), imm64 */ +#define R_IA64_DTPREL32MSB 0xb4 /* @dtprel(sym + add), data4 MSB */ +#define R_IA64_DTPREL32LSB 0xb5 /* @dtprel(sym + add), data4 LSB */ +#define R_IA64_DTPREL64MSB 0xb6 /* @dtprel(sym + add), data8 MSB */ +#define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */ +#define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */ + +/* SH specific declarations */ + +/* SH relocs. */ +#define R_SH_NONE 0 +#define R_SH_DIR32 1 +#define R_SH_REL32 2 +#define R_SH_DIR8WPN 3 +#define R_SH_IND12W 4 +#define R_SH_DIR8WPL 5 +#define R_SH_DIR8WPZ 6 +#define R_SH_DIR8BP 7 +#define R_SH_DIR8W 8 +#define R_SH_DIR8L 9 +#define R_SH_SWITCH16 25 +#define R_SH_SWITCH32 26 +#define R_SH_USES 27 +#define R_SH_COUNT 28 +#define R_SH_ALIGN 29 +#define R_SH_CODE 30 +#define R_SH_DATA 31 +#define R_SH_LABEL 32 +#define R_SH_SWITCH8 33 +#define R_SH_GNU_VTINHERIT 34 +#define R_SH_GNU_VTENTRY 35 +#define R_SH_TLS_GD_32 144 +#define R_SH_TLS_LD_32 145 +#define R_SH_TLS_LDO_32 146 +#define R_SH_TLS_IE_32 147 +#define R_SH_TLS_LE_32 148 +#define R_SH_TLS_DTPMOD32 149 +#define R_SH_TLS_DTPOFF32 150 +#define R_SH_TLS_TPOFF32 151 +#define R_SH_GOT32 160 +#define R_SH_PLT32 161 +#define R_SH_COPY 162 +#define R_SH_GLOB_DAT 163 +#define R_SH_JMP_SLOT 164 +#define R_SH_RELATIVE 165 +#define R_SH_GOTOFF 166 +#define R_SH_GOTPC 167 +/* Keep this the last entry. */ +#define R_SH_NUM 256 + +/* Additional s390 relocs */ + +#define R_390_NONE 0 /* No reloc. */ +#define R_390_8 1 /* Direct 8 bit. */ +#define R_390_12 2 /* Direct 12 bit. */ +#define R_390_16 3 /* Direct 16 bit. */ +#define R_390_32 4 /* Direct 32 bit. */ +#define R_390_PC32 5 /* PC relative 32 bit. */ +#define R_390_GOT12 6 /* 12 bit GOT offset. */ +#define R_390_GOT32 7 /* 32 bit GOT offset. */ +#define R_390_PLT32 8 /* 32 bit PC relative PLT address. */ +#define R_390_COPY 9 /* Copy symbol at runtime. */ +#define R_390_GLOB_DAT 10 /* Create GOT entry. */ +#define R_390_JMP_SLOT 11 /* Create PLT entry. */ +#define R_390_RELATIVE 12 /* Adjust by program base. */ +#define R_390_GOTOFF32 13 /* 32 bit offset to GOT. */ +#define R_390_GOTPC 14 /* 32 bit PC relative offset to GOT. */ +#define R_390_GOT16 15 /* 16 bit GOT offset. */ +#define R_390_PC16 16 /* PC relative 16 bit. */ +#define R_390_PC16DBL 17 /* PC relative 16 bit shifted by 1. */ +#define R_390_PLT16DBL 18 /* 16 bit PC rel. PLT shifted by 1. */ +#define R_390_PC32DBL 19 /* PC relative 32 bit shifted by 1. */ +#define R_390_PLT32DBL 20 /* 32 bit PC rel. PLT shifted by 1. */ +#define R_390_GOTPCDBL 21 /* 32 bit PC rel. GOT shifted by 1. */ +#define R_390_64 22 /* Direct 64 bit. */ +#define R_390_PC64 23 /* PC relative 64 bit. */ +#define R_390_GOT64 24 /* 64 bit GOT offset. */ +#define R_390_PLT64 25 /* 64 bit PC relative PLT address. */ +#define R_390_GOTENT 26 /* 32 bit PC rel. to GOT entry >> 1. */ +#define R_390_GOTOFF16 27 /* 16 bit offset to GOT. */ +#define R_390_GOTOFF64 28 /* 64 bit offset to GOT. */ +#define R_390_GOTPLT12 29 /* 12 bit offset to jump slot. */ +#define R_390_GOTPLT16 30 /* 16 bit offset to jump slot. */ +#define R_390_GOTPLT32 31 /* 32 bit offset to jump slot. */ +#define R_390_GOTPLT64 32 /* 64 bit offset to jump slot. */ +#define R_390_GOTPLTENT 33 /* 32 bit rel. offset to jump slot. */ +#define R_390_PLTOFF16 34 /* 16 bit offset from GOT to PLT. */ +#define R_390_PLTOFF32 35 /* 32 bit offset from GOT to PLT. */ +#define R_390_PLTOFF64 36 /* 16 bit offset from GOT to PLT. */ +#define R_390_TLS_LOAD 37 /* Tag for load insn in TLS code. */ +#define R_390_TLS_GDCALL 38 /* Tag for function call in general + dynamic TLS code. */ +#define R_390_TLS_LDCALL 39 /* Tag for function call in local + dynamic TLS code. */ +#define R_390_TLS_GD32 40 /* Direct 32 bit for general dynamic + thread local data. */ +#define R_390_TLS_GD64 41 /* Direct 64 bit for general dynamic + thread local data. */ +#define R_390_TLS_GOTIE12 42 /* 12 bit GOT offset for static TLS + block offset. */ +#define R_390_TLS_GOTIE32 43 /* 32 bit GOT offset for static TLS + block offset. */ +#define R_390_TLS_GOTIE64 44 /* 64 bit GOT offset for static TLS + block offset. */ +#define R_390_TLS_LDM32 45 /* Direct 32 bit for local dynamic + thread local data in LE code. */ +#define R_390_TLS_LDM64 46 /* Direct 64 bit for local dynamic + thread local data in LE code. */ +#define R_390_TLS_IE32 47 /* 32 bit address of GOT entry for + negated static TLS block offset. */ +#define R_390_TLS_IE64 48 /* 64 bit address of GOT entry for + negated static TLS block offset. */ +#define R_390_TLS_IEENT 49 /* 32 bit rel. offset to GOT entry for + negated static TLS block offset. */ +#define R_390_TLS_LE32 50 /* 32 bit negated offset relative to + static TLS block. */ +#define R_390_TLS_LE64 51 /* 64 bit negated offset relative to + static TLS block. */ +#define R_390_TLS_LDO32 52 /* 32 bit offset relative to TLS + block. */ +#define R_390_TLS_LDO64 53 /* 64 bit offset relative to TLS + block. */ +#define R_390_TLS_DTPMOD 54 /* ID of module containing symbol. */ +#define R_390_TLS_DTPOFF 55 /* Offset in TLS block. */ +#define R_390_TLS_TPOFF 56 /* Negated offset in static TLS + block. */ +#define R_390_20 57 /* Direct 20 bit. */ +#define R_390_GOT20 58 /* 20 bit GOT offset. */ +#define R_390_GOTPLT20 59 /* 20 bit offset to jump slot. */ +#define R_390_TLS_GOTIE20 60 /* 20 bit GOT offset for static TLS + block offset. */ +/* Keep this the last entry. */ +#define R_390_NUM 61 + + +/* CRIS relocations. */ +#define R_CRIS_NONE 0 +#define R_CRIS_8 1 +#define R_CRIS_16 2 +#define R_CRIS_32 3 +#define R_CRIS_8_PCREL 4 +#define R_CRIS_16_PCREL 5 +#define R_CRIS_32_PCREL 6 +#define R_CRIS_GNU_VTINHERIT 7 +#define R_CRIS_GNU_VTENTRY 8 +#define R_CRIS_COPY 9 +#define R_CRIS_GLOB_DAT 10 +#define R_CRIS_JUMP_SLOT 11 +#define R_CRIS_RELATIVE 12 +#define R_CRIS_16_GOT 13 +#define R_CRIS_32_GOT 14 +#define R_CRIS_16_GOTPLT 15 +#define R_CRIS_32_GOTPLT 16 +#define R_CRIS_32_GOTREL 17 +#define R_CRIS_32_PLT_GOTREL 18 +#define R_CRIS_32_PLT_PCREL 19 + +#define R_CRIS_NUM 20 + + +/* AMD x86-64 relocations. */ +#define R_X86_64_NONE 0 /* No reloc */ +#define R_X86_64_64 1 /* Direct 64 bit */ +#define R_X86_64_PC32 2 /* PC relative 32 bit signed */ +#define R_X86_64_GOT32 3 /* 32 bit GOT entry */ +#define R_X86_64_PLT32 4 /* 32 bit PLT address */ +#define R_X86_64_COPY 5 /* Copy symbol at runtime */ +#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */ +#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */ +#define R_X86_64_RELATIVE 8 /* Adjust by program base */ +#define R_X86_64_GOTPCREL 9 /* 32 bit signed PC relative + offset to GOT */ +#define R_X86_64_32 10 /* Direct 32 bit zero extended */ +#define R_X86_64_32S 11 /* Direct 32 bit sign extended */ +#define R_X86_64_16 12 /* Direct 16 bit zero extended */ +#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */ +#define R_X86_64_8 14 /* Direct 8 bit sign extended */ +#define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */ +#define R_X86_64_DTPMOD64 16 /* ID of module containing symbol */ +#define R_X86_64_DTPOFF64 17 /* Offset in module's TLS block */ +#define R_X86_64_TPOFF64 18 /* Offset in initial TLS block */ +#define R_X86_64_TLSGD 19 /* 32 bit signed PC relative offset + to two GOT entries for GD symbol */ +#define R_X86_64_TLSLD 20 /* 32 bit signed PC relative offset + to two GOT entries for LD symbol */ +#define R_X86_64_DTPOFF32 21 /* Offset in TLS block */ +#define R_X86_64_GOTTPOFF 22 /* 32 bit signed PC relative offset + to GOT entry for IE symbol */ +#define R_X86_64_TPOFF32 23 /* Offset in initial TLS block */ + +#define R_X86_64_NUM 24 + + +/* AM33 relocations. */ +#define R_MN10300_NONE 0 /* No reloc. */ +#define R_MN10300_32 1 /* Direct 32 bit. */ +#define R_MN10300_16 2 /* Direct 16 bit. */ +#define R_MN10300_8 3 /* Direct 8 bit. */ +#define R_MN10300_PCREL32 4 /* PC-relative 32-bit. */ +#define R_MN10300_PCREL16 5 /* PC-relative 16-bit signed. */ +#define R_MN10300_PCREL8 6 /* PC-relative 8-bit signed. */ +#define R_MN10300_GNU_VTINHERIT 7 /* Ancient C++ vtable garbage... */ +#define R_MN10300_GNU_VTENTRY 8 /* ... collection annotation. */ +#define R_MN10300_24 9 /* Direct 24 bit. */ +#define R_MN10300_GOTPC32 10 /* 32-bit PCrel offset to GOT. */ +#define R_MN10300_GOTPC16 11 /* 16-bit PCrel offset to GOT. */ +#define R_MN10300_GOTOFF32 12 /* 32-bit offset from GOT. */ +#define R_MN10300_GOTOFF24 13 /* 24-bit offset from GOT. */ +#define R_MN10300_GOTOFF16 14 /* 16-bit offset from GOT. */ +#define R_MN10300_PLT32 15 /* 32-bit PCrel to PLT entry. */ +#define R_MN10300_PLT16 16 /* 16-bit PCrel to PLT entry. */ +#define R_MN10300_GOT32 17 /* 32-bit offset to GOT entry. */ +#define R_MN10300_GOT24 18 /* 24-bit offset to GOT entry. */ +#define R_MN10300_GOT16 19 /* 16-bit offset to GOT entry. */ +#define R_MN10300_COPY 20 /* Copy symbol at runtime. */ +#define R_MN10300_GLOB_DAT 21 /* Create GOT entry. */ +#define R_MN10300_JMP_SLOT 22 /* Create PLT entry. */ +#define R_MN10300_RELATIVE 23 /* Adjust by program base. */ + +#define R_MN10300_NUM 24 + + +/* M32R relocs. */ +#define R_M32R_NONE 0 /* No reloc. */ +#define R_M32R_16 1 /* Direct 16 bit. */ +#define R_M32R_32 2 /* Direct 32 bit. */ +#define R_M32R_24 3 /* Direct 24 bit. */ +#define R_M32R_10_PCREL 4 /* PC relative 10 bit shifted. */ +#define R_M32R_18_PCREL 5 /* PC relative 18 bit shifted. */ +#define R_M32R_26_PCREL 6 /* PC relative 26 bit shifted. */ +#define R_M32R_HI16_ULO 7 /* High 16 bit with unsigned low. */ +#define R_M32R_HI16_SLO 8 /* High 16 bit with signed low. */ +#define R_M32R_LO16 9 /* Low 16 bit. */ +#define R_M32R_SDA16 10 /* 16 bit offset in SDA. */ +#define R_M32R_GNU_VTINHERIT 11 +#define R_M32R_GNU_VTENTRY 12 +/* M32R relocs use SHT_RELA. */ +#define R_M32R_16_RELA 33 /* Direct 16 bit. */ +#define R_M32R_32_RELA 34 /* Direct 32 bit. */ +#define R_M32R_24_RELA 35 /* Direct 24 bit. */ +#define R_M32R_10_PCREL_RELA 36 /* PC relative 10 bit shifted. */ +#define R_M32R_18_PCREL_RELA 37 /* PC relative 18 bit shifted. */ +#define R_M32R_26_PCREL_RELA 38 /* PC relative 26 bit shifted. */ +#define R_M32R_HI16_ULO_RELA 39 /* High 16 bit with unsigned low */ +#define R_M32R_HI16_SLO_RELA 40 /* High 16 bit with signed low */ +#define R_M32R_LO16_RELA 41 /* Low 16 bit */ +#define R_M32R_SDA16_RELA 42 /* 16 bit offset in SDA */ +#define R_M32R_RELA_GNU_VTINHERIT 43 +#define R_M32R_RELA_GNU_VTENTRY 44 +#define R_M32R_REL32 45 /* PC relative 32 bit. */ + +#define R_M32R_GOT24 48 /* 24 bit GOT entry */ +#define R_M32R_26_PLTREL 49 /* 26 bit PC relative to PLT shifted */ +#define R_M32R_COPY 50 /* Copy symbol at runtime */ +#define R_M32R_GLOB_DAT 51 /* Create GOT entry */ +#define R_M32R_JMP_SLOT 52 /* Create PLT entry */ +#define R_M32R_RELATIVE 53 /* Adjust by program base */ +#define R_M32R_GOTOFF 54 /* 24 bit offset to GOT */ +#define R_M32R_GOTPC24 55 /* 24 bit PC relative offset to GOT */ +#define R_M32R_GOT16_HI_ULO 56 /* High 16 bit GOT entry with unsigned + low */ +#define R_M32R_GOT16_HI_SLO 57 /* High 16 bit GOT entry with signed + low */ +#define R_M32R_GOT16_LO 58 /* Low 16 bit GOT entry */ +#define R_M32R_GOTPC_HI_ULO 59 /* High 16 bit PC relative offset to + GOT with unsigned low */ +#define R_M32R_GOTPC_HI_SLO 60 /* High 16 bit PC relative offset to + GOT with signed low */ +#define R_M32R_GOTPC_LO 61 /* Low 16 bit PC relative offset to + GOT */ +#define R_M32R_GOTOFF_HI_ULO 62 /* High 16 bit offset to GOT + with unsigned low */ +#define R_M32R_GOTOFF_HI_SLO 63 /* High 16 bit offset to GOT + with signed low */ +#define R_M32R_GOTOFF_LO 64 /* Low 16 bit offset to GOT */ +#define R_M32R_NUM 256 /* Keep this the last entry. */ + +#endif /* elf.h */ + +// Local Variables: +// tab-width: 4 +// c-basic-offset: 4 +// c-file-offsets:((innamespace . 0)(inline-open . 0)) +// indent-tabs-mode: nil +// End: + +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: /branches/fault_tolerance/softs/tsar_boot/include/io.h =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/include/io.h (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/include/io.h (revision 724) @@ -0,0 +1,126 @@ +/********************************************************************** + * \file io.h + * \date 5 September 2012 + * \author Cesar Fuguet / Alain Greiner + * + * Utility functions to write or read memory mapped hardware registers + *********************************************************************/ + +#ifndef IO_H +#define IO_H + +#include + +/********************************************************************** + * Read an 32 bits memory mapped hardware register + * with physical address extension to access cluster_io + *********************************************************************/ +static inline unsigned int ioread32(void * addr) +{ + unsigned int value; + unsigned int ext = CLUSTER_IO; + + asm volatile( + "mtc2 %2, $24 \n" /* PADDR_EXT <= cluster_io */ + "lw %0, 0(%1) \n" /* value <= *(ext\addr) */ + "mtc2 $0, $24 \n" /* PADDR_EXT <= 0 */ + : "=r" (value) + : "r" (addr), "r" (ext) + : "memory" ); + + return (volatile unsigned int)value; +} + +/********************************************************************** + * Read an 16 bits memory mapped hardware register + *********************************************************************/ +static inline unsigned short ioread16(void * addr) +{ + unsigned short value; + unsigned int ext = CLUSTER_IO; + + asm volatile( + "mtc2 %2, $24 \n" /* PADDR_EXT <= cluster_io */ + "lhu %0, 0(%1) \n" /* value <= *(ext\addr) */ + "mtc2 $0, $24 \n" /* PADDR_EXT <= 0 */ + : "=r" (value) + : "r" (addr), "r" (ext) + : "memory" ); + + return (volatile unsigned short)value; +} + +/********************************************************************** + * Read an 8 bits memory mapped hardware register + *********************************************************************/ +static inline unsigned char ioread8(void * addr) +{ + unsigned char value; + unsigned int ext = CLUSTER_IO; + + asm volatile( + "mtc2 %2, $24 \n" /* PADDR_EXT <= cluster_io */ + "lbu %0, 0(%1) \n" /* value <= *(ext\addr) */ + "mtc2 $0, $24 \n" /* PADDR_EXT <= 0 */ + : "=r" (value) + : "r" (addr), "r" (ext) + : "memory" ); + + return (volatile unsigned char)value; +} + +/********************************************************************** + * Write an 32 bits memory mapped hardware register + * with physical address extension to access cluster_io + *********************************************************************/ +static inline void iowrite32(void * addr, unsigned int value) +{ + unsigned int ext = CLUSTER_IO; + + asm volatile( + "mtc2 %2, $24 \n" /* PADDR_EXT <= cluster_io */ + "sw %0, 0(%1) \n" /* *(ext\addr) <= value */ + "mtc2 $0, $24 \n" /* PADDR_EXT <= 0 */ + "sync \n" /* sync barrier */ + : + : "r" (value), "r" (addr), "r" (ext) + : "memory" ); +} + +/********************************************************************** + * Write an 16 bits memory mapped hardware register + *********************************************************************/ +static inline void iowrite16(void * addr, unsigned short value) +{ + unsigned int ext = CLUSTER_IO; + + asm volatile( + "mtc2 %2, $24 \n" /* PADDR_EXT <= cluster_io */ + "sh %0, 0(%1) \n" /* *(ext\addr) <= value */ + "mtc2 $0, $24 \n" /* PADDR_EXT <= 0 */ + "sync \n" /* sync barrier */ + : + : "r" (value), "r" (addr), "r" (ext) + : "memory" ); +} + +/********************************************************************** + * Write an 8 bits memory mapped hardware register + *********************************************************************/ +static inline void iowrite8(void * addr, unsigned char value) +{ + unsigned int ext = CLUSTER_IO; + + asm volatile( + "mtc2 %2, $24 \n" /* PADDR_EXT <= cluster_io */ + "sb %0, 0(%1) \n" /* *(ext\addr) <= value */ + "mtc2 $0, $24 \n" /* PADDR_EXT <= 0 */ + "sync \n" /* sync barrier */ + : + : "r" (value), "r" (addr), "r" (ext) + : "memory" ); +} + +#endif + +// vim: tabstop=4 : softtabstop=4 : shiftwidth=4 : expandtab Index: /branches/fault_tolerance/softs/tsar_boot/include/mcc.h =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/include/mcc.h (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/include/mcc.h (revision 724) @@ -0,0 +1,30 @@ +#ifndef MCC_H +#define MCC_H + +enum MccRegisters +{ + MCC_LOCK = 0, + MCC_ADDR_LO = 1, + MCC_ADDR_HI = 2, + MCC_LENGTH = 3, + MCC_CMD = 4 +}; + +enum MccConfigCmd +{ + MCC_CMD_NOP = 0, + MCC_CMD_INVAL = 1, + MCC_CMD_SYNC = 2 +}; + +#endif + +// Local Variables: +// tab-width: 4; +// c-basic-offset: 4; +// c-file-offsets:((innamespace . 0)(inline-open . 0)); +// indent-tabs-mode: nil; +// End: +// +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: /branches/fault_tolerance/softs/tsar_boot/include/mips32_registers.h =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/include/mips32_registers.h (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/include/mips32_registers.h (revision 724) @@ -0,0 +1,82 @@ +/********************************************************************************/ +/* File : mips32_registers.h */ +/* Author : Alain Greiner */ +/* Date : 26/03/2012 */ +/* Modified by : Cesar Fuguet 10/02/2013 */ +/********************************************************************************/ +/* We define mnemonics for MIPS32 registers */ +/********************************************************************************/ + +#ifndef _MIPS32_REGISTERS_H +#define _MIPS32_REGISTERS_H + +/* processor registers */ + +#define zero $0 +#define at $at +#define v0 $2 +#define v1 $3 +#define a0 $4 +#define a1 $5 +#define a2 $6 +#define a3 $7 +#define t0 $8 +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 +#define s0 $16 +#define s1 $17 +#define s2 $18 +#define s3 $19 +#define s4 $20 +#define s5 $21 +#define s6 $22 +#define s7 $23 +#define t8 $24 +#define t9 $25 +#define k0 $26 +#define k1 $27 +#define gp $28 +#define sp $29 +#define fp $30 +#define ra $31 + +/* CP0 registers */ + +#define CP0_COUNT $9 +#define CP0_STATUS $12,0 +#define CP0_CAUSE $13,0 +#define CP0_EPC $14,0 +#define CP0_EBASE $15,1 +#define CP0_PROCID $15,1 + +/* CP2 registers */ + +#define CP2_PTPR $0 +#define CP2_MODE $1 +#define CP2_ICACHE_FLUSH $2 +#define CP2_DCACHE_FLUSH $3 +#define CP2_ITLB_INVAL $4 +#define CP2_DTLB_INVAL $5 +#define CP2_ICACHE_INVAL $6 +#define CP2_DCACHE_INVAL $7 +#define CP2_ICACHE_PREFETCH $8 +#define CP2_DCACHE_PREFETCH $9 +#define CP2_SYNC $10 +#define CP2_IETR $11 +#define CP2_DETR $12 +#define CP2_IBVAR $13 +#define CP2_DBVAR $14 +#define CP2_PARAMS $15 +#define CP2_RELEASE $16 +#define CP2_DATA_LO $17 +#define CP2_DATA_HI $18 +#define CP2_ICACHE_INVAL_PA $19 +#define CP2_DCACHE_INVAL_PA $20 +#define CP2_PADDR_EXT $24 + +#endif Index: /branches/fault_tolerance/softs/tsar_boot/include/reset_ioc.h =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/include/reset_ioc.h (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/include/reset_ioc.h (revision 724) @@ -0,0 +1,31 @@ +#ifndef RESET_IOC_H +#define RESET_IOC_H + +#if USE_SPI +#include +#include +#endif /* USE_SPI */ + +#if USE_BDV +#include +#include +#endif /* USE_BDV */ + +#include +#include +#include +#include + +#if USE_SPI +extern int reset_ioc_init(); +#endif /* USE_SPI */ + +extern int reset_ioc_read( unsigned int lba, + void* buffer, + unsigned int count ); + +#endif /* RESET_IOC_H */ + +/* + * vim: tabstop=4 : shiftwidth=4 : expandtab + */ Index: /branches/fault_tolerance/softs/tsar_boot/include/reset_tty.h =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/include/reset_tty.h (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/include/reset_tty.h (revision 724) @@ -0,0 +1,13 @@ +#ifndef RESET_TTY_H +#define RESET_TTY_H + +# include + +void reset_exit(); +int reset_getc(char * c); +void reset_putc(const char c); +void reset_puts(const char *buffer); +void reset_putx(unsigned int val); +void reset_putd(unsigned int val); + +#endif Index: /branches/fault_tolerance/softs/tsar_boot/include/reset_utils.h =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/include/reset_utils.h (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/include/reset_utils.h (revision 724) @@ -0,0 +1,59 @@ +/* + * \file : reset_utils.h + * \date : August 2012 + * \author : Cesar Fuguet + */ + +#ifndef BOOT_UTILS_H +#define BOOT_UTILS_H + +#include +#include +#include +#include +#include +#include + +/******************************************************************** + * Integer types definition + ********************************************************************/ +typedef unsigned int size_t; +typedef unsigned int addr_t; + +/******************************************************************** + * Other types definition + ********************************************************************/ + +/* + * cache line aligned disk block (sector) buffer + */ +struct aligned_blk +{ + char b[BLOCK_SIZE]; +} __attribute__((aligned(CACHE_LINE_SIZE))); + +/******************************************************************** + * Utility functions definition + ********************************************************************/ + +extern unsigned int proctime(); + +extern int pread(size_t file_offset, void *buf, size_t nbyte, size_t offset); + +extern void* memcpy(void *_dst, const void *_src, size_t n); +extern void* memset(void *_dst, int c, size_t len); + +extern void check_elf_header(Elf32_Ehdr *ehdr); +extern void reset_print_elf_phdr(Elf32_Phdr * elf_phdr_ptr); + +#if USE_IOB +void reset_mcc_invalidate (const void * buf, size_t size); +#endif /* USE_IOB */ + +#if (CACHE_COHERENCE == 0) || USE_IOB +void reset_buf_invalidate (const void * buf, size_t line_size, size_t size); +#endif /* (CACHE_COHERENCE == 0) || USE_IOB */ +#endif /* BOOT_UTILS_H */ + +// vim: tabstop=4 : softtabstop=4 : shiftwidth=4 : expandtab + Index: /branches/fault_tolerance/softs/tsar_boot/include/sdcard.h =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/include/sdcard.h (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/include/sdcard.h (revision 724) @@ -0,0 +1,172 @@ +/** + * \file sdcard.h + * \date 30 August 2012 + * \author Cesar fuguet + * + * This file defines the driver of a SD Card device using an SPI controller + */ + +#ifndef SDCARD_H +#define SDCARD_H + +#include + +/** + * \brief SD Card type definition + */ +struct sdcard_dev +{ + /** + * SPI controller pointer + */ + struct spi_dev * spi; + + /** + * Block length of the SDCARD + */ + unsigned int block_length; + + /** + * Access pointer representing the offset in bytes used + * to read or write in the SDCARD. + * + * \note this driver is for cards SDSD, therefore this offset + * must be multiple of the block length + */ + unsigned int access_pointer; + + /** + * Slave ID. This ID represents the number of the slave select signal + * used in the hardware platform + */ + int slave_id; + + /* is the card high capacity ? */ + int sdhc; +}; + +/** + * \param sdcard : uninitialized pointer. This parameter will contain + * a pointer to the initialized block device or NULL otherwise + * \param spi : initialized pointer to the spi controller + * \param ss : slave select signal number + * + * \return 0 when initialization succeeds or an error code value otherwise. + * The error codes are defined in this header file. + * + * \brief Initialize the block device + */ +int sdcard_dev_open(struct sdcard_dev * sdcard, struct spi_dev * spi, int ss); + +/** + * \param sdcard : Pointer to the initialized block device + * \param buf : Pointer to a memory segment wherein store + * \param count : number of bytes to read + * + * \return 0 when read succeeds or an error code value otherwise. + * The error codes are defined in this header file. + * + * \brief Read in the block device + * + * The read is made in the current block device access pointer. + * In the read succeeds, the block device access pointer is + * relocated to the next block. + */ +int sdcard_dev_read(struct sdcard_dev * sdcard, void * buf, unsigned int count); + +/** + * \param sdcard : Pointer to the initialized block device + * \param buf : Pointer to a memory segment wherein the + * \param count : number of blocks to write + * + * \return 0 when write succeeds or an error code value otherwise. + * The error codes are defined in this header file. + * + * \brief Write in the block device + * + * The write is made in the current block device access pointer. + * In the write succeeds, the block device access pointer is + * relocated to the next block. + */ +unsigned int sdcard_dev_write(struct sdcard_dev * sdcard, void * buf, unsigned int count); + +/** + * \param sdcard : Pointer to the initialized block device + * \param pos : Position where the block device access + * pointer must be move + * + * \return void + * + * \brief Change block device access pointer position + * + * The block device access pointer is relocated in terms of blocks + */ +void sdcard_dev_lseek(struct sdcard_dev * sdcard, unsigned int pos); + +/** + * \param sdcard : Pointer to the initialized block device + * \param len : Block device length to set + * + * \return 0 when succeed or error code value otherwise + * + * \brief Set the block length of the device + */ +int sdcard_dev_set_blocklen(struct sdcard_dev * sdcard, unsigned int len); + +/** + * SD Card constants + */ + +/** Number of retries after an unacknowledge command */ +#define SDCARD_COMMAND_TIMEOUT 100 + +/** This command is a simple SD commmand */ +#define SDCARD_CMD 0 + +/** This is an application specific command */ +#define SDCARD_ACMD 1 + +/** The transmition is done in the negative edge of the clock */ +#define SDCARD_TX_NEGEDGE 0 + +/** The transmition is done in the positive edge of the clock */ +#define SDCARD_TX_POSEDGE 1 + +/** The reception is done in the negative edge of the clock */ +#define SDCARD_RX_NEGEDGE 0 + +/** The reception is done in the positive edge of the clock */ +#define SDCARD_RX_POSEDGE 1 + +/** + * SD Card macros + */ + +/** Check if the response is valid */ +#define SDCARD_CHECK_R1_VALID(x) (~x & SDCARD_R1_RSP_VALID) ? 1 : 0 + +/** + * Check if there is an error in the response + * + * \note this macro must be used after verify that the response is + * valid + */ +#define SDCARD_CHECK_R1_ERROR(x) ( x & 0x7E) ? 1 : 0 + +/** + * SD Card Response 1 (R1) format constants + */ +#define SDCARD_R1_IN_IDLE_STATE ( 1 << 0 ) /**< \brief R1 bit 0 */ +#define SDCARD_R1_ERASE_RESET ( 1 << 1 ) /**< \brief R1 bit 1 */ +#define SDCARD_R1_ILLEGAL_CMD ( 1 << 2 ) /**< \brief R1 bit 2 */ +#define SDCARD_R1_COM_CRC_ERR ( 1 << 3 ) /**< \brief R1 bit 3 */ +#define SDCARD_R1_ERASE_SEQ_ERR ( 1 << 4 ) /**< \brief R1 bit 4 */ +#define SDCARD_R1_ADDRESS_ERR ( 1 << 5 ) /**< \brief R1 bit 5 */ +#define SDCARD_R1_PARAMETER_ERR ( 1 << 6 ) /**< \brief R1 bit 6 */ +#define SDCARD_R1_RSP_VALID ( 1 << 7 ) /**< \brief R1 bit 7 */ + +#endif + +/* + * vim: tabstop=4 : shiftwidth=4 : expandtab : softtabstop=4 + */ Index: /branches/fault_tolerance/softs/tsar_boot/include/spi.h =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/include/spi.h (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/include/spi.h (revision 724) @@ -0,0 +1,154 @@ +/** + * \file : spi.h + * \date : 30 August 2012 + * \author: Cesar Fuguet + * + * This file contains the definition of a driver for the SPI controller + */ + +#ifndef SPI_H +#define SPI_H + +#include + +/** + * SPI type definition + */ +struct spi_dev +{ + /** + * RX/TX registers of the SPI controller + */ + unsigned int rx_tx[4]; + + /** + * Control register of the SPI controller + */ + unsigned int ctrl; + + /** + * Divider register for the SPI controller generated clock signal + */ + unsigned int divider; + + /** + * Slave select register of the SPI controller + */ + unsigned int ss; + unsigned int dma_base; + unsigned int dma_baseh; + unsigned int dma_count; +}; + +/** + * \param spi : initialized pointer to a SPI controller. + * \param byte : Byte to send to the SPI controller + * \param index : index of the TX register in the SPI (TX[index]) + * + * \return void + * + * \brief Send a byte to one of the tx buffer registers of the + * SPI controller + */ +void spi_put_tx(struct spi_dev * spi, unsigned char byte, int index); + +/** + * \param spi : initialized pointer to a SPI controller. + * \param index : index of the RX register in the SPI (RX[index]) + * + * \return byte from the RX[index] register + * + * \brief Get a byte from one of the rx buffer registers of the + * SPI controller + */ +inline volatile unsigned char spi_get_rx(struct spi_dev * spi, int index); + +/** + * \param spi : initialized pointer to a SPI controller. + * \param buf : buffer to store data read + * \param count : byte count to read + * + * \return void + * + * \brief get a data block from the SPI controller using 128bits + * reads if possible + */ +void spi_get_data(struct spi_dev * spi, void *buf, unsigned int count); + +/** + * \param spi : initialized pointer to a SPI controller. + * \param index : index of the slave select signal to assert + * + * \return void + * + * \brief Set the index selected slave select signal (ss[index] <= '0') + */ +inline void spi_ss_assert(struct spi_dev * spi, int index); + +/** + * \param spi : initialized pointer to a SPI controller. + * \param index : index of the slave select signal to deassert + * + * \return void + * + * \brief Unset the index selected slave select signal (ss[index] <= '0') + */ +inline void spi_ss_deassert(struct spi_dev * spi, int index); + +/** + * \param spi : initialized pointer to a SPI controller. + * \param spi_freq : SPI Master to Slave clock frequency (in Hz) + * \param sys_freq : System clock frequency (in Hz) + * \param char_len : number to bits to transmit in one transfer + * \param tx_edge : when 0, the Master Out Slave In signal is changed + * on the falling edge of the clock + * \param rx_edge : when 0, the Master In Slave Out signal is latched + * on the falling edge of the clock + * + * \return void + * + * \brief Configure the SPI controller + * \note Any of the arguments can be less than 0 if you want to keep the old value + */ +void spi_dev_config ( + struct spi_dev * spi, + int spi_freq , + int sys_freq , + int char_len , + int tx_edge , + int rx_edge ); + +/** + * SPI macros and constants + */ +#define SPI_TX_POSEDGE 1 /**< MOSI is changed on neg edge */ +#define SPI_TX_NEGEDGE 0 /**< MOSI is changed on pos edge */ +#define SPI_RX_POSEDGE 1 /**< MISO is latched on pos edge */ +#define SPI_RX_NEGEDGE 0 /**< MISO is latched on neg edge */ + +#define SPI_CTRL_ASS_EN ( 1 << 13 ) /**< Auto Slave Sel Assertion */ +#define SPI_CTRL_IE_EN ( 1 << 12 ) /**< Interrupt Enable */ +#define SPI_CTRL_LSB_EN ( 1 << 11 ) /**< LSB are sent first */ +#define SPI_CTRL_TXN_EN ( 1 << 10 ) /**< MOSI is changed on neg edge */ +#define SPI_CTRL_RXN_EN ( 1 << 9 ) /**< MISO is latched on neg edge */ +#define SPI_CTRL_GO_BSY ( 1 << 8 ) /**< Start the transfer */ +#define SPI_CTRL_DMA_BSY (1 << 16) /*** DMA in progress */ +#define SPI_CTRL_CHAR_LEN_MASK ( 0xFF ) /**< Bits transmited in 1 transfer */ +#define SPI_RXTX_MASK ( 0xFF ) /**< Mask for the an RX/TX value */ + +#define SPI_DMA_COUNT_READ (1 << 0) /* operation is a read (else write) */ + +/** + * \param x : Initialized pointer to the SPI controller + * + * \return 1 if there is an unfinished transfer in the SPI controller + * + * \brief Check the GO_BUSY bit of the SPI Controller + */ +#define SPI_IS_BUSY(x) ((ioread32(&x->ctrl) & (SPI_CTRL_GO_BSY|SPI_CTRL_DMA_BSY)) != 0) ? 1 : 0 + +#endif + +/* + * vim: tabstop=4 : shiftwidth=4 : expandtab : softtabstop=4 + */ Index: /branches/fault_tolerance/softs/tsar_boot/include/tty.h =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/include/tty.h (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/include/tty.h (revision 724) @@ -0,0 +1,23 @@ +#ifndef TTY_REGS_H +#define TTY_REGS_H + +enum SoclibTtyRegisters { + TTY_WRITE = 0, + TTY_STATUS = 1, + TTY_READ = 2, + TTY_CONFIG = 3, + /**/ + TTY_SPAN = 4, +}; + +#endif + +// Local Variables: +// tab-width: 4; +// c-basic-offset: 4; +// c-file-offsets:((innamespace . 0)(inline-open . 0)); +// indent-tabs-mode: nil; +// End: +// +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 + Index: /branches/fault_tolerance/softs/tsar_boot/src/reset.S =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/src/reset.S (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/src/reset.S (revision 724) @@ -0,0 +1,244 @@ +/* + * \file : reset.S + * \date : 01/12/2012 + * \author: Cesar FUGUET & Manuel BOUYER & Alain Greiner + * + * This is a generic reset code for a generic multi-clusters / multi-processors + * TSAR architecture (up to 256 clusters / up to 4 processors per cluster). + * + * There is one XICU, one TTY, one DMA, and one memory bank per cluster. + * + * This preloader uses a stack segment allocated in cluster 0, defined + * by the seg_reset_stack_base parameters in ldscript, of size 0x10000 (64k) + * - Processor 0 uses a larger stack: 64 Kbytes. + * - Other processors use a smaller stack: 256 bytes. + * => the seg_stack_size cannot be smaller than 0x50000 bytes (320 Kytes). + * (64K + 1024 * 256 = 320 Kbytes) + * Those stacks can be used by both the preloader and the boot-loader code. + * + * The replicated XICU is used to awake the sleeping processors: + * xicu_paddr_base = ICU_PADDR_BASE + (cluster_xy << 32) + * + * It is intended to be used with various operating systems or nano kernels, + * including NetBSD, ALMOS, and GIET_VM. + * + * - Each processor initializes its Status Register (SR) to disable interrupts. + * - Each processor initializes its Count Register. + * - Each processor initialises its private XICU WTI mask register. + * - Each processor initializes its Stack Pointer. + * - Only processor 0 executes the reset_load_elf function to load into memory + * the system specific boot-loader stored on disk at BOOT_LOADER_LBA + * - All other processors wait in a low power consumption mode that the + * processor 0 wakes them using an IPI (Inter Processor Interruption) + */ + + #include + #include + + /* These define should be consistent with values defined in map.xml file */ + + .extern seg_reset_stack_base + + .section .reset,"ax",@progbits + + .extern dtb_addr + .extern reset_putc + .extern reset_getc + .extern reset_ioc_read + .extern reset_elf_loader + .extern memcpy + .extern reset_puts + .extern reset_putx + .extern reset_putd + .extern reset_ioc_init + .extern versionstr + + .globl reset /* Makes reset an external symbol */ + .ent reset + + .align 2 + .set noreorder + +reset: + b _reset /* 0xbfc0000 */ + nop /* 0xbfc0004 */ + + /* Addresses of the functions provided by this reset code */ + +preloader_vector: + .word RESET_VERSION /* 0xbfc0008 */ + .word dtb_addr /* 0xbfc000c */ + .word reset_putc /* 0xbfc0010 */ + .word reset_getc /* 0xbfc0014 */ + .word reset_ioc_read /* 0xbfc0018 */ + .word reset_elf_loader /* 0xbfc001C */ + .word memcpy /* 0xbfc0020 */ + .word reset_puts /* 0xbfc0024 */ + .word reset_putx /* 0xbfc0028 */ + .word reset_putd /* 0xbfc002C */ + +_reset: + + /* All processors Disable interruptions, keep STATUSbev enabled */ + + li k0, (1 << 22) + mtc0 k0, CP0_STATUS + + /* All processors compute proc_id, lpid, cluster_xy */ + + mfc0 k0, CP0_EBASE + andi t0, k0, 0x3FF /* t0 <= proc_id (at most 1024 processors) */ + + move t3, t0 + + la k0, NB_PROCS /* k0 <= number of processors per cluster */ + divu t3, k0 + mfhi t1 /* t1 <= lpid = proc_id % NB_PROCS */ + mflo t2 /* t2 <= cluster_xy = proc_id / NB_PROCS */ + + /* All processors initialise the count register in CP0 */ + + mtc0 zero, CP0_COUNT + + /* + * All processors enable the WTI for XICU + * Each processor may have IRQ_PER_PROC irq outputs from the XICU + * In each cluster, the XICU base address depends on the cluster_xy + */ + + la t3, ICU_PADDR_BASE /* t3 <= ICU base address */ + move t4, t1 /* t4 <= local_id */ + li t5, IRQ_PER_PROC /* t5 <= IRQ_PER_PROC */ + multu t4, t5 + mflo t6 /* t6 <= IRQ_PER_PROC * local_id */ + sll t4, t6, 2 /* t4 <= OUT_INDEX = t6 * 4 */ + + li t5, (0xC << 7) /* t5 <= FUNC = XICU_MSK_WTI */ + or t4, t4, t5 /* t4 <= FUNC | INDEX | 00 */ + or t5, t3, t4 /* t5 <= &XICU[MSK_WTI][OUT_INDEX] */ + + /* All processors set WTI mask using the physical address extension */ + + li t4, 1 + sllv t4, t4, t1 /* Set XICU[MSK_WTI][INDEX][local_id] */ + + mtc2 t2, CP2_PADDR_EXT /* set PADDR extension */ + sw t4, 0(t5) /* XICU[MSK_WTI][INDEX] <= t4 */ + mtc2 zero, CP2_PADDR_EXT /* reset PADDR extension */ + + /* All processors initializes stack pointer, depending on proc_id */ + + la k0, seg_reset_stack_base + li k1, 0x10000 /* k1 <= P0 stack size == 64 Kbytes */ + addu sp, k0, k1 /* P0 stack from base to (base + 64K) */ + + li k1, 0x200 /* k1 <= Pi stack size == 512 bytes */ + multu k1, t0 + mflo k0 /* k0 <= 256 * proc_id */ + addu sp, sp, k1 + addu sp, sp, k0 /* Pi stacks from base + 64K + proc_id*256 */ + + /* + * Only processor 0 in cluster 0 loads and executes the boot-loader + * We have: + * t0: global proc_id + * t1: local proc_id + * t2: cluster_xy + * t3: xicu physical base address in cluster 0 + */ + + bne zero, t0, _reset_wait + nop + + /* Processor 0 displays version for this reset code */ + + la a0, versionstr + la k0, reset_puts + jalr k0 + nop + + +#if USE_SPI + + /* Processor 0 Initialize the SPI controller */ + + la k0, reset_ioc_init + jalr k0 + nop + +#endif + + /* + * Processor 0 jumps to the reset_elf_loader routine + * Passing as argument the block number in which is loaded the .elf file + */ + + la k0, reset_elf_loader + li a0, BOOT_LOADER_LBA + jalr k0 + nop + + /* + * Processor O jumps to the entry address defined in the .elf file, + * and returned by reset_elf_loader function. + * First argument is pointer to the preloader function vectors + * other function arguments are 0 + */ + + la a0, preloader_vector + move a1, zero + move a2, zero + move a3, zero + jr v0 + nop + + /* + * All processor (but processor 0) wait in low power mode + * until processor 0 wakes them using an IPI. + * We have: + * t0: global id + * t1: local id + * t2: cluster id + * t3: xicu physical base address in cluster 0 + */ + +_reset_wait: + + sll t4, t1, 2 /* t4 <= local_id * 4 */ + addu t5, t4, t3 /* t5 <= &XICU[WTI_REG][local_id] */ + + wait + + /* + * All other processors, when exiting wait mode, + * read from XICU the address to jump. + * This address is the boot-loader entry address that has been + * written in the mailbox by the IPI sent by processor 0 + */ + + mtc2 t2, CP2_PADDR_EXT /* set PADDR extension */ + lw k0, 0(t5) /* k0 <= XICU[WTI_REG][local_id] */ + mtc2 zero, CP2_PADDR_EXT /* reset PADDR extension */ + + jr k0 + nop + +/* Exception entry point */ + +.org 0x0380 +_excep: + mfc0 a0, CP0_STATUS /* first arg is status */ + mfc0 a1, CP0_CAUSE /* second arg is cause */ + mfc0 a2, CP0_EPC /* third argc is epc */ + mfc2 a3, CP2_DBVAR /* fourth argc is dbvar */ + nop + j handle_except + nop + + .end reset + + .set reorder + +/* + * vim: tabstop=4 : shiftwidth=4 : expandtab + */ Index: /branches/fault_tolerance/softs/tsar_boot/src/reset_elf_loader.c =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/src/reset_elf_loader.c (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/src/reset_elf_loader.c (revision 724) @@ -0,0 +1,100 @@ +/** + * \file : reset_elf_loader.c + * \date : August 2012 + * \author : Cesar Fuguet + * + * This file defines an elf file loader which reads an executable .elf file + * starting at a sector passed as argument on a disk and copy the different + * ELF program segments in the appropriate memory address using as information + * the virtual address read from the .elf file. + */ + +#include +#include +#include +#include +#include + +/////////////////////////////////////////////////////////////////////////////// +void * reset_elf_loader(size_t lba) +/////////////////////////////////////////////////////////////////////////////// +{ + size_t file_offset = lba * BLOCK_SIZE; + + reset_puts("\n[RESET] Start reset_elf_loader at cycle "); + reset_putd( proctime() ); + reset_puts("\n"); + + /* + * Load ELF HEADER + */ + Elf32_Ehdr elf_header; + if (pread(file_offset, (void*)&elf_header, sizeof(Elf32_Ehdr), 0) < 0) { + goto error; + } + check_elf_header(&elf_header); + + /* + * Load ELF PROGRAM HEADER TABLE + */ + Elf32_Phdr elf_pht[PHDR_ARRAY_SIZE]; + size_t phdr_nbyte = sizeof(Elf32_Phdr) * elf_header.e_phnum; + size_t phdr_off = elf_header.e_phoff; + if (pread(file_offset, (void*)&elf_pht, phdr_nbyte, phdr_off) < 0) { + goto error; + } + + /* + * Search for loadable segments in the ELF file + */ + int pseg; + for (pseg = 0; pseg < elf_header.e_phnum; pseg++) + { + if(elf_pht[pseg].p_type != PT_LOAD) continue; + +#if (RESET_DEBUG == 1) + reset_puts("[RESET DEBUG] Loadable segment found:\n"); + reset_print_elf_phdr(&elf_pht[pseg]); +#endif + + addr_t p_paddr = elf_pht[pseg].p_paddr; + size_t p_filesz = elf_pht[pseg].p_filesz; + size_t p_memsz = elf_pht[pseg].p_memsz; + size_t p_offset = elf_pht[pseg].p_offset; + + /* + * Copy program segment from ELF executable into corresponding physical + * address + */ + if (pread(file_offset, (void*)p_paddr, p_filesz, p_offset) < 0) { + goto error; + } + + /* + * Fill remaining bytes with zero (filesz < memsz) + */ + char* pseg_ptr = (char*)p_paddr; + memset((void*)&pseg_ptr[p_filesz], 0, (p_memsz - p_filesz)); + + reset_puts("\n[RESET] Segment loaded : address = "); + reset_putx(p_paddr); + reset_puts(" / size = "); + reset_putx(p_filesz); + reset_puts("\n"); + } + + reset_puts("\n[RESET] Complete reset_elf_loader at cycle "); + reset_putd( proctime() ); + reset_puts(" / boot entry = "); + reset_putx( (addr_t)(elf_header.e_entry) ); + reset_puts("\n"); + + return ((void *) elf_header.e_entry); + +error: + reset_puts("\n[RESET ERROR] Error while loading ELF file"); + reset_exit(); + return 0; +} + +// vim: tabstop=4 : softtabstop=4 : shiftwidth=4 : expandtab Index: /branches/fault_tolerance/softs/tsar_boot/src/reset_exception.c =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/src/reset_exception.c (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/src/reset_exception.c (revision 724) @@ -0,0 +1,25 @@ +/** + * \file : exceptions.c + * \date : December 2012 + * \author : Manuel Bouyer + * + * This file defines a simple exceptions handler + */ + +#include + +void handle_except(int status, int cause, int epc, int dbvar) +{ + reset_puts("\n[RESET] exception handler called: \r\n status "); + reset_putx(status); + reset_puts("\r\n cause "); + reset_putx(cause); + reset_puts(" (exception "); + reset_putx((cause >> 2) & 0x1f); + reset_puts(")\r\n epc "); + reset_putx(epc); + reset_puts("\r\n dbvar "); + reset_putx(dbvar); + reset_puts("\r\n"); + while (1); +} Index: /branches/fault_tolerance/softs/tsar_boot/src/reset_ioc.c =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/src/reset_ioc.c (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/src/reset_ioc.c (revision 724) @@ -0,0 +1,207 @@ +#include + +#if USE_SPI +static struct sdcard_dev _sdcard_device; +static struct spi_dev *const _spi_device = (struct spi_dev*) IOC_PADDR_BASE; +#endif + +#define SDCARD_RESET_ITER_MAX 4 + +/////////////////////////////////// +inline void reset_sleep(int cycles) +{ + int i; + for (i = 0; i < cycles; i++); +} + +#if USE_SPI +/////////////////////////////////////////////////////////////////////////////// +// reset_ioc_init +// This function initializes the SDCARD / required for FPGA. +/////////////////////////////////////////////////////////////////////////////// +int reset_ioc_init() +{ + unsigned char sdcard_rsp; + + reset_puts("Initializing block device\n\r"); + + /** + * Initializing the SPI controller + */ + spi_dev_config ( + _spi_device , + 200000 , /**< SPI_clk: 200 Khz */ + SYSCLK_FREQ , /**< Sys_clk */ + 8 , /**< Charlen: 8 */ + SPI_TX_NEGEDGE, + SPI_RX_POSEDGE + ); + + /** + * Initializing the SD Card + */ + unsigned int iter = 0; + while(1) + { + reset_puts("Trying to initialize SD card... "); + + sdcard_rsp = sdcard_dev_open(&_sdcard_device, _spi_device, 0); + if (sdcard_rsp == 0) + { + reset_puts("OK\n"); + break; + } + + reset_puts("KO\n"); + reset_sleep(1000); + if (++iter >= SDCARD_RESET_ITER_MAX) + { + reset_puts("\nERROR: During SD card reset to IDLE state\n" + "/ card response = "); + reset_putx(sdcard_rsp); + reset_puts("\n"); + reset_exit(); + } + } + + /** + * Set the block length of the SD Card + */ + sdcard_rsp = sdcard_dev_set_blocklen(&_sdcard_device, 512); + if (sdcard_rsp) + { + reset_puts("ERROR: During SD card blocklen initialization\n"); + reset_exit(); + } + + /** + * Incrementing SDCARD clock frequency for normal function + */ + spi_dev_config ( + _spi_device , + 10000000 , /**< SPI_clk 10 Mhz */ + SYSCLK_FREQ , /**< Sys_clk */ + -1 , /**< Charlen: 8 */ + -1 , + -1 + ); + + reset_puts("Finish block device initialization\n\r"); + + return 0; +} // end reset_ioc_init() +#endif + +////////////////////////////////////////////////////////////////////////////// +// reset_bdv_read() +///////////////////////////////////////////////////////////////////////////// +#if USE_BDV +int reset_bdv_read( unsigned int lba, + void* buffer, + unsigned int count ) +{ + unsigned int * ioc_address = (unsigned int*)IOC_PADDR_BASE; + + // block_device configuration + iowrite32( &ioc_address[BLOCK_DEVICE_BUFFER], (unsigned int) buffer ); + iowrite32( &ioc_address[BLOCK_DEVICE_COUNT], count ); + iowrite32( &ioc_address[BLOCK_DEVICE_LBA], lba ); + iowrite32( &ioc_address[BLOCK_DEVICE_IRQ_ENABLE], 0 ); + + // block_device trigger transfer + iowrite32( &ioc_address[BLOCK_DEVICE_OP], ( unsigned int ) + BLOCK_DEVICE_READ ); + + unsigned int status = 0; + while ( 1 ) + { + status = ioread32(&ioc_address[BLOCK_DEVICE_STATUS]); + if ( status == BLOCK_DEVICE_READ_SUCCESS ) + { + break; + } + if ( status == BLOCK_DEVICE_READ_ERROR ) { + reset_puts("ERROR during read on the BLK device\n"); + return 1; + } + } +#if (CACHE_COHERENCE == 0) || USE_IOB + reset_buf_invalidate(buffer, CACHE_LINE_SIZE, count * 512); +#endif + return 0; +} +#endif + +////////////////////////////////////////////////////////////////////////////// +// reset_spi_read() +///////////////////////////////////////////////////////////////////////////// +#if USE_SPI +static int reset_spi_read( unsigned int lba, + void* buffer, + unsigned int count ) +{ + unsigned int sdcard_rsp; + unsigned int i; + + sdcard_dev_lseek(&_sdcard_device, lba); + for(i = 0; i < count; i++) + { + unsigned char* buf = (unsigned char *) buffer + (512 * i); + if (( sdcard_rsp = sdcard_dev_read ( &_sdcard_device, buf, 512 ) )) + { + reset_puts("ERROR during read on the SDCARD device. Code: "); + reset_putx(sdcard_rsp); + reset_puts("\n"); + return 1; + } + } + return 0; +} +#endif + +////////////////////////////////////////////////////////////////////////////// +// reset_rdk_read() +///////////////////////////////////////////////////////////////////////////// +#if USE_RDK +static int reset_rdk_read( unsigned int lba, + void* buffer, + unsigned int count ) +{ + unsigned int* rdk_address = (unsigned int*) RDK_PADDR_BASE; + char* src = (char*) rdk_address + (lba * 512); + + memcpy(buffer, (void*) src, count * 512); + return 0; +} +#endif + +/////////////////////////////////////////////////////////////////////////////// +// reset_ioc_read() +// Transfer data from disk to a memory buffer +// - param lba : first block index on the disk +// - param buffer : base address of the memory buffer +// - param count : number of blocks to be transfered +// This is a blocking function. The function returns once the transfer is +// completed. +// +// The USE_BDV, USE_SPI and USE_RDK variables signal if the disk is accessed +// through a BLOCK DEVICE, SPI or RAMDISK respectively +/////////////////////////////////////////////////////////////////////////////// +int reset_ioc_read( unsigned int lba, + void* buffer, + unsigned int count ) +{ +#if USE_BDV + return reset_bdv_read(lba, buffer, count); +#elif USE_SPI + return reset_spi_read(lba, buffer, count); +#elif USE_RDK + return reset_rdk_read(lba, buffer, count); +#else +# error "reset_ioc_read() : No supported disk controller chosen" +#endif +} + +/* + * vim: tabstop=4 : shiftwidth=4 : expandtab + */ Index: /branches/fault_tolerance/softs/tsar_boot/src/reset_tty.c =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/src/reset_tty.c (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/src/reset_tty.c (revision 724) @@ -0,0 +1,103 @@ +/******************************************************************** + * \file reset_tty.c + * \date 5 mars 2014 + * \author Cesar Fuguet + * + * Minimal driver for TTY controler + *******************************************************************/ + +#include +#include +#include + +/////////////////////// +int reset_getc(char *c) +{ + unsigned int* tty_address = (unsigned int*) TTY_PADDR_BASE; + + if (ioread32( &tty_address[TTY_STATUS] ) == 0) return 0; + *c = ioread32( &tty_address[TTY_READ] ); + return 1; +} + +///////////////////////////// +void reset_putc(const char c) +{ + unsigned int* tty_address = (unsigned int*) TTY_PADDR_BASE; + + iowrite32( &tty_address[TTY_WRITE], (unsigned int)c ); + if (c == '\n') reset_putc( '\r' ); +} + +/////////////////////////////////// +void reset_puts(const char *buffer) +{ + unsigned int n; + + for ( n=0; n<100; n++) + { + if (buffer[n] == 0) break; + reset_putc(buffer[n]); + } +} + +///////////////////////////////// +void reset_putx(unsigned int val) +{ + static const char HexaTab[] = "0123456789ABCDEF"; + char buf[11]; + unsigned int c; + + buf[0] = '0'; + buf[1] = 'x'; + buf[10] = 0; + + for ( c = 0 ; c < 8 ; c++ ) + { + buf[9-c] = HexaTab[val&0xF]; + val = val >> 4; + } + reset_puts(buf); +} + +///////////////////////////////// +void reset_putd(unsigned int val) +{ + static const char DecTab[] = "0123456789"; + char buf[11]; + unsigned int i; + unsigned int first = 0; + + buf[10] = 0; + + for ( i = 0 ; i < 10 ; i++ ) + { + if ((val != 0) || (i == 0)) + { + buf[9-i] = DecTab[val % 10]; + first = 9-i; + } + else + { + break; + } + val /= 10; + } + reset_puts( &buf[first] ); +} + +///////////////// +void reset_exit() +{ + register int pid; + asm volatile( "mfc0 %0, $15, 1": "=r"(pid) ); + + reset_puts("\n!!! Exit Processor "); + reset_putx(pid); + reset_puts(" !!!\n"); + + while(1) asm volatile("nop"); // infinite loop... +} + + + Index: /branches/fault_tolerance/softs/tsar_boot/src/reset_utils.c =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/src/reset_utils.c (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/src/reset_utils.c (revision 724) @@ -0,0 +1,300 @@ +/** + * \file : reset_utils.c + * \date : August 2012 + * \author : Cesar Fuguet + * + * Definition of utilities functions used by the TSAR pre-loader + */ + +#include + +/* + * pread(size_t file_offset, void* buf, size_t nbyte, size_t offset) + * + * read from disk into buffer "nbyte" bytes from (file_offset + offset) + * + * \param file_offset: Disk relative offset of file + * \param buf: Destination buffer + * \param nbyte: Number of bytes to read + * \param offset: File relative offset + * + * \note Absolute disk offset (in bytes) is (file_offset + offset) + */ +int pread(size_t file_offset, void *buf, size_t nbyte, size_t offset) { + if (nbyte == 0) return 0; + + /* + * Cache block data buffer and cached block index + */ + static struct aligned_blk blk_buf; + static int blk_buf_idx = -1; + + char *dst; + int offset_blk; + int unaligned_nbyte; + int read_nbyte; + + dst = (char*) buf; + + /* + * Offset parameter is relative to file, therefore compute disk relative + * offset (in bytes) + */ + offset += file_offset; + + /* + * Read unaligned bytes at start of segment passing by block cache + */ + offset_blk = (offset / BLOCK_SIZE); + offset = (offset % BLOCK_SIZE); + unaligned_nbyte = BLOCK_SIZE - offset; + read_nbyte = 0; + if (offset) { + /* + * Check cache block hit: if miss, read new block else, use cache block + * data + */ + if (offset_blk != blk_buf_idx) { + if (reset_ioc_read(offset_blk, (void*)&blk_buf, 1)) { + return -1; + } + } + blk_buf_idx = offset_blk; + read_nbyte = (nbyte > unaligned_nbyte) ? unaligned_nbyte : nbyte; + memcpy((void*)dst, (void*)&blk_buf.b[offset], read_nbyte); + nbyte -= read_nbyte; + offset_blk += 1; + } + + /* + * Read aligned bytes directly to buffer + */ + size_t nblk = nbyte / BLOCK_SIZE; + if (nblk) { + if (reset_ioc_read(offset_blk, (void*)&dst[read_nbyte], nblk)) { + return -1; + } + read_nbyte += (nblk * BLOCK_SIZE); + nbyte -= read_nbyte; + offset_blk += nblk; + } + + /* + * Read unaligned bytes at the end of segment passing by block cache + */ + if (nbyte) { + if (reset_ioc_read(offset_blk, (void*)&blk_buf, 1)) { + return -1; + } + blk_buf_idx = offset_blk; + memcpy((void*)&dst[read_nbyte], (void*)&blk_buf, nbyte); + read_nbyte += nbyte; + } + return read_nbyte; +} + +/******************************************************************** + * proctime() + * + * Returns processor local time. + ********************************************************************/ +inline unsigned int proctime() +{ + unsigned int ret; + asm volatile ("mfc0 %0, $9":"=r" (ret)); + return ret; +} + +/******************************************************************** + * memcpy( _dst, _src, size ) + * + * Transfer data between two memory buffers. + * + * \param _dst : Destination buffer base address + * \param _src : Source buffer base address + * \param size : Number of bytes to transfer + * + ********************************************************************/ +void* memcpy(void *_dst, const void *_src, size_t n) +{ + unsigned int *dst = _dst; + const unsigned int *src = _src; + if (!((unsigned int)dst & 3) && !((unsigned int)src & 3)) { + while (n > 3) { + *dst++ = *src++; + n -= 4; + } + } + + unsigned char *cdst = (unsigned char*) dst; + unsigned char *csrc = (unsigned char*) src; + while (n--) { + *cdst++ = *csrc++; + } + return _dst; +} + +/******************************************************************** + * memset( _dst, value, size ) + * + * Initialize memory buffers with predefined value. + * + * \param _dst : Destination buffer base address + * \param value : Initialization value + * \param size : Number of bytes to initialize + * + ********************************************************************/ +void* memset(void *_dst, int c, size_t len) +{ + if (len == 0) return _dst; + + unsigned char val = (unsigned char) c; + + /* + * Set not word aligned bytes at start of destination buffer + */ + unsigned char* cdst = (unsigned char*) _dst; + while (((addr_t)cdst & 3) && len--) { + *cdst++ = val; + } + + /* + * Set 4 bytes words on destination buffer + */ + unsigned int word = (val << 24) | (val << 16) | (val << 8 ) | val; + addr_t *wdst = (addr_t*)cdst; + while (len > 3) { + *wdst++ = word; + len -= 4; + } + + /* + * Set not word aligned bytes at end of destination buffer + */ + cdst = (unsigned char*) wdst; + while(len--) { + *cdst++ = val; + } + return _dst; +} + +/******************************************************************** + * check_elf_header(Elf32_Ehdr*) + * + * Verify that ELF file is valid and that the number of program + * headers does not exceed the defined maximum + * + * \param ehdr : ELF header pointer + * + ********************************************************************/ +void check_elf_header(Elf32_Ehdr *ehdr) +{ + /* + * Verification of ELF Magic Number + */ + if ((ehdr->e_ident[EI_MAG0] != ELFMAG0) || + (ehdr->e_ident[EI_MAG1] != ELFMAG1) || + (ehdr->e_ident[EI_MAG2] != ELFMAG2) || + (ehdr->e_ident[EI_MAG3] != ELFMAG3)) + { + reset_puts("[RESET ERROR] Unrecognized file format (not an ELF format)\n"); + reset_exit(); + } + + /* + * Verification of Program Headers table size. It must be + * smaller than the work size allocated for the + * elf_pht[PHDR_ARRAY_SIZE] array + */ + if (ehdr->e_phnum > PHDR_ARRAY_SIZE) + { + reset_puts("[RESET ERROR] ELF PHDR table size too large\n"); + reset_exit(); + } +} + +/******************************************************************** + * reset_print_elf_phdr( elf_phdr_ptr ) + * + * Print some fields of a ELF program header + * + * \param elf_phdr_ptr : Pointer to the ELF program header to print + * + ********************************************************************/ +void reset_print_elf_phdr(Elf32_Phdr * elf_phdr_ptr) +{ + reset_puts("- type : "); + reset_putx(elf_phdr_ptr->p_type); + reset_puts("\n- offset : "); + reset_putx(elf_phdr_ptr->p_offset); + reset_puts("\n- vaddr : "); + reset_putx(elf_phdr_ptr->p_vaddr); + reset_puts("\n- paddr : "); + reset_putx(elf_phdr_ptr->p_paddr); + reset_puts("\n- filesz : "); + reset_putx(elf_phdr_ptr->p_filesz); + reset_puts("\n- memsz : "); + reset_putx(elf_phdr_ptr->p_memsz); + reset_puts("\n- flags : "); + reset_putx(elf_phdr_ptr->p_flags); + reset_puts("\n- align : "); + reset_putx(elf_phdr_ptr->p_align); + reset_puts("\n"); +} + + +/******************************************************************** + * reset_mcc_inval() + * + * Invalidate all data cache lines corresponding to a memory buffer + * (identified by an address and a size) in L2 cache. + ********************************************************************/ +#if USE_IOB +void reset_mcc_invalidate (const void * buffer, size_t size) +{ + addr_t *mcc_address = (addr_t*)MCC_PADDR_BASE; + + // get the hard lock assuring exclusive access to MEMC + while (ioread32(&mcc_address[MCC_LOCK])); + + // write invalidate paremeters on the memory cache this preloader + // use only the cluster 0 and then the HI bits are not used + + iowrite32(&mcc_address[MCC_ADDR_LO], (unsigned int) buffer); + iowrite32(&mcc_address[MCC_ADDR_HI], (unsigned int) 0); + iowrite32(&mcc_address[MCC_LENGTH] , (unsigned int) size); + iowrite32(&mcc_address[MCC_CMD] , (unsigned int) MCC_CMD_INVAL); + + // release the lock protecting MEMC + iowrite32(&mcc_address[MCC_LOCK], (unsigned int) 0); +} +#endif + +/******************************************************************** + * reset_dcache_buf_invalidate() + * + * Invalidate all data cache lines corresponding to a memory buffer + * (identified by an address and a size) in L1 cache and L2 cache. + ********************************************************************/ +#if (CACHE_COHERENCE == 0) || USE_IOB +void reset_buf_invalidate (const void * buffer, size_t line_size, size_t size) +{ + unsigned int i; + + // iterate on cache lines + for (i = 0; i <= size; i += line_size) + { + asm volatile( + " cache %0, %1" + :// no outputs + :"i" (0x11), "R" (*((unsigned char *) buffer + i)) + ); + } + +#if USE_IOB + reset_mcc_invalidate(buffer, size); +#endif +} +#endif + +// vim: tabstop=4 : softtabstop=4 : shiftwidth=4 : expandtab Index: /branches/fault_tolerance/softs/tsar_boot/src/sdcard.c =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/src/sdcard.c (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/src/sdcard.c (revision 724) @@ -0,0 +1,366 @@ +/** + * \file : sdcard.c + * \date : 30 August 2012 + * \author : Cesar Fuguet + * + * This file defines the driver of a SD Card device using an SPI controller + */ + +#include +#include + +/** + * \param sdcard: Initialized pointer to the block device + * + * \return void + * + * \brief Enable SD Card select signal + */ +static void _sdcard_enable(struct sdcard_dev * sdcard) +{ + spi_ss_assert(sdcard->spi, sdcard->slave_id); +} + +/** + * \param sdcard: Initialized pointer to the block device + * + * \return void + * + * \brief Disable SD Card select signal + */ +static void _sdcard_disable(struct sdcard_dev * sdcard) +{ + spi_ss_deassert(sdcard->spi, sdcard->slave_id); +} + +/** + * \param tick_count: SD Card clock ticks number + * + * \return void + * + * \brief Enable SD Card clock + * The tick count is byte measured (1 tick, 8 clock) + */ +static void _sdcard_gen_tick(struct sdcard_dev * sdcard, unsigned int tick_count) +{ + register int i = 0; + while(i++ < tick_count) spi_put_tx(sdcard->spi, 0xFF, 0); +} + +/** + * \param sdcard: Initialized pointer to the block device + * + * \return char from the SD card + * + * \brief Get a byte from the SD Card + */ +static unsigned char _sdcard_receive_char(struct sdcard_dev * sdcard) +{ + _sdcard_gen_tick(sdcard, 1); + + return spi_get_rx(sdcard->spi, 0); +} + +/** + * \param sdcard: Initialized pointer to the block device + * + * \return sdcard response + * + * \brief Wait for a valid response after the send of a command + * This function can return if one of the next two conditions are true: + * 1. Bit valid received + * 2. Timeout (not valid bit received after SDCARD_COMMAND_TIMEOUT + * wait ticks) + */ +static unsigned char _sdcard_wait_response(struct sdcard_dev * sdcard) +{ + unsigned char sdcard_rsp; + register int iter; + + iter = 0; + sdcard_rsp = _sdcard_receive_char(sdcard); + while ( + (iter < SDCARD_COMMAND_TIMEOUT) && + !SDCARD_CHECK_R1_VALID(sdcard_rsp) + ) + { + sdcard_rsp = _sdcard_receive_char(sdcard); + iter++; + } + + return sdcard_rsp; +} + +/** + * \params sdcard: Initialized pointer to the block device + * + * \return void + * + * \brief Wait data block start marker + */ +static void _sdcard_wait_data_block(struct sdcard_dev * sdcard) +{ + while (_sdcard_receive_char(sdcard) != 0xFE); +} + +/** + * \param sdcard : Initialized pointer to block device + * \param index : SD card CMD index + * \param app : Type of command, 0 for normal command or 1 for application + * specific + * \param args : SD card CMD arguments + * + * \return response first byte + * + * \brief Send command to the SD card + */ +static int _sdcard_send_command ( + struct sdcard_dev * sdcard , + int index , + int app , + void * args , + unsigned crc7 ) +{ + unsigned char sdcard_rsp; + unsigned char * _args; + + _sdcard_gen_tick(sdcard, 5); + + if (app == SDCARD_ACMD) + { + spi_put_tx(sdcard->spi, 0x40 | 55 , 0 );/* CMD and START bit */ + spi_put_tx(sdcard->spi, 0x00 , 0 );/* Argument[0] */ + spi_put_tx(sdcard->spi, 0x00 , 0 );/* Argument[1] */ + spi_put_tx(sdcard->spi, 0x00 , 0 );/* Argument[2] */ + spi_put_tx(sdcard->spi, 0x00 , 0 );/* Argument[3] */ + spi_put_tx(sdcard->spi, 0x01 | (crc7 << 1), 0 );/* END bit */ + + sdcard_rsp = _sdcard_wait_response(sdcard); + if (SDCARD_CHECK_R1_ERROR(sdcard_rsp)) + { + return sdcard_rsp; + } + } + + _args = (unsigned char *) args; + + _sdcard_gen_tick(sdcard, 1); + + spi_put_tx(sdcard->spi, 0x40 | index , 0 ); + spi_put_tx(sdcard->spi, _args[0] , 0 ); + spi_put_tx(sdcard->spi, _args[1] , 0 ); + spi_put_tx(sdcard->spi, _args[2] , 0 ); + spi_put_tx(sdcard->spi, _args[3] , 0 ); + spi_put_tx(sdcard->spi, 0x01 | (crc7 << 1), 0 ); + + return _sdcard_wait_response(sdcard); +} + +int sdcard_dev_open(struct sdcard_dev * sdcard, struct spi_dev * spi, int ss) +{ + unsigned char args[4]; + unsigned char sdcard_rsp; + unsigned int iter, ersp; + + sdcard->spi = spi; + sdcard->slave_id = ss; + + /* + * Supply SD card ramp up time (min 74 cycles) + */ + _sdcard_gen_tick(sdcard, 10); + + /* + * Assert slave select signal + * Send CMD0 (Reset Command) + * Deassert slave select signal + */ + _sdcard_enable(sdcard); + + args[0] = 0; + args[1] = 0; + args[2] = 0; + args[3] = 0; + sdcard_rsp = _sdcard_send_command(sdcard, 0, SDCARD_CMD, args, 0x4A); + if ( sdcard_rsp != 0x01 ) + { + reset_puts("card CMD0 failed "); + return sdcard_rsp; + } + + _sdcard_disable(sdcard); + /* + * send CMD8. If card is pre-v2, It will reply with illegal command. + * Otherwise we announce sdhc support. + */ + _sdcard_enable(sdcard); + args[0] = 0; + args[1] = 0; + args[2] = 0x01; + args[3] = 0x01; + sdcard_rsp = _sdcard_send_command(sdcard, 8, SDCARD_CMD, args, 0x63); + if (!SDCARD_CHECK_R1_VALID(sdcard_rsp)) { + reset_puts("card CMD8 failed "); + return sdcard_rsp; + } + if (!SDCARD_CHECK_R1_ERROR(sdcard_rsp)) { + /* no error, command accepted. get whole reply */ + ersp = _sdcard_receive_char(sdcard); + ersp = (ersp << 8) | _sdcard_receive_char(sdcard); + ersp = (ersp << 8) | _sdcard_receive_char(sdcard); + ersp = (ersp << 8) | _sdcard_receive_char(sdcard); + if ((ersp & 0xffff) != 0x0101) { + /* voltage mismatch */ + reset_puts("card CMD8 mismatch: "); + reset_putx(ersp); + return sdcard_rsp; + } + reset_puts("v2 or later "); + sdcard->sdhc = 1; + } else if ((sdcard_rsp & SDCARD_R1_ILLEGAL_CMD) == 0) { + /* other error */ + reset_puts("card CMD8 error "); + return sdcard_rsp; + } else { + sdcard->sdhc = 0; + } + _sdcard_disable(sdcard); + /* send CMD41, enabling the card */ + _sdcard_enable(sdcard); + args[0] = sdcard->sdhc ? 0x40: 0; + args[1] = 0; + args[2] = 0; + args[3] = 0; + + iter = 0; + while( iter++ < SDCARD_COMMAND_TIMEOUT ) + { + sdcard_rsp = _sdcard_send_command(sdcard, 41, SDCARD_ACMD, args, 0x00); + if( sdcard_rsp == 0x01 ) + { + continue; + } + + break; + } + + _sdcard_disable(sdcard); + if (sdcard_rsp) { + reset_puts("SD ACMD41 failed "); + return sdcard_rsp; + } + if (sdcard->sdhc != 0) { + /* get the card capacity to see if it's really HC */ + _sdcard_enable(sdcard); + args[0] = sdcard->sdhc ? 0x40: 0; + args[1] = 0; + args[2] = 0; + args[3] = 0; + sdcard_rsp = _sdcard_send_command(sdcard, 58, SDCARD_CMD, + args, 0x00); + if (sdcard_rsp) { + reset_puts("SD CMD58 failed "); + return sdcard_rsp; + } + ersp = _sdcard_receive_char(sdcard); + ersp = (ersp << 8) | _sdcard_receive_char(sdcard); + ersp = (ersp << 8) | _sdcard_receive_char(sdcard); + ersp = (ersp << 8) | _sdcard_receive_char(sdcard); + if (ersp & 0x40000000) { + reset_puts("SDHC "); + } else { + sdcard->sdhc = 0; + } + _sdcard_disable(sdcard); + } + reset_puts("card detected "); + return 0; +} + +int sdcard_dev_read(struct sdcard_dev * sdcard, void * buf, unsigned int count) +{ + unsigned char args[4]; + unsigned char sdcard_rsp; + register int i; + + for (i = 0; i < 4; i++) + { + args[i] = (sdcard->access_pointer >> (32 - (i+1)*8)) & 0xFF; + } + + _sdcard_enable(sdcard); + + sdcard_rsp = _sdcard_send_command(sdcard, 17, SDCARD_CMD, args, 0x00); + if ( SDCARD_CHECK_R1_ERROR(sdcard_rsp) ) + { + _sdcard_disable(sdcard); + return sdcard_rsp; + } + + _sdcard_wait_data_block(sdcard); + + spi_get_data(sdcard->spi, buf, count); + + /* + * Get the remainder of the block bytes and the CRC16 (comes + * at the end of the data block) + */ + i = count; + while( i++ < (512 + 2) ) _sdcard_receive_char(sdcard); + + _sdcard_disable(sdcard); + + /* + * Move the access pointer to the next block + */ + sdcard->access_pointer += sdcard->block_length; + + return 0; +} + +unsigned int sdcard_dev_write(struct sdcard_dev *sdcard, void * buf, unsigned int count) +{ + return 0; +} + +void sdcard_dev_lseek(struct sdcard_dev * sdcard, unsigned int blk_pos) +{ + sdcard->access_pointer = sdcard->block_length * blk_pos; +} + +int sdcard_dev_set_blocklen(struct sdcard_dev * sdcard, unsigned int len) +{ + unsigned char args[4]; + unsigned char sdcard_rsp; + register int i; + + if (len != 512) + return 1; + + if (sdcard->sdhc) { + sdcard->block_length = 1; + return 0; + } + + for (i = 0; i < 4; i++) + args[i] = (len >> (32 - (i+1)*8)) & 0xFF; + + _sdcard_enable(sdcard); + + sdcard_rsp = _sdcard_send_command(sdcard, 16, SDCARD_CMD, args, 0x00); + if ( SDCARD_CHECK_R1_ERROR(sdcard_rsp) ) + { + _sdcard_disable(sdcard); + return sdcard_rsp; + } + + _sdcard_disable(sdcard); + + sdcard->block_length = len; + + return 0; +} + +/* + * vim: tabstop=4 : shiftwidth=4 : expandtab : softtabstop=4 + */ Index: /branches/fault_tolerance/softs/tsar_boot/src/spi.c =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/src/spi.c (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/src/spi.c (revision 724) @@ -0,0 +1,192 @@ +/** + * \file spi.c + * \date 31 August 2012 + * \author Cesar Fuguet + */ +#include +#include +#include + +/** + * \param x: input value + * + * \return byte-swapped value + * + * \brief byte-swap a 32bit word + */ +static unsigned int bswap32(unsigned int x) +{ + unsigned int y; + y = (x & 0x000000ff) << 24; + y |= (x & 0x0000ff00) << 8; + y |= (x & 0x00ff0000) >> 8; + y |= (x & 0xff000000) >> 24; + return y; +} + +/** + * \param spi : Initialized pointer to the SPI controller + * + * \brief Wait until the SPI controller has finished a transfer + * + * Wait until the GO_BUSY bit of the SPI controller be deasserted + */ +static void _spi_wait_if_busy(struct spi_dev * spi) +{ + register int delay; + + while(SPI_IS_BUSY(spi)) + { + for (delay = 0; delay < 100; delay++); + } +} + +/** + * \param spi : Initialized pointer to the SPI controller + * + * \return void + * + * \brief Init transfer of the tx registers to the selected slaves + */ +static void _spi_init_transfer(struct spi_dev * spi) +{ + unsigned int spi_ctrl = ioread32(&spi->ctrl); + + iowrite32(&spi->ctrl, spi_ctrl | SPI_CTRL_GO_BSY); +} + +/** + * \param spi_freq : Desired frequency for the generated clock from the SPI + * controller + * \param sys_freq : System clock frequency + * + * \brief Calculated the value for the divider register in order to obtain the SPI + * desired clock frequency + */ +static unsigned int _spi_calc_divider_value ( + unsigned int spi_freq , + unsigned int sys_freq ) +{ + return ((sys_freq / (spi_freq * 2)) - 1); +} + +void spi_put_tx(struct spi_dev * spi, unsigned char byte, int index) +{ + _spi_wait_if_busy(spi); + { + iowrite8(&spi->rx_tx[index % 4], byte); + _spi_init_transfer(spi); + } + _spi_wait_if_busy(spi); +} + +volatile unsigned char spi_get_rx(struct spi_dev * spi, int index) +{ + return ioread8(&spi->rx_tx[index % 4]); +} + +void spi_get_data(struct spi_dev * spi, void *buf, unsigned int count) +{ + unsigned int *data = buf; + unsigned char *data8; + unsigned int spi_ctrl0, spi_ctrl; + int i; + + _spi_wait_if_busy(spi); + + spi_ctrl0 = ioread32(&spi->ctrl); +#ifdef IOC_USE_DMA + if (count == 512 && ((int)buf & 0x3f) == 0) { + /* use DMA */ + spi->dma_base = (int)buf; + spi->dma_baseh = 0; + spi->dma_count = count | SPI_DMA_COUNT_READ; + _spi_wait_if_busy(spi); + i = count / 4; + } else +#endif /* IOC_USE_DMA */ + { + /* switch to 128 bits words */ + spi_ctrl = (spi_ctrl0 & ~SPI_CTRL_CHAR_LEN_MASK) | 128; + iowrite32(&spi->ctrl, spi_ctrl); + + /* read data */ + for (i = 0; i + 3 < count / 4; i += 4) { + iowrite32(&spi->rx_tx[0], 0xffffffff); + iowrite32(&spi->rx_tx[1], 0xffffffff); + iowrite32(&spi->rx_tx[2], 0xffffffff); + iowrite32(&spi->rx_tx[3], 0xffffffff); + iowrite32(&spi->ctrl, spi_ctrl | SPI_CTRL_GO_BSY); + + _spi_wait_if_busy(spi); + + *data = bswap32(ioread32(&spi->rx_tx[3])); + data++; + *data = bswap32(ioread32(&spi->rx_tx[2])); + data++; + *data = bswap32(ioread32(&spi->rx_tx[1])); + data++; + *data = bswap32(ioread32(&spi->rx_tx[0])); + data++; + } + } + + /* switch back to original word size */ + iowrite32(&spi->ctrl, spi_ctrl0); + + /* read missing bits */ + data8 = (void *)data; + i = i * 4; + for (; i < count; i++) + { + iowrite32(&spi->rx_tx[0], 0xffffffff); + iowrite32(&spi->ctrl, spi_ctrl0 | SPI_CTRL_GO_BSY); + + _spi_wait_if_busy(spi); + + *data8 = spi_get_rx(spi, 0); + data8++; + } + return; +} + +void spi_ss_assert(struct spi_dev * spi, int index) +{ + unsigned int spi_ss = ioread32(&spi->ss); + + iowrite32(&spi->ss, spi_ss | (1 << index)); +} + +void spi_ss_deassert(struct spi_dev * spi, int index) +{ + unsigned int spi_ss = ioread32(&spi->ss); + + iowrite32(&spi->ss, spi_ss & ~(1 << index)); +} + +void spi_dev_config ( + struct spi_dev * spi, + int spi_freq , + int sys_freq , + int char_len , + int tx_edge , + int rx_edge ) +{ + unsigned int spi_ctrl = ioread32(&spi->ctrl); + + if ( tx_edge == 0 ) spi_ctrl |= SPI_CTRL_TXN_EN; + else if ( tx_edge == 1 ) spi_ctrl &= ~SPI_CTRL_TXN_EN; + if ( rx_edge == 0 ) spi_ctrl |= SPI_CTRL_RXN_EN; + else if ( rx_edge == 1 ) spi_ctrl &= ~SPI_CTRL_RXN_EN; + if ( char_len > 0 ) spi_ctrl = (spi_ctrl & ~SPI_CTRL_CHAR_LEN_MASK) | + (char_len & SPI_CTRL_CHAR_LEN_MASK); + + iowrite32(&spi->ctrl, spi_ctrl); + + if (spi_freq > 0 && sys_freq > 0) + iowrite32(&spi->divider, _spi_calc_divider_value(spi_freq, sys_freq)); +} + +/* + * vim: tabstop=4 : shiftwidth=4 : expandtab : softtabstop=4 + */ Index: /branches/fault_tolerance/softs/tsar_boot/version.sh =================================================================== --- /branches/fault_tolerance/softs/tsar_boot/version.sh (revision 724) +++ /branches/fault_tolerance/softs/tsar_boot/version.sh (revision 724) @@ -0,0 +1,20 @@ +#!/bin/sh + +n="tsarboot" +v=$(cat VERSION) +t=$(date) +u=${USER-root} +h=$(hostname) + +reporev=$(svn info 2>/dev/null) +if [ $? -eq 0 ]; +then + repotype="svn" + reporev=$(echo "$reporev" | awk -F: '$1 == "Last Changed Rev" {print $2}') +else + repotype="git" + reporev=$(git rev-parse HEAD) +fi + +printf "%s" \ + "const char versionstr[]=\"$n $v ($u@$h $t) ($repotype revision $reporev)\n\r\";"