Changeset 73 for trunk/modules/vci_cc_vcache_wrapper2_v1/caba

Timestamp:

Aug 7, 2010, 12:42:20 AM (14 years ago)

Author:

bouyer

Message:

Fix several issues regarding management of the r_dcache_in_itlb/r_dcache_in_dtlb
arrays:

• fix convertion from cache line number to physical address in various place
• ICACHE_TLB_CC_INVAL: add ICACHE_TLB1_WRITE and ICACHE_TLB2_WRITE to the list of cases where r_icache_inval_tlb_rsp should be set to true. Otherwise, the fsm will go to ICACHE_TLB1_WRITE the ICACHE_TLB1_UPD once the ICACHE_TLB_CC_INVAL is done, and the TLB entry being dealt with will be entered, while it's not registered any more with the dcache.
• add a check in ICACHE_IDLE and DCACHE_IDLE that a tlb hit] should imply the correspoding PTE entry being in the dcache, and the r_dcache_in_itlb/r_dcache_in_dtlb arrray. abort() if an inconsistency is found.

File:

• trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp (modified) (11 diffs)

trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp

@@ -1007 +1007 @@
         else                                                                // MMU activated
         { 
+            size_t c_way, c_set;
             m_cpt_ins_tlb_read++;
             icache_hit_t  = icache_tlb.cctranslate(ireq.addr, &tlb_ipaddr, &icache_pte_info, 
@@ -1014 +1015 @@
             spc_ipaddr    = ((paddr_t)r_icache_ppn_save << PAGE_K_NBITS) | (paddr_t)(ireq.addr & PAGE_K_MASK);
             icache_cached = icache_pte_info.c; 
+            if (icache_hit_t) {
+               if (!r_dcache.read(icache_tlb_nline << (uint32_log2(m_dcache_words) + 2), &icache_ins, &c_way, &c_set)) {
+                std::cout << "itlb PTE " << std::hex << icache_tlb_nline << " " << (icache_tlb_nline << (uint32_log2(m_dcache_words) + 2)) << " not in cache" << std::endl;
+                abort();
+              }
+              if (!r_dcache_in_itlb[m_dcache_sets*c_way+c_set]) {
+                std::cout << "itlb PTE " << std::hex << icache_tlb_nline << " "
+                    << (icache_tlb_nline << (uint32_log2(m_dcache_words) + 2)) <<
+                    " " << c_way << "," << c_set << " @" << &r_dcache_in_itlb[m_dcache_sets*c_way+c_set] << " not in_itlb" << std::endl;
+                abort();
+              }
+           }
         }
 
@@ -2031 +2044 @@
         // invalidate cache
         if( (( r_icache_fsm_save == ICACHE_TLB1_READ ) || ( r_icache_fsm_save == ICACHE_TLB2_READ )  ||
-          /* ( r_icache_fsm_save == ICACHE_TLB1_WRITE )|| ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) ||*/
+          ( r_icache_fsm_save == ICACHE_TLB1_WRITE )|| ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) ||
              ( r_icache_fsm_save == ICACHE_TLB1_UPDT ) || ( r_icache_fsm_save == ICACHE_TLB2_UPDT )) && 
             (((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) >> (uint32_log2(m_icache_words) + 2) ) == r_dcache_itlb_inval_line.read()) ) 
@@ -2556 +2569 @@
             else                                                            // MMU activated
             {
+                size_t c_way, c_set;
                 m_cpt_data_tlb_read++;
                 dcache_hit_t  = dcache_tlb.cctranslate(dreq.addr, &tlb_dpaddr, &dcache_pte_info, 
@@ -2565 +2579 @@
                                 ((dreq.type != iss_t::DATA_LL)  && (dreq.type != iss_t::DATA_SC) &&
                                  (dreq.type != iss_t::XTN_READ) && (dreq.type != iss_t::XTN_WRITE));    
+               if (dcache_hit_t) {
+                   if (!r_dcache.read(dcache_tlb_nline << (uint32_log2(m_dcache_words) + 2), &dcache_rdata, &c_way, &c_set)) {
+                    std::cout << "dtlb PTE " << std::hex << dcache_tlb_nline << " " << (dcache_tlb_nline << (uint32_log2(m_dcache_words) + 2)) << " not in cache" << std::endl;
+                    abort();
+                  }
+                  if (!r_dcache_in_dtlb[m_dcache_sets*c_way+c_set]) {
+                    std::cout << "dtlb PTE " << std::hex << dcache_tlb_nline <<
+                        " " << c_way << "," << c_set << " not in_dtlb" <<
+                        std::endl;
+                    abort();
+                  }
+              }
             }
 
@@ -3556 +3582 @@
             if (dcache_tlb.update(r_dcache_pte_update,dreq.addr,(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index))
             {
-                r_dcache.setinbit((paddr_t)victim_index*m_dcache_words*2, r_dcache_in_dtlb, false);
+                r_dcache.setinbit((paddr_t)victim_index << (uint32_log2(m_dcache_words) + 2), r_dcache_in_dtlb, false);
             }
             r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true);
@@ -4013 +4039 @@
             if (dcache_tlb.update(r_dcache_pte_update,r_dcache_ppn_update,dreq.addr,(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index))
             {
-                r_dcache.setinbit((paddr_t)victim_index*m_dcache_words*2, r_dcache_in_dtlb, false);
+                r_dcache.setinbit((paddr_t)victim_index << (uint32_log2(m_dcache_words) + 2), r_dcache_in_dtlb, false);
             }
             r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true);
@@ -4036 +4062 @@
         if ( r_dcache_itlb_cleanup_req )
         {    
-            r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read()*m_dcache_words*2), r_dcache_in_itlb, false);
+            r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read() << (uint32_log2(m_dcache_words) + 2)), r_dcache_in_itlb, false);
             r_dcache_itlb_cleanup_req = false;
         }
@@ -4046 +4072 @@
                 if(dcache_tlb.checkcleanup(way, set, &victim_index))
                 {
-                    r_dcache.setinbit((paddr_t)(victim_index << (m_dcache_words+2)), r_dcache_in_dtlb, false); 
+                    /*
+                     * this is correct because checkcleanup returns true only
+                     * if none of the PTE entries of the line is global.
+                     */
+                    r_dcache.setinbit((paddr_t)victim_index << (uint32_log2(m_dcache_words) + 2), r_dcache_in_dtlb, false); 
                 }
             }
@@ -4143 +4173 @@
         if ( dcache_tlb.inval(r_dcache_wdata_save, &victim_index) )
         {  
-            r_dcache.setinbit((paddr_t)(victim_index << (m_dcache_words+2)), r_dcache_in_dtlb, false); 
+            r_dcache.setinbit((paddr_t)(victim_index << (uint32_log2(m_dcache_words) + 2)), r_dcache_in_dtlb, false); 
         }
         r_dtlb_translation_valid = false;
@@ -4954 +4984 @@
         if ( dreq.valid ) m_cost_data_miss_frz++;
 
-        r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read()*m_dcache_words*2), r_dcache_in_itlb, false);
+        r_dcache.setinbit((paddr_t)r_dcache_itlb_cleanup_line.read() << (uint32_log2(m_dcache_words) + 2), r_dcache_in_itlb, false);
         r_dcache_itlb_cleanup_req = false;
         r_dcache_fsm = DCACHE_IDLE;