Index: branches/fault_tolerance/platforms/tsar_generic_iob/arch.py
===================================================================
--- branches/fault_tolerance/platforms/tsar_generic_iob/arch.py	(revision 736)
+++ branches/fault_tolerance/platforms/tsar_generic_iob/arch.py	(revision 738)
@@ -12,6 +12,6 @@
 #  physical space segmentation) and the mapping of all kernel objects (global vsegs).
 #  This platform includes 6 external peripherals, accessible through two IO_Bridge
-# components located in cluster [0,0] and cluster [x_size-1, y_size-1].
-# Available peripherals are: TTY, BDV, FBF, ROM, NIC, CMA.
+#  components located in cluster [0,0] and cluster [x_size-1, y_size-1].
+#  Available peripherals are: TTY, BDV, FBF, ROM, NIC, CMA.
 #
 #  The "constructor" parameters are:
@@ -41,16 +41,16 @@
     ### define architecture constants
 
-    distptabs      = 1
-    nb_ttys        = 1
-    nb_nics        = 2
-    fbf_width      = 1024
-    x_io           = 0
-    y_io           = 0
-    x_width        = 4
-    y_width        = 4
-    paddr_width    = 40
-    irq_per_proc   = 4
-    use_ramdisk    = False
-    peri_increment = 0x10000
+    nb_ttys           = 1
+    nb_nics           = 2
+    fbf_width         = 1024
+    x_io              = 0
+    y_io              = 0
+    x_width           = 4
+    y_width           = 4
+    paddr_width       = 40
+    irq_per_proc      = 4
+    use_ramdisk       = False
+    peri_increment    = 0x10000
+    distributed_ptabs = True
 
     ### parameters checking
@@ -161,5 +161,7 @@
                        x_io           = x_io,
                        y_io           = y_io,
-                       peri_increment = peri_increment )
+                       peri_increment = peri_increment,
+                       ram_base       = ram_base,
+                       ram_size       = ram_size )
 
     ###  external peripherals (accessible in cluster[0,0] only for this mapping)
@@ -241,5 +243,5 @@
     ### global vsegs for kernel
 
-    if distptabs:
+    if distributed_ptabs:
         for x in xrange( x_size ):
             for y in xrange( y_size ):
@@ -291,6 +293,6 @@
                        vtype = 'PERI', x = 0, y = 0, pseg = 'PIC', identity = True )
 
-    ### Global vsegs for replicated peripherals, and for schedulers
-    ### name is indexed by (x,y), base address is incremented by (cluster_xy * peri_increment)
+    ### global vsegs for internal peripherals, and for schedulers
+    ### name is indexed by (x,y) / vbase address is incremented by (cluster_xy * peri_increment)
 
     for x in xrange( x_size ):
@@ -322,12 +324,7 @@
 if __name__ == '__main__':
 
-    mapping = genmap( x_size    = 2,
-                      y_size    = 2,
-                      nb_procs  = 2,
-                      nb_ttys   = 1,
-                      nb_nics   = 2,
-                      fbf_width = 128,
-                      x_io      = 0,
-                      y_io      = 0 )
+    mapping = arch( x_size    = 2,
+                    y_size    = 2,
+                    nb_procs  = 2 )
 
 #   print mapping.netbsd_dts()
Index: branches/fault_tolerance/platforms/tsar_generic_iob/soclib.conf
===================================================================
--- branches/fault_tolerance/platforms/tsar_generic_iob/soclib.conf	(revision 736)
+++ branches/fault_tolerance/platforms/tsar_generic_iob/soclib.conf	(revision 738)
@@ -1,5 +1,4 @@
 cflags = config.default.toolchain.cflags \
          + ['-DUSE_OPENMP=0'] \
-         + ['-DDISTRIBUTED_BOOT=false'] \
 #        + ['-ggdb']
 
Index: branches/fault_tolerance/platforms/tsar_generic_iob/top.cpp
===================================================================
--- branches/fault_tolerance/platforms/tsar_generic_iob/top.cpp	(revision 736)
+++ branches/fault_tolerance/platforms/tsar_generic_iob/top.cpp	(revision 738)
@@ -9,10 +9,9 @@
 // an external bus (i.e. Hypertransport) to access 7 external peripherals:
 //
-// - BROM : boot ROM
 // - FBUF : Frame Buffer
-// - MTTY : multi TTY (up to 15 channels)
+// - MTTY : multi TTY (one channel)
 // - MNIC : Network controller (up to 2 channels)
 // - CDMA : Chained Buffer DMA controller (up to 4 channels)
-// - BDEV : Dlock Device controler (1 channel)
+// - BDEV : Dlock Device controler (one channel)
 // - IOPI : HWI to SWI translator.
 //
@@ -39,6 +38,4 @@
 // external IOPIC component, that must be configured by the OS to route
 // these WTI ITQS to one or several internal XICU components.
-// The total number of channels for the external peripherals (MTTY, MNIC, CDMA
-// IOC or HBA) is limited by the IOPIC 32 HWI inputs:..
 // - IOPIC HWI[1:0]     connected to IRQ_NIC_RX[1:0]
 // - IOPIC HWI[3:2]     connected to IRQ_NIC_TX[1:0]
@@ -48,5 +45,5 @@
 // - IOPIC HWI[31:9]    unused       (grounded)
 //
-// Besides the external peripherals, each cluster contains on XICU component,
+// Besides the external peripherals, each cluster contains one XICU component,
 // and one multi channels DMA component.
 // The XICU component is mainly used to handle WTI IRQs, as only 2 HWI IRQs
@@ -227,13 +224,4 @@
 #define BOOT_SOFT_NAME        "../../softs/tsar_boot/preloader.elf"
 
-// Activate Distributed Boot
-// When this is activated, every processor boots with its physical address
-// extension register initialized to its cluster index (X_LOCAL, Y_LOCAL). To
-// support this feature, a distributed ROM is implemented in each cluster.
-
-#ifndef DISTRIBUTED_BOOT
-#define DISTRIBUTED_BOOT false
-#endif
-
 ////////////////////////////////////////////////////////////
 //     DEBUG Parameters default values
@@ -246,9 +234,8 @@
 /////////////////////////////////////////////////////////
 
-// Replicated RAMs : address is incremented by a cluster offset
-//     offset  = cluster(x,y) << (address_width-x_width-y_width);
-
-#define SEG_RAM_BASE          0x0000000000
-#define SEG_RAM_SIZE          0x0004000000   // 64 Mbytes
+// All physical segments base addresses and sizes are defined
+// in the hard_config.h file. For replicated segments, the
+// base address is incremented by a cluster offset:
+// offset  = cluster(x,y) << (address_width-x_width-y_width);
 
 ////////////////////////////////////////////////////////////////////////
@@ -449,4 +436,12 @@
    }
 
+   // Activate Distributed Boot (set by environment variable)
+   // When this is activated, every processor boots with its instruction and data
+   // physical address extension register initialized to its cluster index
+   // (X_LOCAL, Y_LOCAL). To support this feature, a distributed ROM is
+   // implemented in each cluster.
+
+   const bool distributed_boot = (getenv("DISTRIBUTED_BOOT") != NULL);
+
    // checking hardware parameters
    assert( (XMAX <= 16) and
@@ -479,4 +474,5 @@
              << " - RAM_LATENCY     = " << XRAM_LATENCY << std::endl
              << " - MAX_FROZEN      = " << frozen_cycles << std::endl
+             << " - DIST_BOOT       = " << distributed_boot << std::endl
              << " - DEBUG_PROCID    = " << debug_proc_id << std::endl
              << " - DEBUG_MEMCID    = " << debug_memc_id << std::endl
@@ -979,4 +975,5 @@
                                        IntTab(0, IOX_IOPI_TGT_ID),
                                        32 );        // number of input HWI
+
    // Clusters
    TsarIobCluster<vci_param_int,
@@ -1069,5 +1066,5 @@
                 XCU_NB_INPUTS,
 
-                DISTRIBUTED_BOOT,
+                distributed_boot,
 
                 loader,
