Index: /trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp
===================================================================
--- /trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp	(revision 72)
+++ /trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp	(revision 73)
@@ -1007,4 +1007,5 @@
         else                                                                // MMU activated
         { 
+	    size_t c_way, c_set;
             m_cpt_ins_tlb_read++;
             icache_hit_t  = icache_tlb.cctranslate(ireq.addr, &tlb_ipaddr, &icache_pte_info, 
@@ -1014,4 +1015,16 @@
             spc_ipaddr    = ((paddr_t)r_icache_ppn_save << PAGE_K_NBITS) | (paddr_t)(ireq.addr & PAGE_K_MASK);
             icache_cached = icache_pte_info.c; 
+	    if (icache_hit_t) {
+	       if (!r_dcache.read(icache_tlb_nline << (uint32_log2(m_dcache_words) + 2), &icache_ins, &c_way, &c_set)) {
+		std::cout << "itlb PTE " << std::hex << icache_tlb_nline << " " << (icache_tlb_nline << (uint32_log2(m_dcache_words) + 2)) << " not in cache" << std::endl;
+		abort();
+	      }
+	      if (!r_dcache_in_itlb[m_dcache_sets*c_way+c_set]) {
+		std::cout << "itlb PTE " << std::hex << icache_tlb_nline << " "
+		    << (icache_tlb_nline << (uint32_log2(m_dcache_words) + 2)) <<
+		    " " << c_way << "," << c_set << " @" << &r_dcache_in_itlb[m_dcache_sets*c_way+c_set] << " not in_itlb" << std::endl;
+		abort();
+	      }
+	   }
         }
 
@@ -2031,5 +2044,5 @@
         // invalidate cache
         if( (( r_icache_fsm_save == ICACHE_TLB1_READ ) || ( r_icache_fsm_save == ICACHE_TLB2_READ )  ||
-          /* ( r_icache_fsm_save == ICACHE_TLB1_WRITE )|| ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) ||*/
+          ( r_icache_fsm_save == ICACHE_TLB1_WRITE )|| ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) ||
              ( r_icache_fsm_save == ICACHE_TLB1_UPDT ) || ( r_icache_fsm_save == ICACHE_TLB2_UPDT )) && 
             (((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) >> (uint32_log2(m_icache_words) + 2) ) == r_dcache_itlb_inval_line.read()) ) 
@@ -2556,4 +2569,5 @@
             else                                                            // MMU activated
             {
+		size_t c_way, c_set;
                 m_cpt_data_tlb_read++;
                 dcache_hit_t  = dcache_tlb.cctranslate(dreq.addr, &tlb_dpaddr, &dcache_pte_info, 
@@ -2565,4 +2579,16 @@
                                 ((dreq.type != iss_t::DATA_LL)  && (dreq.type != iss_t::DATA_SC) &&
                                  (dreq.type != iss_t::XTN_READ) && (dreq.type != iss_t::XTN_WRITE));    
+	       if (dcache_hit_t) {
+	           if (!r_dcache.read(dcache_tlb_nline << (uint32_log2(m_dcache_words) + 2), &dcache_rdata, &c_way, &c_set)) {
+		    std::cout << "dtlb PTE " << std::hex << dcache_tlb_nline << " " << (dcache_tlb_nline << (uint32_log2(m_dcache_words) + 2)) << " not in cache" << std::endl;
+		    abort();
+	          }
+	          if (!r_dcache_in_dtlb[m_dcache_sets*c_way+c_set]) {
+		    std::cout << "dtlb PTE " << std::hex << dcache_tlb_nline <<
+			" " << c_way << "," << c_set << " not in_dtlb" <<
+			std::endl;
+		    abort();
+	          }
+	      }
             }
 
@@ -3556,5 +3582,5 @@
             if (dcache_tlb.update(r_dcache_pte_update,dreq.addr,(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index))
             {
-                r_dcache.setinbit((paddr_t)victim_index*m_dcache_words*2, r_dcache_in_dtlb, false);
+                r_dcache.setinbit((paddr_t)victim_index << (uint32_log2(m_dcache_words) + 2), r_dcache_in_dtlb, false);
             }
             r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true);
@@ -4013,5 +4039,5 @@
             if (dcache_tlb.update(r_dcache_pte_update,r_dcache_ppn_update,dreq.addr,(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index))
             {
-                r_dcache.setinbit((paddr_t)victim_index*m_dcache_words*2, r_dcache_in_dtlb, false);
+                r_dcache.setinbit((paddr_t)victim_index << (uint32_log2(m_dcache_words) + 2), r_dcache_in_dtlb, false);
             }
             r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true);
@@ -4036,5 +4062,5 @@
         if ( r_dcache_itlb_cleanup_req )
         {    
-            r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read()*m_dcache_words*2), r_dcache_in_itlb, false);
+            r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read() << (uint32_log2(m_dcache_words) + 2)), r_dcache_in_itlb, false);
             r_dcache_itlb_cleanup_req = false;
 	}
@@ -4046,5 +4072,9 @@
                 if(dcache_tlb.checkcleanup(way, set, &victim_index))
                 {
-                    r_dcache.setinbit((paddr_t)(victim_index << (m_dcache_words+2)), r_dcache_in_dtlb, false); 
+		    /*
+		     * this is correct because checkcleanup returns true only
+		     * if none of the PTE entries of the line is global.
+		     */
+                    r_dcache.setinbit((paddr_t)victim_index << (uint32_log2(m_dcache_words) + 2), r_dcache_in_dtlb, false); 
                 }
             }
@@ -4143,5 +4173,5 @@
         if ( dcache_tlb.inval(r_dcache_wdata_save, &victim_index) )
         {  
-            r_dcache.setinbit((paddr_t)(victim_index << (m_dcache_words+2)), r_dcache_in_dtlb, false); 
+            r_dcache.setinbit((paddr_t)(victim_index << (uint32_log2(m_dcache_words) + 2)), r_dcache_in_dtlb, false); 
         }
         r_dtlb_translation_valid = false;
@@ -4954,5 +4984,5 @@
         if ( dreq.valid ) m_cost_data_miss_frz++;
 
-        r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read()*m_dcache_words*2), r_dcache_in_itlb, false);
+        r_dcache.setinbit((paddr_t)r_dcache_itlb_cleanup_line.read() << (uint32_log2(m_dcache_words) + 2), r_dcache_in_itlb, false);
         r_dcache_itlb_cleanup_req = false;
         r_dcache_fsm = DCACHE_IDLE;