Changeset 742
- Timestamp:
- Jul 9, 2014, 5:36:08 PM (10 years ago)
- Location:
- branches/fault_tolerance
- Files:
-
- 10 edited
Legend:
- Unmodified
- Added
- Removed
-
branches/fault_tolerance/modules/vci_block_device_tsar/caba/source/include/vci_block_device_tsar.h
r724 r742 33 33 // contain 32 bits words. It supports VCI addresss lartger than 32 bits. 34 34 // 35 // This component can perform data transfers between one single file belonging36 // to the host system and a buffer in the memory of the virtual prototype.37 // The file name is an argument of the constructor.35 // This component can perform data transfers between one single file (belonging 36 // to the host system) and a buffer in the memory of the virtual prototype. 37 // The name of the file containing the disk image is a constructor argument. 38 38 // This component has a DMA capability, and is both a target and an initiator. 39 39 // The block size (bytes), and the burst size (bytes) must be power of 2. … … 54 54 // - BLOCK_DEVICE_SIZE 0x18 (read-only) Number of addressable blocks. 55 55 // - BLOCK_DEVICE_BLOCK_SIZE 0x1C (read_only) Block size in bytes. 56 // - BLOCK_DEVICE_BUFFER_EXT 0x20 (read _only)Memory buffer base address (MSB bits)56 // - BLOCK_DEVICE_BUFFER_EXT 0x20 (read/write) Memory buffer base address (MSB bits) 57 57 // 58 58 // The following operations codes are supported: -
branches/fault_tolerance/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
r724 r742 342 342 bool m_debug_dcache_fsm; 343 343 bool m_debug_cmd_fsm; 344 uint32_t m_previous_status; 345 344 346 345 347 /////////////////////////////// -
branches/fault_tolerance/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r724 r742 476 476 { 477 477 // b0 : write buffer trace 478 // b1 : dump processor registers 478 479 // b2 : dcache trace 479 480 // b3 : icache trace 480 481 // b4 : dtlb trace 481 482 // b5 : itlb trace 483 // b6 : SR (ISS register 32) 482 484 483 485 std::cout << std::dec << "PROC " << name() << std::endl; … … 509 511 r_wbuf.printTrace((mode>>1)&1); 510 512 } 513 if(mode & 0x02) 514 { 515 r_iss.dump(); 516 } 511 517 if(mode & 0x04) 512 518 { … … 528 534 std::cout << " Instruction TLB" << std::endl; 529 535 r_itlb.printTrace(); 536 } 537 if(mode & 0x40) 538 { 539 uint32_t status = r_iss.debugGetRegisterValue( 32 ); 540 std::cout << name(); 541 if ( status != m_previous_status ) std::cout << " NEW "; 542 std::cout << " status = " << std::hex << status << " " << std::endl; 543 m_previous_status = status; 530 544 } 531 545 } -
branches/fault_tolerance/modules/vci_io_bridge/caba/source/src/vci_io_bridge.cpp
r724 r742 736 736 { 737 737 assert( p_vci_tgt_iox.eop.read() and 738 (p_vci_tgt_iox.cmd == vci_param_int::CMD_WRITE) and738 (p_vci_tgt_iox.cmd.read() == vci_param_int::CMD_WRITE) and 739 739 "ERROR in VCI_IOB illegal VCI WTI command from IOX network"); 740 740 -
branches/fault_tolerance/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r725 r742 3940 3940 if (m_debug) 3941 3941 std::cout << " <MEMC " << name() << " WRITE_BC_DIR_INVAL> Inval DIR and register in TRT:" 3942 << " address = " << r_write_address.read() << std::endl;3942 << " address = " << std::hex << r_write_address.read() << std::endl; 3943 3943 #endif 3944 3944 r_write_fsm = WRITE_BC_CC_SEND; -
branches/fault_tolerance/platforms/tsar_generic_iob/top.cpp
r738 r742 47 47 // Besides the external peripherals, each cluster contains one XICU component, 48 48 // and one multi channels DMA component. 49 // The XICU component is mainly used to handle WTI IRQs, as only 2HWI IRQs49 // The XICU component is mainly used to handle WTI IRQs, as only 5 HWI IRQs 50 50 // are connected to XICU in each cluster: 51 51 // - IRQ_IN[0] : MMC -
branches/fault_tolerance/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h
r724 r742 71 71 // interrupt signals 72 72 sc_signal<bool> signal_false; 73 sc_signal<bool> signal_proc_it[ 8];73 sc_signal<bool> signal_proc_it[16]; 74 74 sc_signal<bool> signal_irq_mdma[8]; 75 75 sc_signal<bool> signal_irq_memc; -
branches/fault_tolerance/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp
r724 r742 639 639 } 640 640 641 SC_METHOD(init); 641 SC_METHOD(init); 642 642 643 } // end constructor 643 644 644 645 tmpl(void)::init() 645 646 { 646 signal_ram_dspin_cmd_false.write = false; 647 signal_ram_dspin_cmd_false.read = true; 648 signal_ram_dspin_rsp_false.write = false; 649 signal_ram_dspin_rsp_false.read = true; 647 signal_ram_dspin_cmd_false.write = false; 648 signal_ram_dspin_rsp_false.read = true; 650 649 } // end init 651 650 -
branches/fault_tolerance/softs/tsar_boot/conf/platform_tsar_generic_iob/defs_platform.h
r724 r742 1 #define NB_PROCS 1 2 #define NB_CLUSTERS 4 1 #define NB_PROCS 4 2 #define NB_CLUSTERS 1 3 #define CLUSTER_IO 0 3 4 4 #define IRQ_PER_PROC 15 #define IRQ_PER_PROC 4 5 6 6 7 #define USE_IOB 1 -
branches/fault_tolerance/softs/tsar_boot/conf/platform_tsar_generic_iob/ldscript
r724 r742 9 9 seg_reset_code_base = 0xBFC00000; 10 10 11 seg_reset_stack_base = 0x000 60000;12 seg_reset_stack_size = 0x000 90000;11 seg_reset_stack_base = 0x000D0000; 12 seg_reset_stack_size = 0x00050000; 13 13 14 14 /* Grouping sections into segments */
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