Index: branches/fault_tolerance/modules/vci_block_device_tsar/caba/source/include/vci_block_device_tsar.h
===================================================================
--- branches/fault_tolerance/modules/vci_block_device_tsar/caba/source/include/vci_block_device_tsar.h	(revision 725)
+++ branches/fault_tolerance/modules/vci_block_device_tsar/caba/source/include/vci_block_device_tsar.h	(revision 742)
@@ -33,7 +33,7 @@
 // contain 32 bits words. It supports VCI addresss lartger than 32 bits.
 //
-// This component can perform data transfers between one single file belonging 
-// to the host system and a buffer in the memory of the virtual prototype.
-// The file name is an argument of the constructor.
+// This component can perform data transfers between one single file (belonging 
+// to the host system) and a buffer in the memory of the virtual prototype.
+// The name of the file containing the disk image is a constructor argument.
 // This component has a DMA capability, and is both a target and an initiator.
 // The block size (bytes), and the burst size (bytes) must be power of 2.
@@ -54,5 +54,5 @@
 // - BLOCK_DEVICE_SIZE          0x18 (read-only)   Number of addressable blocks.
 // - BLOCK_DEVICE_BLOCK_SIZE    0x1C (read_only)   Block size in bytes.
-// - BLOCK_DEVICE_BUFFER_EXT    0x20 (read_only)   Memory buffer base address (MSB bits)
+// - BLOCK_DEVICE_BUFFER_EXT    0x20 (read/write)  Memory buffer base address (MSB bits)
 //
 // The following operations codes are supported: 
Index: branches/fault_tolerance/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
===================================================================
--- branches/fault_tolerance/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 725)
+++ branches/fault_tolerance/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 742)
@@ -342,4 +342,6 @@
     bool                                m_debug_dcache_fsm;
     bool                                m_debug_cmd_fsm;
+    uint32_t                            m_previous_status;
+
 
     ///////////////////////////////
Index: branches/fault_tolerance/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
===================================================================
--- branches/fault_tolerance/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 725)
+++ branches/fault_tolerance/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 742)
@@ -476,8 +476,10 @@
 {
     // b0 : write buffer trace
+    // b1 : dump processor registers
     // b2 : dcache trace
     // b3 : icache trace
     // b4 : dtlb trace
     // b5 : itlb trace
+    // b6 : SR (ISS register 32)
 
     std::cout << std::dec << "PROC " << name() << std::endl;
@@ -509,4 +511,8 @@
         r_wbuf.printTrace((mode>>1)&1);
     }
+    if(mode & 0x02)
+    {
+        r_iss.dump();
+    }
     if(mode & 0x04)
     {
@@ -528,4 +534,12 @@
         std::cout << "  Instruction TLB" << std::endl;
         r_itlb.printTrace();
+    }
+    if(mode & 0x40)
+    {
+        uint32_t status = r_iss.debugGetRegisterValue( 32 );
+        std::cout << name();
+        if ( status != m_previous_status ) std::cout << " NEW ";
+        std::cout << " status = " << std::hex << status << " " << std::endl;
+        m_previous_status = status;
     }
 }
Index: branches/fault_tolerance/modules/vci_io_bridge/caba/source/src/vci_io_bridge.cpp
===================================================================
--- branches/fault_tolerance/modules/vci_io_bridge/caba/source/src/vci_io_bridge.cpp	(revision 725)
+++ branches/fault_tolerance/modules/vci_io_bridge/caba/source/src/vci_io_bridge.cpp	(revision 742)
@@ -736,5 +736,5 @@
                         {
                             assert( p_vci_tgt_iox.eop.read() and
-                                   (p_vci_tgt_iox.cmd == vci_param_int::CMD_WRITE) and
+                                   (p_vci_tgt_iox.cmd.read() == vci_param_int::CMD_WRITE) and
                             "ERROR in VCI_IOB illegal VCI WTI command from IOX network");
 
Index: branches/fault_tolerance/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
===================================================================
--- branches/fault_tolerance/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp	(revision 725)
+++ branches/fault_tolerance/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp	(revision 742)
@@ -3940,5 +3940,5 @@
                     if (m_debug)
                         std::cout << "  <MEMC " << name() << " WRITE_BC_DIR_INVAL> Inval DIR and register in TRT:"
-                            << " address = " << r_write_address.read() << std::endl;
+                            << " address = " << std::hex << r_write_address.read() << std::endl;
 #endif
                     r_write_fsm = WRITE_BC_CC_SEND;