Index: /branches/reconfiguration/platforms/tsar_generic_iob/arch.py =================================================================== --- /branches/reconfiguration/platforms/tsar_generic_iob/arch.py (revision 747) +++ /branches/reconfiguration/platforms/tsar_generic_iob/arch.py (revision 748) @@ -8,5 +8,5 @@ # author : Alain Greiner ####################################################################################### -# This file contains a mapping generator for the "tsar_generic_iob" platform. +# This file contains a mapping generator for the "tsar_generic_iob" platform. # This includes both the hardware architecture (clusters, processors, peripherals, # physical space segmentation) and the mapping of all kernel objects (global vsegs). @@ -42,5 +42,5 @@ nb_ttys = 1 - nb_nics = 2 + nb_nics = 2 fbf_width = 1024 x_io = 0 @@ -53,13 +53,13 @@ peri_increment = 0x10000 distributed_ptabs = True - + ### parameters checking assert( nb_procs <= 4 ) - assert( (x_size == 1) or (x_size == 2) or (x_size == 4) + assert( (x_size == 1) or (x_size == 2) or (x_size == 4) or (y_size == 8) or (x_size == 16) ) - assert( (y_size == 1) or (y_size == 2) or (y_size == 4) + assert( (y_size == 1) or (y_size == 2) or (y_size == 4) or (y_size == 8) or (y_size == 16) ) @@ -70,18 +70,21 @@ platform_name = 'tsar_iob_%d_%d_%d' % ( x_size, y_size, nb_procs ) - + ### define physical segments - ram_base = 0x0000000000 - ram_size = 0x4000000 # 64 Mbytes - - xcu_base = 0x00B0000000 - xcu_size = 0x1000 # 4 Kbytes - - dma_base = 0x00B1000000 - dma_size = 0x1000 * nb_procs # 4 Kbytes * nb_procs - - mmc_base = 0x00B2000000 - mmc_size = 0x1000 # 4 Kbytes + ram_base = 0x0000000000 + ram_size = 0x4000000 # 64 Mbytes + + xcu_base = 0x00B0000000 + xcu_size = 0x1000 # 4 Kbytes + + dma_base = 0x00B1000000 + dma_size = 0x1000 * nb_procs # 4 Kbytes * nb_procs + + mmc_base = 0x00B2000000 + mmc_size = 0x1000 # 4 Kbytes + + rom_base = 0x00BFC00000 + rom_size = 0x8000 # 32 Kbytes offset_io = ((x_io << y_width) + y_io) << (paddr_width - x_width - y_width) @@ -106,8 +109,7 @@ iob_base = 0x00BE000000 + offset_io - iob_size = 0x1000 # 4kbytes - - rom_base = 0x00BFC00000 + offset_io - rom_size = 0x4000 # 16 Kbytes + iob_size = 0x1000 # 4 kbytes + + ### GIET_VM specifics virtual segments ### define bootloader vsegs base addresses @@ -117,6 +119,6 @@ boot_code_vbase = 0x00040000 # ident - boot_code_size = 0x00020000 # 128 Kbytes - + boot_code_size = 0x00020000 # 128 Kbytes + boot_data_vbase = 0x00060000 # ident boot_data_size = 0x00010000 # 64 Kbytes @@ -125,10 +127,10 @@ boot_buffer_size = 0x00060000 # 384 Kbytes - boot_stack_vbase = 0x000D0000 # ident - boot_stack_size = 0x00050000 # 320 Kbytes + boot_stack_vbase = 0x03F00000 # ident + boot_stack_size = 0x00100000 # 1 Mbytes ### define kernel vsegs base addresses - kernel_code_vbase = 0x80000000 + kernel_code_vbase = 0x80000000 kernel_code_size = 0x00020000 # 128 Kbytes @@ -147,19 +149,19 @@ ### create mapping - mapping = Mapping( name = platform_name, - x_size = x_size, - y_size = y_size, - procs_max = nb_procs, - x_width = x_width, - y_width = y_width, - paddr_width = paddr_width, - coherence = True, - irq_per_proc = irq_per_proc, - use_ramdisk = use_ramdisk, - x_io = x_io, + mapping = Mapping( name = platform_name, + x_size = x_size, + y_size = y_size, + procs_max = nb_procs, + x_width = x_width, + y_width = y_width, + paddr_width = paddr_width, + coherence = True, + irq_per_proc = irq_per_proc, + use_ramdisk = use_ramdisk, + x_io = x_io, y_io = y_io, - peri_increment = peri_increment, - ram_base = ram_base, - ram_size = ram_size ) + peri_increment = peri_increment, + ram_base = ram_base, + ram_size = ram_size ) ### external peripherals (accessible in cluster[0,0] only for this mapping) @@ -171,11 +173,9 @@ tty = mapping.addPeriph( 'TTY', base = tty_base, size = tty_size, ptype = 'TTY', channels = nb_ttys ) - nic = mapping.addPeriph( 'NIC', base = nic_base, size = nic_size, ptype = 'NIC', channels = nb_nics ) + nic = mapping.addPeriph( 'NIC', base = nic_base, size = nic_size, ptype = 'NIC', channels = nb_nics ) cma = mapping.addPeriph( 'CMA', base = cma_base, size = cma_size, ptype = 'CMA', channels = 2*nb_nics ) fbf = mapping.addPeriph( 'FBF', base = fbf_base, size = fbf_size, ptype = 'FBF', arg = fbf_width ) - - rom = mapping.addPeriph( 'ROM', base = rom_base, size = rom_size, ptype = 'ROM' ) pic = mapping.addPeriph( 'PIC', base = pic_base, size = pic_size, ptype = 'PIC', channels = 32 ) @@ -196,5 +196,5 @@ mapping.addIrq( pic, index = 9, isrtype = 'ISR_TTY_RX', channel = 0 ) - ### hardware components replicated in all clusters + ### hardware components replicated in all clusters for x in xrange( x_size ): @@ -205,12 +205,15 @@ ram = mapping.addRam( 'RAM', base = ram_base + offset, size = ram_size ) - mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset, size = mmc_size, + mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset, size = mmc_size, ptype = 'MMC' ) - dma = mapping.addPeriph( 'DMA', base = dma_base + offset, size = dma_size, - ptype = 'DMA', channels = nb_procs ) - - xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset, size = xcu_size, + dma = mapping.addPeriph( 'DMA', base = dma_base + offset, size = dma_size, + ptype = 'DMA', channels = nb_procs ) + + xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset, size = xcu_size, ptype = 'XCU', channels = nb_procs * irq_per_proc, arg = 16 ) + + rom = mapping.addPeriph( 'ROM', base = rom_base + offset, size = rom_size, + ptype = 'ROM' ) # MMC IRQ replicated in all clusters @@ -221,28 +224,22 @@ mapping.addProc( x, y, p ) - ### global vsegs for boot_loader / identity mapping - - mapping.addGlobal( 'seg_boot_mapping', boot_mapping_vbase, boot_mapping_size, - 'C_W_', vtype = 'BLOB' , x = 0, y = 0, pseg = 'RAM', - identity = True ) - - mapping.addGlobal( 'seg_boot_code', boot_code_vbase, boot_code_size, - 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', - identity = True ) - - mapping.addGlobal( 'seg_boot_data', boot_data_vbase, boot_data_size, - 'C_W_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', - identity = True ) - - mapping.addGlobal( 'seg_boot_buffer', boot_buffer_vbase, boot_buffer_size, - 'C_W_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', - identity = True ) - - mapping.addGlobal( 'seg_boot_stack', boot_stack_vbase, boot_stack_size, - 'C_W_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', - identity = True ) - - ### the code global vsegs for kernel can be replicated in all clusters - ### if the page tables are distributed in all clusters. + ### global vsegs for boot_loader / identity mapping + + mapping.addGlobal( 'seg_boot_mapping' , boot_mapping_vbase , boot_mapping_size , 'C_W_', + vtype = 'BLOB' , x = 0, y = 0, pseg = 'RAM', identity = True ) + + mapping.addGlobal( 'seg_boot_code' , boot_code_vbase , boot_code_size , 'CXW_', + vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) + + mapping.addGlobal( 'seg_boot_data' , boot_data_vbase , boot_data_size , 'C_W_', + vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) + + mapping.addGlobal( 'seg_boot_buffer' , boot_buffer_vbase , boot_buffer_size , 'C_W_', + vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) + + mapping.addGlobal( 'seg_boot_stack' , boot_stack_vbase , boot_stack_size , 'C_W_', + vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', identity = True ) + + ### global vsegs for kernel if distributed_ptabs: @@ -261,55 +258,40 @@ mapping.addGlobal( 'seg_kernel_code', kernel_code_vbase, kernel_code_size, 'CXW_', vtype = 'ELF', x = 0 , y = 0 , pseg = 'RAM', - binpath = 'build/kernel/kernel.elf', local = False ) + binpath = 'build/kernel/kernel.elf' ) mapping.addGlobal( 'seg_kernel_init', kernel_init_vbase, kernel_init_size, 'CXW_', vtype = 'ELF', x = 0 , y = 0 , pseg = 'RAM', - binpath = 'build/kernel/kernel.elf', local = False ) - - ### shared global vsegs for kernel - - mapping.addGlobal( 'seg_kernel_data', kernel_data_vbase, kernel_data_size, - 'C_W_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', - binpath = 'build/kernel/kernel.elf', local = False ) - - mapping.addGlobal( 'seg_kernel_uncdata', kernel_uncdata_vbase, kernel_uncdata_size, - '__W_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', - binpath = 'build/kernel/kernel.elf', local = False ) + binpath = 'build/kernel/kernel.elf' ) + + mapping.addGlobal( 'seg_kernel_data' , kernel_data_vbase , kernel_data_size , 'C_W_', + vtype = 'ELF' , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' ) + + mapping.addGlobal( 'seg_kernel_uncdata', kernel_uncdata_vbase, kernel_uncdata_size, '__W_', + vtype = 'ELF' , x = 0, y = 0, pseg = 'RAM', binpath = 'build/kernel/kernel.elf' ) ### global vsegs for external peripherals / identity mapping - mapping.addGlobal( 'seg_iob', iob_base, iob_size, '__W_', - vtype = 'PERI', x = 0, y = 0, pseg = 'IOB', - identity = True ) - - mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size, '__W_', - vtype = 'PERI', x = 0, y = 0, pseg = 'BDV', - identity = True ) - - mapping.addGlobal( 'seg_tty', tty_base, tty_size, '__W_', - vtype = 'PERI', x = 0, y = 0, pseg = 'TTY', - identity = True ) - - mapping.addGlobal( 'seg_nic', nic_base, nic_size, '__W_', - vtype = 'PERI', x = 0, y = 0, pseg = 'NIC', - identity = True ) - - mapping.addGlobal( 'seg_cma', cma_base, cma_size, '__W_', - vtype = 'PERI', x = 0, y = 0, pseg = 'CMA', - identity = True ) - - mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, '__W_', - vtype = 'PERI', x = 0, y = 0, pseg = 'FBF', - identity = True ) - - mapping.addGlobal( 'seg_pic', pic_base, pic_size, '__W_', - vtype = 'PERI', x = 0, y = 0, pseg = 'PIC', - identity = True ) - - mapping.addGlobal( 'seg_rom', rom_base, rom_size, 'CXW_', - vtype = 'PERI', x = 0, y = 0, pseg = 'ROM', - identity = True ) - - ### global vsegs for internal peripherals, and for schedulers + mapping.addGlobal( 'seg_iob', iob_base, iob_size, '__W_', + vtype = 'PERI', x = 0, y = 0, pseg = 'IOB', identity = True ) + + mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size, '__W_', + vtype = 'PERI', x = 0, y = 0, pseg = 'BDV', identity = True ) + + mapping.addGlobal( 'seg_tty', tty_base, tty_size, '__W_', + vtype = 'PERI', x = 0, y = 0, pseg = 'TTY', identity = True ) + + mapping.addGlobal( 'seg_nic', nic_base, nic_size, '__W_', + vtype = 'PERI', x = 0, y = 0, pseg = 'NIC', identity = True ) + + mapping.addGlobal( 'seg_cma', cma_base, cma_size, '__W_', + vtype = 'PERI', x = 0, y = 0, pseg = 'CMA', identity = True ) + + mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, '__W_', + vtype = 'PERI', x = 0, y = 0, pseg = 'FBF', identity = True ) + + mapping.addGlobal( 'seg_pic', pic_base, pic_size, '__W_', + vtype = 'PERI', x = 0, y = 0, pseg = 'PIC', identity = True ) + + ### global vsegs for internal peripherals, and for schedulers ### name is indexed by (x,y) / vbase address is incremented by (cluster_xy * peri_increment) @@ -319,4 +301,7 @@ offset = cluster_xy * peri_increment + mapping.addGlobal( 'seg_rom_%d_%d' %(x,y), rom_base + offset, rom_size, + 'CX__', vtype = 'PERI' , x = x , y = y , pseg = 'ROM' ) + mapping.addGlobal( 'seg_xcu_%d_%d' %(x,y), xcu_base + offset, xcu_size, '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'XCU' ) @@ -348,5 +333,5 @@ # print mapping.giet_vsegs() - + # Local Variables: Index: /branches/reconfiguration/platforms/tsar_generic_iob/conf/preloader_4c1p/Makefile =================================================================== --- /branches/reconfiguration/platforms/tsar_generic_iob/conf/preloader_4c1p/Makefile (revision 748) +++ /branches/reconfiguration/platforms/tsar_generic_iob/conf/preloader_4c1p/Makefile (revision 748) @@ -0,0 +1,11 @@ +PRELOADER_PATH := $(TSARPATH)/softs/tsar_boot +ARGS := " PLATFORM_DIR=$(PWD)" +ARGS += " SOCLIB=1" +ARGS += " USE_DT=0" + +all: + make -C $(PRELOADER_PATH) $(ARGS) + +clean: + make -C $(PRELOADER_PATH) $(ARGS) clean + Index: /branches/reconfiguration/platforms/tsar_generic_iob/conf/preloader_4c1p/defs_platform.h =================================================================== --- /branches/reconfiguration/platforms/tsar_generic_iob/conf/preloader_4c1p/defs_platform.h (revision 748) +++ /branches/reconfiguration/platforms/tsar_generic_iob/conf/preloader_4c1p/defs_platform.h (revision 748) @@ -0,0 +1,17 @@ +#define NB_PROCS 1 +#define NB_CLUSTERS 4 + +#define IRQ_PER_PROC 4 + +#define USE_IOB 1 +#define CACHE_COHERENCE 1 +#define CACHE_LINE_SIZE 64 // bytes + +#define RESET_DEBUG 0 + +#define ICU_PADDR_BASE 0xB0000000 +#define MCC_PADDR_BASE 0xB2000000 +#define IOC_PADDR_BASE 0xB3000000 +#define TTY_PADDR_BASE 0xB4000000 + +#define SYSCLK_FREQ 50000000 Index: /branches/reconfiguration/platforms/tsar_generic_iob/conf/preloader_4c1p/ldscript =================================================================== --- /branches/reconfiguration/platforms/tsar_generic_iob/conf/preloader_4c1p/ldscript (revision 748) +++ /branches/reconfiguration/platforms/tsar_generic_iob/conf/preloader_4c1p/ldscript (revision 748) @@ -0,0 +1,35 @@ +/********************************************************** + File : ldscript + Author : Cesar Fuguet + Date : June 2011 +**********************************************************/ + +/* Definition of the base address for code segment */ + +seg_code_base = 0xBFC00000; +seg_stack_base = 0x03F00000; + +/* Grouping sections into segments */ + +ENTRY(reset) + +SECTIONS +{ + . = seg_code_base; + .text : + { + *(.reset) + *(.rodata) + *(.rodata.*) + . = ALIGN(0x4); + dtb_addr = .; + INCLUDE "build/platform.ld"; + } + + . = seg_stack_base; + .bss ALIGN(0x4) (NOLOAD) : + { + *(.bss) + *(.data) + } +} Index: /branches/reconfiguration/platforms/tsar_generic_iob/conf/preloader_4c2p/Makefile =================================================================== --- /branches/reconfiguration/platforms/tsar_generic_iob/conf/preloader_4c2p/Makefile (revision 748) +++ /branches/reconfiguration/platforms/tsar_generic_iob/conf/preloader_4c2p/Makefile (revision 748) @@ -0,0 +1,11 @@ +PRELOADER_PATH := $(TSARPATH)/softs/tsar_boot +ARGS := " PLATFORM_DIR=$(PWD)" +ARGS += " SOCLIB=1" +ARGS += " USE_DT=0" + +all: + make -C $(PRELOADER_PATH) $(ARGS) + +clean: + make -C $(PRELOADER_PATH) $(ARGS) clean + Index: /branches/reconfiguration/platforms/tsar_generic_iob/conf/preloader_4c2p/defs_platform.h =================================================================== --- /branches/reconfiguration/platforms/tsar_generic_iob/conf/preloader_4c2p/defs_platform.h (revision 748) +++ /branches/reconfiguration/platforms/tsar_generic_iob/conf/preloader_4c2p/defs_platform.h (revision 748) @@ -0,0 +1,17 @@ +#define NB_PROCS 2 +#define NB_CLUSTERS 4 + +#define IRQ_PER_PROC 4 + +#define USE_IOB 1 +#define CACHE_COHERENCE 1 +#define CACHE_LINE_SIZE 64 // bytes + +#define RESET_DEBUG 0 + +#define ICU_PADDR_BASE 0xB0000000 +#define MCC_PADDR_BASE 0xB2000000 +#define IOC_PADDR_BASE 0xB3000000 +#define TTY_PADDR_BASE 0xB4000000 + +#define SYSCLK_FREQ 50000000 Index: /branches/reconfiguration/platforms/tsar_generic_iob/conf/preloader_4c2p/ldscript =================================================================== --- /branches/reconfiguration/platforms/tsar_generic_iob/conf/preloader_4c2p/ldscript (revision 748) +++ /branches/reconfiguration/platforms/tsar_generic_iob/conf/preloader_4c2p/ldscript (revision 748) @@ -0,0 +1,35 @@ +/********************************************************** + File : ldscript + Author : Cesar Fuguet + Date : June 2011 +**********************************************************/ + +/* Definition of the base address for code segment */ + +seg_code_base = 0xBFC00000; +seg_stack_base = 0x03F00000; + +/* Grouping sections into segments */ + +ENTRY(reset) + +SECTIONS +{ + . = seg_code_base; + .text : + { + *(.reset) + *(.rodata) + *(.rodata.*) + . = ALIGN(0x4); + dtb_addr = .; + INCLUDE "build/platform.ld"; + } + + . = seg_stack_base; + .bss ALIGN(0x4) (NOLOAD) : + { + *(.bss) + *(.data) + } +} Index: /branches/reconfiguration/platforms/tsar_generic_iob/soclib.conf =================================================================== --- /branches/reconfiguration/platforms/tsar_generic_iob/soclib.conf (revision 748) +++ /branches/reconfiguration/platforms/tsar_generic_iob/soclib.conf (revision 748) @@ -0,0 +1,13 @@ +cflags = config.default.toolchain.cflags \ + + ['-DUSE_OPENMP=0'] \ +# + ['-ggdb'] + +config.default.toolchain.set( + "cflags", cflags +) + +import os +tsar_path = os.environ['TSARPATH'] +config.addDescPath(tsar_path + "/trunk/lib") +config.addDescPath(tsar_path + "/trunk/communication") +config.addDescPath(tsar_path + "/trunk/modules") Index: /branches/reconfiguration/platforms/tsar_generic_iob/top.cpp =================================================================== --- /branches/reconfiguration/platforms/tsar_generic_iob/top.cpp (revision 747) +++ /branches/reconfiguration/platforms/tsar_generic_iob/top.cpp (revision 748) @@ -9,5 +9,4 @@ // an external bus (i.e. Hypertransport) to access 7 external peripherals: // -// - BROM : boot ROM // - FBUF : Frame Buffer // - MTTY : multi TTY (one channel) @@ -44,4 +43,5 @@ // - IOPIC HWI[8] connected to IRQ_BDEV // - IOPIC HWI[9] connected to IRQ_TTY_RX[0] +// - IOPIC HWI[31:9] unused (grounded) // // Besides the external peripherals, each cluster contains one XICU component, @@ -228,5 +228,5 @@ //////////////////////i///////////////////////////////////// -#define MAX_FROZEN_CYCLES 20000000 +#define MAX_FROZEN_CYCLES 200000 ///////////////////////////////////////////////////////// @@ -276,5 +276,6 @@ #define INT_XICU_TGT_ID 1 #define INT_MDMA_TGT_ID 2 -#define INT_IOBX_TGT_ID 3 +#define INT_BROM_TGT_ID 3 +#define INT_IOBX_TGT_ID 4 #define INT_PROC_INI_ID 0 // from 0 to (NB_PROCS_MAX-1) @@ -299,9 +300,8 @@ #define IOX_MNIC_TGT_ID 2 #define IOX_CDMA_TGT_ID 3 -#define IOX_BROM_TGT_ID 4 -#define IOX_MTTY_TGT_ID 5 -#define IOX_IOPI_TGT_ID 6 -#define IOX_IOB0_TGT_ID 7 -#define IOX_IOB1_TGT_ID 8 +#define IOX_MTTY_TGT_ID 4 +#define IOX_IOPI_TGT_ID 5 +#define IOX_IOB0_TGT_ID 6 +#define IOX_IOB1_TGT_ID 7 #define IOX_BDEV_INI_ID 0 @@ -349,5 +349,5 @@ if ((strcmp(argv[n],"-NCYCLES") == 0) && (n+1> 4; size_t y = debug_memc_id & 0xF; @@ -377,5 +377,5 @@ else if ((strcmp(argv[n],"-XRAMID") == 0) && (n+1> 4; size_t y = debug_xram_id & 0xF; @@ -388,9 +388,9 @@ else if ((strcmp(argv[n],"-IOB") == 0) && (n+1> 4; @@ -404,14 +404,14 @@ else if ((strcmp(argv[n], "-THREADS") == 0) && ((n+1) < argc)) { - threads_nr = atoi(argv[n+1]); + threads_nr = strtol(argv[n+1], NULL, 0); threads_nr = (threads_nr < 1) ? 1 : threads_nr; } else if ((strcmp(argv[n], "-FROZEN") == 0) && (n+1 < argc)) { - frozen_cycles = atoi(argv[n+1]); + frozen_cycles = strtol(argv[n+1], NULL, 0); } else if ((strcmp(argv[n], "-PERIOD") == 0) && (n+1 < argc)) { - debug_period = atoi(argv[n+1]); + debug_period = strtol(argv[n+1], NULL, 0); } else @@ -436,4 +436,12 @@ } + // Activate Distributed Boot (set by environment variable) + // When this is activated, every processor boots with its instruction and data + // physical address extension register initialized to its cluster index + // (X_LOCAL, Y_LOCAL). To support this feature, a distributed ROM is + // implemented in each cluster. + + const bool distributed_boot = (getenv("DISTRIBUTED_BOOT") != NULL); + // checking hardware parameters assert( (XMAX <= 16) and @@ -466,4 +474,5 @@ << " - RAM_LATENCY = " << XRAM_LATENCY << std::endl << " - MAX_FROZEN = " << frozen_cycles << std::endl + << " - DIST_BOOT = " << distributed_boot << std::endl << " - DEBUG_PROCID = " << debug_proc_id << std::endl << " - DEBUG_MEMCID = " << debug_memc_id << std::endl @@ -544,4 +553,9 @@ IntTab(cluster(x,y), INT_MDMA_TGT_ID), not cacheable)); + std::ostringstream sbrom; + sbrom << "int_seg_brom_" << x << "_" << y; + maptab_int.add(Segment(sbrom.str(), SEG_ROM_BASE+offset, SEG_ROM_SIZE, + IntTab(cluster(x,y), INT_BROM_TGT_ID), cacheable)); + // the following segments are only defined in cluster_iob0 or in cluster_iob1 @@ -572,9 +586,4 @@ maptab_int.add(Segment(snic.str(), SEG_NIC_BASE+offset, SEG_NIC_SIZE, IntTab(cluster(x,y), INT_IOBX_TGT_ID), not cacheable)); - - std::ostringstream srom; - srom << "int_seg_brom_" << x << "_" << y; - maptab_int.add(Segment(srom.str(), SEG_ROM_BASE+offset, SEG_ROM_SIZE, - IntTab(cluster(x,y), INT_IOBX_TGT_ID), cacheable )); std::ostringstream sdma; @@ -698,6 +707,4 @@ maptab_iox.add(Segment("iox_seg_cdma_0", SEG_CMA_BASE + iob0_base, SEG_CMA_SIZE, IntTab(0, IOX_CDMA_TGT_ID), false)); - maptab_iox.add(Segment("iox_seg_brom_0", SEG_ROM_BASE + iob0_base, SEG_ROM_SIZE, - IntTab(0, IOX_BROM_TGT_ID), false)); maptab_iox.add(Segment("iox_seg_iopi_0", SEG_PIC_BASE + iob0_base, SEG_PIC_SIZE, IntTab(0, IOX_IOPI_TGT_ID), false)); @@ -718,6 +725,4 @@ maptab_iox.add(Segment("iox_seg_cdma_1", SEG_CMA_BASE + iob1_base, SEG_CMA_SIZE, IntTab(0, IOX_CDMA_TGT_ID), false)); - maptab_iox.add(Segment("iox_seg_brom_1", SEG_ROM_BASE + iob1_base, SEG_ROM_SIZE, - IntTab(0, IOX_BROM_TGT_ID), false)); maptab_iox.add(Segment("iox_seg_iopi_1", SEG_PIC_BASE + iob1_base, SEG_PIC_SIZE, IntTab(0, IOX_IOPI_TGT_ID), false)); @@ -813,5 +818,4 @@ VciSignals signal_vci_tgt_fbuf("signal_vci_tgt_fbuf"); VciSignals signal_vci_tgt_mnic("signal_vci_tgt_mnic"); - VciSignals signal_vci_tgt_brom("signal_vci_tgt_brom"); VciSignals signal_vci_tgt_bdev("signal_vci_tgt_bdev"); VciSignals signal_vci_tgt_cdma("signal_vci_tgt_cdma"); @@ -901,5 +905,5 @@ const size_t nb_iox_initiators = (cluster_iob0 != cluster_iob1) ? 5 : 4; - const size_t nb_iox_targets = (cluster_iob0 != cluster_iob1) ? 9 : 8; + const size_t nb_iox_targets = (cluster_iob0 != cluster_iob1) ? 8 : 7; // IOX network @@ -909,10 +913,5 @@ nb_iox_targets, nb_iox_initiators ); - // boot ROM - VciSimpleRom* brom; - brom = new VciSimpleRom( "brom", - IntTab(0, IOX_BROM_TGT_ID), - maptab_iox, - loader ); + // Network Controller VciMultiNic* mnic; @@ -976,4 +975,5 @@ IntTab(0, IOX_IOPI_TGT_ID), 32 ); // number of input HWI + // Clusters TsarIobClusterp_to_tgt[IOX_FBUF_TGT_ID] (signal_vci_tgt_fbuf); iox_network->p_to_tgt[IOX_MNIC_TGT_ID] (signal_vci_tgt_mnic); - iox_network->p_to_tgt[IOX_BROM_TGT_ID] (signal_vci_tgt_brom); iox_network->p_to_tgt[IOX_BDEV_TGT_ID] (signal_vci_tgt_bdev); iox_network->p_to_tgt[IOX_CDMA_TGT_ID] (signal_vci_tgt_cdma); @@ -1138,11 +1140,4 @@ std::cout << " - MNIC connected" << std::endl; - - // BROM connexion - brom->p_clk (signal_clk); - brom->p_resetn (signal_resetn); - brom->p_vci (signal_vci_tgt_brom); - - std::cout << " - BROM connected" << std::endl; // MTTY connexion @@ -1423,5 +1418,5 @@ // Monitor a specific address for one L2 cache - // clusters[0][0]->memc->cache_monitor( 0x1542c0ULL, true ); // single word + // clusters[0][0]->memc->cache_monitor( 0x170000ULL); // Monitor a specific address for one XRAM @@ -1440,6 +1435,6 @@ size_t x = cluster_xy >> 4; size_t y = cluster_xy & 0xF; - - clusters[x][y]->proc[l]->print_trace(0x40); + + clusters[x][y]->proc[l]->print_trace(1); std::ostringstream proc_signame; proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; @@ -1451,27 +1446,12 @@ clusters[x][y]->signal_int_vci_tgt_xicu.print_trace(xicu_signame.str()); - clusters[x][y]->mdma->print_trace(); - std::ostringstream mdma_signame; - mdma_signame << "[SIG]MDMA_" << x << "_" << y; - clusters[x][y]->signal_int_vci_tgt_mdma.print_trace(mdma_signame.str()); - - // local interrupts in cluster(x,y) - if( clusters[x][y]->signal_irq_memc.read() ) - std::cout << "### IRQ_MMC_" << std::dec << x << "_" << y - << " ACTIVE" << std::endl; - - for ( size_t c = 0 ; c < NB_DMA_CHANNELS ; c++ ) - { - if( clusters[x][y]->signal_irq_mdma[c].read() ) - std::cout << "### IRQ_DMA_" << std::dec << x << "_" << y << "_" << c - << " ACTIVE" << std::endl; - } - - for ( size_t c = 0 ; c < NB_PROCS_MAX ; c++ ) - { - if( clusters[x][y]->signal_proc_it[c].read() ) - std::cout << "### IRQ_PROC_" << std::dec << x << "_" << y << "_" << c - << " ACTIVE" << std::endl; - } +// clusters[x][y]->mdma->print_trace(); +// std::ostringstream mdma_signame; +// mdma_signame << "[SIG]MDMA_" << x << "_" << y; +// clusters[x][y]->signal_int_vci_tgt_mdma.print_trace(mdma_signame.str()); + + if( clusters[x][y]->signal_proc_it[l].read() ) + std::cout << "### IRQ_PROC_" << std::dec + << x << "_" << y << "_" << l << " ACTIVE" << std::endl; } @@ -1521,6 +1501,6 @@ // clusters[0][0]->signal_ram_vci_ini_iobx.print_trace( "[SIG]IOB0_RAM_INI"); -// signal_vci_ini_iob0.print_trace("[SIG]IOB0_IOX_INI"); -// signal_vci_tgt_iob0.print_trace("[SIG]IOB0_IOX_TGT"); + signal_vci_ini_iob0.print_trace("[SIG]IOB0_IOX_INI"); + signal_vci_tgt_iob0.print_trace("[SIG]IOB0_IOX_TGT"); // cdma->print_trace(); @@ -1528,7 +1508,4 @@ // signal_vci_ini_cdma.print_trace("[SIG]IOX_CDMA_INI"); -// brom->print_trace(); -// signal_vci_tgt_brom.print_trace("[SIG]IOX_BROM_TGT"); - // mtty->print_trace(); // signal_vci_tgt_mtty.print_trace("[SIG]IOX_MTTY_TGT"); @@ -1538,6 +1515,6 @@ signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); -// mnic->print_trace(); -// signal_vci_tgt_mnic.print_trace("[SIG]MNIC_TGT"); + mnic->print_trace(); + signal_vci_tgt_mnic.print_trace("[SIG]MNIC_TGT"); // fbuf->print_trace(); Index: /branches/reconfiguration/platforms/tsar_generic_iob/top.desc =================================================================== --- /branches/reconfiguration/platforms/tsar_generic_iob/top.desc (revision 747) +++ /branches/reconfiguration/platforms/tsar_generic_iob/top.desc (revision 748) @@ -28,5 +28,5 @@ uses = [ # cluster - Uses('caba:tsar_iob_cluster', + Uses('caba:reconfiguration:tsar_iob_cluster', vci_data_width_int = vci_cell_size_int, vci_data_width_ext = vci_cell_size_ext, Index: /branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd =================================================================== --- /branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd (revision 747) +++ /branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd (revision 748) @@ -2,5 +2,5 @@ # -*- python -*- -Module('caba:tsar_iob_cluster', +Module('caba:reconfiguration:tsar_iob_cluster', classname = 'soclib::caba::TsarIobCluster', @@ -48,4 +48,7 @@ Uses('caba:vci_multi_dma', + cell_size = parameter.Reference('vci_data_width_int')), + + Uses('caba:vci_simple_rom', cell_size = parameter.Reference('vci_data_width_int')), Index: /branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h =================================================================== --- /branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h (revision 747) +++ /branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h (revision 748) @@ -32,4 +32,5 @@ #include "vci_cc_vcache_wrapper.h" #include "vci_io_bridge.h" +#include "vci_simple_rom.h" namespace soclib { namespace caba { @@ -94,4 +95,5 @@ VciSignals signal_int_vci_tgt_xicu; VciSignals signal_int_vci_tgt_mdma; + VciSignals signal_int_vci_tgt_brom; VciSignals signal_int_vci_tgt_iobx; @@ -146,4 +148,6 @@ VciMultiDma* mdma; + VciSimpleRom* brom; + VciLocalCrossbar* int_xbar_d; @@ -205,4 +209,5 @@ size_t int_xicu_tgt_id, size_t int_mdma_tgt_id, + size_t int_brom_tgt_id, size_t int_iobx_tgt_id, size_t int_proc_ini_id, @@ -227,4 +232,6 @@ size_t xcu_nb_inputs, + bool distboot, + const Loader &loader, // loader for XRAM Index: /branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp =================================================================== --- /branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp (revision 747) +++ /branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp (revision 748) @@ -50,4 +50,5 @@ size_t int_xicu_tgt_id, // local index size_t int_mdma_tgt_id, // local index + size_t int_brom_tgt_id, // local index size_t int_iobx_tgt_id, // local index @@ -73,5 +74,7 @@ size_t xcu_nb_inputs, - const Loader &loader, + bool distboot, + + const Loader &loader, uint32_t frozen_cycles, @@ -137,4 +140,12 @@ debug_start_cycle, proc_debug_ok); + + // initialize physical address extension with cluster ID when using + // distributed boot + if (distboot) + { + proc[p]->set_dcache_paddr_ext_reset(cluster_id); + proc[p]->set_icache_paddr_ext_reset(cluster_id); + } } @@ -193,7 +204,17 @@ nb_dmas); // number of IRQs + /////////// DISTRIBUTED BOOT ROM + std::ostringstream s_brom; + s_brom << "brom_" << x_id << "_" << y_id; + brom = new VciSimpleRom( + s_brom.str().c_str(), + IntTab(cluster_id, int_brom_tgt_id), + mt_int, + loader, + x_width + y_width); // msb drop bits + /////////// Direct LOCAL_XBAR(S) size_t nb_direct_initiators = is_io ? nb_procs + 2 : nb_procs + 1; - size_t nb_direct_targets = is_io ? 4 : 3; + size_t nb_direct_targets = is_io ? 5 : 4; std::ostringstream s_int_xbar_d; @@ -432,4 +453,5 @@ int_xbar_d->p_to_target[int_xicu_tgt_id] (signal_int_vci_tgt_xicu); int_xbar_d->p_to_target[int_mdma_tgt_id] (signal_int_vci_tgt_mdma); + int_xbar_d->p_to_target[int_brom_tgt_id] (signal_int_vci_tgt_brom); int_xbar_d->p_to_initiator[int_mdma_ini_id] (signal_int_vci_ini_mdma); for (size_t p = 0; p < nb_procs; p++) @@ -550,4 +572,9 @@ mdma->p_irq[i] (signal_irq_mdma[i]); + /////////////////////////////////// BROM + brom->p_clk (this->p_clk); + brom->p_resetn (this->p_resetn); + brom->p_vci (signal_int_vci_tgt_brom); + //////////////////////////// RAM network CMD & RSP routers ram_router_cmd->p_clk (this->p_clk); @@ -626,10 +653,10 @@ // Local Variables: -// tab-width: 3 -// c-basic-offset: 3 +// tab-width: 4 +// c-basic-offset: 4 // c-file-offsets:((innamespace . 0)(inline-open . 0)) // indent-tabs-mode: nil // End: -// vim: filetype=cpp:expandtab:shiftwidth=3:tabstop=3:softtabstop=3 - +// vim: filetype=cpp:expandtab:shiftwidth=4:tabstop=4:softtabstop=4 +