Index: trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
===================================================================
--- trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 740)
+++ trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 752)
@@ -29,4 +29,6 @@
 
 #include <cassert>
+#include <signal.h>
+
 #include "arithmetics.h"
 #include "../include/vci_cc_vcache_wrapper.h"
@@ -1142,4 +1144,5 @@
             // We register processor request
             r_icache_vaddr_save = m_ireq.addr;
+            paddr = (paddr_t) m_ireq.addr;
 
             // sytematic itlb access (if activated)
@@ -1157,15 +1160,7 @@
                                             &tlb_set ); // unused
             }
-            else
-            {
-                if (vci_param::N > 32)
-                {
-                    paddr =  (paddr_t)m_ireq.addr |
-                            ((paddr_t)r_icache_paddr_ext.read() << 32);
-                }
-                else
-                {
-                    paddr = (paddr_t)m_ireq.addr;
-                }
+            else if (vci_param::N > 32)
+            {
+                paddr = paddr | ((paddr_t) r_icache_paddr_ext.read() << 32);
             }
 
@@ -2249,5 +2244,5 @@
                       // updt_request, wbuf_request, wbuf_write_miss.
     {
-        paddr_t     paddr;                          // physical address
+        paddr_t     paddr;
         pte_info_t 	tlb_flags;
         size_t     	tlb_way;
@@ -2267,4 +2262,5 @@
 
         // physical address computation : systematic DTLB access if activated)
+        paddr = (paddr_t) m_dreq.addr;
         if ( m_dreq.valid )
         {
@@ -2283,5 +2279,4 @@
             else                                    // identity mapping
             {
-                paddr = (paddr_t)m_dreq.addr;
                 // we take into account the paddr extension
                 if (vci_param::N > 32) 
@@ -2293,4 +2288,5 @@
         if ( r_mmu_mode.read() & DATA_CACHE_MASK)
         {
+
             if ( m_dreq.valid and r_dcache_updt_req.read() ) // read DIR and write DATA
             {
Index: trunk/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h
===================================================================
--- trunk/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h	(revision 740)
+++ trunk/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h	(revision 752)
@@ -650,4 +650,6 @@
               {
                   m_cache_data[i][j] = new uint32_t [words];
+                  // Init to avoid potential errors from memory checkers
+                  std::memset(m_cache_data[i][j], 0, sizeof(uint32_t) * words);
               }
           }
Index: trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
===================================================================
--- trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	(revision 740)
+++ trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	(revision 752)
@@ -404,6 +404,6 @@
 
       // instrumentation counters
-      uint32_t     m_cpt_cycles;         // Counter of cycles
-      uint32_t     m_cpt_reset_count;    // Cycle at which the counters were last reset
+      uint64_t     m_cpt_cycles;         // Counter of cycles
+      uint64_t     m_cpt_reset_count;    // Cycle at which the counters were last reset
 
       // Counters accessible in software (not yet but eventually)