Changeset 767 for branches

Timestamp:

Aug 25, 2014, 5:58:16 PM (10 years ago)

Author:

devigne

Message:

RWT commit :

• Merge with trunk.

• Cosmetic

• Bugfix in state WRITE_IVT_LOCK_HIT_WB.

MemCache? records invalidation in IVT in this state but we do not check that
the IVT was full. Thus invalidation was issued without actually recorded in the
query IVT ...

• Bugfix :

When a NCC line owned by a L1 cache with srcid != 0 was removed from MemCache?,
the owner field was reset to 0. If this same L1 cache was sending a read to
retrieve this line the MemCache? sent this line on CC mode.

• Bugfix :

The MemCache? reset the 'inst' field to 0 when solving a
invalidation due to a change of state of line (NCC to CC).
But a line can be NCC (ie contained in a DATA cache) then asked by INST cache,
this read triggers a transition NCC to CC but we must save the nature of this read.
Now this information is stored in a register (r_read_to_cleanup_inst).

• Add a counter for the number of minimum inputs available

in the heap. This counter indicates whether the heap size of 4096 is relevant.

Location:

branches/RWT

Files:

• lib/generic_cache_tsar/include/generic_cache.h (modified) (1 diff)
• modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (modified) (4 diffs)
• modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (modified) (46 diffs)
• modules/vci_mem_cache/caba/source/include/update_tab.h (modified) (1 prop)
• modules/vci_mem_cache/caba/source/include/vci_mem_cache.h (modified) (13 diffs, 1 prop)
• modules/vci_mem_cache/caba/source/include/xram_transaction.h (modified) (2 diffs)
• modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (modified) (96 diffs, 1 prop)

branches/RWT/lib/generic_cache_tsar/include/generic_cache.h

@@ -586 +586 @@
                       data_t    data)
     {
-       /**/ //std::cout << "write cache : way = "<<way<<" | set = "<<set<<" | word = "<<word<<" | data = "<<(uint32_t)data << std::endl;
         cache_data(way, set, word) = data;
         cache_set_lru(way, set);

branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h

@@ -280 +280 @@
     };
 
-//    enum transaction_type_d_e
-//    {
-//        // b0 : 1 if cached
-//        // b1 : 1 if instruction
-//        TYPE_DATA_UNC     = 0x0,
-//        TYPE_DATA_MISS    = 0x1,
-//        TYPE_INS_UNC      = 0x2,
-//        TYPE_INS_MISS     = 0x3,
-//    };
-
-    //////////////////MODIFIED////////////////
+
+    // cache line status
     enum content_line_cache_status_e
     {
@@ -522 +513 @@
     sc_signal<size_t>       r_dcache_cc_send_updt_tab_idx;  // DCACHE cc_send update table index
     
-    // special registers for ODCCP/RWT
-    sc_signal<bool>         r_dcache_cc_cleanup_updt_data;          // Register for cleanup with data (wb updt)
-    sc_signal<bool>         r_dcache_cc_cleanup_line_ncc;          // Register for cleanup with data (wb updt)
-    sc_signal<bool>         r_dcache_miss_victim_no_coherence;      // Register for victim in no coherence mode
-    sc_signal<bool>         r_dcache_line_no_coherence;             // Register for line current in no coherence mode
+    // special registers for RWT
+    sc_signal<bool>         r_dcache_cc_cleanup_updt_data;     // Register for cleanup with data (wb updt)
+    sc_signal<bool>         r_dcache_cc_cleanup_line_ncc;      // Register for cleanup with data (wb updt)
+    sc_signal<bool>         r_dcache_miss_victim_no_coherence; // Register for victim in no coherence mode
+    sc_signal<bool>         r_dcache_line_no_coherence;        // Register for line current in no coherence mode
     sc_signal<bool>         r_dcache_dirty_save;             
     sc_signal<uint32_t>     r_cc_send_cpt_word;
@@ -536 +527 @@
     sc_signal<paddr_t>      r_dcache_xtn_data_addr;
     sc_signal<uint32_t>     r_dcache_xtn_data_cpt;
+    sc_signal<bool>         r_dcache_read_state;
+
     // dcache directory extension
-    ///////////////////////////MODIFIED///////////////////////////////////////////////////
-    //bool                    *r_dcache_in_tlb;           // copy exist in dtlb or itlb
-    //bool                    *r_dcache_contains_ptd;     // cache line contains a PTD
     int                     *r_dcache_content_state; // content state of one cache line
-    int                     *r_dcache_dirty_word;    
-    bool                    *r_dcache_zombi_ncc;     
+    // Stats
+    int                     *r_dcache_dirty_word;    // use for compute number of words dirty per cleanup_data
+    bool                    *r_dcache_zombi_ncc;     // use for compute number of blocked write on ncc zombi line
     //////////////////////////////////////////////////////////////////////////////////////
 
-    //RWT
-    sc_signal<bool>         r_dcache_read_state;
-   
-     ///////////////////////////////////
+    ///////////////////////////////////
     // Physical address extension for data access
     sc_signal<uint32_t>     r_dcache_paddr_ext;             // CP2 register (if vci_address > 32)
@@ -574 +562 @@
     //RWT
     GenericFifo<bool>       r_vci_rsp_fifo_rpktid;
-
     GenericFifo<uint32_t>   r_cc_send_data_fifo;   
 

branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

@@ -346 +346 @@
       r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
       r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
-//     r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
-//     r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
-//     r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
       r_dcache_tlb_way("r_dcache_tlb_way"),
       r_dcache_tlb_set("r_dcache_tlb_set"),
@@ -425 +422 @@
 
     assert( (itlb_sets == dtlb_sets) and
-             "itlb_sets and dtlb_sets parameters must be etqual");
+             "itlb_sets and dtlb_sets parameters must be equal");
 
     assert( (itlb_ways == dtlb_ways) and
-             "itlb_ways and dtlb_ways parameters must be etqual");
+             "itlb_ways and dtlb_ways parameters must be equal");
 
     r_mmu_params = (uint32_log2(m_dtlb_ways)   << 29)   | (uint32_log2(m_dtlb_sets)   << 25) |
@@ -470 +467 @@
 /////////////////////////////////////
 {
-    ////////////MODIFIED/////////////
-    //delete [] r_dcache_in_tlb;
-    //delete [] r_dcache_contains_ptd;
     delete [] r_dcache_content_state;
     delete [] r_dcache_dirty_word;
     delete [] r_dcache_zombi_ncc;
     /////////////////////////////////
-    print_stats();
+    //print_stats();
 }
 
@@ -783 +777 @@
         for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++)
         {
-            // MODIFIED
-            //r_dcache_in_tlb[i]        = false;
-            //r_dcache_contains_ptd[i]  = false;
             r_dcache_content_state[i] = LINE_CACHE_DATA_NOT_DIRTY;
             r_dcache_dirty_word[i]    = 0;
@@ -2246 +2237 @@
     m_drsp.error = false;
     m_drsp.rdata = 0;
-    //if(m_cpt_total_cycles % 1000000 == 0 ) r_dcache.printTrace();
 
     switch ( r_dcache_fsm.read() )
@@ -2381 +2371 @@
             size_t way = r_dcache_save_cache_way.read();
             size_t set = r_dcache_save_cache_set.read();
-            // MODIFIED
-            //if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
-            //{
+
             if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB )
             {
@@ -2390 +2378 @@
                     r_dcache_tlb_inval_line  = r_dcache_save_paddr.read()>>
                                            (uint32_log2(m_dcache_words<<2));
-                // MODIFIED RWT: DIRTY
-                    //r_dcache_in_tlb[way*m_dcache_sets+set] = false;
+
                 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
             }
-            // MODIFIED
-            //else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
-            //{
             else if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD )
             {
                 r_itlb.reset();
                 r_dtlb.reset();
-                // MODIFIED
-                    //r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
+
                 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
             }
@@ -2802 +2785 @@
 m_cpt_data_miss++;
 #endif
-                                /*ODCCP*/
-                                //std::cout << "\t\t\t\t\tCACHE MISS NEED READ for : " << name() << std::endl;
                                 // request a VCI DMISS transaction
                                 r_dcache_vci_paddr    = paddr;
@@ -2832 +2813 @@
 m_cpt_data_read++;
 #endif
-                                /*if ((tlb_flags.s == 0) and (r_mmu_mode.read() & DATA_TLB_MASK) and (cache_state == CACHE_SLOT_STATE_VALID_CC))
-                                {
-                                    //ODCCP
-                                    std::cout << "READ NO COHERENCE on " << name() << " | paddr = " << std::hex << paddr << std::dec << " | way = " << cache_way << " | set = " << cache_set << " | at cycle : "<< m_cpt_total_cycles << std::endl;
-                                    r_dcache.write_dir(cache_way,
-                                                       cache_set,
-                                                       CACHE_SLOT_STATE_VALID_NCC);
-                                }*/
                                 // returns data to processor
                                 m_drsp.valid   = true;
@@ -2883 +2856 @@
                         r_dcache_ll_rsp_count = 0;
                         r_dcache_fsm          = DCACHE_LL_WAIT;
-                        /*ODCCP*/
-                        //std::cout << "LL on " << name() << " | paddr = " << std::hex << paddr << std::dec << " | at cycle : " << m_cpt_total_cycles << std::endl;
 
                     }// end LL
@@ -2973 +2944 @@
                                 m_cpt_data_write_on_zombi++;
                             }
-                            else
+                            else // Miss in DCACHE
                             {
-                               m_cpt_data_write_miss++;
-                               
-                               m_drsp.valid = true;
-                               wbuf_request = true;
-                               updt_request = false;
+                                m_drsp.valid = true;
+                                wbuf_request = true;
+                                updt_request = false;
+                                m_cpt_data_write_miss++;
                             }
                         }
@@ -3155 +3125 @@
                        &word,
                        &cache_state );
+
 #ifdef INSTRUMENTATION
 m_cpt_dcache_data_read++;
 m_cpt_dcache_dir_read++;
 #endif
-        /*ODCCP*/
-//        assert((cache_state != CACHE_SLOT_STATE_VALID_NCC) and "DCACHE_TLB_PTE1_GET : IMPOSSIBLE NCC HERE");
-//        if ( cache_state == CACHE_SLOT_STATE_VALID_CC )   // hit in dcache
+
         if (( cache_state == CACHE_SLOT_STATE_VALID_NCC ) or ( cache_state == CACHE_SLOT_STATE_VALID_CC ))
         {
@@ -3199 +3168 @@
             {
                 // mark the cache line ac containing a PTD
-                //MODIFIED
-                //r_dcache_contains_ptd[m_dcache_sets*way+set] = true;
                 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_CONTAINS_PTD;
 
@@ -3236 +3203 @@
             else                        //  PTE1 :  we must update the TLB
             {
-                // MODIFIED
-                //r_dcache_in_tlb[m_icache_sets*way+set] = true;
                 r_dcache_content_state[m_icache_sets*way+set] = LINE_CACHE_IN_TLB;
                 r_dcache_tlb_pte_flags  = entry;
-               //r_dcache_tlb_cache_way  = way;
-               //r_dcache_tlb_cache_set  = set;
-               //r_dcache_tlb_cache_word = word;
                 r_dcache_fsm            = DCACHE_TLB_PTE1_SELECT;
 
@@ -3479 +3441 @@
 m_cpt_dcache_dir_read++;
 #endif
-        /*ODCCP*/
-//        assert((cache_state != CACHE_SLOT_STATE_VALID_NCC) and "DCACHE_TLB_PTE2_GET : IMPOSSIBLE NCC HERE");
-//        if (cache_state == CACHE_SLOT_STATE_VALID_CC)    // hit in dcache
         if ((cache_state == CACHE_SLOT_STATE_VALID_CC) or (cache_state == CACHE_SLOT_STATE_VALID_NCC))
         {
@@ -3514 +3473 @@
             else                                // mapped : we must update the TLB
             {
-                // MODIFIED
-                //r_dcache_in_tlb[m_dcache_sets*way+set] = true;
                 r_dcache_content_state[m_dcache_sets*way+set] = LINE_CACHE_IN_TLB;
                 r_dcache_tlb_pte_flags  = pte_flags;
                 r_dcache_tlb_pte_ppn    = pte_ppn;
-               //r_dcache_tlb_cache_way  = way;
-               //r_dcache_tlb_cache_set  = set;
-               //r_dcache_tlb_cache_word = word;
                 r_dcache_fsm            = DCACHE_TLB_PTE2_SELECT;
 
@@ -4002 +3956 @@
                                &tag,
                                &state );
-            /*ODCCP*/
 
             if ( state == CACHE_SLOT_STATE_VALID_CC )         // inval required
@@ -4031 +3984 @@
                 r_dcache_miss_set     = set;
                 r_dcache_cc_cleanup_line_ncc = true;
+
                 if (r_dcache_content_state[m_dcache_sets*way+set] != LINE_CACHE_DATA_NOT_DIRTY)//Must send data in the cleanup
-                //if (true)//Must send data in the cleanup
                 {
                     r_dcache_xtn_flush_addr_data = (tag * m_dcache_sets + set) * m_dcache_words * 4;
@@ -4092 +4045 @@
             }
         }
-//       else if ( r_dcache_clack_req.read() )
-//       {
-//           r_dcache_fsm = DCACHE_CC_CHECK;
-//           r_dcache_fsm_cc_save = r_dcache_fsm.read();
-//           break;
-//       }
         break;
     }
@@ -4109 +4056 @@
         size_t set = r_dcache_miss_set.read();
 
-        // MODIFIED
-        //r_dcache_in_tlb[m_dcache_sets*way+set]       = false;
-        //r_dcache_contains_ptd[m_dcache_sets*way+set] = false;
         r_dcache_content_state[m_dcache_sets*way+set]  = LINE_CACHE_DATA_DIRTY;
 
@@ -4215 +4159 @@
                            &set,
                            &word );
-        /*ODCCP*/
-        //assert((state != CACHE_SLOT_STATE_VALID_NCC) and "NOT YET DONE");
+
         if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC))      // inval to be done
         {
@@ -4266 +4209 @@
 m_cpt_dcache_dir_write++;
 #endif
-            // MODIFIER POUR DIRTY BIT //
+
             if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC))// request cleanup
             {
@@ -4284 +4227 @@
                     r_dcache_cc_cleanup_line_ncc = true;
                     if ((r_dcache_content_state[way*m_dcache_sets+set] != LINE_CACHE_DATA_NOT_DIRTY)) //must send data
-                    //if (true) //must send data
                     {
                         r_dcache_cc_cleanup_updt_data = true;
@@ -4305 +4247 @@
                 }
             }
-            /*ODCCP*/
 
             // possible itlb & dtlb invalidate
-            // MODIFIED
-            //if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
-            //{
             if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB )
             {
@@ -4317 +4255 @@
                 r_dcache_fsm_scan_save  = DCACHE_XTN_DC_INVAL_END;
                 r_dcache_fsm            = DCACHE_INVAL_TLB_SCAN;
-                // MODIFIED
-                //r_dcache_in_tlb[way*m_dcache_sets+set] = false;
                 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
             }
-            // MODIFIED
-            //else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
-            //{
             else if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD)
             {
                 r_itlb.reset();
                 r_dtlb.reset();
-                // MODIFIED
-                //r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
                 r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
                 r_dcache_fsm = DCACHE_IDLE;
@@ -4354 +4285 @@
     /*ODCCP*/
     //////////////////////////////
-    case DCACHE_XTN_DC_INVAL_DATA:      //A verifier
+    case DCACHE_XTN_DC_INVAL_DATA:
     {
 
@@ -4420 +4351 @@
         }
 
-            bool     found = false;
-            bool     cleanup = false;
-            size_t   way = 0;
-            size_t   set = 0;
-            paddr_t  victim = 0;
-            int state;
-            bool     s_cleanup_updt_data = false;
-            bool     s_cleanup_line_ncc = false;
+            bool    found = false;
+            bool    cleanup = false;
+            size_t  way = 0;
+            size_t  set = 0;
+            paddr_t victim = 0;
+            int     state;
+            bool    s_cleanup_updt_data = false;
+            bool    s_cleanup_line_ncc = false;
 
 #ifdef INSTRUMENTATION
@@ -4449 +4380 @@
                     r_dcache_miss_clack   = true;
                     r_dcache_fsm          = DCACHE_MISS_CLEAN;
-                    if( (state == CACHE_SLOT_STATE_VALID_NCC) )//and (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_DIRTY) )
+                    if( (state == CACHE_SLOT_STATE_VALID_NCC) )
                     {
-                        //MODIFIER POUR DIRTY BIT //
                         s_cleanup_line_ncc = true;
                         r_dcache_miss_data_addr = (victim*m_dcache_words)*4;
                         if ((r_dcache_content_state[way*m_dcache_sets+set] != LINE_CACHE_DATA_NOT_DIRTY))//must send data
-                        //if (true)//must send data
                         {
                             s_cleanup_updt_data = true;
@@ -4472 +4401 @@
                             m_cpt_cleanup_data_not_dirty ++;
                     }
-                        
                     else
                     {
@@ -4555 +4483 @@
             }
         }
-//       else if ( r_dcache_clack_req.read() )
-//       {
-//           r_dcache_fsm = DCACHE_CC_CHECK;
-//           r_dcache_fsm_cc_save = r_dcache_fsm.read();
-//           break;
-//       }
 
         break;
@@ -4590 +4512 @@
         // if selective itlb & dtlb invalidate are required
         // the miss response is not handled before invalidate completed
-        // MODIFIED
-        //if ( r_dcache_in_tlb[way*m_dcache_sets+set] )
-        //{
         if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB )
         {
-            //MODIFIED
-            //r_dcache_in_tlb[way*m_dcache_sets+set] = false;
             r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
             if( not r_dcache_cleanup_victim_req.read() )
@@ -4610 +4527 @@
             r_dcache_fsm             = DCACHE_INVAL_TLB_SCAN;
         }
-        // MODIFIED
-        //else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] )
-        //{
         else if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD )
         {
             r_itlb.reset();
             r_dtlb.reset();
-            // MODIFIED
-            //r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
             r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
             r_dcache_fsm = DCACHE_MISS_WAIT;
@@ -4846 +4758 @@
                 if (r_dcache_read_state.read())
                 {
-                  r_dcache.write_dir( r_dcache_save_paddr.read(),
+                    r_dcache.write_dir( r_dcache_save_paddr.read(),
                                         r_dcache_miss_way.read(),
                                         r_dcache_miss_set.read(),
@@ -4856 +4768 @@
                 else
                 {
-                  r_dcache.write_dir( r_dcache_save_paddr.read(),
+                    r_dcache.write_dir( r_dcache_save_paddr.read(),
                                         r_dcache_miss_way.read(),
                                         r_dcache_miss_set.read(),
@@ -4878 +4790 @@
           << " / SET = "   << r_dcache_miss_set.read() << std::endl;
 #endif
-                // reset directory extension
-
-                // MODIFIED
-                //r_dcache_in_tlb[way*m_dcache_sets+set] = false;
-                //r_dcache_contains_ptd[way*m_dcache_sets+set] = false;
             }
             if      (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
@@ -5157 +5064 @@
                            word,
                            r_dcache_vci_cas_new.read());
-            //std::cout << "CAS local" << std::endl;
+
             if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB )
             {
@@ -5317 +5224 @@
         r_dcache_cc_way = way;
         r_dcache_cc_set = set;
-            /*RWT / ODCCP*/
-        if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC))             // hit
-        {
-          // need to update the cache state
+
+        if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC))  // hit
+        {
+            // need to update the cache state
             r_dcache_cc_need_write = true;
             r_dcache_cc_cleanup_line_ncc = false;
@@ -5424 +5331 @@
             }
         }
-            assert (not r_dcache_cc_send_req.read() &&
+        assert (not r_dcache_cc_send_req.read() &&
                     "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "
                     "must not be set");
-            // coherence request completed
-                r_cc_receive_dcache_req = false;
-            // request multicast acknowledgement
-                r_dcache_cc_send_req = true;
-                r_dcache_cc_send_way = way;
-                r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
-                r_dcache_cc_send_type = CC_TYPE_CLEANUP;
-                // MODIFIER POUR DIRTY BIT //
-                if (cache_state == CACHE_SLOT_STATE_VALID_NCC and not r_cc_receive_dcache_inval_is_config.read())
+        // coherence request completed
+        r_cc_receive_dcache_req = false;
+        // request multicast acknowledgement
+        r_dcache_cc_send_req = true;
+        r_dcache_cc_send_way = way;
+        r_dcache_cc_send_nline = r_cc_receive_dcache_nline.read();
+        r_dcache_cc_send_type = CC_TYPE_CLEANUP;
+
+        if (cache_state == CACHE_SLOT_STATE_VALID_NCC and not r_cc_receive_dcache_inval_is_config.read())
+        {
+            r_dcache_cc_cleanup_line_ncc = true; 
+            if ((r_dcache_content_state[way*m_dcache_sets+set] != LINE_CACHE_DATA_NOT_DIRTY) or r_dcache_dirty_save.read() or dirty_save) //must send data
+            {
+                r_dcache_cc_cleanup_updt_data = true;
+                for (size_t w = 0; w< m_dcache_words; w++)
                 {
-                    r_dcache_cc_cleanup_line_ncc = true; 
-                    if ((r_dcache_content_state[way*m_dcache_sets+set] != LINE_CACHE_DATA_NOT_DIRTY) or r_dcache_dirty_save.read() or dirty_save) //must send data
-                    {
-                        r_dcache_cc_cleanup_updt_data = true;
-                        for (size_t w = 0; w< m_dcache_words; w++)
-                        {
-                            m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets*way+set)*m_dcache_words + w];
-                        }
-
-                        r_dcache_fsm          = DCACHE_CC_INVAL_DATA;
-                    }
-                    else
-                    {
-                        r_dcache.write_dir( way,
-                                            set,
-                                            CACHE_SLOT_STATE_ZOMBI );
+                    m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets*way+set)*m_dcache_words + w];
+                }
+
+                r_dcache_fsm          = DCACHE_CC_INVAL_DATA;
+            }
+            else
+            {
+                r_dcache.write_dir( way,
+                                    set,
+                                    CACHE_SLOT_STATE_ZOMBI );
  
-                        r_dcache_cc_cleanup_updt_data = false;
-                        r_dcache_fsm = r_dcache_fsm_cc_save.read();
-                    }
-                }
-                else
-                {
-                    r_dcache_cc_cleanup_updt_data = false;
-                    r_dcache_fsm = r_dcache_fsm_cc_save.read();
-                }
+                r_dcache_cc_cleanup_updt_data = false;
+                r_dcache_fsm = r_dcache_fsm_cc_save.read();
+            }
+        }
+        else
+        {
+            r_dcache_cc_cleanup_updt_data = false;
+            r_dcache_fsm = r_dcache_fsm_cc_save.read();
+        }
 
         break;
@@ -6220 +6127 @@
             if (p_dspin_p2m.read.read())
             {
-                //std::cout << "CLEANUP send on line " << r_dcache_cc_send_nline.read() << std::endl;
+
                 if(r_dcache_cc_cleanup_updt_data.read() and (r_cc_send_last_client.read() == 0))//dcache request with data
-               {
+                {
                     r_cc_send_fsm = CC_SEND_CLEANUP_DATA_UPDT;
                 }
@@ -6248 +6155 @@
                 if(r_cc_send_data_fifo.rok())
                 {
-                    /*ODCCP*///std::cout<<"CLEANUP_DATA_UPDT" << std::endl;
                     m_cpt_data_cleanup++;
                     cleanup_data_updt_fifo_dcache_get = true;
@@ -6254 +6160 @@
                     if (r_cc_send_cpt_word.read() == m_dcache_words-1)
                     {
-                        //std::cout << "L1 paddr CLEANUP DATA | paddr = " << std::hex << (r_dcache_cc_send_nline.read()*m_dcache_words)*4 << std::dec << std::endl;
-                        /*ODCCP*/
-                        //std::cout << "CLEANUP with DATA finished by " << name() << std::endl;
                         r_dcache_cc_send_req = false;
                         r_dcache_cc_cleanup_updt_data = false;
@@ -6583 +6486 @@
                                  vci_rsp_fifo_dcache_put,
                                  vci_rsp_fifo_dcache_data);
-    //BUG pktid
+
     r_vci_rsp_fifo_rpktid.update(vci_rsp_fifo_rpktid_get,
                                  vci_rsp_fifo_rpktid_put,
@@ -6798 +6701 @@
         {
             // initialize dspin send data
-//            DspinDhccpParam::dspin_set(dspin_send_data,
-//                                       0,
-//                                       DspinDhccpParam::P2M_EOP);
             DspinDhccpParam::dspin_set(dspin_send_data,
                                        m_cc_global_id,
@@ -6892 +6792 @@
         case CC_SEND_CLEANUP_DATA_UPDT:
         {
-            /*if (r_cc_send_cpt_word.read() == m_dcache_words-1)
-            {
-                DspinDhccpParam::dspin_set(dspin_send_data,
-                                           1,
-                                           DspinDhccpParam::FROM_L1_EOP);
-            }
-            else
-            {
-                DspinDhccpParam::dspin_set(dspin_send_data,
-                                           0,
-                                           DspinDhccpParam::FROM_L1_EOP);
-            }*/
 
             DspinDhccpParam::dspin_set(dspin_send_data,
@@ -6910 +6798 @@
             
             p_dspin_p2m.data = dspin_send_data;
-            //std::cout << "genmoore CLEANUP DATA UPDT : dspin_send_data = " << std::hex << dspin_send_data << std::dec << std::endl;
             p_dspin_p2m.write = true;
             p_dspin_p2m.eop = (r_cc_send_cpt_word.read() == m_dcache_words-1);
@@ -6919 +6806 @@
         {
             // initialize dspin send data
-//            DspinDhccpParam::dspin_set(dspin_send_data,
-//                                       1,
-//                                       DspinDhccpParam::P2M_EOP);
             DspinDhccpParam::dspin_set(dspin_send_data,
                                        0,

branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h

@@ -83 +83 @@
         TGT_CMD_WRITE,
         TGT_CMD_CAS,
-        TGT_CMD_ERROR,
-        TGT_CMD_CONFIG
+        TGT_CMD_CONFIG,
+        TGT_CMD_ERROR
       };
 
@@ -96 +96 @@
         TGT_RSP_MULTI_ACK_IDLE,
         TGT_RSP_CLEANUP_IDLE,
+        TGT_RSP_TGT_CMD_IDLE,
         TGT_RSP_CONFIG_IDLE,
-        TGT_RSP_TGT_CMD_IDLE,
         TGT_RSP_READ,
         TGT_RSP_WRITE,
@@ -104 +104 @@
         TGT_RSP_MULTI_ACK,
         TGT_RSP_CLEANUP,
-        TGT_RSP_CONFIG,
-        TGT_RSP_TGT_CMD
+        TGT_RSP_TGT_CMD,
+        TGT_RSP_CONFIG
       };
 
@@ -122 +122 @@
         CC_SEND_XRAM_RSP_IDLE,
         CC_SEND_WRITE_IDLE,
+        CC_SEND_READ_IDLE,
         CC_SEND_CAS_IDLE,
         CC_SEND_CONFIG_IDLE,
@@ -437 +438 @@
       uint32_t     m_cpt_write_flits_remote; // number of flits for remote WRITEs
       uint32_t     m_cpt_write_cost;     // Number of (flits * distance) for WRITEs
+      uint32_t     m_cpt_write_ncc_miss;   // Number of write on ncc line
 
       uint32_t     m_cpt_ll_local;       // Number of local LL transactions
@@ -552 +554 @@
       uint32_t     m_cpt_xram_rsp_fsm_heap_used; // NB cycles HEAP LOCK used
       
-      uint32_t     m_cpt_heap_unused;            // NB cycles HEAP LOCK unused
+      uint32_t     m_cpt_heap_unused;             // NB cycles HEAP LOCK unused
+      uint32_t     m_cpt_heap_slot_available;     // NB HEAP slot available refresh at each cycles
+      uint32_t     m_cpt_heap_min_slot_available; // NB HEAP : Min of slot available 
 
       //RWT
@@ -584 +588 @@
       sc_in<bool>                                 p_clk;
       sc_in<bool>                                 p_resetn;
-      sc_in<bool>                                 p_irq;
+      sc_out<bool>                                p_irq;
       soclib::caba::VciTarget<vci_param_int>      p_vci_tgt;
       soclib::caba::VciInitiator<vci_param_ext>   p_vci_ixr;
@@ -618 +622 @@
           const soclib::common::IntTab       &srcid_x,        // global index RAM network
           const soclib::common::IntTab       &tgtid_d,        // global index INT network
-          const size_t                       cc_global_id,    // global index CC network
           const size_t                       x_width,         // X width in platform
           const size_t                       y_width,         // Y width in platform
@@ -635 +638 @@
 
       void reset_counters();
-      void print_stats(bool activity_counters, bool stats);
+      void print_stats(bool activity_counters = true, bool stats = false);
       void print_trace( size_t detailled = 0 );
       void cache_monitor(addr_t addr);
@@ -647 +650 @@
       void check_monitor(addr_t addr, data_t data, bool read);
       uint32_t req_distance(uint32_t req_srcid);
+      uint32_t min_value(uint32_t old_value, uint32_t new_value);
       bool is_local_req(uint32_t req_srcid);
       int  read_instrumentation(uint32_t regr, uint32_t & rdata);
@@ -661 +665 @@
       const size_t                       m_sets;             // Number of cache sets
       const size_t                       m_words;            // Number of words in a line
-      const size_t                       m_cc_global_id;     // global_index on cc network
-      const size_t                       m_xwidth;           // number of x bits in platform
-      const size_t                       m_ywidth;           // number of y bits in platform
+      size_t                             m_x_self;           // X self coordinate
+      size_t                             m_y_self;           // Y self coordinate
+      const size_t                       m_x_width;          // number of x bits in platform
+      const size_t                       m_y_width;          // number of y bits in platform
       size_t                             m_debug_start_cycle;
       bool                               m_debug_ok;
@@ -834 +839 @@
       sc_signal<addr_t>   r_read_to_cleanup_nline;  // cache line index
       sc_signal<size_t>   r_read_to_cleanup_srcid;
+      sc_signal<size_t>   r_read_to_cleanup_inst;
       sc_signal<size_t>   r_read_to_cleanup_length;
       sc_signal<size_t>   r_read_to_cleanup_first_word;
@@ -1069 +1075 @@
       sc_signal<size_t>   r_xram_rsp_ivt_index;         // IVT entry index
       sc_signal<size_t>   r_xram_rsp_next_ptr;          // Next pointer to the heap
+      sc_signal<bool>     r_xram_rsp_rerror_irq;        // WRITE MISS rerror irq
+      sc_signal<bool>     r_xram_rsp_rerror_irq_enable; // WRITE MISS rerror irq enable
+      sc_signal<addr_t>   r_xram_rsp_rerror_address;    // WRITE MISS rerror address
+      sc_signal<size_t>   r_xram_rsp_rerror_rsrcid;     // WRITE MISS rerror srcid
 
       // Buffer between XRAM_RSP fsm and TGT_RSP fsm  (response to L1 cache)

branches/RWT/modules/vci_mem_cache/caba/source/include/xram_transaction.h

@@ -426 +426 @@
     void write_rsp(const size_t      index,
                    const size_t      word,
-                   const wide_data_t data)
+                   const wide_data_t data,
+                   const bool        rerror)
     {
         data_t  value;
@@ -442 +443 @@
         assert( (tab[index].xram_read ) and
         "MEMC ERROR: TRT entry is not a GET in TRT write_rsp()");
+
+        if ( rerror )
+        {
+            tab[index].rerror = true;
+            return;
+        }
 
         // first 32 bits word

branches/RWT/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp

@@ -56 +56 @@
 #define RANDOMIZE_CAS        1
 
+// RWT configuration
+#define REVERT_CC_MECANISM   0
+
+// Configuration
+#define REVERT_BC_MECANISM   0
+
 namespace soclib { namespace caba {
 
@@ -64 +70 @@
         "TGT_CMD_WRITE",
         "TGT_CMD_CAS",
-        "TGT_CMD_ERROR",
-        "TGT_CMD_CONFIG"
+        "TGT_CMD_CONFIG",
+        "TGT_CMD_ERROR"
     };
     const char *tgt_rsp_fsm_str[] =
@@ -75 +81 @@
         "TGT_RSP_MULTI_ACK_IDLE",
         "TGT_RSP_CLEANUP_IDLE",
+        "TGT_RSP_TGT_CMD_IDLE",
         "TGT_RSP_CONFIG_IDLE",
-        "TGT_RSP_TGT_CMD_IDLE",
         "TGT_RSP_READ",
         "TGT_RSP_WRITE",
@@ -83 +89 @@
         "TGT_RSP_MULTI_ACK",
         "TGT_RSP_CLEANUP",
-        "TGT_RSP_CONFIG",
-        "TGT_RSP_TGT_CMD"
+        "TGT_RSP_TGT_CMD",
+        "TGT_RSP_CONFIG"
     };
     const char *cc_receive_fsm_str[] =
@@ -97 +103 @@
         "CC_SEND_XRAM_RSP_IDLE",
         "CC_SEND_WRITE_IDLE",
+        "CC_SEND_READ_IDLE",
         "CC_SEND_CAS_IDLE",
         "CC_SEND_CONFIG_IDLE",
@@ -353 +360 @@
             const IntTab        &srcid_x,          // global index on external network
             const IntTab        &tgtid_d,          // global index on direct network
-            const size_t        cc_global_id,      // global index on cc network
             const size_t        x_width,           // number of x bits in platform
             const size_t        y_width,           // number of x bits in platform
@@ -378 +384 @@
         p_dspin_clack( "p_dspin_clack" ),
 
-        m_seglist( mtp.getSegmentList(tgtid_d) ),
-        m_nseg( 0 ),
-        m_srcid_x( mtx.indexForId(srcid_x) ),
-        m_initiators( 1 << vci_param_int::S ),
-        m_heap_size( heap_size ),
-        m_ways( nways ),
-        m_sets( nsets ),
-        m_words( nwords ),
-        m_cc_global_id( cc_global_id ),
-        m_xwidth(x_width),
-        m_ywidth(y_width),
+        m_seglist(mtp.getSegmentList(tgtid_d)),
+        m_nseg(0),
+        m_srcid_x( mtx.indexForId(srcid_x)),
+        m_initiators(1 << vci_param_int::S),
+        m_heap_size(heap_size),
+        m_ways(nways),
+        m_sets(nsets),
+        m_words(nwords),
+        m_x_width(x_width),
+        m_y_width(y_width),
         m_debug_start_cycle( debug_start_cycle ),
         m_debug_ok( debug_ok ),
@@ -547 +552 @@
             }
 
+            assert( (m_nseg > 0) and
+                    "MEMC ERROR : At least one segment must be mapped to this component");
+
             m_seg = new soclib::common::Segment*[m_nseg];
 
@@ -555 +563 @@
                 i++;
             }
+
+            addr_t gid = m_seg[0]->baseAddress() >> (vci_param_int::N - x_width - y_width);
+            m_x_self = (gid >> m_y_width) & ((1 << m_x_width) - 1);
+            m_y_self =  gid               & ((1 << m_y_width) - 1);
 
             // Allocation for IXR_RSP FSM
@@ -664 +676 @@
     }
 
+    /////////////////////////////////////////////////////
+    tmpl(uint32_t)::min_value(uint32_t old_value, uint32_t new_value)
+        /////////////////////////////////////////////////////
+    {
+        if (old_value < new_value)
+            return old_value;
+        else
+            return new_value;
+    }
 
     /////////////////////////////////////////////////////
@@ -670 +691 @@
     {
         const uint32_t srcid_width = vci_param_int::S;
-        uint8_t self_x_srcid = m_cc_global_id >> (srcid_width - m_xwidth);
-        uint8_t self_y_srcid = (m_cc_global_id >> (srcid_width - m_ywidth)) & ((1 << m_xwidth) - 1);
-
-        uint8_t x_srcid = req_srcid >> (srcid_width - m_xwidth);
-        uint8_t y_srcid = (req_srcid >> (srcid_width - m_ywidth - m_xwidth)) & ((1 << m_xwidth) - 1);
-        return abs(self_x_srcid - x_srcid) + abs(self_y_srcid - y_srcid);
+
+        uint8_t req_x = (req_srcid >> (srcid_width - m_x_width));
+        uint8_t req_y = (req_srcid >> (srcid_width - m_x_width - m_y_width)) & ((1 << m_y_width) - 1);
+
+        return abs(m_x_self - req_x) + abs(m_y_self - req_y);
     }
 
@@ -865 +885 @@
         m_cpt_ncc_to_cc_write    = 0;
         m_cpt_ncc_to_cc          = 0;
+        m_cpt_write_ncc_miss     = 0;
     }
 
 
     /////////////////////////////////////////
-    tmpl(void)::print_stats(bool activity_counters = true, bool stats = true)
+    tmpl(void)::print_stats(bool activity_counters, bool stats)
     {
         std::cout << "**********************************" << std::dec << std::endl;
@@ -891 +912 @@
                 << "[008] WRITE FLITS REMOTE        = " << m_cpt_write_flits_remote << std::endl
                 << "[009] WRITE COST (FLITS * DIST) = " << m_cpt_write_cost << std::endl
+                << "[XXX] WRITE L1 MISS NCC         = " << m_cpt_write_ncc_miss << std::endl
                 << std::endl
                 << "[010] LOCAL LL                  = " << m_cpt_ll_local << std::endl
@@ -929 +951 @@
                 << "[037] GET (UNIMPLEMENTED)       = " << m_cpt_get << std::endl
                 << "[038] WRITE BROADCAST           = " << m_cpt_write_broadcast << std::endl
+                << "[039] MIN HEAP SLOT AVAILABLE   = " << m_cpt_heap_min_slot_available << std::endl
                 << std::endl
-                << "[039] CLEANUP DATA (FLITS)      = " << m_cpt_cleanup_data * 16 << std::endl
-                << "[040] NCC TO CC (READ)          = " << m_cpt_ncc_to_cc_read << std::endl
-                << "[041] NCC TO CC (WRITE)         = " << m_cpt_ncc_to_cc_write << std::endl
-                << "[042] NCC TO CC (TOTAL)         = " << m_cpt_ncc_to_cc << std::endl
+                << "[040] CLEANUP DATA (FLITS)      = " << m_cpt_cleanup_data * 16 << std::endl
+                << "[041] NCC TO CC (READ)          = " << m_cpt_ncc_to_cc_read << std::endl
+                << "[042] NCC TO CC (WRITE)         = " << m_cpt_ncc_to_cc_write << std::endl
+                << "[043] NCC TO CC (TOTAL)         = " << m_cpt_ncc_to_cc << std::endl
                 << std::endl;
         }
@@ -1017 +1040 @@
         delete [] m_debug_previous_data;
         delete [] m_debug_data;
-
-        print_stats();
     }
 
@@ -1137 +1158 @@
             r_xram_rsp_to_ixr_cmd_req          = false;
             r_xram_rsp_trt_index               = 0;
+            r_xram_rsp_rerror_irq              = false;
+            r_xram_rsp_rerror_irq_enable       = false;
 
             m_xram_rsp_to_cc_send_inst_fifo.init();
@@ -1175 +1198 @@
             m_cpt_write_flits_local  = 0;
             m_cpt_write_flits_remote = 0;
+            m_cpt_write_ncc_miss     = 0;
             m_cpt_write_cost         = 0;
             m_cpt_ll_local           = 0;
@@ -1253 +1277 @@
             m_cpt_ncc_to_cc_write         = 0;       
             m_cpt_ncc_to_cc               = 0;        
+
+            m_cpt_heap_min_slot_available = m_heap_size;
+            m_cpt_heap_slot_available     = m_heap_size;
+
             return;
         }
@@ -1360 +1388 @@
 #endif
                     // checking segmentation violation
-                    addr_t      address  = p_vci_tgt.address.read();
-                    uint32_t    plen     = p_vci_tgt.plen.read();
-                    bool        found    = false;
-                    bool        config   = false;
-
-                    for (size_t seg_id = 0; (seg_id < m_nseg) && !found; seg_id++)
+                    addr_t   address = p_vci_tgt.address.read();
+                    uint32_t plen    = p_vci_tgt.plen.read();
+                    bool     config  = false;
+
+                    for (size_t seg_id = 0; (seg_id < m_nseg) ; seg_id++)
                     {
                         if (m_seg[seg_id]->contains(address) &&
                                 m_seg[seg_id]->contains(address + plen - vci_param_int::B) )
                         {
-                            found = true;
                             if ( m_seg[seg_id]->special() ) config = true;
                         }
                     }
 
-                    if (!found)                /////////// out of segment error
-                    {
-                        r_tgt_cmd_fsm   = TGT_CMD_ERROR;
-                    }
-                    else if ( config )              /////////// configuration command
+                    if (config)                     /////////// configuration command
                     {
                         if (!p_vci_tgt.eop.read()) r_tgt_cmd_fsm = TGT_CMD_ERROR;
-                        else                            r_tgt_cmd_fsm = TGT_CMD_CONFIG;
+                        else                       r_tgt_cmd_fsm = TGT_CMD_CONFIG;
                     }
                     else                            //////////// memory access 
@@ -1404 +1426 @@
                             // ==> TYPE_WRITE = X100 with the TSAR encoding
                             // ==> mask = 0b0111 = 0x7
-                            assert(((p_vci_tgt.pktid.read() & 0x7) == 0x4 or (p_vci_tgt.pktid.read() == 0x0)) and
+                            assert((((p_vci_tgt.pktid.read() & 0x7) == 0x4)  or ((p_vci_tgt.pktid.read() & 0x7) == 0x0)) and
                                     "The type specified in the pktid field is incompatible with the WRITE CMD");
                             r_tgt_cmd_fsm = TGT_CMD_WRITE;
@@ -1620 +1642 @@
                         }
 
+                        // xram GET bus error registers
+                        case MEMC_RERROR:
+                        {
+                            need_rsp = true;
+                            error    = 0;
+
+                            if (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)
+                            {
+                                switch (regr)
+                                {
+                                    case MEMC_RERROR_IRQ_ENABLE:
+                                        r_xram_rsp_rerror_irq_enable =
+                                            (p_vci_tgt.wdata.read() != 0);
+
+                                        break;
+                                        
+                                    default:
+                                        error = 1;
+                                        break;
+                                }
+                            }
+                            else if (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ)
+                            {
+                                switch (regr)
+                                {
+                                    case MEMC_RERROR_SRCID:
+                                        rdata = (uint32_t)
+                                            r_xram_rsp_rerror_rsrcid.read();
+
+                                        break;
+
+                                    case MEMC_RERROR_ADDR_LO:
+                                        rdata = (uint32_t)
+                                            (r_xram_rsp_rerror_address.read()) &
+                                            ((1ULL<<32)-1);
+
+                                        break;
+
+                                    case MEMC_RERROR_ADDR_HI:
+                                        rdata = (uint32_t)
+                                            (r_xram_rsp_rerror_address.read() >> 32) &
+                                            ((1ULL<<32)-1);
+
+                                        break;
+
+                                    case MEMC_RERROR_IRQ_RESET:
+                                        if (not r_xram_rsp_rerror_irq.read()) break;
+
+                                        r_xram_rsp_rerror_irq = false;
+
+                                        break;
+
+                                    case MEMC_RERROR_IRQ_ENABLE:
+                                        rdata = (uint32_t)
+                                            (r_xram_rsp_rerror_irq_enable.read()) ? 1 : 0;
+
+                                        break;
+
+                                    default:
+                                        error = 1;
+                                        break;
+                                }
+                            }
+                            else
+                            {
+                                error = 1;
+                            }
+
+                            break;
+                        }
+
                         //unknown function
                         default:
@@ -2100 +2193 @@
         //   is signaled by the CLEANUP FSM by decrementing the r_config_rsp_lines counter.
         //   The CONFIG INVAL response is sent only when the last line has been invalidated.
+        //   There is no PUT transaction to XRAM, even if the invalidated line is dirty...
         //   TODO : The target buffer address must be aligned on a cache line boundary.
         //   This constraint can be released, but it requires to make 2 PUT transactions
@@ -2559 +2653 @@
                         r_config_heap_next = entry.next;
                         if ( last_copy ) r_config_fsm = CONFIG_HEAP_LAST;
+
+                        // <Activity counters>
+                        m_cpt_heap_slot_available++;
+                        // </Activity counters>
                     }
 
@@ -2684 +2782 @@
                     {
                         r_read_ll_key   = m_llsc_table.ll(m_cmd_read_addr_fifo.read());
-                        /**//*std::cout << "MEMCACHE : from proc " << m_cmd_read_srcid_fifo.read()
-                              << " | @ " << std::hex << m_cmd_read_addr_fifo.read()
-                              << " | LL" << std::endl;*/
                         r_read_ll_done  = true;
                     }
@@ -2708 +2803 @@
                     {
                         r_read_coherent = entry.cache_coherent;
-                        if (entry.cache_coherent or (entry.count == 0))// or (entry.owner.srcid == m_cmd_read_srcid_fifo.read())) //hit on a WT line or the owner has no more copy (if LL, the owner must be invalidated even if he made the request)
+
+                        // hit on a WT line or the owner has no more copy (if LL, the owner must be invalidated even if he made the request)
+                        if (entry.cache_coherent or (entry.count == 0))// or (entry.owner.srcid == m_cmd_read_srcid_fifo.read())) 
                         {
                             // test if we need to register a new copy in the heap
@@ -2717 +2814 @@
                             else
                             {
-                                //std::cout << "is LL = " << ((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) << std::endl;
-                                //std::cout << "coherent = " << entry.cache_coherent << " | count = " << std::dec << entry.count << " | cached = " << cached_read << std::endl;
                                 r_read_fsm = READ_HEAP_REQ;
                             }
@@ -2755 +2850 @@
                         size_t index;
                         addr_t nline = m_nline[(addr_t)(m_cmd_read_addr_fifo.read())];
-                        /*std::cout << "nline = " << std::dec <<  nline << std::endl
-                          << "inval en cours sur la ligne = " << m_upt.search_inval(nline, index) << std::endl
-                          << "UPT full = " << m_upt.is_full() << std::endl
-                          << "CC_SEND req = " << r_read_to_cc_send_req.read() << std::endl
-                          << "CLENAUP req = " <<r_read_to_cleanup_req.read() << std::endl;*/
                         if(m_ivt.search_inval(nline, index) or m_ivt.is_full() or r_read_to_cc_send_req.read() or r_read_to_cleanup_req.read()) //Check pending inval
                         {
@@ -2782 +2872 @@
                             r_read_to_cleanup_nline = nline;
                             r_read_to_cleanup_srcid = m_cmd_read_srcid_fifo.read();
+                            r_read_to_cleanup_inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); 
                             r_read_to_cleanup_length  = m_cmd_read_length_fifo.read();
                             r_read_to_cleanup_first_word = m_x[(addr_t) m_cmd_read_addr_fifo.read()];
@@ -2788 +2879 @@
                             r_read_to_cleanup_is_ll= ((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL);
                             r_read_to_cleanup_ll_key = r_read_ll_key.read();
-                            //std::cout << "cleanup req (read) on line " << nline << " /on proc " << r_read_copy.read() << std::endl;
 
                             m_ivt.set(false,     // it's an inval transaction
@@ -2807 +2897 @@
                             {
                                 std::cout
-                                    << "  <MEMC " << name() << " READ_IVT_LOCK>" 
+                                    << "  <MEMC " << name() << " READ_IVT_LOCK>"
+                                    << std::hex
                                     << " Inval req on an NCC line"
+                                    << " | owner = " << r_read_copy.read()
+                                    << " | nline = " << nline
+                                    << std::dec
                                     << std::endl;
                             }
@@ -2861 +2955 @@
                     DirectoryEntry entry;
                     entry.valid   = true;
-                    entry.cache_coherent = r_read_coherent.read() or inst_read or (!(cached_read)) or (r_read_copy.read() != m_cmd_read_srcid_fifo.read());
-                    r_read_coherent = r_read_coherent.read() or inst_read or (!(cached_read)) or (r_read_copy.read() != m_cmd_read_srcid_fifo.read());
+                    //entry.cache_coherent = r_read_coherent.read() or inst_read or (!(cached_read)) or (r_read_copy.read() != m_cmd_read_srcid_fifo.read());
+                    //r_read_coherent = r_read_coherent.read() or inst_read or (!(cached_read)) or (r_read_copy.read() != m_cmd_read_srcid_fifo.read());
+
+                    entry.cache_coherent = r_read_coherent.read() or inst_read or (!(cached_read));
+                    r_read_coherent = r_read_coherent.read() or inst_read or (!(cached_read));
+
                     entry.is_cnt  = is_cnt;
                     entry.dirty   = r_read_dirty.read();
@@ -2984 +3082 @@
                         else            // switching to counter mode
                         {
-                            if(r_read_count.read() >1)              // heap must be cleared
+                            if(r_read_count.read() > 1)              // heap must be cleared
                             {
                                 HeapEntry next_entry = m_heap.read(r_read_ptr.read());
@@ -3043 +3141 @@
                         m_heap.write_free_entry(heap_entry);
                         m_heap.write_free_ptr(r_read_next_ptr.read());
-                        if(r_read_last_free.read())  m_heap.set_full();
+
+                        if(r_read_last_free.read()) {
+                            m_heap.set_full();
+                        }
+                        
+                        // <Activity counters>
+                        m_cpt_heap_slot_available--;
+                        // </Activity counters>
 
                         r_read_fsm = READ_RSP;
@@ -3107 +3212 @@
                         m_heap.write(r_read_ptr.read(),last_entry);
                         r_read_fsm = READ_RSP;
+
+                        // <Activity counters>
+                        m_cpt_heap_slot_available = m_cpt_heap_slot_available + (r_read_count.read() - 1);
+                        // </Activity counters>
                     }
                     else
@@ -3125 +3234 @@
                         r_read_to_tgt_rsp_length = m_cmd_read_length_fifo.read();
                         r_read_to_tgt_rsp_srcid  = m_cmd_read_srcid_fifo.read();
-                        /*RWT*/
-                        //BUG pktid
+
                         if (r_read_coherent.read())
                         {
                             r_read_to_tgt_rsp_pktid = 0x0 + m_cmd_read_pktid_fifo.read();
-                            //std::cout << "READ RSP COHERENT on word" << std::hex << m_x[(addr_t) m_cmd_read_addr_fifo.read()] << std::dec << std::endl;
                         }
                         else
@@ -3442 +3549 @@
                         r_write_coherent   = entry.cache_coherent;
 
+                        if((entry.cache_coherent == false) and (entry.count != 0))
+                        {
+                            m_cpt_write_ncc_miss++;
+                        }
+
                         if (entry.cache_coherent or (entry.owner.srcid == r_write_srcid.read()) or (entry.count == 0)) // hit WT
                         {
@@ -3462 +3574 @@
                             {
                                 r_write_fsm = WRITE_IVT_LOCK_HIT_WB;
-                                //            if(r_write_pktid.read() == TYPE_SC)
-                                //            {
-                                //              r_write_sc_fail = true;
-                                //            }
                             }
                         }
@@ -3500 +3608 @@
                         addr_t nline = m_nline[(addr_t)(r_write_address.read())];
 
-                        //std::cout << "WRITE on NCC on line" << std::hex << nline << std::dec << std::endl;
                         //if there is a matched updt req, we should wait until it is over. Because 
                         //we need the lastest updt data.
@@ -3508 +3615 @@
 
                         if( not match_inval                          and 
+                            not m_ivt.is_full()                      and
                             not r_write_to_cc_send_req.read()        and
                             not r_write_to_cc_send_multi_req.read()  and
@@ -3533 +3641 @@
                         if(m_debug)
                         {
-                            std::cout << "  <MEMC " << name() << " WRITE_IVT_LOCK_HIT_WB> get access to the UPT: "
+                            std::cout << "  <MEMC " << name() << " WRITE_IVT_LOCK_HIT_WB> get access to the IVT: "
                                 << " Inval requested =  " << (not match_inval and not r_write_to_cc_send_req.read())
                                 << std::endl;
@@ -4808 +4916 @@
                         r_ixr_rsp_trt_index = p_vci_ixr.rtrdid.read();
 
-                        assert( ((p_vci_ixr.rerror.read() & 0x1) == 0) and
-                                "MEMC ERROR in IXR_RSP state: XRAM response error !");
-
-                        if(p_vci_ixr.reop.read())   // PUT
+                        if (p_vci_ixr.reop.read() and not
+                            p_vci_ixr.rerror.read())   // PUT
                         {
                             r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE;
@@ -4836 +4942 @@
                 }
 
-                ////////////////////////
-            case IXR_RSP_TRT_ERASE:   // erase the entry in the TRT
-                // decrease the line counter if config request
+               ///////////////////////
+            case IXR_RSP_TRT_ERASE: // erase the entry in the TRT
+                                    // decrease the line counter if config request
                 {
                     if(r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP)
@@ -4846 +4952 @@
                         {
                             config_rsp_lines_ixr_rsp_decr = true;
-                            m_trt.erase(index);
-                            r_ixr_rsp_fsm = IXR_RSP_IDLE;
-                        }
-                        else                            // not a config transaction
-                        {
-                            m_trt.erase(index);
-                            r_ixr_rsp_fsm = IXR_RSP_IDLE;
-                        }
+                        }
+                        m_trt.erase(index);
+                        r_ixr_rsp_fsm = IXR_RSP_IDLE;
 
 #if DEBUG_MEMC_IXR_RSP
@@ -4872 +4973 @@
                         bool        eop      = p_vci_ixr.reop.read();
                         wide_data_t data     = p_vci_ixr.rdata.read();
-                        bool        error    = ((p_vci_ixr.rerror.read() & 0x1) == 1);
-
-                        assert(((eop == (word == (m_words-2))) or error) and
+                        bool        rerror   = ((p_vci_ixr.rerror.read() & 0x1) == 1);
+
+                        assert(((eop == (word == (m_words-2))) or rerror) and
                                 "MEMC ERROR in IXR_RSP_TRT_READ state : invalid response from XRAM");
 
-                        m_trt.write_rsp( index,
-                                word,
-                                data );
+                        m_trt.write_rsp( index, word, data, rerror );
 
                         r_ixr_rsp_cpt = word + 2;
@@ -5009 +5108 @@
                     r_xram_rsp_victim_is_cnt    = victim.is_cnt;
                     r_xram_rsp_victim_inval     = inval ;
-                    r_xram_rsp_victim_dirty     = victim.dirty or (!victim.cache_coherent && (victim.count == 1)); //a NCC line is by default considered as dirty in the L1: we must take a reservation on a TRT entry
-
-                    if( not r_xram_rsp_trt_buf.rerror ) r_xram_rsp_fsm = XRAM_RSP_IVT_LOCK;
-                    else                                r_xram_rsp_fsm = XRAM_RSP_ERROR_ERASE;
+                    // a NCC line is by default considered as dirty in the L1: we must take a reservation on a TRT entry
+                    r_xram_rsp_victim_dirty     = victim.dirty or (!victim.cache_coherent && (victim.count == 1)); 
+
+
+                    // A line that undergoes a change in its state (ncc to cc), should not be evicted from the memory cache.
+                    if((victim.tag * m_sets + set) == r_read_to_cleanup_nline.read() and r_read_to_cleanup_req.read()) 
+                    {
+                        r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
+
+#if DEBUG_MEMC_XRAM_RSP
+                        if(m_debug)
+                            std::cout << "  <MEMC " << name() << " XRAM_RSP_TRT_COPY>"
+                                << " Victim line is in ncc to cc mecanism"
+                                << " / nline = " << std::hex << (victim.tag * m_sets + set)
+                                << std::endl;
+#endif
+                    }
+                    else if( not r_xram_rsp_trt_buf.rerror ) 
+                    {
+                        r_xram_rsp_fsm = XRAM_RSP_IVT_LOCK;
+                    }
+                    else 
+                    {
+                        r_xram_rsp_fsm = XRAM_RSP_ERROR_ERASE;
+                    }
 
 #if DEBUG_MEMC_XRAM_RSP
@@ -5195 +5315 @@
 #endif
 
-                    // If the victim is not dirty (RWT: if it is not coherent, we can not know wether it is dirty or not), we don't need another XRAM  put transaction,
-                    // and we can erase the TRT entry
+                    // If the victim is not dirty (RWT: if it is not coherent,
+                    // we can not know wether it is dirty or not), we don't
+                    // need another XRAM  put transaction, and we can erase the
+                    // TRT entry
                     if(!r_xram_rsp_victim_dirty.read() and (r_xram_rsp_victim_coherent.read() or (r_xram_rsp_victim_count.read() == 0)))  m_trt.erase(r_xram_rsp_trt_index.read());
 
                     // Next state
-                    if(r_xram_rsp_victim_dirty.read() or (!r_xram_rsp_victim_coherent.read() and (r_xram_rsp_victim_count.read() == 1)))       r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY;
+                    if(r_xram_rsp_victim_dirty.read() or (!r_xram_rsp_victim_coherent.read() and (r_xram_rsp_victim_count.read() == 1)))  r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY;
                     else if(r_xram_rsp_trt_buf.proc_read)    r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
                     else if(r_xram_rsp_victim_inval.read())  r_xram_rsp_fsm = XRAM_RSP_INVAL;
@@ -5235 +5357 @@
 #endif
 
-                        //        if( not r_xram_rsp_victim_coherent )
-                        //            std::cout << "a victim coherent not sent trt index =" << r_xram_rsp_trt_index.read() << std::endl;
                         if(r_xram_rsp_trt_buf.proc_read)         r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;
                         else if(r_xram_rsp_victim_inval.read())  r_xram_rsp_fsm = XRAM_RSP_INVAL;
@@ -5311 +5431 @@
                         else                         r_xram_rsp_fsm = XRAM_RSP_IDLE;
 
-                        // std::cout << "cleanup sent for trt index =" << r_xram_rsp_trt_index.read() << std::endl;
 #if DEBUG_MEMC_XRAM_RSP
                         if(m_debug)
@@ -5373 +5492 @@
                         HeapEntry entry = m_heap.read(r_xram_rsp_next_ptr.read());
 
-                        xram_rsp_to_cc_send_fifo_srcid    = entry.owner.srcid;
+                        xram_rsp_to_cc_send_fifo_srcid = entry.owner.srcid;
                         xram_rsp_to_cc_send_fifo_inst  = entry.owner.inst;
                         xram_rsp_to_cc_send_fifo_put   = true;
@@ -5387 +5506 @@
                             {
                                 r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE;
+
                             }
                         }
@@ -5431 +5551 @@
                     m_heap.write(r_xram_rsp_next_ptr.read(),last_entry);
 
+                    // <Activity counters>
+                    m_cpt_heap_slot_available = m_cpt_heap_slot_available + (r_xram_rsp_victim_count.read() - 1);
+                    // </Activity counters>
+
                     r_xram_rsp_fsm = XRAM_RSP_IDLE;
 
@@ -5446 +5570 @@
 
                     // Next state
-                    if(r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_ERROR_RSP;
-                    else                             r_xram_rsp_fsm = XRAM_RSP_IDLE;
+                    if (r_xram_rsp_trt_buf.proc_read)
+                    {
+                        r_xram_rsp_fsm = XRAM_RSP_ERROR_RSP;
+                    }
+                    else
+                    {
+                        // Trigger an interruption to signal a bus error from
+                        // the XRAM because a processor WRITE MISS (XRAM GET
+                        // transaction and not processor read).
+                        //
+                        // To avoid deadlocks we do not wait an error to be
+                        // acknowledged before signaling another one.
+                        // Therefore, when there is an active error, and other
+                        // errors arrive, these are not considered 
+
+                        if (!r_xram_rsp_rerror_irq.read() && r_xram_rsp_rerror_irq_enable.read()
+                                && r_xram_rsp_trt_buf.xram_read )
+                        {
+                            r_xram_rsp_rerror_irq     = true;
+                            r_xram_rsp_rerror_address = r_xram_rsp_trt_buf.nline * m_words * 4;
+                            r_xram_rsp_rerror_rsrcid  = r_xram_rsp_trt_buf.srcid;
 
 #if DEBUG_MEMC_XRAM_RSP
-                    if(m_debug)
+                            if (m_debug)
+                                std::cout
+                                    << "  <MEMC " << name() << " XRAM_RSP_ERROR_ERASE>"
+                                    << " Triggering interrupt to signal WRITE MISS bus error"
+                                    << " / irq_enable = " << r_xram_rsp_rerror_irq_enable.read()
+                                    << " / nline = "      << r_xram_rsp_trt_buf.nline
+                                    << " / rsrcid = "     << r_xram_rsp_trt_buf.srcid
+                                    << std::endl;
+#endif
+                        }
+
+                        r_xram_rsp_fsm = XRAM_RSP_IDLE;
+                    }
+
+#if DEBUG_MEMC_XRAM_RSP
+                    if (m_debug)
                         std::cout << "  <MEMC " << name() << " XRAM_RSP_ERROR_ERASE>"
                             << " Error reported by XRAM / erase the TRT entry" << std::endl;
@@ -5572 +5730 @@
                         DspinDhccpParam::dspin_get(flit, DspinDhccpParam::CLEANUP_NLINE_LSB);
 
-                    //A MODIFIER POUR DIRTY //
                     bool eop =
                         DspinDhccpParam::dspin_get(flit, DspinDhccpParam::P2M_EOP) == 0x1;
+
                     if (! eop)
                     {
@@ -5643 +5801 @@
 
                     r_cleanup_fsm = CLEANUP_DIR_LOCK;
-                    //std::cout << " MEM_CACHE : CLEANUP_DIR_REQ" << std::endl;
 
 #if DEBUG_MEMC_CLEANUP
@@ -5668 +5825 @@
                         exit(0);
                     }
-                    //std::cout << " MEM_CACHE : CLEANUP_DIR_LOCK" << std::endl;
 
                     // Read the directory
@@ -5709 +5865 @@
                         }
                     }
-                    else                // miss : check UPT for a pending invalidation transaction
+                    else           // miss : check IVT for a pending invalidation transaction
                     {
                         r_cleanup_fsm = CLEANUP_IVT_LOCK;
@@ -5769 +5925 @@
                     /*RWT*/
                     bool   inval_request = (r_read_to_cleanup_req.read() and (r_cleanup_nline.read() == r_read_to_cleanup_nline.read())) // NCC to CC initiated by a read transaction
-                        or (r_write_to_cleanup_req.read() and (r_cleanup_nline.read() == r_write_to_cleanup_nline.read())); //NCC to CC initiated by a wrtie transaction
+                        or (r_write_to_cleanup_req.read() and (r_cleanup_nline.read() == r_write_to_cleanup_nline.read()));              // NCC to CC initiated by a write transaction
 
 
@@ -5794 +5950 @@
                         if (r_read_to_cleanup_cached_read.read())
                         {
-                            entry.count          = r_cleanup_count.read();
-                            entry.owner.srcid    = r_read_to_cleanup_srcid.read();
-                            entry.owner.inst     = 0;
+                            entry.count       = r_cleanup_count.read();
+                            entry.owner.srcid = r_read_to_cleanup_srcid.read();
+                            entry.owner.inst  = r_read_to_cleanup_inst.read();
                         }
                         else
                         {
-                            entry.count          = r_cleanup_count.read() - 1;
-                            entry.owner.srcid    = r_cleanup_copy.read();
-                            entry.owner.inst     = r_cleanup_copy_inst.read();
+                            entry.count       = r_cleanup_count.read() - 1;
+                            entry.owner.srcid = r_cleanup_copy.read();
+                            entry.owner.inst  = r_cleanup_copy_inst.read();
                         }
                         if (r_read_to_cleanup_is_ll.read())
@@ -5811 +5967 @@
                     else
                     {
-                        entry.count          = r_cleanup_count.read() - 1;
-                        entry.owner.srcid    = 0;
-                        entry.owner.inst     = 0;
+                        entry.count       = r_cleanup_count.read() - 1;
+                        entry.owner.srcid = 0;
+                        entry.owner.inst  = 0;
+
+#if REVERT_CC_MECANISM
+                        // Revert CC to NCC if : 
+                        //  - no more copy in L1 caches
+                        //  - this line is not in counter mode (broadcast)
+                        //  - this line is not in NCC to CC mecanism
+                        if (((r_cleanup_count.read() - 1) == 0) and (r_cleanup_is_cnt == false) and (inval_request == false))
+                        {
+                            entry.cache_coherent = false;
+                        }
+#endif
+
+#if REVERT_BC_MECANISM
+                        if ((r_cleanup_count.read() - 1) == 0) 
+                        {
+                            entry.is_cnt = false;
+                        }
+#endif
+
                     }
 
@@ -5852 +6027 @@
                             << " / is_cnt = "  << entry.is_cnt
                             << " / match_inval = " << inval_request
+                            << " / is_coherent = " << entry.cache_coherent
+                            << std::dec
                             << std::endl;
                     }
@@ -5861 +6038 @@
             case CLEANUP_IVT_LOCK_DATA://RWT
                 {
-                    //Search for a matching inval in the UPT (there must be one) and check if there is a pending read.
+                    //Search for a matching inval in the IVT (there must be one) and check if there is a pending read.
                     if(r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP)
                     {
@@ -5877 +6054 @@
                         r_cleanup_fsm = CLEANUP_IVT_CLEAR_DATA;
                     }
-#if DEBUG_MC_CLEANUP
+#if DEBUG_MEMC_CLEANUP
                     if (m_debug)
                     {
@@ -5902 +6079 @@
                         r_cleanup_fsm = CLEANUP_SEND_CLACK;
                     }
-#if DEBUG_MC_CLEANUP
+#if DEBUG_MEMC_CLEANUP
                     if (m_debug)
                     {
                         std::cout
                             << " <MEMC " << name()
-                            << " CLEANUP_IVT_CLEAR_DATA> clear UPT entry"
+                            << " CLEANUP_IVT_CLEAR_DATA> clear IVT entry"
                             << std::endl;
                     }
@@ -5922 +6099 @@
                     r_cleanup_to_tgt_rsp_srcid   = r_cleanup_read_srcid.read();
                     r_cleanup_to_tgt_rsp_trdid   = r_cleanup_read_trdid.read();
-                    r_cleanup_to_tgt_rsp_pktid   = 0x0 + r_cleanup_read_pktid.read();//WT
+                    r_cleanup_to_tgt_rsp_pktid   = 0x0 + r_cleanup_read_pktid.read();//RWT
                     r_cleanup_to_tgt_rsp_type    = 0; //Read instruction
                     r_cleanup_to_tgt_rsp_length  = r_read_to_cleanup_length.read();
@@ -5945 +6122 @@
                     r_cleanup_fsm                = CLEANUP_SEND_CLACK;
 
-#if DEBUG_MC_CLEANUP
+#if DEBUG_MEMC_CLEANUP
                     if (m_debug)
                     {
@@ -6197 +6374 @@
                     m_heap.write_free_ptr(r_cleanup_next_ptr.read());
                     m_heap.unset_full();
+
+                    // <Activity counters>
+                    m_cpt_heap_slot_available++;
+                    // </Activity counters>
 
                     r_cleanup_fsm = CLEANUP_SEND_CLACK;
@@ -6322 +6503 @@
                     if(r_cleanup_to_tgt_rsp_req.read()) break;
 
+                    assert ( (r_cleanup_ncc.read() == false) and
+                            "CLEANUP_WRITE_RSP : Cleanup on NCC line invalid in "
+                            "MEM_CACHE with write_rsp needed. STRANGE BEHAVIOUR");
                     // no pending request
                     r_cleanup_to_tgt_rsp_req     = true;
@@ -6385 +6569 @@
                                         data_vector);
                             }
-                            //std::cout << "cleanup with a non coherent ligne in trt index = " << index << std::endl;
                             r_cleanup_to_ixr_cmd_srcid        = r_cleanup_srcid.read();
                             r_cleanup_to_ixr_cmd_index        = index;
@@ -7242 +7425 @@
         //
         // It implements a round-robin priority between the four possible client FSMs
-        //     XRAM_RSP > CAS > WRITE > CONFIG 
+        //     XRAM_RSP > CAS > READ > WRITE > CONFIG 
         //
         // Each FSM can request the next services:
@@ -7369 +7552 @@
                         break;
                     }
-                    // WRITE
+                    // READ
                     if(r_read_to_cc_send_req.read())
                     {
@@ -7375 +7558 @@
                         break;
                     }
-
+                    // WRITE
                     if(r_write_to_cc_send_req.read())
                     {
@@ -7395 +7578 @@
                 }
                 ///////////////////////////
-            case CC_SEND_XRAM_RSP_IDLE:   // CAS FSM has highest priority
-                {
+            case CC_SEND_READ_IDLE: 
+                {
+                    // WRITE
+                    if(r_write_to_cc_send_req.read())
+                    {
+                        r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_HEADER;
+                        break;
+                    }
+                    if(m_write_to_cc_send_inst_fifo.rok() or
+                            r_write_to_cc_send_multi_req.read())
+                    {
+                        r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER;
+                        break;
+                    }
+                    if(r_write_to_cc_send_brdcast_req.read())
+                    {
+                        r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER;
+                        break;
+                    }
+                    // CONFIG
+                    if(r_config_to_cc_send_multi_req.read())
+                    {
+                        r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER;
+                        break;
+                    }
+                    if(r_config_to_cc_send_brdcast_req.read())
+                    {
+                        r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER;
+                        break;
+                    }
+                    // XRAM_RSP
+                    if(m_xram_rsp_to_cc_send_inst_fifo.rok() or
+                            r_xram_rsp_to_cc_send_multi_req.read())
+                    {
+                        r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER;
+                        break;
+                    }
+                    if(r_xram_rsp_to_cc_send_brdcast_req.read())
+                    {
+                        r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER;
+                        break;
+                    }
                     // CAS
                     if(m_cas_to_cc_send_inst_fifo.rok() or
@@ -7409 +7632 @@
                         break;
                     }
-
+                    // READ
                     if(r_read_to_cc_send_req.read())
                     {
@@ -7415 +7638 @@
                         break;
                     }
-
-                    if(r_write_to_cc_send_req.read())
-                    {
-                        r_cc_send_fsm = CC_SEND_WRITE_NCC_INVAL_HEADER;
+                    break;
+
+                }
+                ///////////////////////////
+            case CC_SEND_XRAM_RSP_IDLE:   // CAS FSM has highest priority
+                {
+                    // CAS
+                    if(m_cas_to_cc_send_inst_fifo.rok() or
+                            r_cas_to_cc_send_multi_req.read())
+                    {
+                        r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER;
                         break;
                     }
-
-
-                    // WRITE
+                    if(r_cas_to_cc_send_brdcast_req.read())
+                    {
+                        r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER;
+                        break;
+                    }
+
+                    // READ
                     if(r_read_to_cc_send_req.read())
                     {
@@ -7430 +7664 @@
                     }
 
+                    // WRITE
                     if(r_write_to_cc_send_req.read())
                     {
@@ -7473 +7708 @@
                 }
                 //////////////////////
-            case CC_SEND_CAS_IDLE:   // CLEANUP FSM has highest priority
-                {
-
+            case CC_SEND_CAS_IDLE:   // READ FSM has highest priority
+                {
+
+                    // READ
                     if(r_read_to_cc_send_req.read())
                     {
@@ -7481 +7717 @@
                         break;
                     }
-
+                    // WRITE
                     if(r_write_to_cc_send_req.read())
                     {
@@ -7488 +7724 @@
                     }
 
-
                     if(m_write_to_cc_send_inst_fifo.rok() or
                             r_write_to_cc_send_multi_req.read())
@@ -7511 +7746 @@
                         break;
                     }
+                    // XRAM RSP
                     if(m_xram_rsp_to_cc_send_inst_fifo.rok() or
                             r_xram_rsp_to_cc_send_multi_req.read())
@@ -7522 +7758 @@
                         break;
                     }
+                    // CAS
                     if(m_cas_to_cc_send_inst_fifo.rok() or
                             r_cas_to_cc_send_multi_req.read())
@@ -7683 +7920 @@
 
                     r_read_to_cc_send_req = false;
-                    r_cc_send_fsm = CC_SEND_WRITE_IDLE;
+                    r_cc_send_fsm = CC_SEND_READ_IDLE;
 
 #if DEBUG_MEMC_CC_SEND
@@ -7691 +7928 @@
                             << "  <MEMC " << name()
                             << " CC_SEND_READ_NCC_INVAL_HEADER> Inval for line "
-                            << r_read_to_cc_send_nline.read()
+                            << std::hex <<r_read_to_cc_send_nline.read() << std::dec
                             << std::endl;
                     }
@@ -7720 +7957 @@
                             << "  <MEMC " << name()
                             << " CC_SEND_WRITE_NCC_INVAL_HEADER> Inval for line "
-                            << r_write_to_cc_send_nline.read()
+                            << std::hex << r_write_to_cc_send_nline.read() << std::dec
                             << std::endl;
                     }
@@ -8369 +8606 @@
                 }
                 /////////////////////
-            case TGT_RSP_CLEANUP:   // pas clair pour moi (AG)
+            case TGT_RSP_CLEANUP:
                 {
                     if(p_vci_tgt.rspack)
@@ -9616 +9853 @@
             }
         }
-        //m_cc_receive_to_cleanup_fifo.update( cc_receive_to_cleanup_fifo_get,
-        //                                     cc_receive_to_cleanup_fifo_put, 
-        //                                     p_dspin_p2m.data.read() );
 
         ////////////////////////////////////////////////////////////////////////////////////
@@ -9679 +9913 @@
             r_config_rsp_lines = r_config_rsp_lines.read() - 1;
         }
+
+        ////////////////////////////////////////////////////////////////////////////////////
+        //            Update min m_cpt_heap_min_slot_available.
+        // The four sources of (increment / decrement) are READ / CLEANUP / XRAM_RSP / CONFIG FSMs 
+        ////////////////////////////////////////////////////////////////////////////////////
+        assert((m_cpt_heap_slot_available <= m_heap_size) and "m_cpt_heap_slot_available > m_heap_size");
+        assert((m_cpt_heap_min_slot_available <= m_heap_size) and "m_cpt_heap_min_slot_available > m_heap_size");
+        m_cpt_heap_min_slot_available = min_value(m_cpt_heap_min_slot_available, m_cpt_heap_slot_available);
 
     } // end transition()
@@ -9759 +10001 @@
             p_vci_ixr.cmd     = vci_param_ext::CMD_WRITE;
             p_vci_ixr.cmdval  = true;
-            /*p_vci_ixr.address = (addr_t)((r_cleanup_to_ixr_cmd_nline.read() * m_words + 
-              r_ixr_cmd_word.read()) * 4);*/
             p_vci_ixr.address = (addr_t)r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2);
             p_vci_ixr.wdata   = ((wide_data_t)(r_ixr_cmd_wdata[r_ixr_cmd_word.read()].read()) | 
@@ -9988 +10228 @@
 
         ////////////////////////////////////////////////////////////////////
+        //  p_irq port
+        //
+        //  WRITE MISS response error signaling
+        ////////////////////////////////////////////////////////////////////
+
+        p_irq =
+            r_xram_rsp_rerror_irq.read() &&
+            r_xram_rsp_rerror_irq_enable.read();
+
+        ////////////////////////////////////////////////////////////////////
         //  p_dspin_m2p port (CC_SEND FSM)
         ////////////////////////////////////////////////////////////////////
@@ -10026 +10276 @@
                             DspinDhccpParam::MULTI_INVAL_DEST);
 
-                    DspinDhccpParam::dspin_set( flit,
-                            m_cc_global_id,
-                            DspinDhccpParam::MULTI_INVAL_SRCID);
-
                     // MODIFIED FOR CONFIG INVAL (solution 1 bit in flit multi_inval)
                     DspinDhccpParam::dspin_set( flit,
@@ -10082 +10328 @@
 
                     DspinDhccpParam::dspin_set( flit,
-                            m_cc_global_id,
-                            DspinDhccpParam::MULTI_INVAL_SRCID);
-
-                    DspinDhccpParam::dspin_set( flit,
                             r_xram_rsp_to_cc_send_trdid.read(),
                             DspinDhccpParam::MULTI_INVAL_UPDT_INDEX);
@@ -10119 +10361 @@
                             m_broadcast_boundaries,
                             DspinDhccpParam::BROADCAST_BOX);
-                    // MODIFIED FOR CONFIG INVAL (solution 1 bit in flit multi_inval)
+                    
                     DspinDhccpParam::dspin_set( flit,
                             1,
                             DspinDhccpParam::MULTI_INVAL_IS_CONFIG);
-
-                    DspinDhccpParam::dspin_set( flit,
-                            m_cc_global_id,
-                            DspinDhccpParam::BROADCAST_SRCID);
 
                     DspinDhccpParam::dspin_set( flit,
@@ -10145 +10383 @@
                             m_broadcast_boundaries,
                             DspinDhccpParam::BROADCAST_BOX);
-
-                    DspinDhccpParam::dspin_set( flit,
-                            m_cc_global_id,
-                            DspinDhccpParam::BROADCAST_SRCID);
 
                     DspinDhccpParam::dspin_set( flit,
@@ -10204 +10438 @@
                     DspinDhccpParam::dspin_set(
                             flit,
-                            m_cc_global_id,
-                            DspinDhccpParam::MULTI_INVAL_SRCID);
-
-                    DspinDhccpParam::dspin_set(
-                            flit,
                             DspinDhccpParam::TYPE_MULTI_INVAL_DATA,
                             DspinDhccpParam::M2P_TYPE);
@@ -10246 +10475 @@
                             r_write_to_cc_send_dest.read(),
                             DspinDhccpParam::MULTI_INVAL_DEST);
-
-                    DspinDhccpParam::dspin_set(
-                            flit,
-                            m_cc_global_id,
-                            DspinDhccpParam::MULTI_INVAL_SRCID);
 
                     DspinDhccpParam::dspin_set(
@@ -10333 +10557 @@
                     DspinDhccpParam::dspin_set(
                             flit,
-                            m_cc_global_id,
-                            DspinDhccpParam::MULTI_UPDT_SRCID);
-
-                    DspinDhccpParam::dspin_set(
-                            flit,
                             r_write_to_cc_send_trdid.read(),
                             DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);
@@ -10423 +10642 @@
                             dest,
                             DspinDhccpParam::MULTI_UPDT_DEST);
-
-                    DspinDhccpParam::dspin_set(
-                            flit,
-                            m_cc_global_id,
-                            DspinDhccpParam::MULTI_UPDT_SRCID);
 
                     DspinDhccpParam::dspin_set(