Changeset 767 for branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include

Timestamp:

Aug 25, 2014, 5:58:16 PM (10 years ago)

Author:

devigne

Message:

RWT commit :

• Merge with trunk.

• Cosmetic

• Bugfix in state WRITE_IVT_LOCK_HIT_WB.

MemCache? records invalidation in IVT in this state but we do not check that
the IVT was full. Thus invalidation was issued without actually recorded in the
query IVT ...

• Bugfix :

When a NCC line owned by a L1 cache with srcid != 0 was removed from MemCache?,
the owner field was reset to 0. If this same L1 cache was sending a read to
retrieve this line the MemCache? sent this line on CC mode.

• Bugfix :

The MemCache? reset the 'inst' field to 0 when solving a
invalidation due to a change of state of line (NCC to CC).
But a line can be NCC (ie contained in a DATA cache) then asked by INST cache,
this read triggers a transition NCC to CC but we must save the nature of this read.
Now this information is stored in a register (r_read_to_cleanup_inst).

• Add a counter for the number of minimum inputs available

in the heap. This counter indicates whether the heap size of 4096 is relevant.

File:

• branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (modified) (4 diffs)

branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h

@@ -280 +280 @@
     };
 
-//    enum transaction_type_d_e
-//    {
-//        // b0 : 1 if cached
-//        // b1 : 1 if instruction
-//        TYPE_DATA_UNC     = 0x0,
-//        TYPE_DATA_MISS    = 0x1,
-//        TYPE_INS_UNC      = 0x2,
-//        TYPE_INS_MISS     = 0x3,
-//    };
-
-    //////////////////MODIFIED////////////////
+
+    // cache line status
     enum content_line_cache_status_e
     {
@@ -522 +513 @@
     sc_signal<size_t>       r_dcache_cc_send_updt_tab_idx;  // DCACHE cc_send update table index
     
-    // special registers for ODCCP/RWT
-    sc_signal<bool>         r_dcache_cc_cleanup_updt_data;          // Register for cleanup with data (wb updt)
-    sc_signal<bool>         r_dcache_cc_cleanup_line_ncc;          // Register for cleanup with data (wb updt)
-    sc_signal<bool>         r_dcache_miss_victim_no_coherence;      // Register for victim in no coherence mode
-    sc_signal<bool>         r_dcache_line_no_coherence;             // Register for line current in no coherence mode
+    // special registers for RWT
+    sc_signal<bool>         r_dcache_cc_cleanup_updt_data;     // Register for cleanup with data (wb updt)
+    sc_signal<bool>         r_dcache_cc_cleanup_line_ncc;      // Register for cleanup with data (wb updt)
+    sc_signal<bool>         r_dcache_miss_victim_no_coherence; // Register for victim in no coherence mode
+    sc_signal<bool>         r_dcache_line_no_coherence;        // Register for line current in no coherence mode
     sc_signal<bool>         r_dcache_dirty_save;             
     sc_signal<uint32_t>     r_cc_send_cpt_word;
@@ -536 +527 @@
     sc_signal<paddr_t>      r_dcache_xtn_data_addr;
     sc_signal<uint32_t>     r_dcache_xtn_data_cpt;
+    sc_signal<bool>         r_dcache_read_state;
+
     // dcache directory extension
-    ///////////////////////////MODIFIED///////////////////////////////////////////////////
-    //bool                    *r_dcache_in_tlb;           // copy exist in dtlb or itlb
-    //bool                    *r_dcache_contains_ptd;     // cache line contains a PTD
     int                     *r_dcache_content_state; // content state of one cache line
-    int                     *r_dcache_dirty_word;    
-    bool                    *r_dcache_zombi_ncc;     
+    // Stats
+    int                     *r_dcache_dirty_word;    // use for compute number of words dirty per cleanup_data
+    bool                    *r_dcache_zombi_ncc;     // use for compute number of blocked write on ncc zombi line
     //////////////////////////////////////////////////////////////////////////////////////
 
-    //RWT
-    sc_signal<bool>         r_dcache_read_state;
-   
-     ///////////////////////////////////
+    ///////////////////////////////////
     // Physical address extension for data access
     sc_signal<uint32_t>     r_dcache_paddr_ext;             // CP2 register (if vci_address > 32)
@@ -574 +562 @@
     //RWT
     GenericFifo<bool>       r_vci_rsp_fifo_rpktid;
-
     GenericFifo<uint32_t>   r_cc_send_data_fifo;