Index: branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
===================================================================
--- branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	(revision 644)
+++ branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	(revision 767)
@@ -83,6 +83,6 @@
         TGT_CMD_WRITE,
         TGT_CMD_CAS,
-        TGT_CMD_ERROR,
-        TGT_CMD_CONFIG
+        TGT_CMD_CONFIG,
+        TGT_CMD_ERROR
       };
 
@@ -96,6 +96,6 @@
         TGT_RSP_MULTI_ACK_IDLE,
         TGT_RSP_CLEANUP_IDLE,
+        TGT_RSP_TGT_CMD_IDLE,
         TGT_RSP_CONFIG_IDLE,
-        TGT_RSP_TGT_CMD_IDLE,
         TGT_RSP_READ,
         TGT_RSP_WRITE,
@@ -104,6 +104,6 @@
         TGT_RSP_MULTI_ACK,
         TGT_RSP_CLEANUP,
-        TGT_RSP_CONFIG,
-        TGT_RSP_TGT_CMD
+        TGT_RSP_TGT_CMD,
+        TGT_RSP_CONFIG
       };
 
@@ -122,4 +122,5 @@
         CC_SEND_XRAM_RSP_IDLE,
         CC_SEND_WRITE_IDLE,
+        CC_SEND_READ_IDLE,
         CC_SEND_CAS_IDLE,
         CC_SEND_CONFIG_IDLE,
@@ -437,4 +438,5 @@
       uint32_t     m_cpt_write_flits_remote; // number of flits for remote WRITEs
       uint32_t     m_cpt_write_cost;     // Number of (flits * distance) for WRITEs
+      uint32_t     m_cpt_write_ncc_miss;   // Number of write on ncc line
 
       uint32_t     m_cpt_ll_local;       // Number of local LL transactions
@@ -552,5 +554,7 @@
       uint32_t     m_cpt_xram_rsp_fsm_heap_used; // NB cycles HEAP LOCK used
       
-      uint32_t     m_cpt_heap_unused;            // NB cycles HEAP LOCK unused
+      uint32_t     m_cpt_heap_unused;             // NB cycles HEAP LOCK unused
+      uint32_t     m_cpt_heap_slot_available;     // NB HEAP slot available refresh at each cycles
+      uint32_t     m_cpt_heap_min_slot_available; // NB HEAP : Min of slot available 
 
       //RWT
@@ -584,5 +588,5 @@
       sc_in<bool>                                 p_clk;
       sc_in<bool>                                 p_resetn;
-      sc_in<bool>                                 p_irq;
+      sc_out<bool>                                p_irq;
       soclib::caba::VciTarget<vci_param_int>      p_vci_tgt;
       soclib::caba::VciInitiator<vci_param_ext>   p_vci_ixr;
@@ -618,5 +622,4 @@
           const soclib::common::IntTab       &srcid_x,        // global index RAM network
           const soclib::common::IntTab       &tgtid_d,        // global index INT network
-          const size_t                       cc_global_id,    // global index CC network
           const size_t                       x_width,         // X width in platform
           const size_t                       y_width,         // Y width in platform
@@ -635,5 +638,5 @@
 
       void reset_counters();
-      void print_stats(bool activity_counters, bool stats);
+      void print_stats(bool activity_counters = true, bool stats = false);
       void print_trace( size_t detailled = 0 );
       void cache_monitor(addr_t addr);
@@ -647,4 +650,5 @@
       void check_monitor(addr_t addr, data_t data, bool read);
       uint32_t req_distance(uint32_t req_srcid);
+      uint32_t min_value(uint32_t old_value, uint32_t new_value);
       bool is_local_req(uint32_t req_srcid);
       int  read_instrumentation(uint32_t regr, uint32_t & rdata);
@@ -661,7 +665,8 @@
       const size_t                       m_sets;             // Number of cache sets
       const size_t                       m_words;            // Number of words in a line
-      const size_t                       m_cc_global_id;     // global_index on cc network
-      const size_t                       m_xwidth;           // number of x bits in platform
-      const size_t                       m_ywidth;           // number of y bits in platform
+      size_t                             m_x_self;           // X self coordinate
+      size_t                             m_y_self;           // Y self coordinate
+      const size_t                       m_x_width;          // number of x bits in platform
+      const size_t                       m_y_width;          // number of y bits in platform
       size_t                             m_debug_start_cycle;
       bool                               m_debug_ok;
@@ -834,4 +839,5 @@
       sc_signal<addr_t>   r_read_to_cleanup_nline;  // cache line index
       sc_signal<size_t>   r_read_to_cleanup_srcid;
+      sc_signal<size_t>   r_read_to_cleanup_inst;
       sc_signal<size_t>   r_read_to_cleanup_length;
       sc_signal<size_t>   r_read_to_cleanup_first_word;
@@ -1069,4 +1075,8 @@
       sc_signal<size_t>   r_xram_rsp_ivt_index;         // IVT entry index
       sc_signal<size_t>   r_xram_rsp_next_ptr;          // Next pointer to the heap
+      sc_signal<bool>     r_xram_rsp_rerror_irq;        // WRITE MISS rerror irq
+      sc_signal<bool>     r_xram_rsp_rerror_irq_enable; // WRITE MISS rerror irq enable
+      sc_signal<addr_t>   r_xram_rsp_rerror_address;    // WRITE MISS rerror address
+      sc_signal<size_t>   r_xram_rsp_rerror_rsrcid;     // WRITE MISS rerror srcid
 
       // Buffer between XRAM_RSP fsm and TGT_RSP fsm  (response to L1 cache)
