Changeset 771 for branches/RWT/modules/vci_cc_vcache_wrapper
- Timestamp:
- Aug 26, 2014, 4:40:29 PM (10 years ago)
- Location:
- branches/RWT/modules/vci_cc_vcache_wrapper/caba
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
branches/RWT/modules/vci_cc_vcache_wrapper/caba/metadata/vci_cc_vcache_wrapper.sd
r468 r771 3 3 4 4 Module('caba:vci_cc_vcache_wrapper', 5 5 classname = 'soclib::caba::VciCcVCacheWrapper', 6 6 7 7 tmpl_parameters = [ 8 8 parameter.Module('vci_param', default = 'caba:vci_param'), 9 9 parameter.Int('dspin_in_width'), 10 10 parameter.Int('dspin_out_width'), 11 11 parameter.Module('iss_t') 12 12 ], 13 13 14 14 header_files = [ '../source/include/vci_cc_vcache_wrapper.h' ], 15 15 16 16 implementation_files = [ '../source/src/vci_cc_vcache_wrapper.cpp' ], 17 17 18 18 uses = [ 19 19 Uses('caba:base_module'), 20 20 Uses('common:mapping_table'), 21 22 23 24 Uses('caba:generic_cache_tsar',21 Uses('common:iss2'), 22 Uses('caba:multi_write_buffer'), 23 Uses('caba:generic_fifo'), 24 Uses('caba:generic_cache_tsar_rwt', 25 25 addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', 26 26 parameter.Reference('addr_size'))), … … 32 32 parameter.Reference('addr_size')) 33 33 ), 34 Uses('caba:dspin_dhccp_param'),34 Uses('caba:dspin_rwt_param'), 35 35 ], 36 36 37 37 ports = [ 38 38 Port('caba:vci_initiator', 'p_vci'), 39 39 Port('caba:dspin_input', 'p_dspin_m2p', … … 43 43 Port('caba:dspin_input', 'p_dspin_clack', 44 44 dspin_data_size = parameter.Reference('dspin_in_width')), 45 46 47 45 Port('caba:bit_in','p_irq', parameter.Constant('n_irq')), 46 Port('caba:bit_in', 'p_resetn', auto = 'resetn'), 47 Port('caba:clock_in', 'p_clk', auto = 'clock') 48 48 ], 49 49 50 50 instance_parameters = [ 51 51 parameter.Int('proc_id'), 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 52 parameter.Module('mt', 'common:mapping_table'), 53 parameter.Module('mc', 'common:mapping_table'), 54 parameter.IntTab('initiator_rw_index'), 55 parameter.IntTab('initiator_c_index'), 56 parameter.IntTab('target_index'), 57 parameter.Int('itlb_ways'), 58 parameter.Int('itlb_sets'), 59 parameter.Int('dtlb_ways'), 60 parameter.Int('dtlb_sets'), 61 parameter.Int('icache_ways'), 62 parameter.Int('icache_sets'), 63 parameter.Int('icache_words'), 64 parameter.Int('dcache_ways'), 65 parameter.Int('dcache_sets'), 66 parameter.Int('dcache_words'), 67 parameter.Int('wbuf_nlines'), 68 parameter.Int('wbuf_nwords'), 69 parameter.Int('max_frozen_cycles') 70 70 ], 71 71 ) -
branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
r767 r771 35 35 #include <inttypes.h> 36 36 #include <systemc> 37 37 38 #include "caba_base_module.h" 38 39 #include "multi_write_buffer.h" … … 42 43 #include "vci_initiator.h" 43 44 #include "dspin_interface.h" 44 #include "dspin_ dhccp_param.h"45 #include "dspin_rwt_param.h" 45 46 #include "mapping_table.h" 46 47 #include "static_assert.h" -
branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r767 r771 4289 4289 4290 4290 uint32_t rdata; 4291 size_t way ;4292 size_t set ;4291 size_t way = 0; // To avoid gcc warning 4292 size_t set = 0; // To avoid gcc warning 4293 4293 size_t word; 4294 4294 r_dcache.read_neutral(r_dcache_xtn_data_addr.read(), … … 5379 5379 5380 5380 uint32_t rdata; 5381 size_t way ;5382 size_t set ;5381 size_t way = 0; // to avoid gcc warning 5382 size_t set = 0; // to avoid gcc warning 5383 5383 size_t word; 5384 5384 r_dcache.read_neutral(r_dcache_cc_inval_addr.read(), … … 5399 5399 r_dcache_cc_inval_data_cpt = 0; 5400 5400 r_dcache_fsm = r_dcache_fsm_cc_save.read(); 5401 r_dcache.write_dir( 5402 5403 5401 r_dcache.write_dir(way, 5402 set, 5403 CACHE_SLOT_STATE_ZOMBI ); 5404 5404 } 5405 5405 } … … 6207 6207 uint64_t receive_data = p_dspin_m2p.data.read(); 6208 6208 // initialize coherence packet type 6209 uint64_t receive_type = Dspin DhccpParam::dspin_get(receive_data,6210 Dspin DhccpParam::M2P_TYPE);6209 uint64_t receive_type = DspinRwtParam::dspin_get(receive_data, 6210 DspinRwtParam::M2P_TYPE); 6211 6211 // test for a broadcast 6212 if (Dspin DhccpParam::dspin_get(receive_data,DspinDhccpParam::M2P_BC))6212 if (DspinRwtParam::dspin_get(receive_data,DspinRwtParam::M2P_BC)) 6213 6213 { 6214 6214 r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER; 6215 6215 } 6216 6216 // test for a multi updt 6217 else if (receive_type == Dspin DhccpParam::TYPE_MULTI_UPDT_DATA)6217 else if (receive_type == DspinRwtParam::TYPE_MULTI_UPDT_DATA) 6218 6218 { 6219 6219 r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_HEADER; 6220 6220 } 6221 else if (receive_type == Dspin DhccpParam::TYPE_MULTI_UPDT_INST)6221 else if (receive_type == DspinRwtParam::TYPE_MULTI_UPDT_INST) 6222 6222 { 6223 6223 r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_HEADER; 6224 6224 } 6225 6225 // test for a multi inval 6226 else if (receive_type == Dspin DhccpParam::TYPE_MULTI_INVAL_DATA)6226 else if (receive_type == DspinRwtParam::TYPE_MULTI_INVAL_DATA) 6227 6227 { 6228 6228 r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_HEADER; … … 6257 6257 // request dcache to handle the BROADCAST 6258 6258 r_cc_receive_dcache_req = true; 6259 r_cc_receive_dcache_nline = Dspin DhccpParam::dspin_get(receive_data,6260 Dspin DhccpParam::BROADCAST_NLINE);6259 r_cc_receive_dcache_nline = DspinRwtParam::dspin_get(receive_data, 6260 DspinRwtParam::BROADCAST_NLINE); 6261 6261 r_cc_receive_dcache_type = CC_TYPE_INVAL; 6262 6262 // request icache to handle the BROADCAST 6263 6263 r_cc_receive_icache_req = true; 6264 r_cc_receive_icache_nline = Dspin DhccpParam::dspin_get(receive_data,6265 Dspin DhccpParam::BROADCAST_NLINE);6264 r_cc_receive_icache_nline = DspinRwtParam::dspin_get(receive_data, 6265 DspinRwtParam::BROADCAST_NLINE); 6266 6266 r_cc_receive_icache_type = CC_TYPE_INVAL; 6267 6267 // get back to idle state … … 6279 6279 // sample updt tab index in the HEADER, then skip to second flit 6280 6280 r_cc_receive_fsm = CC_RECEIVE_DATA_INVAL_NLINE; 6281 r_cc_receive_dcache_inval_is_config = Dspin DhccpParam::dspin_get(receive_data,6282 Dspin DhccpParam::MULTI_INVAL_IS_CONFIG);6281 r_cc_receive_dcache_inval_is_config = DspinRwtParam::dspin_get(receive_data, 6282 DspinRwtParam::MULTI_INVAL_IS_CONFIG); 6283 6283 break; 6284 6284 } … … 6301 6301 // request dcache to handle the INVAL 6302 6302 r_cc_receive_dcache_req = true; 6303 r_cc_receive_dcache_nline = Dspin DhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);6303 r_cc_receive_dcache_nline = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_INVAL_NLINE); 6304 6304 r_cc_receive_dcache_type = CC_TYPE_INVAL; 6305 6305 // get back to idle state … … 6320 6320 // request icache to handle the INVAL 6321 6321 r_cc_receive_icache_req = true; 6322 r_cc_receive_icache_nline = Dspin DhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_INVAL_NLINE);6322 r_cc_receive_icache_nline = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_INVAL_NLINE); 6323 6323 r_cc_receive_icache_type = CC_TYPE_INVAL; 6324 6324 // get back to idle state … … 6337 6337 if (not r_cc_receive_dcache_req.read()) 6338 6338 { 6339 r_cc_receive_dcache_updt_tab_idx = Dspin DhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);6339 r_cc_receive_dcache_updt_tab_idx = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_UPDT_INDEX); 6340 6340 r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_NLINE; 6341 6341 break; … … 6352 6352 if (not r_cc_receive_icache_req.read()) 6353 6353 { 6354 r_cc_receive_icache_updt_tab_idx = Dspin DhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX);6354 r_cc_receive_icache_updt_tab_idx = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_UPDT_INDEX); 6355 6355 r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_NLINE; 6356 6356 break; … … 6370 6370 { 6371 6371 r_cc_receive_dcache_req = true; 6372 r_cc_receive_dcache_nline = Dspin DhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);6373 r_cc_receive_word_idx = Dspin DhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);6372 r_cc_receive_dcache_nline = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_NLINE); 6373 r_cc_receive_word_idx = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_WORD_INDEX); 6374 6374 r_cc_receive_dcache_type = CC_TYPE_UPDT; 6375 6375 // get back to idle state … … 6390 6390 { 6391 6391 r_cc_receive_icache_req = true; 6392 r_cc_receive_icache_nline = Dspin DhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE);6393 r_cc_receive_word_idx = Dspin DhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX);6392 r_cc_receive_icache_nline = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_NLINE); 6393 r_cc_receive_word_idx = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_WORD_INDEX); 6394 6394 r_cc_receive_icache_type = CC_TYPE_UPDT; 6395 6395 // get back to idle state … … 6407 6407 uint64_t receive_data = p_dspin_m2p.data.read(); 6408 6408 bool receive_eop = p_dspin_m2p.eop.read(); 6409 cc_receive_updt_fifo_be = Dspin DhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);6410 cc_receive_updt_fifo_data = Dspin DhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);6409 cc_receive_updt_fifo_be = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_BE); 6410 cc_receive_updt_fifo_data = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_DATA); 6411 6411 cc_receive_updt_fifo_eop = receive_eop; 6412 6412 cc_receive_updt_fifo_put = true; … … 6423 6423 uint64_t receive_data = p_dspin_m2p.data.read(); 6424 6424 bool receive_eop = p_dspin_m2p.eop.read(); 6425 cc_receive_updt_fifo_be = Dspin DhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_BE);6426 cc_receive_updt_fifo_data = Dspin DhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_DATA);6425 cc_receive_updt_fifo_be = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_BE); 6426 cc_receive_updt_fifo_data = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_DATA); 6427 6427 cc_receive_updt_fifo_eop = receive_eop; 6428 6428 cc_receive_updt_fifo_put = true; … … 6436 6436 ///////////////// DSPIN CLACK interface /////////////// 6437 6437 6438 uint64_t clack_type = Dspin DhccpParam::dspin_get(r_dspin_clack_flit.read(),6439 Dspin DhccpParam::CLACK_TYPE);6440 6441 size_t clack_way = Dspin DhccpParam::dspin_get(r_dspin_clack_flit.read(),6442 Dspin DhccpParam::CLACK_WAY);6443 6444 size_t clack_set = Dspin DhccpParam::dspin_get(r_dspin_clack_flit.read(),6445 Dspin DhccpParam::CLACK_SET);6438 uint64_t clack_type = DspinRwtParam::dspin_get(r_dspin_clack_flit.read(), 6439 DspinRwtParam::CLACK_TYPE); 6440 6441 size_t clack_way = DspinRwtParam::dspin_get(r_dspin_clack_flit.read(), 6442 DspinRwtParam::CLACK_WAY); 6443 6444 size_t clack_set = DspinRwtParam::dspin_get(r_dspin_clack_flit.read(), 6445 DspinRwtParam::CLACK_SET); 6446 6446 6447 6447 bool dspin_clack_get = false; 6448 bool dcache_clack_request = (clack_type == Dspin DhccpParam::TYPE_CLACK_DATA);6449 bool icache_clack_request = (clack_type == Dspin DhccpParam::TYPE_CLACK_INST);6448 bool dcache_clack_request = (clack_type == DspinRwtParam::TYPE_CLACK_DATA); 6449 bool icache_clack_request = (clack_type == DspinRwtParam::TYPE_CLACK_INST); 6450 6450 6451 6451 if (r_dspin_clack_req.read()) … … 6701 6701 { 6702 6702 // initialize dspin send data 6703 Dspin DhccpParam::dspin_set(dspin_send_data,6703 DspinRwtParam::dspin_set(dspin_send_data, 6704 6704 m_cc_global_id, 6705 Dspin DhccpParam::CLEANUP_SRCID);6706 Dspin DhccpParam::dspin_set(dspin_send_data,6705 DspinRwtParam::CLEANUP_SRCID); 6706 DspinRwtParam::dspin_set(dspin_send_data, 6707 6707 0, 6708 Dspin DhccpParam::P2M_BC);6708 DspinRwtParam::P2M_BC); 6709 6709 6710 6710 if(r_cc_send_last_client.read() == 0) // dcache active request … … 6712 6712 uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read() 6713 6713 >> (m_nline_width - m_x_width - m_y_width) 6714 << (Dspin DhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);6715 Dspin DhccpParam::dspin_set(dspin_send_data,6714 << (DspinRwtParam::GLOBALID_WIDTH - m_x_width - m_y_width); 6715 DspinRwtParam::dspin_set(dspin_send_data, 6716 6716 dest, 6717 Dspin DhccpParam::CLEANUP_DEST);6718 6719 Dspin DhccpParam::dspin_set(dspin_send_data,6717 DspinRwtParam::CLEANUP_DEST); 6718 6719 DspinRwtParam::dspin_set(dspin_send_data, 6720 6720 (r_dcache_cc_send_nline.read() & 0x300000000ULL)>>32, 6721 Dspin DhccpParam::CLEANUP_NLINE_MSB);6722 6723 Dspin DhccpParam::dspin_set(dspin_send_data,6721 DspinRwtParam::CLEANUP_NLINE_MSB); 6722 6723 DspinRwtParam::dspin_set(dspin_send_data, 6724 6724 r_dcache_cc_send_way.read(), 6725 Dspin DhccpParam::CLEANUP_WAY_INDEX);6726 6727 Dspin DhccpParam::dspin_set(dspin_send_data,6728 Dspin DhccpParam::TYPE_CLEANUP_DATA,6729 Dspin DhccpParam::P2M_TYPE);6730 6731 Dspin DhccpParam::dspin_set(dspin_send_data,6725 DspinRwtParam::CLEANUP_WAY_INDEX); 6726 6727 DspinRwtParam::dspin_set(dspin_send_data, 6728 DspinRwtParam::TYPE_CLEANUP_DATA, 6729 DspinRwtParam::P2M_TYPE); 6730 6731 DspinRwtParam::dspin_set(dspin_send_data, 6732 6732 (r_dcache_cc_cleanup_line_ncc.read() and (r_cc_send_last_client.read() == 0)), 6733 Dspin DhccpParam::CLEANUP_NCC);6733 DspinRwtParam::CLEANUP_NCC); 6734 6734 } 6735 6735 else // icache active request … … 6737 6737 uint64_t dest = (uint64_t) r_icache_cc_send_nline.read() 6738 6738 >> (m_nline_width - m_x_width - m_y_width) 6739 << (Dspin DhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);6740 6741 Dspin DhccpParam::dspin_set(dspin_send_data,6739 << (DspinRwtParam::GLOBALID_WIDTH - m_x_width - m_y_width); 6740 6741 DspinRwtParam::dspin_set(dspin_send_data, 6742 6742 dest, 6743 Dspin DhccpParam::CLEANUP_DEST);6744 6745 Dspin DhccpParam::dspin_set(dspin_send_data,6743 DspinRwtParam::CLEANUP_DEST); 6744 6745 DspinRwtParam::dspin_set(dspin_send_data, 6746 6746 (r_icache_cc_send_nline.read() & 0x300000000ULL)>>32, 6747 Dspin DhccpParam::CLEANUP_NLINE_MSB);6748 6749 Dspin DhccpParam::dspin_set(dspin_send_data,6747 DspinRwtParam::CLEANUP_NLINE_MSB); 6748 6749 DspinRwtParam::dspin_set(dspin_send_data, 6750 6750 r_icache_cc_send_way.read(), 6751 Dspin DhccpParam::CLEANUP_WAY_INDEX);6752 6753 Dspin DhccpParam::dspin_set(dspin_send_data,6754 Dspin DhccpParam::TYPE_CLEANUP_INST,6755 Dspin DhccpParam::P2M_TYPE);6756 6757 Dspin DhccpParam::dspin_set(dspin_send_data,6751 DspinRwtParam::CLEANUP_WAY_INDEX); 6752 6753 DspinRwtParam::dspin_set(dspin_send_data, 6754 DspinRwtParam::TYPE_CLEANUP_INST, 6755 DspinRwtParam::P2M_TYPE); 6756 6757 DspinRwtParam::dspin_set(dspin_send_data, 6758 6758 0, 6759 Dspin DhccpParam::CLEANUP_NCC);6759 DspinRwtParam::CLEANUP_NCC); 6760 6760 6761 6761 … … 6773 6773 if(r_cc_send_last_client.read() == 0) // dcache active request 6774 6774 { 6775 Dspin DhccpParam::dspin_set(dspin_send_data,6775 DspinRwtParam::dspin_set(dspin_send_data, 6776 6776 r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL, 6777 Dspin DhccpParam::CLEANUP_NLINE_LSB);6777 DspinRwtParam::CLEANUP_NLINE_LSB); 6778 6778 } 6779 6779 else // icache active request 6780 6780 { 6781 Dspin DhccpParam::dspin_set(dspin_send_data,6781 DspinRwtParam::dspin_set(dspin_send_data, 6782 6782 r_icache_cc_send_nline.read() & 0xFFFFFFFFULL, 6783 Dspin DhccpParam::CLEANUP_NLINE_LSB);6783 DspinRwtParam::CLEANUP_NLINE_LSB); 6784 6784 } 6785 6785 // send flit … … 6793 6793 { 6794 6794 6795 Dspin DhccpParam::dspin_set(dspin_send_data,6795 DspinRwtParam::dspin_set(dspin_send_data, 6796 6796 r_cc_send_data_fifo.read(), 6797 Dspin DhccpParam::CLEANUP_DATA_UPDT);6797 DspinRwtParam::CLEANUP_DATA_UPDT); 6798 6798 6799 6799 p_dspin_p2m.data = dspin_send_data; … … 6806 6806 { 6807 6807 // initialize dspin send data 6808 Dspin DhccpParam::dspin_set(dspin_send_data,6808 DspinRwtParam::dspin_set(dspin_send_data, 6809 6809 0, 6810 Dspin DhccpParam::P2M_BC);6811 Dspin DhccpParam::dspin_set(dspin_send_data,6812 Dspin DhccpParam::TYPE_MULTI_ACK,6813 Dspin DhccpParam::P2M_TYPE);6810 DspinRwtParam::P2M_BC); 6811 DspinRwtParam::dspin_set(dspin_send_data, 6812 DspinRwtParam::TYPE_MULTI_ACK, 6813 DspinRwtParam::P2M_TYPE); 6814 6814 6815 6815 if(r_cc_send_last_client.read() == 0) // dcache active request … … 6817 6817 uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read() 6818 6818 >> (m_nline_width - m_x_width - m_y_width) 6819 << (Dspin DhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);6819 << (DspinRwtParam::GLOBALID_WIDTH - m_x_width - m_y_width); 6820 6820 6821 Dspin DhccpParam::dspin_set(dspin_send_data,6821 DspinRwtParam::dspin_set(dspin_send_data, 6822 6822 dest, 6823 Dspin DhccpParam::MULTI_ACK_DEST);6824 6825 Dspin DhccpParam::dspin_set(dspin_send_data,6823 DspinRwtParam::MULTI_ACK_DEST); 6824 6825 DspinRwtParam::dspin_set(dspin_send_data, 6826 6826 r_dcache_cc_send_updt_tab_idx.read(), 6827 Dspin DhccpParam::MULTI_ACK_UPDT_INDEX);6827 DspinRwtParam::MULTI_ACK_UPDT_INDEX); 6828 6828 } 6829 6829 else // icache active request … … 6831 6831 uint64_t dest = (uint64_t) r_icache_cc_send_nline.read() 6832 6832 >> (m_nline_width - m_x_width - m_y_width) 6833 << (Dspin DhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width);6833 << (DspinRwtParam::GLOBALID_WIDTH - m_x_width - m_y_width); 6834 6834 6835 6835 6836 Dspin DhccpParam::dspin_set(dspin_send_data,6836 DspinRwtParam::dspin_set(dspin_send_data, 6837 6837 dest, 6838 Dspin DhccpParam::MULTI_ACK_DEST);6839 6840 Dspin DhccpParam::dspin_set(dspin_send_data,6838 DspinRwtParam::MULTI_ACK_DEST); 6839 6840 DspinRwtParam::dspin_set(dspin_send_data, 6841 6841 r_icache_cc_send_updt_tab_idx.read(), 6842 Dspin DhccpParam::MULTI_ACK_UPDT_INDEX);6842 DspinRwtParam::MULTI_ACK_UPDT_INDEX); 6843 6843 } 6844 6844 // send flit … … 6938 6938 6939 6939 6940 int clack_type = Dspin DhccpParam::dspin_get(r_dspin_clack_flit.read(),6941 Dspin DhccpParam::CLACK_TYPE);6940 int clack_type = DspinRwtParam::dspin_get(r_dspin_clack_flit.read(), 6941 DspinRwtParam::CLACK_TYPE); 6942 6942 6943 6943 bool dspin_clack_get = false; 6944 bool dcache_clack_request = (clack_type == Dspin DhccpParam::TYPE_CLACK_DATA);6945 bool icache_clack_request = (clack_type == Dspin DhccpParam::TYPE_CLACK_INST);6944 bool dcache_clack_request = (clack_type == DspinRwtParam::TYPE_CLACK_DATA); 6945 bool icache_clack_request = (clack_type == DspinRwtParam::TYPE_CLACK_INST); 6946 6946 6947 6947 if (r_dspin_clack_req.read())
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