Changeset 785 for branches/MESI/modules/vci_mem_cache
- Timestamp:
- Sep 2, 2014, 6:25:53 PM (10 years ago)
- Location:
- branches/MESI/modules/vci_mem_cache/caba
- Files:
-
- 3 edited
-
metadata/vci_mem_cache.sd (modified) (1 diff)
-
source/include/vci_mem_cache.h (modified) (8 diffs)
-
source/src/vci_mem_cache.cpp (modified) (562 diffs)
Legend:
- Unmodified
- Added
- Removed
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branches/MESI/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd
r670 r785 40 40 Uses('caba:generic_fifo'), 41 41 Uses('caba:generic_llsc_global_table'), 42 Uses('caba:dspin_ dhccp_param')42 Uses('caba:dspin_hmesi_param') 43 43 ], 44 44 -
branches/MESI/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r719 r785 38 38 #include <list> 39 39 #include <cassert> 40 40 41 #include "arithmetics.h" 41 42 #include "alloc_elems.h" … … 51 52 #include "update_tab.h" 52 53 #include "dspin_interface.h" 53 #include "dspin_ dhccp_param.h"54 #include "dspin_hmesi_param.h" 54 55 55 56 #define TRT_ENTRIES 4 // Number of entries in TRT … … 69 70 : public soclib::caba::BaseModule 70 71 { 71 typedef typename vci_param_int::fast_addr_t 72 typedef typename sc_dt::sc_uint<64> 73 typedef uint32_t 74 typedef uint32_t 75 typedef uint32_t 76 typedef uint32_t 72 typedef typename vci_param_int::fast_addr_t addr_t; 73 typedef typename sc_dt::sc_uint<64> wide_data_t; 74 typedef uint32_t data_t; 75 typedef uint32_t tag_t; 76 typedef uint32_t be_t; 77 typedef uint32_t copy_t; 77 78 78 79 /* States of the TGT_CMD fsm */ … … 392 393 // b1 accÚs table llsc type SW / other 393 394 // b2 WRITE/CAS/LL/SC 394 TYPE_DATA_UNC 395 TYPE_READ_DATA_MISS 396 TYPE_READ_INS_UNC 397 TYPE_READ_INS_MISS 398 TYPE_WRITE 399 TYPE_CAS 400 TYPE_LL 401 TYPE_SC 395 TYPE_DATA_UNC = 0x0, 396 TYPE_READ_DATA_MISS = 0x1, 397 TYPE_READ_INS_UNC = 0x2, 398 TYPE_READ_INS_MISS = 0x3, 399 TYPE_WRITE = 0x4, 400 TYPE_CAS = 0x5, 401 TYPE_LL = 0x6, 402 TYPE_SC = 0x7 402 403 }; 403 404 … … 405 406 enum sc_status_type_e 406 407 { 407 SC_SUCCESS =0x00000000,408 SC_FAIL =0x00000001408 SC_SUCCESS = 0x00000000, 409 SC_FAIL = 0x00000001 409 410 }; 410 411 411 412 // debug variables 412 bool 413 size_t 414 size_t 415 bool 416 data_t * 417 data_t * 413 bool m_debug; 414 size_t m_debug_previous_valid; 415 size_t m_debug_previous_count; 416 bool m_debug_previous_dirty; 417 data_t * m_debug_previous_data; 418 data_t * m_debug_data; 418 419 419 420 // instrumentation counters 420 uint32_t m_cpt_cycles; // Counter of cycles 421 422 // Counters accessible in software (not yet but eventually) 423 uint32_t m_cpt_reset_count; // Last cycle at which counters have been reset 424 uint32_t m_cpt_read_miss_local; // Number of local READ transactions 425 uint32_t m_cpt_read_miss_remote; // number of remote READ transactions 426 uint32_t m_cpt_read_miss_cost; // Number of (flits * distance) for READs 427 428 uint32_t m_cpt_getm_miss_local; // Number of local getm miss transactions 429 uint32_t m_cpt_getm_miss_remote; // number of remote getm miss transactions 430 431 uint32_t m_cpt_getm_hit_local; // Number of local getm hit transactions 432 uint32_t m_cpt_getm_hit_remote; // number of remote getm hit transactions 433 uint32_t m_cpt_getm_cost; // Number of (flits * distance) for getm 434 435 uint32_t m_cpt_write_local; // Number of local WRITE transactions 436 uint32_t m_cpt_write_remote; // number of remote WRITE transactions 437 uint32_t m_cpt_write_flits_local; // number of flits for local WRITEs 438 uint32_t m_cpt_write_flits_remote; // number of flits for remote WRITEs 439 uint32_t m_cpt_write_cost; // Number of (flits * distance) for WRITEs 440 441 uint32_t m_cpt_ll_local; // Number of local LL transactions 442 uint32_t m_cpt_ll_remote; // number of remote LL transactions 443 uint32_t m_cpt_ll_cost; // Number of (flits * distance) for LLs 444 445 uint32_t m_cpt_sc_local; // Number of local SC transactions 446 uint32_t m_cpt_sc_remote; // number of remote SC transactions 447 uint32_t m_cpt_sc_cost; // Number of (flits * distance) for SCs 448 449 uint32_t m_cpt_cas_local; // Number of local SC transactions 450 uint32_t m_cpt_cas_remote; // number of remote SC transactions 451 uint32_t m_cpt_cas_cost; // Number of (flits * distance) for SCs 452 453 uint32_t m_cpt_update; // Number of requests causing an UPDATE 454 uint32_t m_cpt_update_local; // Number of local UPDATE transactions 455 uint32_t m_cpt_update_remote; // Number of remote UPDATE transactions 456 uint32_t m_cpt_update_cost; // Number of (flits * distance) for UPDT 457 458 uint32_t m_cpt_minval; // Number of requests causing M_INV 459 uint32_t m_cpt_minval_local; // Number of local M_INV transactions 460 uint32_t m_cpt_minval_remote; // Number of remote M_INV transactions 461 uint32_t m_cpt_minval_cost; // Number of (flits * distance) for M_INV 462 463 uint32_t m_cpt_binval; // Number of BROADCAST INVAL 464 465 uint32_t m_cpt_cleanup_local; // Number of local CLEANUP transactions 466 uint32_t m_cpt_cleanup_remote; // Number of remote CLEANUP transactions 467 uint32_t m_cpt_cleanup_with_data; 468 uint32_t m_cpt_cleanup_cost; // Number of (flits * distance) for CLEANUPs 469 470 uint32_t m_cpt_multi_ack_miss; // Number of local CLEANUP transactions 471 uint32_t m_cpt_multi_ack_hit; // Number of local CLEANUP transactions 472 uint32_t m_cpt_multi_ack_hit_with_data; // Number of remote CLEANUP transactions 421 uint32_t m_cpt_cycles; // Counter of cycles 422 423 // Counters 424 // (*) = Counters accessible in software 425 uint32_t m_cpt_reset_count; // Last cycle at which counters have been reset 426 427 uint32_t m_cpt_read_local; // Number of local READ transactions (*) 428 uint32_t m_cpt_read_remote; // number of remote READ transactions (*) 429 uint32_t m_cpt_read_cost; // Number of (flits * distance) for READs (*) 430 431 uint32_t m_cpt_write_local; // Number of local WRITE transactions 432 uint32_t m_cpt_write_remote; // number of remote WRITE transactions 433 uint32_t m_cpt_write_flits_local; // number of flits for local WRITEs (*) 434 uint32_t m_cpt_write_flits_remote; // number of flits for remote WRITEs (*) 435 uint32_t m_cpt_write_cost; // Number of (flits * distance) for WRITEs (*) 436 437 uint32_t m_cpt_ll_local; // Number of local LL transactions (*) 438 uint32_t m_cpt_ll_remote; // number of remote LL transactions (*) 439 uint32_t m_cpt_ll_cost; // Number of (flits * distance) for LLs (*) 440 441 uint32_t m_cpt_sc_local; // Number of local SC transactions (*) 442 uint32_t m_cpt_sc_remote; // number of remote SC transactions (*) 443 uint32_t m_cpt_sc_cost; // Number of (flits * distance) for SCs (*) 444 445 uint32_t m_cpt_cas_local; // Number of local SC transactions (*) 446 uint32_t m_cpt_cas_remote; // number of remote SC transactions (*) 447 uint32_t m_cpt_cas_cost; // Number of (flits * distance) for SCs (*) 448 449 uint32_t m_cpt_minval; // Number of requests causing M_INV (*) 450 uint32_t m_cpt_minval_local; // Number of local M_INV transactions (*) 451 uint32_t m_cpt_minval_remote; // Number of remote M_INV transactions (*) 452 uint32_t m_cpt_minval_cost; // Number of (flits * distance) for M_INV (*) 453 454 uint32_t m_cpt_binval; // Number of BROADCAST INVAL (*) 455 uint32_t m_cpt_write_broadcast;// Number of BROADCAST INVAL caused by write 456 uint32_t m_cpt_getm_broadcast; // Number of BROADCAST INVAL caused by getm 457 458 uint32_t m_cpt_cleanup_local; // Number of local CLEANUP transactions (*) 459 uint32_t m_cpt_cleanup_remote; // Number of remote CLEANUP transactions (*) 460 uint32_t m_cpt_cleanup_cost; // Number of (flits * distance) for CLEANUPs (*) 461 uint32_t m_cpt_cleanup_data_local; // 462 uint32_t m_cpt_cleanup_data_remote; // 463 uint32_t m_cpt_cleanup_data_cost; // 464 465 uint32_t m_cpt_read_miss; // Number of MISS READ 466 uint32_t m_cpt_write_miss; // Number of MISS WRITE 467 uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions 468 uint32_t m_cpt_getm_miss; // Number of getm miss 469 470 uint32_t m_cpt_getm_local; // Number of local getm miss transactions 471 uint32_t m_cpt_getm_remote; // number of remote getm miss transactions 472 uint32_t m_cpt_getm_cost; // Number of (flits * distance) for getm 473 474 uint32_t m_cpt_inval_ro_local; // Number of local INVAL RO (*) 475 uint32_t m_cpt_inval_ro_remote; // Number of local INVAL RO (*) 476 uint32_t m_cpt_inval_ro_cost; // Cost for INVAL RO (*) 473 477 474 // Counters not accessible by software 475 uint32_t m_cpt_read_miss; // Number of MISS READ 476 uint32_t m_cpt_getm_miss; // Number of getm miss 477 uint32_t m_cpt_getm_broadcast; // Number of BROADCAST INVAL because getm 478 uint32_t m_cpt_getm_minval; // Number of MULTI INVAL because getm 479 uint32_t m_cpt_write_miss; // Number of MISS WRITE 480 uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions 481 uint32_t m_cpt_write_broadcast;// Number of BROADCAST INVAL because write 482 uint32_t m_cpt_write_minval; // Number of MULTI INVAL because write 483 uint32_t m_cpt_cas_broadcast; // Number of BROADCAST INVAL because cas 484 uint32_t m_cpt_cas_minval; // Number of MULTI INVAL because cas 485 uint32_t m_cpt_cas_miss; 486 487 uint32_t m_cpt_read_locked_rb; // Read blocked by a locked ligne 488 uint32_t m_cpt_cas_locked_rb; // cas blocked by a locked ligne 489 uint32_t m_cpt_write_locked_rb; // wt blocked by a locked ligne 490 491 uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt 492 uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt 493 uint32_t m_cpt_put; 494 uint32_t m_cpt_get; 495 496 uint32_t m_cpt_read_fsm_dir_lock; // wait DIR LOCK 497 uint32_t m_cpt_read_fsm_n_dir_lock; // NB DIR LOCK 498 uint32_t m_cpt_write_fsm_dir_lock; // wait DIR LOCK 499 uint32_t m_cpt_write_fsm_n_dir_lock; // NB DIR LOCK 500 uint32_t m_cpt_xram_rsp_fsm_dir_lock; // wait DIR LOCK 501 uint32_t m_cpt_xram_rsp_fsm_n_dir_lock; // NB DIR LOCK 502 uint32_t m_cpt_cas_fsm_dir_lock; // wait DIR LOCK 503 uint32_t m_cpt_cas_fsm_n_dir_lock; // NB DIR LOCK 504 uint32_t m_cpt_cleanup_fsm_dir_lock; // wait DIR LOCK 505 uint32_t m_cpt_cleanup_fsm_n_dir_lock; // NB DIR LOCK 506 uint32_t m_cpt_multi_ack_fsm_dir_lock; // wait DIR LOCK 507 uint32_t m_cpt_multi_ack_fsm_n_dir_lock; // NB DIR LOCK 508 509 uint32_t m_cpt_dir_unused; // NB cycles DIR LOCK unused 510 uint32_t m_cpt_read_fsm_dir_used; // NB cycles DIR LOCK used 511 uint32_t m_cpt_write_fsm_dir_used; // NB cycles DIR LOCK used 512 uint32_t m_cpt_cas_fsm_dir_used; // NB cycles DIR LOCK used 513 uint32_t m_cpt_xram_rsp_fsm_dir_used; // NB cycles DIR LOCK used 514 uint32_t m_cpt_cleanup_fsm_dir_used; // NB cycles DIR LOCK used 515 uint32_t m_cpt_multi_ack_fsm_dir_used; // NB cycles DIR LOCK used 516 517 uint32_t m_cpt_read_fsm_trt_lock; // wait TRT LOCK 518 uint32_t m_cpt_write_fsm_trt_lock; // wait TRT LOCK 519 uint32_t m_cpt_cas_fsm_trt_lock; // wait TRT LOCK 520 uint32_t m_cpt_xram_rsp_fsm_trt_lock; // wait TRT LOCK 521 uint32_t m_cpt_ixr_fsm_trt_lock; // wait TRT LOCK 522 523 uint32_t m_cpt_read_fsm_n_trt_lock; // NB TRT LOCK 524 uint32_t m_cpt_write_fsm_n_trt_lock; // NB TRT LOCK 525 uint32_t m_cpt_cas_fsm_n_trt_lock; // NB TRT LOCK 526 uint32_t m_cpt_xram_rsp_fsm_n_trt_lock; // NB TRT LOCK 527 uint32_t m_cpt_ixr_cmd_fsm_n_trt_lock; // NB TRT LOCK 528 uint32_t m_cpt_ixr_rsp_fsm_n_trt_lock; // NB TRT LOCK 529 530 uint32_t m_cpt_read_fsm_trt_used; // NB cycles TRT LOCK used 531 uint32_t m_cpt_write_fsm_trt_used; // NB cycles TRT LOCK used 532 uint32_t m_cpt_cas_fsm_trt_used; // NB cycles TRT LOCK used 533 uint32_t m_cpt_xram_rsp_fsm_trt_used; // NB cycles TRT LOCK used 534 uint32_t m_cpt_ixr_cmd_fsm_trt_used; // NB cycles TRT LOCK used 535 uint32_t m_cpt_ixr_rsp_fsm_trt_used; // NB cycles TRT LOCK used 536 uint32_t m_cpt_cleanup_fsm_trt_used; // NB cycles TRT LOCK used 537 538 uint32_t m_cpt_trt_unused; // NB cycles TRT LOCK unused 539 540 uint32_t m_cpt_cleanup_fsm_ivt_lock; // wait ivt LOCK 541 uint32_t m_cpt_cleanup_fsm_n_ivt_lock; // NB cycles UPT LOCK used 542 543 uint32_t m_cpt_multi_ack_fsm_ivt_lock; // wait ivt LOCK 544 uint32_t m_cpt_multi_ack_fsm_n_ivt_lock; // NB cycles UPT LOCK used 545 546 uint32_t m_cpt_ivt_unused; // NB cycles UPT LOCK unused 547 548 uint32_t m_cpt_read_fsm_heap_lock; // wait HEAP LOCK 549 uint32_t m_cpt_write_fsm_heap_lock; // wait HEAP LOCK 550 uint32_t m_cpt_cas_fsm_heap_lock; // wait HEAP LOCK 551 uint32_t m_cpt_cleanup_fsm_heap_lock; // wait HEAP LOCK 552 uint32_t m_cpt_xram_rsp_fsm_heap_lock; // wait HEAP LOCK 553 uint32_t m_cpt_multi_ack_fsm_heap_lock; // wait HEAP LOCK 554 555 uint32_t m_cpt_read_fsm_n_heap_lock; // NB HEAP LOCK 556 uint32_t m_cpt_write_fsm_n_heap_lock; // NB HEAP LOCK 557 uint32_t m_cpt_cas_fsm_n_heap_lock; // NB HEAP LOCK 558 uint32_t m_cpt_cleanup_fsm_n_heap_lock; // NB HEAP LOCK 559 uint32_t m_cpt_xram_rsp_fsm_n_heap_lock; // NB HEAP LOCK 560 uint32_t m_cpt_multi_ack_fsm_n_heap_lock; // NB HEAP LOCK 561 562 uint32_t m_cpt_read_fsm_heap_used; // NB cycles HEAP LOCK used 563 uint32_t m_cpt_write_fsm_heap_used; // NB cycles HEAP LOCK used 564 uint32_t m_cpt_cas_fsm_heap_used; // NB cycles HEAP LOCK used 565 uint32_t m_cpt_cleanup_fsm_heap_used; // NB cycles HEAP LOCK used 566 uint32_t m_cpt_xram_rsp_fsm_heap_used; // NB cycles HEAP LOCK used 567 uint32_t m_cpt_multi_ack_fsm_heap_used; // NB cycles HEAP LOCK used 568 569 uint32_t m_cpt_heap_unused; // NB cycles HEAP LOCK unused 570 uint32_t m_cpt_slot_inval; 478 uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt 479 uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt 480 uint32_t m_cpt_put; 481 uint32_t m_cpt_get; 482 483 uint32_t m_cpt_heap_unused; // NB cycles HEAP LOCK unused 484 uint32_t m_cpt_slot_inval; 571 485 572 486 protected: … … 602 516 sc_out<int> p_cc_send_fsm; 603 517 sc_out<int> p_cc_receive_fsm; 604 sc_out<int> p_multi_ack_fsm; 518 sc_out<int> p_multi_ack_fsm; 605 519 #endif 606 520 … … 611 525 const soclib::common::IntTab &srcid_x, // global index RAM network 612 526 const soclib::common::IntTab &tgtid_d, // global index INT network 613 const size_t cc_global_id, // global index CC network614 527 const size_t x_width, // X width in platform 615 528 const size_t y_width, // Y width in platform … … 654 567 const size_t m_sets; // Number of cache sets 655 568 const size_t m_words; // Number of words in a line 656 const size_t m_cc_global_id; // global_index on cc network 657 const size_t m_xwidth; // number of x bits in platform 658 const size_t m_ywidth; // number of y bits in platform 569 size_t m_x_self; // X self coordinate 570 size_t m_y_self; // Y self coordinate 571 const size_t m_x_width; // number of x bits in platform 572 const size_t m_y_width; // number of y bits in platform 659 573 size_t m_debug_start_cycle; 660 574 bool m_debug_ok; -
branches/MESI/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r719 r785 351 351 const IntTab &srcid_x, // global index on external network 352 352 const IntTab &tgtid_d, // global index on direct network 353 const size_t cc_global_id, // global index on cc network354 353 const size_t x_width, // number of x bits in platform 355 354 const size_t y_width, // number of x bits in platform … … 384 383 m_sets( nsets ), 385 384 m_words( nwords ), 386 m_cc_global_id( cc_global_id ), 387 m_xwidth(x_width), 388 m_ywidth(y_width), 385 m_x_width(x_width), 386 m_y_width(y_width), 389 387 m_debug_start_cycle( debug_start_cycle ), 390 388 m_debug_ok( debug_ok ), … … 550 548 for(seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++) 551 549 { 552 if ( 550 if (seg->special() ) m_seg_config = i; 553 551 m_seg[i] = & (*seg); 554 552 i++; 555 553 } 554 555 addr_t gid = m_seg[0]->baseAddress() >> (vci_param_int::N - x_width - y_width); 556 m_x_self = (gid >> m_y_width) & ((1 << m_x_width) - 1); 557 m_y_self = gid & ((1 << m_y_width) - 1); 556 558 557 559 // Allocation for IXR_RSP FSM … … 614 616 bool data_change = false; 615 617 616 if ( 618 if (entry.state != ENTRY_INVALID ) 617 619 { 618 620 for ( size_t word = 0 ; word<m_words ; word++ ) 619 621 { 620 622 m_debug_data[word] = m_cache_data.read(way, set, word); 621 if ( 623 if ((m_debug_previous_valid != ENTRY_INVALID) and 622 624 (m_debug_data[word] != m_debug_previous_data[word]) ) 623 625 { … … 628 630 629 631 // print values if any change 630 if ( 632 if ((entry.state != m_debug_previous_valid) or 631 633 ((entry.state != ENTRY_INVALID) and (entry.count != m_debug_previous_count)) or 632 634 ((entry.state != ENTRY_INVALID) and (entry.dirty != m_debug_previous_dirty)) or data_change ) … … 672 674 { 673 675 const uint32_t srcid_width = vci_param_int::S; 674 uint8_t self_x_srcid = m_cc_global_id >> (srcid_width - m_xwidth); 675 uint8_t self_y_srcid = (m_cc_global_id >> (srcid_width - m_ywidth)) & ((1 << m_xwidth) - 1); 676 677 uint8_t x_srcid = req_srcid >> (srcid_width - m_xwidth); 678 uint8_t y_srcid = (req_srcid >> (srcid_width - m_ywidth - m_xwidth)) & ((1 << m_xwidth) - 1); 679 return abs(self_x_srcid - x_srcid) + abs(self_y_srcid - y_srcid); 676 677 uint8_t req_x = (req_srcid >> (srcid_width - m_x_width)); 678 uint8_t req_y = (req_srcid >> (srcid_width - m_x_width - m_y_width)) & ((1 << m_y_width) - 1); 679 680 return abs(m_x_self - req_x) + abs(m_y_self - req_y); 680 681 } 681 682 … … 706 707 // LOCAL 707 708 708 case MEMC_LOCAL_READ_LO : rdata = m_cpt_read_ miss_local ; break;709 case MEMC_LOCAL_READ_LO : rdata = m_cpt_read_local ; break; 709 710 case MEMC_LOCAL_WRITE_LO : rdata = m_cpt_write_flits_local ; break; 710 711 case MEMC_LOCAL_LL_LO : rdata = m_cpt_ll_local ; break; … … 719 720 // REMOTE 720 721 721 case MEMC_REMOTE_READ_LO : rdata = m_cpt_read_ miss_remote ; break;722 case MEMC_REMOTE_READ_LO : rdata = m_cpt_read_remote ; break; 722 723 case MEMC_REMOTE_WRITE_LO : rdata = m_cpt_write_flits_remote ; break; 723 724 case MEMC_REMOTE_LL_LO : rdata = m_cpt_ll_remote ; break; … … 732 733 // COST 733 734 734 case MEMC_COST_READ_LO : rdata = m_cpt_read_ miss_cost ; break;735 case MEMC_COST_READ_LO : rdata = m_cpt_read_cost ; break; 735 736 case MEMC_COST_WRITE_LO : rdata = m_cpt_write_cost; break; 736 737 case MEMC_COST_LL_LO : rdata = m_cpt_ll_cost ; break; … … 753 754 // LOCAL 754 755 755 case MEMC_LOCAL_MUPDATE_LO : rdata = m_cpt_ update_local; break;756 case MEMC_LOCAL_MINVAL_LO : rdata = m_cpt_minval_local ; break;757 case MEMC_LOCAL_CLEANUP_LO : rdata = m_cpt_cleanup_local; break;756 case MEMC_LOCAL_MUPDATE_LO : rdata = m_cpt_inval_ro_local; break; 757 case MEMC_LOCAL_MINVAL_LO : rdata = m_cpt_minval_local ; break; 758 case MEMC_LOCAL_CLEANUP_LO : rdata = m_cpt_cleanup_local; break; 758 759 case MEMC_LOCAL_MUPDATE_HI : 759 760 case MEMC_LOCAL_MINVAL_HI : … … 762 763 // REMOTE 763 764 764 case MEMC_REMOTE_MUPDATE_LO : rdata = m_cpt_ update_remote; break;765 case MEMC_REMOTE_MINVAL_LO : rdata = m_cpt_minval_remote ; break;766 case MEMC_REMOTE_CLEANUP_LO : rdata = m_cpt_cleanup_remote; break;765 case MEMC_REMOTE_MUPDATE_LO : rdata = m_cpt_inval_ro_remote; break; 766 case MEMC_REMOTE_MINVAL_LO : rdata = m_cpt_minval_remote ; break; 767 case MEMC_REMOTE_CLEANUP_LO : rdata = m_cpt_cleanup_remote; break; 767 768 case MEMC_REMOTE_MUPDATE_HI : 768 769 case MEMC_REMOTE_MINVAL_HI : … … 771 772 // COST 772 773 773 case MEMC_COST_MUPDATE_LO : rdata = m_cpt_ update_cost; break;774 case MEMC_COST_MINVAL_LO : rdata = m_cpt_minval_cost ;break;775 case MEMC_COST_CLEANUP_LO : rdata = m_cpt_cleanup_cost ;break;774 case MEMC_COST_MUPDATE_LO : rdata = m_cpt_inval_ro_cost; break; 775 case MEMC_COST_MINVAL_LO : rdata = m_cpt_minval_cost; break; 776 case MEMC_COST_CLEANUP_LO : rdata = m_cpt_cleanup_cost; break; 776 777 case MEMC_COST_MUPDATE_HI : 777 778 case MEMC_COST_MINVAL_HI : … … 779 780 780 781 // TOTAL 781 782 case MEMC_TOTAL_MUPDATE_LO : rdata = m_cpt_ update; break;783 case MEMC_TOTAL_MINVAL_LO : rdata = m_cpt_minval ; break;784 case MEMC_TOTAL_BINVAL_LO : rdata = m_cpt_binval ; break;782 // inval_ro are equal to the number of requests triggering them 783 case MEMC_TOTAL_MUPDATE_LO : rdata = m_cpt_inval_ro_local + m_cpt_inval_ro_remote; break; 784 case MEMC_TOTAL_MINVAL_LO : rdata = m_cpt_minval ; break; 785 case MEMC_TOTAL_BINVAL_LO : rdata = m_cpt_binval ; break; 785 786 case MEMC_TOTAL_MUPDATE_HI : 786 787 case MEMC_TOTAL_MINVAL_HI : … … 788 789 789 790 // unknown register 790 791 791 default : error = 1; 792 792 } … … 819 819 << " | " << alloc_heap_fsm_str[r_alloc_heap_fsm.read()] << std::endl; 820 820 821 if ( 821 if (detailed ) m_trt.print(0); 822 822 } 823 823 … … 827 827 ///////////////////////////////////////// 828 828 { 829 m_cpt_reset_count = m_cpt_cycles; 830 831 m_cpt_read_miss_local = 0 ; 832 m_cpt_read_miss_remote = 0 ; 833 m_cpt_read_miss_cost = 0 ; 834 835 m_cpt_getm_miss_local = 0 ; 836 m_cpt_getm_miss_remote = 0 ; 837 838 m_cpt_getm_hit_local = 0 ; 839 m_cpt_getm_hit_remote = 0 ; 840 m_cpt_getm_cost = 0 ; 841 842 m_cpt_write_local = 0 ; 843 m_cpt_write_remote = 0 ; 844 m_cpt_write_flits_local = 0 ; 845 m_cpt_write_flits_remote = 0 ; 846 m_cpt_write_cost = 0 ; 847 848 m_cpt_ll_local = 0 ; 849 m_cpt_ll_remote = 0 ; 850 m_cpt_ll_cost = 0 ; 851 852 m_cpt_sc_local = 0 ; 853 m_cpt_sc_remote = 0 ; 854 m_cpt_sc_cost = 0 ; 855 856 m_cpt_cas_local = 0 ; 857 m_cpt_cas_remote = 0 ; 858 m_cpt_cas_cost = 0 ; 859 860 m_cpt_update = 0 ; 861 m_cpt_update_local = 0 ; 862 m_cpt_update_remote = 0 ; 863 m_cpt_update_cost = 0 ; 864 865 m_cpt_minval = 0 ; 866 m_cpt_minval_local = 0 ; 867 m_cpt_minval_remote = 0 ; 868 m_cpt_minval_cost = 0 ; 869 870 m_cpt_binval = 0 ; 871 872 m_cpt_cleanup_local = 0 ; 873 m_cpt_cleanup_remote = 0 ; 874 m_cpt_cleanup_with_data = 0 ; 875 m_cpt_cleanup_cost = 0 ; 876 877 m_cpt_multi_ack_miss = 0 ; 878 m_cpt_multi_ack_hit = 0 ; 879 m_cpt_multi_ack_hit_with_data = 0 ; 880 881 882 m_cpt_read_miss = 0 ; 883 m_cpt_getm_miss = 0 ; 884 m_cpt_getm_broadcast = 0 ; 885 m_cpt_getm_minval = 0 ; 886 m_cpt_write_miss = 0 ; 887 m_cpt_write_dirty = 0 ; 888 m_cpt_write_broadcast = 0 ; 889 m_cpt_write_minval = 0 ; 890 m_cpt_cas_broadcast = 0 ; 891 m_cpt_cas_minval = 0 ; 892 m_cpt_cas_miss = 0 ; 893 894 m_cpt_read_locked_rb = 0 ; 895 m_cpt_cas_locked_rb = 0 ; 896 m_cpt_write_locked_rb = 0 ; 897 898 m_cpt_trt_rb = 0 ; 899 m_cpt_trt_full = 0 ; 900 m_cpt_put = 0 ; 901 m_cpt_get = 0 ; 902 m_cpt_read_fsm_dir_lock = 0 ; 903 m_cpt_read_fsm_n_dir_lock = 0 ; 904 m_cpt_write_fsm_dir_lock = 0 ; 905 m_cpt_write_fsm_n_dir_lock = 0 ; 906 m_cpt_xram_rsp_fsm_dir_lock = 0 ; 907 m_cpt_xram_rsp_fsm_n_dir_lock = 0 ; 908 m_cpt_cas_fsm_dir_lock = 0 ; 909 m_cpt_cas_fsm_n_dir_lock = 0 ; 910 m_cpt_cleanup_fsm_dir_lock = 0 ; 911 m_cpt_cleanup_fsm_n_dir_lock = 0 ; 912 m_cpt_multi_ack_fsm_dir_lock = 0 ; 913 m_cpt_multi_ack_fsm_n_dir_lock = 0 ; 914 915 m_cpt_dir_unused = 0 ; 916 m_cpt_read_fsm_dir_used = 0 ; 917 m_cpt_write_fsm_dir_used = 0 ; 918 m_cpt_cas_fsm_dir_used = 0 ; 919 m_cpt_xram_rsp_fsm_dir_used = 0 ; 920 m_cpt_cleanup_fsm_dir_used = 0 ; 921 m_cpt_multi_ack_fsm_dir_used = 0 ; 922 923 m_cpt_read_fsm_trt_lock = 0 ; 924 m_cpt_write_fsm_trt_lock = 0 ; 925 m_cpt_cas_fsm_trt_lock = 0 ; 926 m_cpt_xram_rsp_fsm_trt_lock = 0 ; 927 m_cpt_ixr_fsm_trt_lock = 0 ; 928 929 m_cpt_read_fsm_n_trt_lock = 0 ; 930 m_cpt_write_fsm_n_trt_lock = 0 ; 931 m_cpt_cas_fsm_n_trt_lock = 0 ; 932 m_cpt_xram_rsp_fsm_n_trt_lock = 0 ; 933 m_cpt_ixr_cmd_fsm_n_trt_lock = 0 ; 934 m_cpt_ixr_rsp_fsm_n_trt_lock = 0 ; 935 936 m_cpt_read_fsm_trt_used = 0 ; 937 m_cpt_write_fsm_trt_used = 0 ; 938 m_cpt_cas_fsm_trt_used = 0 ; 939 m_cpt_xram_rsp_fsm_trt_used = 0 ; 940 m_cpt_ixr_cmd_fsm_trt_used = 0 ; 941 m_cpt_ixr_rsp_fsm_trt_used = 0 ; 942 m_cpt_cleanup_fsm_trt_used = 0 ; 943 944 m_cpt_trt_unused = 0 ; 945 946 m_cpt_cleanup_fsm_ivt_lock = 0 ; 947 m_cpt_cleanup_fsm_n_ivt_lock = 0 ; 948 949 m_cpt_multi_ack_fsm_ivt_lock = 0 ; 950 m_cpt_multi_ack_fsm_n_ivt_lock = 0 ; 951 952 m_cpt_ivt_unused = 0 ; 953 954 m_cpt_read_fsm_heap_lock = 0 ; 955 m_cpt_write_fsm_heap_lock = 0 ; 956 m_cpt_cas_fsm_heap_lock = 0 ; 957 m_cpt_cleanup_fsm_heap_lock = 0 ; 958 m_cpt_xram_rsp_fsm_heap_lock = 0 ; 959 m_cpt_multi_ack_fsm_heap_lock = 0 ; 960 961 m_cpt_read_fsm_n_heap_lock = 0 ; 962 m_cpt_write_fsm_n_heap_lock = 0 ; 963 m_cpt_cas_fsm_n_heap_lock = 0 ; 964 m_cpt_cleanup_fsm_n_heap_lock = 0 ; 965 m_cpt_xram_rsp_fsm_n_heap_lock = 0 ; 966 m_cpt_multi_ack_fsm_n_heap_lock = 0 ; 967 968 m_cpt_read_fsm_heap_used = 0 ; 969 m_cpt_write_fsm_heap_used = 0 ; 970 m_cpt_cas_fsm_heap_used = 0 ; 971 m_cpt_cleanup_fsm_heap_used = 0 ; 972 m_cpt_xram_rsp_fsm_heap_used = 0 ; 973 m_cpt_multi_ack_fsm_heap_used = 0 ; 974 975 m_cpt_heap_unused = 0 ; 976 m_cpt_slot_inval = 0 ; 977 829 m_cpt_reset_count = m_cpt_cycles; 830 831 m_cpt_read_local = 0; 832 m_cpt_read_remote = 0; 833 m_cpt_read_cost = 0; 834 835 m_cpt_write_local = 0; 836 m_cpt_write_remote = 0; 837 m_cpt_write_flits_local = 0; 838 m_cpt_write_flits_remote = 0; 839 m_cpt_write_cost = 0; 840 841 m_cpt_ll_local = 0; 842 m_cpt_ll_remote = 0; 843 m_cpt_ll_cost = 0; 844 845 m_cpt_sc_local = 0; 846 m_cpt_sc_remote = 0; 847 m_cpt_sc_cost = 0; 848 849 m_cpt_cas_local = 0; 850 m_cpt_cas_remote = 0; 851 m_cpt_cas_cost = 0; 852 853 m_cpt_minval = 0; 854 m_cpt_minval_local = 0; 855 m_cpt_minval_remote = 0; 856 m_cpt_minval_cost = 0; 857 858 m_cpt_binval = 0; 859 m_cpt_write_broadcast = 0; 860 m_cpt_getm_broadcast = 0; 861 862 m_cpt_cleanup_local = 0; 863 m_cpt_cleanup_remote = 0; 864 m_cpt_cleanup_cost = 0; 865 m_cpt_cleanup_data_local = 0; 866 m_cpt_cleanup_data_remote = 0; 867 m_cpt_cleanup_data_cost = 0; 868 869 m_cpt_read_miss = 0; 870 m_cpt_write_miss = 0; 871 m_cpt_write_dirty = 0; 872 m_cpt_getm_miss = 0; 873 874 m_cpt_getm_local = 0; 875 m_cpt_getm_remote = 0; 876 m_cpt_getm_cost = 0; 877 878 m_cpt_inval_ro_local = 0; 879 m_cpt_inval_ro_remote = 0; 880 m_cpt_inval_ro_cost = 0; 881 882 m_cpt_trt_rb = 0; 883 m_cpt_trt_full = 0; 884 m_cpt_put = 0; 885 m_cpt_get = 0; 886 887 m_cpt_heap_unused = 0; 888 m_cpt_slot_inval = 0; 978 889 } 979 890 980 891 981 892 ///////////////////////////////////////// 982 tmpl(void)::print_stats(bool activity_counters = true, bool stats = true)893 tmpl(void)::print_stats(bool activity_counters) 983 894 { 984 895 std::cout << "**********************************" << std::dec << std::endl; … … 993 904 << "[001] NUMBER OF CYCLES = " << m_cpt_cycles << std::endl 994 905 << std::endl 995 << "[0 02] LOCAL READ = " << m_cpt_read_miss_local << std::endl996 << "[0 03] REMOTE READ = " << m_cpt_read_miss_remote << std::endl997 << "[0 04] READ COST (FLITS * DIST) = " << m_cpt_read_miss_cost << std::endl906 << "[010] LOCAL READ = " << m_cpt_read_local << std::endl 907 << "[011] REMOTE READ = " << m_cpt_read_remote << std::endl 908 << "[012] READ COST (FLITS * DIST) = " << m_cpt_read_cost << std::endl 998 909 << std::endl 999 << "[005] LOCAL WRITE = " << m_cpt_write_local << std::endl 1000 << "[006] REMOTE WRITE = " << m_cpt_write_remote << std::endl 1001 << "[007] WRITE FLITS LOCAL = " << m_cpt_write_flits_local << std::endl 1002 << "[008] WRITE FLITS REMOTE = " << m_cpt_write_flits_remote << std::endl 1003 << "[009] WRITE COST (FLITS * DIST) = " << m_cpt_write_cost << std::endl 910 << "[020] LOCAL WRITE = " << m_cpt_write_local << std::endl 911 << "[021] REMOTE WRITE = " << m_cpt_write_remote << std::endl 912 << "[022] WRITE FLITS LOCAL = " << m_cpt_write_flits_local << std::endl 913 << "[023] WRITE FLITS REMOTE = " << m_cpt_write_flits_remote << std::endl 914 << "[024] WRITE COST (FLITS * DIST) = " << m_cpt_write_cost << std::endl 915 << "[025] WRITE L1 MISS NCC = " << "0" << std::endl 1004 916 << std::endl 1005 << "[0 10] LOCAL LL = " << m_cpt_ll_local << std::endl1006 << "[0 11] REMOTE LL = " << m_cpt_ll_remote << std::endl1007 << "[0 12] LL COST (FLITS * DIST) = " << m_cpt_ll_cost << std::endl917 << "[030] LOCAL LL = " << m_cpt_ll_local << std::endl 918 << "[031] REMOTE LL = " << m_cpt_ll_remote << std::endl 919 << "[032] LL COST (FLITS * DIST) = " << m_cpt_ll_cost << std::endl 1008 920 << std::endl 1009 << "[0 13] LOCAL SC = " << m_cpt_sc_local << std::endl1010 << "[0 14] REMOTE SC = " << m_cpt_sc_remote << std::endl1011 << "[0 15] SC COST (FLITS * DIST) = " << m_cpt_sc_cost << std::endl921 << "[040] LOCAL SC = " << m_cpt_sc_local << std::endl 922 << "[041] REMOTE SC = " << m_cpt_sc_remote << std::endl 923 << "[042] SC COST (FLITS * DIST) = " << m_cpt_sc_cost << std::endl 1012 924 << std::endl 1013 << "[0 16] LOCAL CAS = " << m_cpt_cas_local << std::endl1014 << "[0 17] REMOTE CAS = " << m_cpt_cas_remote << std::endl1015 << "[0 18] CAS COST (FLITS * DIST) = " << m_cpt_cas_cost << std::endl925 << "[050] LOCAL CAS = " << m_cpt_cas_local << std::endl 926 << "[051] REMOTE CAS = " << m_cpt_cas_remote << std::endl 927 << "[052] CAS COST (FLITS * DIST) = " << m_cpt_cas_cost << std::endl 1016 928 << std::endl 1017 << "[0 19] REQUESTS TRIG. UPDATE = " << m_cpt_update<< std::endl1018 << "[0 20] LOCAL UPDATE = " << m_cpt_update_local<< std::endl1019 << "[0 21] REMOTE UPDATE = " << m_cpt_update_remote<< std::endl1020 << "[0 22] UPDT COST (FLITS * DIST) = " << m_cpt_update_cost<< std::endl929 << "[060] REQUESTS TRIG. UPDATE = " << "0" << std::endl 930 << "[061] LOCAL UPDATE = " << "0" << std::endl 931 << "[062] REMOTE UPDATE = " << "0" << std::endl 932 << "[063] UPDT COST (FLITS * DIST) = " << "0" << std::endl 1021 933 << std::endl 1022 << "[0 23] REQUESTS TRIG. M_INV = " << m_cpt_minval << std::endl1023 << "[0 24] LOCAL M_INV = " << m_cpt_minval_local << std::endl1024 << "[0 25] REMOTE M_INV = " << m_cpt_minval_remote << std::endl1025 << "[0 26] M_INV COST (FLITS * DIST) = " << m_cpt_minval_cost << std::endl934 << "[070] REQUESTS TRIG. M_INV = " << m_cpt_minval << std::endl 935 << "[071] LOCAL M_INV = " << m_cpt_minval_local << std::endl 936 << "[072] REMOTE M_INV = " << m_cpt_minval_remote << std::endl 937 << "[073] M_INV COST (FLITS * DIST) = " << m_cpt_minval_cost << std::endl 1026 938 << std::endl 1027 << "[027] BROADCAT INVAL = " << m_cpt_binval << std::endl 939 << "[080] BROADCAT INVAL = " << m_cpt_binval << std::endl 940 << "[081] WRITE BROADCAST = " << m_cpt_write_broadcast << std::endl 941 << "[082] GETM BROADCAST = " << m_cpt_getm_broadcast << std::endl 1028 942 << std::endl 1029 << "[028] LOCAL CLEANUP = " << m_cpt_cleanup_local << std::endl 1030 << "[029] REMOTE CLEANUP = " << m_cpt_cleanup_remote << std::endl 1031 << "[030] CLNUP COST (FLITS * DIST) = " << m_cpt_cleanup_cost << std::endl 943 << "[090] LOCAL CLEANUP = " << m_cpt_cleanup_local << std::endl 944 << "[091] REMOTE CLEANUP = " << m_cpt_cleanup_remote << std::endl 945 << "[092] CLNUP COST (FLITS * DIST) = " << m_cpt_cleanup_cost << std::endl 946 << "[093] LOCAL CLEANUP DATA = " << m_cpt_cleanup_data_local << std::endl 947 << "[094] REMOTE CLEANUP DATA = " << m_cpt_cleanup_data_remote << std::endl 948 << "[095] CLEANUP DATA COST = " << m_cpt_cleanup_data_cost << std::endl 1032 949 << std::endl 950 << "[100] READ MISS = " << m_cpt_read_miss << std::endl 951 << "[101] WRITE MISS = " << m_cpt_write_miss << std::endl 952 << "[102] WRITE DIRTY = " << m_cpt_write_dirty << std::endl 953 << "[103] GETM MISS = " << m_cpt_getm_miss << std::endl 1033 954 << std::endl 1034 << "[031] READ MISS = " << m_cpt_read_miss << std::endl 1035 << "[032] WRITE MISS = " << m_cpt_write_miss << std::endl 1036 << "[033] WRITE DIRTY = " << m_cpt_write_dirty << std::endl 1037 << "[034] RD BLOCKED BY HIT IN TRT = " << m_cpt_trt_rb << std::endl 1038 << "[035] TRANS BLOCKED BY FULL TRT = " << m_cpt_trt_full << std::endl 1039 << "[036] PUT (UNIMPLEMENTED) = " << m_cpt_put << std::endl 1040 << "[037] GET (UNIMPLEMENTED) = " << m_cpt_get << std::endl 1041 << "[038] WRITE BROADCAST = " << m_cpt_write_broadcast << std::endl 955 << "[110] RD BLOCKED BY HIT IN TRT = " << m_cpt_trt_rb << std::endl 956 << "[111] TRANS BLOCKED BY FULL TRT = " << m_cpt_trt_full << std::endl 957 << "[120] PUT (UNIMPLEMENTED) = " << m_cpt_put << std::endl 958 << "[121] GET (UNIMPLEMENTED) = " << m_cpt_get << std::endl 959 << "[130] MIN HEAP SLOT AVAILABLE = " << "-1" << std::endl 1042 960 << std::endl 1043 961 << "[140] NCC TO CC (READ) = " << "0" << std::endl 962 << "[141] NCC TO CC (WRITE) = " << "0" << std::endl 963 << std::endl 964 << "[150] LOCAL GETM = " << m_cpt_getm_local << std::endl 965 << "[151] REMOTE GETM = " << m_cpt_getm_remote << std::endl 966 << "[152] GETM COST (FLITS * DIST) = " << m_cpt_getm_cost << std::endl 967 << std::endl 968 << "[160] LOCAL INVAL RO = " << m_cpt_inval_ro_local << std::endl 969 << "[161] REMOTE INVAL RO = " << m_cpt_inval_ro_remote << std::endl 970 << "[162] INVAL RO COST = " << m_cpt_inval_ro_cost << std::endl 971 << std::endl; 972 973 #if 0 1044 974 << "[050] LOCAL GETM MISS = " << m_cpt_getm_miss_local << std::endl 1045 975 << "[051] REMOTE GETM MISS = " << m_cpt_getm_miss_remote << std::endl … … 1047 977 << "[053] REMOTE GETM HIT = " << m_cpt_getm_hit_remote << std::endl 1048 978 << "[054] GETM COST (FLITS * DIST) = " << m_cpt_getm_cost << std::endl 1049 << std::endl1050 << "[055] CLEANUP WITH DATA = " << m_cpt_cleanup_with_data << std::endl1051 979 << std::endl 1052 980 << "[056] MULTI_ACK_MISS = " << m_cpt_multi_ack_miss << std::endl … … 1064 992 << "[066] EVICTED SLOT = " << m_cpt_slot_inval << std::endl 1065 993 << std::endl; 994 #endif 1066 995 } 1067 996 1068 if (stats) { 1069 std::cout << "----------------------------------" << std::dec << std::endl; 1070 std::cout << "--- Calculated Stats ---" << std::dec << std::endl; 1071 std::cout << "----------------------------------" << std::dec << std::endl; 1072 std::cout 1073 << "[100] READ TOTAL = " << m_cpt_read_miss_local + m_cpt_read_miss_remote << std::endl 1074 << "[101] READ RATE = " << (double) (m_cpt_read_miss_local + m_cpt_read_miss_remote) / m_cpt_cycles << std::endl 1075 << "[102] LOCAL READ RATE = " << (double) m_cpt_read_miss_local / m_cpt_cycles << std::endl 1076 << "[103] REMOTE READ RATE = " << (double) m_cpt_read_miss_remote / m_cpt_cycles << std::endl 1077 << "[104] READ MISS RATE = " << (double) m_cpt_read_miss / (m_cpt_read_miss_local + m_cpt_read_miss_remote) << std::endl 1078 << "[105] GETM MISS TOTAL = " << m_cpt_getm_miss_local + m_cpt_getm_miss_remote << std::endl 1079 << "[106] GETM MISS RATE = " << (double) (m_cpt_getm_miss_local + m_cpt_getm_miss_remote) / m_cpt_cycles << std::endl 1080 << "[107] LOCAL GETM MISS RATE = " << (double) m_cpt_getm_miss_local / m_cpt_cycles << std::endl 1081 << "[108] REMOTE GETM MISS RATE = " << (double) m_cpt_getm_miss_remote / m_cpt_cycles << std::endl 1082 << "[109] GETM HIT TOTAL = " << m_cpt_getm_hit_local + m_cpt_getm_hit_remote << std::endl 1083 << "[110] GETM HIT RATE = " << (double) (m_cpt_getm_hit_local + m_cpt_getm_hit_remote) / m_cpt_cycles << std::endl 1084 << "[111] LOCAL GETM HIT RATE = " << (double) m_cpt_getm_hit_local / m_cpt_cycles << std::endl 1085 << "[112] REMOTE GETM HIT RATE = " << (double) m_cpt_getm_hit_remote / m_cpt_cycles << std::endl 1086 1087 << "[113] GETM TOTAL = " << m_cpt_getm_hit_local + m_cpt_getm_hit_remote + m_cpt_getm_miss_remote + m_cpt_getm_miss_local << std::endl 1088 1089 << "[114] GETM MISS RATE = " << (double) m_cpt_read_miss / (m_cpt_getm_hit_local + m_cpt_getm_hit_remote + m_cpt_getm_miss_remote + m_cpt_getm_miss_local) << std::endl 1090 1091 << std::endl 1092 << "[115] WRITE TOTAL = " << m_cpt_write_local + m_cpt_write_remote << std::endl 1093 << "[116] WRITE RATE = " << (double) (m_cpt_write_local + m_cpt_write_remote) / m_cpt_cycles << std::endl 1094 << "[117] LOCAL WRITE RATE = " << (double) m_cpt_write_local / m_cpt_cycles << std::endl 1095 << "[118] REMOTE WRITE RATE = " << (double) m_cpt_write_remote / m_cpt_cycles << std::endl 1096 << "[119] WRITE MISS RATE = " << (double) m_cpt_write_miss / (m_cpt_write_local + m_cpt_write_remote) << std::endl 1097 << "[120] WRITE BURST TOTAL = " << m_cpt_write_flits_local + m_cpt_write_flits_remote << std::endl 1098 << "[121] WRITE BURST AVERAGE = " << (double) (m_cpt_write_flits_local + m_cpt_write_flits_remote) / (m_cpt_write_local + m_cpt_write_remote) << std::endl 1099 << "[122] LOCAL WRITE BURST AV. = " << (double) m_cpt_write_flits_local / (m_cpt_write_local + m_cpt_write_remote) << std::endl 1100 << "[123] REMOTE WRITE BURST AV = " << (double) m_cpt_write_flits_remote / (m_cpt_write_local + m_cpt_write_remote) << std::endl 1101 << std::endl 1102 << "[124] UPDATE RATE = " << (double) m_cpt_update / m_cpt_cycles << std::endl 1103 << "[125] AV. UPDATE PER UP REQ = " << (double) (m_cpt_update_local + m_cpt_update_remote) / m_cpt_update << std::endl 1104 << "[126] AV. LOC UPDT PER UP REQ = " << (double) m_cpt_update_local / m_cpt_update << std::endl 1105 << "[127] AV. REMOTE UPDT PER UP REQ = " << (double) m_cpt_update_remote / m_cpt_update << std::endl 1106 << std::endl 1107 << "[128] INVAL MULTICAST RATE = " << (double) m_cpt_minval / m_cpt_cycles << std::endl 1108 << "[129] AVE. INVAL PER M_INV = " << (double) (m_cpt_minval_local + m_cpt_minval_remote) / m_cpt_minval << std::endl 1109 << "[130] AV. LOC INV PER M_INV = " << (double) m_cpt_minval_local / m_cpt_minval << std::endl 1110 << "[131] AV. REM INV PER M_INV = " << (double) m_cpt_minval_remote / m_cpt_minval << std::endl 1111 << std::endl 1112 << "[132] INVAL BROADCAST RATE = " << (double) m_cpt_binval / m_cpt_cycles << std::endl 1113 << "[133] WRITE DIRTY RATE = " << (double) m_cpt_write_dirty / m_cpt_cycles << std::endl 1114 << std::endl 1115 << "[134] CLEANUP RATE = " << (double) (m_cpt_cleanup_local + m_cpt_cleanup_remote) / m_cpt_cycles << std::endl 1116 << "[135] LOCAL CLEANUP RATE = " << (double) m_cpt_cleanup_local / m_cpt_cycles << std::endl 1117 << "[136] REMOTE CLEANUP RATE = " << (double) m_cpt_cleanup_remote / m_cpt_cycles << std::endl 1118 << "[137] LL RATE = " << (double) (m_cpt_ll_local + m_cpt_ll_remote) / m_cpt_cycles << std::endl 1119 << "[138] LOCAL LL RATE = " << (double) m_cpt_ll_local / m_cpt_cycles << std::endl 1120 << "[139] REMOTE LL RATE = " << (double) m_cpt_ll_remote / m_cpt_cycles << std::endl 1121 << "[140] SC RATE = " << (double) (m_cpt_sc_local + m_cpt_sc_remote) / m_cpt_cycles << std::endl 1122 << "[141] LOCAL SC RATE = " << (double) m_cpt_sc_local / m_cpt_cycles << std::endl 1123 << "[142] REMOTE SC RATE = " << (double) m_cpt_sc_remote / m_cpt_cycles << std::endl 1124 << "[143] CAS RATE = " << (double) (m_cpt_cas_local + m_cpt_cas_remote) / m_cpt_cycles << std::endl 1125 << "[144] LOCAL CAS RATE = " << (double) m_cpt_cas_local / m_cpt_cycles << std::endl 1126 << "[145] REMOTE CAS RATE = " << (double) m_cpt_cas_remote / m_cpt_cycles << std::endl 1127 << "[124] MULTI ACK RATE = " << (double) (m_cpt_multi_ack_hit + m_cpt_multi_ack_miss) / m_cpt_cycles << std::endl 1128 << std::endl; 1129 } 997 // No more calculated stats 1130 998 } 1131 999 1132 1000 1133 1001 ///////////////////////////////// 1134 tmpl(/**/) 1135 1002 tmpl(/**/)::~VciMemCache() 1003 ///////////////////////////////// 1136 1004 { 1137 1005 delete [] m_seg; … … 1168 1036 ////////////////////////////////// 1169 1037 tmpl(void) ::transition() 1170 1038 ////////////////////////////////// 1171 1039 { 1172 1040 using soclib::common::uint32_log2; 1173 1041 1174 1042 // RESET 1175 if (! p_resetn.read())1043 if (! p_resetn.read()) 1176 1044 { 1177 1045 … … 1317 1185 1318 1186 // Activity counters 1319 m_cpt_reset_count = 0 ; 1320 m_cpt_read_miss_local = 0 ; 1321 m_cpt_read_miss_remote = 0 ; 1322 m_cpt_read_miss_cost = 0 ; 1323 1324 m_cpt_getm_miss_local = 0 ; 1325 m_cpt_getm_miss_remote = 0 ; 1326 1327 m_cpt_getm_hit_local = 0 ; 1328 m_cpt_getm_hit_remote = 0 ; 1329 m_cpt_getm_cost = 0 ; 1330 1331 m_cpt_write_local = 0 ; 1332 m_cpt_write_remote = 0 ; 1333 m_cpt_write_flits_local = 0 ; 1334 m_cpt_write_flits_remote = 0 ; 1335 m_cpt_write_cost = 0 ; 1336 1337 m_cpt_ll_local = 0 ; 1338 m_cpt_ll_remote = 0 ; 1339 m_cpt_ll_cost = 0 ; 1340 1341 m_cpt_sc_local = 0 ; 1342 m_cpt_sc_remote = 0 ; 1343 m_cpt_sc_cost = 0 ; 1344 1345 m_cpt_cas_local = 0 ; 1346 m_cpt_cas_remote = 0 ; 1347 m_cpt_cas_cost = 0 ; 1348 1349 m_cpt_update = 0 ; 1350 m_cpt_update_local = 0 ; 1351 m_cpt_update_remote = 0 ; 1352 m_cpt_update_cost = 0 ; 1353 1354 m_cpt_minval = 0 ; 1355 m_cpt_minval_local = 0 ; 1356 m_cpt_minval_remote = 0 ; 1357 m_cpt_minval_cost = 0 ; 1358 1359 m_cpt_binval = 0 ; 1360 1361 m_cpt_cleanup_local = 0 ; 1362 m_cpt_cleanup_remote = 0 ; 1363 m_cpt_cleanup_with_data = 0 ; 1364 m_cpt_cleanup_cost = 0 ; 1365 1366 m_cpt_multi_ack_miss = 0 ; 1367 m_cpt_multi_ack_hit = 0 ; 1368 m_cpt_multi_ack_hit_with_data = 0 ; 1369 1370 1371 m_cpt_read_miss = 0 ; 1372 m_cpt_getm_miss = 0 ; 1373 m_cpt_getm_broadcast = 0 ; 1374 m_cpt_getm_minval = 0 ; 1375 m_cpt_write_miss = 0 ; 1376 m_cpt_write_dirty = 0 ; 1377 m_cpt_write_broadcast = 0 ; 1378 m_cpt_write_minval = 0 ; 1379 m_cpt_cas_broadcast = 0 ; 1380 m_cpt_cas_minval = 0 ; 1381 m_cpt_cas_miss = 0 ; 1382 1383 m_cpt_read_locked_rb = 0 ; 1384 m_cpt_cas_locked_rb = 0 ; 1385 m_cpt_write_locked_rb = 0 ; 1386 1387 m_cpt_trt_rb = 0 ; 1388 m_cpt_trt_full = 0 ; 1389 m_cpt_put = 0 ; 1390 m_cpt_get = 0 ; 1391 1392 m_cpt_read_fsm_dir_lock = 0 ; 1393 m_cpt_read_fsm_n_dir_lock = 0 ; 1394 m_cpt_write_fsm_dir_lock = 0 ; 1395 m_cpt_write_fsm_n_dir_lock = 0 ; 1396 m_cpt_xram_rsp_fsm_dir_lock = 0 ; 1397 m_cpt_xram_rsp_fsm_n_dir_lock = 0 ; 1398 m_cpt_cas_fsm_dir_lock = 0 ; 1399 m_cpt_cas_fsm_n_dir_lock = 0 ; 1400 m_cpt_cleanup_fsm_dir_lock = 0 ; 1401 m_cpt_cleanup_fsm_n_dir_lock = 0 ; 1402 m_cpt_multi_ack_fsm_dir_lock = 0 ; 1403 m_cpt_multi_ack_fsm_n_dir_lock = 0 ; 1404 1405 m_cpt_dir_unused = 0 ; 1406 m_cpt_read_fsm_dir_used = 0 ; 1407 m_cpt_write_fsm_dir_used = 0 ; 1408 m_cpt_cas_fsm_dir_used = 0 ; 1409 m_cpt_xram_rsp_fsm_dir_used = 0 ; 1410 m_cpt_cleanup_fsm_dir_used = 0 ; 1411 m_cpt_multi_ack_fsm_dir_used = 0 ; 1412 1413 m_cpt_read_fsm_trt_lock = 0 ; 1414 m_cpt_write_fsm_trt_lock = 0 ; 1415 m_cpt_cas_fsm_trt_lock = 0 ; 1416 m_cpt_xram_rsp_fsm_trt_lock = 0 ; 1417 m_cpt_ixr_fsm_trt_lock = 0 ; 1418 1419 m_cpt_read_fsm_n_trt_lock = 0 ; 1420 m_cpt_write_fsm_n_trt_lock = 0 ; 1421 m_cpt_cas_fsm_n_trt_lock = 0 ; 1422 m_cpt_xram_rsp_fsm_n_trt_lock = 0 ; 1423 m_cpt_ixr_cmd_fsm_n_trt_lock = 0 ; 1424 m_cpt_ixr_rsp_fsm_n_trt_lock = 0 ; 1425 1426 m_cpt_read_fsm_trt_used = 0 ; 1427 m_cpt_write_fsm_trt_used = 0 ; 1428 m_cpt_cas_fsm_trt_used = 0 ; 1429 m_cpt_xram_rsp_fsm_trt_used = 0 ; 1430 m_cpt_ixr_cmd_fsm_trt_used = 0 ; 1431 m_cpt_ixr_rsp_fsm_trt_used = 0 ; 1432 m_cpt_cleanup_fsm_trt_used = 0 ; 1433 1434 m_cpt_trt_unused = 0 ; 1435 1436 m_cpt_cleanup_fsm_ivt_lock = 0 ; 1437 m_cpt_cleanup_fsm_n_ivt_lock = 0 ; 1438 1439 m_cpt_multi_ack_fsm_ivt_lock = 0 ; 1440 m_cpt_multi_ack_fsm_n_ivt_lock = 0 ; 1441 1442 m_cpt_ivt_unused = 0 ; 1443 1444 m_cpt_read_fsm_heap_lock = 0 ; 1445 m_cpt_write_fsm_heap_lock = 0 ; 1446 m_cpt_cas_fsm_heap_lock = 0 ; 1447 m_cpt_cleanup_fsm_heap_lock = 0 ; 1448 m_cpt_xram_rsp_fsm_heap_lock = 0 ; 1449 m_cpt_multi_ack_fsm_heap_lock = 0 ; 1450 1451 m_cpt_read_fsm_n_heap_lock = 0 ; 1452 m_cpt_write_fsm_n_heap_lock = 0 ; 1453 m_cpt_cas_fsm_n_heap_lock = 0 ; 1454 m_cpt_cleanup_fsm_n_heap_lock = 0 ; 1455 m_cpt_xram_rsp_fsm_n_heap_lock = 0 ; 1456 m_cpt_multi_ack_fsm_n_heap_lock = 0 ; 1457 1458 m_cpt_read_fsm_heap_used = 0 ; 1459 m_cpt_write_fsm_heap_used = 0 ; 1460 m_cpt_cas_fsm_heap_used = 0 ; 1461 m_cpt_cleanup_fsm_heap_used = 0 ; 1462 m_cpt_xram_rsp_fsm_heap_used = 0 ; 1463 m_cpt_multi_ack_fsm_heap_used = 0 ; 1464 1465 m_cpt_heap_unused = 0 ; 1466 m_cpt_slot_inval = 0 ; 1187 m_cpt_reset_count = 0; 1188 m_cpt_read_local = 0; 1189 m_cpt_read_remote = 0; 1190 m_cpt_read_cost = 0; 1191 1192 m_cpt_write_local = 0; 1193 m_cpt_write_remote = 0; 1194 m_cpt_write_flits_local = 0; 1195 m_cpt_write_flits_remote = 0; 1196 m_cpt_write_cost = 0; 1197 1198 m_cpt_ll_local = 0; 1199 m_cpt_ll_remote = 0; 1200 m_cpt_ll_cost = 0; 1201 1202 m_cpt_sc_local = 0; 1203 m_cpt_sc_remote = 0; 1204 m_cpt_sc_cost = 0; 1205 1206 m_cpt_cas_local = 0; 1207 m_cpt_cas_remote = 0; 1208 m_cpt_cas_cost = 0; 1209 1210 m_cpt_minval = 0; 1211 m_cpt_minval_local = 0; 1212 m_cpt_minval_remote = 0; 1213 m_cpt_minval_cost = 0; 1214 1215 m_cpt_binval = 0; 1216 m_cpt_write_broadcast = 0; 1217 m_cpt_getm_broadcast = 0; 1218 1219 m_cpt_cleanup_local = 0; 1220 m_cpt_cleanup_remote = 0; 1221 m_cpt_cleanup_cost = 0; 1222 m_cpt_cleanup_data_local = 0; 1223 m_cpt_cleanup_data_remote = 0; 1224 m_cpt_cleanup_data_cost = 0; 1225 1226 m_cpt_read_miss = 0; 1227 m_cpt_write_miss = 0; 1228 m_cpt_write_dirty = 0; 1229 m_cpt_getm_miss = 0; 1230 1231 m_cpt_getm_local = 0; 1232 m_cpt_getm_remote = 0; 1233 m_cpt_getm_cost = 0; 1234 1235 m_cpt_inval_ro_local = 0; 1236 m_cpt_inval_ro_remote = 0; 1237 m_cpt_inval_ro_cost = 0; 1238 1239 m_cpt_trt_rb = 0; 1240 m_cpt_trt_full = 0; 1241 m_cpt_put = 0; 1242 m_cpt_get = 0; 1243 1244 m_cpt_heap_unused = 0; 1245 m_cpt_slot_inval = 0; 1246 1467 1247 return; 1468 1248 } … … 1515 1295 1516 1296 #if DEBUG_MEMC_GLOBAL 1517 if (m_debug)1297 if (m_debug) 1518 1298 { 1519 1299 std::cout … … 1565 1345 ////////////////// 1566 1346 case TGT_CMD_IDLE: // waiting a VCI command (RAM or CONFIG) 1567 if (p_vci_tgt.cmdval)1347 if (p_vci_tgt.cmdval) 1568 1348 { 1569 1349 1570 1350 #if DEBUG_MEMC_TGT_CMD 1571 if (m_debug)1351 if (m_debug) 1572 1352 std::cout << " <MEMC " << name() 1573 1353 << " TGT_CMD_IDLE> Receive command from srcid " … … 1587 1367 { 1588 1368 found = true; 1589 if ( 1369 if (m_seg[seg_id]->special() ) config = true; 1590 1370 } 1591 1371 } … … 1593 1373 if (!found) /////////// out of segment error 1594 1374 { 1595 r_tgt_cmd_fsm 1596 } 1597 else if ( 1375 r_tgt_cmd_fsm = TGT_CMD_ERROR; 1376 } 1377 else if (config ) /////////// configuration command 1598 1378 { 1599 1379 if (!p_vci_tgt.eop.read()) r_tgt_cmd_fsm = TGT_CMD_ERROR; 1600 else 1380 else r_tgt_cmd_fsm = TGT_CMD_CONFIG; 1601 1381 } 1602 1382 else //////////// memory access 1603 1383 { 1604 if ( p_vci_tgt.cmd.read() == vci_param_int::CMD_READ)1384 if (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) 1605 1385 { 1606 1386 // check that the pktid is either : … … 1615 1395 r_tgt_cmd_fsm = TGT_CMD_READ; 1616 1396 } 1617 else if (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)1397 else if (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) 1618 1398 { 1619 1399 // check that the pktid is TYPE_WRITE … … 1622 1402 r_tgt_cmd_fsm = TGT_CMD_WRITE; 1623 1403 } 1624 else if (p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ)1404 else if (p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) 1625 1405 { 1626 1406 // check that the pktid is TYPE_LL … … 1631 1411 r_tgt_cmd_fsm = TGT_CMD_READ; 1632 1412 } 1633 else if (p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP)1413 else if (p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP) 1634 1414 { 1635 1415 // check that the pktid is either : … … 1642 1422 "The type specified in the pktid field is incompatible with the NOP CMD"); 1643 1423 1644 if ((p_vci_tgt.pktid.read() & 0x7) == TYPE_CAS) r_tgt_cmd_fsm = TGT_CMD_CAS;1645 else r_tgt_cmd_fsm = TGT_CMD_WRITE;1424 if ((p_vci_tgt.pktid.read() & 0x7) == TYPE_CAS) r_tgt_cmd_fsm = TGT_CMD_CAS; 1425 else r_tgt_cmd_fsm = TGT_CMD_WRITE; 1646 1426 } 1647 1427 else … … 1657 1437 1658 1438 // wait if pending request 1659 if (r_tgt_cmd_to_tgt_rsp_req.read()) break;1439 if (r_tgt_cmd_to_tgt_rsp_req.read()) break; 1660 1440 1661 1441 // consume all the command packet flits before sending response error 1662 if ( p_vci_tgt.cmdval and p_vci_tgt.eop)1442 if (p_vci_tgt.cmdval and p_vci_tgt.eop) 1663 1443 { 1664 1444 r_tgt_cmd_to_tgt_rsp_srcid = p_vci_tgt.srcid.read(); … … 1670 1450 1671 1451 #if DEBUG_MEMC_TGT_CMD 1672 if (m_debug)1452 if (m_debug) 1673 1453 std::cout << " <MEMC " << name() 1674 1454 << " TGT_CMD_ERROR> Segmentation violation:" … … 1885 1665 uint32_t wdata = p_vci_tgt.wdata.read(); 1886 1666 1887 if ( 1667 if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) // get lock 1888 1668 and (cell == MEMC_LOCK) ) 1889 1669 { … … 1893 1673 r_config_lock = true; 1894 1674 } 1895 else if ( 1675 else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // release lock 1896 1676 and (cell == MEMC_LOCK)) 1897 1677 { … … 1900 1680 r_config_lock = false; 1901 1681 } 1902 else if ( 1682 else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_lo 1903 1683 and (cell == MEMC_ADDR_LO)) 1904 1684 { … … 1911 1691 ((addr_t)wdata); 1912 1692 } 1913 else if ( 1693 else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_hi 1914 1694 and (cell == MEMC_ADDR_HI)) 1915 1695 { … … 1919 1699 (((addr_t) wdata) << 32); 1920 1700 } 1921 else if ( 1701 else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set buf_lines 1922 1702 and (cell == MEMC_BUF_LENGTH)) 1923 1703 { … … 1929 1709 r_config_rsp_lines = 0; 1930 1710 } 1931 else if ( 1711 else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set cmd type 1932 1712 and (cell == MEMC_CMD_TYPE)) 1933 1713 { … … 1945 1725 } 1946 1726 1947 if ( 1727 if (need_rsp ) 1948 1728 { 1949 1729 // blocked if previous pending request to TGT_RSP FSM 1950 if ( 1730 if (r_tgt_cmd_to_tgt_rsp_req.read() ) break; 1951 1731 1952 1732 r_tgt_cmd_to_tgt_rsp_srcid = p_vci_tgt.srcid.read(); … … 1964 1744 1965 1745 #if DEBUG_MEMC_TGT_CMD 1966 if (m_debug)1746 if (m_debug) 1967 1747 std::cout << " <MEMC " << name() << " TGT_CMD_CONFIG> Configuration request:" 1968 1748 << " address = " << std::hex << p_vci_tgt.address.read() … … 1978 1758 1979 1759 // check that the read does not cross a cache line limit. 1980 if ( 1760 if (((m_x[(addr_t) p_vci_tgt.address.read()]+ (p_vci_tgt.plen.read() >>2)) > 16) and 1981 1761 (p_vci_tgt.cmd.read() != vci_param_int::CMD_LOCKED_READ)) 1982 1762 { … … 1986 1766 } 1987 1767 // check single flit 1988 if (!p_vci_tgt.eop.read())1768 if (!p_vci_tgt.eop.read()) 1989 1769 { 1990 1770 std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state" … … 1993 1773 } 1994 1774 // check plen for LL 1995 if ( 1775 if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) and 1996 1776 (p_vci_tgt.plen.read() != 8) ) 1997 1777 { … … 2001 1781 } 2002 1782 2003 if ( 1783 if (p_vci_tgt.cmdval and m_cmd_read_addr_fifo.wok() ) 2004 1784 { 2005 1785 2006 1786 #if DEBUG_MEMC_TGT_CMD 2007 if (m_debug)1787 if (m_debug) 2008 1788 std::cout << " <MEMC " << name() << " TGT_CMD_READ> Push into read_fifo:" 2009 1789 << " address = " << std::hex << p_vci_tgt.address.read() … … 2016 1796 // <Activity counters> 2017 1797 if (p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) { 2018 if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_ll_local++; 2019 else m_cpt_ll_remote++; 2020 m_cpt_ll_cost += req_distance(p_vci_tgt.srcid.read()); // LL on a single word 2021 } 2022 else { 2023 if ((p_vci_tgt.pktid.read() & 0x7) == TYPE_WRITE) 2024 { 2025 if ((p_vci_tgt.pktid.read() & 0x8) == 0x8) 2026 { 2027 if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_getm_hit_local++; 2028 else m_cpt_getm_hit_remote++; 2029 } 2030 else 2031 { 2032 if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_getm_miss_local++; 2033 else m_cpt_getm_miss_remote++; 2034 } 2035 m_cpt_getm_cost += req_distance(p_vci_tgt.srcid.read()); 1798 if (is_local_req(p_vci_tgt.srcid.read())) 1799 { 1800 m_cpt_ll_local++; 2036 1801 } 2037 1802 else 2038 1803 { 2039 if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_read_miss_local++; 2040 else m_cpt_read_miss_remote++; 2041 m_cpt_read_miss_cost += req_distance(p_vci_tgt.srcid.read()); 2042 } 1804 m_cpt_ll_remote++; 1805 } 1806 // (1 (CMD) + 2 (RSP)) VCI flits for LL => 2 + 3 dspin flits 1807 m_cpt_ll_cost += 5 * req_distance(p_vci_tgt.srcid.read()); // LL on a single word 1808 } 1809 else if ((p_vci_tgt.pktid.read() & 0x7) == TYPE_WRITE) 1810 { 1811 if (is_local_req(p_vci_tgt.srcid.read())) 1812 { 1813 m_cpt_getm_local++; 1814 } 1815 else 1816 { 1817 m_cpt_getm_remote++; 1818 } 1819 // (1 (CMD) + m_words (RSP)) flits VCI => 2 + m_words + 1 flits dspin 1820 m_cpt_getm_cost += (3 + m_words) * req_distance(p_vci_tgt.srcid.read()); 1821 } 1822 else 1823 { 1824 if (is_local_req(p_vci_tgt.srcid.read())) 1825 { 1826 m_cpt_read_local++; 1827 } 1828 else 1829 { 1830 m_cpt_read_remote++; 1831 } 1832 // (1 (CMD) + m_words (RSP)) flits VCI => 2 + m_words + 1 flits dspin 1833 m_cpt_read_cost += (3 + m_words) * req_distance(p_vci_tgt.srcid.read()); 2043 1834 } 2044 1835 // </Activity counters> … … 2049 1840 /////////////////// 2050 1841 case TGT_CMD_WRITE: 2051 if (p_vci_tgt.cmdval and m_cmd_write_addr_fifo.wok())2052 { 2053 1842 if (p_vci_tgt.cmdval and m_cmd_write_addr_fifo.wok()) 1843 { 1844 uint32_t plen = p_vci_tgt.plen.read(); 2054 1845 #if DEBUG_MEMC_TGT_CMD 2055 if (m_debug)1846 if (m_debug) 2056 1847 std::cout << " <MEMC " << name() << " TGT_CMD_WRITE> Push into write_fifo:" 2057 1848 << " address = " << std::hex << p_vci_tgt.address.read() … … 2061 1852 << " / wdata = " << p_vci_tgt.wdata.read() 2062 1853 << " / be = " << p_vci_tgt.be.read() 2063 << " / plen = " << std::dec << p _vci_tgt.plen.read()<< std::endl;1854 << " / plen = " << std::dec << plen << std::endl; 2064 1855 #endif 2065 1856 cmd_write_fifo_put = true; 2066 1857 // <Activity counters> 2067 1858 if (p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP) { 2068 m_cpt_sc_cost += req_distance(p_vci_tgt.srcid.read()); 1859 // (2 (CMD) + 1 (RSP)) flits VCI => 4 + (1 (success) || 2 (failure)) flits dspin 1860 m_cpt_sc_cost += 5 * req_distance(p_vci_tgt.srcid.read()); 2069 1861 } 2070 1862 else { 2071 if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_write_flits_local++; 2072 else m_cpt_write_flits_remote++; 2073 m_cpt_write_cost += req_distance(p_vci_tgt.srcid.read()); 1863 if (is_local_req(p_vci_tgt.srcid.read())) 1864 { 1865 m_cpt_write_flits_local++; 1866 } 1867 else 1868 { 1869 m_cpt_write_flits_remote++; 1870 } 1871 // (burst_size (CMD) + 1 (RSP) flits VCI => 2 + burst_size + 1 flits dspin 1872 m_cpt_write_cost += (3 + (plen >> 2)) * req_distance(p_vci_tgt.srcid.read()); 2074 1873 } 2075 1874 // </Activity counters> … … 2078 1877 // <Activity counters> 2079 1878 if (p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP) { 2080 if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_sc_local++; 2081 else m_cpt_sc_remote++; 2082 1879 if (is_local_req(p_vci_tgt.srcid.read())) 1880 { 1881 m_cpt_sc_local++; 1882 } 1883 else 1884 { 1885 m_cpt_sc_remote++; 1886 } 2083 1887 } 2084 1888 else { 2085 if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_write_local++; 2086 else m_cpt_write_remote++; 1889 if (is_local_req(p_vci_tgt.srcid.read())) 1890 { 1891 m_cpt_write_local++; 1892 } 1893 else 1894 { 1895 m_cpt_write_remote++; 1896 } 2087 1897 } 2088 1898 // </Activity counters> … … 2093 1903 ///////////////// 2094 1904 case TGT_CMD_CAS: 2095 if ((p_vci_tgt.plen.read() != 8) and (p_vci_tgt.plen.read() != 16))1905 if ((p_vci_tgt.plen.read() != 8) and (p_vci_tgt.plen.read() != 16)) 2096 1906 { 2097 1907 std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_CAS state" … … 2100 1910 } 2101 1911 2102 if (p_vci_tgt.cmdval and m_cmd_cas_addr_fifo.wok())1912 if (p_vci_tgt.cmdval and m_cmd_cas_addr_fifo.wok()) 2103 1913 { 2104 1914 2105 1915 #if DEBUG_MEMC_TGT_CMD 2106 if (m_debug)1916 if (m_debug) 2107 1917 std::cout << " <MEMC " << name() << " TGT_CMD_CAS> Pushing command into cmd_cas_fifo:" 2108 1918 << " address = " << std::hex << p_vci_tgt.address.read() … … 2117 1927 if (p_vci_tgt.eop) { 2118 1928 // <Activity counters> 2119 if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_cas_local++; 2120 else m_cpt_cas_remote++; 2121 m_cpt_cas_cost += req_distance(p_vci_tgt.srcid.read()); 1929 if (is_local_req(p_vci_tgt.srcid.read())) 1930 { 1931 m_cpt_cas_local++; 1932 } 1933 else 1934 { 1935 m_cpt_cas_remote++; 1936 } 1937 // (2 (CMD) + 1 (RSP)) flits VCI => 4 + (1 (success) || 2 (failure)) flits dspin 1938 m_cpt_cas_cost += 5 * req_distance(p_vci_tgt.srcid.read()); 2122 1939 // </Activity counters> 2123 1940 r_tgt_cmd_fsm = TGT_CMD_IDLE; … … 2151 1968 uint64_t flit = m_cc_receive_to_multi_ack_fifo.read(); 2152 1969 2153 if ( not multi_ack_fifo_rok)1970 if (not multi_ack_fifo_rok) 2154 1971 break; 2155 1972 2156 size_t ivt_index = DspinDhccpParam::dspin_get(flit,2157 Dspin DhccpParam::MULTI_ACK_UPDT_INDEX);2158 2159 bool miss_updt = DspinDhccpParam::dspin_get(flit,2160 Dspin DhccpParam::MULTI_ACK_UPDT_MISS);2161 2162 bool eop = Dspin DhccpParam::dspin_get(flit, DspinDhccpParam::P2M_EOP) == 0x1;1973 size_t ivt_index = DspinHmesiParam::dspin_get(flit, 1974 DspinHmesiParam::MULTI_ACK_UPDT_INDEX); 1975 1976 bool miss_updt = DspinHmesiParam::dspin_get(flit, 1977 DspinHmesiParam::MULTI_ACK_UPDT_MISS); 1978 1979 bool eop = DspinHmesiParam::dspin_get(flit, DspinHmesiParam::P2M_EOP) == 0x1; 2163 1980 2164 1981 cc_receive_to_multi_ack_fifo_get = true; … … 2171 1988 r_multi_ack_miss_updt = miss_updt; 2172 1989 2173 if(miss_updt) 2174 m_cpt_multi_ack_miss ++; 2175 else 2176 m_cpt_multi_ack_hit ++; 2177 2178 if( not eop) 2179 { 2180 r_multi_ack_fsm = MULTI_ACK_GET_DATA; 1990 if (not eop) 1991 { 2181 1992 r_multi_ack_need_data = true; 2182 1993 r_multi_ack_data_index = 0; 2183 m_cpt_multi_ack_hit_with_data ++;1994 r_multi_ack_fsm = MULTI_ACK_GET_DATA; 2184 1995 } 2185 1996 else 2186 1997 { 1998 r_multi_ack_need_data = false; 2187 1999 r_multi_ack_fsm = MULTI_ACK_DIR_REQ; 2188 r_multi_ack_need_data = false;2189 2000 } 2190 2001 2191 2002 #if DEBUG_MEMC_MULTI_ACK 2192 if (m_debug)2003 if (m_debug) 2193 2004 { 2194 2005 if (multi_ack_fifo_rok) … … 2211 2022 2212 2023 uint32_t data = 2213 Dspin DhccpParam::dspin_get (flit, DspinDhccpParam::CLEANUP_DATA_UPDT);2214 2215 bool eop = Dspin DhccpParam::dspin_get(flit, DspinDhccpParam::P2M_EOP) == 0x1;2024 DspinHmesiParam::dspin_get (flit, DspinHmesiParam::CLEANUP_DATA_UPDT); 2025 2026 bool eop = DspinHmesiParam::dspin_get(flit, DspinHmesiParam::P2M_EOP) == 0x1; 2216 2027 #if DEBUG_MEMC_CLEANUP 2217 if (m_debug)2028 if (m_debug) 2218 2029 { 2219 2030 std::cout … … 2242 2053 case MULTI_ACK_IVT_LOCK: 2243 2054 { 2244 m_cpt_multi_ack_fsm_ivt_lock ++; 2245 if(r_alloc_ivt_fsm.read() != ALLOC_IVT_MULTI_ACK) break; 2246 2247 m_cpt_multi_ack_fsm_n_ivt_lock ++; 2055 if (r_alloc_ivt_fsm.read() != ALLOC_IVT_MULTI_ACK) break; 2248 2056 2249 2057 assert( r_alloc_dir_fsm.read() == ALLOC_DIR_MULTI_ACK && " BAD ALLOC_DIR_MULTI_ACK IN MULTI_ACK_IVT_LOCK STATE"); 2250 size_t index 2251 size_t count 2252 size_t nline 2058 size_t index = r_multi_ack_ivt_index.read(); 2059 size_t count = m_ivt.count(index); 2060 size_t nline = m_ivt.nline(index); 2253 2061 r_multi_ack_nline = nline; 2254 2062 r_multi_ack_srcid = m_ivt.srcid(index); … … 2256 2064 r_multi_ack_pktid = m_ivt.pktid(index); 2257 2065 r_multi_ack_rsp = m_ivt.need_rsp(index); 2258 //bool is_valid = m_ivt.is_valid(index); 2259 2260 // if(r_multi_ack_miss_updt.read()) 2261 //{ 2262 r_multi_ack_fsm = MULTI_ACK_DIR_LOCK; // this way may be bring about the problem of critical path 2263 //} 2264 //else 2265 //{ 2266 bool is_updt = m_ivt.is_update(index); 2066 uint32_t srcid = m_ivt.srcid(index); 2267 2067 2268 assert(is_updt && "MULTI_ACK: is not an updt index for a multi ack rsp"); 2269 assert(count == 1 && "there is only one copy in the memc"); 2270 2271 // r_multi_ack_fsm = MULTI_ACK_IVT_CLEAR; 2068 // <Activity Counters> 2069 // We count "read-only invalidations" at the same place as 2070 // multi ack. 2071 // The idea is that a RO inval is always responded by a multi ack, 2072 // and that a multi ack is sent only for inval RO. 2073 // Thus, we add one to the cost for the inval RO fleet, and 2074 // depending on the response, we add either 1 or m_words + 1 for the cost for the multi ack flits 2075 if (r_multi_ack_need_data.read()) 2076 { 2077 // multi_ack with data 2078 if (is_local_req(srcid)) 2079 { 2080 m_cpt_inval_ro_local++; 2081 } 2082 else 2083 { 2084 m_cpt_inval_ro_remote++; 2085 } 2086 // 2 flits for inval RO + (m_words + 1) flits for the multi ack 2087 m_cpt_inval_ro_cost += (m_words + 1) * req_distance(srcid); 2088 } 2089 else 2090 { 2091 // multi_ack without data 2092 if (is_local_req(srcid)) 2093 { 2094 m_cpt_inval_ro_local++; 2095 } 2096 else 2097 { 2098 m_cpt_inval_ro_remote++; 2099 } 2100 // 2 flits for inval RO + 1 flit for the multi ack 2101 m_cpt_inval_ro_cost += 3 * req_distance(srcid); // 1 flit 2102 } 2103 // </Activity Counters> 2104 2105 2106 r_multi_ack_fsm = MULTI_ACK_DIR_LOCK; // this way may be bring about the problem of critical path 2107 bool is_updt = m_ivt.is_update(index); 2108 2109 assert(is_updt && "MULTI_ACK: is not an updt index for a multi ack rsp"); 2110 assert(count == 1 && "there is only one copy in the memc"); 2272 2111 2273 2112 #if DEBUG_MEMC_MULTI_ACK 2274 if (m_debug)2113 if (m_debug) 2275 2114 std::cout << " <MEMC " << name() 2276 2115 << " MULTI_ACK_IVT_LOCK> " … … 2283 2122 case MULTI_ACK_IVT_CLEAR: 2284 2123 { 2285 if (r_alloc_ivt_fsm.read() != ALLOC_IVT_MULTI_ACK )2124 if (r_alloc_ivt_fsm.read() != ALLOC_IVT_MULTI_ACK ) 2286 2125 { 2287 2126 std::cout … … 2297 2136 2298 2137 #if DEBUG_MEMC_MULTI_ACK 2299 if (m_debug)2138 if (m_debug) 2300 2139 std::cout << " <MEMC " << name() 2301 2140 << " MULTI_ACK_IVT_CLEAR> IVT clear:" … … 2308 2147 case MULTI_ACK_DIR_REQ: // Get the lock to the directory 2309 2148 { 2310 m_cpt_multi_ack_fsm_dir_lock ++; 2311 if(r_alloc_dir_fsm.read() != ALLOC_DIR_MULTI_ACK) break; 2149 if (r_alloc_dir_fsm.read() != ALLOC_DIR_MULTI_ACK) break; 2312 2150 2313 2151 r_multi_ack_fsm = MULTI_ACK_IVT_LOCK; 2314 2152 //std::cout << " MEM_CACHE : CLEANUP_DIR_REQ" << std::endl; 2315 m_cpt_multi_ack_fsm_n_dir_lock ++;2316 2153 2317 2154 #if DEBUG_MEMC_CLEANUP 2318 if (m_debug)2155 if (m_debug) 2319 2156 std::cout << " <MEMC " << name() << " MULTI_ACK_DIR_REQ> Requesting DIR lock" << std::endl; 2320 2157 #endif … … 2325 2162 case MULTI_ACK_DIR_LOCK: //updt data with the registers which have saved the set and way 2326 2163 { 2327 if (r_alloc_dir_fsm.read() != ALLOC_DIR_MULTI_ACK)2164 if (r_alloc_dir_fsm.read() != ALLOC_DIR_MULTI_ACK) 2328 2165 { 2329 2166 std::cout … … 2349 2186 2350 2187 #if DEBUG_MEMC_MULTI_ACK 2351 if (m_debug)2188 if (m_debug) 2352 2189 { 2353 2190 std::cout … … 2365 2202 } 2366 2203 #endif 2367 assert( (entry.state == ENTRY_LOCKED) && "mutli rsp check the entry, the line is not locked!!!");2204 assert((entry.state == ENTRY_LOCKED) && "multi rsp check the entry, the line is not locked!!!"); 2368 2205 2369 if (r_multi_ack_miss_updt.read() and entry.count) //cache L1 has sent the cleanup when it receives the cc_updt request,2206 if (r_multi_ack_miss_updt.read() and entry.count) //cache L1 has sent the cleanup when it receives the cc_updt request, 2370 2207 { 2371 2208 r_multi_ack_fsm = MULTI_ACK_IVT_CHANGE; 2372 2209 } 2373 else if (not entry.count or match_ll) // The line has been already evicted from cache L12210 else if (not entry.count or match_ll) // The line has been already evicted from cache L1 2374 2211 { 2375 2212 assert(((entry.count == 1) or (entry.count == 0)) && "multi ack for a ll request, count is 1"); 2376 r_multi_ack_fsm 2213 r_multi_ack_fsm = MULTI_ACK_DIR_UPDT; 2377 2214 } 2378 2215 else 2379 2216 { 2380 r_multi_ack_fsm 2217 r_multi_ack_fsm = MULTI_ACK_HEAP_REQ; 2381 2218 } 2382 2219 break; 2383 2220 } 2384 2221 ///////////// 2385 case MULTI_ACK_IVT_CHANGE: // release all locks and retry from beginning2222 case MULTI_ACK_IVT_CHANGE: 2386 2223 { 2387 if (r_alloc_ivt_fsm.read() != ALLOC_IVT_MULTI_ACK)2224 if (r_alloc_ivt_fsm.read() != ALLOC_IVT_MULTI_ACK) 2388 2225 { 2389 2226 std::cout … … 2396 2233 m_ivt.change(r_multi_ack_ivt_index.read()); 2397 2234 #if DEBUG_MEMC_MULTI_ACK 2398 if (m_debug)2235 if (m_debug) 2399 2236 { 2400 2237 std::cout << " <MEMC " << name() … … 2408 2245 case MULTI_ACK_DIR_UPDT: 2409 2246 { 2410 if (r_alloc_dir_fsm.read() != ALLOC_DIR_MULTI_ACK)2247 if (r_alloc_dir_fsm.read() != ALLOC_DIR_MULTI_ACK) 2411 2248 { 2412 2249 std::cout … … 2420 2257 bool match_ll = ((r_multi_ack_pktid.read() & 0x07) == TYPE_LL); 2421 2258 2422 if (r_multi_ack_need_data.read())2423 { 2424 for (size_t word=0; word<m_words; word++)2259 if (r_multi_ack_need_data.read()) 2260 { 2261 for (size_t word = 0; word<m_words; word++) 2425 2262 { 2426 2263 m_cache_data.write(r_multi_ack_way.read(), … … 2429 2266 r_multi_ack_data[word]); 2430 2267 } 2431 // addr_t min = r_multi_ack_nline.read()*m_words*4 ;2432 // addr_t max = r_multi_ack_nline.read()*m_words*4 + (m_words - 1)*4;2433 // m_llsc_table.sw(min, max);2434 2435 2268 } 2436 2269 else 2437 2270 { 2438 m_cache_data.read_line( 2439 2440 2271 m_cache_data.read_line(r_multi_ack_way.read(), 2272 r_multi_ack_set.read(), 2273 r_multi_ack_data); 2441 2274 } 2442 2275 2443 2276 DirectoryEntry entry; 2444 entry.is_cnt 2445 entry.dirty 2446 entry.tag 2447 entry.lock 2448 entry.ptr 2449 2450 if (match_ll)2451 { 2452 entry.owner.srcid 2453 entry.count 2277 entry.is_cnt = false; 2278 entry.dirty = r_multi_ack_dirty.read() or r_multi_ack_need_data.read(); 2279 entry.tag = r_multi_ack_tag.read(); 2280 entry.lock = r_multi_ack_lock.read(); 2281 entry.ptr = 0; 2282 2283 if (match_ll) 2284 { 2285 entry.owner.srcid = r_multi_ack_copy.read(); 2286 entry.count = r_multi_ack_count.read(); 2454 2287 } 2455 2288 else 2456 2289 { 2457 entry.owner.srcid = r_multi_ack_srcid.read(); 2458 entry.count = 1; 2459 } 2460 2461 2462 // if( (r_multi_ack_pktid.read() & 0x07) == 0x03 or match_ll) 2463 // { 2464 entry.state = ENTRY_SHARED; // MISS INST 2465 // } 2466 // else 2467 // { 2468 // entry.state = ENTRY_EXCLUSIVE; // MISS DATA 2469 // } 2470 2471 if((r_multi_ack_pktid.read() & 0x7) == 0x03) 2290 entry.owner.srcid = r_multi_ack_srcid.read(); 2291 entry.count = 1; 2292 } 2293 2294 entry.state = ENTRY_SHARED; // MISS INST 2295 2296 if ((r_multi_ack_pktid.read() & 0x7) == 0x03) 2472 2297 { 2473 2298 entry.owner.inst = true; … … 2483 2308 r_multi_ack_fsm = MULTI_ACK_IVT_CLEAR; 2484 2309 #if DEBUG_MEMC_MULTI_ACK 2485 if (m_debug)2310 if (m_debug) 2486 2311 { 2487 2312 std::cout << " <MEMC " << name() << " MULTI_ACK_DIR_UPDT>" … … 2499 2324 // wait if pending request to the TGT_RSP FSM 2500 2325 { 2501 if (r_multi_ack_to_tgt_rsp_req.read()) break;2502 2503 for (size_t i = 0; i<m_words; i++)2326 if (r_multi_ack_to_tgt_rsp_req.read()) break; 2327 2328 for (size_t i = 0; i<m_words; i++) 2504 2329 { 2505 2330 r_multi_ack_to_tgt_rsp_data[i] = r_multi_ack_data[i].read(); 2506 2331 } 2507 2332 // no pending request 2508 r_multi_ack_to_tgt_rsp_req 2509 if (r_read_to_multi_ack_req.read() and (r_read_to_multi_ack_nline.read() == r_multi_ack_nline.read()))2510 { 2511 r_multi_ack_to_tgt_rsp_word 2512 r_multi_ack_to_tgt_rsp_length 2513 r_read_to_multi_ack_req 2333 r_multi_ack_to_tgt_rsp_req = true; 2334 if (r_read_to_multi_ack_req.read() and (r_read_to_multi_ack_nline.read() == r_multi_ack_nline.read())) 2335 { 2336 r_multi_ack_to_tgt_rsp_word = r_read_to_multi_ack_first_word.read(); 2337 r_multi_ack_to_tgt_rsp_length = r_read_to_multi_ack_length.read(); 2338 r_read_to_multi_ack_req = false; 2514 2339 } 2515 2340 else 2516 2341 { 2517 r_multi_ack_to_tgt_rsp_word = 0; 2518 r_multi_ack_to_tgt_rsp_length = 16; 2519 } 2520 2521 r_multi_ack_to_tgt_ll_key = r_read_to_multi_ack_ll_key.read(); 2522 r_multi_ack_to_tgt_rsp_srcid = r_multi_ack_srcid.read(); 2523 r_multi_ack_to_tgt_rsp_trdid = r_multi_ack_trdid.read(); 2524 2525 // if(r_multi_ack_rsp_shared.read()) // rsp read with shared or exclusive state 2526 // { 2527 r_multi_ack_to_tgt_rsp_pktid = r_multi_ack_pktid.read(); 2528 // } 2529 // else 2530 //{ 2531 // r_multi_ack_to_tgt_rsp_pktid = 0x08 + r_multi_ack_pktid.read(); 2532 //} 2533 2534 r_multi_ack_fsm = MULTI_ACK_IDLE; 2342 r_multi_ack_to_tgt_rsp_word = 0; 2343 r_multi_ack_to_tgt_rsp_length = 16; 2344 } 2345 2346 r_multi_ack_to_tgt_ll_key = r_read_to_multi_ack_ll_key.read(); 2347 r_multi_ack_to_tgt_rsp_srcid = r_multi_ack_srcid.read(); 2348 r_multi_ack_to_tgt_rsp_trdid = r_multi_ack_trdid.read(); 2349 r_multi_ack_to_tgt_rsp_pktid = r_multi_ack_pktid.read(); 2350 2351 r_multi_ack_fsm = MULTI_ACK_IDLE; 2535 2352 2536 2353 #if DEBUG_MEMC_MULTI_ACK 2537 if (m_debug)2354 if (m_debug) 2538 2355 std::cout << " <MEMC " << name() << " MULTI_ACK_RSP>" 2539 2356 << " Send a response to a previous read/ll request: " … … 2553 2370 case MULTI_ACK_HEAP_REQ: // Get the lock to the HEAP directory 2554 2371 { 2555 m_cpt_multi_ack_fsm_n_heap_lock ++; 2556 if(r_alloc_heap_fsm.read() == ALLOC_HEAP_MULTI_ACK) 2372 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_MULTI_ACK) 2557 2373 { 2558 2374 r_multi_ack_fsm = MULTI_ACK_HEAP_LOCK; 2559 2375 } 2560 2376 2561 m_cpt_multi_ack_fsm_heap_lock ++;2562 2377 #if DEBUG_MEMC_MULTI_ACK 2563 if (m_debug)2378 if (m_debug) 2564 2379 std::cout << " <MEMC " << name() << " MULTI_ACK_HEAP_REQ>" 2565 2380 << " Requesting HEAP lock " << std::endl; … … 2571 2386 // and prepare the HEAP update 2572 2387 { 2573 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_MULTI_ACK and2388 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_MULTI_ACK and 2574 2389 r_alloc_dir_fsm.read() == ALLOC_DIR_MULTI_ACK) 2575 2390 { 2576 if (r_multi_ack_need_data.read())2577 { 2578 for (size_t word=0; word<m_words ; word++)2391 if (r_multi_ack_need_data.read()) 2392 { 2393 for (size_t word = 0; word < m_words ; word++) 2579 2394 { 2580 2395 m_cache_data.write(r_multi_ack_way.read(), … … 2583 2398 r_multi_ack_data[word]); 2584 2399 } 2585 2586 // addr_t min = r_multi_ack_nline.read()*m_words*4 ;2587 // addr_t max = r_multi_ack_nline.read()*m_words*4 + (m_words - 1)*4;2588 // m_llsc_table.sw(min, max);2589 2590 2400 } 2591 2401 else 2592 2402 { 2593 m_cache_data.read_line( 2594 2595 2403 m_cache_data.read_line(r_multi_ack_way.read(), 2404 r_multi_ack_set.read(), 2405 r_multi_ack_data); 2596 2406 } 2597 2407 … … 2606 2416 entry.dirty = r_multi_ack_dirty.read() or r_multi_ack_need_data.read(); 2607 2417 entry.tag = r_multi_ack_tag.read(); 2608 if (not go_cnt) // Not entering counter mode2609 { 2610 entry.owner.srcid 2611 entry.owner.inst 2612 entry.ptr 2613 2614 HeapEntry heap_entry 2615 2616 r_multi_ack_next_ptr 2617 r_multi_ack_last_free 2618 r_multi_ack_fsm 2418 if (not go_cnt) // Not entering counter mode 2419 { 2420 entry.owner.srcid = r_multi_ack_copy.read(); 2421 entry.owner.inst = r_multi_ack_copy_inst.read(); 2422 entry.ptr = m_heap.next_free_ptr(); // set pointer on the heap 2423 2424 HeapEntry heap_entry = m_heap.next_free_entry(); 2425 2426 r_multi_ack_next_ptr = heap_entry.next; 2427 r_multi_ack_last_free = (heap_entry.next == m_heap.next_free_ptr()); 2428 r_multi_ack_fsm = MULTI_ACK_HEAP_WRITE; // add an entry in the HEAP 2619 2429 } 2620 2430 else // Entering Counter mode … … 2629 2439 2630 2440 #if DEBUG_MEMC_MULTI_ACK 2631 if (m_debug)2441 if (m_debug) 2632 2442 std::cout << " <MEMC " << name() << " MULTI_ACK_HEAP_LOCK> Update directory:" 2633 2443 << " tag = " << std::hex << entry.tag … … 2650 2460 case MULTI_ACK_HEAP_WRITE: // add an entry in the heap 2651 2461 { 2652 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_MULTI_ACK and2462 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_MULTI_ACK and 2653 2463 r_alloc_dir_fsm.read() == ALLOC_DIR_MULTI_ACK) 2654 2464 { 2655 2465 HeapEntry heap_entry; 2656 heap_entry.owner.srcid 2657 2658 if ((r_multi_ack_pktid.read() & 0x07) == 0x03)2659 { 2660 heap_entry.owner.inst 2466 heap_entry.owner.srcid = r_multi_ack_srcid.read(); 2467 2468 if ((r_multi_ack_pktid.read() & 0x07) == 0x03) 2469 { 2470 heap_entry.owner.inst = 1; 2661 2471 } 2662 2472 else 2663 2473 { 2664 heap_entry.owner.inst 2665 } 2666 2667 heap_entry.next 2474 heap_entry.owner.inst = 0; 2475 } 2476 2477 heap_entry.next = m_heap.next_free_ptr(); 2668 2478 m_heap.write_free_entry(heap_entry); 2669 2479 m_heap.write_free_ptr(r_multi_ack_next_ptr.read()); 2670 if (r_multi_ack_last_free.read()) m_heap.set_full();2480 if (r_multi_ack_last_free.read()) m_heap.set_full(); 2671 2481 2672 2482 r_multi_ack_fsm = MULTI_ACK_IVT_CLEAR; 2673 2483 2674 2484 #if DEBUG_MEMC_MULTI_ACK 2675 if (m_debug)2485 if (m_debug) 2676 2486 std::cout << " <MEMC " << name() << " MULTI_ACK_HEAP_WRITE> Add an entry in the heap:" 2677 2487 << " owner_id = " << std::hex << heap_entry.owner.srcid … … 2754 2564 //////////////////////////////////////////////////////////////////////////////////// 2755 2565 2756 switch ( r_config_fsm.read())2566 switch (r_config_fsm.read()) 2757 2567 { 2758 2568 ///////////////// 2759 2569 case CONFIG_IDLE: // waiting a config request 2760 2570 { 2761 if ( r_config_cmd.read() != MEMC_CMD_NOP)2762 { 2763 r_config_fsm 2571 if (r_config_cmd.read() != MEMC_CMD_NOP) 2572 { 2573 r_config_fsm = CONFIG_LOOP; 2764 2574 2765 2575 #if DEBUG_MEMC_CONFIG 2766 if (m_debug)2576 if (m_debug) 2767 2577 std::cout << " <MEMC " << name() << " CONFIG_IDLE> Config Request received" 2768 2578 << " address = " << std::hex << r_config_address.read() … … 2776 2586 case CONFIG_LOOP: // test last line to be handled 2777 2587 { 2778 if ( r_config_cmd_lines.read() == 0)2588 if (r_config_cmd_lines.read() == 0) 2779 2589 { 2780 2590 r_config_cmd = MEMC_CMD_NOP; … … 2787 2597 2788 2598 #if DEBUG_MEMC_CONFIG 2789 if (m_debug)2599 if (m_debug) 2790 2600 std::cout << " <MEMC " << name() << " CONFIG_LOOP>" 2791 2601 << " address = " << std::hex << r_config_address.read() … … 2798 2608 case CONFIG_WAIT: // wait completion (last response) 2799 2609 { 2800 if ( r_config_rsp_lines.read() == 0) // last response received2610 if (r_config_rsp_lines.read() == 0) // last response received 2801 2611 { 2802 2612 r_config_fsm = CONFIG_RSP; … … 2804 2614 2805 2615 #if DEBUG_MEMC_CONFIG 2806 if (m_debug)2616 if (m_debug) 2807 2617 std::cout << " <MEMC " << name() << " CONFIG_WAIT>" 2808 2618 << " / lines to do = " << std::dec << r_config_rsp_lines.read() << std::endl; … … 2813 2623 case CONFIG_RSP: // request TGT_RSP FSM to return response 2814 2624 { 2815 if ( 2816 { 2817 r_config_to_tgt_rsp_srcid 2818 r_config_to_tgt_rsp_trdid 2819 r_config_to_tgt_rsp_pktid 2820 r_config_to_tgt_rsp_error 2821 r_config_to_tgt_rsp_req 2822 r_config_fsm 2625 if (not r_config_to_tgt_rsp_req.read() ) 2626 { 2627 r_config_to_tgt_rsp_srcid = r_config_srcid.read(); 2628 r_config_to_tgt_rsp_trdid = r_config_trdid.read(); 2629 r_config_to_tgt_rsp_pktid = r_config_pktid.read(); 2630 r_config_to_tgt_rsp_error = false; 2631 r_config_to_tgt_rsp_req = true; 2632 r_config_fsm = CONFIG_IDLE; 2823 2633 2824 2634 #if DEBUG_MEMC_CONFIG 2825 if (m_debug)2635 if (m_debug) 2826 2636 std::cout << " <MEMC " << name() << " CONFIG_RSP> Request TGT_RSP FSM to return response:" 2827 2637 << " error = " << r_config_to_tgt_rsp_error.read() … … 2838 2648 case CONFIG_DIR_REQ: // Request directory lock 2839 2649 { 2840 if ( 2650 if (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG ) 2841 2651 { 2842 2652 r_config_fsm = CONFIG_DIR_ACCESS; … … 2844 2654 2845 2655 #if DEBUG_MEMC_CONFIG 2846 if (m_debug)2656 if (m_debug) 2847 2657 std::cout << " <MEMC " << name() << " CONFIG_DIR_REQ>" 2848 2658 << " Request DIR access" << std::endl; … … 2871 2681 (r_config_cmd.read() == MEMC_CMD_INVAL)) 2872 2682 { 2873 r_config_fsm 2874 } 2875 else if ( 2683 r_config_fsm = CONFIG_IVT_LOCK; 2684 } 2685 else if ((entry.state == ENTRY_SHARED or entry.state == ENTRY_EXCLUSIVE) and // hit & sync command 2876 2686 entry.dirty and (r_config_cmd.read() == MEMC_CMD_SYNC) ) 2877 2687 { 2878 2688 r_config_fsm = CONFIG_TRT_LOCK; 2879 2689 } 2880 else if (entry.state == ENTRY_LOCKED)2690 else if (entry.state == ENTRY_LOCKED) 2881 2691 { // wait for unlock 2882 2692 r_config_fsm = CONFIG_WAIT; … … 2891 2701 2892 2702 #if DEBUG_MEMC_CONFIG 2893 if (m_debug)2703 if (m_debug) 2894 2704 std::cout << " <MEMC " << name() << " CONFIG_DIR_ACCESS> Accessing directory: " 2895 2705 << " address = " << std::hex << r_config_address.read() … … 2912 2722 "MEMC ERROR in CONFIG_TRT_LOCK state: bad DIR allocation"); 2913 2723 2914 if ( r_alloc_trt_fsm.read() == ALLOC_TRT_CONFIG)2724 if (r_alloc_trt_fsm.read() == ALLOC_TRT_CONFIG) 2915 2725 { 2916 2726 size_t index = 0; 2917 bool wok= not m_trt.full(index);2918 2919 if ( not wok)2727 bool wok = not m_trt.full(index); 2728 2729 if (not wok) 2920 2730 { 2921 2731 r_config_fsm = CONFIG_LOOP; … … 2923 2733 else 2924 2734 { 2925 size_t 2926 size_t 2735 size_t way = r_config_dir_way.read(); 2736 size_t set = m_y[r_config_address.read()]; 2927 2737 2928 2738 // reset dirty bit in DIR … … 2940 2750 2941 2751 r_config_trt_index = index; 2942 r_config_fsm 2752 r_config_fsm = CONFIG_TRT_SET; 2943 2753 } 2944 2754 2945 2755 #if DEBUG_MEMC_CONFIG 2946 if (m_debug)2756 if (m_debug) 2947 2757 std::cout << " <MEMC " << name() << " CONFIG_TRT_LOCK> Access TRT: " 2948 2758 << " wok = " << std::dec << wok … … 2956 2766 // and post a PUT request in TRT 2957 2767 { 2958 assert( 2768 assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and 2959 2769 "MEMC ERROR in CONFIG_TRT_SET state: bad DIR allocation"); 2960 2770 2961 assert( 2771 assert((r_alloc_trt_fsm.read() == ALLOC_TRT_CONFIG) and 2962 2772 "MEMC ERROR in CONFIG_TRT_SET state: bad TRT allocation"); 2963 2773 2964 2774 // read data into cache 2965 size_t 2966 size_t 2775 size_t way = r_config_dir_way.read(); 2776 size_t set = m_y[r_config_address.read()]; 2967 2777 std::vector<data_t> data_vector; 2968 2778 data_vector.clear(); 2969 for (size_t word=0; word<m_words; word++)2970 { 2971 uint32_t data = m_cache_data.read( way, set, word);2972 data_vector.push_back( data);2779 for (size_t word = 0; word < m_words; word++) 2780 { 2781 uint32_t data = m_cache_data.read(way, set, word); 2782 data_vector.push_back(data); 2973 2783 } 2974 2784 … … 2992 2802 2993 2803 #if DEBUG_MEMC_CONFIG 2994 if (m_debug)2804 if (m_debug) 2995 2805 std::cout << " <MEMC " << name() << " CONFIG_TRT_SET> PUT request in TRT:" 2996 2806 << " address = " << std::hex << r_config_address.read() … … 3002 2812 case CONFIG_PUT_REQ: // post PUT request to IXR_CMD_FSM 3003 2813 { 3004 if ( not r_config_to_ixr_cmd_req.read())2814 if (not r_config_to_ixr_cmd_req.read()) 3005 2815 { 3006 2816 r_config_to_ixr_cmd_req = true; … … 3008 2818 3009 2819 // prepare next iteration 3010 r_config_cmd_lines 3011 r_config_address = r_config_address.read() + (m_words<<2);3012 r_config_fsm 2820 r_config_cmd_lines = r_config_cmd_lines.read() - 1; 2821 r_config_address = r_config_address.read() + (m_words << 2); 2822 r_config_fsm = CONFIG_LOOP; 3013 2823 3014 2824 #if DEBUG_MEMC_CONFIG 3015 if (m_debug)2825 if (m_debug) 3016 2826 std::cout << " <MEMC " << name() << " CONFIG_PUT_REQ> post PUT request to IXR_CMD_FSM" 3017 2827 << " / address = " << std::hex << r_config_address.read() << std::endl; … … 3027 2837 // directory if IVT not full. 3028 2838 { 3029 assert( 2839 assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and 3030 2840 "MEMC ERROR in CONFIG_IVT_LOCK state: bad DIR allocation"); 3031 2841 3032 if ( r_alloc_ivt_fsm.read() == ALLOC_IVT_CONFIG)2842 if (r_alloc_ivt_fsm.read() == ALLOC_IVT_CONFIG) 3033 2843 { 3034 2844 size_t set = m_y[(addr_t)(r_config_address.read())]; 3035 2845 size_t way = r_config_dir_way.read(); 3036 2846 3037 if ( r_config_dir_count.read() == 0) // inval DIR and return to LOOP3038 { 3039 m_cache_directory.inval( way, set);2847 if (r_config_dir_count.read() == 0) // inval DIR and return to LOOP 2848 { 2849 m_cache_directory.inval(way, set); 3040 2850 r_config_cmd_lines = r_config_cmd_lines.read() - 1; 3041 r_config_address = r_config_address.read() + (m_words <<2);2851 r_config_address = r_config_address.read() + (m_words << 2); 3042 2852 r_config_fsm = CONFIG_LOOP; 3043 2853 3044 2854 #if DEBUG_MEMC_CONFIG 3045 if (m_debug)2855 if (m_debug) 3046 2856 std::cout << " <MEMC " << name() << " CONFIG_IVT_LOCK>" 3047 2857 << " No copies in L1 : inval DIR entry" << std::endl; … … 3071 2881 index); 3072 2882 3073 if ( wok) // IVT success => inval DIR slot2883 if (wok) // IVT success => inval DIR slot 3074 2884 { 3075 m_cache_directory.inval( way, set);2885 m_cache_directory.inval(way, set); 3076 2886 r_config_ivt_index = index; 3077 2887 config_rsp_lines_incr = true; 3078 if ( broadcast) r_config_fsm = CONFIG_BC_SEND;3079 else 2888 if (broadcast) r_config_fsm = CONFIG_BC_SEND; 2889 else r_config_fsm = CONFIG_INVAL_SEND; 3080 2890 3081 2891 #if DEBUG_MEMC_CONFIG 3082 if (m_debug)2892 if (m_debug) 3083 2893 std::cout << " <MEMC " << name() << " CONFIG_IVT_LOCK>" 3084 2894 << " Inval DIR entry and register inval in IVT" … … 3092 2902 3093 2903 #if DEBUG_MEMC_CONFIG 3094 if (m_debug)2904 if (m_debug) 3095 2905 std::cout << " <MEMC " << name() << " CONFIG_IVT_LOCK>" 3096 2906 << " IVT full : release DIR & IVT locks and retry" << std::endl; … … 3104 2914 case CONFIG_BC_SEND: // Post a broadcast inval request to CC_SEND FSM 3105 2915 { 3106 if (not r_config_to_cc_send_multi_req.read() and3107 not r_config_to_cc_send_brdcast_req.read() 2916 if (not r_config_to_cc_send_multi_req.read() and 2917 not r_config_to_cc_send_brdcast_req.read()) 3108 2918 { 3109 2919 // post bc inval request … … 3119 2929 3120 2930 #if DEBUG_MEMC_CONFIG 3121 if (m_debug)2931 if (m_debug) 3122 2932 std::cout << " <MEMC " << name() << " CONFIG_BC_SEND>" 3123 2933 << " Post a broadcast inval request to CC_SEND FSM" … … 3130 2940 case CONFIG_INVAL_SEND: // Post a multi inval request to CC_SEND FSM 3131 2941 { 3132 if (not r_config_to_cc_send_multi_req.read() and2942 if (not r_config_to_cc_send_multi_req.read() and 3133 2943 not r_config_to_cc_send_brdcast_req.read() ) 3134 2944 { … … 3143 2953 config_to_cc_send_fifo_put = true; 3144 2954 3145 if ( 2955 if (r_config_dir_count.read() == 1 ) // one copy 3146 2956 { 3147 2957 // prepare next iteration … … 3156 2966 3157 2967 #if DEBUG_MEMC_CONFIG 3158 if (m_debug)2968 if (m_debug) 3159 2969 std::cout << " <MEMC " << name() << " CONFIG_INVAL_SEND>" 3160 2970 << " Post multi inval request to CC_SEND FSM" … … 3169 2979 case CONFIG_HEAP_REQ: // Try to get access to Heap 3170 2980 { 3171 if ( 3172 { 3173 r_config_fsm 2981 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_CONFIG ) 2982 { 2983 r_config_fsm = CONFIG_HEAP_SCAN; 3174 2984 r_config_heap_next = r_config_dir_ptr.read(); 3175 2985 } 3176 2986 3177 2987 #if DEBUG_MEMC_CONFIG 3178 if (m_debug)2988 if (m_debug) 3179 2989 std::cout << " <MEMC " << name() << " CONFIG_HEAP_REQ>" 3180 2990 << " Requesting HEAP lock" << std::endl; … … 3193 3003 config_to_cc_send_fifo_put = true; 3194 3004 3195 if ( m_config_to_cc_send_inst_fifo.wok()) // inval request accepted3005 if (m_config_to_cc_send_inst_fifo.wok()) // inval request accepted 3196 3006 { 3197 3007 r_config_heap_next = entry.next; 3198 if ( last_copy) r_config_fsm = CONFIG_HEAP_LAST;3008 if (last_copy) r_config_fsm = CONFIG_HEAP_LAST; 3199 3009 } 3200 3010 3201 3011 #if DEBUG_MEMC_CONFIG 3202 if (m_debug)3012 if (m_debug) 3203 3013 std::cout << " <MEMC " << name() << " CONFIG_HEAP_SCAN>" 3204 3014 << " Post multi inval request to CC_SEND FSM" … … 3217 3027 last_entry.owner.inst = false; 3218 3028 3219 if ( m_heap.is_full())3029 if (m_heap.is_full()) 3220 3030 { 3221 3031 last_entry.next = r_config_dir_ptr.read(); … … 3227 3037 } 3228 3038 3229 m_heap.write_free_ptr( 3230 m_heap.write( 3039 m_heap.write_free_ptr(r_config_dir_ptr.read() ); 3040 m_heap.write(r_config_heap_next.read(), last_entry ); 3231 3041 3232 3042 // prepare next iteration 3233 r_config_cmd_lines 3234 r_config_address 3235 r_config_fsm 3043 r_config_cmd_lines = r_config_cmd_lines.read() - 1; 3044 r_config_address = r_config_address.read() + (m_words<<2); 3045 r_config_fsm = CONFIG_LOOP; 3236 3046 3237 3047 #if DEBUG_MEMC_CONFIG 3238 if (m_debug)3048 if (m_debug) 3239 3049 std::cout << " <MEMC " << name() << " CONFIG_HEAP_LAST>" 3240 3050 << " Heap housekeeping" << std::endl; … … 3272 3082 case READ_IDLE: // waiting a read request 3273 3083 { 3274 if (m_cmd_read_addr_fifo.rok())3084 if (m_cmd_read_addr_fifo.rok()) 3275 3085 { 3276 3086 … … 3280 3090 3281 3091 #if DEBUG_MEMC_READ 3282 if (m_debug)3092 if (m_debug) 3283 3093 std::cout << " <MEMC " << name() << " READ_IDLE> Read request" 3284 3094 << " : address = " << std::hex << m_cmd_read_addr_fifo.read() … … 3298 3108 case READ_DIR_REQ: // Get the lock to the directory 3299 3109 { 3300 if (r_alloc_dir_fsm.read() == ALLOC_DIR_READ)3110 if (r_alloc_dir_fsm.read() == ALLOC_DIR_READ) 3301 3111 { 3302 3112 r_read_fsm = READ_DIR_LOCK; 3303 m_cpt_read_fsm_n_dir_lock++;3304 3113 } 3305 3114 3306 3115 #if DEBUG_MEMC_READ 3307 if (m_debug)3116 if (m_debug) 3308 3117 std::cout << " <MEMC " << name() << " READ_DIR_REQ> Requesting DIR lock " << std::endl; 3309 3118 #endif 3310 3311 m_cpt_read_fsm_dir_lock++;3312 3313 3119 break; 3314 3120 } … … 3323 3129 DirectoryEntry entry = 3324 3130 m_cache_directory.read(m_cmd_read_addr_fifo.read(), way); 3325 if (((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) and not r_read_ll_done.read()) // access the global table ONLY when we have an LL cmd3326 { 3327 r_read_ll_key 3131 if (((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) and not r_read_ll_done.read()) // access the global table ONLY when we have an LL cmd 3132 { 3133 r_read_ll_key = m_llsc_table.ll(m_cmd_read_addr_fifo.read()); 3328 3134 /**//*std::cout << "MEMCACHE : from proc " << m_cmd_read_srcid_fifo.read() 3329 3135 << " | @ " << std::hex << m_cmd_read_addr_fifo.read() … … 3331 3137 r_read_ll_done = true; 3332 3138 } 3333 3334 //bool s_getm_hit = m_cmd_read_pktid_fifo.read() & 0x8;3335 3139 3336 3140 r_read_is_cnt = entry.is_cnt; … … 3350 3154 bool cached_read = ((m_cmd_read_pktid_fifo.read() & 0x7) != 0) and ((m_cmd_read_pktid_fifo.read() & 0x7) != 0x2) and ((m_cmd_read_pktid_fifo.read() & 0x7) != 0x6); 3351 3155 3352 if (entry.state == ENTRY_SHARED or entry.state == ENTRY_EXCLUSIVE) // hit3353 { 3354 if ( 3156 if (entry.state == ENTRY_SHARED or entry.state == ENTRY_EXCLUSIVE) // hit 3157 { 3158 if ((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_WRITE ) 3355 3159 { 3356 3160 // Invalid the line in the others processors and put the line in trt with data. 3357 if (entry.count == 0)3161 if (entry.count == 0) 3358 3162 // ((entry.count == 1) and not entry.is_cnt and (entry.state == ENTRY_SHARED) and (entry.owner.srcid == m_cmd_read_srcid_fifo.read())) or 3359 3163 // (entry.count == 1 and entry.is_cnt and entry.state == ENTRY_SHARED and s_getm_hit)) … … 3363 3167 else 3364 3168 { 3365 if ((entry.state == ENTRY_EXCLUSIVE) and (entry.owner.srcid == m_cmd_read_srcid_fifo.read()))3169 if ((entry.state == ENTRY_EXCLUSIVE) and (entry.owner.srcid == m_cmd_read_srcid_fifo.read())) 3366 3170 { 3367 3171 std::cout <<"exclusive line && srcid != read srcid "<< std::endl; … … 3372 3176 3373 3177 addr_t min = m_cmd_read_addr_fifo.read(); 3374 addr_t max = m_cmd_read_addr_fifo.read() + m_cmd_read_length_fifo.read() *4;3178 addr_t max = m_cmd_read_addr_fifo.read() + m_cmd_read_length_fifo.read() * 4; 3375 3179 m_llsc_table.sw(min, max); 3376 3180 } 3377 3181 else // a read miss request 3378 3182 { 3379 if ( 3183 if (entry.state == ENTRY_SHARED or entry.count == 0) 3380 3184 { 3381 if (entry.is_cnt or (entry.count == 0) or (not cached_read))3185 if (entry.is_cnt or (entry.count == 0) or (not cached_read)) 3382 3186 { 3383 3187 r_read_fsm = READ_DIR_HIT; … … 3388 3192 } 3389 3193 } 3390 else if ( entry.state == ENTRY_EXCLUSIVE)3194 else if (entry.state == ENTRY_EXCLUSIVE) 3391 3195 { 3392 3196 r_read_fsm = READ_IVT_UPDT_LOCK; … … 3394 3198 } 3395 3199 } 3396 else if(entry.state == ENTRY_LOCKED) // the line is locked, can't use it at this time 3397 { 3398 m_cpt_read_locked_rb ++; 3200 else if (entry.state == ENTRY_LOCKED) // the line is locked, can't use it at this time 3201 { 3399 3202 r_read_fsm = READ_WAIT; 3400 3203 } … … 3405 3208 3406 3209 #if DEBUG_MEMC_READ 3407 if (m_debug)3210 if (m_debug) 3408 3211 { 3409 3212 std::cout << " <MEMC " << name() << " READ_DIR_LOCK> Accessing directory: " … … 3415 3218 << " / is_inst = " << entry.owner.inst 3416 3219 << " / is_cnt = " << entry.is_cnt << std::endl; 3417 if ((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) std::cout << " / LL access" << std::endl;3220 if ((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) std::cout << " / LL access" << std::endl; 3418 3221 else std::cout << std::endl; 3419 3222 } … … 3438 3241 size_t ivt_send_count = 0; 3439 3242 3440 if (m_ivt.is_full() or // not need to check match inval, because of the LOCKED STATE3243 if (m_ivt.is_full() or // not need to check match inval, because of the LOCKED STATE 3441 3244 r_read_to_cc_send_multi_req.read() or 3442 3245 r_read_to_cc_send_brdcast_req.read() or … … 3446 3249 r_read_fsm = READ_WAIT; 3447 3250 #if DEBUG_MEMC_READ 3448 if (m_debug)3251 if (m_debug) 3449 3252 { 3450 3253 std::cout … … 3475 3278 //r_read_to_cc_send_is_shared = r_read_state.read() == ENTRY_SHARED; 3476 3279 3477 if (r_read_need_block.read())3280 if (r_read_need_block.read()) 3478 3281 { 3479 3282 r_read_to_cleanup_nline = nline; … … 3502 3305 index); 3503 3306 3504 if (not_last_multi_req )3307 if (not_last_multi_req ) 3505 3308 { 3506 3309 r_read_fsm = READ_INVAL_HEAP_REQ; … … 3512 3315 } 3513 3316 3514 if(multi_req)3515 m_cpt_getm_minval ++;3516 else3317 // <Activity counters> 3318 if (!multi_req) 3319 { 3517 3320 m_cpt_getm_broadcast ++; 3321 } 3322 // </Activity counters> 3518 3323 #if DEBUG_MEMC_READ 3519 if (m_debug)3324 if (m_debug) 3520 3325 { 3521 3326 std::cout … … 3534 3339 case READ_INVAL_HEAP_REQ: 3535 3340 { 3536 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ )3341 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ ) 3537 3342 { 3538 3343 r_read_fsm = READ_INVAL_HEAP_ERASE; 3539 3344 } 3540 3345 #if DEBUG_MEMC_READ 3541 if (m_debug)3346 if (m_debug) 3542 3347 std::cout << " <MEMC " << name() << " READ_INVAL_HEAP_REQ>" 3543 3348 << " Requesting HEAP lock" << std::endl; … … 3548 3353 case READ_INVAL_HEAP_ERASE: 3549 3354 { 3550 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)3355 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) 3551 3356 { 3552 3357 HeapEntry entry = m_heap.read(r_read_next_ptr.read()); … … 3557 3362 r_read_next_ptr = entry.next; 3558 3363 3559 if (entry.next == r_read_next_ptr.read()) // last copy3364 if (entry.next == r_read_next_ptr.read()) // last copy 3560 3365 { 3561 3366 r_read_to_cc_send_multi_req = true; … … 3568 3373 3569 3374 #if DEBUG_MEMC_READ 3570 if (m_debug)3375 if (m_debug) 3571 3376 std::cout << " <MEMC " << name() << " READ_HEAP_ERASE>" 3572 3377 << " Erase copy:" … … 3580 3385 case READ_INVAL_HEAP_LAST: // last copy 3581 3386 { 3582 if (r_alloc_heap_fsm.read() != ALLOC_HEAP_READ)3387 if (r_alloc_heap_fsm.read() != ALLOC_HEAP_READ) 3583 3388 { 3584 3389 std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_INVAL_HEAP_LAST" … … 3591 3396 last_entry.owner.srcid = 0; 3592 3397 last_entry.owner.inst = false; 3593 if (m_heap.is_full())3398 if (m_heap.is_full()) 3594 3399 { 3595 3400 last_entry.next = r_read_next_ptr.read(); … … 3608 3413 3609 3414 #if DEBUG_MEMC_READ 3610 if (m_debug)3415 if (m_debug) 3611 3416 std::cout << " <MEMC " << name() << " READ_INVAL_HEAP_LAST>" 3612 3417 << " Heap housekeeping" << std::endl; … … 3622 3427 addr_t nline = m_nline[(addr_t)(m_cmd_read_addr_fifo.read())]; 3623 3428 size_t set = m_y[(addr_t)(m_cmd_read_addr_fifo.read())]; 3624 if (m_ivt.is_full() or3429 if (m_ivt.is_full() or 3625 3430 r_read_to_cc_send_multi_req.read() or 3626 3431 r_read_to_cc_send_brdcast_req.read() or … … 3629 3434 r_read_fsm = READ_WAIT; 3630 3435 #if DEBUG_MEMC_READ 3631 if (m_debug)3436 if (m_debug) 3632 3437 { 3633 3438 std::cout … … 3652 3457 m_cache_directory.write(set, r_read_way.read(), entry); 3653 3458 3654 if (r_read_need_block.read())3459 if (r_read_need_block.read()) 3655 3460 { 3656 3461 r_read_to_multi_ack_nline = nline; … … 3687 3492 3688 3493 #if DEBUG_MEMC_READ 3689 if (m_debug)3494 if (m_debug) 3690 3495 { 3691 3496 std::cout … … 3709 3514 r_read_fsm = READ_DIR_REQ; 3710 3515 #if DEBUG_MEMC_READ 3711 if (m_debug)3516 if (m_debug) 3712 3517 { 3713 3518 std::cout … … 3747 3552 DirectoryEntry entry; 3748 3553 3749 if (inst_read)3554 if (inst_read) 3750 3555 { 3751 3556 entry.state = ENTRY_SHARED; 3752 3557 } 3753 else if (is_getm)3558 else if (is_getm) 3754 3559 { 3755 3560 entry.state = ENTRY_EXCLUSIVE; … … 3761 3566 3762 3567 //entry.cache_coherent = r_read_coherent.read() or inst_read or (!(cached_read)) or (r_read_copy.read() != m_cmd_read_srcid_fifo.read()); 3763 if (entry.state == ENTRY_SHARED) r_read_shared = true;3568 if (entry.state == ENTRY_SHARED) r_read_shared = true; 3764 3569 else r_read_shared = false; 3765 3570 entry.is_cnt = is_cnt; … … 3768 3573 entry.lock = r_read_lock.read(); 3769 3574 entry.ptr = r_read_ptr.read(); 3770 if (cached_read) // Cached read => we must update the copies3771 { 3772 if (is_getm)3575 if (cached_read) // Cached read => we must update the copies 3576 { 3577 if (is_getm) 3773 3578 { 3774 3579 entry.owner.srcid = m_cmd_read_srcid_fifo.read(); … … 3777 3582 3778 3583 } 3779 else if (!is_cnt) // Not counter mode3584 else if (!is_cnt) // Not counter mode 3780 3585 { 3781 3586 entry.owner.srcid = m_cmd_read_srcid_fifo.read(); … … 3798 3603 3799 3604 #if DEBUG_MEMC_READ 3800 if (m_debug)3605 if (m_debug) 3801 3606 std::cout << " <MEMC " << name() << " READ_DIR_HIT> Update directory entry:" 3802 3607 << " addr = " << std::hex << m_cmd_read_addr_fifo.read() … … 3818 3623 case READ_HEAP_REQ: // Get the lock to the HEAP directory 3819 3624 { 3820 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)3625 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) 3821 3626 { 3822 3627 r_read_fsm = READ_HEAP_LOCK; 3823 m_cpt_read_fsm_n_heap_lock++;3824 3628 } 3825 3629 3826 3630 #if DEBUG_MEMC_READ 3827 if (m_debug)3631 if (m_debug) 3828 3632 std::cout << " <MEMC " << name() << " READ_HEAP_REQ>" 3829 3633 << " Requesting HEAP lock " << std::endl; 3830 3634 #endif 3831 3832 m_cpt_read_fsm_heap_lock++;3833 3834 3635 break; 3835 3636 } … … 3839 3640 // and prepare the HEAP update 3840 3641 { 3841 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)3642 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) 3842 3643 { 3843 3644 // enter counter mode when we reach the limit of copies or the heap is full … … 3862 3663 r_read_shared = true; //ack to cache L1 with shared state 3863 3664 3864 if (not go_cnt) // Not entering counter mode3665 if (not go_cnt) // Not entering counter mode 3865 3666 { 3866 3667 entry.owner.srcid = r_read_copy.read(); … … 3878 3679 3879 3680 // prepare the heap update (add an entry, or clear the linked list) 3880 if (not go_cnt) // not switching to counter mode3681 if (not go_cnt) // not switching to counter mode 3881 3682 { 3882 3683 // We test if the next free entry in the heap is the last … … 3889 3690 else // switching to counter mode 3890 3691 { 3891 if (r_read_count.read() >1) // heap must be cleared3692 if (r_read_count.read() >1) // heap must be cleared 3892 3693 { 3893 3694 HeapEntry next_entry = m_heap.read(r_read_ptr.read()); … … 3895 3696 m_heap.write_free_ptr(r_read_ptr.read()); 3896 3697 3897 if (next_entry.next == r_read_ptr.read()) // last entry3698 if (next_entry.next == r_read_ptr.read()) // last entry 3898 3699 { 3899 3700 r_read_fsm = READ_HEAP_LAST; // erase the entry … … 3912 3713 3913 3714 #if DEBUG_MEMC_READ 3914 if (m_debug)3715 if (m_debug) 3915 3716 std::cout << " <MEMC " << name() << " READ_HEAP_LOCK> Update directory:" 3916 3717 << " tag = " << std::hex << entry.tag … … 3932 3733 case READ_HEAP_WRITE: // add an entry in the heap 3933 3734 { 3934 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)3735 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) 3935 3736 { 3936 3737 HeapEntry heap_entry; … … 3938 3739 heap_entry.owner.inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); 3939 3740 3940 if (r_read_count.read() == 1) // creation of a new linked list3741 if (r_read_count.read() == 1) // creation of a new linked list 3941 3742 { 3942 3743 heap_entry.next = m_heap.next_free_ptr(); … … 3948 3749 m_heap.write_free_entry(heap_entry); 3949 3750 m_heap.write_free_ptr(r_read_next_ptr.read()); 3950 if (r_read_last_free.read()) m_heap.set_full();3751 if (r_read_last_free.read()) m_heap.set_full(); 3951 3752 3952 3753 r_read_fsm = READ_RSP; 3953 3754 3954 3755 #if DEBUG_MEMC_READ 3955 if (m_debug)3756 if (m_debug) 3956 3757 std::cout << " <MEMC " << name() << " READ_HEAP_WRITE> Add an entry in the heap:" 3957 3758 << " owner_id = " << std::hex << heap_entry.owner.srcid … … 3970 3771 case READ_HEAP_ERASE: 3971 3772 { 3972 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)3773 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) 3973 3774 { 3974 3775 HeapEntry next_entry = m_heap.read(r_read_ptr.read()); 3975 if (next_entry.next == r_read_ptr.read())3776 if (next_entry.next == r_read_ptr.read()) 3976 3777 { 3977 3778 r_read_fsm = READ_HEAP_LAST; … … 3995 3796 case READ_HEAP_LAST: 3996 3797 { 3997 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)3798 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) 3998 3799 { 3999 3800 HeapEntry last_entry; … … 4001 3802 last_entry.owner.inst = false; 4002 3803 4003 if (m_heap.is_full())3804 if (m_heap.is_full()) 4004 3805 { 4005 3806 last_entry.next = r_read_ptr.read(); … … 4024 3825 case READ_RSP: // request the TGT_RSP FSM to return data 4025 3826 { 4026 if (not r_read_to_tgt_rsp_req.read())3827 if (not r_read_to_tgt_rsp_req.read()) 4027 3828 { 4028 3829 for(size_t i=0 ; i<m_words ; i++) r_read_to_tgt_rsp_data[i] = r_read_data[i]; … … 4046 3847 4047 3848 #if DEBUG_MEMC_READ 4048 if (m_debug)3849 if (m_debug) 4049 3850 std::cout << " <MEMC " << name() << " READ_RSP> Request TGT_RSP FSM to return data:" 4050 3851 << " rsrcid = " << std::hex << m_cmd_read_srcid_fifo.read() … … 4058 3859 case READ_TRT_LOCK: // read miss : check the Transaction Table 4059 3860 { 4060 if (r_alloc_trt_fsm.read() == ALLOC_TRT_READ)3861 if (r_alloc_trt_fsm.read() == ALLOC_TRT_READ) 4061 3862 { 4062 3863 size_t index = 0; … … 4067 3868 bool wok = !m_trt.full(index); 4068 3869 4069 //if(hit_write) m_trt.print(index_write); 4070 if(hit_read or !wok or hit_write) // missing line already requested or no space 4071 { 4072 if(!wok) 3870 //if (hit_write) m_trt.print(index_write); 3871 if (hit_read or !wok or hit_write) // missing line already requested or no space 3872 { 3873 // <Activity counters> 3874 if (!wok) 4073 3875 { 4074 3876 m_cpt_trt_full++; 4075 3877 } 4076 if(hit_read or hit_write) m_cpt_trt_rb++; 3878 if (hit_read or hit_write) 3879 { 3880 m_cpt_trt_rb++; 3881 } 3882 // </Activity counters> 4077 3883 r_read_fsm = READ_IDLE; 4078 3884 } 4079 else // missing line is requested to the XRAM 4080 { 4081 4082 if ( (m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_WRITE ) 4083 m_cpt_getm_miss ++; 4084 else 3885 else // missing line is requested to the XRAM 3886 { 3887 3888 // <Activity counters> 3889 if ((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_WRITE) { 3890 m_cpt_getm_miss++; 3891 } 3892 else { 4085 3893 m_cpt_read_miss++; 3894 } 3895 // </Activity counters> 4086 3896 4087 3897 r_read_trt_index = index; … … 4090 3900 4091 3901 #if DEBUG_MEMC_READ 4092 if (m_debug)3902 if (m_debug) 4093 3903 std::cout << " <MEMC " << name() << " READ_TRT_LOCK> Check TRT:" 4094 3904 << " hit_read = " << hit_read 4095 3905 << " / hit_write = " << hit_write 4096 3906 << " / full = " << !wok << std::endl; 4097 m_cpt_read_fsm_n_trt_lock++; 4098 #endif 4099 } 4100 4101 m_cpt_read_fsm_trt_lock++; 4102 3907 #endif 3908 } 4103 3909 break; 4104 3910 } … … 4107 3913 case READ_TRT_SET: // register get transaction in TRT 4108 3914 { 4109 if (r_alloc_trt_fsm.read() == ALLOC_TRT_READ)3915 if (r_alloc_trt_fsm.read() == ALLOC_TRT_READ) 4110 3916 { 4111 3917 m_trt.set(r_read_trt_index.read(), … … 4123 3929 4124 3930 #if DEBUG_MEMC_READ 4125 if (m_debug)3931 if (m_debug) 4126 3932 std::cout << " <MEMC " << name() << " READ_TRT_SET> Set a GET in TGT:" 4127 3933 << " address = " << std::hex << m_cmd_read_addr_fifo.read() … … 4136 3942 case READ_TRT_REQ: // consume the read request in FIFO and send it to IXR_CMD_FSM 4137 3943 { 4138 if (not r_read_to_ixr_cmd_req)3944 if (not r_read_to_ixr_cmd_req) 4139 3945 { 4140 3946 cmd_read_fifo_get = true; … … 4145 3951 4146 3952 #if DEBUG_MEMC_READ 4147 if (m_debug)3953 if (m_debug) 4148 3954 std::cout << " <MEMC " << name() << " READ_TRT_REQ> Request GET transaction for address " 4149 3955 << std::hex << m_cmd_read_addr_fifo.read() << std::endl; … … 4217 4023 for(size_t word=0 ; word<m_words ; word++) 4218 4024 { 4219 if (word == index) r_write_be[word] = m_cmd_write_be_fifo.read();4025 if (word == index) r_write_be[word] = m_cmd_write_be_fifo.read(); 4220 4026 else r_write_be[word] = 0x0; 4221 4027 } … … 4231 4037 4232 4038 #if DEBUG_MEMC_WRITE 4233 if (m_debug)4039 if (m_debug) 4234 4040 std::cout << " <MEMC " << name() << " WRITE_IDLE> Write request " 4235 4041 << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read() … … 4295 4101 if (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE ) 4296 4102 { 4297 m_cpt_write_fsm_n_dir_lock ++;4298 4103 break; 4299 4104 } … … 4326 4131 } 4327 4132 4328 m_cpt_write_fsm_dir_lock ++;4329 4330 4133 #if DEBUG_MEMC_WRITE 4331 if (m_debug)4134 if (m_debug) 4332 4135 std::cout << " <MEMC " << name() << " WRITE_DIR_REQ> Requesting DIR lock " 4333 4136 << std::endl; … … 4344 4147 DirectoryEntry entry(m_cache_directory.read(r_write_address.read(), way)); 4345 4148 4346 if (entry.state != ENTRY_INVALID) // hit4149 if (entry.state != ENTRY_INVALID) // hit 4347 4150 { 4348 4151 // copy directory entry in local buffer in case of hit … … 4357 4160 r_write_state = entry.state; 4358 4161 4359 if (r_write_pktid == TYPE_DATA_UNC and entry.count != 0)4162 if (r_write_pktid == TYPE_DATA_UNC and entry.count != 0) 4360 4163 { 4361 4164 assert( false && " found a copy for an uncached write quest"); … … 4363 4166 else 4364 4167 { 4365 if (not entry.count and (entry.state != ENTRY_LOCKED))4168 if (not entry.count and (entry.state != ENTRY_LOCKED)) 4366 4169 { 4367 4170 r_write_fsm = WRITE_DIR_HIT; … … 4369 4172 else if (entry.state == ENTRY_LOCKED)//the line is locked 4370 4173 { 4371 m_cpt_write_locked_rb ++;4372 4174 r_write_fsm = WRITE_WAIT; 4373 4175 } … … 4384 4186 4385 4187 #if DEBUG_MEMC_WRITE 4386 if (m_debug)4188 if (m_debug) 4387 4189 { 4388 4190 std::cout << " <MEMC " << name() << " WRITE_DIR_LOCK> Check the directory: " … … 4391 4193 << " / count = " << entry.count 4392 4194 << " / is_cnt = " << entry.is_cnt ; 4393 if ((r_write_pktid.read() & 0x7) == TYPE_SC)4195 if ((r_write_pktid.read() & 0x7) == TYPE_SC) 4394 4196 std::cout << " / SC access" << std::endl; 4395 4197 else … … 4439 4241 4440 4242 #if DEBUG_MEMC_WRITE 4441 if (m_debug)4243 if (m_debug) 4442 4244 { 4443 4245 std::cout << " <MEMC " << name() … … 4451 4253 case WRITE_HEAP_REQ: // Get the lock to the HEAP directory 4452 4254 { 4453 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE)4255 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE) 4454 4256 { 4455 4257 r_write_fsm = WRITE_HEAP_ERASE; 4456 m_cpt_write_fsm_n_heap_lock++;4457 4258 } 4458 4259 4459 4260 #if DEBUG_MEMC_WRITE 4460 if (m_debug)4261 if (m_debug) 4461 4262 std::cout << " <MEMC " << name() << " WRITE_HEAP_REQ>" 4462 4263 << " Requesting HEAP lock " << std::endl; 4463 4264 #endif 4464 4465 m_cpt_write_fsm_heap_lock++;4466 4467 4265 break; 4468 4266 } … … 4471 4269 case WRITE_HEAP_ERASE: // get access to heap 4472 4270 { 4473 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE)4271 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE) 4474 4272 { 4475 4273 HeapEntry entry = m_heap.read(r_write_next_ptr.read()); … … 4478 4276 write_to_cc_send_fifo_inst = entry.owner.inst; 4479 4277 write_to_cc_send_fifo_put = true; 4480 if (m_write_to_cc_send_inst_fifo.wok())4278 if (m_write_to_cc_send_inst_fifo.wok()) 4481 4279 { 4482 4280 r_write_next_ptr = entry.next; 4483 if (entry.next == r_write_next_ptr.read()) // last copy4281 if (entry.next == r_write_next_ptr.read()) // last copy 4484 4282 { 4485 4283 r_write_to_cc_send_multi_req = true; … … 4497 4295 4498 4296 #if DEBUG_MEMC_WRITE 4499 if (m_debug)4297 if (m_debug) 4500 4298 std::cout << " <MEMC " << name() 4501 4299 << " WRITE_HEAP_LOCK> Get acces to the HEAP" << std::endl; 4502 4300 #endif 4503 4301 } 4504 4505 m_cpt_write_fsm_heap_lock++;4506 4507 4302 break; 4508 4303 } … … 4510 4305 case WRITE_HEAP_LAST: // last copy 4511 4306 { 4512 if (r_alloc_heap_fsm.read() != ALLOC_HEAP_WRITE)4307 if (r_alloc_heap_fsm.read() != ALLOC_HEAP_WRITE) 4513 4308 { 4514 4309 std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_HEAP_LAST" … … 4521 4316 last_entry.owner.srcid = 0; 4522 4317 last_entry.owner.inst = false; 4523 if (m_heap.is_full())4318 if (m_heap.is_full()) 4524 4319 { 4525 4320 last_entry.next = r_write_next_ptr.read(); … … 4537 4332 4538 4333 #if DEBUG_MEMC_XRAM_RSP 4539 if (m_debug)4334 if (m_debug) 4540 4335 std::cout << " <MEMC " << name() << " WRITE_HEAP_LAST>" 4541 4336 << " Heap housekeeping" << std::endl; … … 4592 4387 for(size_t word=0 ; word<m_words ; word++) 4593 4388 { 4594 if (word == index) r_write_be[word] = m_cmd_write_be_fifo.read();4389 if (word == index) r_write_be[word] = m_cmd_write_be_fifo.read(); 4595 4390 else r_write_be[word] = 0x0; 4596 4391 } 4597 4392 4598 if (m_cmd_write_eop_fifo.read())4393 if (m_cmd_write_eop_fifo.read()) 4599 4394 { 4600 4395 r_write_fsm = WRITE_DIR_REQ; … … 4607 4402 4608 4403 #if DEBUG_MEMC_WRITE 4609 if (m_debug)4404 if (m_debug) 4610 4405 { 4611 4406 std::cout << " <MEMC " << name() << " WRITE_RSP> Post a request to TGT_RSP FSM" … … 4614 4409 << " : sc_fail= " << std::hex << r_write_sc_fail.read() 4615 4410 << std::endl; 4616 if (m_cmd_write_addr_fifo.rok())4411 if (m_cmd_write_addr_fifo.rok()) 4617 4412 { 4618 4413 std::cout << " New Write request: " … … 4631 4426 case WRITE_MISS_TRT_LOCK: // Miss : check Transaction Table 4632 4427 { 4633 if (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE)4428 if (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) 4634 4429 { 4635 4430 size_t hit_index = 0; … … 4640 4435 bool wok = not m_trt.full(wok_index); 4641 4436 #if DEBUG_MEMC_WRITE 4642 if (m_debug)4437 if (m_debug) 4643 4438 std::cout << " <MEMC " << name() << " WRITE_MISS_TRT_LOCK> Check the TRT" 4644 4439 << "hit read =" << hit_read … … 4649 4444 4650 4445 // wait an empty entry in TRT 4651 if (not hit_read and (not wok or hit_write))4446 if (not hit_read and (not wok or hit_write)) 4652 4447 { 4653 4448 r_write_fsm = WRITE_WAIT; 4449 // <Activity counters> 4654 4450 m_cpt_trt_full++; 4655 4451 // </Activity counters> 4656 4452 break; 4657 4453 } … … 4668 4464 r_write_trt_index = hit_index; 4669 4465 r_write_fsm = WRITE_MISS_TRT_DATA; 4466 // <Activity counters> 4670 4467 m_cpt_write_miss++; 4468 // </Activity counters> 4671 4469 break; 4672 4470 } … … 4676 4474 r_write_trt_index = wok_index; 4677 4475 r_write_fsm = WRITE_MISS_TRT_SET; 4476 // <Activity counters> 4678 4477 m_cpt_write_miss++; 4478 // </Activity counters> 4679 4479 break; 4680 4480 } 4681 4481 4682 m_cpt_write_fsm_n_trt_lock ++;4683 4482 assert(false && "VCI_MEM_CACHE ERROR: this part must not be reached"); 4684 4483 } … … 4692 4491 4693 4492 #if DEBUG_MEMC_WRITE 4694 if (m_debug)4493 if (m_debug) 4695 4494 std::cout << " <MEMC " << name() << " WRITE_WAIT> Releases the locks before retry" << std::endl; 4696 4495 #endif … … 4702 4501 case WRITE_MISS_TRT_SET: // register a new transaction in TRT (Write Buffer) 4703 4502 { 4704 if (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE)4503 if (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) 4705 4504 { 4706 4505 std::vector<be_t> be_vector; … … 4727 4526 4728 4527 #if DEBUG_MEMC_WRITE 4729 if (m_debug)4528 if (m_debug) 4730 4529 std::cout << " <MEMC " << name() << " WRITE_MISS_TRT_SET> Set a new entry in TRT" << std::endl; 4731 4530 #endif … … 4737 4536 case WRITE_MISS_TRT_DATA: // update an entry in TRT (used as a Write Buffer) 4738 4537 { 4739 if (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE)4538 if (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) 4740 4539 { 4741 4540 std::vector<be_t> be_vector; … … 4754 4553 4755 4554 #if DEBUG_MEMC_WRITE 4756 if (m_debug)4555 if (m_debug) 4757 4556 std::cout << " <MEMC " << name() << " WRITE_MISS_TRT_DATA> Modify an existing entry in TRT" << std::endl; 4758 4557 #endif … … 4764 4563 case WRITE_MISS_XRAM_REQ: // send a GET request to IXR_CMD FSM 4765 4564 { 4766 if (not r_write_to_ixr_cmd_req.read())4565 if (not r_write_to_ixr_cmd_req.read()) 4767 4566 { 4768 4567 r_write_to_ixr_cmd_req = true; … … 4771 4570 4772 4571 #if DEBUG_MEMC_WRITE 4773 if (m_debug)4572 if (m_debug) 4774 4573 std::cout << " <MEMC " << name() 4775 4574 << " WRITE_MISS_XRAM_REQ> Post a GET request to the" … … 4796 4595 // (r_write_inval_trt_send.read() or not r_write_to_cleanup_req.read()); 4797 4596 4798 if (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE)4597 if (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) 4799 4598 { 4800 4599 bool wok = false; … … 4810 4609 //r_write_ivt_index = index; 4811 4610 4812 if (not ivt_full and cc_send_valid) //avoid to deadlock, we make sure that we can send cc_send request.4611 if (not ivt_full and cc_send_valid) //avoid to deadlock, we make sure that we can send cc_send request. 4813 4612 { 4814 4613 wok = m_ivt.set(false, // it's an inval transaction … … 4824 4623 index); 4825 4624 4826 if(is_brdcast) 4827 m_cpt_write_broadcast ++; 4828 else 4829 m_cpt_write_minval ++; 4625 // <Activity counters> 4626 if (is_brdcast) 4627 { 4628 m_cpt_write_broadcast++; 4629 } 4630 // </Activity counters> 4631 4830 4632 #if DEBUG_MEMC_WRITE 4831 if (m_debug and wok )4633 if (m_debug and wok ) 4832 4634 std::cout << " <MEMC " << name() << " WRITE_INVAL_IVT_LOCK> Register broadcast inval in IVT" 4833 4635 << "ivt index = " << index … … 4856 4658 { 4857 4659 4858 if (r_write_state.read() == ENTRY_SHARED)4660 if (r_write_state.read() == ENTRY_SHARED) 4859 4661 { 4860 4662 m_cache_data.write(way, set, word, r_write_data[word].read(), r_write_be[word].read()); … … 4880 4682 case WRITE_INVAL_CC_SEND: // Post a coherence broadcast request to CC_SEND FSM 4881 4683 { 4882 if (not r_write_to_cc_send_multi_req.read() and4684 if (not r_write_to_cc_send_multi_req.read() and 4883 4685 not r_write_to_cc_send_brdcast_req.read()) 4884 4686 { … … 4894 4696 r_write_next_ptr = r_write_ptr.read(); 4895 4697 4896 if (r_write_state.read() == ENTRY_EXCLUSIVE)4698 if (r_write_state.read() == ENTRY_EXCLUSIVE) 4897 4699 { 4898 4700 r_write_to_cleanup_req = true; … … 4900 4702 } 4901 4703 4902 if (not last_multi_inval and multi_inval)4704 if (not last_multi_inval and multi_inval) 4903 4705 { 4904 4706 r_write_fsm = WRITE_HEAP_REQ; … … 4909 4711 } 4910 4712 #if DEBUG_MEMC_WRITE 4911 if (m_debug)4713 if (m_debug) 4912 4714 std::cout << " <MEMC " << name() 4913 4715 << " WRITE_INVAL_CC_SEND> Post a inval request to CC_SEND FSM" << std::endl; … … 4948 4750 case IXR_CMD_READ_IDLE: 4949 4751 if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; 4950 else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;4951 else if (r_cleanup_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;4952 else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;4953 else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;4954 else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT;4752 else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; 4753 else if (r_cleanup_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT; 4754 else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; 4755 else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; 4756 else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; 4955 4757 break; 4956 4758 //////////////////////// 4957 4759 case IXR_CMD_WRITE_IDLE: 4958 4760 if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; 4959 else if (r_cleanup_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;4960 else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;4961 else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;4962 else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT;4963 else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;4761 else if (r_cleanup_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT; 4762 else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; 4763 else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; 4764 else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; 4765 else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; 4964 4766 break; 4965 4767 //////////////////////// 4966 4768 case IXR_CMD_CAS_IDLE: 4967 4769 if (r_cleanup_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT; 4968 else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;4969 else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;4970 else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT;4971 else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;4972 else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;4770 else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; 4771 else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; 4772 else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; 4773 else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; 4774 else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; 4973 4775 break; 4974 4776 //////////////////////// 4975 4777 case IXR_CMD_XRAM_IDLE: 4976 4778 if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; 4977 else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT;4978 else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;4979 else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;4980 else if (r_cleanup_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;4981 else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;4779 else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; 4780 else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; 4781 else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; 4782 else if (r_cleanup_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT; 4783 else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; 4982 4784 break; 4983 4785 //////////////////////// 4984 4786 case IXR_CMD_CLEANUP_IDLE: 4985 4787 if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; 4986 else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;4987 else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;4988 else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;4989 else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;4990 else if (r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;4788 else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; 4789 else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; 4790 else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; 4791 else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; 4792 else if (r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT; 4991 4793 break; 4992 4794 ///////////////////////// … … 4994 4796 { 4995 4797 if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; 4996 else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;4997 else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;4998 else if (r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;4999 else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;5000 else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;4798 else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; 4799 else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; 4800 else if (r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT; 4801 else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; 4802 else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; 5001 4803 break; 5002 4804 } … … 5005 4807 case IXR_CMD_READ_TRT: // access TRT for a GET 5006 4808 { 5007 if ( 4809 if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) 5008 4810 { 5009 4811 TransactionTabEntry entry = m_trt.read( r_read_to_ixr_cmd_index.read() ); … … 5015 4817 5016 4818 #if DEBUG_MEMC_IXR_CMD 5017 if (m_debug)4819 if (m_debug) 5018 4820 std::cout << " <MEMC " << name() << " IXR_CMD_READ_TRT> TRT access" 5019 4821 << " index = " << std::dec << r_read_to_ixr_cmd_index.read() … … 5026 4828 case IXR_CMD_WRITE_TRT: // access TRT for a PUT or a GET 5027 4829 { 5028 if ( 4830 if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) 5029 4831 { 5030 4832 TransactionTabEntry entry = m_trt.read( r_write_to_ixr_cmd_index.read() ); … … 5042 4844 5043 4845 #if DEBUG_MEMC_IXR_CMD 5044 if (m_debug)4846 if (m_debug) 5045 4847 std::cout << " <MEMC " << name() << " IXR_CMD_WRITE_TRT> TRT access" 5046 4848 << " index = " << std::dec << r_write_to_ixr_cmd_index.read() … … 5053 4855 case IXR_CMD_CAS_TRT: // access TRT for a PUT or a GET 5054 4856 { 5055 if ( 4857 if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) 5056 4858 { 5057 4859 TransactionTabEntry entry = m_trt.read( r_cas_to_ixr_cmd_index.read() ); … … 5069 4871 5070 4872 #if DEBUG_MEMC_IXR_CMD 5071 if (m_debug)4873 if (m_debug) 5072 4874 std::cout << " <MEMC " << name() << " IXR_CMD_CAS_TRT> TRT access" 5073 4875 << " index = " << std::dec << r_cas_to_ixr_cmd_index.read() … … 5080 4882 case IXR_CMD_XRAM_TRT: // access TRT for a PUT 5081 4883 { 5082 if ( 4884 if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) 5083 4885 { 5084 4886 TransactionTabEntry entry = m_trt.read( r_xram_rsp_to_ixr_cmd_index.read() ); … … 5089 4891 r_ixr_cmd_fsm = IXR_CMD_XRAM_SEND; 5090 4892 for( size_t i=0 ; i<m_words ; i++ ) r_ixr_cmd_wdata[i] = entry.wdata[i]; 5091 5092 m_cpt_ixr_cmd_fsm_n_trt_lock ++;5093 4893 #if DEBUG_MEMC_IXR_CMD 5094 if (m_debug)4894 if (m_debug) 5095 4895 std::cout << " <MEMC " << name() << " IXR_CMD_XRAM_TRT> TRT access" 5096 4896 << " index = " << std::dec << r_xram_rsp_to_ixr_cmd_index.read() … … 5103 4903 case IXR_CMD_CLEANUP_TRT: // access TRT for a PUT 5104 4904 { 5105 if ( 4905 if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) 5106 4906 { 5107 4907 … … 5115 4915 5116 4916 #if DEBUG_MEMC_IXR_CMD 5117 if (m_debug)4917 if (m_debug) 5118 4918 std::cout << " <MEMC " << name() << " IXR_CMD_CLEANUP_TRT> TRT access" 5119 4919 << " index = " << std::dec << r_cleanup_to_ixr_cmd_index.read() … … 5126 4926 case IXR_CMD_CONFIG_TRT: // access TRT for a PUT 5127 4927 { 5128 if ( 4928 if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) 5129 4929 { 5130 4930 TransactionTabEntry entry = m_trt.read( r_config_to_ixr_cmd_index.read() ); … … 5137 4937 5138 4938 #if DEBUG_MEMC_IXR_CMD 5139 if (m_debug)4939 if (m_debug) 5140 4940 std::cout << " <MEMC " << name() << " IXR_CMD_CONFIG_TRT> TRT access" 5141 4941 << " index = " << std::dec << r_config_to_ixr_cmd_index.read() … … 5149 4949 case IXR_CMD_READ_SEND: // send a get from READ FSM 5150 4950 { 5151 if (p_vci_ixr.cmdack)4951 if (p_vci_ixr.cmdack) 5152 4952 { 5153 4953 r_ixr_cmd_fsm = IXR_CMD_READ_IDLE; … … 5155 4955 5156 4956 #if DEBUG_MEMC_IXR_CMD 5157 if (m_debug)4957 if (m_debug) 5158 4958 std::cout << " <MEMC " << name() << " IXR_CMD_READ_SEND> GET request:" << std::hex 5159 4959 << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; … … 5165 4965 case IXR_CMD_WRITE_SEND: // send a put or get from WRITE FSM 5166 4966 { 5167 if (p_vci_ixr.cmdack)4967 if (p_vci_ixr.cmdack) 5168 4968 { 5169 4969 if (not r_ixr_cmd_get.read()) // PUT 5170 4970 { 5171 if (r_ixr_cmd_word.read() == (m_words - 2))4971 if (r_ixr_cmd_word.read() == (m_words - 2)) 5172 4972 { 5173 4973 r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE; … … 5180 4980 5181 4981 #if DEBUG_MEMC_IXR_CMD 5182 if (m_debug)4982 if (m_debug) 5183 4983 std::cout << " <MEMC " << name() << " IXR_CMD_WRITE_SEND> PUT request:" << std::hex 5184 4984 << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; … … 5191 4991 5192 4992 #if DEBUG_MEMC_IXR_CMD 5193 if (m_debug)4993 if (m_debug) 5194 4994 std::cout << " <MEMC " << name() << " IXR_CMD_WRITE_SEND> GET request:" << std::hex 5195 4995 << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; … … 5202 5002 case IXR_CMD_CAS_SEND: // send a put or get command from CAS FSM 5203 5003 { 5204 if (p_vci_ixr.cmdack)5004 if (p_vci_ixr.cmdack) 5205 5005 { 5206 5006 if (not r_ixr_cmd_get.read()) // PUT 5207 5007 { 5208 if (r_ixr_cmd_word.read() == (m_words - 2))5008 if (r_ixr_cmd_word.read() == (m_words - 2)) 5209 5009 { 5210 5010 r_ixr_cmd_fsm = IXR_CMD_CAS_IDLE; … … 5217 5017 5218 5018 #if DEBUG_MEMC_IXR_CMD 5219 if (m_debug)5019 if (m_debug) 5220 5020 std::cout << " <MEMC " << name() << " IXR_CMD_CAS_SEND> PUT request:" << std::hex 5221 5021 << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; … … 5228 5028 5229 5029 #if DEBUG_MEMC_IXR_CMD 5230 if (m_debug)5030 if (m_debug) 5231 5031 std::cout << " <MEMC " << name() << " IXR_CMD_CAS_SEND> GET request:" << std::hex 5232 5032 << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; … … 5239 5039 case IXR_CMD_XRAM_SEND: // send a put from XRAM_RSP FSM 5240 5040 { 5241 if (p_vci_ixr.cmdack.read())5242 { 5243 if (r_ixr_cmd_word.read() == (m_words - 2))5041 if (p_vci_ixr.cmdack.read()) 5042 { 5043 if (r_ixr_cmd_word.read() == (m_words - 2)) 5244 5044 { 5245 5045 r_ixr_cmd_fsm = IXR_CMD_XRAM_IDLE; … … 5251 5051 } 5252 5052 #if DEBUG_MEMC_IXR_CMD 5253 if (m_debug)5053 if (m_debug) 5254 5054 std::cout << " <MEMC " << name() << " IXR_CMD_XRAM_SEND> PUT request:" << std::hex 5255 5055 << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; … … 5262 5062 case IXR_CMD_CLEANUP_DATA_SEND: // send a put command to XRAM 5263 5063 { 5264 if (p_vci_ixr.cmdack.read())5265 { 5266 if (r_ixr_cmd_word.read() == (m_words - 2))5064 if (p_vci_ixr.cmdack.read()) 5065 { 5066 if (r_ixr_cmd_word.read() == (m_words - 2)) 5267 5067 { 5268 5068 r_ixr_cmd_fsm = IXR_CMD_CLEANUP_IDLE; … … 5277 5077 5278 5078 #if DEBUG_MEMC_IXR_CMD 5279 if (m_debug)5079 if (m_debug) 5280 5080 { 5281 5081 std::cout << " <MEMC " << name() << ".IXR_CMD_CLEANUP_DATA_SEND> Send a put request to xram" << std::endl; … … 5289 5089 case IXR_CMD_CONFIG_SEND: // send a put from CONFIG FSM 5290 5090 { 5291 if (p_vci_ixr.cmdack.read())5292 { 5293 if (r_ixr_cmd_word.read() == (m_words - 2))5091 if (p_vci_ixr.cmdack.read()) 5092 { 5093 if (r_ixr_cmd_word.read() == (m_words - 2)) 5294 5094 { 5295 5095 r_ixr_cmd_fsm = IXR_CMD_CONFIG_IDLE; … … 5302 5102 5303 5103 #if DEBUG_MEMC_IXR_CMD 5304 if (m_debug)5104 if (m_debug) 5305 5105 std::cout << " <MEMC " << name() << " IXR_CMD_CONFIG_SEND> PUT request:" << std::hex 5306 5106 << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; … … 5337 5137 case IXR_RSP_IDLE: // test transaction type: PUT/GET 5338 5138 { 5339 if (p_vci_ixr.rspval.read())5139 if (p_vci_ixr.rspval.read()) 5340 5140 { 5341 5141 r_ixr_rsp_cpt = 0; … … 5345 5145 "MEMC ERROR in IXR_RSP state: XRAM response error !"); 5346 5146 5347 if (p_vci_ixr.reop.read()) // PUT5147 if (p_vci_ixr.reop.read()) // PUT 5348 5148 { 5349 5149 r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE; … … 5355 5155 5356 5156 #if DEBUG_MEMC_IXR_RSP 5357 if (m_debug)5157 if (m_debug) 5358 5158 std::cout << " <MEMC " << name() 5359 5159 << " IXR_RSP_IDLE> Response from XRAM to a get transaction" << std::endl; … … 5374 5174 // decrease the line counter if config request 5375 5175 { 5376 if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP)5176 if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) 5377 5177 { 5378 5178 size_t index = r_ixr_rsp_trt_index.read(); … … 5388 5188 r_ixr_rsp_fsm = IXR_RSP_IDLE; 5389 5189 } 5390 5391 m_cpt_ixr_rsp_fsm_n_trt_lock ++;5392 5190 #if DEBUG_MEMC_IXR_RSP 5393 if (m_debug)5191 if (m_debug) 5394 5192 std::cout << " <MEMC " << name() << " IXR_RSP_TRT_ERASE> Erase TRT entry " 5395 5193 << r_ixr_rsp_trt_index.read() << std::endl; … … 5401 5199 case IXR_RSP_TRT_READ: // write a 64 bits data in the TRT 5402 5200 { 5403 if ((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and p_vci_ixr.rspval)5201 if ((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and p_vci_ixr.rspval) 5404 5202 { 5405 5203 size_t index = r_ixr_rsp_trt_index.read(); … … 5418 5216 r_ixr_rsp_cpt = word + 2; 5419 5217 5420 if (eop)5218 if (eop) 5421 5219 { 5422 5220 r_ixr_rsp_to_xram_rsp_rok[r_ixr_rsp_trt_index.read()]=true; … … 5425 5223 5426 5224 #if DEBUG_MEMC_IXR_RSP 5427 if (m_debug)5225 if (m_debug) 5428 5226 std::cout << " <MEMC " << name() << " IXR_RSP_TRT_READ> Writing a word in TRT : " 5429 5227 << " index = " << std::dec << index … … 5431 5229 << " / data = " << std::hex << data << std::endl; 5432 5230 #endif 5433 m_cpt_ixr_rsp_fsm_n_trt_lock ++; 5434 } 5435 m_cpt_ixr_fsm_trt_lock++; 5231 } 5436 5232 break; 5437 5233 } … … 5471 5267 { 5472 5268 size_t index = (i+old+1) %lines; 5473 if (r_ixr_rsp_to_xram_rsp_rok[index])5269 if (r_ixr_rsp_to_xram_rsp_rok[index]) 5474 5270 { 5475 5271 r_xram_rsp_trt_index = index; … … 5478 5274 5479 5275 #if DEBUG_MEMC_XRAM_RSP 5480 if (m_debug)5276 if (m_debug) 5481 5277 std::cout << " <MEMC " << name() << " XRAM_RSP_IDLE>" 5482 5278 << " Available cache line in TRT:" … … 5492 5288 // Copy the TRT entry in a local buffer 5493 5289 { 5494 if ((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and5290 if ((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and 5495 5291 (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP)) 5496 5292 { … … 5501 5297 5502 5298 #if DEBUG_MEMC_XRAM_RSP 5503 if (m_debug)5299 if (m_debug) 5504 5300 std::cout << " <MEMC " << name() << " XRAM_RSP_DIR_LOCK>" 5505 5301 << " Get access to DIR and TRT" << std::endl; 5506 5302 #endif 5507 m_cpt_xram_rsp_fsm_n_dir_lock++; 5508 m_cpt_xram_rsp_fsm_n_trt_lock++; 5509 } 5510 m_cpt_xram_rsp_fsm_dir_lock++; 5511 m_cpt_xram_rsp_fsm_trt_lock++; 5303 } 5512 5304 break; 5513 5305 } … … 5528 5320 DirectoryEntry victim(m_cache_directory.select(set, way)); 5529 5321 5530 if (way == -1)5322 if (way == -1) 5531 5323 { 5532 5324 #if DEBUG_MEMC_XRAM_RSP 5533 if (m_debug)5325 if (m_debug) 5534 5326 std::cout << " <MEMC " << name() << " XRAM_RSP_TRT_COPY>" 5535 5327 << " not a disponible victim" … … 5559 5351 assert( victim.state != ENTRY_LOCKED && "XRAM RSP SELECTED A LOCKED VICTIM "); 5560 5352 5561 if (not r_xram_rsp_trt_buf.rerror ) r_xram_rsp_fsm = XRAM_RSP_IVT_LOCK;5353 if (not r_xram_rsp_trt_buf.rerror ) r_xram_rsp_fsm = XRAM_RSP_IVT_LOCK; 5562 5354 else r_xram_rsp_fsm = XRAM_RSP_ERROR_ERASE; 5563 5355 5564 5356 #if DEBUG_MEMC_XRAM_RSP 5565 if (m_debug)5357 if (m_debug) 5566 5358 std::cout << " <MEMC " << name() << " XRAM_RSP_TRT_COPY>" 5567 5359 << " Select a victim slot: " … … 5585 5377 "MEMC ERROR in XRAM_RSP_IVT_LOCK state: Bad TRT allocation"); 5586 5378 5587 if (r_alloc_ivt_fsm == ALLOC_IVT_XRAM_RSP)5379 if (r_alloc_ivt_fsm == ALLOC_IVT_XRAM_RSP) 5588 5380 { 5589 5381 size_t index = 0; 5590 if (m_ivt.search_inval(r_xram_rsp_trt_buf.nline, index)) // pending inval5382 if (m_ivt.search_inval(r_xram_rsp_trt_buf.nline, index)) // pending inval 5591 5383 { 5592 5384 r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; 5593 5385 5594 5386 #if DEBUG_MEMC_XRAM_RSP 5595 if (m_debug)5387 if (m_debug) 5596 5388 std::cout << " <MEMC " << name() << " XRAM_RSP_IVT_LOCK>" 5597 5389 << " Get acces to IVT, but line invalidation registered" … … 5601 5393 5602 5394 } 5603 else if (m_ivt.is_full() and r_xram_rsp_victim_inval.read()) // IVT full5395 else if (m_ivt.is_full() and r_xram_rsp_victim_inval.read()) // IVT full 5604 5396 { 5605 5397 r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; 5606 5398 5607 5399 #if DEBUG_MEMC_XRAM_RSP 5608 if (m_debug)5400 if (m_debug) 5609 5401 std::cout << " <MEMC " << name() << " XRAM_RSP_IVT_LOCK>" 5610 5402 << " Get acces to IVT, but inval required and IVT full" << std::endl; … … 5616 5408 5617 5409 #if DEBUG_MEMC_XRAM_RSP 5618 if (m_debug)5410 if (m_debug) 5619 5411 std::cout << " <MEMC " << name() << " XRAM_RSP_IVT_LOCK>" 5620 5412 << " Get acces to IVT / no pending inval request" << std::endl; … … 5629 5421 5630 5422 #if DEBUG_MEMC_XRAM_RSP 5631 if (m_debug)5423 if (m_debug) 5632 5424 std::cout << " <MEMC " << name() << " XRAM_RSP_INVAL_WAIT>" 5633 5425 << " Release all locks and retry" << std::endl; … … 5680 5472 DirectoryEntry entry; 5681 5473 5682 if (inst_read and (r_xram_rsp_trt_buf.proc_read))5474 if (inst_read and (r_xram_rsp_trt_buf.proc_read)) 5683 5475 { 5684 5476 entry.state = ENTRY_SHARED; … … 5694 5486 entry.tag = r_xram_rsp_trt_buf.nline / m_sets; 5695 5487 entry.ptr = 0; 5696 if (cached_read and r_xram_rsp_trt_buf.proc_read)5488 if (cached_read and r_xram_rsp_trt_buf.proc_read) 5697 5489 { 5698 5490 entry.owner.srcid = r_xram_rsp_trt_buf.srcid; … … 5710 5502 r_xram_rsp_coherent = inst_read; 5711 5503 // request an invalidattion request in IVT for victim line 5712 if (r_xram_rsp_victim_inval.read())5504 if (r_xram_rsp_victim_inval.read()) 5713 5505 { 5714 5506 bool broadcast = r_xram_rsp_victim_is_cnt.read(); … … 5743 5535 // } 5744 5536 #if DEBUG_MEMC_XRAM_RSP 5745 if (m_debug)5537 if (m_debug) 5746 5538 { 5747 5539 std::cout << " <MEMC " << name() << " XRAM_RSP_DIR_UPDT>" … … 5754 5546 << " / nline = " << r_xram_rsp_trt_buf.nline 5755 5547 << " / is_cnt = " << entry.is_cnt << std::endl; 5756 if (r_xram_rsp_victim_inval.read())5548 if (r_xram_rsp_victim_inval.read()) 5757 5549 std::cout << " Invalidation request for victim line " 5758 5550 << std::hex << r_xram_rsp_victim_nline.read() … … 5763 5555 // If the victim is not dirty (RWT: if it is not coherent, we can not know wether it is dirty or not), we don't need another XRAM put transaction, 5764 5556 // and we can erase the TRT entry 5765 if ((not r_xram_rsp_victim_dirty.read()) or (r_xram_rsp_victim_state.read() == ENTRY_INVALID))5557 if ((not r_xram_rsp_victim_dirty.read()) or (r_xram_rsp_victim_state.read() == ENTRY_INVALID)) 5766 5558 { 5767 5559 m_trt.erase(r_xram_rsp_trt_index.read()); 5768 5560 } 5769 5561 // Next state 5770 if (r_xram_rsp_victim_dirty.read()) r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY;5771 else if (r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;5772 else if (r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL;5562 if (r_xram_rsp_victim_dirty.read()) r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY; 5563 else if (r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_DIR_RSP; 5564 else if (r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; 5773 5565 else r_xram_rsp_fsm = XRAM_RSP_IDLE; 5774 5566 break; … … 5777 5569 case XRAM_RSP_TRT_DIRTY: // set the TRT entry (write to XRAM) if the victim is dirty or not coherent (RWT) 5778 5570 { 5779 if (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP)5571 if (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) 5780 5572 { 5781 5573 std::vector<data_t> data_vector; … … 5798 5590 data_vector); 5799 5591 #if DEBUG_MEMC_XRAM_RSP 5800 if (m_debug)5592 if (m_debug) 5801 5593 std::cout << " <MEMC " << name() << " XRAM_RSP_TRT_DIRTY>" 5802 5594 << " Set TRT entry for the put transaction" … … 5804 5596 #endif 5805 5597 5806 // if (not r_xram_rsp_victim_coherent )5598 // if (not r_xram_rsp_victim_coherent ) 5807 5599 // std::cout << "a victim coherent not sent trt index =" << r_xram_rsp_trt_index.read() << std::endl; 5808 if (r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;5809 else if (r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL;5600 if (r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_DIR_RSP; 5601 else if (r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; 5810 5602 else r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; 5811 m_cpt_xram_rsp_fsm_n_trt_lock++; 5812 } 5813 5814 m_cpt_xram_rsp_fsm_trt_lock++; 5815 5603 } 5816 5604 break; 5817 5605 } … … 5819 5607 case XRAM_RSP_DIR_RSP: // Request a response to TGT_RSP FSM 5820 5608 { 5821 if (not r_xram_rsp_to_tgt_rsp_req.read())5609 if (not r_xram_rsp_to_tgt_rsp_req.read()) 5822 5610 { 5823 5611 r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid; … … 5842 5630 5843 5631 5844 if (r_xram_rsp_victim_inval) r_xram_rsp_fsm = XRAM_RSP_INVAL;5845 else if (r_xram_rsp_victim_dirty) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;5632 if (r_xram_rsp_victim_inval) r_xram_rsp_fsm = XRAM_RSP_INVAL; 5633 else if (r_xram_rsp_victim_dirty) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; 5846 5634 else r_xram_rsp_fsm = XRAM_RSP_IDLE; 5847 5635 5848 5636 #if DEBUG_MEMC_XRAM_RSP 5849 if (m_debug)5637 if (m_debug) 5850 5638 std::cout << " <MEMC " << name() << " XRAM_RSP_DIR_RSP>" 5851 5639 << " Request the TGT_RSP FSM to return data:" … … 5861 5649 case XRAM_RSP_INVAL: // send invalidate request to CC_SEND FSM 5862 5650 { 5863 if (!r_xram_rsp_to_cc_send_multi_req.read() and5651 if (!r_xram_rsp_to_cc_send_multi_req.read() and 5864 5652 !r_xram_rsp_to_cc_send_brdcast_req.read()) 5865 5653 { … … 5877 5665 r_xram_rsp_next_ptr = r_xram_rsp_victim_ptr.read(); 5878 5666 5879 if (r_xram_rsp_victim_dirty.read() and (r_xram_rsp_victim_state.read() == ENTRY_SHARED))5667 if (r_xram_rsp_victim_dirty.read() and (r_xram_rsp_victim_state.read() == ENTRY_SHARED)) 5880 5668 r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; 5881 else if (not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ;5669 else if (not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ; 5882 5670 else r_xram_rsp_fsm = XRAM_RSP_IDLE; 5883 5671 5884 5672 // std::cout << "cleanup sent for trt index =" << r_xram_rsp_trt_index.read() << std::endl; 5885 5673 #if DEBUG_MEMC_XRAM_RSP 5886 if (m_debug)5674 if (m_debug) 5887 5675 std::cout << " <MEMC " << name() << " XRAM_RSP_INVAL>" 5888 5676 << " Send an inval request to CC_SEND FSM" … … 5893 5681 { 5894 5682 #if DEBUG_MEMC_XRAM_RSP 5895 if (m_debug)5683 if (m_debug) 5896 5684 std::cout << " <MEMC " << name() << " XRAM_RSP_INVAL>" 5897 5685 << " multi req = " << r_xram_rsp_to_cc_send_multi_req.read() … … 5904 5692 case XRAM_RSP_WRITE_DIRTY: // send a write request to IXR_CMD FSM 5905 5693 { 5906 if ( 5907 { 5908 if ((r_xram_rsp_victim_state.read() == ENTRY_EXCLUSIVE) and (r_xram_rsp_victim_count.read() == 1))5694 if (not r_xram_rsp_to_ixr_cmd_req.read() ) 5695 { 5696 if ((r_xram_rsp_victim_state.read() == ENTRY_EXCLUSIVE) and (r_xram_rsp_victim_count.read() == 1)) 5909 5697 { 5910 5698 std::cout << "can't send a trt req when the line state is exlusive" << std::endl; … … 5914 5702 r_xram_rsp_to_ixr_cmd_index = r_xram_rsp_trt_index.read(); 5915 5703 5704 // <Activity counters> 5916 5705 m_cpt_write_dirty++; 5706 // </Activity counters> 5917 5707 5918 5708 bool multi_req = not r_xram_rsp_victim_is_cnt.read() and … … 5920 5710 bool not_last_multi_req = multi_req and (r_xram_rsp_victim_count.read() != 1); 5921 5711 5922 if (not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ;5712 if (not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ; 5923 5713 else r_xram_rsp_fsm = XRAM_RSP_IDLE; 5924 5714 5925 5715 #if DEBUG_MEMC_XRAM_RSP 5926 if (m_debug)