Changeset 785 for branches/MESI/modules/vci_mem_cache/caba
- Timestamp:
- Sep 2, 2014, 6:25:53 PM (10 years ago)
- Location:
- branches/MESI/modules/vci_mem_cache/caba
- Files:
-
- 3 edited
-
metadata/vci_mem_cache.sd (modified) (1 diff)
-
source/include/vci_mem_cache.h (modified) (8 diffs)
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source/src/vci_mem_cache.cpp (modified) (562 diffs)
Legend:
- Unmodified
- Added
- Removed
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branches/MESI/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd
r670 r785 40 40 Uses('caba:generic_fifo'), 41 41 Uses('caba:generic_llsc_global_table'), 42 Uses('caba:dspin_ dhccp_param')42 Uses('caba:dspin_hmesi_param') 43 43 ], 44 44 -
branches/MESI/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
r719 r785 38 38 #include <list> 39 39 #include <cassert> 40 40 41 #include "arithmetics.h" 41 42 #include "alloc_elems.h" … … 51 52 #include "update_tab.h" 52 53 #include "dspin_interface.h" 53 #include "dspin_ dhccp_param.h"54 #include "dspin_hmesi_param.h" 54 55 55 56 #define TRT_ENTRIES 4 // Number of entries in TRT … … 69 70 : public soclib::caba::BaseModule 70 71 { 71 typedef typename vci_param_int::fast_addr_t 72 typedef typename sc_dt::sc_uint<64> 73 typedef uint32_t 74 typedef uint32_t 75 typedef uint32_t 76 typedef uint32_t 72 typedef typename vci_param_int::fast_addr_t addr_t; 73 typedef typename sc_dt::sc_uint<64> wide_data_t; 74 typedef uint32_t data_t; 75 typedef uint32_t tag_t; 76 typedef uint32_t be_t; 77 typedef uint32_t copy_t; 77 78 78 79 /* States of the TGT_CMD fsm */ … … 392 393 // b1 accÚs table llsc type SW / other 393 394 // b2 WRITE/CAS/LL/SC 394 TYPE_DATA_UNC 395 TYPE_READ_DATA_MISS 396 TYPE_READ_INS_UNC 397 TYPE_READ_INS_MISS 398 TYPE_WRITE 399 TYPE_CAS 400 TYPE_LL 401 TYPE_SC 395 TYPE_DATA_UNC = 0x0, 396 TYPE_READ_DATA_MISS = 0x1, 397 TYPE_READ_INS_UNC = 0x2, 398 TYPE_READ_INS_MISS = 0x3, 399 TYPE_WRITE = 0x4, 400 TYPE_CAS = 0x5, 401 TYPE_LL = 0x6, 402 TYPE_SC = 0x7 402 403 }; 403 404 … … 405 406 enum sc_status_type_e 406 407 { 407 SC_SUCCESS =0x00000000,408 SC_FAIL =0x00000001408 SC_SUCCESS = 0x00000000, 409 SC_FAIL = 0x00000001 409 410 }; 410 411 411 412 // debug variables 412 bool 413 size_t 414 size_t 415 bool 416 data_t * 417 data_t * 413 bool m_debug; 414 size_t m_debug_previous_valid; 415 size_t m_debug_previous_count; 416 bool m_debug_previous_dirty; 417 data_t * m_debug_previous_data; 418 data_t * m_debug_data; 418 419 419 420 // instrumentation counters 420 uint32_t m_cpt_cycles; // Counter of cycles 421 422 // Counters accessible in software (not yet but eventually) 423 uint32_t m_cpt_reset_count; // Last cycle at which counters have been reset 424 uint32_t m_cpt_read_miss_local; // Number of local READ transactions 425 uint32_t m_cpt_read_miss_remote; // number of remote READ transactions 426 uint32_t m_cpt_read_miss_cost; // Number of (flits * distance) for READs 427 428 uint32_t m_cpt_getm_miss_local; // Number of local getm miss transactions 429 uint32_t m_cpt_getm_miss_remote; // number of remote getm miss transactions 430 431 uint32_t m_cpt_getm_hit_local; // Number of local getm hit transactions 432 uint32_t m_cpt_getm_hit_remote; // number of remote getm hit transactions 433 uint32_t m_cpt_getm_cost; // Number of (flits * distance) for getm 434 435 uint32_t m_cpt_write_local; // Number of local WRITE transactions 436 uint32_t m_cpt_write_remote; // number of remote WRITE transactions 437 uint32_t m_cpt_write_flits_local; // number of flits for local WRITEs 438 uint32_t m_cpt_write_flits_remote; // number of flits for remote WRITEs 439 uint32_t m_cpt_write_cost; // Number of (flits * distance) for WRITEs 440 441 uint32_t m_cpt_ll_local; // Number of local LL transactions 442 uint32_t m_cpt_ll_remote; // number of remote LL transactions 443 uint32_t m_cpt_ll_cost; // Number of (flits * distance) for LLs 444 445 uint32_t m_cpt_sc_local; // Number of local SC transactions 446 uint32_t m_cpt_sc_remote; // number of remote SC transactions 447 uint32_t m_cpt_sc_cost; // Number of (flits * distance) for SCs 448 449 uint32_t m_cpt_cas_local; // Number of local SC transactions 450 uint32_t m_cpt_cas_remote; // number of remote SC transactions 451 uint32_t m_cpt_cas_cost; // Number of (flits * distance) for SCs 452 453 uint32_t m_cpt_update; // Number of requests causing an UPDATE 454 uint32_t m_cpt_update_local; // Number of local UPDATE transactions 455 uint32_t m_cpt_update_remote; // Number of remote UPDATE transactions 456 uint32_t m_cpt_update_cost; // Number of (flits * distance) for UPDT 457 458 uint32_t m_cpt_minval; // Number of requests causing M_INV 459 uint32_t m_cpt_minval_local; // Number of local M_INV transactions 460 uint32_t m_cpt_minval_remote; // Number of remote M_INV transactions 461 uint32_t m_cpt_minval_cost; // Number of (flits * distance) for M_INV 462 463 uint32_t m_cpt_binval; // Number of BROADCAST INVAL 464 465 uint32_t m_cpt_cleanup_local; // Number of local CLEANUP transactions 466 uint32_t m_cpt_cleanup_remote; // Number of remote CLEANUP transactions 467 uint32_t m_cpt_cleanup_with_data; 468 uint32_t m_cpt_cleanup_cost; // Number of (flits * distance) for CLEANUPs 469 470 uint32_t m_cpt_multi_ack_miss; // Number of local CLEANUP transactions 471 uint32_t m_cpt_multi_ack_hit; // Number of local CLEANUP transactions 472 uint32_t m_cpt_multi_ack_hit_with_data; // Number of remote CLEANUP transactions 421 uint32_t m_cpt_cycles; // Counter of cycles 422 423 // Counters 424 // (*) = Counters accessible in software 425 uint32_t m_cpt_reset_count; // Last cycle at which counters have been reset 426 427 uint32_t m_cpt_read_local; // Number of local READ transactions (*) 428 uint32_t m_cpt_read_remote; // number of remote READ transactions (*) 429 uint32_t m_cpt_read_cost; // Number of (flits * distance) for READs (*) 430 431 uint32_t m_cpt_write_local; // Number of local WRITE transactions 432 uint32_t m_cpt_write_remote; // number of remote WRITE transactions 433 uint32_t m_cpt_write_flits_local; // number of flits for local WRITEs (*) 434 uint32_t m_cpt_write_flits_remote; // number of flits for remote WRITEs (*) 435 uint32_t m_cpt_write_cost; // Number of (flits * distance) for WRITEs (*) 436 437 uint32_t m_cpt_ll_local; // Number of local LL transactions (*) 438 uint32_t m_cpt_ll_remote; // number of remote LL transactions (*) 439 uint32_t m_cpt_ll_cost; // Number of (flits * distance) for LLs (*) 440 441 uint32_t m_cpt_sc_local; // Number of local SC transactions (*) 442 uint32_t m_cpt_sc_remote; // number of remote SC transactions (*) 443 uint32_t m_cpt_sc_cost; // Number of (flits * distance) for SCs (*) 444 445 uint32_t m_cpt_cas_local; // Number of local SC transactions (*) 446 uint32_t m_cpt_cas_remote; // number of remote SC transactions (*) 447 uint32_t m_cpt_cas_cost; // Number of (flits * distance) for SCs (*) 448 449 uint32_t m_cpt_minval; // Number of requests causing M_INV (*) 450 uint32_t m_cpt_minval_local; // Number of local M_INV transactions (*) 451 uint32_t m_cpt_minval_remote; // Number of remote M_INV transactions (*) 452 uint32_t m_cpt_minval_cost; // Number of (flits * distance) for M_INV (*) 453 454 uint32_t m_cpt_binval; // Number of BROADCAST INVAL (*) 455 uint32_t m_cpt_write_broadcast;// Number of BROADCAST INVAL caused by write 456 uint32_t m_cpt_getm_broadcast; // Number of BROADCAST INVAL caused by getm 457 458 uint32_t m_cpt_cleanup_local; // Number of local CLEANUP transactions (*) 459 uint32_t m_cpt_cleanup_remote; // Number of remote CLEANUP transactions (*) 460 uint32_t m_cpt_cleanup_cost; // Number of (flits * distance) for CLEANUPs (*) 461 uint32_t m_cpt_cleanup_data_local; // 462 uint32_t m_cpt_cleanup_data_remote; // 463 uint32_t m_cpt_cleanup_data_cost; // 464 465 uint32_t m_cpt_read_miss; // Number of MISS READ 466 uint32_t m_cpt_write_miss; // Number of MISS WRITE 467 uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions 468 uint32_t m_cpt_getm_miss; // Number of getm miss 469 470 uint32_t m_cpt_getm_local; // Number of local getm miss transactions 471 uint32_t m_cpt_getm_remote; // number of remote getm miss transactions 472 uint32_t m_cpt_getm_cost; // Number of (flits * distance) for getm 473 474 uint32_t m_cpt_inval_ro_local; // Number of local INVAL RO (*) 475 uint32_t m_cpt_inval_ro_remote; // Number of local INVAL RO (*) 476 uint32_t m_cpt_inval_ro_cost; // Cost for INVAL RO (*) 473 477 474 // Counters not accessible by software 475 uint32_t m_cpt_read_miss; // Number of MISS READ 476 uint32_t m_cpt_getm_miss; // Number of getm miss 477 uint32_t m_cpt_getm_broadcast; // Number of BROADCAST INVAL because getm 478 uint32_t m_cpt_getm_minval; // Number of MULTI INVAL because getm 479 uint32_t m_cpt_write_miss; // Number of MISS WRITE 480 uint32_t m_cpt_write_dirty; // Cumulated length for WRITE transactions 481 uint32_t m_cpt_write_broadcast;// Number of BROADCAST INVAL because write 482 uint32_t m_cpt_write_minval; // Number of MULTI INVAL because write 483 uint32_t m_cpt_cas_broadcast; // Number of BROADCAST INVAL because cas 484 uint32_t m_cpt_cas_minval; // Number of MULTI INVAL because cas 485 uint32_t m_cpt_cas_miss; 486 487 uint32_t m_cpt_read_locked_rb; // Read blocked by a locked ligne 488 uint32_t m_cpt_cas_locked_rb; // cas blocked by a locked ligne 489 uint32_t m_cpt_write_locked_rb; // wt blocked by a locked ligne 490 491 uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt 492 uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt 493 uint32_t m_cpt_put; 494 uint32_t m_cpt_get; 495 496 uint32_t m_cpt_read_fsm_dir_lock; // wait DIR LOCK 497 uint32_t m_cpt_read_fsm_n_dir_lock; // NB DIR LOCK 498 uint32_t m_cpt_write_fsm_dir_lock; // wait DIR LOCK 499 uint32_t m_cpt_write_fsm_n_dir_lock; // NB DIR LOCK 500 uint32_t m_cpt_xram_rsp_fsm_dir_lock; // wait DIR LOCK 501 uint32_t m_cpt_xram_rsp_fsm_n_dir_lock; // NB DIR LOCK 502 uint32_t m_cpt_cas_fsm_dir_lock; // wait DIR LOCK 503 uint32_t m_cpt_cas_fsm_n_dir_lock; // NB DIR LOCK 504 uint32_t m_cpt_cleanup_fsm_dir_lock; // wait DIR LOCK 505 uint32_t m_cpt_cleanup_fsm_n_dir_lock; // NB DIR LOCK 506 uint32_t m_cpt_multi_ack_fsm_dir_lock; // wait DIR LOCK 507 uint32_t m_cpt_multi_ack_fsm_n_dir_lock; // NB DIR LOCK 508 509 uint32_t m_cpt_dir_unused; // NB cycles DIR LOCK unused 510 uint32_t m_cpt_read_fsm_dir_used; // NB cycles DIR LOCK used 511 uint32_t m_cpt_write_fsm_dir_used; // NB cycles DIR LOCK used 512 uint32_t m_cpt_cas_fsm_dir_used; // NB cycles DIR LOCK used 513 uint32_t m_cpt_xram_rsp_fsm_dir_used; // NB cycles DIR LOCK used 514 uint32_t m_cpt_cleanup_fsm_dir_used; // NB cycles DIR LOCK used 515 uint32_t m_cpt_multi_ack_fsm_dir_used; // NB cycles DIR LOCK used 516 517 uint32_t m_cpt_read_fsm_trt_lock; // wait TRT LOCK 518 uint32_t m_cpt_write_fsm_trt_lock; // wait TRT LOCK 519 uint32_t m_cpt_cas_fsm_trt_lock; // wait TRT LOCK 520 uint32_t m_cpt_xram_rsp_fsm_trt_lock; // wait TRT LOCK 521 uint32_t m_cpt_ixr_fsm_trt_lock; // wait TRT LOCK 522 523 uint32_t m_cpt_read_fsm_n_trt_lock; // NB TRT LOCK 524 uint32_t m_cpt_write_fsm_n_trt_lock; // NB TRT LOCK 525 uint32_t m_cpt_cas_fsm_n_trt_lock; // NB TRT LOCK 526 uint32_t m_cpt_xram_rsp_fsm_n_trt_lock; // NB TRT LOCK 527 uint32_t m_cpt_ixr_cmd_fsm_n_trt_lock; // NB TRT LOCK 528 uint32_t m_cpt_ixr_rsp_fsm_n_trt_lock; // NB TRT LOCK 529 530 uint32_t m_cpt_read_fsm_trt_used; // NB cycles TRT LOCK used 531 uint32_t m_cpt_write_fsm_trt_used; // NB cycles TRT LOCK used 532 uint32_t m_cpt_cas_fsm_trt_used; // NB cycles TRT LOCK used 533 uint32_t m_cpt_xram_rsp_fsm_trt_used; // NB cycles TRT LOCK used 534 uint32_t m_cpt_ixr_cmd_fsm_trt_used; // NB cycles TRT LOCK used 535 uint32_t m_cpt_ixr_rsp_fsm_trt_used; // NB cycles TRT LOCK used 536 uint32_t m_cpt_cleanup_fsm_trt_used; // NB cycles TRT LOCK used 537 538 uint32_t m_cpt_trt_unused; // NB cycles TRT LOCK unused 539 540 uint32_t m_cpt_cleanup_fsm_ivt_lock; // wait ivt LOCK 541 uint32_t m_cpt_cleanup_fsm_n_ivt_lock; // NB cycles UPT LOCK used 542 543 uint32_t m_cpt_multi_ack_fsm_ivt_lock; // wait ivt LOCK 544 uint32_t m_cpt_multi_ack_fsm_n_ivt_lock; // NB cycles UPT LOCK used 545 546 uint32_t m_cpt_ivt_unused; // NB cycles UPT LOCK unused 547 548 uint32_t m_cpt_read_fsm_heap_lock; // wait HEAP LOCK 549 uint32_t m_cpt_write_fsm_heap_lock; // wait HEAP LOCK 550 uint32_t m_cpt_cas_fsm_heap_lock; // wait HEAP LOCK 551 uint32_t m_cpt_cleanup_fsm_heap_lock; // wait HEAP LOCK 552 uint32_t m_cpt_xram_rsp_fsm_heap_lock; // wait HEAP LOCK 553 uint32_t m_cpt_multi_ack_fsm_heap_lock; // wait HEAP LOCK 554 555 uint32_t m_cpt_read_fsm_n_heap_lock; // NB HEAP LOCK 556 uint32_t m_cpt_write_fsm_n_heap_lock; // NB HEAP LOCK 557 uint32_t m_cpt_cas_fsm_n_heap_lock; // NB HEAP LOCK 558 uint32_t m_cpt_cleanup_fsm_n_heap_lock; // NB HEAP LOCK 559 uint32_t m_cpt_xram_rsp_fsm_n_heap_lock; // NB HEAP LOCK 560 uint32_t m_cpt_multi_ack_fsm_n_heap_lock; // NB HEAP LOCK 561 562 uint32_t m_cpt_read_fsm_heap_used; // NB cycles HEAP LOCK used 563 uint32_t m_cpt_write_fsm_heap_used; // NB cycles HEAP LOCK used 564 uint32_t m_cpt_cas_fsm_heap_used; // NB cycles HEAP LOCK used 565 uint32_t m_cpt_cleanup_fsm_heap_used; // NB cycles HEAP LOCK used 566 uint32_t m_cpt_xram_rsp_fsm_heap_used; // NB cycles HEAP LOCK used 567 uint32_t m_cpt_multi_ack_fsm_heap_used; // NB cycles HEAP LOCK used 568 569 uint32_t m_cpt_heap_unused; // NB cycles HEAP LOCK unused 570 uint32_t m_cpt_slot_inval; 478 uint32_t m_cpt_trt_rb; // Read blocked by a hit in trt 479 uint32_t m_cpt_trt_full; // Transaction blocked due to a full trt 480 uint32_t m_cpt_put; 481 uint32_t m_cpt_get; 482 483 uint32_t m_cpt_heap_unused; // NB cycles HEAP LOCK unused 484 uint32_t m_cpt_slot_inval; 571 485 572 486 protected: … … 602 516 sc_out<int> p_cc_send_fsm; 603 517 sc_out<int> p_cc_receive_fsm; 604 sc_out<int> p_multi_ack_fsm; 518 sc_out<int> p_multi_ack_fsm; 605 519 #endif 606 520 … … 611 525 const soclib::common::IntTab &srcid_x, // global index RAM network 612 526 const soclib::common::IntTab &tgtid_d, // global index INT network 613 const size_t cc_global_id, // global index CC network614 527 const size_t x_width, // X width in platform 615 528 const size_t y_width, // Y width in platform … … 654 567 const size_t m_sets; // Number of cache sets 655 568 const size_t m_words; // Number of words in a line 656 const size_t m_cc_global_id; // global_index on cc network 657 const size_t m_xwidth; // number of x bits in platform 658 const size_t m_ywidth; // number of y bits in platform 569 size_t m_x_self; // X self coordinate 570 size_t m_y_self; // Y self coordinate 571 const size_t m_x_width; // number of x bits in platform 572 const size_t m_y_width; // number of y bits in platform 659 573 size_t m_debug_start_cycle; 660 574 bool m_debug_ok; -
branches/MESI/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
r719 r785 351 351 const IntTab &srcid_x, // global index on external network 352 352 const IntTab &tgtid_d, // global index on direct network 353 const size_t cc_global_id, // global index on cc network354 353 const size_t x_width, // number of x bits in platform 355 354 const size_t y_width, // number of x bits in platform … … 384 383 m_sets( nsets ), 385 384 m_words( nwords ), 386 m_cc_global_id( cc_global_id ), 387 m_xwidth(x_width), 388 m_ywidth(y_width), 385 m_x_width(x_width), 386 m_y_width(y_width), 389 387 m_debug_start_cycle( debug_start_cycle ), 390 388 m_debug_ok( debug_ok ), … … 550 548 for(seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++) 551 549 { 552 if ( 550 if (seg->special() ) m_seg_config = i; 553 551 m_seg[i] = & (*seg); 554 552 i++; 555 553 } 554 555 addr_t gid = m_seg[0]->baseAddress() >> (vci_param_int::N - x_width - y_width); 556 m_x_self = (gid >> m_y_width) & ((1 << m_x_width) - 1); 557 m_y_self = gid & ((1 << m_y_width) - 1); 556 558 557 559 // Allocation for IXR_RSP FSM … … 614 616 bool data_change = false; 615 617 616 if ( 618 if (entry.state != ENTRY_INVALID ) 617 619 { 618 620 for ( size_t word = 0 ; word<m_words ; word++ ) 619 621 { 620 622 m_debug_data[word] = m_cache_data.read(way, set, word); 621 if ( 623 if ((m_debug_previous_valid != ENTRY_INVALID) and 622 624 (m_debug_data[word] != m_debug_previous_data[word]) ) 623 625 { … … 628 630 629 631 // print values if any change 630 if ( 632 if ((entry.state != m_debug_previous_valid) or 631 633 ((entry.state != ENTRY_INVALID) and (entry.count != m_debug_previous_count)) or 632 634 ((entry.state != ENTRY_INVALID) and (entry.dirty != m_debug_previous_dirty)) or data_change ) … … 672 674 { 673 675 const uint32_t srcid_width = vci_param_int::S; 674 uint8_t self_x_srcid = m_cc_global_id >> (srcid_width - m_xwidth); 675 uint8_t self_y_srcid = (m_cc_global_id >> (srcid_width - m_ywidth)) & ((1 << m_xwidth) - 1); 676 677 uint8_t x_srcid = req_srcid >> (srcid_width - m_xwidth); 678 uint8_t y_srcid = (req_srcid >> (srcid_width - m_ywidth - m_xwidth)) & ((1 << m_xwidth) - 1); 679 return abs(self_x_srcid - x_srcid) + abs(self_y_srcid - y_srcid); 676 677 uint8_t req_x = (req_srcid >> (srcid_width - m_x_width)); 678 uint8_t req_y = (req_srcid >> (srcid_width - m_x_width - m_y_width)) & ((1 << m_y_width) - 1); 679 680 return abs(m_x_self - req_x) + abs(m_y_self - req_y); 680 681 } 681 682 … … 706 707 // LOCAL 707 708 708 case MEMC_LOCAL_READ_LO : rdata = m_cpt_read_ miss_local ; break;709 case MEMC_LOCAL_READ_LO : rdata = m_cpt_read_local ; break; 709 710 case MEMC_LOCAL_WRITE_LO : rdata = m_cpt_write_flits_local ; break; 710 711 case MEMC_LOCAL_LL_LO : rdata = m_cpt_ll_local ; break; … … 719 720 // REMOTE 720 721 721 case MEMC_REMOTE_READ_LO : rdata = m_cpt_read_ miss_remote ; break;722 case MEMC_REMOTE_READ_LO : rdata = m_cpt_read_remote ; break; 722 723 case MEMC_REMOTE_WRITE_LO : rdata = m_cpt_write_flits_remote ; break; 723 724 case MEMC_REMOTE_LL_LO : rdata = m_cpt_ll_remote ; break; … … 732 733 // COST 733 734 734 case MEMC_COST_READ_LO : rdata = m_cpt_read_ miss_cost ; break;735 case MEMC_COST_READ_LO : rdata = m_cpt_read_cost ; break; 735 736 case MEMC_COST_WRITE_LO : rdata = m_cpt_write_cost; break; 736 737 case MEMC_COST_LL_LO : rdata = m_cpt_ll_cost ; break; … … 753 754 // LOCAL 754 755 755 case MEMC_LOCAL_MUPDATE_LO : rdata = m_cpt_ update_local; break;756 case MEMC_LOCAL_MINVAL_LO : rdata = m_cpt_minval_local ; break;757 case MEMC_LOCAL_CLEANUP_LO : rdata = m_cpt_cleanup_local; break;756 case MEMC_LOCAL_MUPDATE_LO : rdata = m_cpt_inval_ro_local; break; 757 case MEMC_LOCAL_MINVAL_LO : rdata = m_cpt_minval_local ; break; 758 case MEMC_LOCAL_CLEANUP_LO : rdata = m_cpt_cleanup_local; break; 758 759 case MEMC_LOCAL_MUPDATE_HI : 759 760 case MEMC_LOCAL_MINVAL_HI : … … 762 763 // REMOTE 763 764 764 case MEMC_REMOTE_MUPDATE_LO : rdata = m_cpt_ update_remote; break;765 case MEMC_REMOTE_MINVAL_LO : rdata = m_cpt_minval_remote ; break;766 case MEMC_REMOTE_CLEANUP_LO : rdata = m_cpt_cleanup_remote; break;765 case MEMC_REMOTE_MUPDATE_LO : rdata = m_cpt_inval_ro_remote; break; 766 case MEMC_REMOTE_MINVAL_LO : rdata = m_cpt_minval_remote ; break; 767 case MEMC_REMOTE_CLEANUP_LO : rdata = m_cpt_cleanup_remote; break; 767 768 case MEMC_REMOTE_MUPDATE_HI : 768 769 case MEMC_REMOTE_MINVAL_HI : … … 771 772 // COST 772 773 773 case MEMC_COST_MUPDATE_LO : rdata = m_cpt_ update_cost; break;774 case MEMC_COST_MINVAL_LO : rdata = m_cpt_minval_cost ;break;775 case MEMC_COST_CLEANUP_LO : rdata = m_cpt_cleanup_cost ;break;774 case MEMC_COST_MUPDATE_LO : rdata = m_cpt_inval_ro_cost; break; 775 case MEMC_COST_MINVAL_LO : rdata = m_cpt_minval_cost; break; 776 case MEMC_COST_CLEANUP_LO : rdata = m_cpt_cleanup_cost; break; 776 777 case MEMC_COST_MUPDATE_HI : 777 778 case MEMC_COST_MINVAL_HI : … … 779 780 780 781 // TOTAL 781 782 case MEMC_TOTAL_MUPDATE_LO : rdata = m_cpt_ update; break;783 case MEMC_TOTAL_MINVAL_LO : rdata = m_cpt_minval ; break;784 case MEMC_TOTAL_BINVAL_LO : rdata = m_cpt_binval ; break;782 // inval_ro are equal to the number of requests triggering them 783 case MEMC_TOTAL_MUPDATE_LO : rdata = m_cpt_inval_ro_local + m_cpt_inval_ro_remote; break; 784 case MEMC_TOTAL_MINVAL_LO : rdata = m_cpt_minval ; break; 785 case MEMC_TOTAL_BINVAL_LO : rdata = m_cpt_binval ; break; 785 786 case MEMC_TOTAL_MUPDATE_HI : 786 787 case MEMC_TOTAL_MINVAL_HI : … … 788 789 789 790 // unknown register 790 791 791 default : error = 1; 792 792 } … … 819 819 << " | " << alloc_heap_fsm_str[r_alloc_heap_fsm.read()] << std::endl; 820 820 821 if ( 821 if (detailed ) m_trt.print(0); 822 822 } 823 823 … … 827 827 ///////////////////////////////////////// 828 828 { 829 m_cpt_reset_count = m_cpt_cycles; 830 831 m_cpt_read_miss_local = 0 ; 832 m_cpt_read_miss_remote = 0 ; 833 m_cpt_read_miss_cost = 0 ; 834 835 m_cpt_getm_miss_local = 0 ; 836 m_cpt_getm_miss_remote = 0 ; 837 838 m_cpt_getm_hit_local = 0 ; 839 m_cpt_getm_hit_remote = 0 ; 840 m_cpt_getm_cost = 0 ; 841 842 m_cpt_write_local = 0 ; 843 m_cpt_write_remote = 0 ; 844 m_cpt_write_flits_local = 0 ; 845 m_cpt_write_flits_remote = 0 ; 846 m_cpt_write_cost = 0 ; 847 848 m_cpt_ll_local = 0 ; 849 m_cpt_ll_remote = 0 ; 850 m_cpt_ll_cost = 0 ; 851 852 m_cpt_sc_local = 0 ; 853 m_cpt_sc_remote = 0 ; 854 m_cpt_sc_cost = 0 ; 855 856 m_cpt_cas_local = 0 ; 857 m_cpt_cas_remote = 0 ; 858 m_cpt_cas_cost = 0 ; 859 860 m_cpt_update = 0 ; 861 m_cpt_update_local = 0 ; 862 m_cpt_update_remote = 0 ; 863 m_cpt_update_cost = 0 ; 864 865 m_cpt_minval = 0 ; 866 m_cpt_minval_local = 0 ; 867 m_cpt_minval_remote = 0 ; 868 m_cpt_minval_cost = 0 ; 869 870 m_cpt_binval = 0 ; 871 872 m_cpt_cleanup_local = 0 ; 873 m_cpt_cleanup_remote = 0 ; 874 m_cpt_cleanup_with_data = 0 ; 875 m_cpt_cleanup_cost = 0 ; 876 877 m_cpt_multi_ack_miss = 0 ; 878 m_cpt_multi_ack_hit = 0 ; 879 m_cpt_multi_ack_hit_with_data = 0 ; 880 881 882 m_cpt_read_miss = 0 ; 883 m_cpt_getm_miss = 0 ; 884 m_cpt_getm_broadcast = 0 ; 885 m_cpt_getm_minval = 0 ; 886 m_cpt_write_miss = 0 ; 887 m_cpt_write_dirty = 0 ; 888 m_cpt_write_broadcast = 0 ; 889 m_cpt_write_minval = 0 ; 890 m_cpt_cas_broadcast = 0 ; 891 m_cpt_cas_minval = 0 ; 892 m_cpt_cas_miss = 0 ; 893 894 m_cpt_read_locked_rb = 0 ; 895 m_cpt_cas_locked_rb = 0 ; 896 m_cpt_write_locked_rb = 0 ; 897 898 m_cpt_trt_rb = 0 ; 899 m_cpt_trt_full = 0 ; 900 m_cpt_put = 0 ; 901 m_cpt_get = 0 ; 902 m_cpt_read_fsm_dir_lock = 0 ; 903 m_cpt_read_fsm_n_dir_lock = 0 ; 904 m_cpt_write_fsm_dir_lock = 0 ; 905 m_cpt_write_fsm_n_dir_lock = 0 ; 906 m_cpt_xram_rsp_fsm_dir_lock = 0 ; 907 m_cpt_xram_rsp_fsm_n_dir_lock = 0 ; 908 m_cpt_cas_fsm_dir_lock = 0 ; 909 m_cpt_cas_fsm_n_dir_lock = 0 ; 910 m_cpt_cleanup_fsm_dir_lock = 0 ; 911 m_cpt_cleanup_fsm_n_dir_lock = 0 ; 912 m_cpt_multi_ack_fsm_dir_lock = 0 ; 913 m_cpt_multi_ack_fsm_n_dir_lock = 0 ; 914 915 m_cpt_dir_unused = 0 ; 916 m_cpt_read_fsm_dir_used = 0 ; 917 m_cpt_write_fsm_dir_used = 0 ; 918 m_cpt_cas_fsm_dir_used = 0 ; 919 m_cpt_xram_rsp_fsm_dir_used = 0 ; 920 m_cpt_cleanup_fsm_dir_used = 0 ; 921 m_cpt_multi_ack_fsm_dir_used = 0 ; 922 923 m_cpt_read_fsm_trt_lock = 0 ; 924 m_cpt_write_fsm_trt_lock = 0 ; 925 m_cpt_cas_fsm_trt_lock = 0 ; 926 m_cpt_xram_rsp_fsm_trt_lock = 0 ; 927 m_cpt_ixr_fsm_trt_lock = 0 ; 928 929 m_cpt_read_fsm_n_trt_lock = 0 ; 930 m_cpt_write_fsm_n_trt_lock = 0 ; 931 m_cpt_cas_fsm_n_trt_lock = 0 ; 932 m_cpt_xram_rsp_fsm_n_trt_lock = 0 ; 933 m_cpt_ixr_cmd_fsm_n_trt_lock = 0 ; 934 m_cpt_ixr_rsp_fsm_n_trt_lock = 0 ; 935 936 m_cpt_read_fsm_trt_used = 0 ; 937 m_cpt_write_fsm_trt_used = 0 ; 938 m_cpt_cas_fsm_trt_used = 0 ; 939 m_cpt_xram_rsp_fsm_trt_used = 0 ; 940 m_cpt_ixr_cmd_fsm_trt_used = 0 ; 941 m_cpt_ixr_rsp_fsm_trt_used = 0 ; 942 m_cpt_cleanup_fsm_trt_used = 0 ; 943 944 m_cpt_trt_unused = 0 ; 945 946 m_cpt_cleanup_fsm_ivt_lock = 0 ; 947 m_cpt_cleanup_fsm_n_ivt_lock = 0 ; 948 949 m_cpt_multi_ack_fsm_ivt_lock = 0 ; 950 m_cpt_multi_ack_fsm_n_ivt_lock = 0 ; 951 952 m_cpt_ivt_unused = 0 ; 953 954 m_cpt_read_fsm_heap_lock = 0 ; 955 m_cpt_write_fsm_heap_lock = 0 ; 956 m_cpt_cas_fsm_heap_lock = 0 ; 957 m_cpt_cleanup_fsm_heap_lock = 0 ; 958 m_cpt_xram_rsp_fsm_heap_lock = 0 ; 959 m_cpt_multi_ack_fsm_heap_lock = 0 ; 960 961 m_cpt_read_fsm_n_heap_lock = 0 ; 962 m_cpt_write_fsm_n_heap_lock = 0 ; 963 m_cpt_cas_fsm_n_heap_lock = 0 ; 964 m_cpt_cleanup_fsm_n_heap_lock = 0 ; 965 m_cpt_xram_rsp_fsm_n_heap_lock = 0 ; 966 m_cpt_multi_ack_fsm_n_heap_lock = 0 ; 967 968 m_cpt_read_fsm_heap_used = 0 ; 969 m_cpt_write_fsm_heap_used = 0 ; 970 m_cpt_cas_fsm_heap_used = 0 ; 971 m_cpt_cleanup_fsm_heap_used = 0 ; 972 m_cpt_xram_rsp_fsm_heap_used = 0 ; 973 m_cpt_multi_ack_fsm_heap_used = 0 ; 974 975 m_cpt_heap_unused = 0 ; 976 m_cpt_slot_inval = 0 ; 977 829 m_cpt_reset_count = m_cpt_cycles; 830 831 m_cpt_read_local = 0; 832 m_cpt_read_remote = 0; 833 m_cpt_read_cost = 0; 834 835 m_cpt_write_local = 0; 836 m_cpt_write_remote = 0; 837 m_cpt_write_flits_local = 0; 838 m_cpt_write_flits_remote = 0; 839 m_cpt_write_cost = 0; 840 841 m_cpt_ll_local = 0; 842 m_cpt_ll_remote = 0; 843 m_cpt_ll_cost = 0; 844 845 m_cpt_sc_local = 0; 846 m_cpt_sc_remote = 0; 847 m_cpt_sc_cost = 0; 848 849 m_cpt_cas_local = 0; 850 m_cpt_cas_remote = 0; 851 m_cpt_cas_cost = 0; 852 853 m_cpt_minval = 0; 854 m_cpt_minval_local = 0; 855 m_cpt_minval_remote = 0; 856 m_cpt_minval_cost = 0; 857 858 m_cpt_binval = 0; 859 m_cpt_write_broadcast = 0; 860 m_cpt_getm_broadcast = 0; 861 862 m_cpt_cleanup_local = 0; 863 m_cpt_cleanup_remote = 0; 864 m_cpt_cleanup_cost = 0; 865 m_cpt_cleanup_data_local = 0; 866 m_cpt_cleanup_data_remote = 0; 867 m_cpt_cleanup_data_cost = 0; 868 869 m_cpt_read_miss = 0; 870 m_cpt_write_miss = 0; 871 m_cpt_write_dirty = 0; 872 m_cpt_getm_miss = 0; 873 874 m_cpt_getm_local = 0; 875 m_cpt_getm_remote = 0; 876 m_cpt_getm_cost = 0; 877 878 m_cpt_inval_ro_local = 0; 879 m_cpt_inval_ro_remote = 0; 880 m_cpt_inval_ro_cost = 0; 881 882 m_cpt_trt_rb = 0; 883 m_cpt_trt_full = 0; 884 m_cpt_put = 0; 885 m_cpt_get = 0; 886 887 m_cpt_heap_unused = 0; 888 m_cpt_slot_inval = 0; 978 889 } 979 890 980 891 981 892 ///////////////////////////////////////// 982 tmpl(void)::print_stats(bool activity_counters = true, bool stats = true)893 tmpl(void)::print_stats(bool activity_counters) 983 894 { 984 895 std::cout << "**********************************" << std::dec << std::endl; … … 993 904 << "[001] NUMBER OF CYCLES = " << m_cpt_cycles << std::endl 994 905 << std::endl 995 << "[0 02] LOCAL READ = " << m_cpt_read_miss_local << std::endl996 << "[0 03] REMOTE READ = " << m_cpt_read_miss_remote << std::endl997 << "[0 04] READ COST (FLITS * DIST) = " << m_cpt_read_miss_cost << std::endl906 << "[010] LOCAL READ = " << m_cpt_read_local << std::endl 907 << "[011] REMOTE READ = " << m_cpt_read_remote << std::endl 908 << "[012] READ COST (FLITS * DIST) = " << m_cpt_read_cost << std::endl 998 909 << std::endl 999 << "[005] LOCAL WRITE = " << m_cpt_write_local << std::endl 1000 << "[006] REMOTE WRITE = " << m_cpt_write_remote << std::endl 1001 << "[007] WRITE FLITS LOCAL = " << m_cpt_write_flits_local << std::endl 1002 << "[008] WRITE FLITS REMOTE = " << m_cpt_write_flits_remote << std::endl 1003 << "[009] WRITE COST (FLITS * DIST) = " << m_cpt_write_cost << std::endl 910 << "[020] LOCAL WRITE = " << m_cpt_write_local << std::endl 911 << "[021] REMOTE WRITE = " << m_cpt_write_remote << std::endl 912 << "[022] WRITE FLITS LOCAL = " << m_cpt_write_flits_local << std::endl 913 << "[023] WRITE FLITS REMOTE = " << m_cpt_write_flits_remote << std::endl 914 << "[024] WRITE COST (FLITS * DIST) = " << m_cpt_write_cost << std::endl 915 << "[025] WRITE L1 MISS NCC = " << "0" << std::endl 1004 916 << std::endl 1005 << "[0 10] LOCAL LL = " << m_cpt_ll_local << std::endl1006 << "[0 11] REMOTE LL = " << m_cpt_ll_remote << std::endl1007 << "[0 12] LL COST (FLITS * DIST) = " << m_cpt_ll_cost << std::endl917 << "[030] LOCAL LL = " << m_cpt_ll_local << std::endl 918 << "[031] REMOTE LL = " << m_cpt_ll_remote << std::endl 919 << "[032] LL COST (FLITS * DIST) = " << m_cpt_ll_cost << std::endl 1008 920 << std::endl 1009 << "[0 13] LOCAL SC = " << m_cpt_sc_local << std::endl1010 << "[0 14] REMOTE SC = " << m_cpt_sc_remote << std::endl1011 << "[0 15] SC COST (FLITS * DIST) = " << m_cpt_sc_cost << std::endl921 << "[040] LOCAL SC = " << m_cpt_sc_local << std::endl 922 << "[041] REMOTE SC = " << m_cpt_sc_remote << std::endl 923 << "[042] SC COST (FLITS * DIST) = " << m_cpt_sc_cost << std::endl 1012 924 << std::endl 1013 << "[0 16] LOCAL CAS = " << m_cpt_cas_local << std::endl1014 << "[0 17] REMOTE CAS = " << m_cpt_cas_remote << std::endl1015 << "[0 18] CAS COST (FLITS * DIST) = " << m_cpt_cas_cost << std::endl925 << "[050] LOCAL CAS = " << m_cpt_cas_local << std::endl 926 << "[051] REMOTE CAS = " << m_cpt_cas_remote << std::endl 927 << "[052] CAS COST (FLITS * DIST) = " << m_cpt_cas_cost << std::endl 1016 928 << std::endl 1017 << "[0 19] REQUESTS TRIG. UPDATE = " << m_cpt_update<< std::endl1018 << "[0 20] LOCAL UPDATE = " << m_cpt_update_local<< std::endl1019 << "[0 21] REMOTE UPDATE = " << m_cpt_update_remote<< std::endl1020 << "[0 22] UPDT COST (FLITS * DIST) = " << m_cpt_update_cost<< std::endl929 << "[060] REQUESTS TRIG. UPDATE = " << "0" << std::endl 930 << "[061] LOCAL UPDATE = " << "0" << std::endl 931 << "[062] REMOTE UPDATE = " << "0" << std::endl 932 << "[063] UPDT COST (FLITS * DIST) = " << "0" << std::endl 1021 933 << std::endl 1022 << "[0 23] REQUESTS TRIG. M_INV = " << m_cpt_minval << std::endl1023 << "[0 24] LOCAL M_INV = " << m_cpt_minval_local << std::endl1024 << "[0 25] REMOTE M_INV = " << m_cpt_minval_remote << std::endl1025 << "[0 26] M_INV COST (FLITS * DIST) = " << m_cpt_minval_cost << std::endl934 << "[070] REQUESTS TRIG. M_INV = " << m_cpt_minval << std::endl 935 << "[071] LOCAL M_INV = " << m_cpt_minval_local << std::endl 936 << "[072] REMOTE M_INV = " << m_cpt_minval_remote << std::endl 937 << "[073] M_INV COST (FLITS * DIST) = " << m_cpt_minval_cost << std::endl 1026 938 << std::endl 1027 << "[027] BROADCAT INVAL = " << m_cpt_binval << std::endl 939 << "[080] BROADCAT INVAL = " << m_cpt_binval << std::endl 940 << "[081] WRITE BROADCAST = " << m_cpt_write_broadcast << std::endl 941 << "[082] GETM BROADCAST = " << m_cpt_getm_broadcast << std::endl 1028 942 << std::endl 1029 << "[028] LOCAL CLEANUP = " << m_cpt_cleanup_local << std::endl 1030 << "[029] REMOTE CLEANUP = " << m_cpt_cleanup_remote << std::endl 1031 << "[030] CLNUP COST (FLITS * DIST) = " << m_cpt_cleanup_cost << std::endl 943 << "[090] LOCAL CLEANUP = " << m_cpt_cleanup_local << std::endl 944 << "[091] REMOTE CLEANUP = " << m_cpt_cleanup_remote << std::endl 945 << "[092] CLNUP COST (FLITS * DIST) = " << m_cpt_cleanup_cost << std::endl 946 << "[093] LOCAL CLEANUP DATA = " << m_cpt_cleanup_data_local << std::endl 947 << "[094] REMOTE CLEANUP DATA = " << m_cpt_cleanup_data_remote << std::endl 948 << "[095] CLEANUP DATA COST = " << m_cpt_cleanup_data_cost << std::endl 1032 949 << std::endl 950 << "[100] READ MISS = " << m_cpt_read_miss << std::endl 951 << "[101] WRITE MISS = " << m_cpt_write_miss << std::endl 952 << "[102] WRITE DIRTY = " << m_cpt_write_dirty << std::endl 953 << "[103] GETM MISS = " << m_cpt_getm_miss << std::endl 1033 954 << std::endl 1034 << "[031] READ MISS = " << m_cpt_read_miss << std::endl 1035 << "[032] WRITE MISS = " << m_cpt_write_miss << std::endl 1036 << "[033] WRITE DIRTY = " << m_cpt_write_dirty << std::endl 1037 << "[034] RD BLOCKED BY HIT IN TRT = " << m_cpt_trt_rb << std::endl 1038 << "[035] TRANS BLOCKED BY FULL TRT = " << m_cpt_trt_full << std::endl 1039 << "[036] PUT (UNIMPLEMENTED) = " << m_cpt_put << std::endl 1040 << "[037] GET (UNIMPLEMENTED) = " << m_cpt_get << std::endl 1041 << "[038] WRITE BROADCAST = " << m_cpt_write_broadcast << std::endl 955 << "[110] RD BLOCKED BY HIT IN TRT = " << m_cpt_trt_rb << std::endl 956 << "[111] TRANS BLOCKED BY FULL TRT = " << m_cpt_trt_full << std::endl 957 << "[120] PUT (UNIMPLEMENTED) = " << m_cpt_put << std::endl 958 << "[121] GET (UNIMPLEMENTED) = " << m_cpt_get << std::endl 959 << "[130] MIN HEAP SLOT AVAILABLE = " << "-1" << std::endl 1042 960 << std::endl 1043 961 << "[140] NCC TO CC (READ) = " << "0" << std::endl 962 << "[141] NCC TO CC (WRITE) = " << "0" << std::endl 963 << std::endl 964 << "[150] LOCAL GETM = " << m_cpt_getm_local << std::endl 965 << "[151] REMOTE GETM = " << m_cpt_getm_remote << std::endl 966 << "[152] GETM COST (FLITS * DIST) = " << m_cpt_getm_cost << std::endl 967 << std::endl 968 << "[160] LOCAL INVAL RO = " << m_cpt_inval_ro_local << std::endl 969 << "[161] REMOTE INVAL RO = " << m_cpt_inval_ro_remote << std::endl 970 << "[162] INVAL RO COST = " << m_cpt_inval_ro_cost << std::endl 971 << std::endl; 972 973 #if 0 1044 974 << "[050] LOCAL GETM MISS = " << m_cpt_getm_miss_local << std::endl 1045 975 << "[051] REMOTE GETM MISS = " << m_cpt_getm_miss_remote << std::endl … … 1047 977 << "[053] REMOTE GETM HIT = " << m_cpt_getm_hit_remote << std::endl 1048 978 << "[054] GETM COST (FLITS * DIST) = " << m_cpt_getm_cost << std::endl 1049 << std::endl1050 << "[055] CLEANUP WITH DATA = " << m_cpt_cleanup_with_data << std::endl1051 979 << std::endl 1052 980 << "[056] MULTI_ACK_MISS = " << m_cpt_multi_ack_miss << std::endl … … 1064 992 << "[066] EVICTED SLOT = " << m_cpt_slot_inval << std::endl 1065 993 << std::endl; 994 #endif 1066 995 } 1067 996 1068 if (stats) { 1069 std::cout << "----------------------------------" << std::dec << std::endl; 1070 std::cout << "--- Calculated Stats ---" << std::dec << std::endl; 1071 std::cout << "----------------------------------" << std::dec << std::endl; 1072 std::cout 1073 << "[100] READ TOTAL = " << m_cpt_read_miss_local + m_cpt_read_miss_remote << std::endl 1074 << "[101] READ RATE = " << (double) (m_cpt_read_miss_local + m_cpt_read_miss_remote) / m_cpt_cycles << std::endl 1075 << "[102] LOCAL READ RATE = " << (double) m_cpt_read_miss_local / m_cpt_cycles << std::endl 1076 << "[103] REMOTE READ RATE = " << (double) m_cpt_read_miss_remote / m_cpt_cycles << std::endl 1077 << "[104] READ MISS RATE = " << (double) m_cpt_read_miss / (m_cpt_read_miss_local + m_cpt_read_miss_remote) << std::endl 1078 << "[105] GETM MISS TOTAL = " << m_cpt_getm_miss_local + m_cpt_getm_miss_remote << std::endl 1079 << "[106] GETM MISS RATE = " << (double) (m_cpt_getm_miss_local + m_cpt_getm_miss_remote) / m_cpt_cycles << std::endl 1080 << "[107] LOCAL GETM MISS RATE = " << (double) m_cpt_getm_miss_local / m_cpt_cycles << std::endl 1081 << "[108] REMOTE GETM MISS RATE = " << (double) m_cpt_getm_miss_remote / m_cpt_cycles << std::endl 1082 << "[109] GETM HIT TOTAL = " << m_cpt_getm_hit_local + m_cpt_getm_hit_remote << std::endl 1083 << "[110] GETM HIT RATE = " << (double) (m_cpt_getm_hit_local + m_cpt_getm_hit_remote) / m_cpt_cycles << std::endl 1084 << "[111] LOCAL GETM HIT RATE = " << (double) m_cpt_getm_hit_local / m_cpt_cycles << std::endl 1085 << "[112] REMOTE GETM HIT RATE = " << (double) m_cpt_getm_hit_remote / m_cpt_cycles << std::endl 1086 1087 << "[113] GETM TOTAL = " << m_cpt_getm_hit_local + m_cpt_getm_hit_remote + m_cpt_getm_miss_remote + m_cpt_getm_miss_local << std::endl 1088 1089 << "[114] GETM MISS RATE = " << (double) m_cpt_read_miss / (m_cpt_getm_hit_local + m_cpt_getm_hit_remote + m_cpt_getm_miss_remote + m_cpt_getm_miss_local) << std::endl 1090 1091 << std::endl 1092 << "[115] WRITE TOTAL = " << m_cpt_write_local + m_cpt_write_remote << std::endl 1093 << "[116] WRITE RATE = " << (double) (m_cpt_write_local + m_cpt_write_remote) / m_cpt_cycles << std::endl 1094 << "[117] LOCAL WRITE RATE = " << (double) m_cpt_write_local / m_cpt_cycles << std::endl 1095 << "[118] REMOTE WRITE RATE = " << (double) m_cpt_write_remote / m_cpt_cycles << std::endl 1096 << "[119] WRITE MISS RATE = " << (double) m_cpt_write_miss / (m_cpt_write_local + m_cpt_write_remote) << std::endl 1097 << "[120] WRITE BURST TOTAL = " << m_cpt_write_flits_local + m_cpt_write_flits_remote << std::endl 1098 << "[121] WRITE BURST AVERAGE = " << (double) (m_cpt_write_flits_local + m_cpt_write_flits_remote) / (m_cpt_write_local + m_cpt_write_remote) << std::endl 1099 << "[122] LOCAL WRITE BURST AV. = " << (double) m_cpt_write_flits_local / (m_cpt_write_local + m_cpt_write_remote) << std::endl 1100 << "[123] REMOTE WRITE BURST AV = " << (double) m_cpt_write_flits_remote / (m_cpt_write_local + m_cpt_write_remote) << std::endl 1101 << std::endl 1102 << "[124] UPDATE RATE = " << (double) m_cpt_update / m_cpt_cycles << std::endl 1103 << "[125] AV. UPDATE PER UP REQ = " << (double) (m_cpt_update_local + m_cpt_update_remote) / m_cpt_update << std::endl 1104 << "[126] AV. LOC UPDT PER UP REQ = " << (double) m_cpt_update_local / m_cpt_update << std::endl 1105 << "[127] AV. REMOTE UPDT PER UP REQ = " << (double) m_cpt_update_remote / m_cpt_update << std::endl 1106 << std::endl 1107 << "[128] INVAL MULTICAST RATE = " << (double) m_cpt_minval / m_cpt_cycles << std::endl 1108 << "[129] AVE. INVAL PER M_INV = " << (double) (m_cpt_minval_local + m_cpt_minval_remote) / m_cpt_minval << std::endl 1109 << "[130] AV. LOC INV PER M_INV = " << (double) m_cpt_minval_local / m_cpt_minval << std::endl 1110 << "[131] AV. REM INV PER M_INV = " << (double) m_cpt_minval_remote / m_cpt_minval << std::endl 1111 << std::endl 1112 << "[132] INVAL BROADCAST RATE = " << (double) m_cpt_binval / m_cpt_cycles << std::endl 1113 << "[133] WRITE DIRTY RATE = " << (double) m_cpt_write_dirty / m_cpt_cycles << std::endl 1114 << std::endl 1115 << "[134] CLEANUP RATE = " << (double) (m_cpt_cleanup_local + m_cpt_cleanup_remote) / m_cpt_cycles << std::endl 1116 << "[135] LOCAL CLEANUP RATE = " << (double) m_cpt_cleanup_local / m_cpt_cycles << std::endl 1117 << "[136] REMOTE CLEANUP RATE = " << (double) m_cpt_cleanup_remote / m_cpt_cycles << std::endl 1118 << "[137] LL RATE = " << (double) (m_cpt_ll_local + m_cpt_ll_remote) / m_cpt_cycles << std::endl 1119 << "[138] LOCAL LL RATE = " << (double) m_cpt_ll_local / m_cpt_cycles << std::endl 1120 << "[139] REMOTE LL RATE = " << (double) m_cpt_ll_remote / m_cpt_cycles << std::endl 1121 << "[140] SC RATE = " << (double) (m_cpt_sc_local + m_cpt_sc_remote) / m_cpt_cycles << std::endl 1122 << "[141] LOCAL SC RATE = " << (double) m_cpt_sc_local / m_cpt_cycles << std::endl 1123 << "[142] REMOTE SC RATE = " << (double) m_cpt_sc_remote / m_cpt_cycles << std::endl 1124 << "[143] CAS RATE = " << (double) (m_cpt_cas_local + m_cpt_cas_remote) / m_cpt_cycles << std::endl 1125 << "[144] LOCAL CAS RATE = " << (double) m_cpt_cas_local / m_cpt_cycles << std::endl 1126 << "[145] REMOTE CAS RATE = " << (double) m_cpt_cas_remote / m_cpt_cycles << std::endl 1127 << "[124] MULTI ACK RATE = " << (double) (m_cpt_multi_ack_hit + m_cpt_multi_ack_miss) / m_cpt_cycles << std::endl 1128 << std::endl; 1129 } 997 // No more calculated stats 1130 998 } 1131 999 1132 1000 1133 1001 ///////////////////////////////// 1134 tmpl(/**/) 1135 1002 tmpl(/**/)::~VciMemCache() 1003 ///////////////////////////////// 1136 1004 { 1137 1005 delete [] m_seg; … … 1168 1036 ////////////////////////////////// 1169 1037 tmpl(void) ::transition() 1170 1038 ////////////////////////////////// 1171 1039 { 1172 1040 using soclib::common::uint32_log2; 1173 1041 1174 1042 // RESET 1175 if (! p_resetn.read())1043 if (! p_resetn.read()) 1176 1044 { 1177 1045 … … 1317 1185 1318 1186 // Activity counters 1319 m_cpt_reset_count = 0 ; 1320 m_cpt_read_miss_local = 0 ; 1321 m_cpt_read_miss_remote = 0 ; 1322 m_cpt_read_miss_cost = 0 ; 1323 1324 m_cpt_getm_miss_local = 0 ; 1325 m_cpt_getm_miss_remote = 0 ; 1326 1327 m_cpt_getm_hit_local = 0 ; 1328 m_cpt_getm_hit_remote = 0 ; 1329 m_cpt_getm_cost = 0 ; 1330 1331 m_cpt_write_local = 0 ; 1332 m_cpt_write_remote = 0 ; 1333 m_cpt_write_flits_local = 0 ; 1334 m_cpt_write_flits_remote = 0 ; 1335 m_cpt_write_cost = 0 ; 1336 1337 m_cpt_ll_local = 0 ; 1338 m_cpt_ll_remote = 0 ; 1339 m_cpt_ll_cost = 0 ; 1340 1341 m_cpt_sc_local = 0 ; 1342 m_cpt_sc_remote = 0 ; 1343 m_cpt_sc_cost = 0 ; 1344 1345 m_cpt_cas_local = 0 ; 1346 m_cpt_cas_remote = 0 ; 1347 m_cpt_cas_cost = 0 ; 1348 1349 m_cpt_update = 0 ; 1350 m_cpt_update_local = 0 ; 1351 m_cpt_update_remote = 0 ; 1352 m_cpt_update_cost = 0 ; 1353 1354 m_cpt_minval = 0 ; 1355 m_cpt_minval_local = 0 ; 1356 m_cpt_minval_remote = 0 ; 1357 m_cpt_minval_cost = 0 ; 1358 1359 m_cpt_binval = 0 ; 1360 1361 m_cpt_cleanup_local = 0 ; 1362 m_cpt_cleanup_remote = 0 ; 1363 m_cpt_cleanup_with_data = 0 ; 1364 m_cpt_cleanup_cost = 0 ; 1365 1366 m_cpt_multi_ack_miss = 0 ; 1367 m_cpt_multi_ack_hit = 0 ; 1368 m_cpt_multi_ack_hit_with_data = 0 ; 1369 1370 1371 m_cpt_read_miss = 0 ; 1372 m_cpt_getm_miss = 0 ; 1373 m_cpt_getm_broadcast = 0 ; 1374 m_cpt_getm_minval = 0 ; 1375 m_cpt_write_miss = 0 ; 1376 m_cpt_write_dirty = 0 ; 1377 m_cpt_write_broadcast = 0 ; 1378 m_cpt_write_minval = 0 ; 1379 m_cpt_cas_broadcast = 0 ; 1380 m_cpt_cas_minval = 0 ; 1381 m_cpt_cas_miss = 0 ; 1382 1383 m_cpt_read_locked_rb = 0 ; 1384 m_cpt_cas_locked_rb = 0 ; 1385 m_cpt_write_locked_rb = 0 ; 1386 1387 m_cpt_trt_rb = 0 ; 1388 m_cpt_trt_full = 0 ; 1389 m_cpt_put = 0 ; 1390 m_cpt_get = 0 ; 1391 1392 m_cpt_read_fsm_dir_lock = 0 ; 1393 m_cpt_read_fsm_n_dir_lock = 0 ; 1394 m_cpt_write_fsm_dir_lock = 0 ; 1395 m_cpt_write_fsm_n_dir_lock = 0 ; 1396 m_cpt_xram_rsp_fsm_dir_lock = 0 ; 1397 m_cpt_xram_rsp_fsm_n_dir_lock = 0 ; 1398 m_cpt_cas_fsm_dir_lock = 0 ; 1399 m_cpt_cas_fsm_n_dir_lock = 0 ; 1400 m_cpt_cleanup_fsm_dir_lock = 0 ; 1401 m_cpt_cleanup_fsm_n_dir_lock = 0 ; 1402 m_cpt_multi_ack_fsm_dir_lock = 0 ; 1403 m_cpt_multi_ack_fsm_n_dir_lock = 0 ; 1404 1405 m_cpt_dir_unused = 0 ; 1406 m_cpt_read_fsm_dir_used = 0 ; 1407 m_cpt_write_fsm_dir_used = 0 ; 1408 m_cpt_cas_fsm_dir_used = 0 ; 1409 m_cpt_xram_rsp_fsm_dir_used = 0 ; 1410 m_cpt_cleanup_fsm_dir_used = 0 ; 1411 m_cpt_multi_ack_fsm_dir_used = 0 ; 1412 1413 m_cpt_read_fsm_trt_lock = 0 ; 1414 m_cpt_write_fsm_trt_lock = 0 ; 1415 m_cpt_cas_fsm_trt_lock = 0 ; 1416 m_cpt_xram_rsp_fsm_trt_lock = 0 ; 1417 m_cpt_ixr_fsm_trt_lock = 0 ; 1418 1419 m_cpt_read_fsm_n_trt_lock = 0 ; 1420 m_cpt_write_fsm_n_trt_lock = 0 ; 1421 m_cpt_cas_fsm_n_trt_lock = 0 ; 1422 m_cpt_xram_rsp_fsm_n_trt_lock = 0 ; 1423 m_cpt_ixr_cmd_fsm_n_trt_lock = 0 ; 1424 m_cpt_ixr_rsp_fsm_n_trt_lock = 0 ; 1425 1426 m_cpt_read_fsm_trt_used = 0 ; 1427 m_cpt_write_fsm_trt_used = 0 ; 1428 m_cpt_cas_fsm_trt_used = 0 ; 1429 m_cpt_xram_rsp_fsm_trt_used = 0 ; 1430 m_cpt_ixr_cmd_fsm_trt_used = 0 ; 1431 m_cpt_ixr_rsp_fsm_trt_used = 0 ; 1432 m_cpt_cleanup_fsm_trt_used = 0 ; 1433 1434 m_cpt_trt_unused = 0 ; 1435 1436 m_cpt_cleanup_fsm_ivt_lock = 0 ; 1437 m_cpt_cleanup_fsm_n_ivt_lock = 0 ; 1438 1439 m_cpt_multi_ack_fsm_ivt_lock = 0 ; 1440 m_cpt_multi_ack_fsm_n_ivt_lock = 0 ; 1441 1442 m_cpt_ivt_unused = 0 ; 1443 1444 m_cpt_read_fsm_heap_lock = 0 ; 1445 m_cpt_write_fsm_heap_lock = 0 ; 1446 m_cpt_cas_fsm_heap_lock = 0 ; 1447 m_cpt_cleanup_fsm_heap_lock = 0 ; 1448 m_cpt_xram_rsp_fsm_heap_lock = 0 ; 1449 m_cpt_multi_ack_fsm_heap_lock = 0 ; 1450 1451 m_cpt_read_fsm_n_heap_lock = 0 ; 1452 m_cpt_write_fsm_n_heap_lock = 0 ; 1453 m_cpt_cas_fsm_n_heap_lock = 0 ; 1454 m_cpt_cleanup_fsm_n_heap_lock = 0 ; 1455 m_cpt_xram_rsp_fsm_n_heap_lock = 0 ; 1456 m_cpt_multi_ack_fsm_n_heap_lock = 0 ; 1457 1458 m_cpt_read_fsm_heap_used = 0 ; 1459 m_cpt_write_fsm_heap_used = 0 ; 1460 m_cpt_cas_fsm_heap_used = 0 ; 1461 m_cpt_cleanup_fsm_heap_used = 0 ; 1462 m_cpt_xram_rsp_fsm_heap_used = 0 ; 1463 m_cpt_multi_ack_fsm_heap_used = 0 ; 1464 1465 m_cpt_heap_unused = 0 ; 1466 m_cpt_slot_inval = 0 ; 1187 m_cpt_reset_count = 0; 1188 m_cpt_read_local = 0; 1189 m_cpt_read_remote = 0; 1190 m_cpt_read_cost = 0; 1191 1192 m_cpt_write_local = 0; 1193 m_cpt_write_remote = 0; 1194 m_cpt_write_flits_local = 0; 1195 m_cpt_write_flits_remote = 0; 1196 m_cpt_write_cost = 0; 1197 1198 m_cpt_ll_local = 0; 1199 m_cpt_ll_remote = 0; 1200 m_cpt_ll_cost = 0; 1201 1202 m_cpt_sc_local = 0; 1203 m_cpt_sc_remote = 0; 1204 m_cpt_sc_cost = 0; 1205 1206 m_cpt_cas_local = 0; 1207 m_cpt_cas_remote = 0; 1208 m_cpt_cas_cost = 0; 1209 1210 m_cpt_minval = 0; 1211 m_cpt_minval_local = 0; 1212 m_cpt_minval_remote = 0; 1213 m_cpt_minval_cost = 0; 1214 1215 m_cpt_binval = 0; 1216 m_cpt_write_broadcast = 0; 1217 m_cpt_getm_broadcast = 0; 1218 1219 m_cpt_cleanup_local = 0; 1220 m_cpt_cleanup_remote = 0; 1221 m_cpt_cleanup_cost = 0; 1222 m_cpt_cleanup_data_local = 0; 1223 m_cpt_cleanup_data_remote = 0; 1224 m_cpt_cleanup_data_cost = 0; 1225 1226 m_cpt_read_miss = 0; 1227 m_cpt_write_miss = 0; 1228 m_cpt_write_dirty = 0; 1229 m_cpt_getm_miss = 0; 1230 1231 m_cpt_getm_local = 0; 1232 m_cpt_getm_remote = 0; 1233 m_cpt_getm_cost = 0; 1234 1235 m_cpt_inval_ro_local = 0; 1236 m_cpt_inval_ro_remote = 0; 1237 m_cpt_inval_ro_cost = 0; 1238 1239 m_cpt_trt_rb = 0; 1240 m_cpt_trt_full = 0; 1241 m_cpt_put = 0; 1242 m_cpt_get = 0; 1243 1244 m_cpt_heap_unused = 0; 1245 m_cpt_slot_inval = 0; 1246 1467 1247 return; 1468 1248 } … … 1515 1295 1516 1296 #if DEBUG_MEMC_GLOBAL 1517 if (m_debug)1297 if (m_debug) 1518 1298 { 1519 1299 std::cout … … 1565 1345 ////////////////// 1566 1346 case TGT_CMD_IDLE: // waiting a VCI command (RAM or CONFIG) 1567 if (p_vci_tgt.cmdval)1347 if (p_vci_tgt.cmdval) 1568 1348 { 1569 1349 1570 1350 #if DEBUG_MEMC_TGT_CMD 1571 if (m_debug)1351 if (m_debug) 1572 1352 std::cout << " <MEMC " << name() 1573 1353 << " TGT_CMD_IDLE> Receive command from srcid " … … 1587 1367 { 1588 1368 found = true; 1589 if ( 1369 if (m_seg[seg_id]->special() ) config = true; 1590 1370 } 1591 1371 } … … 1593 1373 if (!found) /////////// out of segment error 1594 1374 { 1595 r_tgt_cmd_fsm 1596 } 1597 else if ( 1375 r_tgt_cmd_fsm = TGT_CMD_ERROR; 1376 } 1377 else if (config ) /////////// configuration command 1598 1378 { 1599 1379 if (!p_vci_tgt.eop.read()) r_tgt_cmd_fsm = TGT_CMD_ERROR; 1600 else 1380 else r_tgt_cmd_fsm = TGT_CMD_CONFIG; 1601 1381 } 1602 1382 else //////////// memory access 1603 1383 { 1604 if ( p_vci_tgt.cmd.read() == vci_param_int::CMD_READ)1384 if (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) 1605 1385 { 1606 1386 // check that the pktid is either : … … 1615 1395 r_tgt_cmd_fsm = TGT_CMD_READ; 1616 1396 } 1617 else if (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE)1397 else if (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) 1618 1398 { 1619 1399 // check that the pktid is TYPE_WRITE … … 1622 1402 r_tgt_cmd_fsm = TGT_CMD_WRITE; 1623 1403 } 1624 else if (p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ)1404 else if (p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) 1625 1405 { 1626 1406 // check that the pktid is TYPE_LL … … 1631 1411 r_tgt_cmd_fsm = TGT_CMD_READ; 1632 1412 } 1633 else if (p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP)1413 else if (p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP) 1634 1414 { 1635 1415 // check that the pktid is either : … … 1642 1422 "The type specified in the pktid field is incompatible with the NOP CMD"); 1643 1423 1644 if ((p_vci_tgt.pktid.read() & 0x7) == TYPE_CAS) r_tgt_cmd_fsm = TGT_CMD_CAS;1645 else r_tgt_cmd_fsm = TGT_CMD_WRITE;1424 if ((p_vci_tgt.pktid.read() & 0x7) == TYPE_CAS) r_tgt_cmd_fsm = TGT_CMD_CAS; 1425 else r_tgt_cmd_fsm = TGT_CMD_WRITE; 1646 1426 } 1647 1427 else … … 1657 1437 1658 1438 // wait if pending request 1659 if (r_tgt_cmd_to_tgt_rsp_req.read()) break;1439 if (r_tgt_cmd_to_tgt_rsp_req.read()) break; 1660 1440 1661 1441 // consume all the command packet flits before sending response error 1662 if ( p_vci_tgt.cmdval and p_vci_tgt.eop)1442 if (p_vci_tgt.cmdval and p_vci_tgt.eop) 1663 1443 { 1664 1444 r_tgt_cmd_to_tgt_rsp_srcid = p_vci_tgt.srcid.read(); … … 1670 1450 1671 1451 #if DEBUG_MEMC_TGT_CMD 1672 if (m_debug)1452 if (m_debug) 1673 1453 std::cout << " <MEMC " << name() 1674 1454 << " TGT_CMD_ERROR> Segmentation violation:" … … 1885 1665 uint32_t wdata = p_vci_tgt.wdata.read(); 1886 1666 1887 if ( 1667 if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) // get lock 1888 1668 and (cell == MEMC_LOCK) ) 1889 1669 { … … 1893 1673 r_config_lock = true; 1894 1674 } 1895 else if ( 1675 else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // release lock 1896 1676 and (cell == MEMC_LOCK)) 1897 1677 { … … 1900 1680 r_config_lock = false; 1901 1681 } 1902 else if ( 1682 else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_lo 1903 1683 and (cell == MEMC_ADDR_LO)) 1904 1684 { … … 1911 1691 ((addr_t)wdata); 1912 1692 } 1913 else if ( 1693 else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_hi 1914 1694 and (cell == MEMC_ADDR_HI)) 1915 1695 { … … 1919 1699 (((addr_t) wdata) << 32); 1920 1700 } 1921 else if ( 1701 else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set buf_lines 1922 1702 and (cell == MEMC_BUF_LENGTH)) 1923 1703 { … … 1929 1709 r_config_rsp_lines = 0; 1930 1710 } 1931 else if ( 1711 else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set cmd type 1932 1712 and (cell == MEMC_CMD_TYPE)) 1933 1713 { … … 1945 1725 } 1946 1726 1947 if ( 1727 if (need_rsp ) 1948 1728 { 1949 1729 // blocked if previous pending request to TGT_RSP FSM 1950 if ( 1730 if (r_tgt_cmd_to_tgt_rsp_req.read() ) break; 1951 1731 1952 1732 r_tgt_cmd_to_tgt_rsp_srcid = p_vci_tgt.srcid.read(); … … 1964 1744 1965 1745 #if DEBUG_MEMC_TGT_CMD 1966 if (m_debug)1746 if (m_debug) 1967 1747 std::cout << " <MEMC " << name() << " TGT_CMD_CONFIG> Configuration request:" 1968 1748 << " address = " << std::hex << p_vci_tgt.address.read() … … 1978 1758 1979 1759 // check that the read does not cross a cache line limit. 1980 if ( 1760 if (((m_x[(addr_t) p_vci_tgt.address.read()]+ (p_vci_tgt.plen.read() >>2)) > 16) and 1981 1761 (p_vci_tgt.cmd.read() != vci_param_int::CMD_LOCKED_READ)) 1982 1762 { … … 1986 1766 } 1987 1767 // check single flit 1988 if (!p_vci_tgt.eop.read())1768 if (!p_vci_tgt.eop.read()) 1989 1769 { 1990 1770 std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_READ state" … … 1993 1773 } 1994 1774 // check plen for LL 1995 if ( 1775 if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) and 1996 1776 (p_vci_tgt.plen.read() != 8) ) 1997 1777 { … … 2001 1781 } 2002 1782 2003 if ( 1783 if (p_vci_tgt.cmdval and m_cmd_read_addr_fifo.wok() ) 2004 1784 { 2005 1785 2006 1786 #if DEBUG_MEMC_TGT_CMD 2007 if (m_debug)1787 if (m_debug) 2008 1788 std::cout << " <MEMC " << name() << " TGT_CMD_READ> Push into read_fifo:" 2009 1789 << " address = " << std::hex << p_vci_tgt.address.read() … … 2016 1796 // <Activity counters> 2017 1797 if (p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) { 2018 if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_ll_local++; 2019 else m_cpt_ll_remote++; 2020 m_cpt_ll_cost += req_distance(p_vci_tgt.srcid.read()); // LL on a single word 2021 } 2022 else { 2023 if ((p_vci_tgt.pktid.read() & 0x7) == TYPE_WRITE) 2024 { 2025 if ((p_vci_tgt.pktid.read() & 0x8) == 0x8) 2026 { 2027 if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_getm_hit_local++; 2028 else m_cpt_getm_hit_remote++; 2029 } 2030 else 2031 { 2032 if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_getm_miss_local++; 2033 else m_cpt_getm_miss_remote++; 2034 } 2035 m_cpt_getm_cost += req_distance(p_vci_tgt.srcid.read()); 1798 if (is_local_req(p_vci_tgt.srcid.read())) 1799 { 1800 m_cpt_ll_local++; 2036 1801 } 2037 1802 else 2038 1803 { 2039 if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_read_miss_local++; 2040 else m_cpt_read_miss_remote++; 2041 m_cpt_read_miss_cost += req_distance(p_vci_tgt.srcid.read()); 2042 } 1804 m_cpt_ll_remote++; 1805 } 1806 // (1 (CMD) + 2 (RSP)) VCI flits for LL => 2 + 3 dspin flits 1807 m_cpt_ll_cost += 5 * req_distance(p_vci_tgt.srcid.read()); // LL on a single word 1808 } 1809 else if ((p_vci_tgt.pktid.read() & 0x7) == TYPE_WRITE) 1810 { 1811 if (is_local_req(p_vci_tgt.srcid.read())) 1812 { 1813 m_cpt_getm_local++; 1814 } 1815 else 1816 { 1817 m_cpt_getm_remote++; 1818 } 1819 // (1 (CMD) + m_words (RSP)) flits VCI => 2 + m_words + 1 flits dspin 1820 m_cpt_getm_cost += (3 + m_words) * req_distance(p_vci_tgt.srcid.read()); 1821 } 1822 else 1823 { 1824 if (is_local_req(p_vci_tgt.srcid.read())) 1825 { 1826 m_cpt_read_local++; 1827 } 1828 else 1829 { 1830 m_cpt_read_remote++; 1831 } 1832 // (1 (CMD) + m_words (RSP)) flits VCI => 2 + m_words + 1 flits dspin 1833 m_cpt_read_cost += (3 + m_words) * req_distance(p_vci_tgt.srcid.read()); 2043 1834 } 2044 1835 // </Activity counters> … … 2049 1840 /////////////////// 2050 1841 case TGT_CMD_WRITE: 2051 if (p_vci_tgt.cmdval and m_cmd_write_addr_fifo.wok())2052 { 2053 1842 if (p_vci_tgt.cmdval and m_cmd_write_addr_fifo.wok()) 1843 { 1844 uint32_t plen = p_vci_tgt.plen.read(); 2054 1845 #if DEBUG_MEMC_TGT_CMD 2055 if (m_debug)1846 if (m_debug) 2056 1847 std::cout << " <MEMC " << name() << " TGT_CMD_WRITE> Push into write_fifo:" 2057 1848 << " address = " << std::hex << p_vci_tgt.address.read() … … 2061 1852 << " / wdata = " << p_vci_tgt.wdata.read() 2062 1853 << " / be = " << p_vci_tgt.be.read() 2063 << " / plen = " << std::dec << p _vci_tgt.plen.read()<< std::endl;1854 << " / plen = " << std::dec << plen << std::endl; 2064 1855 #endif 2065 1856 cmd_write_fifo_put = true; 2066 1857 // <Activity counters> 2067 1858 if (p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP) { 2068 m_cpt_sc_cost += req_distance(p_vci_tgt.srcid.read()); 1859 // (2 (CMD) + 1 (RSP)) flits VCI => 4 + (1 (success) || 2 (failure)) flits dspin 1860 m_cpt_sc_cost += 5 * req_distance(p_vci_tgt.srcid.read()); 2069 1861 } 2070 1862 else { 2071 if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_write_flits_local++; 2072 else m_cpt_write_flits_remote++; 2073 m_cpt_write_cost += req_distance(p_vci_tgt.srcid.read()); 1863 if (is_local_req(p_vci_tgt.srcid.read())) 1864 { 1865 m_cpt_write_flits_local++; 1866 } 1867 else 1868 { 1869 m_cpt_write_flits_remote++; 1870 } 1871 // (burst_size (CMD) + 1 (RSP) flits VCI => 2 + burst_size + 1 flits dspin 1872 m_cpt_write_cost += (3 + (plen >> 2)) * req_distance(p_vci_tgt.srcid.read()); 2074 1873 } 2075 1874 // </Activity counters> … … 2078 1877 // <Activity counters> 2079 1878 if (p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP) { 2080 if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_sc_local++; 2081 else m_cpt_sc_remote++; 2082 1879 if (is_local_req(p_vci_tgt.srcid.read())) 1880 { 1881 m_cpt_sc_local++; 1882 } 1883 else 1884 { 1885 m_cpt_sc_remote++; 1886 } 2083 1887 } 2084 1888 else { 2085 if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_write_local++; 2086 else m_cpt_write_remote++; 1889 if (is_local_req(p_vci_tgt.srcid.read())) 1890 { 1891 m_cpt_write_local++; 1892 } 1893 else 1894 { 1895 m_cpt_write_remote++; 1896 } 2087 1897 } 2088 1898 // </Activity counters> … … 2093 1903 ///////////////// 2094 1904 case TGT_CMD_CAS: 2095 if ((p_vci_tgt.plen.read() != 8) and (p_vci_tgt.plen.read() != 16))1905 if ((p_vci_tgt.plen.read() != 8) and (p_vci_tgt.plen.read() != 16)) 2096 1906 { 2097 1907 std::cout << "VCI_MEM_CACHE ERROR " << name() << " TGT_CMD_CAS state" … … 2100 1910 } 2101 1911 2102 if (p_vci_tgt.cmdval and m_cmd_cas_addr_fifo.wok())1912 if (p_vci_tgt.cmdval and m_cmd_cas_addr_fifo.wok()) 2103 1913 { 2104 1914 2105 1915 #if DEBUG_MEMC_TGT_CMD 2106 if (m_debug)1916 if (m_debug) 2107 1917 std::cout << " <MEMC " << name() << " TGT_CMD_CAS> Pushing command into cmd_cas_fifo:" 2108 1918 << " address = " << std::hex << p_vci_tgt.address.read() … … 2117 1927 if (p_vci_tgt.eop) { 2118 1928 // <Activity counters> 2119 if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_cas_local++; 2120 else m_cpt_cas_remote++; 2121 m_cpt_cas_cost += req_distance(p_vci_tgt.srcid.read()); 1929 if (is_local_req(p_vci_tgt.srcid.read())) 1930 { 1931 m_cpt_cas_local++; 1932 } 1933 else 1934 { 1935 m_cpt_cas_remote++; 1936 } 1937 // (2 (CMD) + 1 (RSP)) flits VCI => 4 + (1 (success) || 2 (failure)) flits dspin 1938 m_cpt_cas_cost += 5 * req_distance(p_vci_tgt.srcid.read()); 2122 1939 // </Activity counters> 2123 1940 r_tgt_cmd_fsm = TGT_CMD_IDLE; … … 2151 1968 uint64_t flit = m_cc_receive_to_multi_ack_fifo.read(); 2152 1969 2153 if ( not multi_ack_fifo_rok)1970 if (not multi_ack_fifo_rok) 2154 1971 break; 2155 1972 2156 size_t ivt_index = DspinDhccpParam::dspin_get(flit,2157 Dspin DhccpParam::MULTI_ACK_UPDT_INDEX);2158 2159 bool miss_updt = DspinDhccpParam::dspin_get(flit,2160 Dspin DhccpParam::MULTI_ACK_UPDT_MISS);2161 2162 bool eop = Dspin DhccpParam::dspin_get(flit, DspinDhccpParam::P2M_EOP) == 0x1;1973 size_t ivt_index = DspinHmesiParam::dspin_get(flit, 1974 DspinHmesiParam::MULTI_ACK_UPDT_INDEX); 1975 1976 bool miss_updt = DspinHmesiParam::dspin_get(flit, 1977 DspinHmesiParam::MULTI_ACK_UPDT_MISS); 1978 1979 bool eop = DspinHmesiParam::dspin_get(flit, DspinHmesiParam::P2M_EOP) == 0x1; 2163 1980 2164 1981 cc_receive_to_multi_ack_fifo_get = true; … … 2171 1988 r_multi_ack_miss_updt = miss_updt; 2172 1989 2173 if(miss_updt) 2174 m_cpt_multi_ack_miss ++; 2175 else 2176 m_cpt_multi_ack_hit ++; 2177 2178 if( not eop) 2179 { 2180 r_multi_ack_fsm = MULTI_ACK_GET_DATA; 1990 if (not eop) 1991 { 2181 1992 r_multi_ack_need_data = true; 2182 1993 r_multi_ack_data_index = 0; 2183 m_cpt_multi_ack_hit_with_data ++;1994 r_multi_ack_fsm = MULTI_ACK_GET_DATA; 2184 1995 } 2185 1996 else 2186 1997 { 1998 r_multi_ack_need_data = false; 2187 1999 r_multi_ack_fsm = MULTI_ACK_DIR_REQ; 2188 r_multi_ack_need_data = false;2189 2000 } 2190 2001 2191 2002 #if DEBUG_MEMC_MULTI_ACK 2192 if (m_debug)2003 if (m_debug) 2193 2004 { 2194 2005 if (multi_ack_fifo_rok) … … 2211 2022 2212 2023 uint32_t data = 2213 Dspin DhccpParam::dspin_get (flit, DspinDhccpParam::CLEANUP_DATA_UPDT);2214 2215 bool eop = Dspin DhccpParam::dspin_get(flit, DspinDhccpParam::P2M_EOP) == 0x1;2024 DspinHmesiParam::dspin_get (flit, DspinHmesiParam::CLEANUP_DATA_UPDT); 2025 2026 bool eop = DspinHmesiParam::dspin_get(flit, DspinHmesiParam::P2M_EOP) == 0x1; 2216 2027 #if DEBUG_MEMC_CLEANUP 2217 if (m_debug)2028 if (m_debug) 2218 2029 { 2219 2030 std::cout … … 2242 2053 case MULTI_ACK_IVT_LOCK: 2243 2054 { 2244 m_cpt_multi_ack_fsm_ivt_lock ++; 2245 if(r_alloc_ivt_fsm.read() != ALLOC_IVT_MULTI_ACK) break; 2246 2247 m_cpt_multi_ack_fsm_n_ivt_lock ++; 2055 if (r_alloc_ivt_fsm.read() != ALLOC_IVT_MULTI_ACK) break; 2248 2056 2249 2057 assert( r_alloc_dir_fsm.read() == ALLOC_DIR_MULTI_ACK && " BAD ALLOC_DIR_MULTI_ACK IN MULTI_ACK_IVT_LOCK STATE"); 2250 size_t index 2251 size_t count 2252 size_t nline 2058 size_t index = r_multi_ack_ivt_index.read(); 2059 size_t count = m_ivt.count(index); 2060 size_t nline = m_ivt.nline(index); 2253 2061 r_multi_ack_nline = nline; 2254 2062 r_multi_ack_srcid = m_ivt.srcid(index); … … 2256 2064 r_multi_ack_pktid = m_ivt.pktid(index); 2257 2065 r_multi_ack_rsp = m_ivt.need_rsp(index); 2258 //bool is_valid = m_ivt.is_valid(index); 2259 2260 // if(r_multi_ack_miss_updt.read()) 2261 //{ 2262 r_multi_ack_fsm = MULTI_ACK_DIR_LOCK; // this way may be bring about the problem of critical path 2263 //} 2264 //else 2265 //{ 2266 bool is_updt = m_ivt.is_update(index); 2066 uint32_t srcid = m_ivt.srcid(index); 2267 2067 2268 assert(is_updt && "MULTI_ACK: is not an updt index for a multi ack rsp"); 2269 assert(count == 1 && "there is only one copy in the memc"); 2270 2271 // r_multi_ack_fsm = MULTI_ACK_IVT_CLEAR; 2068 // <Activity Counters> 2069 // We count "read-only invalidations" at the same place as 2070 // multi ack. 2071 // The idea is that a RO inval is always responded by a multi ack, 2072 // and that a multi ack is sent only for inval RO. 2073 // Thus, we add one to the cost for the inval RO fleet, and 2074 // depending on the response, we add either 1 or m_words + 1 for the cost for the multi ack flits 2075 if (r_multi_ack_need_data.read()) 2076 { 2077 // multi_ack with data 2078 if (is_local_req(srcid)) 2079 { 2080 m_cpt_inval_ro_local++; 2081 } 2082 else 2083 { 2084 m_cpt_inval_ro_remote++; 2085 } 2086 // 2 flits for inval RO + (m_words + 1) flits for the multi ack 2087 m_cpt_inval_ro_cost += (m_words + 1) * req_distance(srcid); 2088 } 2089 else 2090 { 2091 // multi_ack without data 2092 if (is_local_req(srcid)) 2093 { 2094 m_cpt_inval_ro_local++; 2095 } 2096 else 2097 { 2098 m_cpt_inval_ro_remote++; 2099 } 2100 // 2 flits for inval RO + 1 flit for the multi ack 2101 m_cpt_inval_ro_cost += 3 * req_distance(srcid); // 1 flit 2102 } 2103 // </Activity Counters> 2104 2105 2106 r_multi_ack_fsm = MULTI_ACK_DIR_LOCK; // this way may be bring about the problem of critical path 2107 bool is_updt = m_ivt.is_update(index); 2108 2109 assert(is_updt && "MULTI_ACK: is not an updt index for a multi ack rsp"); 2110 assert(count == 1 && "there is only one copy in the memc"); 2272 2111 2273 2112 #if DEBUG_MEMC_MULTI_ACK 2274 if (m_debug)2113 if (m_debug) 2275 2114 std::cout << " <MEMC " << name() 2276 2115 << " MULTI_ACK_IVT_LOCK> " … … 2283 2122 case MULTI_ACK_IVT_CLEAR: 2284 2123 { 2285 if (r_alloc_ivt_fsm.read() != ALLOC_IVT_MULTI_ACK )2124 if (r_alloc_ivt_fsm.read() != ALLOC_IVT_MULTI_ACK ) 2286 2125 { 2287 2126 std::cout … … 2297 2136 2298 2137 #if DEBUG_MEMC_MULTI_ACK 2299 if (m_debug)2138 if (m_debug) 2300 2139 std::cout << " <MEMC " << name() 2301 2140 << " MULTI_ACK_IVT_CLEAR> IVT clear:" … … 2308 2147 case MULTI_ACK_DIR_REQ: // Get the lock to the directory 2309 2148 { 2310 m_cpt_multi_ack_fsm_dir_lock ++; 2311 if(r_alloc_dir_fsm.read() != ALLOC_DIR_MULTI_ACK) break; 2149 if (r_alloc_dir_fsm.read() != ALLOC_DIR_MULTI_ACK) break; 2312 2150 2313 2151 r_multi_ack_fsm = MULTI_ACK_IVT_LOCK; 2314 2152 //std::cout << " MEM_CACHE : CLEANUP_DIR_REQ" << std::endl; 2315 m_cpt_multi_ack_fsm_n_dir_lock ++;2316 2153 2317 2154 #if DEBUG_MEMC_CLEANUP 2318 if (m_debug)2155 if (m_debug) 2319 2156 std::cout << " <MEMC " << name() << " MULTI_ACK_DIR_REQ> Requesting DIR lock" << std::endl; 2320 2157 #endif … … 2325 2162 case MULTI_ACK_DIR_LOCK: //updt data with the registers which have saved the set and way 2326 2163 { 2327 if (r_alloc_dir_fsm.read() != ALLOC_DIR_MULTI_ACK)2164 if (r_alloc_dir_fsm.read() != ALLOC_DIR_MULTI_ACK) 2328 2165 { 2329 2166 std::cout … … 2349 2186 2350 2187 #if DEBUG_MEMC_MULTI_ACK 2351 if (m_debug)2188 if (m_debug) 2352 2189 { 2353 2190 std::cout … … 2365 2202 } 2366 2203 #endif 2367 assert( (entry.state == ENTRY_LOCKED) && "mutli rsp check the entry, the line is not locked!!!");2204 assert((entry.state == ENTRY_LOCKED) && "multi rsp check the entry, the line is not locked!!!"); 2368 2205 2369 if (r_multi_ack_miss_updt.read() and entry.count) //cache L1 has sent the cleanup when it receives the cc_updt request,2206 if (r_multi_ack_miss_updt.read() and entry.count) //cache L1 has sent the cleanup when it receives the cc_updt request, 2370 2207 { 2371 2208 r_multi_ack_fsm = MULTI_ACK_IVT_CHANGE; 2372 2209 } 2373 else if (not entry.count or match_ll) // The line has been already evicted from cache L12210 else if (not entry.count or match_ll) // The line has been already evicted from cache L1 2374 2211 { 2375 2212 assert(((entry.count == 1) or (entry.count == 0)) && "multi ack for a ll request, count is 1"); 2376 r_multi_ack_fsm 2213 r_multi_ack_fsm = MULTI_ACK_DIR_UPDT; 2377 2214 } 2378 2215 else 2379 2216 { 2380 r_multi_ack_fsm 2217 r_multi_ack_fsm = MULTI_ACK_HEAP_REQ; 2381 2218 } 2382 2219 break; 2383 2220 } 2384 2221 ///////////// 2385 case MULTI_ACK_IVT_CHANGE: // release all locks and retry from beginning2222 case MULTI_ACK_IVT_CHANGE: 2386 2223 { 2387 if (r_alloc_ivt_fsm.read() != ALLOC_IVT_MULTI_ACK)2224 if (r_alloc_ivt_fsm.read() != ALLOC_IVT_MULTI_ACK) 2388 2225 { 2389 2226 std::cout … … 2396 2233 m_ivt.change(r_multi_ack_ivt_index.read()); 2397 2234 #if DEBUG_MEMC_MULTI_ACK 2398 if (m_debug)2235 if (m_debug) 2399 2236 { 2400 2237 std::cout << " <MEMC " << name() … … 2408 2245 case MULTI_ACK_DIR_UPDT: 2409 2246 { 2410 if (r_alloc_dir_fsm.read() != ALLOC_DIR_MULTI_ACK)2247 if (r_alloc_dir_fsm.read() != ALLOC_DIR_MULTI_ACK) 2411 2248 { 2412 2249 std::cout … … 2420 2257 bool match_ll = ((r_multi_ack_pktid.read() & 0x07) == TYPE_LL); 2421 2258 2422 if (r_multi_ack_need_data.read())2423 { 2424 for (size_t word=0; word<m_words; word++)2259 if (r_multi_ack_need_data.read()) 2260 { 2261 for (size_t word = 0; word<m_words; word++) 2425 2262 { 2426 2263 m_cache_data.write(r_multi_ack_way.read(), … … 2429 2266 r_multi_ack_data[word]); 2430 2267 } 2431 // addr_t min = r_multi_ack_nline.read()*m_words*4 ;2432 // addr_t max = r_multi_ack_nline.read()*m_words*4 + (m_words - 1)*4;2433 // m_llsc_table.sw(min, max);2434 2435 2268 } 2436 2269 else 2437 2270 { 2438 m_cache_data.read_line( 2439 2440 2271 m_cache_data.read_line(r_multi_ack_way.read(), 2272 r_multi_ack_set.read(), 2273 r_multi_ack_data); 2441 2274 } 2442 2275 2443 2276 DirectoryEntry entry; 2444 entry.is_cnt 2445 entry.dirty 2446 entry.tag 2447 entry.lock 2448 entry.ptr 2449 2450 if (match_ll)2451 { 2452 entry.owner.srcid 2453 entry.count 2277 entry.is_cnt = false; 2278 entry.dirty = r_multi_ack_dirty.read() or r_multi_ack_need_data.read(); 2279 entry.tag = r_multi_ack_tag.read(); 2280 entry.lock = r_multi_ack_lock.read(); 2281 entry.ptr = 0; 2282 2283 if (match_ll) 2284 { 2285 entry.owner.srcid = r_multi_ack_copy.read(); 2286 entry.count = r_multi_ack_count.read(); 2454 2287 } 2455 2288 else 2456 2289 { 2457 entry.owner.srcid = r_multi_ack_srcid.read(); 2458 entry.count = 1; 2459 } 2460 2461 2462 // if( (r_multi_ack_pktid.read() & 0x07) == 0x03 or match_ll) 2463 // { 2464 entry.state = ENTRY_SHARED; // MISS INST 2465 // } 2466 // else 2467 // { 2468 // entry.state = ENTRY_EXCLUSIVE; // MISS DATA 2469 // } 2470 2471 if((r_multi_ack_pktid.read() & 0x7) == 0x03) 2290 entry.owner.srcid = r_multi_ack_srcid.read(); 2291 entry.count = 1; 2292 } 2293 2294 entry.state = ENTRY_SHARED; // MISS INST 2295 2296 if ((r_multi_ack_pktid.read() & 0x7) == 0x03) 2472 2297 { 2473 2298 entry.owner.inst = true; … … 2483 2308 r_multi_ack_fsm = MULTI_ACK_IVT_CLEAR; 2484 2309 #if DEBUG_MEMC_MULTI_ACK 2485 if (m_debug)2310 if (m_debug) 2486 2311 { 2487 2312 std::cout << " <MEMC " << name() << " MULTI_ACK_DIR_UPDT>" … … 2499 2324 // wait if pending request to the TGT_RSP FSM 2500 2325 { 2501 if (r_multi_ack_to_tgt_rsp_req.read()) break;2502 2503 for (size_t i = 0; i<m_words; i++)2326 if (r_multi_ack_to_tgt_rsp_req.read()) break; 2327 2328 for (size_t i = 0; i<m_words; i++) 2504 2329 { 2505 2330 r_multi_ack_to_tgt_rsp_data[i] = r_multi_ack_data[i].read(); 2506 2331 } 2507 2332 // no pending request 2508 r_multi_ack_to_tgt_rsp_req 2509 if (r_read_to_multi_ack_req.read() and (r_read_to_multi_ack_nline.read() == r_multi_ack_nline.read()))2510 { 2511 r_multi_ack_to_tgt_rsp_word 2512 r_multi_ack_to_tgt_rsp_length 2513 r_read_to_multi_ack_req 2333 r_multi_ack_to_tgt_rsp_req = true; 2334 if (r_read_to_multi_ack_req.read() and (r_read_to_multi_ack_nline.read() == r_multi_ack_nline.read())) 2335 { 2336 r_multi_ack_to_tgt_rsp_word = r_read_to_multi_ack_first_word.read(); 2337 r_multi_ack_to_tgt_rsp_length = r_read_to_multi_ack_length.read(); 2338 r_read_to_multi_ack_req = false; 2514 2339 } 2515 2340 else 2516 2341 { 2517 r_multi_ack_to_tgt_rsp_word = 0; 2518 r_multi_ack_to_tgt_rsp_length = 16; 2519 } 2520 2521 r_multi_ack_to_tgt_ll_key = r_read_to_multi_ack_ll_key.read(); 2522 r_multi_ack_to_tgt_rsp_srcid = r_multi_ack_srcid.read(); 2523 r_multi_ack_to_tgt_rsp_trdid = r_multi_ack_trdid.read(); 2524 2525 // if(r_multi_ack_rsp_shared.read()) // rsp read with shared or exclusive state 2526 // { 2527 r_multi_ack_to_tgt_rsp_pktid = r_multi_ack_pktid.read(); 2528 // } 2529 // else 2530 //{ 2531 // r_multi_ack_to_tgt_rsp_pktid = 0x08 + r_multi_ack_pktid.read(); 2532 //} 2533 2534 r_multi_ack_fsm = MULTI_ACK_IDLE; 2342 r_multi_ack_to_tgt_rsp_word = 0; 2343 r_multi_ack_to_tgt_rsp_length = 16; 2344 } 2345 2346 r_multi_ack_to_tgt_ll_key = r_read_to_multi_ack_ll_key.read(); 2347 r_multi_ack_to_tgt_rsp_srcid = r_multi_ack_srcid.read(); 2348 r_multi_ack_to_tgt_rsp_trdid = r_multi_ack_trdid.read(); 2349 r_multi_ack_to_tgt_rsp_pktid = r_multi_ack_pktid.read(); 2350 2351 r_multi_ack_fsm = MULTI_ACK_IDLE; 2535 2352 2536 2353 #if DEBUG_MEMC_MULTI_ACK 2537 if (m_debug)2354 if (m_debug) 2538 2355 std::cout << " <MEMC " << name() << " MULTI_ACK_RSP>" 2539 2356 << " Send a response to a previous read/ll request: " … … 2553 2370 case MULTI_ACK_HEAP_REQ: // Get the lock to the HEAP directory 2554 2371 { 2555 m_cpt_multi_ack_fsm_n_heap_lock ++; 2556 if(r_alloc_heap_fsm.read() == ALLOC_HEAP_MULTI_ACK) 2372 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_MULTI_ACK) 2557 2373 { 2558 2374 r_multi_ack_fsm = MULTI_ACK_HEAP_LOCK; 2559 2375 } 2560 2376 2561 m_cpt_multi_ack_fsm_heap_lock ++;2562 2377 #if DEBUG_MEMC_MULTI_ACK 2563 if (m_debug)2378 if (m_debug) 2564 2379 std::cout << " <MEMC " << name() << " MULTI_ACK_HEAP_REQ>" 2565 2380 << " Requesting HEAP lock " << std::endl; … … 2571 2386 // and prepare the HEAP update 2572 2387 { 2573 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_MULTI_ACK and2388 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_MULTI_ACK and 2574 2389 r_alloc_dir_fsm.read() == ALLOC_DIR_MULTI_ACK) 2575 2390 { 2576 if (r_multi_ack_need_data.read())2577 { 2578 for (size_t word=0; word<m_words ; word++)2391 if (r_multi_ack_need_data.read()) 2392 { 2393 for (size_t word = 0; word < m_words ; word++) 2579 2394 { 2580 2395 m_cache_data.write(r_multi_ack_way.read(), … … 2583 2398 r_multi_ack_data[word]); 2584 2399 } 2585 2586 // addr_t min = r_multi_ack_nline.read()*m_words*4 ;2587 // addr_t max = r_multi_ack_nline.read()*m_words*4 + (m_words - 1)*4;2588 // m_llsc_table.sw(min, max);2589 2590 2400 } 2591 2401 else 2592 2402 { 2593 m_cache_data.read_line( 2594 2595 2403 m_cache_data.read_line(r_multi_ack_way.read(), 2404 r_multi_ack_set.read(), 2405 r_multi_ack_data); 2596 2406 } 2597 2407 … … 2606 2416 entry.dirty = r_multi_ack_dirty.read() or r_multi_ack_need_data.read(); 2607 2417 entry.tag = r_multi_ack_tag.read(); 2608 if (not go_cnt) // Not entering counter mode2609 { 2610 entry.owner.srcid 2611 entry.owner.inst 2612 entry.ptr 2613 2614 HeapEntry heap_entry 2615 2616 r_multi_ack_next_ptr 2617 r_multi_ack_last_free 2618 r_multi_ack_fsm 2418 if (not go_cnt) // Not entering counter mode 2419 { 2420 entry.owner.srcid = r_multi_ack_copy.read(); 2421 entry.owner.inst = r_multi_ack_copy_inst.read(); 2422 entry.ptr = m_heap.next_free_ptr(); // set pointer on the heap 2423 2424 HeapEntry heap_entry = m_heap.next_free_entry(); 2425 2426 r_multi_ack_next_ptr = heap_entry.next; 2427 r_multi_ack_last_free = (heap_entry.next == m_heap.next_free_ptr()); 2428 r_multi_ack_fsm = MULTI_ACK_HEAP_WRITE; // add an entry in the HEAP 2619 2429 } 2620 2430 else // Entering Counter mode … … 2629 2439 2630 2440 #if DEBUG_MEMC_MULTI_ACK 2631 if (m_debug)2441 if (m_debug) 2632 2442 std::cout << " <MEMC " << name() << " MULTI_ACK_HEAP_LOCK> Update directory:" 2633 2443 << " tag = " << std::hex << entry.tag … … 2650 2460 case MULTI_ACK_HEAP_WRITE: // add an entry in the heap 2651 2461 { 2652 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_MULTI_ACK and2462 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_MULTI_ACK and 2653 2463 r_alloc_dir_fsm.read() == ALLOC_DIR_MULTI_ACK) 2654 2464 { 2655 2465 HeapEntry heap_entry; 2656 heap_entry.owner.srcid 2657 2658 if ((r_multi_ack_pktid.read() & 0x07) == 0x03)2659 { 2660 heap_entry.owner.inst 2466 heap_entry.owner.srcid = r_multi_ack_srcid.read(); 2467 2468 if ((r_multi_ack_pktid.read() & 0x07) == 0x03) 2469 { 2470 heap_entry.owner.inst = 1; 2661 2471 } 2662 2472 else 2663 2473 { 2664 heap_entry.owner.inst 2665 } 2666 2667 heap_entry.next 2474 heap_entry.owner.inst = 0; 2475 } 2476 2477 heap_entry.next = m_heap.next_free_ptr(); 2668 2478 m_heap.write_free_entry(heap_entry); 2669 2479 m_heap.write_free_ptr(r_multi_ack_next_ptr.read()); 2670 if (r_multi_ack_last_free.read()) m_heap.set_full();2480 if (r_multi_ack_last_free.read()) m_heap.set_full(); 2671 2481 2672 2482 r_multi_ack_fsm = MULTI_ACK_IVT_CLEAR; 2673 2483 2674 2484 #if DEBUG_MEMC_MULTI_ACK 2675 if (m_debug)2485 if (m_debug) 2676 2486 std::cout << " <MEMC " << name() << " MULTI_ACK_HEAP_WRITE> Add an entry in the heap:" 2677 2487 << " owner_id = " << std::hex << heap_entry.owner.srcid … … 2754 2564 //////////////////////////////////////////////////////////////////////////////////// 2755 2565 2756 switch ( r_config_fsm.read())2566 switch (r_config_fsm.read()) 2757 2567 { 2758 2568 ///////////////// 2759 2569 case CONFIG_IDLE: // waiting a config request 2760 2570 { 2761 if ( r_config_cmd.read() != MEMC_CMD_NOP)2762 { 2763 r_config_fsm 2571 if (r_config_cmd.read() != MEMC_CMD_NOP) 2572 { 2573 r_config_fsm = CONFIG_LOOP; 2764 2574 2765 2575 #if DEBUG_MEMC_CONFIG 2766 if (m_debug)2576 if (m_debug) 2767 2577 std::cout << " <MEMC " << name() << " CONFIG_IDLE> Config Request received" 2768 2578 << " address = " << std::hex << r_config_address.read() … … 2776 2586 case CONFIG_LOOP: // test last line to be handled 2777 2587 { 2778 if ( r_config_cmd_lines.read() == 0)2588 if (r_config_cmd_lines.read() == 0) 2779 2589 { 2780 2590 r_config_cmd = MEMC_CMD_NOP; … … 2787 2597 2788 2598 #if DEBUG_MEMC_CONFIG 2789 if (m_debug)2599 if (m_debug) 2790 2600 std::cout << " <MEMC " << name() << " CONFIG_LOOP>" 2791 2601 << " address = " << std::hex << r_config_address.read() … … 2798 2608 case CONFIG_WAIT: // wait completion (last response) 2799 2609 { 2800 if ( r_config_rsp_lines.read() == 0) // last response received2610 if (r_config_rsp_lines.read() == 0) // last response received 2801 2611 { 2802 2612 r_config_fsm = CONFIG_RSP; … … 2804 2614 2805 2615 #if DEBUG_MEMC_CONFIG 2806 if (m_debug)2616 if (m_debug) 2807 2617 std::cout << " <MEMC " << name() << " CONFIG_WAIT>" 2808 2618 << " / lines to do = " << std::dec << r_config_rsp_lines.read() << std::endl; … … 2813 2623 case CONFIG_RSP: // request TGT_RSP FSM to return response 2814 2624 { 2815 if ( 2816 { 2817 r_config_to_tgt_rsp_srcid 2818 r_config_to_tgt_rsp_trdid 2819 r_config_to_tgt_rsp_pktid 2820 r_config_to_tgt_rsp_error 2821 r_config_to_tgt_rsp_req 2822 r_config_fsm 2625 if (not r_config_to_tgt_rsp_req.read() ) 2626 { 2627 r_config_to_tgt_rsp_srcid = r_config_srcid.read(); 2628 r_config_to_tgt_rsp_trdid = r_config_trdid.read(); 2629 r_config_to_tgt_rsp_pktid = r_config_pktid.read(); 2630 r_config_to_tgt_rsp_error = false; 2631 r_config_to_tgt_rsp_req = true; 2632 r_config_fsm = CONFIG_IDLE; 2823 2633 2824 2634 #if DEBUG_MEMC_CONFIG 2825 if (m_debug)2635 if (m_debug) 2826 2636 std::cout << " <MEMC " << name() << " CONFIG_RSP> Request TGT_RSP FSM to return response:" 2827 2637 << " error = " << r_config_to_tgt_rsp_error.read() … … 2838 2648 case CONFIG_DIR_REQ: // Request directory lock 2839 2649 { 2840 if ( 2650 if (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG ) 2841 2651 { 2842 2652 r_config_fsm = CONFIG_DIR_ACCESS; … … 2844 2654 2845 2655 #if DEBUG_MEMC_CONFIG 2846 if (m_debug)2656 if (m_debug) 2847 2657 std::cout << " <MEMC " << name() << " CONFIG_DIR_REQ>" 2848 2658 << " Request DIR access" << std::endl; … … 2871 2681 (r_config_cmd.read() == MEMC_CMD_INVAL)) 2872 2682 { 2873 r_config_fsm 2874 } 2875 else if ( 2683 r_config_fsm = CONFIG_IVT_LOCK; 2684 } 2685 else if ((entry.state == ENTRY_SHARED or entry.state == ENTRY_EXCLUSIVE) and // hit & sync command 2876 2686 entry.dirty and (r_config_cmd.read() == MEMC_CMD_SYNC) ) 2877 2687 { 2878 2688 r_config_fsm = CONFIG_TRT_LOCK; 2879 2689 } 2880 else if (entry.state == ENTRY_LOCKED)2690 else if (entry.state == ENTRY_LOCKED) 2881 2691 { // wait for unlock 2882 2692 r_config_fsm = CONFIG_WAIT; … … 2891 2701 2892 2702 #if DEBUG_MEMC_CONFIG 2893 if (m_debug)2703 if (m_debug) 2894 2704 std::cout << " <MEMC " << name() << " CONFIG_DIR_ACCESS> Accessing directory: " 2895 2705 << " address = " << std::hex << r_config_address.read() … … 2912 2722 "MEMC ERROR in CONFIG_TRT_LOCK state: bad DIR allocation"); 2913 2723 2914 if ( r_alloc_trt_fsm.read() == ALLOC_TRT_CONFIG)2724 if (r_alloc_trt_fsm.read() == ALLOC_TRT_CONFIG) 2915 2725 { 2916 2726 size_t index = 0; 2917 bool wok= not m_trt.full(index);2918 2919 if ( not wok)2727 bool wok = not m_trt.full(index); 2728 2729 if (not wok) 2920 2730 { 2921 2731 r_config_fsm = CONFIG_LOOP; … … 2923 2733 else 2924 2734 { 2925 size_t 2926 size_t 2735 size_t way = r_config_dir_way.read(); 2736 size_t set = m_y[r_config_address.read()]; 2927 2737 2928 2738 // reset dirty bit in DIR … … 2940 2750 2941 2751 r_config_trt_index = index; 2942 r_config_fsm 2752 r_config_fsm = CONFIG_TRT_SET; 2943 2753 } 2944 2754 2945 2755 #if DEBUG_MEMC_CONFIG 2946 if (m_debug)2756 if (m_debug) 2947 2757 std::cout << " <MEMC " << name() << " CONFIG_TRT_LOCK> Access TRT: " 2948 2758 << " wok = " << std::dec << wok … … 2956 2766 // and post a PUT request in TRT 2957 2767 { 2958 assert( 2768 assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and 2959 2769 "MEMC ERROR in CONFIG_TRT_SET state: bad DIR allocation"); 2960 2770 2961 assert( 2771 assert((r_alloc_trt_fsm.read() == ALLOC_TRT_CONFIG) and 2962 2772 "MEMC ERROR in CONFIG_TRT_SET state: bad TRT allocation"); 2963 2773 2964 2774 // read data into cache 2965 size_t 2966 size_t 2775 size_t way = r_config_dir_way.read(); 2776 size_t set = m_y[r_config_address.read()]; 2967 2777 std::vector<data_t> data_vector; 2968 2778 data_vector.clear(); 2969 for (size_t word=0; word<m_words; word++)2970 { 2971 uint32_t data = m_cache_data.read( way, set, word);2972 data_vector.push_back( data);2779 for (size_t word = 0; word < m_words; word++) 2780 { 2781 uint32_t data = m_cache_data.read(way, set, word); 2782 data_vector.push_back(data); 2973 2783 } 2974 2784 … … 2992 2802 2993 2803 #if DEBUG_MEMC_CONFIG 2994 if (m_debug)2804 if (m_debug) 2995 2805 std::cout << " <MEMC " << name() << " CONFIG_TRT_SET> PUT request in TRT:" 2996 2806 << " address = " << std::hex << r_config_address.read() … … 3002 2812 case CONFIG_PUT_REQ: // post PUT request to IXR_CMD_FSM 3003 2813 { 3004 if ( not r_config_to_ixr_cmd_req.read())2814 if (not r_config_to_ixr_cmd_req.read()) 3005 2815 { 3006 2816 r_config_to_ixr_cmd_req = true; … … 3008 2818 3009 2819 // prepare next iteration 3010 r_config_cmd_lines 3011 r_config_address = r_config_address.read() + (m_words<<2);3012 r_config_fsm 2820 r_config_cmd_lines = r_config_cmd_lines.read() - 1; 2821 r_config_address = r_config_address.read() + (m_words << 2); 2822 r_config_fsm = CONFIG_LOOP; 3013 2823 3014 2824 #if DEBUG_MEMC_CONFIG 3015 if (m_debug)2825 if (m_debug) 3016 2826 std::cout << " <MEMC " << name() << " CONFIG_PUT_REQ> post PUT request to IXR_CMD_FSM" 3017 2827 << " / address = " << std::hex << r_config_address.read() << std::endl; … … 3027 2837 // directory if IVT not full. 3028 2838 { 3029 assert( 2839 assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and 3030 2840 "MEMC ERROR in CONFIG_IVT_LOCK state: bad DIR allocation"); 3031 2841 3032 if ( r_alloc_ivt_fsm.read() == ALLOC_IVT_CONFIG)2842 if (r_alloc_ivt_fsm.read() == ALLOC_IVT_CONFIG) 3033 2843 { 3034 2844 size_t set = m_y[(addr_t)(r_config_address.read())]; 3035 2845 size_t way = r_config_dir_way.read(); 3036 2846 3037 if ( r_config_dir_count.read() == 0) // inval DIR and return to LOOP3038 { 3039 m_cache_directory.inval( way, set);2847 if (r_config_dir_count.read() == 0) // inval DIR and return to LOOP 2848 { 2849 m_cache_directory.inval(way, set); 3040 2850 r_config_cmd_lines = r_config_cmd_lines.read() - 1; 3041 r_config_address = r_config_address.read() + (m_words <<2);2851 r_config_address = r_config_address.read() + (m_words << 2); 3042 2852 r_config_fsm = CONFIG_LOOP; 3043 2853 3044 2854 #if DEBUG_MEMC_CONFIG 3045 if (m_debug)2855 if (m_debug) 3046 2856 std::cout << " <MEMC " << name() << " CONFIG_IVT_LOCK>" 3047 2857 << " No copies in L1 : inval DIR entry" << std::endl; … … 3071 2881 index); 3072 2882 3073 if ( wok) // IVT success => inval DIR slot2883 if (wok) // IVT success => inval DIR slot 3074 2884 { 3075 m_cache_directory.inval( way, set);2885 m_cache_directory.inval(way, set); 3076 2886 r_config_ivt_index = index; 3077 2887 config_rsp_lines_incr = true; 3078 if ( broadcast) r_config_fsm = CONFIG_BC_SEND;3079 else 2888 if (broadcast) r_config_fsm = CONFIG_BC_SEND; 2889 else r_config_fsm = CONFIG_INVAL_SEND; 3080 2890 3081 2891 #if DEBUG_MEMC_CONFIG 3082 if (m_debug)2892 if (m_debug) 3083 2893 std::cout << " <MEMC " << name() << " CONFIG_IVT_LOCK>" 3084 2894 << " Inval DIR entry and register inval in IVT" … … 3092 2902 3093 2903 #if DEBUG_MEMC_CONFIG 3094 if (m_debug)2904 if (m_debug) 3095 2905 std::cout << " <MEMC " << name() << " CONFIG_IVT_LOCK>" 3096 2906 << " IVT full : release DIR & IVT locks and retry" << std::endl; … … 3104 2914 case CONFIG_BC_SEND: // Post a broadcast inval request to CC_SEND FSM 3105 2915 { 3106 if (not r_config_to_cc_send_multi_req.read() and3107 not r_config_to_cc_send_brdcast_req.read() 2916 if (not r_config_to_cc_send_multi_req.read() and 2917 not r_config_to_cc_send_brdcast_req.read()) 3108 2918 { 3109 2919 // post bc inval request … … 3119 2929 3120 2930 #if DEBUG_MEMC_CONFIG 3121 if (m_debug)2931 if (m_debug) 3122 2932 std::cout << " <MEMC " << name() << " CONFIG_BC_SEND>" 3123 2933 << " Post a broadcast inval request to CC_SEND FSM" … … 3130 2940 case CONFIG_INVAL_SEND: // Post a multi inval request to CC_SEND FSM 3131 2941 { 3132 if (not r_config_to_cc_send_multi_req.read() and2942 if (not r_config_to_cc_send_multi_req.read() and 3133 2943 not r_config_to_cc_send_brdcast_req.read() ) 3134 2944 { … … 3143 2953 config_to_cc_send_fifo_put = true; 3144 2954 3145 if ( 2955 if (r_config_dir_count.read() == 1 ) // one copy 3146 2956 { 3147 2957 // prepare next iteration … … 3156 2966 3157 2967 #if DEBUG_MEMC_CONFIG 3158 if (m_debug)2968 if (m_debug) 3159 2969 std::cout << " <MEMC " << name() << " CONFIG_INVAL_SEND>" 3160 2970 << " Post multi inval request to CC_SEND FSM" … … 3169 2979 case CONFIG_HEAP_REQ: // Try to get access to Heap 3170 2980 { 3171 if ( 3172 { 3173 r_config_fsm 2981 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_CONFIG ) 2982 { 2983 r_config_fsm = CONFIG_HEAP_SCAN; 3174 2984 r_config_heap_next = r_config_dir_ptr.read(); 3175 2985 } 3176 2986 3177 2987 #if DEBUG_MEMC_CONFIG 3178 if (m_debug)2988 if (m_debug) 3179 2989 std::cout << " <MEMC " << name() << " CONFIG_HEAP_REQ>" 3180 2990 << " Requesting HEAP lock" << std::endl; … … 3193 3003 config_to_cc_send_fifo_put = true; 3194 3004 3195 if ( m_config_to_cc_send_inst_fifo.wok()) // inval request accepted3005 if (m_config_to_cc_send_inst_fifo.wok()) // inval request accepted 3196 3006 { 3197 3007 r_config_heap_next = entry.next; 3198 if ( last_copy) r_config_fsm = CONFIG_HEAP_LAST;3008 if (last_copy) r_config_fsm = CONFIG_HEAP_LAST; 3199 3009 } 3200 3010 3201 3011 #if DEBUG_MEMC_CONFIG 3202 if (m_debug)3012 if (m_debug) 3203 3013 std::cout << " <MEMC " << name() << " CONFIG_HEAP_SCAN>" 3204 3014 << " Post multi inval request to CC_SEND FSM" … … 3217 3027 last_entry.owner.inst = false; 3218 3028 3219 if ( m_heap.is_full())3029 if (m_heap.is_full()) 3220 3030 { 3221 3031 last_entry.next = r_config_dir_ptr.read(); … … 3227 3037 } 3228 3038 3229 m_heap.write_free_ptr( 3230 m_heap.write( 3039 m_heap.write_free_ptr(r_config_dir_ptr.read() ); 3040 m_heap.write(r_config_heap_next.read(), last_entry ); 3231 3041 3232 3042 // prepare next iteration 3233 r_config_cmd_lines 3234 r_config_address 3235 r_config_fsm 3043 r_config_cmd_lines = r_config_cmd_lines.read() - 1; 3044 r_config_address = r_config_address.read() + (m_words<<2); 3045 r_config_fsm = CONFIG_LOOP; 3236 3046 3237 3047 #if DEBUG_MEMC_CONFIG 3238 if (m_debug)3048 if (m_debug) 3239 3049 std::cout << " <MEMC " << name() << " CONFIG_HEAP_LAST>" 3240 3050 << " Heap housekeeping" << std::endl; … … 3272 3082 case READ_IDLE: // waiting a read request 3273 3083 { 3274 if (m_cmd_read_addr_fifo.rok())3084 if (m_cmd_read_addr_fifo.rok()) 3275 3085 { 3276 3086 … … 3280 3090 3281 3091 #if DEBUG_MEMC_READ 3282 if (m_debug)3092 if (m_debug) 3283 3093 std::cout << " <MEMC " << name() << " READ_IDLE> Read request" 3284 3094 << " : address = " << std::hex << m_cmd_read_addr_fifo.read() … … 3298 3108 case READ_DIR_REQ: // Get the lock to the directory 3299 3109 { 3300 if (r_alloc_dir_fsm.read() == ALLOC_DIR_READ)3110 if (r_alloc_dir_fsm.read() == ALLOC_DIR_READ) 3301 3111 { 3302 3112 r_read_fsm = READ_DIR_LOCK; 3303 m_cpt_read_fsm_n_dir_lock++;3304 3113 } 3305 3114 3306 3115 #if DEBUG_MEMC_READ 3307 if (m_debug)3116 if (m_debug) 3308 3117 std::cout << " <MEMC " << name() << " READ_DIR_REQ> Requesting DIR lock " << std::endl; 3309 3118 #endif 3310 3311 m_cpt_read_fsm_dir_lock++;3312 3313 3119 break; 3314 3120 } … … 3323 3129 DirectoryEntry entry = 3324 3130 m_cache_directory.read(m_cmd_read_addr_fifo.read(), way); 3325 if (((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) and not r_read_ll_done.read()) // access the global table ONLY when we have an LL cmd3326 { 3327 r_read_ll_key 3131 if (((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) and not r_read_ll_done.read()) // access the global table ONLY when we have an LL cmd 3132 { 3133 r_read_ll_key = m_llsc_table.ll(m_cmd_read_addr_fifo.read()); 3328 3134 /**//*std::cout << "MEMCACHE : from proc " << m_cmd_read_srcid_fifo.read() 3329 3135 << " | @ " << std::hex << m_cmd_read_addr_fifo.read() … … 3331 3137 r_read_ll_done = true; 3332 3138 } 3333 3334 //bool s_getm_hit = m_cmd_read_pktid_fifo.read() & 0x8;3335 3139 3336 3140 r_read_is_cnt = entry.is_cnt; … … 3350 3154 bool cached_read = ((m_cmd_read_pktid_fifo.read() & 0x7) != 0) and ((m_cmd_read_pktid_fifo.read() & 0x7) != 0x2) and ((m_cmd_read_pktid_fifo.read() & 0x7) != 0x6); 3351 3155 3352 if (entry.state == ENTRY_SHARED or entry.state == ENTRY_EXCLUSIVE) // hit3353 { 3354 if ( 3156 if (entry.state == ENTRY_SHARED or entry.state == ENTRY_EXCLUSIVE) // hit 3157 { 3158 if ((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_WRITE ) 3355 3159 { 3356 3160 // Invalid the line in the others processors and put the line in trt with data. 3357 if (entry.count == 0)3161 if (entry.count == 0) 3358 3162 // ((entry.count == 1) and not entry.is_cnt and (entry.state == ENTRY_SHARED) and (entry.owner.srcid == m_cmd_read_srcid_fifo.read())) or 3359 3163 // (entry.count == 1 and entry.is_cnt and entry.state == ENTRY_SHARED and s_getm_hit)) … … 3363 3167 else 3364 3168 { 3365 if ((entry.state == ENTRY_EXCLUSIVE) and (entry.owner.srcid == m_cmd_read_srcid_fifo.read()))3169 if ((entry.state == ENTRY_EXCLUSIVE) and (entry.owner.srcid == m_cmd_read_srcid_fifo.read())) 3366 3170 { 3367 3171 std::cout <<"exclusive line && srcid != read srcid "<< std::endl; … … 3372 3176 3373 3177 addr_t min = m_cmd_read_addr_fifo.read(); 3374 addr_t max = m_cmd_read_addr_fifo.read() + m_cmd_read_length_fifo.read() *4;3178 addr_t max = m_cmd_read_addr_fifo.read() + m_cmd_read_length_fifo.read() * 4; 3375 3179 m_llsc_table.sw(min, max); 3376 3180 } 3377 3181 else // a read miss request 3378 3182 { 3379 if ( 3183 if (entry.state == ENTRY_SHARED or entry.count == 0) 3380 3184 { 3381 if (entry.is_cnt or (entry.count == 0) or (not cached_read))3185 if (entry.is_cnt or (entry.count == 0) or (not cached_read)) 3382 3186 { 3383 3187 r_read_fsm = READ_DIR_HIT; … … 3388 3192 } 3389 3193 } 3390 else if ( entry.state == ENTRY_EXCLUSIVE)3194 else if (entry.state == ENTRY_EXCLUSIVE) 3391 3195 { 3392 3196 r_read_fsm = READ_IVT_UPDT_LOCK; … … 3394 3198 } 3395 3199 } 3396 else if(entry.state == ENTRY_LOCKED) // the line is locked, can't use it at this time 3397 { 3398 m_cpt_read_locked_rb ++; 3200 else if (entry.state == ENTRY_LOCKED) // the line is locked, can't use it at this time 3201 { 3399 3202 r_read_fsm = READ_WAIT; 3400 3203 } … … 3405 3208 3406 3209 #if DEBUG_MEMC_READ 3407 if (m_debug)3210 if (m_debug) 3408 3211 { 3409 3212 std::cout << " <MEMC " << name() << " READ_DIR_LOCK> Accessing directory: " … … 3415 3218 << " / is_inst = " << entry.owner.inst 3416 3219 << " / is_cnt = " << entry.is_cnt << std::endl; 3417 if ((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) std::cout << " / LL access" << std::endl;3220 if ((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) std::cout << " / LL access" << std::endl; 3418 3221 else std::cout << std::endl; 3419 3222 } … … 3438 3241 size_t ivt_send_count = 0; 3439 3242 3440 if (m_ivt.is_full() or // not need to check match inval, because of the LOCKED STATE3243 if (m_ivt.is_full() or // not need to check match inval, because of the LOCKED STATE 3441 3244 r_read_to_cc_send_multi_req.read() or 3442 3245 r_read_to_cc_send_brdcast_req.read() or … … 3446 3249 r_read_fsm = READ_WAIT; 3447 3250 #if DEBUG_MEMC_READ 3448 if (m_debug)3251 if (m_debug) 3449 3252 { 3450 3253 std::cout … … 3475 3278 //r_read_to_cc_send_is_shared = r_read_state.read() == ENTRY_SHARED; 3476 3279 3477 if (r_read_need_block.read())3280 if (r_read_need_block.read()) 3478 3281 { 3479 3282 r_read_to_cleanup_nline = nline; … … 3502 3305 index); 3503 3306 3504 if (not_last_multi_req )3307 if (not_last_multi_req ) 3505 3308 { 3506 3309 r_read_fsm = READ_INVAL_HEAP_REQ; … … 3512 3315 } 3513 3316 3514 if(multi_req)3515 m_cpt_getm_minval ++;3516 else3317 // <Activity counters> 3318 if (!multi_req) 3319 { 3517 3320 m_cpt_getm_broadcast ++; 3321 } 3322 // </Activity counters> 3518 3323 #if DEBUG_MEMC_READ 3519 if (m_debug)3324 if (m_debug) 3520 3325 { 3521 3326 std::cout … … 3534 3339 case READ_INVAL_HEAP_REQ: 3535 3340 { 3536 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ )3341 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ ) 3537 3342 { 3538 3343 r_read_fsm = READ_INVAL_HEAP_ERASE; 3539 3344 } 3540 3345 #if DEBUG_MEMC_READ 3541 if (m_debug)3346 if (m_debug) 3542 3347 std::cout << " <MEMC " << name() << " READ_INVAL_HEAP_REQ>" 3543 3348 << " Requesting HEAP lock" << std::endl; … … 3548 3353 case READ_INVAL_HEAP_ERASE: 3549 3354 { 3550 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)3355 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) 3551 3356 { 3552 3357 HeapEntry entry = m_heap.read(r_read_next_ptr.read()); … … 3557 3362 r_read_next_ptr = entry.next; 3558 3363 3559 if (entry.next == r_read_next_ptr.read()) // last copy3364 if (entry.next == r_read_next_ptr.read()) // last copy 3560 3365 { 3561 3366 r_read_to_cc_send_multi_req = true; … … 3568 3373 3569 3374 #if DEBUG_MEMC_READ 3570 if (m_debug)3375 if (m_debug) 3571 3376 std::cout << " <MEMC " << name() << " READ_HEAP_ERASE>" 3572 3377 << " Erase copy:" … … 3580 3385 case READ_INVAL_HEAP_LAST: // last copy 3581 3386 { 3582 if (r_alloc_heap_fsm.read() != ALLOC_HEAP_READ)3387 if (r_alloc_heap_fsm.read() != ALLOC_HEAP_READ) 3583 3388 { 3584 3389 std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_INVAL_HEAP_LAST" … … 3591 3396 last_entry.owner.srcid = 0; 3592 3397 last_entry.owner.inst = false; 3593 if (m_heap.is_full())3398 if (m_heap.is_full()) 3594 3399 { 3595 3400 last_entry.next = r_read_next_ptr.read(); … … 3608 3413 3609 3414 #if DEBUG_MEMC_READ 3610 if (m_debug)3415 if (m_debug) 3611 3416 std::cout << " <MEMC " << name() << " READ_INVAL_HEAP_LAST>" 3612 3417 << " Heap housekeeping" << std::endl; … … 3622 3427 addr_t nline = m_nline[(addr_t)(m_cmd_read_addr_fifo.read())]; 3623 3428 size_t set = m_y[(addr_t)(m_cmd_read_addr_fifo.read())]; 3624 if (m_ivt.is_full() or3429 if (m_ivt.is_full() or 3625 3430 r_read_to_cc_send_multi_req.read() or 3626 3431 r_read_to_cc_send_brdcast_req.read() or … … 3629 3434 r_read_fsm = READ_WAIT; 3630 3435 #if DEBUG_MEMC_READ 3631 if (m_debug)3436 if (m_debug) 3632 3437 { 3633 3438 std::cout … … 3652 3457 m_cache_directory.write(set, r_read_way.read(), entry); 3653 3458 3654 if (r_read_need_block.read())3459 if (r_read_need_block.read()) 3655 3460 { 3656 3461 r_read_to_multi_ack_nline = nline; … … 3687 3492 3688 3493 #if DEBUG_MEMC_READ 3689 if (m_debug)3494 if (m_debug) 3690 3495 { 3691 3496 std::cout … … 3709 3514 r_read_fsm = READ_DIR_REQ; 3710 3515 #if DEBUG_MEMC_READ 3711 if (m_debug)3516 if (m_debug) 3712 3517 { 3713 3518 std::cout … … 3747 3552 DirectoryEntry entry; 3748 3553 3749 if (inst_read)3554 if (inst_read) 3750 3555 { 3751 3556 entry.state = ENTRY_SHARED; 3752 3557 } 3753 else if (is_getm)3558 else if (is_getm) 3754 3559 { 3755 3560 entry.state = ENTRY_EXCLUSIVE; … … 3761 3566 3762 3567 //entry.cache_coherent = r_read_coherent.read() or inst_read or (!(cached_read)) or (r_read_copy.read() != m_cmd_read_srcid_fifo.read()); 3763 if (entry.state == ENTRY_SHARED) r_read_shared = true;3568 if (entry.state == ENTRY_SHARED) r_read_shared = true; 3764 3569 else r_read_shared = false; 3765 3570 entry.is_cnt = is_cnt; … … 3768 3573 entry.lock = r_read_lock.read(); 3769 3574 entry.ptr = r_read_ptr.read(); 3770 if (cached_read) // Cached read => we must update the copies3771 { 3772 if (is_getm)3575 if (cached_read) // Cached read => we must update the copies 3576 { 3577 if (is_getm) 3773 3578 { 3774 3579 entry.owner.srcid = m_cmd_read_srcid_fifo.read(); … … 3777 3582 3778 3583 } 3779 else if (!is_cnt) // Not counter mode3584 else if (!is_cnt) // Not counter mode 3780 3585 { 3781 3586 entry.owner.srcid = m_cmd_read_srcid_fifo.read(); … … 3798 3603 3799 3604 #if DEBUG_MEMC_READ 3800 if (m_debug)3605 if (m_debug) 3801 3606 std::cout << " <MEMC " << name() << " READ_DIR_HIT> Update directory entry:" 3802 3607 << " addr = " << std::hex << m_cmd_read_addr_fifo.read() … … 3818 3623 case READ_HEAP_REQ: // Get the lock to the HEAP directory 3819 3624 { 3820 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)3625 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) 3821 3626 { 3822 3627 r_read_fsm = READ_HEAP_LOCK; 3823 m_cpt_read_fsm_n_heap_lock++;3824 3628 } 3825 3629 3826 3630 #if DEBUG_MEMC_READ 3827 if (m_debug)3631 if (m_debug) 3828 3632 std::cout << " <MEMC " << name() << " READ_HEAP_REQ>" 3829 3633 << " Requesting HEAP lock " << std::endl; 3830 3634 #endif 3831 3832 m_cpt_read_fsm_heap_lock++;3833 3834 3635 break; 3835 3636 } … … 3839 3640 // and prepare the HEAP update 3840 3641 { 3841 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)3642 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) 3842 3643 { 3843 3644 // enter counter mode when we reach the limit of copies or the heap is full … … 3862 3663 r_read_shared = true; //ack to cache L1 with shared state 3863 3664 3864 if (not go_cnt) // Not entering counter mode3665 if (not go_cnt) // Not entering counter mode 3865 3666 { 3866 3667 entry.owner.srcid = r_read_copy.read(); … … 3878 3679 3879 3680 // prepare the heap update (add an entry, or clear the linked list) 3880 if (not go_cnt) // not switching to counter mode3681 if (not go_cnt) // not switching to counter mode 3881 3682 { 3882 3683 // We test if the next free entry in the heap is the last … … 3889 3690 else // switching to counter mode 3890 3691 { 3891 if (r_read_count.read() >1) // heap must be cleared3692 if (r_read_count.read() >1) // heap must be cleared 3892 3693 { 3893 3694 HeapEntry next_entry = m_heap.read(r_read_ptr.read()); … … 3895 3696 m_heap.write_free_ptr(r_read_ptr.read()); 3896 3697 3897 if (next_entry.next == r_read_ptr.read()) // last entry3698 if (next_entry.next == r_read_ptr.read()) // last entry 3898 3699 { 3899 3700 r_read_fsm = READ_HEAP_LAST; // erase the entry … … 3912 3713 3913 3714 #if DEBUG_MEMC_READ 3914 if (m_debug)3715 if (m_debug) 3915 3716 std::cout << " <MEMC " << name() << " READ_HEAP_LOCK> Update directory:" 3916 3717 << " tag = " << std::hex << entry.tag … … 3932 3733 case READ_HEAP_WRITE: // add an entry in the heap 3933 3734 { 3934 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)3735 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) 3935 3736 { 3936 3737 HeapEntry heap_entry; … … 3938 3739 heap_entry.owner.inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); 3939 3740 3940 if (r_read_count.read() == 1) // creation of a new linked list3741 if (r_read_count.read() == 1) // creation of a new linked list 3941 3742 { 3942 3743 heap_entry.next = m_heap.next_free_ptr(); … … 3948 3749 m_heap.write_free_entry(heap_entry); 3949 3750 m_heap.write_free_ptr(r_read_next_ptr.read()); 3950 if (r_read_last_free.read()) m_heap.set_full();3751 if (r_read_last_free.read()) m_heap.set_full(); 3951 3752 3952 3753 r_read_fsm = READ_RSP; 3953 3754 3954 3755 #if DEBUG_MEMC_READ 3955 if (m_debug)3756 if (m_debug) 3956 3757 std::cout << " <MEMC " << name() << " READ_HEAP_WRITE> Add an entry in the heap:" 3957 3758 << " owner_id = " << std::hex << heap_entry.owner.srcid … … 3970 3771 case READ_HEAP_ERASE: 3971 3772 { 3972 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)3773 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) 3973 3774 { 3974 3775 HeapEntry next_entry = m_heap.read(r_read_ptr.read()); 3975 if (next_entry.next == r_read_ptr.read())3776 if (next_entry.next == r_read_ptr.read()) 3976 3777 { 3977 3778 r_read_fsm = READ_HEAP_LAST; … … 3995 3796 case READ_HEAP_LAST: 3996 3797 { 3997 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ)3798 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) 3998 3799 { 3999 3800 HeapEntry last_entry; … … 4001 3802 last_entry.owner.inst = false; 4002 3803 4003 if (m_heap.is_full())3804 if (m_heap.is_full()) 4004 3805 { 4005 3806 last_entry.next = r_read_ptr.read(); … … 4024 3825 case READ_RSP: // request the TGT_RSP FSM to return data 4025 3826 { 4026 if (not r_read_to_tgt_rsp_req.read())3827 if (not r_read_to_tgt_rsp_req.read()) 4027 3828 { 4028 3829 for(size_t i=0 ; i<m_words ; i++) r_read_to_tgt_rsp_data[i] = r_read_data[i]; … … 4046 3847 4047 3848 #if DEBUG_MEMC_READ 4048 if (m_debug)3849 if (m_debug) 4049 3850 std::cout << " <MEMC " << name() << " READ_RSP> Request TGT_RSP FSM to return data:" 4050 3851 << " rsrcid = " << std::hex << m_cmd_read_srcid_fifo.read() … … 4058 3859 case READ_TRT_LOCK: // read miss : check the Transaction Table 4059 3860 { 4060 if (r_alloc_trt_fsm.read() == ALLOC_TRT_READ)3861 if (r_alloc_trt_fsm.read() == ALLOC_TRT_READ) 4061 3862 { 4062 3863 size_t index = 0; … … 4067 3868 bool wok = !m_trt.full(index); 4068 3869 4069 //if(hit_write) m_trt.print(index_write); 4070 if(hit_read or !wok or hit_write) // missing line already requested or no space 4071 { 4072 if(!wok) 3870 //if (hit_write) m_trt.print(index_write); 3871 if (hit_read or !wok or hit_write) // missing line already requested or no space 3872 { 3873 // <Activity counters> 3874 if (!wok) 4073 3875 { 4074 3876 m_cpt_trt_full++; 4075 3877 } 4076 if(hit_read or hit_write) m_cpt_trt_rb++; 3878 if (hit_read or hit_write) 3879 { 3880 m_cpt_trt_rb++; 3881 } 3882 // </Activity counters> 4077 3883 r_read_fsm = READ_IDLE; 4078 3884 } 4079 else // missing line is requested to the XRAM 4080 { 4081 4082 if ( (m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_WRITE ) 4083 m_cpt_getm_miss ++; 4084 else 3885 else // missing line is requested to the XRAM 3886 { 3887 3888 // <Activity counters> 3889 if ((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_WRITE) { 3890 m_cpt_getm_miss++; 3891 } 3892 else { 4085 3893 m_cpt_read_miss++; 3894 } 3895 // </Activity counters> 4086 3896 4087 3897 r_read_trt_index = index; … … 4090 3900 4091 3901 #if DEBUG_MEMC_READ 4092 if (m_debug)3902 if (m_debug) 4093 3903 std::cout << " <MEMC " << name() << " READ_TRT_LOCK> Check TRT:" 4094 3904 << " hit_read = " << hit_read 4095 3905 << " / hit_write = " << hit_write 4096 3906 << " / full = " << !wok << std::endl; 4097 m_cpt_read_fsm_n_trt_lock++; 4098 #endif 4099 } 4100 4101 m_cpt_read_fsm_trt_lock++; 4102 3907 #endif 3908 } 4103 3909 break; 4104 3910 } … … 4107 3913 case READ_TRT_SET: // register get transaction in TRT 4108 3914 { 4109 if (r_alloc_trt_fsm.read() == ALLOC_TRT_READ)3915 if (r_alloc_trt_fsm.read() == ALLOC_TRT_READ) 4110 3916 { 4111 3917 m_trt.set(r_read_trt_index.read(), … … 4123 3929 4124 3930 #if DEBUG_MEMC_READ 4125 if (m_debug)3931 if (m_debug) 4126 3932 std::cout << " <MEMC " << name() << " READ_TRT_SET> Set a GET in TGT:" 4127 3933 << " address = " << std::hex << m_cmd_read_addr_fifo.read() … … 4136 3942 case READ_TRT_REQ: // consume the read request in FIFO and send it to IXR_CMD_FSM 4137 3943 { 4138 if (not r_read_to_ixr_cmd_req)3944 if (not r_read_to_ixr_cmd_req) 4139 3945 { 4140 3946 cmd_read_fifo_get = true; … … 4145 3951 4146 3952 #if DEBUG_MEMC_READ 4147 if (m_debug)3953 if (m_debug) 4148 3954 std::cout << " <MEMC " << name() << " READ_TRT_REQ> Request GET transaction for address " 4149 3955 << std::hex << m_cmd_read_addr_fifo.read() << std::endl; … … 4217 4023 for(size_t word=0 ; word<m_words ; word++) 4218 4024 { 4219 if (word == index) r_write_be[word] = m_cmd_write_be_fifo.read();4025 if (word == index) r_write_be[word] = m_cmd_write_be_fifo.read(); 4220 4026 else r_write_be[word] = 0x0; 4221 4027 } … … 4231 4037 4232 4038 #if DEBUG_MEMC_WRITE 4233 if (m_debug)4039 if (m_debug) 4234 4040 std::cout << " <MEMC " << name() << " WRITE_IDLE> Write request " 4235 4041 << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read() … … 4295 4101 if (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE ) 4296 4102 { 4297 m_cpt_write_fsm_n_dir_lock ++;4298 4103 break; 4299 4104 } … … 4326 4131 } 4327 4132 4328 m_cpt_write_fsm_dir_lock ++;4329 4330 4133 #if DEBUG_MEMC_WRITE 4331 if (m_debug)4134 if (m_debug) 4332 4135 std::cout << " <MEMC " << name() << " WRITE_DIR_REQ> Requesting DIR lock " 4333 4136 << std::endl; … … 4344 4147 DirectoryEntry entry(m_cache_directory.read(r_write_address.read(), way)); 4345 4148 4346 if (entry.state != ENTRY_INVALID) // hit4149 if (entry.state != ENTRY_INVALID) // hit 4347 4150 { 4348 4151 // copy directory entry in local buffer in case of hit … … 4357 4160 r_write_state = entry.state; 4358 4161 4359 if (r_write_pktid == TYPE_DATA_UNC and entry.count != 0)4162 if (r_write_pktid == TYPE_DATA_UNC and entry.count != 0) 4360 4163 { 4361 4164 assert( false && " found a copy for an uncached write quest"); … … 4363 4166 else 4364 4167 { 4365 if (not entry.count and (entry.state != ENTRY_LOCKED))4168 if (not entry.count and (entry.state != ENTRY_LOCKED)) 4366 4169 { 4367 4170 r_write_fsm = WRITE_DIR_HIT; … … 4369 4172 else if (entry.state == ENTRY_LOCKED)//the line is locked 4370 4173 { 4371 m_cpt_write_locked_rb ++;4372 4174 r_write_fsm = WRITE_WAIT; 4373 4175 } … … 4384 4186 4385 4187 #if DEBUG_MEMC_WRITE 4386 if (m_debug)4188 if (m_debug) 4387 4189 { 4388 4190 std::cout << " <MEMC " << name() << " WRITE_DIR_LOCK> Check the directory: " … … 4391 4193 << " / count = " << entry.count 4392 4194 << " / is_cnt = " << entry.is_cnt ; 4393 if ((r_write_pktid.read() & 0x7) == TYPE_SC)4195 if ((r_write_pktid.read() & 0x7) == TYPE_SC) 4394 4196 std::cout << " / SC access" << std::endl; 4395 4197 else … … 4439 4241 4440 4242 #if DEBUG_MEMC_WRITE 4441 if (m_debug)4243 if (m_debug) 4442 4244 { 4443 4245 std::cout << " <MEMC " << name() … … 4451 4253 case WRITE_HEAP_REQ: // Get the lock to the HEAP directory 4452 4254 { 4453 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE)4255 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE) 4454 4256 { 4455 4257 r_write_fsm = WRITE_HEAP_ERASE; 4456 m_cpt_write_fsm_n_heap_lock++;4457 4258 } 4458 4259 4459 4260 #if DEBUG_MEMC_WRITE 4460 if (m_debug)4261 if (m_debug) 4461 4262 std::cout << " <MEMC " << name() << " WRITE_HEAP_REQ>" 4462 4263 << " Requesting HEAP lock " << std::endl; 4463 4264 #endif 4464 4465 m_cpt_write_fsm_heap_lock++;4466 4467 4265 break; 4468 4266 } … … 4471 4269 case WRITE_HEAP_ERASE: // get access to heap 4472 4270 { 4473 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE)4271 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE) 4474 4272 { 4475 4273 HeapEntry entry = m_heap.read(r_write_next_ptr.read()); … … 4478 4276 write_to_cc_send_fifo_inst = entry.owner.inst; 4479 4277 write_to_cc_send_fifo_put = true; 4480 if (m_write_to_cc_send_inst_fifo.wok())4278 if (m_write_to_cc_send_inst_fifo.wok()) 4481 4279 { 4482 4280 r_write_next_ptr = entry.next; 4483 if (entry.next == r_write_next_ptr.read()) // last copy4281 if (entry.next == r_write_next_ptr.read()) // last copy 4484 4282 { 4485 4283 r_write_to_cc_send_multi_req = true; … … 4497 4295 4498 4296 #if DEBUG_MEMC_WRITE 4499 if (m_debug)4297 if (m_debug) 4500 4298 std::cout << " <MEMC " << name() 4501 4299 << " WRITE_HEAP_LOCK> Get acces to the HEAP" << std::endl; 4502 4300 #endif 4503 4301 } 4504 4505 m_cpt_write_fsm_heap_lock++;4506 4507 4302 break; 4508 4303 } … … 4510 4305 case WRITE_HEAP_LAST: // last copy 4511 4306 { 4512 if (r_alloc_heap_fsm.read() != ALLOC_HEAP_WRITE)4307 if (r_alloc_heap_fsm.read() != ALLOC_HEAP_WRITE) 4513 4308 { 4514 4309 std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_HEAP_LAST" … … 4521 4316 last_entry.owner.srcid = 0; 4522 4317 last_entry.owner.inst = false; 4523 if (m_heap.is_full())4318 if (m_heap.is_full()) 4524 4319 { 4525 4320 last_entry.next = r_write_next_ptr.read(); … … 4537 4332 4538 4333 #if DEBUG_MEMC_XRAM_RSP 4539 if (m_debug)4334 if (m_debug) 4540 4335 std::cout << " <MEMC " << name() << " WRITE_HEAP_LAST>" 4541 4336 << " Heap housekeeping" << std::endl; … … 4592 4387 for(size_t word=0 ; word<m_words ; word++) 4593 4388 { 4594 if (word == index) r_write_be[word] = m_cmd_write_be_fifo.read();4389 if (word == index) r_write_be[word] = m_cmd_write_be_fifo.read(); 4595 4390 else r_write_be[word] = 0x0; 4596 4391 } 4597 4392 4598 if (m_cmd_write_eop_fifo.read())4393 if (m_cmd_write_eop_fifo.read()) 4599 4394 { 4600 4395 r_write_fsm = WRITE_DIR_REQ; … … 4607 4402 4608 4403 #if DEBUG_MEMC_WRITE 4609 if (m_debug)4404 if (m_debug) 4610 4405 { 4611 4406 std::cout << " <MEMC " << name() << " WRITE_RSP> Post a request to TGT_RSP FSM" … … 4614 4409 << " : sc_fail= " << std::hex << r_write_sc_fail.read() 4615 4410 << std::endl; 4616 if (m_cmd_write_addr_fifo.rok())4411 if (m_cmd_write_addr_fifo.rok()) 4617 4412 { 4618 4413 std::cout << " New Write request: " … … 4631 4426 case WRITE_MISS_TRT_LOCK: // Miss : check Transaction Table 4632 4427 { 4633 if (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE)4428 if (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) 4634 4429 { 4635 4430 size_t hit_index = 0; … … 4640 4435 bool wok = not m_trt.full(wok_index); 4641 4436 #if DEBUG_MEMC_WRITE 4642 if (m_debug)4437 if (m_debug) 4643 4438 std::cout << " <MEMC " << name() << " WRITE_MISS_TRT_LOCK> Check the TRT" 4644 4439 << "hit read =" << hit_read … … 4649 4444 4650 4445 // wait an empty entry in TRT 4651 if (not hit_read and (not wok or hit_write))4446 if (not hit_read and (not wok or hit_write)) 4652 4447 { 4653 4448 r_write_fsm = WRITE_WAIT; 4449 // <Activity counters> 4654 4450 m_cpt_trt_full++; 4655 4451 // </Activity counters> 4656 4452 break; 4657 4453 } … … 4668 4464 r_write_trt_index = hit_index; 4669 4465 r_write_fsm = WRITE_MISS_TRT_DATA; 4466 // <Activity counters> 4670 4467 m_cpt_write_miss++; 4468 // </Activity counters> 4671 4469 break; 4672 4470 } … … 4676 4474 r_write_trt_index = wok_index; 4677 4475 r_write_fsm = WRITE_MISS_TRT_SET; 4476 // <Activity counters> 4678 4477 m_cpt_write_miss++; 4478 // </Activity counters> 4679 4479 break; 4680 4480 } 4681 4481 4682 m_cpt_write_fsm_n_trt_lock ++;4683 4482 assert(false && "VCI_MEM_CACHE ERROR: this part must not be reached"); 4684 4483 } … … 4692 4491 4693 4492 #if DEBUG_MEMC_WRITE 4694 if (m_debug)4493 if (m_debug) 4695 4494 std::cout << " <MEMC " << name() << " WRITE_WAIT> Releases the locks before retry" << std::endl; 4696 4495 #endif … … 4702 4501 case WRITE_MISS_TRT_SET: // register a new transaction in TRT (Write Buffer) 4703 4502 { 4704 if (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE)4503 if (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) 4705 4504 { 4706 4505 std::vector<be_t> be_vector; … … 4727 4526 4728 4527 #if DEBUG_MEMC_WRITE 4729 if (m_debug)4528 if (m_debug) 4730 4529 std::cout << " <MEMC " << name() << " WRITE_MISS_TRT_SET> Set a new entry in TRT" << std::endl; 4731 4530 #endif … … 4737 4536 case WRITE_MISS_TRT_DATA: // update an entry in TRT (used as a Write Buffer) 4738 4537 { 4739 if (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE)4538 if (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) 4740 4539 { 4741 4540 std::vector<be_t> be_vector; … … 4754 4553 4755 4554 #if DEBUG_MEMC_WRITE 4756 if (m_debug)4555 if (m_debug) 4757 4556 std::cout << " <MEMC " << name() << " WRITE_MISS_TRT_DATA> Modify an existing entry in TRT" << std::endl; 4758 4557 #endif … … 4764 4563 case WRITE_MISS_XRAM_REQ: // send a GET request to IXR_CMD FSM 4765 4564 { 4766 if (not r_write_to_ixr_cmd_req.read())4565 if (not r_write_to_ixr_cmd_req.read()) 4767 4566 { 4768 4567 r_write_to_ixr_cmd_req = true; … … 4771 4570 4772 4571 #if DEBUG_MEMC_WRITE 4773 if (m_debug)4572 if (m_debug) 4774 4573 std::cout << " <MEMC " << name() 4775 4574 << " WRITE_MISS_XRAM_REQ> Post a GET request to the" … … 4796 4595 // (r_write_inval_trt_send.read() or not r_write_to_cleanup_req.read()); 4797 4596 4798 if (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE)4597 if (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) 4799 4598 { 4800 4599 bool wok = false; … … 4810 4609 //r_write_ivt_index = index; 4811 4610 4812 if (not ivt_full and cc_send_valid) //avoid to deadlock, we make sure that we can send cc_send request.4611 if (not ivt_full and cc_send_valid) //avoid to deadlock, we make sure that we can send cc_send request. 4813 4612 { 4814 4613 wok = m_ivt.set(false, // it's an inval transaction … … 4824 4623 index); 4825 4624 4826 if(is_brdcast) 4827 m_cpt_write_broadcast ++; 4828 else 4829 m_cpt_write_minval ++; 4625 // <Activity counters> 4626 if (is_brdcast) 4627 { 4628 m_cpt_write_broadcast++; 4629 } 4630 // </Activity counters> 4631 4830 4632 #if DEBUG_MEMC_WRITE 4831 if (m_debug and wok )4633 if (m_debug and wok ) 4832 4634 std::cout << " <MEMC " << name() << " WRITE_INVAL_IVT_LOCK> Register broadcast inval in IVT" 4833 4635 << "ivt index = " << index … … 4856 4658 { 4857 4659 4858 if (r_write_state.read() == ENTRY_SHARED)4660 if (r_write_state.read() == ENTRY_SHARED) 4859 4661 { 4860 4662 m_cache_data.write(way, set, word, r_write_data[word].read(), r_write_be[word].read()); … … 4880 4682 case WRITE_INVAL_CC_SEND: // Post a coherence broadcast request to CC_SEND FSM 4881 4683 { 4882 if (not r_write_to_cc_send_multi_req.read() and4684 if (not r_write_to_cc_send_multi_req.read() and 4883 4685 not r_write_to_cc_send_brdcast_req.read()) 4884 4686 { … … 4894 4696 r_write_next_ptr = r_write_ptr.read(); 4895 4697 4896 if (r_write_state.read() == ENTRY_EXCLUSIVE)4698 if (r_write_state.read() == ENTRY_EXCLUSIVE) 4897 4699 { 4898 4700 r_write_to_cleanup_req = true; … … 4900 4702 } 4901 4703 4902 if (not last_multi_inval and multi_inval)4704 if (not last_multi_inval and multi_inval) 4903 4705 { 4904 4706 r_write_fsm = WRITE_HEAP_REQ; … … 4909 4711 } 4910 4712 #if DEBUG_MEMC_WRITE 4911 if (m_debug)4713 if (m_debug) 4912 4714 std::cout << " <MEMC " << name() 4913 4715 << " WRITE_INVAL_CC_SEND> Post a inval request to CC_SEND FSM" << std::endl; … … 4948 4750 case IXR_CMD_READ_IDLE: 4949 4751 if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; 4950 else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;4951 else if (r_cleanup_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;4952 else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;4953 else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;4954 else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT;4752 else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; 4753 else if (r_cleanup_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT; 4754 else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; 4755 else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; 4756 else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; 4955 4757 break; 4956 4758 //////////////////////// 4957 4759 case IXR_CMD_WRITE_IDLE: 4958 4760 if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; 4959 else if (r_cleanup_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;4960 else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;4961 else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;4962 else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT;4963 else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;4761 else if (r_cleanup_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT; 4762 else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; 4763 else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; 4764 else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; 4765 else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; 4964 4766 break; 4965 4767 //////////////////////// 4966 4768 case IXR_CMD_CAS_IDLE: 4967 4769 if (r_cleanup_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT; 4968 else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;4969 else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;4970 else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT;4971 else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;4972 else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;4770 else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; 4771 else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; 4772 else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; 4773 else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; 4774 else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; 4973 4775 break; 4974 4776 //////////////////////// 4975 4777 case IXR_CMD_XRAM_IDLE: 4976 4778 if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; 4977 else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT;4978 else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;4979 else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;4980 else if (r_cleanup_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;4981 else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;4779 else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; 4780 else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; 4781 else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; 4782 else if (r_cleanup_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT; 4783 else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; 4982 4784 break; 4983 4785 //////////////////////// 4984 4786 case IXR_CMD_CLEANUP_IDLE: 4985 4787 if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; 4986 else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;4987 else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;4988 else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;4989 else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;4990 else if (r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;4788 else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; 4789 else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; 4790 else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; 4791 else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; 4792 else if (r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT; 4991 4793 break; 4992 4794 ///////////////////////// … … 4994 4796 { 4995 4797 if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; 4996 else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT;4997 else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT;4998 else if (r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;4999 else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT;5000 else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;4798 else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; 4799 else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; 4800 else if (r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT; 4801 else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; 4802 else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; 5001 4803 break; 5002 4804 } … … 5005 4807 case IXR_CMD_READ_TRT: // access TRT for a GET 5006 4808 { 5007 if ( 4809 if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) 5008 4810 { 5009 4811 TransactionTabEntry entry = m_trt.read( r_read_to_ixr_cmd_index.read() ); … … 5015 4817 5016 4818 #if DEBUG_MEMC_IXR_CMD 5017 if (m_debug)4819 if (m_debug) 5018 4820 std::cout << " <MEMC " << name() << " IXR_CMD_READ_TRT> TRT access" 5019 4821 << " index = " << std::dec << r_read_to_ixr_cmd_index.read() … … 5026 4828 case IXR_CMD_WRITE_TRT: // access TRT for a PUT or a GET 5027 4829 { 5028 if ( 4830 if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) 5029 4831 { 5030 4832 TransactionTabEntry entry = m_trt.read( r_write_to_ixr_cmd_index.read() ); … … 5042 4844 5043 4845 #if DEBUG_MEMC_IXR_CMD 5044 if (m_debug)4846 if (m_debug) 5045 4847 std::cout << " <MEMC " << name() << " IXR_CMD_WRITE_TRT> TRT access" 5046 4848 << " index = " << std::dec << r_write_to_ixr_cmd_index.read() … … 5053 4855 case IXR_CMD_CAS_TRT: // access TRT for a PUT or a GET 5054 4856 { 5055 if ( 4857 if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) 5056 4858 { 5057 4859 TransactionTabEntry entry = m_trt.read( r_cas_to_ixr_cmd_index.read() ); … … 5069 4871 5070 4872 #if DEBUG_MEMC_IXR_CMD 5071 if (m_debug)4873 if (m_debug) 5072 4874 std::cout << " <MEMC " << name() << " IXR_CMD_CAS_TRT> TRT access" 5073 4875 << " index = " << std::dec << r_cas_to_ixr_cmd_index.read() … … 5080 4882 case IXR_CMD_XRAM_TRT: // access TRT for a PUT 5081 4883 { 5082 if ( 4884 if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) 5083 4885 { 5084 4886 TransactionTabEntry entry = m_trt.read( r_xram_rsp_to_ixr_cmd_index.read() ); … … 5089 4891 r_ixr_cmd_fsm = IXR_CMD_XRAM_SEND; 5090 4892 for( size_t i=0 ; i<m_words ; i++ ) r_ixr_cmd_wdata[i] = entry.wdata[i]; 5091 5092 m_cpt_ixr_cmd_fsm_n_trt_lock ++;5093 4893 #if DEBUG_MEMC_IXR_CMD 5094 if (m_debug)4894 if (m_debug) 5095 4895 std::cout << " <MEMC " << name() << " IXR_CMD_XRAM_TRT> TRT access" 5096 4896 << " index = " << std::dec << r_xram_rsp_to_ixr_cmd_index.read() … … 5103 4903 case IXR_CMD_CLEANUP_TRT: // access TRT for a PUT 5104 4904 { 5105 if ( 4905 if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) 5106 4906 { 5107 4907 … … 5115 4915 5116 4916 #if DEBUG_MEMC_IXR_CMD 5117 if (m_debug)4917 if (m_debug) 5118 4918 std::cout << " <MEMC " << name() << " IXR_CMD_CLEANUP_TRT> TRT access" 5119 4919 << " index = " << std::dec << r_cleanup_to_ixr_cmd_index.read() … … 5126 4926 case IXR_CMD_CONFIG_TRT: // access TRT for a PUT 5127 4927 { 5128 if ( 4928 if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) 5129 4929 { 5130 4930 TransactionTabEntry entry = m_trt.read( r_config_to_ixr_cmd_index.read() ); … … 5137 4937 5138 4938 #if DEBUG_MEMC_IXR_CMD 5139 if (m_debug)4939 if (m_debug) 5140 4940 std::cout << " <MEMC " << name() << " IXR_CMD_CONFIG_TRT> TRT access" 5141 4941 << " index = " << std::dec << r_config_to_ixr_cmd_index.read() … … 5149 4949 case IXR_CMD_READ_SEND: // send a get from READ FSM 5150 4950 { 5151 if (p_vci_ixr.cmdack)4951 if (p_vci_ixr.cmdack) 5152 4952 { 5153 4953 r_ixr_cmd_fsm = IXR_CMD_READ_IDLE; … … 5155 4955 5156 4956 #if DEBUG_MEMC_IXR_CMD 5157 if (m_debug)4957 if (m_debug) 5158 4958 std::cout << " <MEMC " << name() << " IXR_CMD_READ_SEND> GET request:" << std::hex 5159 4959 << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; … … 5165 4965 case IXR_CMD_WRITE_SEND: // send a put or get from WRITE FSM 5166 4966 { 5167 if (p_vci_ixr.cmdack)4967 if (p_vci_ixr.cmdack) 5168 4968 { 5169 4969 if (not r_ixr_cmd_get.read()) // PUT 5170 4970 { 5171 if (r_ixr_cmd_word.read() == (m_words - 2))4971 if (r_ixr_cmd_word.read() == (m_words - 2)) 5172 4972 { 5173 4973 r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE; … … 5180 4980 5181 4981 #if DEBUG_MEMC_IXR_CMD 5182 if (m_debug)4982 if (m_debug) 5183 4983 std::cout << " <MEMC " << name() << " IXR_CMD_WRITE_SEND> PUT request:" << std::hex 5184 4984 << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; … … 5191 4991 5192 4992 #if DEBUG_MEMC_IXR_CMD 5193 if (m_debug)4993 if (m_debug) 5194 4994 std::cout << " <MEMC " << name() << " IXR_CMD_WRITE_SEND> GET request:" << std::hex 5195 4995 << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; … … 5202 5002 case IXR_CMD_CAS_SEND: // send a put or get command from CAS FSM 5203 5003 { 5204 if (p_vci_ixr.cmdack)5004 if (p_vci_ixr.cmdack) 5205 5005 { 5206 5006 if (not r_ixr_cmd_get.read()) // PUT 5207 5007 { 5208 if (r_ixr_cmd_word.read() == (m_words - 2))5008 if (r_ixr_cmd_word.read() == (m_words - 2)) 5209 5009 { 5210 5010 r_ixr_cmd_fsm = IXR_CMD_CAS_IDLE; … … 5217 5017 5218 5018 #if DEBUG_MEMC_IXR_CMD 5219 if (m_debug)5019 if (m_debug) 5220 5020 std::cout << " <MEMC " << name() << " IXR_CMD_CAS_SEND> PUT request:" << std::hex 5221 5021 << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; … … 5228 5028 5229 5029 #if DEBUG_MEMC_IXR_CMD 5230 if (m_debug)5030 if (m_debug) 5231 5031 std::cout << " <MEMC " << name() << " IXR_CMD_CAS_SEND> GET request:" << std::hex 5232 5032 << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; … … 5239 5039 case IXR_CMD_XRAM_SEND: // send a put from XRAM_RSP FSM 5240 5040 { 5241 if (p_vci_ixr.cmdack.read())5242 { 5243 if (r_ixr_cmd_word.read() == (m_words - 2))5041 if (p_vci_ixr.cmdack.read()) 5042 { 5043 if (r_ixr_cmd_word.read() == (m_words - 2)) 5244 5044 { 5245 5045 r_ixr_cmd_fsm = IXR_CMD_XRAM_IDLE; … … 5251 5051 } 5252 5052 #if DEBUG_MEMC_IXR_CMD 5253 if (m_debug)5053 if (m_debug) 5254 5054 std::cout << " <MEMC " << name() << " IXR_CMD_XRAM_SEND> PUT request:" << std::hex 5255 5055 << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; … … 5262 5062 case IXR_CMD_CLEANUP_DATA_SEND: // send a put command to XRAM 5263 5063 { 5264 if (p_vci_ixr.cmdack.read())5265 { 5266 if (r_ixr_cmd_word.read() == (m_words - 2))5064 if (p_vci_ixr.cmdack.read()) 5065 { 5066 if (r_ixr_cmd_word.read() == (m_words - 2)) 5267 5067 { 5268 5068 r_ixr_cmd_fsm = IXR_CMD_CLEANUP_IDLE; … … 5277 5077 5278 5078 #if DEBUG_MEMC_IXR_CMD 5279 if (m_debug)5079 if (m_debug) 5280 5080 { 5281 5081 std::cout << " <MEMC " << name() << ".IXR_CMD_CLEANUP_DATA_SEND> Send a put request to xram" << std::endl; … … 5289 5089 case IXR_CMD_CONFIG_SEND: // send a put from CONFIG FSM 5290 5090 { 5291 if (p_vci_ixr.cmdack.read())5292 { 5293 if (r_ixr_cmd_word.read() == (m_words - 2))5091 if (p_vci_ixr.cmdack.read()) 5092 { 5093 if (r_ixr_cmd_word.read() == (m_words - 2)) 5294 5094 { 5295 5095 r_ixr_cmd_fsm = IXR_CMD_CONFIG_IDLE; … … 5302 5102 5303 5103 #if DEBUG_MEMC_IXR_CMD 5304 if (m_debug)5104 if (m_debug) 5305 5105 std::cout << " <MEMC " << name() << " IXR_CMD_CONFIG_SEND> PUT request:" << std::hex 5306 5106 << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; … … 5337 5137 case IXR_RSP_IDLE: // test transaction type: PUT/GET 5338 5138 { 5339 if (p_vci_ixr.rspval.read())5139 if (p_vci_ixr.rspval.read()) 5340 5140 { 5341 5141 r_ixr_rsp_cpt = 0; … … 5345 5145 "MEMC ERROR in IXR_RSP state: XRAM response error !"); 5346 5146 5347 if (p_vci_ixr.reop.read()) // PUT5147 if (p_vci_ixr.reop.read()) // PUT 5348 5148 { 5349 5149 r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE; … … 5355 5155 5356 5156 #if DEBUG_MEMC_IXR_RSP 5357 if (m_debug)5157 if (m_debug) 5358 5158 std::cout << " <MEMC " << name() 5359 5159 << " IXR_RSP_IDLE> Response from XRAM to a get transaction" << std::endl; … … 5374 5174 // decrease the line counter if config request 5375 5175 { 5376 if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP)5176 if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) 5377 5177 { 5378 5178 size_t index = r_ixr_rsp_trt_index.read(); … … 5388 5188 r_ixr_rsp_fsm = IXR_RSP_IDLE; 5389 5189 } 5390 5391 m_cpt_ixr_rsp_fsm_n_trt_lock ++;5392 5190 #if DEBUG_MEMC_IXR_RSP 5393 if (m_debug)5191 if (m_debug) 5394 5192 std::cout << " <MEMC " << name() << " IXR_RSP_TRT_ERASE> Erase TRT entry " 5395 5193 << r_ixr_rsp_trt_index.read() << std::endl; … … 5401 5199 case IXR_RSP_TRT_READ: // write a 64 bits data in the TRT 5402 5200 { 5403 if ((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and p_vci_ixr.rspval)5201 if ((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and p_vci_ixr.rspval) 5404 5202 { 5405 5203 size_t index = r_ixr_rsp_trt_index.read(); … … 5418 5216 r_ixr_rsp_cpt = word + 2; 5419 5217 5420 if (eop)5218 if (eop) 5421 5219 { 5422 5220 r_ixr_rsp_to_xram_rsp_rok[r_ixr_rsp_trt_index.read()]=true; … … 5425 5223 5426 5224 #if DEBUG_MEMC_IXR_RSP 5427 if (m_debug)5225 if (m_debug) 5428 5226 std::cout << " <MEMC " << name() << " IXR_RSP_TRT_READ> Writing a word in TRT : " 5429 5227 << " index = " << std::dec << index … … 5431 5229 << " / data = " << std::hex << data << std::endl; 5432 5230 #endif 5433 m_cpt_ixr_rsp_fsm_n_trt_lock ++; 5434 } 5435 m_cpt_ixr_fsm_trt_lock++; 5231 } 5436 5232 break; 5437 5233 } … … 5471 5267 { 5472 5268 size_t index = (i+old+1) %lines; 5473 if (r_ixr_rsp_to_xram_rsp_rok[index])5269 if (r_ixr_rsp_to_xram_rsp_rok[index]) 5474 5270 { 5475 5271 r_xram_rsp_trt_index = index; … … 5478 5274 5479 5275 #if DEBUG_MEMC_XRAM_RSP 5480 if (m_debug)5276 if (m_debug) 5481 5277 std::cout << " <MEMC " << name() << " XRAM_RSP_IDLE>" 5482 5278 << " Available cache line in TRT:" … … 5492 5288 // Copy the TRT entry in a local buffer 5493 5289 { 5494 if ((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and5290 if ((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and 5495 5291 (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP)) 5496 5292 { … … 5501 5297 5502 5298 #if DEBUG_MEMC_XRAM_RSP 5503 if (m_debug)5299 if (m_debug) 5504 5300 std::cout << " <MEMC " << name() << " XRAM_RSP_DIR_LOCK>" 5505 5301 << " Get access to DIR and TRT" << std::endl; 5506 5302 #endif 5507 m_cpt_xram_rsp_fsm_n_dir_lock++; 5508 m_cpt_xram_rsp_fsm_n_trt_lock++; 5509 } 5510 m_cpt_xram_rsp_fsm_dir_lock++; 5511 m_cpt_xram_rsp_fsm_trt_lock++; 5303 } 5512 5304 break; 5513 5305 } … … 5528 5320 DirectoryEntry victim(m_cache_directory.select(set, way)); 5529 5321 5530 if (way == -1)5322 if (way == -1) 5531 5323 { 5532 5324 #if DEBUG_MEMC_XRAM_RSP 5533 if (m_debug)5325 if (m_debug) 5534 5326 std::cout << " <MEMC " << name() << " XRAM_RSP_TRT_COPY>" 5535 5327 << " not a disponible victim" … … 5559 5351 assert( victim.state != ENTRY_LOCKED && "XRAM RSP SELECTED A LOCKED VICTIM "); 5560 5352 5561 if (not r_xram_rsp_trt_buf.rerror ) r_xram_rsp_fsm = XRAM_RSP_IVT_LOCK;5353 if (not r_xram_rsp_trt_buf.rerror ) r_xram_rsp_fsm = XRAM_RSP_IVT_LOCK; 5562 5354 else r_xram_rsp_fsm = XRAM_RSP_ERROR_ERASE; 5563 5355 5564 5356 #if DEBUG_MEMC_XRAM_RSP 5565 if (m_debug)5357 if (m_debug) 5566 5358 std::cout << " <MEMC " << name() << " XRAM_RSP_TRT_COPY>" 5567 5359 << " Select a victim slot: " … … 5585 5377 "MEMC ERROR in XRAM_RSP_IVT_LOCK state: Bad TRT allocation"); 5586 5378 5587 if (r_alloc_ivt_fsm == ALLOC_IVT_XRAM_RSP)5379 if (r_alloc_ivt_fsm == ALLOC_IVT_XRAM_RSP) 5588 5380 { 5589 5381 size_t index = 0; 5590 if (m_ivt.search_inval(r_xram_rsp_trt_buf.nline, index)) // pending inval5382 if (m_ivt.search_inval(r_xram_rsp_trt_buf.nline, index)) // pending inval 5591 5383 { 5592 5384 r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; 5593 5385 5594 5386 #if DEBUG_MEMC_XRAM_RSP 5595 if (m_debug)5387 if (m_debug) 5596 5388 std::cout << " <MEMC " << name() << " XRAM_RSP_IVT_LOCK>" 5597 5389 << " Get acces to IVT, but line invalidation registered" … … 5601 5393 5602 5394 } 5603 else if (m_ivt.is_full() and r_xram_rsp_victim_inval.read()) // IVT full5395 else if (m_ivt.is_full() and r_xram_rsp_victim_inval.read()) // IVT full 5604 5396 { 5605 5397 r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; 5606 5398 5607 5399 #if DEBUG_MEMC_XRAM_RSP 5608 if (m_debug)5400 if (m_debug) 5609 5401 std::cout << " <MEMC " << name() << " XRAM_RSP_IVT_LOCK>" 5610 5402 << " Get acces to IVT, but inval required and IVT full" << std::endl; … … 5616 5408 5617 5409 #if DEBUG_MEMC_XRAM_RSP 5618 if (m_debug)5410 if (m_debug) 5619 5411 std::cout << " <MEMC " << name() << " XRAM_RSP_IVT_LOCK>" 5620 5412 << " Get acces to IVT / no pending inval request" << std::endl; … … 5629 5421 5630 5422 #if DEBUG_MEMC_XRAM_RSP 5631 if (m_debug)5423 if (m_debug) 5632 5424 std::cout << " <MEMC " << name() << " XRAM_RSP_INVAL_WAIT>" 5633 5425 << " Release all locks and retry" << std::endl; … … 5680 5472 DirectoryEntry entry; 5681 5473 5682 if (inst_read and (r_xram_rsp_trt_buf.proc_read))5474 if (inst_read and (r_xram_rsp_trt_buf.proc_read)) 5683 5475 { 5684 5476 entry.state = ENTRY_SHARED; … … 5694 5486 entry.tag = r_xram_rsp_trt_buf.nline / m_sets; 5695 5487 entry.ptr = 0; 5696 if (cached_read and r_xram_rsp_trt_buf.proc_read)5488 if (cached_read and r_xram_rsp_trt_buf.proc_read) 5697 5489 { 5698 5490 entry.owner.srcid = r_xram_rsp_trt_buf.srcid; … … 5710 5502 r_xram_rsp_coherent = inst_read; 5711 5503 // request an invalidattion request in IVT for victim line 5712 if (r_xram_rsp_victim_inval.read())5504 if (r_xram_rsp_victim_inval.read()) 5713 5505 { 5714 5506 bool broadcast = r_xram_rsp_victim_is_cnt.read(); … … 5743 5535 // } 5744 5536 #if DEBUG_MEMC_XRAM_RSP 5745 if (m_debug)5537 if (m_debug) 5746 5538 { 5747 5539 std::cout << " <MEMC " << name() << " XRAM_RSP_DIR_UPDT>" … … 5754 5546 << " / nline = " << r_xram_rsp_trt_buf.nline 5755 5547 << " / is_cnt = " << entry.is_cnt << std::endl; 5756 if (r_xram_rsp_victim_inval.read())5548 if (r_xram_rsp_victim_inval.read()) 5757 5549 std::cout << " Invalidation request for victim line " 5758 5550 << std::hex << r_xram_rsp_victim_nline.read() … … 5763 5555 // If the victim is not dirty (RWT: if it is not coherent, we can not know wether it is dirty or not), we don't need another XRAM put transaction, 5764 5556 // and we can erase the TRT entry 5765 if ((not r_xram_rsp_victim_dirty.read()) or (r_xram_rsp_victim_state.read() == ENTRY_INVALID))5557 if ((not r_xram_rsp_victim_dirty.read()) or (r_xram_rsp_victim_state.read() == ENTRY_INVALID)) 5766 5558 { 5767 5559 m_trt.erase(r_xram_rsp_trt_index.read()); 5768 5560 } 5769 5561 // Next state 5770 if (r_xram_rsp_victim_dirty.read()) r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY;5771 else if (r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;5772 else if (r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL;5562 if (r_xram_rsp_victim_dirty.read()) r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY; 5563 else if (r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_DIR_RSP; 5564 else if (r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; 5773 5565 else r_xram_rsp_fsm = XRAM_RSP_IDLE; 5774 5566 break; … … 5777 5569 case XRAM_RSP_TRT_DIRTY: // set the TRT entry (write to XRAM) if the victim is dirty or not coherent (RWT) 5778 5570 { 5779 if (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP)5571 if (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) 5780 5572 { 5781 5573 std::vector<data_t> data_vector; … … 5798 5590 data_vector); 5799 5591 #if DEBUG_MEMC_XRAM_RSP 5800 if (m_debug)5592 if (m_debug) 5801 5593 std::cout << " <MEMC " << name() << " XRAM_RSP_TRT_DIRTY>" 5802 5594 << " Set TRT entry for the put transaction" … … 5804 5596 #endif 5805 5597 5806 // if (not r_xram_rsp_victim_coherent )5598 // if (not r_xram_rsp_victim_coherent ) 5807 5599 // std::cout << "a victim coherent not sent trt index =" << r_xram_rsp_trt_index.read() << std::endl; 5808 if (r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_DIR_RSP;5809 else if (r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL;5600 if (r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_DIR_RSP; 5601 else if (r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; 5810 5602 else r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; 5811 m_cpt_xram_rsp_fsm_n_trt_lock++; 5812 } 5813 5814 m_cpt_xram_rsp_fsm_trt_lock++; 5815 5603 } 5816 5604 break; 5817 5605 } … … 5819 5607 case XRAM_RSP_DIR_RSP: // Request a response to TGT_RSP FSM 5820 5608 { 5821 if (not r_xram_rsp_to_tgt_rsp_req.read())5609 if (not r_xram_rsp_to_tgt_rsp_req.read()) 5822 5610 { 5823 5611 r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid; … … 5842 5630 5843 5631 5844 if (r_xram_rsp_victim_inval) r_xram_rsp_fsm = XRAM_RSP_INVAL;5845 else if (r_xram_rsp_victim_dirty) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY;5632 if (r_xram_rsp_victim_inval) r_xram_rsp_fsm = XRAM_RSP_INVAL; 5633 else if (r_xram_rsp_victim_dirty) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; 5846 5634 else r_xram_rsp_fsm = XRAM_RSP_IDLE; 5847 5635 5848 5636 #if DEBUG_MEMC_XRAM_RSP 5849 if (m_debug)5637 if (m_debug) 5850 5638 std::cout << " <MEMC " << name() << " XRAM_RSP_DIR_RSP>" 5851 5639 << " Request the TGT_RSP FSM to return data:" … … 5861 5649 case XRAM_RSP_INVAL: // send invalidate request to CC_SEND FSM 5862 5650 { 5863 if (!r_xram_rsp_to_cc_send_multi_req.read() and5651 if (!r_xram_rsp_to_cc_send_multi_req.read() and 5864 5652 !r_xram_rsp_to_cc_send_brdcast_req.read()) 5865 5653 { … … 5877 5665 r_xram_rsp_next_ptr = r_xram_rsp_victim_ptr.read(); 5878 5666 5879 if (r_xram_rsp_victim_dirty.read() and (r_xram_rsp_victim_state.read() == ENTRY_SHARED))5667 if (r_xram_rsp_victim_dirty.read() and (r_xram_rsp_victim_state.read() == ENTRY_SHARED)) 5880 5668 r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; 5881 else if (not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ;5669 else if (not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ; 5882 5670 else r_xram_rsp_fsm = XRAM_RSP_IDLE; 5883 5671 5884 5672 // std::cout << "cleanup sent for trt index =" << r_xram_rsp_trt_index.read() << std::endl; 5885 5673 #if DEBUG_MEMC_XRAM_RSP 5886 if (m_debug)5674 if (m_debug) 5887 5675 std::cout << " <MEMC " << name() << " XRAM_RSP_INVAL>" 5888 5676 << " Send an inval request to CC_SEND FSM" … … 5893 5681 { 5894 5682 #if DEBUG_MEMC_XRAM_RSP 5895 if (m_debug)5683 if (m_debug) 5896 5684 std::cout << " <MEMC " << name() << " XRAM_RSP_INVAL>" 5897 5685 << " multi req = " << r_xram_rsp_to_cc_send_multi_req.read() … … 5904 5692 case XRAM_RSP_WRITE_DIRTY: // send a write request to IXR_CMD FSM 5905 5693 { 5906 if ( 5907 { 5908 if ((r_xram_rsp_victim_state.read() == ENTRY_EXCLUSIVE) and (r_xram_rsp_victim_count.read() == 1))5694 if (not r_xram_rsp_to_ixr_cmd_req.read() ) 5695 { 5696 if ((r_xram_rsp_victim_state.read() == ENTRY_EXCLUSIVE) and (r_xram_rsp_victim_count.read() == 1)) 5909 5697 { 5910 5698 std::cout << "can't send a trt req when the line state is exlusive" << std::endl; … … 5914 5702 r_xram_rsp_to_ixr_cmd_index = r_xram_rsp_trt_index.read(); 5915 5703 5704 // <Activity counters> 5916 5705 m_cpt_write_dirty++; 5706 // </Activity counters> 5917 5707 5918 5708 bool multi_req = not r_xram_rsp_victim_is_cnt.read() and … … 5920 5710 bool not_last_multi_req = multi_req and (r_xram_rsp_victim_count.read() != 1); 5921 5711 5922 if (not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ;5712 if (not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ; 5923 5713 else r_xram_rsp_fsm = XRAM_RSP_IDLE; 5924 5714 5925 5715 #if DEBUG_MEMC_XRAM_RSP 5926 if (m_debug)5716 if (m_debug) 5927 5717 std::cout << " <MEMC " << name() << " XRAM_RSP_WRITE_DIRTY>" 5928 5718 << " Send the put request to IXR_CMD FSM" … … 5935 5725 case XRAM_RSP_HEAP_REQ: // Get the lock to the HEAP 5936 5726 { 5937 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP)5727 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP) 5938 5728 { 5939 5729 r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE; 5940 m_cpt_xram_rsp_fsm_n_heap_lock++;5941 5730 } 5942 5731 5943 5732 #if DEBUG_MEMC_XRAM_RSP 5944 if (m_debug)5733 if (m_debug) 5945 5734 std::cout << " <MEMC " << name() << " XRAM_RSP_HEAP_REQ>" 5946 5735 << " Requesting HEAP lock" << std::endl; 5947 5736 #endif 5948 5949 m_cpt_xram_rsp_fsm_heap_lock++;5950 5951 5737 break; 5952 5738 } … … 5954 5740 case XRAM_RSP_HEAP_ERASE: // erase the copies and send invalidations 5955 5741 { 5956 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP)5742 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP) 5957 5743 { 5958 5744 HeapEntry entry = m_heap.read(r_xram_rsp_next_ptr.read()); … … 5961 5747 xram_rsp_to_cc_send_fifo_inst = entry.owner.inst; 5962 5748 xram_rsp_to_cc_send_fifo_put = true; 5963 if (m_xram_rsp_to_cc_send_inst_fifo.wok())5749 if (m_xram_rsp_to_cc_send_inst_fifo.wok()) 5964 5750 { 5965 5751 r_xram_rsp_next_ptr = entry.next; 5966 if (entry.next == r_xram_rsp_next_ptr.read()) // last copy5752 if (entry.next == r_xram_rsp_next_ptr.read()) // last copy 5967 5753 { 5968 5754 r_xram_rsp_to_cc_send_multi_req = true; … … 5980 5766 5981 5767 #if DEBUG_MEMC_XRAM_RSP 5982 if (m_debug)5768 if (m_debug) 5983 5769 std::cout << " <MEMC " << name() << " XRAM_RSP_HEAP_ERASE>" 5984 5770 << " Erase copy:" … … 5994 5780 case XRAM_RSP_HEAP_LAST: // last copy 5995 5781 { 5996 if (r_alloc_heap_fsm.read() != ALLOC_HEAP_XRAM_RSP)5782 if (r_alloc_heap_fsm.read() != ALLOC_HEAP_XRAM_RSP) 5997 5783 { 5998 5784 std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_HEAP_LAST" … … 6005 5791 last_entry.owner.srcid = 0; 6006 5792 last_entry.owner.inst = false; 6007 if (m_heap.is_full())5793 if (m_heap.is_full()) 6008 5794 { 6009 5795 last_entry.next = r_xram_rsp_next_ptr.read(); … … 6021 5807 6022 5808 #if DEBUG_MEMC_XRAM_RSP 6023 if (m_debug)5809 if (m_debug) 6024 5810 std::cout << " <MEMC " << name() << " XRAM_RSP_HEAP_LAST>" 6025 5811 << " Heap housekeeping" << std::endl; … … 6033 5819 6034 5820 // Next state 6035 if (r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_ERROR_RSP;5821 if (r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_ERROR_RSP; 6036 5822 else r_xram_rsp_fsm = XRAM_RSP_IDLE; 6037 5823 6038 5824 #if DEBUG_MEMC_XRAM_RSP 6039 if (m_debug)5825 if (m_debug) 6040 5826 std::cout << " <MEMC " << name() << " XRAM_RSP_ERROR_ERASE>" 6041 5827 << " Error reported by XRAM / erase the TRT entry" << std::endl; … … 6046 5832 case XRAM_RSP_ERROR_RSP: // Request an error response to TGT_RSP FSM 6047 5833 { 6048 if (!r_xram_rsp_to_tgt_rsp_req.read())5834 if (!r_xram_rsp_to_tgt_rsp_req.read()) 6049 5835 { 6050 5836 r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid; … … 6063 5849 6064 5850 #if DEBUG_MEMC_XRAM_RSP 6065 if (m_debug)5851 if (m_debug) 6066 5852 std::cout << " <MEMC " << name() 6067 5853 << " XRAM_RSP_ERROR_RSP> Request a response error to TGT_RSP FSM:" … … 6085 5871 case CLEANUP_IDLE: // Get first DSPIN flit of the CLEANUP command 6086 5872 { 6087 if (not m_cc_receive_to_cleanup_fifo.rok()) break;5873 if (not m_cc_receive_to_cleanup_fifo.rok()) break; 6088 5874 6089 5875 uint64_t flit = m_cc_receive_to_cleanup_fifo.read(); 6090 5876 6091 5877 uint32_t srcid = 6092 Dspin DhccpParam::dspin_get(5878 DspinHmesiParam::dspin_get( 6093 5879 flit, 6094 Dspin DhccpParam::CLEANUP_SRCID);5880 DspinHmesiParam::CLEANUP_SRCID); 6095 5881 6096 5882 uint8_t type = 6097 Dspin DhccpParam::dspin_get(5883 DspinHmesiParam::dspin_get( 6098 5884 flit, 6099 Dspin DhccpParam::P2M_TYPE);5885 DspinHmesiParam::P2M_TYPE); 6100 5886 6101 5887 r_cleanup_way_index = 6102 Dspin DhccpParam::dspin_get(5888 DspinHmesiParam::dspin_get( 6103 5889 flit, 6104 Dspin DhccpParam::CLEANUP_WAY_INDEX);5890 DspinHmesiParam::CLEANUP_WAY_INDEX); 6105 5891 6106 5892 r_cleanup_nline = 6107 Dspin DhccpParam::dspin_get(5893 DspinHmesiParam::dspin_get( 6108 5894 flit, 6109 Dspin DhccpParam::CLEANUP_NLINE_MSB) << 32;6110 6111 r_cleanup_inst = (type == Dspin DhccpParam::TYPE_CLEANUP_INST);5895 DspinHmesiParam::CLEANUP_NLINE_MSB) << 32; 5896 5897 r_cleanup_inst = (type == DspinHmesiParam::TYPE_CLEANUP_INST); 6112 5898 r_cleanup_srcid = srcid; 6113 5899 r_cleanup_ncc = 6114 Dspin DhccpParam::dspin_get(5900 DspinHmesiParam::dspin_get( 6115 5901 flit, 6116 Dspin DhccpParam::DATA_NO_SHARED);5902 DspinHmesiParam::DATA_NO_SHARED); 6117 5903 6118 5904 assert( (srcid < m_initiators) and 6119 5905 "MEMC ERROR in CLEANUP_IDLE state : illegal SRCID value"); 6120 5906 6121 // <Activity Counters>6122 if (is_local_req(srcid)) {6123 m_cpt_cleanup_local++;6124 }6125 else {6126 m_cpt_cleanup_remote++;6127 m_cpt_cleanup_cost += req_distance(srcid);6128 }6129 // </Activity Counters>6130 5907 cc_receive_to_cleanup_fifo_get = true; 6131 5908 r_cleanup_fsm = CLEANUP_GET_NLINE; 6132 5909 6133 5910 #if DEBUG_MEMC_CLEANUP 6134 if (m_debug)5911 if (m_debug) 6135 5912 { 6136 5913 std::cout … … 6138 5915 << " CLEANUP_IDLE> Cleanup request:" << std::hex 6139 5916 << " / owner_id = " << srcid 6140 << " / owner_ins = " << (type == Dspin DhccpParam::TYPE_CLEANUP_INST)6141 << " / ncc = " << Dspin DhccpParam::dspin_get(5917 << " / owner_ins = " << (type == DspinHmesiParam::TYPE_CLEANUP_INST) 5918 << " / ncc = " << DspinHmesiParam::dspin_get( 6142 5919 flit, 6143 Dspin DhccpParam::DATA_NO_SHARED)5920 DspinHmesiParam::DATA_NO_SHARED) 6144 5921 << std::endl; 6145 5922 } … … 6151 5928 case CLEANUP_GET_NLINE: // GET second DSPIN flit of the cleanup command 6152 5929 { 6153 if (not m_cc_receive_to_cleanup_fifo.rok()) break;5930 if (not m_cc_receive_to_cleanup_fifo.rok()) break; 6154 5931 6155 5932 uint64_t flit = m_cc_receive_to_cleanup_fifo.read(); 5933 uint32_t srcid = r_cleanup_srcid.read(); 6156 5934 6157 5935 addr_t nline = r_cleanup_nline.read() | 6158 Dspin DhccpParam::dspin_get(flit, DspinDhccpParam::CLEANUP_NLINE_LSB);5936 DspinHmesiParam::dspin_get(flit, DspinHmesiParam::CLEANUP_NLINE_LSB); 6159 5937 6160 5938 //A MODIFIER POUR DIRTY // 6161 5939 bool eop = 6162 Dspin DhccpParam::dspin_get(flit, DspinDhccpParam::P2M_EOP) == 0x1;5940 DspinHmesiParam::dspin_get(flit, DspinHmesiParam::P2M_EOP) == 0x1; 6163 5941 if (! eop) 6164 5942 { … … 6166 5944 r_cleanup_data_index = 0; 6167 5945 r_cleanup_contains_data = true; 6168 m_cpt_cleanup_with_data ++; 5946 // <Activity Counters> 5947 if (is_local_req(srcid)) { 5948 m_cpt_cleanup_local++; 5949 m_cpt_cleanup_data_local++; 5950 } 5951 else { 5952 m_cpt_cleanup_remote++; 5953 m_cpt_cleanup_data_remote++; 5954 } 5955 // 2 + m_words flits for cleanup with data 5956 m_cpt_cleanup_cost += (m_words + 2) * req_distance(srcid); 5957 m_cpt_cleanup_data_cost += (m_words + 2) * req_distance(srcid); 5958 // </Activity Counters> 6169 5959 } 6170 5960 else 6171 5961 { 6172 /*// if( (r_write_to_cleanup_req.read() == true) and (r_write_to_cleanup_nline.read() == nline ))6173 {6174 std::cout << "receive write nline without data" << std::hex << nline << std::endl;6175 6176 }*/6177 5962 r_cleanup_contains_data = false; 6178 5963 r_cleanup_fsm = CLEANUP_DIR_REQ; 5964 // <Activity Counters> 5965 if (is_local_req(srcid)) { 5966 m_cpt_cleanup_local++; 5967 } 5968 else { 5969 m_cpt_cleanup_remote++; 5970 } 5971 // 2 flits for cleanup without data 5972 m_cpt_cleanup_cost += 2 * req_distance(srcid); 5973 // </Activity Counters> 6179 5974 } 6180 5975 cc_receive_to_cleanup_fifo_get = true; 6181 r_cleanup_nline 5976 r_cleanup_nline = nline; 6182 5977 6183 5978 #if DEBUG_MEMC_CLEANUP 6184 if (m_debug)5979 if (m_debug) 6185 5980 { 6186 5981 std::cout … … 6203 5998 6204 5999 uint32_t data = 6205 Dspin DhccpParam::dspin_get (flit, DspinDhccpParam::CLEANUP_DATA_UPDT);6206 6207 if ((r_write_to_cleanup_req.read() == true) and (r_write_to_cleanup_nline.read() == r_cleanup_nline.read()) )6000 DspinHmesiParam::dspin_get (flit, DspinHmesiParam::CLEANUP_DATA_UPDT); 6001 6002 if ((r_write_to_cleanup_req.read() == true) and (r_write_to_cleanup_nline.read() == r_cleanup_nline.read()) ) 6208 6003 { 6209 6004 data_t mask = 0; 6210 if (r_write_to_cleanup_be[r_cleanup_data_index.read()].read() & 0x1) mask = mask | 0x000000FF;6211 if (r_write_to_cleanup_be[r_cleanup_data_index.read()].read() & 0x2) mask = mask | 0x0000FF00;6212 if (r_write_to_cleanup_be[r_cleanup_data_index.read()].read() & 0x4) mask = mask | 0x00FF0000;6213 if (r_write_to_cleanup_be[r_cleanup_data_index.read()].read() & 0x8) mask = mask | 0xFF000000;6005 if (r_write_to_cleanup_be[r_cleanup_data_index.read()].read() & 0x1) mask = mask | 0x000000FF; 6006 if (r_write_to_cleanup_be[r_cleanup_data_index.read()].read() & 0x2) mask = mask | 0x0000FF00; 6007 if (r_write_to_cleanup_be[r_cleanup_data_index.read()].read() & 0x4) mask = mask | 0x00FF0000; 6008 if (r_write_to_cleanup_be[r_cleanup_data_index.read()].read() & 0x8) mask = mask | 0xFF000000; 6214 6009 6215 6010 // complete only if mask is not null (for energy consumption) … … 6231 6026 } 6232 6027 #if DEBUG_MEMC_CLEANUP 6233 if (m_debug)6028 if (m_debug) 6234 6029 { 6235 6030 std::cout … … 6247 6042 case CLEANUP_DIR_REQ: // Get the lock to the directory 6248 6043 { 6249 m_cpt_cleanup_fsm_dir_lock++; 6250 if(r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP) break; 6044 if (r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP) break; 6251 6045 6252 6046 r_cleanup_fsm = CLEANUP_DIR_LOCK; … … 6254 6048 6255 6049 #if DEBUG_MEMC_CLEANUP 6256 if (m_debug)6050 if (m_debug) 6257 6051 std::cout << " <MEMC " << name() << " CLEANUP_DIR_REQ> Requesting DIR lock" << std::endl; 6258 6052 #endif 6259 6260 m_cpt_cleanup_fsm_n_dir_lock++;6261 6262 6053 break; 6263 6054 } … … 6267 6058 { 6268 6059 // test directory status 6269 if (r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP)6060 if (r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP) 6270 6061 { 6271 6062 std::cout … … 6292 6083 r_cleanup_state = entry.state; 6293 6084 6294 if (entry.state == ENTRY_LOCKED)6085 if (entry.state == ENTRY_LOCKED) 6295 6086 { 6296 6087 assert( … … 6302 6093 r_cleanup_fsm = CLEANUP_LOCKED_IVT_LOCK; 6303 6094 } 6304 else if (entry.state == ENTRY_INVALID)6095 else if (entry.state == ENTRY_INVALID) 6305 6096 { 6306 6097 r_cleanup_fsm = CLEANUP_MISS_IVT_LOCK; … … 6313 6104 "In CLEANUP_DIR_LOCK, CLEANUP command on a valid entry " 6314 6105 "with no copies"); 6315 if ((entry.state == ENTRY_SHARED) and (entry.is_cnt == true))6106 if ((entry.state == ENTRY_SHARED) and (entry.is_cnt == true)) 6316 6107 { 6317 6108 r_cleanup_fsm = CLEANUP_DIR_WRITE; 6318 6109 } 6319 else if ((entry.state == ENTRY_EXCLUSIVE) or (entry.count == 1))6110 else if ((entry.state == ENTRY_EXCLUSIVE) or (entry.count == 1)) 6320 6111 { 6321 6112 r_cleanup_fsm = CLEANUP_DIR_WRITE; … … 6328 6119 6329 6120 #if DEBUG_MEMC_CLEANUP 6330 if (m_debug)6121 if (m_debug) 6331 6122 { 6332 6123 std::cout … … 6353 6144 { 6354 6145 // Update the directory entry without heap access 6355 if (r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP)6146 if (r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP) 6356 6147 { 6357 6148 std::cout … … 6370 6161 bool match = match_srcid and match_inst; 6371 6162 6372 if ((r_cleanup_state.read() == ENTRY_EXCLUSIVE) and not match )6163 if ((r_cleanup_state.read() == ENTRY_EXCLUSIVE) and not match ) 6373 6164 { 6374 6165 std::cout … … 6392 6183 entry.state = r_cleanup_state.read(); 6393 6184 6394 if (entry.count == 0)6185 if (entry.count == 0) 6395 6186 { 6396 6187 entry.is_cnt = 0; … … 6416 6207 6417 6208 #if DEBUG_MEMC_CLEANUP 6418 if (m_debug)6209 if (m_debug) 6419 6210 { 6420 6211 std::cout … … 6438 6229 { 6439 6230 //Search for a matching inval in the ivt (there must be one) and check if there is a pending read or cas. 6440 6441 m_cpt_cleanup_fsm_ivt_lock++; 6442 if(r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP) 6231 if (r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP) 6443 6232 { 6444 6233 size_t index = 0; … … 6468 6257 r_cleanup_locked_is_read = m_ivt.is_read(index); 6469 6258 6470 if (m_ivt.is_update(index) and not m_ivt.is_changed(index))6259 if (m_ivt.is_update(index) and not m_ivt.is_changed(index)) 6471 6260 { 6472 6261 r_cleanup_fsm = CLEANUP_LOCKED_IVT_CLEAR; … … 6493 6282 m_ivt.decrement(r_cleanup_locked_index.read(), count); 6494 6283 6495 if (count == 0)6284 if (count == 0) 6496 6285 { 6497 6286 r_cleanup_fsm = CLEANUP_LOCKED_IVT_CLEAR; … … 6504 6293 6505 6294 #if DEBUG_MEMC_CLEANUP 6506 if (m_debug)6295 if (m_debug) 6507 6296 std::cout << " <MEMC " << name() << " CLEANUP_LOCKED_IVT_DECREMENT>" 6508 6297 << " Decrement response counter in IVT:" … … 6534 6323 entry.ptr = r_cleanup_ptr.read(); 6535 6324 6536 if (not r_cleanup_contains_data.read() )6537 { 6538 if (r_write_to_cleanup_req.read() and r_write_to_cleanup_nline.read() == r_cleanup_nline.read())6325 if (not r_cleanup_contains_data.read() ) 6326 { 6327 if (r_write_to_cleanup_req.read() and r_write_to_cleanup_nline.read() == r_cleanup_nline.read()) 6539 6328 //update the line with the data saved in write_to_cleanup_data table if the cleanup without data 6540 6329 { … … 6556 6345 } 6557 6346 6558 if ((r_cleanup_locked_pktid.read() & 0x7) != TYPE_SC)6347 if ((r_cleanup_locked_pktid.read() & 0x7) != TYPE_SC) 6559 6348 { 6560 6349 // addr_t min = r_cleanup_nline.read()*m_words*4 ; … … 6564 6353 } 6565 6354 6566 if (r_cleanup_locked_is_updt.read() and not r_cleanup_locked_is_changed.read()) //cleanup req cross with multi ack rsp. here, just decrements the count and remains the state.6355 if (r_cleanup_locked_is_updt.read() and not r_cleanup_locked_is_changed.read()) //cleanup req cross with multi ack rsp. here, just decrements the count and remains the state. 6567 6356 { 6568 6357 assert(r_cleanup_count.read() == 1 && " only one copy when cleanup fsm receives a req for is_updt command"); … … 6573 6362 r_cleanup_fsm = CLEANUP_SEND_CLACK; 6574 6363 } 6575 else if (r_cleanup_locked_is_updt.read() and r_cleanup_locked_is_changed.read())6364 else if (r_cleanup_locked_is_updt.read() and r_cleanup_locked_is_changed.read()) 6576 6365 { 6577 6366 entry.state = ENTRY_SHARED; 6578 if (match_ll)6367 if (match_ll) 6579 6368 { 6580 6369 entry.count = 0; … … 6587 6376 } 6588 6377 6589 if ((r_cleanup_locked_pktid.read() & 0x7) == TYPE_READ_INS_MISS)6378 if ((r_cleanup_locked_pktid.read() & 0x7) == TYPE_READ_INS_MISS) 6590 6379 { 6591 6380 entry.owner.inst = true; … … 6601 6390 else // cas, getm, one copy updated in dir 6602 6391 { 6603 if (r_cleanup_locked_is_read.read())6392 if (r_cleanup_locked_is_read.read()) 6604 6393 { 6605 6394 entry.state = ENTRY_EXCLUSIVE; … … 6638 6427 case CLEANUP_LOCKED_RSP: 6639 6428 { 6640 if (r_cleanup_to_tgt_rsp_req.read()) break;6429 if (r_cleanup_to_tgt_rsp_req.read()) break; 6641 6430 6642 6431 r_cleanup_to_tgt_rsp_req = true; … … 6645 6434 r_cleanup_to_tgt_rsp_nline = r_cleanup_nline.read(); 6646 6435 6647 if (r_cleanup_locked_is_changed.read() and r_cleanup_locked_is_updt.read())6436 if (r_cleanup_locked_is_changed.read() and r_cleanup_locked_is_updt.read()) 6648 6437 { 6649 6438 r_cleanup_to_tgt_rsp_pktid = r_cleanup_locked_pktid.read(); // rsp for is_updt in shared state … … 6655 6444 } 6656 6445 6657 if (r_read_to_multi_ack_req.read() and (r_read_to_multi_ack_nline.read() == r_cleanup_nline.read()) and // rsp for LL or pheriph6446 if (r_read_to_multi_ack_req.read() and (r_read_to_multi_ack_nline.read() == r_cleanup_nline.read()) and // rsp for LL or pheriph 6658 6447 (r_cleanup_locked_is_changed.read() and r_cleanup_locked_is_updt.read())) 6659 6448 { … … 6663 6452 r_read_to_multi_ack_req = false; 6664 6453 } 6665 else if (r_read_to_cleanup_req.read() and (r_read_to_cleanup_nline.read() == r_cleanup_nline.read())) // rsp for LL or pheriph6454 else if (r_read_to_cleanup_req.read() and (r_read_to_cleanup_nline.read() == r_cleanup_nline.read())) // rsp for LL or pheriph 6666 6455 { 6667 6456 r_cleanup_to_tgt_rsp_ll_key = r_read_to_cleanup_ll_key.read(); … … 6677 6466 } 6678 6467 6679 if (r_write_to_cleanup_req.read() and r_write_to_cleanup_nline.read() == r_cleanup_nline.read())6468 if (r_write_to_cleanup_req.read() and r_write_to_cleanup_nline.read() == r_cleanup_nline.read()) 6680 6469 r_write_to_cleanup_req = false; 6681 6470 … … 6708 6497 { 6709 6498 // get the lock to the HEAP directory 6710 m_cpt_cleanup_fsm_heap_lock ++; 6711 if(r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP) break; 6499 if (r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP) break; 6712 6500 6713 6501 r_cleanup_fsm = CLEANUP_HEAP_LOCK; 6714 6502 6715 6503 #if DEBUG_MEMC_CLEANUP 6716 if (m_debug)6504 if (m_debug) 6717 6505 { 6718 6506 std::cout … … 6722 6510 } 6723 6511 #endif 6724 m_cpt_cleanup_fsm_n_heap_lock++;6725 6512 break; 6726 6513 } … … 6773 6560 // it must be replaced by the first copy registered in 6774 6561 // the heap. The corresponding entry must be freed 6775 if (match_dir)6562 if (match_dir) 6776 6563 { 6777 6564 dir_entry.ptr = heap_entry.next; … … 6785 6572 // It must be freed and the copy registered in directory 6786 6573 // must point to the next copy in heap 6787 else if (match_heap)6574 else if (match_heap) 6788 6575 { 6789 6576 dir_entry.ptr = heap_entry.next; … … 6808 6595 6809 6596 #if DEBUG_MEMC_CLEANUP 6810 if (m_debug)6597 if (m_debug) 6811 6598 { 6812 6599 std::cout … … 6845 6632 6846 6633 // the matching copy must be removed 6847 if (match_heap)6634 if (match_heap) 6848 6635 { 6849 6636 // re-use ressources … … 6862 6649 6863 6650 #if DEBUG_MEMC_CLEANUP 6864 if (m_debug)6865 { 6866 if (not match_heap)6651 if (m_debug) 6652 { 6653 if (not match_heap) 6867 6654 { 6868 6655 std::cout … … 6903 6690 6904 6691 // this is the last entry of the list of copies 6905 if (last)6692 if (last) 6906 6693 { 6907 6694 heap_entry.next = r_cleanup_prev_ptr.read(); … … 6918 6705 6919 6706 #if DEBUG_MEMC_CLEANUP 6920 if (m_debug)6707 if (m_debug) 6921 6708 std::cout << " <MEMC " << name() << " CLEANUP_HEAP_SEARCH>" 6922 6709 << " Remove the copy in the linked list" << std::endl; … … 6934 6721 heap_entry.owner.inst = false; 6935 6722 6936 if (m_heap.is_full())6723 if (m_heap.is_full()) 6937 6724 { 6938 6725 heap_entry.next = r_cleanup_next_ptr.read(); … … 6950 6737 6951 6738 #if DEBUG_MEMC_CLEANUP 6952 if (m_debug)6739 if (m_debug) 6953 6740 std::cout << " <MEMC " << name() << " CLEANUP_HEAP_FREE>" 6954 6741 << " Update the list of free entries" << std::endl; … … 6960 6747 // invalidate transaction matching the cleanup 6961 6748 { 6962 m_cpt_cleanup_fsm_ivt_lock++; 6963 if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) break; 6749 if (r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) break; 6964 6750 6965 6751 size_t index = 0; 6966 6752 bool match_inval; 6967 6753 6968 m_cpt_cleanup_fsm_n_ivt_lock++;6969 6970 6754 match_inval = m_ivt.search_inval(r_cleanup_nline.read(), index); 6971 if ( 6755 if (not match_inval ) // no pending inval 6972 6756 { 6973 6757 r_cleanup_fsm = CLEANUP_SEND_CLACK; 6974 6758 6975 6759 #if DEBUG_MEMC_CLEANUP 6976 if (m_debug)6760 if (m_debug) 6977 6761 std::cout << " <MEMC " << name() 6978 6762 << " CLEANUP_MISS_IVT_LOCK> Unexpected cleanup" … … 6982 6766 << std::endl; 6983 6767 #endif 6984 m_cpt_cleanup_fsm_n_ivt_lock++;6985 6768 } 6986 6769 else … … 6995 6778 r_cleanup_fsm = CLEANUP_MISS_IVT_DECREMENT; 6996 6779 #if DEBUG_MEMC_CLEANUP 6997 if (m_debug)6780 if (m_debug) 6998 6781 std::cout << " <MEMC " << name() 6999 6782 << " CLEANUP_MISS_IVT_LOCK> Cleanup matching pending" … … 7015 6798 m_ivt.decrement(r_cleanup_miss_index.read(), count); 7016 6799 7017 if (count == 0) // multi inval transaction completed6800 if (count == 0) // multi inval transaction completed 7018 6801 { 7019 6802 r_cleanup_fsm = CLEANUP_MISS_IVT_CLEAR; … … 7025 6808 7026 6809 #if DEBUG_MEMC_CLEANUP 7027 if (m_debug)6810 if (m_debug) 7028 6811 std::cout << " <MEMC " << name() << " CLEANUP_MISS_IVT_DECREMENT>" 7029 6812 << " Decrement response counter in IVT:" … … 7041 6824 m_ivt.clear(r_cleanup_miss_index.read()); 7042 6825 7043 if ( 6826 if (r_cleanup_miss_need_ack.read() ) 7044 6827 { 7045 6828 assert( (r_config_rsp_lines.read() > 0) and … … 7054 6837 r_cleanup_fsm = CLEANUP_MISS_RSP; 7055 6838 } 7056 else if ( 6839 else if (r_cleanup_ncc.read() ) 7057 6840 { 7058 6841 r_cleanup_fsm = CLEANUP_MISS_IXR_REQ; … … 7064 6847 7065 6848 #if DEBUG_MEMC_CLEANUP 7066 if (m_debug)6849 if (m_debug) 7067 6850 std::cout << " <MEMC " << name() 7068 6851 << " CLEANUP_MISS_IVT_CLEAR> Clear entry in IVT:" … … 7075 6858 // wait if pending request to the TGT_RSP FSM 7076 6859 { 7077 if (r_cleanup_to_tgt_rsp_req.read()) break;6860 if (r_cleanup_to_tgt_rsp_req.read()) break; 7078 6861 7079 6862 // no pending request … … 7084 6867 r_cleanup_to_tgt_rsp_type = true; 7085 6868 7086 if ( 6869 if (r_cleanup_ncc.read() ) 7087 6870 { 7088 6871 r_cleanup_fsm = CLEANUP_MISS_IXR_REQ; … … 7094 6877 7095 6878 #if DEBUG_MEMC_CLEANUP 7096 if (m_debug)6879 if (m_debug) 7097 6880 std::cout << " <MEMC " << name() << " CLEANUP_MISS_RSP>" 7098 6881 << " Send a response to a previous write request: " … … 7109 6892 if (r_alloc_trt_fsm.read() == ALLOC_TRT_CLEANUP) 7110 6893 { 7111 if (not r_cleanup_to_ixr_cmd_req.read())6894 if (not r_cleanup_to_ixr_cmd_req.read()) 7112 6895 { 7113 6896 size_t index = 0; … … 7147 6930 r_cleanup_fsm = CLEANUP_SEND_CLACK; 7148 6931 #if DEBUG_MEMC_CLEANUP 7149 if (m_debug)6932 if (m_debug) 7150 6933 { 7151 6934 std::cout … … 7161 6944 r_cleanup_fsm = CLEANUP_WAIT; 7162 6945 #if DEBUG_MEMC_CLEANUP 7163 if (m_debug)6946 if (m_debug) 7164 6947 { 7165 6948 std::cout … … 7186 6969 // on the coherence CLACK network. 7187 6970 { 7188 if (not p_dspin_clack.read) break;6971 if (not p_dspin_clack.read) break; 7189 6972 7190 6973 r_cleanup_fsm = CLEANUP_IDLE; 7191 6974 7192 6975 #if DEBUG_MEMC_CLEANUP 7193 if (m_debug)6976 if (m_debug) 7194 6977 std::cout << " <MEMC " << name() 7195 6978 << " CLEANUP_SEND_CLACK> Send the response to a cleanup request:" … … 7233 7016 case CAS_IDLE: // fill the local rdata buffers 7234 7017 { 7235 if (m_cmd_cas_addr_fifo.rok())7018 if (m_cmd_cas_addr_fifo.rok()) 7236 7019 { 7237 7020 7238 7021 #if DEBUG_MEMC_CAS 7239 if (m_debug)7022 if (m_debug) 7240 7023 { 7241 7024 std::cout << " <MEMC " << name() << " CAS_IDLE> CAS command: " << std::hex … … 7247 7030 } 7248 7031 #endif 7249 if (m_cmd_cas_eop_fifo.read())7032 if (m_cmd_cas_eop_fifo.read()) 7250 7033 { 7251 7034 r_cas_fsm = CAS_DIR_REQ; … … 7256 7039 } 7257 7040 // We fill the two buffers 7258 if (r_cas_cpt.read() < 2) // 32 bits access7041 if (r_cas_cpt.read() < 2) // 32 bits access 7259 7042 r_cas_rdata[r_cas_cpt.read()] = m_cmd_cas_wdata_fifo.read(); 7260 7043 7261 if ((r_cas_cpt.read() == 1) and m_cmd_cas_eop_fifo.read())7044 if ((r_cas_cpt.read() == 1) and m_cmd_cas_eop_fifo.read()) 7262 7045 r_cas_wdata = m_cmd_cas_wdata_fifo.read(); 7263 7046 … … 7265 7048 "MEMC ERROR in CAS_IDLE state: illegal CAS command"); 7266 7049 7267 if (r_cas_cpt.read() ==2)7050 if (r_cas_cpt.read() ==2) 7268 7051 r_cas_wdata = m_cmd_cas_wdata_fifo.read(); 7269 7052 … … 7276 7059 case CAS_DIR_REQ: 7277 7060 { 7278 if (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS)7061 if (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) 7279 7062 { 7280 7063 r_cas_fsm = CAS_DIR_LOCK; 7281 m_cpt_cas_fsm_n_dir_lock++;7282 7064 } 7283 7065 7284 7066 #if DEBUG_MEMC_CAS 7285 if (m_debug)7067 if (m_debug) 7286 7068 { 7287 7069 std::cout … … 7290 7072 } 7291 7073 #endif 7292 7293 m_cpt_cas_fsm_dir_lock++;7294 7295 7074 break; 7296 7075 } … … 7315 7094 r_cas_count = entry.count; 7316 7095 7317 if (entry.state == ENTRY_LOCKED)7096 if (entry.state == ENTRY_LOCKED) 7318 7097 { 7319 7098 r_cas_fsm = CAS_WAIT; 7320 m_cpt_cas_locked_rb ++; 7321 } 7322 else if(entry.state == ENTRY_INVALID) 7099 } 7100 else if (entry.state == ENTRY_INVALID) 7323 7101 { 7324 7102 r_cas_fsm = CAS_MISS_TRT_LOCK; … … 7329 7107 } 7330 7108 #if DEBUG_MEMC_CAS 7331 if (m_debug)7109 if (m_debug) 7332 7110 { 7333 7111 std::cout << " <MEMC " << name() << " CAS_DIR_LOCK> Directory acces" … … 7367 7145 7368 7146 #if DEBUG_MEMC_CAS 7369 if (m_debug)7147 if (m_debug) 7370 7148 std::cout << " <MEMC " << name() << " CAS_DIR_HIT_READ> Read data from " 7371 7149 << " cache and store it in buffer" << std::endl; … … 7381 7159 bool ok = (r_cas_rdata[0].read() == r_cas_data[word].read()); 7382 7160 7383 if (r_cas_cpt.read() == 4) // 64 bits CAS7161 if (r_cas_cpt.read() == 4) // 64 bits CAS 7384 7162 ok &= (r_cas_rdata[1] == r_cas_data[word+1]); 7385 7163 … … 7389 7167 7390 7168 // cas success 7391 if (ok and not forced_fail)7169 if (ok and not forced_fail) 7392 7170 { 7393 7171 r_cas_fsm = CAS_DIR_HIT_WRITE; … … 7400 7178 7401 7179 #if DEBUG_MEMC_CAS 7402 if (m_debug)7180 if (m_debug) 7403 7181 std::cout << " <MEMC " << name() << " CAS_DIR_HIT_COMPARE> Compare the old" 7404 7182 << " and the new data" … … 7420 7198 7421 7199 // test coherence request 7422 if (r_cas_count.read()) // replicated line7423 { 7424 if (r_cas_count.read() == 1 and r_cas_state.read() == ENTRY_SHARED and r_cas_copy.read() == m_cmd_cas_srcid_fifo.read())7200 if (r_cas_count.read()) // replicated line 7201 { 7202 if (r_cas_count.read() == 1 and r_cas_state.read() == ENTRY_SHARED and r_cas_copy.read() == m_cmd_cas_srcid_fifo.read()) 7425 7203 { 7426 7204 DirectoryEntry entry; … … 7442 7220 // cache update 7443 7221 m_cache_data.write(way, set, word, r_cas_wdata.read()); 7444 if (r_cas_cpt.read() == 4)7222 if (r_cas_cpt.read() == 4) 7445 7223 m_cache_data.write(way, set, word+1, m_cmd_cas_wdata_fifo.read()); 7446 7224 … … 7452 7230 r_cas_fsm = CAS_INVAL_IVT_LOCK; // multi invalidate required 7453 7231 #if DEBUG_MEMC_CAS 7454 if (m_debug)7232 if (m_debug) 7455 7233 std::cout << " <MEMC " << name() << " CAS_DIR_HIT_WRITE>" 7456 7234 << " Multi Inval required" … … 7467 7245 // cache update 7468 7246 m_cache_data.write(way, set, word, r_cas_wdata.read()); 7469 if (r_cas_cpt.read() == 4)7247 if (r_cas_cpt.read() == 4) 7470 7248 m_cache_data.write(way, set, word+1, m_cmd_cas_wdata_fifo.read()); 7471 7249 … … 7473 7251 7474 7252 #if DEBUG_MEMC_CAS 7475 if (m_debug)7253 if (m_debug) 7476 7254 std::cout << " <MEMC " << name() << " CAS_DIR_HIT_WRITE> Update cache:" 7477 7255 << " way = " << std::dec << way … … 7490 7268 // releases locks to retry later if ivt full 7491 7269 { 7492 if (r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS and7270 if (r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS and 7493 7271 not r_cas_to_cc_send_multi_req.read() and 7494 7272 not r_cas_to_cc_send_brdcast_req.read() and … … 7513 7291 false, // is a command write 7514 7292 index); 7515 if (wok) // coherence transaction registered in ivt7293 if (wok) // coherence transaction registered in ivt 7516 7294 { 7517 7295 // cache update … … 7538 7316 m_cache_data.write(way, set, word, r_cas_wdata.read()); 7539 7317 7540 if (r_cas_cpt.read() == 4)7318 if (r_cas_cpt.read() == 4) 7541 7319 m_cache_data.write(way, set, word+1, m_cmd_cas_wdata_fifo.read()); 7542 7320 7543 if(r_cas_is_cnt.read())7544 m_cpt_cas_broadcast ++;7545 else7546 m_cpt_cas_minval ++;7547 7548 7321 //r_cas_ivt_index = index; 7549 if ((r_cas_count.read() != 1) and not r_cas_is_cnt.read())7322 if ((r_cas_count.read() != 1) and not r_cas_is_cnt.read()) 7550 7323 { 7551 7324 r_cas_fsm = CAS_MULTI_INVAL_HEAP_LOCK; … … 7555 7328 assert(not r_cas_copy_inst.read() && "cas fsm: cas has a copy inst"); 7556 7329 7557 if (not r_cas_is_cnt.read())7330 if (not r_cas_is_cnt.read()) 7558 7331 { 7559 7332 cas_to_cc_send_fifo_put = true; … … 7574 7347 } 7575 7348 #if DEBUG_MEMC_CAS 7576 if (m_debug)7349 if (m_debug) 7577 7350 std::cout << " <MEMC " << name() 7578 7351 << " CAS_INVAL_IVT_LOCK> Line is locked" … … 7597 7370 7598 7371 #if DEBUG_MEMC_CAS 7599 if (m_debug)7372 if (m_debug) 7600 7373 { 7601 7374 std::cout << " <MEMC " << name() … … 7609 7382 case CAS_MULTI_INVAL_HEAP_LOCK: // lock the heap 7610 7383 { 7611 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS)7384 if (r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS) 7612 7385 { 7613 7386 7614 7387 #if DEBUG_MEMC_CAS 7615 if (m_debug)7388 if (m_debug) 7616 7389 { 7617 7390 std::cout << " <MEMC " << name() … … 7620 7393 #endif 7621 7394 r_cas_fsm = CAS_MULTI_INVAL_REQ; 7622 m_cpt_cas_fsm_n_heap_lock++; 7623 } 7624 7625 m_cpt_cas_fsm_heap_lock++; 7626 7395 } 7627 7396 break; 7628 7397 } … … 7635 7404 assert(not r_cas_copy_inst.read() && "cas fsm: cas has a copy inst"); 7636 7405 7637 if (not r_cas_to_cc_send_multi_req.read() and not r_cas_to_cc_send_brdcast_req.read())7406 if (not r_cas_to_cc_send_multi_req.read() and not r_cas_to_cc_send_brdcast_req.read()) 7638 7407 { 7639 7408 r_cas_next_ptr = r_cas_ptr.read(); … … 7644 7413 cas_to_cc_send_fifo_srcid = r_cas_copy.read(); 7645 7414 // We put the first copy in the fifo 7646 if (r_cas_count.read() == 1) // one single copy7415 if (r_cas_count.read() == 1) // one single copy 7647 7416 { 7648 7417 assert( false && "it should be more than one copies in cas_multi_inval_req!!!!"); … … 7654 7423 7655 7424 #if DEBUG_MEMC_CAS 7656 if (m_debug)7425 if (m_debug) 7657 7426 { 7658 7427 std::cout << " <MEMC " << name() << " CAS_MULTI_INVAL_REQ> Send the first update request to CC_SEND FSM " … … 7680 7449 assert(not entry.owner.inst && "cas fsm: cas has a copy inst"); 7681 7450 7682 if (m_cas_to_cc_send_inst_fifo.wok()) // request accepted by CC_SEND FSM7451 if (m_cas_to_cc_send_inst_fifo.wok()) // request accepted by CC_SEND FSM 7683 7452 { 7684 7453 cas_to_cc_send_fifo_srcid = entry.owner.srcid; … … 7686 7455 cas_to_cc_send_fifo_put = true; 7687 7456 r_cas_next_ptr = entry.next; 7688 if (entry.next == r_cas_next_ptr.read()) // last copy7457 if (entry.next == r_cas_next_ptr.read()) // last copy 7689 7458 { 7690 7459 r_cas_to_cc_send_multi_req = true; … … 7693 7462 } 7694 7463 #if DEBUG_MEMC_CAS 7695 if (m_debug)7464 if (m_debug) 7696 7465 { 7697 7466 std::cout << " <MEMC " << name() << " CAS_HEAP_NEXT> Send the next update request to CC_SEND FSM " … … 7707 7476 case CAS_HEAP_LAST: // last copy 7708 7477 { 7709 if (r_alloc_heap_fsm.read() != ALLOC_HEAP_CAS)7478 if (r_alloc_heap_fsm.read() != ALLOC_HEAP_CAS) 7710 7479 { 7711 7480 std::cout << "VCI_MEM_CACHE ERROR " << name() << " CAS_HEAP_LAST" … … 7718 7487 last_entry.owner.srcid = 0; 7719 7488 last_entry.owner.inst = false; 7720 if (m_heap.is_full())7489 if (m_heap.is_full()) 7721 7490 { 7722 7491 last_entry.next = r_cas_next_ptr.read(); … … 7736 7505 7737 7506 #if DEBUG_MEMC_XRAM_RSP 7738 if (m_debug)7507 if (m_debug) 7739 7508 std::cout << " <MEMC " << name() << " CAS_HEAP_LAST>" 7740 7509 << " Heap housekeeping" << std::endl; … … 7745 7514 case CAS_RSP_FAIL: // request TGT_RSP FSM to send a failure response 7746 7515 { 7747 if (not r_cas_to_tgt_rsp_req.read() )7516 if (not r_cas_to_tgt_rsp_req.read() ) 7748 7517 { 7749 7518 cmd_cas_fifo_get = true; … … 7757 7526 7758 7527 #if DEBUG_MEMC_CAS 7759 if (m_debug)7528 if (m_debug) 7760 7529 std::cout << " <MEMC " << name() 7761 7530 << " CAS_RSP_FAIL> Request TGT_RSP to send a failure response" << std::endl; … … 7767 7536 case CAS_RSP_SUCCESS: // request TGT_RSP FSM to send a success response 7768 7537 { 7769 if (not r_cas_to_tgt_rsp_req.read() )7538 if (not r_cas_to_tgt_rsp_req.read() ) 7770 7539 { 7771 7540 cmd_cas_fifo_get = true; … … 7779 7548 7780 7549 #if DEBUG_MEMC_CAS 7781 if (m_debug)7550 if (m_debug) 7782 7551 std::cout << " <MEMC " << name() 7783 7552 << " CAS_RSP_SUCCESS> Request TGT_RSP to send a success response" << std::endl; … … 7789 7558 case CAS_MISS_TRT_LOCK: // cache miss : request access to transaction Table 7790 7559 { 7791 if (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS)7560 if (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) 7792 7561 { 7793 7562 size_t index = 0; … … 7799 7568 7800 7569 #if DEBUG_MEMC_CAS 7801 if (m_debug)7570 if (m_debug) 7802 7571 { 7803 7572 std::cout << " <MEMC " << name() << " CAS_MISS_TRT_LOCK> Check TRT state" … … 7809 7578 #endif 7810 7579 7811 if (hit_read or !wok or hit_write) // missing line already requested or no space in TRT7580 if (hit_read or !wok or hit_write) // missing line already requested or no space in TRT 7812 7581 { 7813 7582 r_cas_fsm = CAS_WAIT; … … 7817 7586 r_cas_trt_index = index; 7818 7587 r_cas_fsm = CAS_MISS_TRT_SET; 7819 m_cpt_cas_miss ++; 7820 } 7821 m_cpt_cas_fsm_n_trt_lock++; 7822 } 7823 7824 m_cpt_cas_fsm_trt_lock++; 7825 7588 } 7589 } 7826 7590 break; 7827 7591 } … … 7856 7620 7857 7621 #if DEBUG_MEMC_CAS 7858 if (m_debug)7622 if (m_debug) 7859 7623 { 7860 7624 std::cout << " <MEMC " << name() << " CAS_MISS_TRT_SET> Register a GET transaction in TRT" << std::hex … … 7868 7632 case CAS_MISS_XRAM_REQ: // request the IXR_CMD FSM to fetch the missing line 7869 7633 { 7870 if (not r_cas_to_ixr_cmd_req.read() )7634 if (not r_cas_to_ixr_cmd_req.read() ) 7871 7635 { 7872 7636 r_cas_to_ixr_cmd_req = true; … … 7875 7639 7876 7640 #if DEBUG_MEMC_CAS 7877 if (m_debug)7641 if (m_debug) 7878 7642 std::cout << " <MEMC " << name() << " CAS_MISS_XRAM_REQ> Request a GET transaction" 7879 7643 << " / address = " << std::hex << (addr_t) m_cmd_cas_addr_fifo.read() … … 7923 7687 m_read_to_cc_send_srcid_fifo.read() == r_cleanup_to_tgt_rsp_srcid.read(); 7924 7688 // XRAM_RSP 7925 if (m_xram_rsp_to_cc_send_inst_fifo.rok() or7689 if (m_xram_rsp_to_cc_send_inst_fifo.rok() or 7926 7690 r_xram_rsp_to_cc_send_multi_req.read()) 7927 7691 { … … 7929 7693 break; 7930 7694 } 7931 if (r_xram_rsp_to_cc_send_brdcast_req.read())7695 if (r_xram_rsp_to_cc_send_brdcast_req.read()) 7932 7696 { 7933 7697 r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER; … … 7935 7699 } 7936 7700 // CAS 7937 if (m_cas_to_cc_send_inst_fifo.rok() or7701 if (m_cas_to_cc_send_inst_fifo.rok() or 7938 7702 r_cas_to_cc_send_multi_req.read()) 7939 7703 { … … 7941 7705 break; 7942 7706 } 7943 if (r_cas_to_cc_send_brdcast_req.read())7707 if (r_cas_to_cc_send_brdcast_req.read()) 7944 7708 { 7945 7709 r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER; … … 7948 7712 7949 7713 // READ 7950 if ((m_read_to_cc_send_inst_fifo.rok() or7714 if ((m_read_to_cc_send_inst_fifo.rok() or 7951 7715 r_read_to_cc_send_multi_req.read()) and not cc_send_updt_delay) 7952 7716 { … … 7954 7718 break; 7955 7719 } 7956 if (r_read_to_cc_send_brdcast_req.read())7720 if (r_read_to_cc_send_brdcast_req.read()) 7957 7721 { 7958 7722 r_cc_send_fsm = CC_SEND_READ_BRDCAST_HEADER; … … 7961 7725 7962 7726 // WRITE 7963 if (m_write_to_cc_send_inst_fifo.rok() or7727 if (m_write_to_cc_send_inst_fifo.rok() or 7964 7728 r_write_to_cc_send_multi_req.read()) 7965 7729 { … … 7967 7731 break; 7968 7732 } 7969 if (r_write_to_cc_send_brdcast_req.read())7733 if (r_write_to_cc_send_brdcast_req.read()) 7970 7734 { 7971 7735 r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER; … … 7973 7737 } 7974 7738 // CONFIG 7975 if (r_config_to_cc_send_multi_req.read())7739 if (r_config_to_cc_send_multi_req.read()) 7976 7740 { 7977 7741 r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; 7978 7742 break; 7979 7743 } 7980 if (r_config_to_cc_send_brdcast_req.read())7744 if (r_config_to_cc_send_brdcast_req.read()) 7981 7745 { 7982 7746 r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; … … 7992 7756 m_read_to_cc_send_srcid_fifo.read() == r_cleanup_to_tgt_rsp_srcid.read(); 7993 7757 // CONFIG 7994 if (r_config_to_cc_send_multi_req.read())7758 if (r_config_to_cc_send_multi_req.read()) 7995 7759 { 7996 7760 r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; 7997 7761 break; 7998 7762 } 7999 if (r_config_to_cc_send_brdcast_req.read())7763 if (r_config_to_cc_send_brdcast_req.read()) 8000 7764 { 8001 7765 r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; … … 8003 7767 } 8004 7768 // XRAM_RSP 8005 if (m_xram_rsp_to_cc_send_inst_fifo.rok() or7769 if (m_xram_rsp_to_cc_send_inst_fifo.rok() or 8006 7770 r_xram_rsp_to_cc_send_multi_req.read()) 8007 7771 { … … 8009 7773 break; 8010 7774 } 8011 if (r_xram_rsp_to_cc_send_brdcast_req.read())7775 if (r_xram_rsp_to_cc_send_brdcast_req.read()) 8012 7776 { 8013 7777 r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER; … … 8015 7779 } 8016 7780 // CAS 8017 if (m_cas_to_cc_send_inst_fifo.rok() or7781 if (m_cas_to_cc_send_inst_fifo.rok() or 8018 7782 r_cas_to_cc_send_multi_req.read()) 8019 7783 { … … 8021 7785 break; 8022 7786 } 8023 if (r_cas_to_cc_send_brdcast_req.read())7787 if (r_cas_to_cc_send_brdcast_req.read()) 8024 7788 { 8025 7789 r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER; … … 8027 7791 } 8028 7792 // READ 8029 if ((m_read_to_cc_send_inst_fifo.rok() or7793 if ((m_read_to_cc_send_inst_fifo.rok() or 8030 7794 r_read_to_cc_send_multi_req.read()) and not cc_send_updt_delay) 8031 7795 { … … 8033 7797 break; 8034 7798 } 8035 if (r_read_to_cc_send_brdcast_req.read())7799 if (r_read_to_cc_send_brdcast_req.read()) 8036 7800 { 8037 7801 r_cc_send_fsm = CC_SEND_READ_BRDCAST_HEADER; … … 8039 7803 } 8040 7804 // WRITE 8041 if (m_write_to_cc_send_inst_fifo.rok() or7805 if (m_write_to_cc_send_inst_fifo.rok() or 8042 7806 r_write_to_cc_send_multi_req.read()) 8043 7807 { … … 8045 7809 break; 8046 7810 } 8047 if (r_write_to_cc_send_brdcast_req.read())7811 if (r_write_to_cc_send_brdcast_req.read()) 8048 7812 { 8049 7813 r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER; … … 8059 7823 m_read_to_cc_send_srcid_fifo.read() == r_cleanup_to_tgt_rsp_srcid.read(); 8060 7824 // CAS 8061 if (m_cas_to_cc_send_inst_fifo.rok() or7825 if (m_cas_to_cc_send_inst_fifo.rok() or 8062 7826 r_cas_to_cc_send_multi_req.read()) 8063 7827 { … … 8065 7829 break; 8066 7830 } 8067 if (r_cas_to_cc_send_brdcast_req.read())7831 if (r_cas_to_cc_send_brdcast_req.read()) 8068 7832 { 8069 7833 r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER; … … 8071 7835 } 8072 7836 // READ 8073 if ((m_read_to_cc_send_inst_fifo.rok() or7837 if ((m_read_to_cc_send_inst_fifo.rok() or 8074 7838 r_read_to_cc_send_multi_req.read()) and not cc_send_updt_delay) 8075 7839 { … … 8077 7841 break; 8078 7842 } 8079 if (r_read_to_cc_send_brdcast_req.read())7843 if (r_read_to_cc_send_brdcast_req.read()) 8080 7844 { 8081 7845 r_cc_send_fsm = CC_SEND_READ_BRDCAST_HEADER; … … 8083 7847 } 8084 7848 //WRITE 8085 if (m_write_to_cc_send_inst_fifo.rok() or7849 if (m_write_to_cc_send_inst_fifo.rok() or 8086 7850 r_write_to_cc_send_multi_req.read()) 8087 7851 { … … 8089 7853 break; 8090 7854 } 8091 if (r_write_to_cc_send_brdcast_req.read())7855 if (r_write_to_cc_send_brdcast_req.read()) 8092 7856 { 8093 7857 r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER; … … 8095 7859 } 8096 7860 // CONFIG 8097 if (r_config_to_cc_send_multi_req.read())7861 if (r_config_to_cc_send_multi_req.read()) 8098 7862 { 8099 7863 r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; 8100 7864 break; 8101 7865 } 8102 if (r_config_to_cc_send_brdcast_req.read())7866 if (r_config_to_cc_send_brdcast_req.read()) 8103 7867 { 8104 7868 r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; … … 8106 7870 } 8107 7871 // XRAM_RSP 8108 if (m_xram_rsp_to_cc_send_inst_fifo.rok() or7872 if (m_xram_rsp_to_cc_send_inst_fifo.rok() or 8109 7873 r_xram_rsp_to_cc_send_multi_req.read()) 8110 7874 { … … 8112 7876 break; 8113 7877 } 8114 if (r_xram_rsp_to_cc_send_brdcast_req.read())7878 if (r_xram_rsp_to_cc_send_brdcast_req.read()) 8115 7879 { 8116 7880 r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER; … … 8126 7890 m_read_to_cc_send_srcid_fifo.read() == r_cleanup_to_tgt_rsp_srcid.read(); 8127 7891 // READ 8128 if ((m_read_to_cc_send_inst_fifo.rok() or7892 if ((m_read_to_cc_send_inst_fifo.rok() or 8129 7893 r_read_to_cc_send_multi_req.read()) and not cc_send_updt_delay) 8130 7894 { … … 8132 7896 break; 8133 7897 } 8134 if (r_read_to_cc_send_brdcast_req.read())7898 if (r_read_to_cc_send_brdcast_req.read()) 8135 7899 { 8136 7900 r_cc_send_fsm = CC_SEND_READ_BRDCAST_HEADER; … … 8138 7902 } 8139 7903 //WRITE 8140 if (m_write_to_cc_send_inst_fifo.rok() or7904 if (m_write_to_cc_send_inst_fifo.rok() or 8141 7905 r_write_to_cc_send_multi_req.read()) 8142 7906 { … … 8144 7908 break; 8145 7909 } 8146 if (r_write_to_cc_send_brdcast_req.read())7910 if (r_write_to_cc_send_brdcast_req.read()) 8147 7911 { 8148 7912 r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER; … … 8150 7914 } 8151 7915 // CONFIG 8152 if (r_config_to_cc_send_multi_req.read())7916 if (r_config_to_cc_send_multi_req.read()) 8153 7917 { 8154 7918 r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; 8155 7919 break; 8156 7920 } 8157 if (r_config_to_cc_send_brdcast_req.read())7921 if (r_config_to_cc_send_brdcast_req.read()) 8158 7922 { 8159 7923 r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; … … 8161 7925 } 8162 7926 //xram 8163 if (m_xram_rsp_to_cc_send_inst_fifo.rok() or7927 if (m_xram_rsp_to_cc_send_inst_fifo.rok() or 8164 7928 r_xram_rsp_to_cc_send_multi_req.read()) 8165 7929 { … … 8167 7931 break; 8168 7932 } 8169 if (r_xram_rsp_to_cc_send_brdcast_req.read())7933 if (r_xram_rsp_to_cc_send_brdcast_req.read()) 8170 7934 { 8171 7935 r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER; … … 8173 7937 } 8174 7938 //cas 8175 if (m_cas_to_cc_send_inst_fifo.rok() or7939 if (m_cas_to_cc_send_inst_fifo.rok() or 8176 7940 r_cas_to_cc_send_multi_req.read()) 8177 7941 { … … 8179 7943 break; 8180 7944 } 8181 if (r_cas_to_cc_send_brdcast_req.read())7945 if (r_cas_to_cc_send_brdcast_req.read()) 8182 7946 { 8183 7947 r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER; … … 8193 7957 m_read_to_cc_send_srcid_fifo.read() == r_cleanup_to_tgt_rsp_srcid.read(); 8194 7958 //WRITE 8195 if (m_write_to_cc_send_inst_fifo.rok() or7959 if (m_write_to_cc_send_inst_fifo.rok() or 8196 7960 r_write_to_cc_send_multi_req.read()) 8197 7961 { … … 8199 7963 break; 8200 7964 } 8201 if (r_write_to_cc_send_brdcast_req.read())7965 if (r_write_to_cc_send_brdcast_req.read()) 8202 7966 { 8203 7967 r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER; … … 8205 7969 } 8206 7970 // CONFIG 8207 if (r_config_to_cc_send_multi_req.read())7971 if (r_config_to_cc_send_multi_req.read()) 8208 7972 { 8209 7973 r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; 8210 7974 break; 8211 7975 } 8212 if (r_config_to_cc_send_brdcast_req.read())7976 if (r_config_to_cc_send_brdcast_req.read()) 8213 7977 { 8214 7978 r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; … … 8216 7980 } 8217 7981 //xram 8218 if (m_xram_rsp_to_cc_send_inst_fifo.rok() or7982 if (m_xram_rsp_to_cc_send_inst_fifo.rok() or 8219 7983 r_xram_rsp_to_cc_send_multi_req.read()) 8220 7984 { … … 8222 7986 break; 8223 7987 } 8224 if (r_xram_rsp_to_cc_send_brdcast_req.read())7988 if (r_xram_rsp_to_cc_send_brdcast_req.read()) 8225 7989 { 8226 7990 r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER; … … 8228 7992 } 8229 7993 //cas 8230 if (m_cas_to_cc_send_inst_fifo.rok() or7994 if (m_cas_to_cc_send_inst_fifo.rok() or 8231 7995 r_cas_to_cc_send_multi_req.read()) 8232 7996 { … … 8234 7998 break; 8235 7999 } 8236 if (r_cas_to_cc_send_brdcast_req.read())8000 if (r_cas_to_cc_send_brdcast_req.read()) 8237 8001 { 8238 8002 r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER; … … 8240 8004 } 8241 8005 // READ 8242 if ((m_read_to_cc_send_inst_fifo.rok() or8006 if ((m_read_to_cc_send_inst_fifo.rok() or 8243 8007 r_read_to_cc_send_multi_req.read()) and not cc_send_updt_delay) 8244 8008 { … … 8246 8010 break; 8247 8011 } 8248 if (r_read_to_cc_send_brdcast_req.read())8012 if (r_read_to_cc_send_brdcast_req.read()) 8249 8013 { 8250 8014 r_cc_send_fsm = CC_SEND_READ_BRDCAST_HEADER; … … 8257 8021 case CC_SEND_CONFIG_INVAL_HEADER: // send first flit multi-inval (from CONFIG FSM) 8258 8022 { 8259 if(m_config_to_cc_send_inst_fifo.rok()) 8260 { 8261 if(not p_dspin_m2p.read) break; 8023 if (m_config_to_cc_send_inst_fifo.rok()) 8024 { 8025 if (not p_dspin_m2p.read) break; 8026 8262 8027 // <Activity Counters> 8263 8028 if (is_local_req(m_config_to_cc_send_srcid_fifo.read())) … … 8268 8033 { 8269 8034 m_cpt_minval_remote++; 8270 m_cpt_minval_cost += req_distance(m_config_to_cc_send_srcid_fifo.read()); 8271 } 8272 // </Activity Counters> 8273 m_cpt_minval++; 8035 } 8036 // 2 flits for multi inval 8037 m_cpt_minval_cost += 2 * req_distance(m_config_to_cc_send_srcid_fifo.read()); 8274 8038 // </Activity Counters> 8275 8039 r_cc_send_fsm = CC_SEND_CONFIG_INVAL_NLINE; 8276 8040 break; 8277 8041 } 8278 if(r_config_to_cc_send_multi_req.read()) r_config_to_cc_send_multi_req = false; 8042 if (r_config_to_cc_send_multi_req.read()) r_config_to_cc_send_multi_req = false; 8043 // <Activity Counters> 8044 m_cpt_minval++; 8045 // </Activity Counters> 8279 8046 r_cc_send_fsm = CC_SEND_CONFIG_IDLE; 8280 8047 break; … … 8283 8050 case CC_SEND_CONFIG_INVAL_NLINE: // send second flit multi-inval (from CONFIG FSM) 8284 8051 { 8285 if (not p_dspin_m2p.read) break;8052 if (not p_dspin_m2p.read) break; 8286 8053 config_to_cc_send_fifo_get = true; 8287 8054 r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; 8288 8055 8289 8056 #if DEBUG_MEMC_CC_SEND 8290 if (m_debug)8057 if (m_debug) 8291 8058 std::cout << " <MEMC " << name() 8292 8059 << " CC_SEND_CONFIG_INVAL_NLINE> multi-inval for line " … … 8298 8065 case CC_SEND_CONFIG_BRDCAST_HEADER: // send first flit BC-inval (from CONFIG FSM) 8299 8066 { 8300 if (not p_dspin_m2p.read) break;8067 if (not p_dspin_m2p.read) break; 8301 8068 r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_NLINE; 8302 8069 break; … … 8305 8072 case CC_SEND_CONFIG_BRDCAST_NLINE: // send second flit BC-inval (from CONFIG FSM) 8306 8073 { 8307 if (not p_dspin_m2p.read) break;8074 if (not p_dspin_m2p.read) break; 8308 8075 // <Activity Counters> 8309 8076 m_cpt_binval++; … … 8313 8080 8314 8081 #if DEBUG_MEMC_CC_SEND 8315 if (m_debug)8082 if (m_debug) 8316 8083 std::cout << " <MEMC " << name() 8317 8084 << " CC_SEND_CONFIG_BRDCAST_NLINE> BC-Inval for line " … … 8320 8087 break; 8321 8088 } 8322 /////////////////////////////////// 8323 case CC_SEND_XRAM_RSP_INVAL_HEADER: // send first flit multi-inval (from XRAM_RSP FSM) 8324 { 8325 if(m_xram_rsp_to_cc_send_inst_fifo.rok()) 8326 { 8327 if(not p_dspin_m2p.read) break; 8089 /////////////////////////////////// 8090 case CC_SEND_XRAM_RSP_INVAL_HEADER: 8091 // send first flit multi-inval (from XRAM_RSP FSM) 8092 { 8093 if (m_xram_rsp_to_cc_send_inst_fifo.rok()) 8094 { 8095 if (not p_dspin_m2p.read) break; 8328 8096 // <Activity Counters> 8329 8097 if (is_local_req(m_xram_rsp_to_cc_send_srcid_fifo.read())) … … 8334 8102 { 8335 8103 m_cpt_minval_remote++; 8336 m_cpt_minval_cost += req_distance(m_xram_rsp_to_cc_send_srcid_fifo.read()); 8337 } 8338 // </Activity Counters> 8339 m_cpt_minval++; 8104 } 8105 // 2 flits for multi inval 8106 m_cpt_minval_cost += 2 * req_distance(m_xram_rsp_to_cc_send_srcid_fifo.read()); 8340 8107 // </Activity Counters> 8341 8108 r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_NLINE; 8342 8109 break; 8343 8110 } 8344 if(r_xram_rsp_to_cc_send_multi_req.read()) r_xram_rsp_to_cc_send_multi_req = false; 8345 8111 if (r_xram_rsp_to_cc_send_multi_req.read()) r_xram_rsp_to_cc_send_multi_req = false; 8112 8113 // <Activity Counters> 8114 m_cpt_minval++; 8115 // </Activity Counters> 8346 8116 r_cc_send_fsm = CC_SEND_XRAM_RSP_IDLE; 8347 8117 break; … … 8350 8120 case CC_SEND_XRAM_RSP_INVAL_NLINE: // send second flit multi-inval (from XRAM_RSP FSM) 8351 8121 { 8352 if (not p_dspin_m2p.read) break;8122 if (not p_dspin_m2p.read) break; 8353 8123 xram_rsp_to_cc_send_fifo_get = true; 8354 8124 r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER; 8355 8125 8356 8126 #if DEBUG_MEMC_CC_SEND 8357 if (m_debug)8127 if (m_debug) 8358 8128 std::cout << " <MEMC " << name() 8359 8129 << " CC_SEND_XRAM_RSP_INVAL_NLINE> Multicast-Inval for line " … … 8365 8135 case CC_SEND_XRAM_RSP_BRDCAST_HEADER: // send first flit broadcast-inval (from XRAM_RSP FSM) 8366 8136 { 8367 if (not p_dspin_m2p.read) break;8137 if (not p_dspin_m2p.read) break; 8368 8138 r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_NLINE; 8369 8139 break; … … 8372 8142 case CC_SEND_XRAM_RSP_BRDCAST_NLINE: // send second flit broadcast-inval (from XRAM_RSP FSM) 8373 8143 { 8374 if (not p_dspin_m2p.read) break;8144 if (not p_dspin_m2p.read) break; 8375 8145 // <Activity Counters> 8376 8146 m_cpt_binval++; … … 8380 8150 8381 8151 #if DEBUG_MEMC_CC_SEND 8382 if (m_debug)8152 if (m_debug) 8383 8153 std::cout << " <MEMC " << name() 8384 8154 << " CC_SEND_XRAM_RSP_BRDCAST_NLINE> BC-Inval for line " … … 8390 8160 case CC_SEND_READ_BRDCAST_HEADER: 8391 8161 { 8392 if (not p_dspin_m2p.read) break;8162 if (not p_dspin_m2p.read) break; 8393 8163 // <Activity Counters> 8394 8164 m_cpt_binval++; … … 8399 8169 case CC_SEND_READ_BRDCAST_NLINE: 8400 8170 { 8401 if (not p_dspin_m2p.read) break;8171 if (not p_dspin_m2p.read) break; 8402 8172 r_read_to_cc_send_brdcast_req = false; 8403 8173 r_cc_send_fsm = CC_SEND_READ_IDLE; … … 8406 8176 case CC_SEND_READ_MULTI_HEADER: 8407 8177 { 8408 if(m_read_to_cc_send_inst_fifo.rok()) 8409 { 8410 if(not p_dspin_m2p.read) break; 8178 if (m_read_to_cc_send_inst_fifo.rok()) 8179 { 8180 if (not p_dspin_m2p.read) break; 8181 8411 8182 // <Activity Counters> 8412 if (is_local_req(m_read_to_cc_send_srcid_fifo.read())) 8413 { 8414 if(r_read_to_cc_send_type.read()) 8415 m_cpt_minval_local ++; 8416 else 8417 m_cpt_update_local ++; 8418 } 8419 else 8420 { 8421 if(r_read_to_cc_send_type.read()) 8183 if (r_read_to_cc_send_type.read()) { 8184 // Can be either an inval RO or a multi inval; 8185 // Counting only multi inval here 8186 if (is_local_req(m_read_to_cc_send_srcid_fifo.read())) 8422 8187 { 8423 m_cpt_minval_remote++; 8424 m_cpt_minval_cost += req_distance(m_read_to_cc_send_srcid_fifo.read()); 8188 m_cpt_minval_local++; 8425 8189 } 8426 8190 else 8427 8191 { 8428 m_cpt_update_remote++; 8429 m_cpt_update_cost += req_distance(m_read_to_cc_send_srcid_fifo.read()); 8192 m_cpt_minval_remote++; 8430 8193 } 8431 } 8432 // </Activity Counters> 8433 if(r_read_to_cc_send_type.read()) 8434 m_cpt_minval++; 8194 // 2 flits for multi inval 8195 m_cpt_minval_cost += 2 * req_distance(m_read_to_cc_send_srcid_fifo.read()); 8196 } 8435 8197 // </Activity Counters> 8436 8198 r_cc_send_fsm = CC_SEND_READ_MULTI_NLINE; … … 8438 8200 } 8439 8201 8440 if (r_read_to_cc_send_multi_req.read())8202 if (r_read_to_cc_send_multi_req.read()) 8441 8203 { 8442 8204 r_read_to_cc_send_multi_req = false; 8443 8205 } 8444 8206 8207 // <Activity Counters> 8208 m_cpt_minval++; 8209 // </Activity Counters> 8445 8210 r_cc_send_fsm = CC_SEND_READ_IDLE; 8446 8211 break; … … 8449 8214 case CC_SEND_READ_MULTI_NLINE: 8450 8215 { 8451 if (not p_dspin_m2p.read) break;8216 if (not p_dspin_m2p.read) break; 8452 8217 8453 8218 read_to_cc_send_fifo_get = true; … … 8455 8220 8456 8221 #if DEBUG_MEMC_CC_SEND 8457 if (m_debug)8222 if (m_debug) 8458 8223 { 8459 8224 std::cout … … 8469 8234 case CC_SEND_WRITE_BRDCAST_HEADER: // send first flit broadcast-inval (from WRITE FSM) 8470 8235 { 8471 if (not p_dspin_m2p.read) break;8236 if (not p_dspin_m2p.read) break; 8472 8237 r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_NLINE; 8473 8238 break; … … 8476 8241 case CC_SEND_WRITE_BRDCAST_NLINE: // send second flit broadcast-inval (from WRITE FSM) 8477 8242 { 8478 if (not p_dspin_m2p.read) break;8243 if (not p_dspin_m2p.read) break; 8479 8244 8480 8245 // <Activity Counters> … … 8486 8251 8487 8252 #if DEBUG_MEMC_CC_SEND 8488 if (m_debug)8253 if (m_debug) 8489 8254 std::cout << " <MEMC " << name() 8490 8255 << " CC_SEND_WRITE_BRDCAST_NLINE> BC-Inval for line " … … 8496 8261 case CC_SEND_WRITE_INVAL_HEADER: // send first flit for a multi-inval (from WRITE FSM) 8497 8262 { 8498 if (m_write_to_cc_send_inst_fifo.rok())8499 { 8500 if (not p_dspin_m2p.read) break;8263 if (m_write_to_cc_send_inst_fifo.rok()) 8264 { 8265 if (not p_dspin_m2p.read) break; 8501 8266 // <Activity Counters> 8502 8267 if (is_local_req(m_write_to_cc_send_srcid_fifo.read())) … … 8507 8272 { 8508 8273 m_cpt_minval_remote++; 8509 m_cpt_minval_cost += req_distance(m_write_to_cc_send_srcid_fifo.read()); 8510 } 8511 // </Activity Counters> 8512 m_cpt_minval++; 8274 } 8275 // 2 flits for multi inval 8276 m_cpt_minval_cost += 2 * req_distance(m_write_to_cc_send_srcid_fifo.read()); 8513 8277 // </Activity Counters> 8514 8278 r_cc_send_fsm = CC_SEND_WRITE_INVAL_NLINE; … … 8516 8280 } 8517 8281 8518 if (r_write_to_cc_send_multi_req.read())8282 if (r_write_to_cc_send_multi_req.read()) 8519 8283 { 8520 8284 r_write_to_cc_send_multi_req = false; 8521 8285 } 8522 8286 8287 // <Activity Counters> 8288 m_cpt_minval++; 8289 // </Activity Counters> 8523 8290 r_cc_send_fsm = CC_SEND_WRITE_IDLE; 8524 8291 break; … … 8527 8294 case CC_SEND_WRITE_INVAL_NLINE: // send second flit for a multi-update (from WRITE FSM) 8528 8295 { 8529 if (not p_dspin_m2p.read) break;8296 if (not p_dspin_m2p.read) break; 8530 8297 write_to_cc_send_fifo_get = true; 8531 8298 r_cc_send_fsm = CC_SEND_WRITE_INVAL_HEADER; 8532 8299 8533 8300 #if DEBUG_MEMC_CC_SEND 8534 if (m_debug)8301 if (m_debug) 8535 8302 std::cout << " <MEMC " << name() 8536 8303 << " CC_SEND_WRITE_INVAL_NLINE> Multicast-Inval for line " … … 8542 8309 case CC_SEND_CAS_BRDCAST_HEADER: // send first flit broadcast-inval (from CAS FSM) 8543 8310 { 8544 if (not p_dspin_m2p.read) break;8311 if (not p_dspin_m2p.read) break; 8545 8312 r_cc_send_fsm = CC_SEND_CAS_BRDCAST_NLINE; 8546 8313 break; … … 8549 8316 case CC_SEND_CAS_BRDCAST_NLINE: // send second flit broadcast-inval (from CAS FSM) 8550 8317 { 8551 if (not p_dspin_m2p.read) break;8318 if (not p_dspin_m2p.read) break; 8552 8319 // <Activity Counters> 8553 8320 m_cpt_binval++; … … 8558 8325 8559 8326 #if DEBUG_MEMC_CC_SEND 8560 if (m_debug)8327 if (m_debug) 8561 8328 std::cout << " <MEMC " << name() 8562 8329 << " CC_SEND_CAS_BRDCAST_NLINE> Broadcast-Inval for line " … … 8568 8335 case CC_SEND_CAS_INVAL_HEADER: // send first flit for a multi-update (from CAS FSM) 8569 8336 { 8570 if (m_cas_to_cc_send_inst_fifo.rok())8571 { 8572 if (not p_dspin_m2p.read) break;8337 if (m_cas_to_cc_send_inst_fifo.rok()) 8338 { 8339 if (not p_dspin_m2p.read) break; 8573 8340 // <Activity Counters> 8574 8341 if (is_local_req(m_cas_to_cc_send_srcid_fifo.read())) … … 8579 8346 { 8580 8347 m_cpt_minval_remote++; 8581 m_cpt_minval_cost += req_distance(m_cas_to_cc_send_srcid_fifo.read()); 8582 } 8583 // <Activity Counters> 8584 m_cpt_minval++; 8348 } 8349 // 2 flits for multi inval 8350 m_cpt_minval_cost += 2 * req_distance(m_cas_to_cc_send_srcid_fifo.read()); 8585 8351 // </Activity Counters> 8586 8352 r_cc_send_fsm = CC_SEND_CAS_INVAL_NLINE; … … 8589 8355 8590 8356 // no more packets to send for the multi-update 8591 if (r_cas_to_cc_send_multi_req.read())8357 if (r_cas_to_cc_send_multi_req.read()) 8592 8358 { 8593 8359 r_cas_to_cc_send_multi_req = false; 8594 8360 } 8595 8361 8362 // <Activity Counters> 8363 m_cpt_minval++; 8364 // </Activity Counters> 8596 8365 r_cc_send_fsm = CC_SEND_CAS_IDLE; 8597 8366 break; … … 8600 8369 case CC_SEND_CAS_INVAL_NLINE: // send second flit for a multi-update (from CAS FSM) 8601 8370 { 8602 if (not p_dspin_m2p.read) break;8371 if (not p_dspin_m2p.read) break; 8603 8372 cas_to_cc_send_fifo_get = true; 8604 8373 r_cc_send_fsm = CC_SEND_CAS_INVAL_HEADER; 8605 8374 8606 8375 #if DEBUG_MEMC_CC_SEND 8607 if (m_debug)8376 if (m_debug) 8608 8377 std::cout << " <MEMC " << name() 8609 8378 << " CC_SEND_CAS_INVAL_NLINE> Multicast-Inval for line " … … 8627 8396 case CC_RECEIVE_IDLE: 8628 8397 { 8629 if (not p_dspin_p2m.write) break;8398 if (not p_dspin_p2m.write) break; 8630 8399 8631 8400 uint8_t type = 8632 Dspin DhccpParam::dspin_get(8401 DspinHmesiParam::dspin_get( 8633 8402 p_dspin_p2m.data.read(), 8634 Dspin DhccpParam::P2M_TYPE);8635 8636 if ((type == DspinDhccpParam::TYPE_CLEANUP_DATA) or8637 (type == Dspin DhccpParam::TYPE_CLEANUP_INST))8403 DspinHmesiParam::P2M_TYPE); 8404 8405 if ((type == DspinHmesiParam::TYPE_CLEANUP_DATA) or 8406 (type == DspinHmesiParam::TYPE_CLEANUP_INST)) 8638 8407 { 8639 8408 r_cc_receive_fsm = CC_RECEIVE_CLEANUP; … … 8641 8410 } 8642 8411 8643 if (type == DspinDhccpParam::TYPE_MULTI_ACK)8412 if (type == DspinHmesiParam::TYPE_MULTI_ACK) 8644 8413 { 8645 8414 r_cc_receive_fsm = CC_RECEIVE_MULTI_ACK; … … 8658 8427 // write first CLEANUP flit in CC_RECEIVE to CLEANUP fifo 8659 8428 8660 if (not p_dspin_p2m.write or not m_cc_receive_to_cleanup_fifo.wok())8429 if (not p_dspin_p2m.write or not m_cc_receive_to_cleanup_fifo.wok()) 8661 8430 break; 8662 8431 8663 8432 cc_receive_to_cleanup_fifo_put = true; 8664 if (p_dspin_p2m.eop.read())8433 if (p_dspin_p2m.eop.read()) 8665 8434 r_cc_receive_fsm = CC_RECEIVE_IDLE; 8666 8435 … … 8672 8441 // write second CLEANUP flit in CC_RECEIVE to CLEANUP fifo 8673 8442 8674 if (not p_dspin_p2m.write or not m_cc_receive_to_cleanup_fifo.wok())8443 if (not p_dspin_p2m.write or not m_cc_receive_to_cleanup_fifo.wok()) 8675 8444 break; 8676 8445 … … 8680 8449 8681 8450 cc_receive_to_cleanup_fifo_put = true; 8682 if (p_dspin_p2m.eop.read())8451 if (p_dspin_p2m.eop.read()) 8683 8452 r_cc_receive_fsm = CC_RECEIVE_IDLE; 8684 8453 break; … … 8691 8460 8692 8461 // wait for a WOK in the CC_RECEIVE to MULTI_ACK fifo 8693 if (not p_dspin_p2m.write or not m_cc_receive_to_multi_ack_fifo.wok())8462 if (not p_dspin_p2m.write or not m_cc_receive_to_multi_ack_fifo.wok()) 8694 8463 break; 8695 8464 8696 if (p_dspin_p2m.eop.read())8465 if (p_dspin_p2m.eop.read()) 8697 8466 r_cc_receive_fsm = CC_RECEIVE_IDLE; 8698 8467 … … 8724 8493 case TGT_RSP_CONFIG_IDLE: // tgt_cmd requests have the highest priority 8725 8494 { 8726 if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;8727 else if (r_read_to_tgt_rsp_req)8495 if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; 8496 else if (r_read_to_tgt_rsp_req) 8728 8497 { 8729 8498 r_tgt_rsp_fsm = TGT_RSP_READ; 8730 8499 r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); 8731 8500 } 8732 else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE;8733 else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS;8734 else if (r_xram_rsp_to_tgt_rsp_req)8501 else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; 8502 else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; 8503 else if (r_xram_rsp_to_tgt_rsp_req) 8735 8504 { 8736 8505 r_tgt_rsp_fsm = TGT_RSP_XRAM; 8737 8506 r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); 8738 8507 } 8739 else if (r_multi_ack_to_tgt_rsp_req)8508 else if (r_multi_ack_to_tgt_rsp_req) 8740 8509 { 8741 8510 r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; 8742 8511 r_tgt_rsp_cpt = r_multi_ack_to_tgt_rsp_word.read(); 8743 8512 } 8744 else if (r_cleanup_to_tgt_rsp_req)8513 else if (r_cleanup_to_tgt_rsp_req) 8745 8514 { 8746 8515 r_tgt_rsp_fsm = TGT_RSP_CLEANUP; 8747 8516 r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read(); 8748 8517 } 8749 else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG;8518 else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; 8750 8519 break; 8751 8520 } … … 8753 8522 case TGT_RSP_TGT_CMD_IDLE: // read requests have the highest priority 8754 8523 { 8755 if (r_read_to_tgt_rsp_req)8524 if (r_read_to_tgt_rsp_req) 8756 8525 { 8757 8526 r_tgt_rsp_fsm = TGT_RSP_READ; 8758 8527 r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); 8759 8528 } 8760 else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE;8761 else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS;8762 else if (r_xram_rsp_to_tgt_rsp_req)8529 else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; 8530 else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; 8531 else if (r_xram_rsp_to_tgt_rsp_req) 8763 8532 { 8764 8533 r_tgt_rsp_fsm = TGT_RSP_XRAM; 8765 8534 r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); 8766 8535 } 8767 else if (r_multi_ack_to_tgt_rsp_req)8536 else if (r_multi_ack_to_tgt_rsp_req) 8768 8537 { 8769 8538 r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; 8770 8539 r_tgt_rsp_cpt = r_multi_ack_to_tgt_rsp_word.read(); 8771 8540 } 8772 else if (r_cleanup_to_tgt_rsp_req)8541 else if (r_cleanup_to_tgt_rsp_req) 8773 8542 { 8774 8543 r_tgt_rsp_fsm = TGT_RSP_CLEANUP; 8775 8544 r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read(); 8776 8545 } 8777 else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG;8778 else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;8546 else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; 8547 else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; 8779 8548 break; 8780 8549 } … … 8782 8551 case TGT_RSP_READ_IDLE: // write requests have the highest priority 8783 8552 { 8784 if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE;8785 else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS;8786 else if (r_xram_rsp_to_tgt_rsp_req)8553 if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; 8554 else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; 8555 else if (r_xram_rsp_to_tgt_rsp_req) 8787 8556 { 8788 8557 r_tgt_rsp_fsm = TGT_RSP_XRAM; 8789 8558 r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); 8790 8559 } 8791 else if (r_multi_ack_to_tgt_rsp_req)8560 else if (r_multi_ack_to_tgt_rsp_req) 8792 8561 { 8793 8562 r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; 8794 8563 r_tgt_rsp_cpt = r_multi_ack_to_tgt_rsp_word.read(); 8795 8564 } 8796 else if (r_cleanup_to_tgt_rsp_req)8565 else if (r_cleanup_to_tgt_rsp_req) 8797 8566 { 8798 8567 r_tgt_rsp_fsm = TGT_RSP_CLEANUP; 8799 8568 r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read(); 8800 8569 } 8801 else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG;8802 else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;8803 else if (r_read_to_tgt_rsp_req)8570 else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; 8571 else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; 8572 else if (r_read_to_tgt_rsp_req) 8804 8573 { 8805 8574 r_tgt_rsp_fsm = TGT_RSP_READ; … … 8811 8580 case TGT_RSP_WRITE_IDLE: // cas requests have the highest priority 8812 8581 { 8813 if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS;8814 else if (r_xram_rsp_to_tgt_rsp_req)8582 if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; 8583 else if (r_xram_rsp_to_tgt_rsp_req) 8815 8584 { 8816 8585 r_tgt_rsp_fsm = TGT_RSP_XRAM; 8817 8586 r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); 8818 8587 } 8819 else if (r_multi_ack_to_tgt_rsp_req)8588 else if (r_multi_ack_to_tgt_rsp_req) 8820 8589 { 8821 8590 r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; 8822 8591 r_tgt_rsp_cpt = r_multi_ack_to_tgt_rsp_word.read(); 8823 8592 } 8824 else if (r_cleanup_to_tgt_rsp_req)8593 else if (r_cleanup_to_tgt_rsp_req) 8825 8594 { 8826 8595 r_tgt_rsp_fsm = TGT_RSP_CLEANUP; 8827 8596 r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read(); 8828 8597 } 8829 else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG;8830 else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;8831 else if (r_read_to_tgt_rsp_req)8598 else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; 8599 else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; 8600 else if (r_read_to_tgt_rsp_req) 8832 8601 { 8833 8602 r_tgt_rsp_fsm = TGT_RSP_READ; 8834 8603 r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); 8835 8604 } 8836 else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE;8605 else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; 8837 8606 break; 8838 8607 } … … 8840 8609 case TGT_RSP_CAS_IDLE: // xram_rsp requests have the highest priority 8841 8610 { 8842 if (r_xram_rsp_to_tgt_rsp_req)8611 if (r_xram_rsp_to_tgt_rsp_req) 8843 8612 { 8844 8613 r_tgt_rsp_fsm = TGT_RSP_XRAM; 8845 8614 r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); 8846 8615 } 8847 else if (r_multi_ack_to_tgt_rsp_req)8616 else if (r_multi_ack_to_tgt_rsp_req) 8848 8617 { 8849 8618 r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; 8850 8619 r_tgt_rsp_cpt = r_multi_ack_to_tgt_rsp_word.read(); 8851 8620 } 8852 else if (r_cleanup_to_tgt_rsp_req)8621 else if (r_cleanup_to_tgt_rsp_req) 8853 8622 { 8854 8623 r_tgt_rsp_fsm = TGT_RSP_CLEANUP; 8855 8624 r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read(); 8856 8625 } 8857 else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG;8858 else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;8859 else if (r_read_to_tgt_rsp_req)8626 else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; 8627 else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; 8628 else if (r_read_to_tgt_rsp_req) 8860 8629 { 8861 8630 r_tgt_rsp_fsm = TGT_RSP_READ; 8862 8631 r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); 8863 8632 } 8864 else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE;8865 else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ;8633 else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; 8634 else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; 8866 8635 break; 8867 8636 } … … 8869 8638 case TGT_RSP_XRAM_IDLE: // multi ack requests have the highest priority 8870 8639 { 8871 if (r_multi_ack_to_tgt_rsp_req.read())8640 if (r_multi_ack_to_tgt_rsp_req.read()) 8872 8641 { 8873 8642 r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; 8874 8643 r_tgt_rsp_cpt = r_multi_ack_to_tgt_rsp_word.read(); 8875 8644 } 8876 else if (r_cleanup_to_tgt_rsp_req)8645 else if (r_cleanup_to_tgt_rsp_req) 8877 8646 { 8878 8647 r_tgt_rsp_fsm = TGT_RSP_CLEANUP; 8879 8648 r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read(); 8880 8649 } 8881 else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG;8882 else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;8883 else if (r_read_to_tgt_rsp_req)8650 else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; 8651 else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; 8652 else if (r_read_to_tgt_rsp_req) 8884 8653 { 8885 8654 r_tgt_rsp_fsm = TGT_RSP_READ; 8886 8655 r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); 8887 8656 } 8888 else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE;8889 else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ;8890 else if (r_xram_rsp_to_tgt_rsp_req)8657 else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; 8658 else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; 8659 else if (r_xram_rsp_to_tgt_rsp_req) 8891 8660 { 8892 8661 r_tgt_rsp_fsm = TGT_RSP_XRAM; … … 8898 8667 case TGT_RSP_MULTI_ACK_IDLE: // cleanup requests have the highest priority 8899 8668 { 8900 if (r_cleanup_to_tgt_rsp_req)8669 if (r_cleanup_to_tgt_rsp_req) 8901 8670 { 8902 8671 r_tgt_rsp_fsm = TGT_RSP_CLEANUP; 8903 8672 r_tgt_rsp_cpt = r_cleanup_to_tgt_rsp_first_word.read(); 8904 8673 } 8905 else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG;8906 else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;8907 else if (r_read_to_tgt_rsp_req)8674 else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; 8675 else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; 8676 else if (r_read_to_tgt_rsp_req) 8908 8677 { 8909 8678 r_tgt_rsp_fsm = TGT_RSP_READ; 8910 8679 r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); 8911 8680 } 8912 else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE;8913 else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ;8914 else if (r_xram_rsp_to_tgt_rsp_req)8681 else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; 8682 else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; 8683 else if (r_xram_rsp_to_tgt_rsp_req) 8915 8684 { 8916 8685 r_tgt_rsp_fsm = TGT_RSP_XRAM; 8917 8686 r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); 8918 8687 } 8919 else if (r_multi_ack_to_tgt_rsp_req)8688 else if (r_multi_ack_to_tgt_rsp_req) 8920 8689 { 8921 8690 r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; … … 8927 8696 case TGT_RSP_CLEANUP_IDLE: // tgt cmd requests have the highest priority 8928 8697 { 8929 if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG;8930 else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD;8931 else if (r_read_to_tgt_rsp_req)8698 if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; 8699 else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; 8700 else if (r_read_to_tgt_rsp_req) 8932 8701 { 8933 8702 r_tgt_rsp_fsm = TGT_RSP_READ; 8934 8703 r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); 8935 8704 } 8936 else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE;8937 else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ;8938 else if (r_xram_rsp_to_tgt_rsp_req)8705 else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; 8706 else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; 8707 else if (r_xram_rsp_to_tgt_rsp_req) 8939 8708 { 8940 8709 r_tgt_rsp_fsm = TGT_RSP_XRAM; 8941 8710 r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); 8942 8711 } 8943 else if (r_multi_ack_to_tgt_rsp_req)8712 else if (r_multi_ack_to_tgt_rsp_req) 8944 8713 { 8945 8714 r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; 8946 8715 r_tgt_rsp_cpt = r_multi_ack_to_tgt_rsp_word.read(); 8947 8716 } 8948 else if (r_cleanup_to_tgt_rsp_req)8717 else if (r_cleanup_to_tgt_rsp_req) 8949 8718 { 8950 8719 r_tgt_rsp_fsm = TGT_RSP_CLEANUP; … … 8956 8725 case TGT_RSP_CONFIG: // send the response for a config transaction 8957 8726 { 8958 if ( 8727 if (p_vci_tgt.rspack ) 8959 8728 { 8960 8729 r_config_to_tgt_rsp_req = false; … … 8962 8731 8963 8732 #if DEBUG_MEMC_TGT_RSP 8964 if (m_debug )8733 if (m_debug ) 8965 8734 { 8966 8735 std::cout … … 8979 8748 case TGT_RSP_TGT_CMD: // send the response for a configuration access 8980 8749 { 8981 if ( 8750 if (p_vci_tgt.rspack ) 8982 8751 { 8983 8752 r_tgt_cmd_to_tgt_rsp_req = false; … … 8985 8754 8986 8755 #if DEBUG_MEMC_TGT_RSP 8987 if (m_debug )8756 if (m_debug ) 8988 8757 { 8989 8758 std::cout … … 9003 8772 case TGT_RSP_READ: // send the response to a read 9004 8773 { 9005 if ( 8774 if (p_vci_tgt.rspack ) 9006 8775 { 9007 8776 9008 8777 #if DEBUG_MEMC_TGT_RSP 9009 if (m_debug )8778 if (m_debug ) 9010 8779 { 9011 8780 std::cout … … 9050 8819 case TGT_RSP_WRITE: // send the write acknowledge 9051 8820 { 9052 if (p_vci_tgt.rspack)8821 if (p_vci_tgt.rspack) 9053 8822 { 9054 8823 9055 8824 #if DEBUG_MEMC_TGT_RSP 9056 if (m_debug)8825 if (m_debug) 9057 8826 std::cout << " <MEMC " << name() << " TGT_RSP_WRITE> Write response" 9058 8827 << " / rsrcid = " << std::hex << r_write_to_tgt_rsp_srcid.read() … … 9068 8837 case TGT_RSP_CLEANUP: // pas clair pour moi (AG) 9069 8838 { 9070 if (p_vci_tgt.rspack)8839 if (p_vci_tgt.rspack) 9071 8840 { 9072 8841 uint32_t last_word_idx = r_cleanup_to_tgt_rsp_first_word.read() + r_cleanup_to_tgt_rsp_length.read() - 1; 9073 8842 bool is_ll = ((r_cleanup_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL); 9074 8843 #if DEBUG_MEMC_TGT_RSP 9075 if (m_debug)8844 if (m_debug) 9076 8845 { 9077 8846 std::cout << " <MEMC " << name() << " TGT_RSP_CLEANUP> Cleanup response" … … 9111 8880 case TGT_RSP_CAS: // send one atomic word response 9112 8881 { 9113 if (p_vci_tgt.rspack)8882 if (p_vci_tgt.rspack) 9114 8883 { 9115 8884 9116 8885 #if DEBUG_MEMC_TGT_RSP 9117 if (m_debug)8886 if (m_debug) 9118 8887 std::cout << " <MEMC " << name() << " TGT_RSP_CAS> CAS response" 9119 8888 << " / rsrcid = " << std::hex << r_cas_to_tgt_rsp_srcid.read() … … 9129 8898 case TGT_RSP_XRAM: // send the response after XRAM access 9130 8899 { 9131 if ( 8900 if (p_vci_tgt.rspack ) 9132 8901 { 9133 8902 9134 8903 #if DEBUG_MEMC_TGT_RSP 9135 if (m_debug )8904 if (m_debug ) 9136 8905 std::cout << " <MEMC " << name() << " TGT_RSP_XRAM> Response following XRAM access" 9137 8906 << " / rsrcid = " << std::hex << r_xram_rsp_to_tgt_rsp_srcid.read() … … 9172 8941 case TGT_RSP_MULTI_ACK: // send the read /LL response after coherence transaction 9173 8942 { 9174 if (p_vci_tgt.rspack)8943 if (p_vci_tgt.rspack) 9175 8944 { 9176 8945 … … 9182 8951 9183 8952 #if DEBUG_MEMC_TGT_RSP 9184 if (m_debug)8953 if (m_debug) 9185 8954 std::cout << " <MEMC " << name() << " TGT_RSP_MULTI_ACK> Write response after coherence transaction" 9186 8955 << " / rsrcid = " << std::hex << r_multi_ack_to_tgt_rsp_srcid.read() … … 9235 9004 if (r_write_fsm.read() != WRITE_INVAL_IVT_LOCK) 9236 9005 { 9237 if ((r_read_fsm.read() == READ_IVT_INVAL_LOCK) or9006 if ((r_read_fsm.read() == READ_IVT_INVAL_LOCK) or 9238 9007 (r_read_fsm.read() == READ_IVT_UPDT_LOCK)) 9239 9008 r_alloc_ivt_fsm = ALLOC_IVT_READ; … … 9255 9024 r_alloc_ivt_fsm = ALLOC_IVT_MULTI_ACK; 9256 9025 9257 else9258 m_cpt_ivt_unused++;9259 9026 } 9260 9027 break; … … 9262 9029 ////////////////////////// 9263 9030 case ALLOC_IVT_READ: // allocated to READ FSM 9264 if ((r_read_fsm.read() != READ_IVT_INVAL_LOCK) and9031 if ((r_read_fsm.read() != READ_IVT_INVAL_LOCK) and 9265 9032 (r_read_fsm.read() != READ_IVT_UPDT_LOCK)) 9266 9033 { … … 9284 9051 r_alloc_ivt_fsm = ALLOC_IVT_WRITE; 9285 9052 9286 else9287 m_cpt_ivt_unused++;9288 9053 } 9289 9054 break; … … 9291 9056 ////////////////////////// 9292 9057 case ALLOC_IVT_XRAM_RSP: // allocated to XRAM_RSP FSM 9293 if (r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK)9058 if (r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK) 9294 9059 { 9295 9060 if ((r_cleanup_fsm.read() == CLEANUP_MISS_IVT_LOCK) or … … 9309 9074 r_alloc_ivt_fsm = ALLOC_IVT_WRITE; 9310 9075 9311 else if ((r_read_fsm.read() == READ_IVT_INVAL_LOCK) or9076 else if ((r_read_fsm.read() == READ_IVT_INVAL_LOCK) or 9312 9077 (r_read_fsm.read() == READ_IVT_UPDT_LOCK)) 9313 9078 r_alloc_ivt_fsm = ALLOC_IVT_READ; 9314 9079 9315 else9316 m_cpt_ivt_unused++;9317 9080 } 9318 9081 break; … … 9337 9100 r_alloc_ivt_fsm = ALLOC_IVT_WRITE; 9338 9101 9339 else if ((r_read_fsm.read() == READ_IVT_INVAL_LOCK) or9102 else if ((r_read_fsm.read() == READ_IVT_INVAL_LOCK) or 9340 9103 (r_read_fsm.read() == READ_IVT_UPDT_LOCK)) 9341 9104 r_alloc_ivt_fsm = ALLOC_IVT_READ; … … 9343 9106 else if (r_xram_rsp_fsm.read() == XRAM_RSP_IVT_LOCK) 9344 9107 r_alloc_ivt_fsm = ALLOC_IVT_XRAM_RSP; 9345 9346 else9347 m_cpt_ivt_unused++;9348 9108 } 9349 9109 break; … … 9362 9122 r_alloc_ivt_fsm = ALLOC_IVT_WRITE; 9363 9123 9364 else if ((r_read_fsm.read() == READ_IVT_INVAL_LOCK) or9124 else if ((r_read_fsm.read() == READ_IVT_INVAL_LOCK) or 9365 9125 (r_read_fsm.read() == READ_IVT_UPDT_LOCK)) 9366 9126 r_alloc_ivt_fsm = ALLOC_IVT_READ; … … 9372 9132 (r_cleanup_fsm.read() == CLEANUP_LOCKED_IVT_LOCK)) 9373 9133 r_alloc_ivt_fsm = ALLOC_IVT_CLEANUP; 9374 9375 else9376 m_cpt_ivt_unused++;9377 9134 } 9378 9135 break; … … 9388 9145 r_alloc_ivt_fsm = ALLOC_IVT_WRITE; 9389 9146 9390 else if ((r_read_fsm.read() == READ_IVT_INVAL_LOCK) or9147 else if ((r_read_fsm.read() == READ_IVT_INVAL_LOCK) or 9391 9148 (r_read_fsm.read() == READ_IVT_UPDT_LOCK)) 9392 9149 r_alloc_ivt_fsm = ALLOC_IVT_READ; … … 9401 9158 else if (r_cas_fsm.read() == CAS_INVAL_IVT_LOCK) 9402 9159 r_alloc_ivt_fsm = ALLOC_IVT_CAS; 9403 9404 else9405 m_cpt_ivt_unused++;9406 9160 } 9407 9161 break; … … 9417 9171 r_alloc_ivt_fsm = ALLOC_IVT_WRITE; 9418 9172 9419 else if ((r_read_fsm.read() == READ_IVT_INVAL_LOCK) or9173 else if ((r_read_fsm.read() == READ_IVT_INVAL_LOCK) or 9420 9174 (r_read_fsm.read() == READ_IVT_UPDT_LOCK)) 9421 9175 r_alloc_ivt_fsm = ALLOC_IVT_READ; … … 9433 9187 else if (r_config_fsm.read() == CONFIG_IVT_LOCK) 9434 9188 r_alloc_ivt_fsm = ALLOC_IVT_CONFIG; 9435 9436 else9437 m_cpt_ivt_unused++;9438 9189 } 9439 9190 break; … … 9459 9210 r_alloc_dir_reset_cpt.write(r_alloc_dir_reset_cpt.read() + 1); 9460 9211 9461 if (r_alloc_dir_reset_cpt.read() == (m_sets - 1))9212 if (r_alloc_dir_reset_cpt.read() == (m_sets - 1)) 9462 9213 { 9463 9214 m_cache_directory.init(); … … 9468 9219 ////////////////////// 9469 9220 case ALLOC_DIR_CONFIG: // allocated to CONFIG FSM 9470 if ( 9221 if ((r_config_fsm.read() != CONFIG_DIR_REQ) and 9471 9222 (r_config_fsm.read() != CONFIG_DIR_ACCESS) and 9472 9223 (r_config_fsm.read() != CONFIG_TRT_LOCK) and … … 9474 9225 (r_config_fsm.read() != CONFIG_IVT_LOCK) ) 9475 9226 { 9476 if (r_read_fsm.read() == READ_DIR_REQ)9227 if (r_read_fsm.read() == READ_DIR_REQ) 9477 9228 r_alloc_dir_fsm = ALLOC_DIR_READ; 9478 9229 9479 else if (r_write_fsm.read() == WRITE_DIR_REQ)9230 else if (r_write_fsm.read() == WRITE_DIR_REQ) 9480 9231 r_alloc_dir_fsm = ALLOC_DIR_WRITE; 9481 9232 9482 else if (r_cas_fsm.read() == CAS_DIR_REQ)9233 else if (r_cas_fsm.read() == CAS_DIR_REQ) 9483 9234 r_alloc_dir_fsm = ALLOC_DIR_CAS; 9484 9235 9485 else if (r_multi_ack_fsm.read() == MULTI_ACK_DIR_REQ)9236 else if (r_multi_ack_fsm.read() == MULTI_ACK_DIR_REQ) 9486 9237 r_alloc_dir_fsm = ALLOC_DIR_MULTI_ACK; 9487 9238 9488 else if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ)9239 else if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ) 9489 9240 r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; 9490 9241 9491 else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)9242 else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) 9492 9243 r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; 9493 9494 else9495 m_cpt_dir_unused++;9496 9497 9244 } 9498 9245 break; … … 9500 9247 //////////////////// 9501 9248 case ALLOC_DIR_READ: // allocated to READ FSM 9502 if (((r_read_fsm.read() != READ_DIR_REQ) and9249 if (((r_read_fsm.read() != READ_DIR_REQ) and 9503 9250 (r_read_fsm.read() != READ_DIR_LOCK) and 9504 9251 (r_read_fsm.read() != READ_TRT_LOCK) and … … 9511 9258 (r_alloc_trt_fsm.read() == ALLOC_TRT_READ)) ) 9512 9259 { 9513 if (r_write_fsm.read() == WRITE_DIR_REQ)9260 if (r_write_fsm.read() == WRITE_DIR_REQ) 9514 9261 r_alloc_dir_fsm = ALLOC_DIR_WRITE; 9515 9262 9516 else if (r_cas_fsm.read() == CAS_DIR_REQ)9263 else if (r_cas_fsm.read() == CAS_DIR_REQ) 9517 9264 r_alloc_dir_fsm = ALLOC_DIR_CAS; 9518 9265 9519 else if (r_multi_ack_fsm.read() == MULTI_ACK_DIR_REQ)9266 else if (r_multi_ack_fsm.read() == MULTI_ACK_DIR_REQ) 9520 9267 r_alloc_dir_fsm = ALLOC_DIR_MULTI_ACK; 9521 9268 9522 else if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ)9269 else if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ) 9523 9270 r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; 9524 9271 9525 else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)9272 else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) 9526 9273 r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; 9527 9274 9528 else if (r_config_fsm.read() == CONFIG_DIR_REQ)9275 else if (r_config_fsm.read() == CONFIG_DIR_REQ) 9529 9276 r_alloc_dir_fsm = ALLOC_DIR_CONFIG; 9530 9531 else 9532 m_cpt_dir_unused++; 9533 } 9534 else 9535 m_cpt_read_fsm_dir_used++; 9277 } 9536 9278 break; 9537 9279 9538 9280 ///////////////////// 9539 9281 case ALLOC_DIR_WRITE: 9540 if (((r_write_fsm.read() != WRITE_DIR_REQ) and9282 if (((r_write_fsm.read() != WRITE_DIR_REQ) and 9541 9283 (r_write_fsm.read() != WRITE_DIR_LOCK) and 9542 9284 (r_write_fsm.read() != WRITE_DIR_HIT) and … … 9552 9294 (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE))) 9553 9295 { 9554 if (r_cas_fsm.read() == CAS_DIR_REQ)9296 if (r_cas_fsm.read() == CAS_DIR_REQ) 9555 9297 r_alloc_dir_fsm = ALLOC_DIR_CAS; 9556 9298 9557 else if (r_multi_ack_fsm.read() == MULTI_ACK_DIR_REQ)9299 else if (r_multi_ack_fsm.read() == MULTI_ACK_DIR_REQ) 9558 9300 r_alloc_dir_fsm = ALLOC_DIR_MULTI_ACK; 9559 9301 9560 else if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ)9302 else if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ) 9561 9303 r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; 9562 9304 9563 else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)9305 else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) 9564 9306 r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; 9565 9307 9566 else if (r_config_fsm.read() == CONFIG_DIR_REQ)9308 else if (r_config_fsm.read() == CONFIG_DIR_REQ) 9567 9309 r_alloc_dir_fsm = ALLOC_DIR_CONFIG; 9568 9310 9569 else if (r_read_fsm.read() == READ_DIR_REQ)9311 else if (r_read_fsm.read() == READ_DIR_REQ) 9570 9312 r_alloc_dir_fsm = ALLOC_DIR_READ; 9571 9572 else 9573 m_cpt_dir_unused++; 9574 } 9575 else 9576 m_cpt_write_fsm_dir_used++; 9313 } 9577 9314 break; 9578 9315 9579 9316 /////////////////// 9580 9317 case ALLOC_DIR_CAS: // allocated to CAS FSM 9581 if (((r_cas_fsm.read() != CAS_DIR_REQ) and9318 if (((r_cas_fsm.read() != CAS_DIR_REQ) and 9582 9319 (r_cas_fsm.read() != CAS_DIR_LOCK) and 9583 9320 (r_cas_fsm.read() != CAS_DIR_HIT_READ) and … … 9594 9331 (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS))) 9595 9332 { 9596 if (r_multi_ack_fsm.read() == MULTI_ACK_DIR_REQ)9333 if (r_multi_ack_fsm.read() == MULTI_ACK_DIR_REQ) 9597 9334 r_alloc_dir_fsm = ALLOC_DIR_MULTI_ACK; 9598 9335 9599 else if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ)9336 else if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ) 9600 9337 r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; 9601 9338 9602 else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)9339 else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) 9603 9340 r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; 9604 9341 9605 else if (r_config_fsm.read() == CONFIG_DIR_REQ)9342 else if (r_config_fsm.read() == CONFIG_DIR_REQ) 9606 9343 r_alloc_dir_fsm = ALLOC_DIR_CONFIG; 9607 9344 9608 else if (r_read_fsm.read() == READ_DIR_REQ)9345 else if (r_read_fsm.read() == READ_DIR_REQ) 9609 9346 r_alloc_dir_fsm = ALLOC_DIR_READ; 9610 9347 9611 else if (r_write_fsm.read() == WRITE_DIR_REQ)9348 else if (r_write_fsm.read() == WRITE_DIR_REQ) 9612 9349 r_alloc_dir_fsm = ALLOC_DIR_WRITE; 9613 9614 else 9615 m_cpt_dir_unused++; 9616 } 9617 else 9618 m_cpt_cas_fsm_dir_used++; 9350 } 9619 9351 break; 9620 9352 //////////////////////// 9621 9353 case ALLOC_DIR_MULTI_ACK: // allocated to MULTI_ACK FSM 9622 if (((r_multi_ack_fsm.read() != MULTI_ACK_DIR_REQ) and9354 if (((r_multi_ack_fsm.read() != MULTI_ACK_DIR_REQ) and 9623 9355 (r_multi_ack_fsm.read() != MULTI_ACK_DIR_LOCK) and 9624 9356 (r_multi_ack_fsm.read() != MULTI_ACK_IVT_LOCK) and … … 9631 9363 // (r_alloc_heap_fsm.read() == ALLOC_HEAP_MULTI_ACK))) 9632 9364 { 9633 if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ)9365 if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ) 9634 9366 r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; 9635 9367 9636 else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)9368 else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) 9637 9369 r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; 9638 9370 9639 else if (r_config_fsm.read() == CONFIG_DIR_REQ)9371 else if (r_config_fsm.read() == CONFIG_DIR_REQ) 9640 9372 r_alloc_dir_fsm = ALLOC_DIR_CONFIG; 9641 9373 9642 else if (r_read_fsm.read() == READ_DIR_REQ)9374 else if (r_read_fsm.read() == READ_DIR_REQ) 9643 9375 r_alloc_dir_fsm = ALLOC_DIR_READ; 9644 9376 9645 else if (r_write_fsm.read() == WRITE_DIR_REQ)9377 else if (r_write_fsm.read() == WRITE_DIR_REQ) 9646 9378 r_alloc_dir_fsm = ALLOC_DIR_WRITE; 9647 9379 9648 else if (r_cas_fsm.read() == CAS_DIR_REQ)9380 else if (r_cas_fsm.read() == CAS_DIR_REQ) 9649 9381 r_alloc_dir_fsm = ALLOC_DIR_CAS; 9650 9651 else 9652 m_cpt_dir_unused++; 9653 } 9654 else 9655 m_cpt_multi_ack_fsm_dir_used++; 9382 } 9656 9383 break; 9657 9384 /////////////////////// 9658 9385 case ALLOC_DIR_CLEANUP: // allocated to CLEANUP FSM 9659 if ((r_cleanup_fsm.read() != CLEANUP_DIR_REQ) and9386 if ((r_cleanup_fsm.read() != CLEANUP_DIR_REQ) and 9660 9387 (r_cleanup_fsm.read() != CLEANUP_DIR_LOCK) and 9661 9388 (r_cleanup_fsm.read() != CLEANUP_LOCKED_IVT_LOCK) and … … 9664 9391 (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK)) 9665 9392 { 9666 if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK)9393 if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) 9667 9394 r_alloc_dir_fsm = ALLOC_DIR_XRAM_RSP; 9668 9395 9669 else if (r_config_fsm.read() == CONFIG_DIR_REQ)9396 else if (r_config_fsm.read() == CONFIG_DIR_REQ) 9670 9397 r_alloc_dir_fsm = ALLOC_DIR_CONFIG; 9671 9398 9672 else if (r_read_fsm.read() == READ_DIR_REQ)9399 else if (r_read_fsm.read() == READ_DIR_REQ) 9673 9400 r_alloc_dir_fsm = ALLOC_DIR_READ; 9674 9401 9675 else if (r_write_fsm.read() == WRITE_DIR_REQ)9402 else if (r_write_fsm.read() == WRITE_DIR_REQ) 9676 9403 r_alloc_dir_fsm = ALLOC_DIR_WRITE; 9677 9404 9678 else if (r_cas_fsm.read() == CAS_DIR_REQ)9405 else if (r_cas_fsm.read() == CAS_DIR_REQ) 9679 9406 r_alloc_dir_fsm = ALLOC_DIR_CAS; 9680 9407 9681 else if (r_multi_ack_fsm.read() == MULTI_ACK_DIR_REQ)9408 else if (r_multi_ack_fsm.read() == MULTI_ACK_DIR_REQ) 9682 9409 r_alloc_dir_fsm = ALLOC_DIR_MULTI_ACK; 9683 9684 else 9685 m_cpt_dir_unused++; 9686 } 9687 else 9688 m_cpt_cleanup_fsm_dir_used++; 9410 } 9689 9411 break; 9690 9412 9691 9413 //////////////////////// 9692 9414 case ALLOC_DIR_XRAM_RSP: // allocated to XRAM_RSP FSM 9693 if ((r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) and9415 if ((r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) and 9694 9416 (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) and 9695 9417 (r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK)) 9696 9418 { 9697 if (r_config_fsm.read() == CONFIG_DIR_REQ)9419 if (r_config_fsm.read() == CONFIG_DIR_REQ) 9698 9420 r_alloc_dir_fsm = ALLOC_DIR_CONFIG; 9699 9421 9700 else if (r_read_fsm.read() == READ_DIR_REQ)9422 else if (r_read_fsm.read() == READ_DIR_REQ) 9701 9423 r_alloc_dir_fsm = ALLOC_DIR_READ; 9702 9424 9703 else if (r_write_fsm.read() == WRITE_DIR_REQ)9425 else if (r_write_fsm.read() == WRITE_DIR_REQ) 9704 9426 r_alloc_dir_fsm = ALLOC_DIR_WRITE; 9705 9427 9706 else if (r_cas_fsm.read() == CAS_DIR_REQ)9428 else if (r_cas_fsm.read() == CAS_DIR_REQ) 9707 9429 r_alloc_dir_fsm = ALLOC_DIR_CAS; 9708 9430 9709 else if (r_multi_ack_fsm.read() == MULTI_ACK_DIR_REQ)9431 else if (r_multi_ack_fsm.read() == MULTI_ACK_DIR_REQ) 9710 9432 r_alloc_dir_fsm = ALLOC_DIR_MULTI_ACK; 9711 9433 9712 else if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ)9434 else if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ) 9713 9435 r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; 9714 9715 else 9716 m_cpt_dir_unused++; 9717 } 9718 else 9719 m_cpt_xram_rsp_fsm_dir_used++; 9436 } 9720 9437 break; 9721 9438 … … 9735 9452 //////////////////// 9736 9453 case ALLOC_TRT_READ: 9737 if (r_read_fsm.read() != READ_TRT_LOCK)9738 { 9739 if (r_write_fsm.read() == WRITE_MISS_TRT_LOCK)9454 if (r_read_fsm.read() != READ_TRT_LOCK) 9455 { 9456 if (r_write_fsm.read() == WRITE_MISS_TRT_LOCK) 9740 9457 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 9741 9458 9742 else if (r_cas_fsm.read() == CAS_MISS_TRT_LOCK)9459 else if (r_cas_fsm.read() == CAS_MISS_TRT_LOCK) 9743 9460 r_alloc_trt_fsm = ALLOC_TRT_CAS; 9744 9461 9745 else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or9462 else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or 9746 9463 (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or 9747 9464 (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or … … 9751 9468 r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; 9752 9469 9753 else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and9470 else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and 9754 9471 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) 9755 9472 r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; 9756 9473 9757 else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or9474 else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or 9758 9475 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) 9759 9476 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; 9760 9477 9761 else if (r_config_fsm.read() == CONFIG_TRT_LOCK )9478 else if (r_config_fsm.read() == CONFIG_TRT_LOCK ) 9762 9479 r_alloc_trt_fsm = ALLOC_TRT_CONFIG; 9763 9480 9764 9481 else if (r_cleanup_fsm.read() == CLEANUP_MISS_IXR_REQ) 9765 9482 r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; 9766 9767 else 9768 m_cpt_trt_unused++; 9769 } 9770 else 9771 m_cpt_read_fsm_trt_used++; 9483 } 9772 9484 break; 9773 9485 9774 9486 ///////////////////// 9775 9487 case ALLOC_TRT_WRITE: 9776 if ((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and9488 if ((r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and 9777 9489 (r_write_fsm.read() != WRITE_INVAL_IVT_LOCK)) 9778 9490 { 9779 if (r_cas_fsm.read() == CAS_MISS_TRT_LOCK)9491 if (r_cas_fsm.read() == CAS_MISS_TRT_LOCK) 9780 9492 r_alloc_trt_fsm = ALLOC_TRT_CAS; 9781 9493 9782 else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or9494 else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or 9783 9495 (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or 9784 9496 (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or … … 9788 9500 r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; 9789 9501 9790 else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and9502 else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and 9791 9503 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) 9792 9504 r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; 9793 9505 9794 else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or9506 else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or 9795 9507 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) 9796 9508 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; 9797 9509 9798 else if (r_config_fsm.read() == CONFIG_TRT_LOCK )9510 else if (r_config_fsm.read() == CONFIG_TRT_LOCK ) 9799 9511 r_alloc_trt_fsm = ALLOC_TRT_CONFIG; 9800 9512 … … 9802 9514 r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; 9803 9515 9804 else if (r_read_fsm.read() == READ_TRT_LOCK)9516 else if (r_read_fsm.read() == READ_TRT_LOCK) 9805 9517 r_alloc_trt_fsm = ALLOC_TRT_READ; 9806 9807 else 9808 m_cpt_trt_unused++; 9809 } 9810 else 9811 m_cpt_write_fsm_trt_used++; 9518 } 9812 9519 break; 9813 9520 9814 9521 //////////////////// 9815 9522 case ALLOC_TRT_CAS: 9816 if (r_cas_fsm.read() != CAS_MISS_TRT_LOCK)9817 { 9818 if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or9523 if (r_cas_fsm.read() != CAS_MISS_TRT_LOCK) 9524 { 9525 if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or 9819 9526 (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or 9820 9527 (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or … … 9824 9531 r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; 9825 9532 9826 else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and9533 else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and 9827 9534 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) 9828 9535 r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; 9829 9536 9830 else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or9537 else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or 9831 9538 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) 9832 9539 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; 9833 9540 9834 else if (r_config_fsm.read() == CONFIG_TRT_LOCK )9541 else if (r_config_fsm.read() == CONFIG_TRT_LOCK ) 9835 9542 r_alloc_trt_fsm = ALLOC_TRT_CONFIG; 9836 9543 … … 9838 9545 r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; 9839 9546 9840 else if (r_read_fsm.read() == READ_TRT_LOCK)9547 else if (r_read_fsm.read() == READ_TRT_LOCK) 9841 9548 r_alloc_trt_fsm = ALLOC_TRT_READ; 9842 9549 9843 else if (r_write_fsm.read() == WRITE_MISS_TRT_LOCK)9550 else if (r_write_fsm.read() == WRITE_MISS_TRT_LOCK) 9844 9551 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 9845 9846 else 9847 m_cpt_trt_unused++; 9848 } 9849 else 9850 m_cpt_cas_fsm_trt_used++; 9552 } 9851 9553 break; 9852 9554 /////////////////////// 9853 9555 case ALLOC_TRT_IXR_CMD: 9854 if ((r_ixr_cmd_fsm.read() != IXR_CMD_READ_TRT) and9556 if ((r_ixr_cmd_fsm.read() != IXR_CMD_READ_TRT) and 9855 9557 (r_ixr_cmd_fsm.read() != IXR_CMD_WRITE_TRT) and 9856 9558 (r_ixr_cmd_fsm.read() != IXR_CMD_CAS_TRT) and … … 9859 9561 (r_ixr_cmd_fsm.read() != IXR_CMD_CONFIG_TRT)) 9860 9562 { 9861 if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and9563 if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and 9862 9564 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) 9863 9565 r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; 9864 9566 9865 else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or9567 else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or 9866 9568 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) 9867 9569 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; 9868 9570 9869 else if (r_config_fsm.read() == CONFIG_TRT_LOCK )9571 else if (r_config_fsm.read() == CONFIG_TRT_LOCK ) 9870 9572 r_alloc_trt_fsm = ALLOC_TRT_CONFIG; 9871 9573 … … 9873 9575 r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; 9874 9576 9875 else if (r_read_fsm.read() == READ_TRT_LOCK)9577 else if (r_read_fsm.read() == READ_TRT_LOCK) 9876 9578 r_alloc_trt_fsm = ALLOC_TRT_READ; 9877 9579 9878 else if (r_write_fsm.read() == WRITE_MISS_TRT_LOCK)9580 else if (r_write_fsm.read() == WRITE_MISS_TRT_LOCK) 9879 9581 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 9880 9582 9881 else if (r_cas_fsm.read() == CAS_MISS_TRT_LOCK)9583 else if (r_cas_fsm.read() == CAS_MISS_TRT_LOCK) 9882 9584 r_alloc_trt_fsm = ALLOC_TRT_CAS; 9883 9884 else 9885 m_cpt_trt_unused++; 9886 9887 } 9888 else 9889 m_cpt_ixr_cmd_fsm_trt_used++; 9890 9585 } 9891 9586 break; 9892 9587 9893 9588 //////////////////////// 9894 9589 case ALLOC_TRT_XRAM_RSP: 9895 if (((r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) or9590 if (((r_xram_rsp_fsm.read() != XRAM_RSP_DIR_LOCK) or 9896 9591 (r_alloc_dir_fsm.read() != ALLOC_DIR_XRAM_RSP)) and 9897 9592 (r_xram_rsp_fsm.read() != XRAM_RSP_TRT_COPY) and … … 9899 9594 (r_xram_rsp_fsm.read() != XRAM_RSP_IVT_LOCK)) 9900 9595 { 9901 if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or9596 if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or 9902 9597 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) 9903 9598 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; 9904 9599 9905 else if (r_config_fsm.read() == CONFIG_TRT_LOCK )9600 else if (r_config_fsm.read() == CONFIG_TRT_LOCK ) 9906 9601 r_alloc_trt_fsm = ALLOC_TRT_CONFIG; 9907 9602 … … 9909 9604 r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; 9910 9605 9911 else if (r_read_fsm.read() == READ_TRT_LOCK)9606 else if (r_read_fsm.read() == READ_TRT_LOCK) 9912 9607 r_alloc_trt_fsm = ALLOC_TRT_READ; 9913 9608 9914 else if (r_write_fsm.read() == WRITE_MISS_TRT_LOCK)9609 else if (r_write_fsm.read() == WRITE_MISS_TRT_LOCK) 9915 9610 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 9916 9611 9917 else if (r_cas_fsm.read() == CAS_MISS_TRT_LOCK)9612 else if (r_cas_fsm.read() == CAS_MISS_TRT_LOCK) 9918 9613 r_alloc_trt_fsm = ALLOC_TRT_CAS; 9919 9614 9920 else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or9615 else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or 9921 9616 (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or 9922 9617 (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or … … 9925 9620 (r_ixr_cmd_fsm.read() == IXR_CMD_CONFIG_TRT) ) 9926 9621 r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; 9927 9928 else 9929 m_cpt_trt_unused++; 9930 } 9931 else 9932 m_cpt_xram_rsp_fsm_trt_used++; 9622 } 9933 9623 break; 9934 9624 9935 9625 //////////////////////// 9936 9626 case ALLOC_TRT_IXR_RSP: 9937 if ((r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE) and9627 if ((r_ixr_rsp_fsm.read() != IXR_RSP_TRT_ERASE) and 9938 9628 (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ)) 9939 9629 { 9940 if (r_config_fsm.read() == CONFIG_TRT_LOCK )9630 if (r_config_fsm.read() == CONFIG_TRT_LOCK ) 9941 9631 r_alloc_trt_fsm = ALLOC_TRT_CONFIG; 9942 9632 … … 9944 9634 r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; 9945 9635 9946 else if (r_read_fsm.read() == READ_TRT_LOCK)9636 else if (r_read_fsm.read() == READ_TRT_LOCK) 9947 9637 r_alloc_trt_fsm = ALLOC_TRT_READ; 9948 9638 9949 else if (r_write_fsm.read() == WRITE_MISS_TRT_LOCK)9639 else if (r_write_fsm.read() == WRITE_MISS_TRT_LOCK) 9950 9640 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 9951 9641 9952 else if (r_cas_fsm.read() == CAS_MISS_TRT_LOCK)9642 else if (r_cas_fsm.read() == CAS_MISS_TRT_LOCK) 9953 9643 r_alloc_trt_fsm = ALLOC_TRT_CAS; 9954 9644 9955 else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or9645 else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or 9956 9646 (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or 9957 9647 (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or … … 9961 9651 r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; 9962 9652 9963 else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) &&9653 else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) && 9964 9654 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) 9965 9655 r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; 9966 9967 else 9968 m_cpt_trt_unused++; 9969 } 9970 else 9971 m_cpt_ixr_rsp_fsm_trt_used++; 9656 } 9972 9657 break; 9973 9658 9974 9659 ////////////////////// 9975 9660 case ALLOC_TRT_CONFIG: 9976 if ((r_config_fsm.read() != CONFIG_TRT_LOCK) and9661 if ((r_config_fsm.read() != CONFIG_TRT_LOCK) and 9977 9662 (r_config_fsm.read() != CONFIG_TRT_SET)) 9978 9663 { … … 9980 9665 r_alloc_trt_fsm = ALLOC_TRT_CLEANUP; 9981 9666 9982 else if (r_read_fsm.read() == READ_TRT_LOCK)9667 else if (r_read_fsm.read() == READ_TRT_LOCK) 9983 9668 r_alloc_trt_fsm = ALLOC_TRT_READ; 9984 9669 9985 else if (r_write_fsm.read() == WRITE_MISS_TRT_LOCK)9670 else if (r_write_fsm.read() == WRITE_MISS_TRT_LOCK) 9986 9671 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 9987 9672 9988 else if (r_cas_fsm.read() == CAS_MISS_TRT_LOCK)9673 else if (r_cas_fsm.read() == CAS_MISS_TRT_LOCK) 9989 9674 r_alloc_trt_fsm = ALLOC_TRT_CAS; 9990 9675 9991 else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or9676 else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or 9992 9677 (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or 9993 9678 (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or … … 9997 9682 r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; 9998 9683 9999 else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and9684 else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and 10000 9685 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) 10001 9686 r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; 10002 9687 10003 else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or9688 else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) or 10004 9689 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) 10005 9690 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; … … 10009 9694 //////////////////////// 10010 9695 case ALLOC_TRT_CLEANUP: 10011 if (r_cleanup_fsm.read() != CLEANUP_MISS_IXR_REQ)10012 { 10013 if (r_read_fsm.read() == READ_TRT_LOCK)9696 if (r_cleanup_fsm.read() != CLEANUP_MISS_IXR_REQ) 9697 { 9698 if (r_read_fsm.read() == READ_TRT_LOCK) 10014 9699 r_alloc_trt_fsm = ALLOC_TRT_READ; 10015 9700 10016 else if (r_write_fsm.read() == WRITE_MISS_TRT_LOCK)9701 else if (r_write_fsm.read() == WRITE_MISS_TRT_LOCK) 10017 9702 r_alloc_trt_fsm = ALLOC_TRT_WRITE; 10018 9703 10019 else if (r_cas_fsm.read() == CAS_MISS_TRT_LOCK)9704 else if (r_cas_fsm.read() == CAS_MISS_TRT_LOCK) 10020 9705 r_alloc_trt_fsm = ALLOC_TRT_CAS; 10021 9706 10022 else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or9707 else if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_TRT) or 10023 9708 (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_TRT) or 10024 9709 (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_TRT) or … … 10028 9713 r_alloc_trt_fsm = ALLOC_TRT_IXR_CMD; 10029 9714 10030 else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and9715 else if ((r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) and 10031 9716 (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP)) 10032 9717 r_alloc_trt_fsm = ALLOC_TRT_XRAM_RSP; 10033 9718 10034 else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ||9719 else if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) || 10035 9720 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) 10036 9721 r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; 10037 9722 10038 else if (r_config_fsm.read() == CONFIG_TRT_LOCK )9723 else if (r_config_fsm.read() == CONFIG_TRT_LOCK ) 10039 9724 r_alloc_trt_fsm = ALLOC_TRT_CONFIG; 10040 10041 else 10042 m_cpt_trt_unused ++; 10043 } 10044 else 10045 m_cpt_cleanup_fsm_trt_used++; 9725 } 10046 9726 break; 10047 9727 … … 10066 9746 r_alloc_heap_reset_cpt.write(r_alloc_heap_reset_cpt.read() + 1); 10067 9747 10068 if (r_alloc_heap_reset_cpt.read() == (m_heap_size-1))9748 if (r_alloc_heap_reset_cpt.read() == (m_heap_size-1)) 10069 9749 { 10070 9750 m_heap.init(); … … 10076 9756 //////////////////// 10077 9757 case ALLOC_HEAP_READ: 10078 if ((r_read_fsm.read() != READ_HEAP_REQ) and9758 if ((r_read_fsm.read() != READ_HEAP_REQ) and 10079 9759 (r_read_fsm.read() != READ_HEAP_LOCK) and 10080 9760 (r_read_fsm.read() != READ_HEAP_ERASE) and … … 10082 9762 (r_read_fsm.read() != READ_INVAL_HEAP_ERASE)) 10083 9763 { 10084 if (r_write_fsm.read() == WRITE_HEAP_REQ)9764 if (r_write_fsm.read() == WRITE_HEAP_REQ) 10085 9765 r_alloc_heap_fsm = ALLOC_HEAP_WRITE; 10086 9766 10087 else if (r_cas_fsm.read() == CAS_MULTI_INVAL_HEAP_LOCK)9767 else if (r_cas_fsm.read() == CAS_MULTI_INVAL_HEAP_LOCK) 10088 9768 r_alloc_heap_fsm = ALLOC_HEAP_CAS; 10089 9769 10090 else if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ)9770 else if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ) 10091 9771 r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; 10092 9772 10093 else if (r_multi_ack_fsm.read() == MULTI_ACK_HEAP_REQ)9773 else if (r_multi_ack_fsm.read() == MULTI_ACK_HEAP_REQ) 10094 9774 r_alloc_heap_fsm = ALLOC_HEAP_MULTI_ACK; 10095 9775 10096 else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ)9776 else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ) 10097 9777 r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; 10098 9778 10099 else if (r_config_fsm.read() == CONFIG_HEAP_REQ)9779 else if (r_config_fsm.read() == CONFIG_HEAP_REQ) 10100 9780 r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; 10101 9781 … … 10103 9783 m_cpt_heap_unused++; 10104 9784 } 10105 else10106 m_cpt_read_fsm_heap_used++;10107 9785 break; 10108 9786 10109 9787 ///////////////////// 10110 9788 case ALLOC_HEAP_WRITE: 10111 if ((r_write_fsm.read() != WRITE_HEAP_REQ) and9789 if ((r_write_fsm.read() != WRITE_HEAP_REQ) and 10112 9790 (r_write_fsm.read() != WRITE_HEAP_ERASE)) 10113 9791 { 10114 if (r_cas_fsm.read() == CAS_MULTI_INVAL_HEAP_LOCK)9792 if (r_cas_fsm.read() == CAS_MULTI_INVAL_HEAP_LOCK) 10115 9793 r_alloc_heap_fsm = ALLOC_HEAP_CAS; 10116 9794 10117 else if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ)9795 else if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ) 10118 9796 r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; 10119 9797 10120 else if (r_multi_ack_fsm.read() == MULTI_ACK_HEAP_REQ)9798 else if (r_multi_ack_fsm.read() == MULTI_ACK_HEAP_REQ) 10121 9799 r_alloc_heap_fsm = ALLOC_HEAP_MULTI_ACK; 10122 9800 10123 else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ)9801 else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ) 10124 9802 r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; 10125 9803 10126 else if (r_config_fsm.read() == CONFIG_HEAP_REQ)9804 else if (r_config_fsm.read() == CONFIG_HEAP_REQ) 10127 9805 r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; 10128 9806 10129 else if ((r_read_fsm.read() == READ_HEAP_REQ) or9807 else if ((r_read_fsm.read() == READ_HEAP_REQ) or 10130 9808 (r_read_fsm.read() == READ_INVAL_HEAP_REQ)) 10131 9809 r_alloc_heap_fsm = ALLOC_HEAP_READ; … … 10134 9812 m_cpt_heap_unused++; 10135 9813 } 10136 else10137 m_cpt_write_fsm_heap_used++;10138 9814 break; 10139 9815 10140 9816 //////////////////// 10141 9817 case ALLOC_HEAP_CAS: 10142 if ((r_cas_fsm.read() != CAS_MULTI_INVAL_HEAP_LOCK) and9818 if ((r_cas_fsm.read() != CAS_MULTI_INVAL_HEAP_LOCK) and 10143 9819 (r_cas_fsm.read() != CAS_MULTI_INVAL_REQ) and 10144 9820 (r_cas_fsm.read() != CAS_HEAP_NEXT)) 10145 9821 { 10146 if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ)9822 if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ) 10147 9823 r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; 10148 9824 10149 else if (r_multi_ack_fsm.read() == MULTI_ACK_HEAP_REQ)9825 else if (r_multi_ack_fsm.read() == MULTI_ACK_HEAP_REQ) 10150 9826 r_alloc_heap_fsm = ALLOC_HEAP_MULTI_ACK; 10151 9827 10152 else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ)9828 else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ) 10153 9829 r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; 10154 9830 10155 else if (r_config_fsm.read() == CONFIG_HEAP_REQ)9831 else if (r_config_fsm.read() == CONFIG_HEAP_REQ) 10156 9832 r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; 10157 9833 10158 else if ((r_read_fsm.read() == READ_HEAP_REQ) or9834 else if ((r_read_fsm.read() == READ_HEAP_REQ) or 10159 9835 (r_read_fsm.read() == READ_INVAL_HEAP_REQ)) 10160 9836 r_alloc_heap_fsm = ALLOC_HEAP_READ; 10161 9837 10162 else if (r_write_fsm.read() == WRITE_HEAP_REQ)9838 else if (r_write_fsm.read() == WRITE_HEAP_REQ) 10163 9839 r_alloc_heap_fsm = ALLOC_HEAP_WRITE; 10164 9840 … … 10166 9842 m_cpt_heap_unused++; 10167 9843 } 10168 else10169 m_cpt_cas_fsm_heap_used++;10170 9844 break; 10171 9845 10172 9846 /////////////////////// 10173 9847 case ALLOC_HEAP_CLEANUP: 10174 if ((r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) and9848 if ((r_cleanup_fsm.read() != CLEANUP_HEAP_REQ) and 10175 9849 (r_cleanup_fsm.read() != CLEANUP_HEAP_LOCK) and 10176 9850 (r_cleanup_fsm.read() != CLEANUP_HEAP_SEARCH) and 10177 9851 (r_cleanup_fsm.read() != CLEANUP_HEAP_CLEAN)) 10178 9852 { 10179 if (r_multi_ack_fsm.read() == MULTI_ACK_HEAP_REQ)9853 if (r_multi_ack_fsm.read() == MULTI_ACK_HEAP_REQ) 10180 9854 r_alloc_heap_fsm = ALLOC_HEAP_MULTI_ACK; 10181 9855 10182 else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ)9856 else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ) 10183 9857 r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; 10184 9858 10185 else if (r_config_fsm.read() == CONFIG_HEAP_REQ)9859 else if (r_config_fsm.read() == CONFIG_HEAP_REQ) 10186 9860 r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; 10187 9861 10188 else if ((r_read_fsm.read() == READ_HEAP_REQ) or9862 else if ((r_read_fsm.read() == READ_HEAP_REQ) or 10189 9863 (r_read_fsm.read() == READ_INVAL_HEAP_REQ)) 10190 9864 r_alloc_heap_fsm = ALLOC_HEAP_READ; 10191 9865 10192 else if (r_write_fsm.read() == WRITE_HEAP_REQ)9866 else if (r_write_fsm.read() == WRITE_HEAP_REQ) 10193 9867 r_alloc_heap_fsm = ALLOC_HEAP_WRITE; 10194 9868 10195 else if (r_cas_fsm.read() == CAS_MULTI_INVAL_HEAP_LOCK)9869 else if (r_cas_fsm.read() == CAS_MULTI_INVAL_HEAP_LOCK) 10196 9870 r_alloc_heap_fsm = ALLOC_HEAP_CAS; 10197 9871 … … 10199 9873 m_cpt_heap_unused++; 10200 9874 } 10201 else10202 m_cpt_cleanup_fsm_heap_used++;10203 9875 break; 10204 9876 10205 9877 //////////////////////// 10206 9878 case ALLOC_HEAP_MULTI_ACK: 10207 if ((r_multi_ack_fsm.read() != MULTI_ACK_HEAP_REQ) and9879 if ((r_multi_ack_fsm.read() != MULTI_ACK_HEAP_REQ) and 10208 9880 (r_multi_ack_fsm.read() != MULTI_ACK_HEAP_LOCK)) 10209 9881 { 10210 if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ)9882 if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ) 10211 9883 r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; 10212 9884 10213 else if (r_config_fsm.read() == CONFIG_HEAP_REQ)9885 else if (r_config_fsm.read() == CONFIG_HEAP_REQ) 10214 9886 r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; 10215 9887 10216 else if ((r_read_fsm.read() == READ_HEAP_REQ) or9888 else if ((r_read_fsm.read() == READ_HEAP_REQ) or 10217 9889 (r_read_fsm.read() == READ_INVAL_HEAP_REQ)) 10218 9890 r_alloc_heap_fsm = ALLOC_HEAP_READ; 10219 9891 10220 else if (r_write_fsm.read() == WRITE_HEAP_REQ)9892 else if (r_write_fsm.read() == WRITE_HEAP_REQ) 10221 9893 r_alloc_heap_fsm = ALLOC_HEAP_WRITE; 10222 9894 10223 else if (r_cas_fsm.read() == CAS_MULTI_INVAL_HEAP_LOCK)9895 else if (r_cas_fsm.read() == CAS_MULTI_INVAL_HEAP_LOCK) 10224 9896 r_alloc_heap_fsm = ALLOC_HEAP_CAS; 10225 9897 10226 else if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ)9898 else if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ) 10227 9899 r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; 10228 9900 … … 10230 9902 m_cpt_heap_unused++; 10231 9903 } 10232 else10233 m_cpt_multi_ack_fsm_heap_used++;10234 9904 break; 10235 9905 10236 9906 //////////////////////// 10237 9907 case ALLOC_HEAP_XRAM_RSP: 10238 if ((r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_REQ) and9908 if ((r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_REQ) and 10239 9909 (r_xram_rsp_fsm.read() != XRAM_RSP_HEAP_ERASE)) 10240 9910 { 10241 if (r_config_fsm.read() == CONFIG_HEAP_REQ)9911 if (r_config_fsm.read() == CONFIG_HEAP_REQ) 10242 9912 r_alloc_heap_fsm = ALLOC_HEAP_CONFIG; 10243 9913 10244 else if ((r_read_fsm.read() == READ_HEAP_REQ) or9914 else if ((r_read_fsm.read() == READ_HEAP_REQ) or 10245 9915 (r_read_fsm.read() == READ_INVAL_HEAP_REQ)) 10246 9916 r_alloc_heap_fsm = ALLOC_HEAP_READ; 10247 9917 10248 else if (r_write_fsm.read() == WRITE_HEAP_REQ)9918 else if (r_write_fsm.read() == WRITE_HEAP_REQ) 10249 9919 r_alloc_heap_fsm = ALLOC_HEAP_WRITE; 10250 9920 10251 else if (r_cas_fsm.read() == CAS_MULTI_INVAL_HEAP_LOCK)9921 else if (r_cas_fsm.read() == CAS_MULTI_INVAL_HEAP_LOCK) 10252 9922 r_alloc_heap_fsm = ALLOC_HEAP_CAS; 10253 9923 10254 else if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ)9924 else if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ) 10255 9925 r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; 10256 9926 10257 else if (r_multi_ack_fsm.read() == MULTI_ACK_HEAP_REQ)9927 else if (r_multi_ack_fsm.read() == MULTI_ACK_HEAP_REQ) 10258 9928 r_alloc_heap_fsm = ALLOC_HEAP_MULTI_ACK; 10259 9929 10260 9930 else 10261 9931 m_cpt_heap_unused++; 10262 10263 9932 } 10264 9933 break; … … 10266 9935 /////////////////////// 10267 9936 case ALLOC_HEAP_CONFIG: 10268 if ((r_config_fsm.read() != CONFIG_HEAP_REQ) and9937 if ((r_config_fsm.read() != CONFIG_HEAP_REQ) and 10269 9938 (r_config_fsm.read() != CONFIG_HEAP_SCAN)) 10270 9939 { 10271 if ((r_read_fsm.read() == READ_HEAP_REQ) or9940 if ((r_read_fsm.read() == READ_HEAP_REQ) or 10272 9941 (r_read_fsm.read() == READ_INVAL_HEAP_REQ)) 10273 9942 r_alloc_heap_fsm = ALLOC_HEAP_READ; 10274 9943 10275 else if (r_write_fsm.read() == WRITE_HEAP_REQ)9944 else if (r_write_fsm.read() == WRITE_HEAP_REQ) 10276 9945 r_alloc_heap_fsm = ALLOC_HEAP_WRITE; 10277 9946 10278 else if (r_cas_fsm.read() == CAS_MULTI_INVAL_HEAP_LOCK)9947 else if (r_cas_fsm.read() == CAS_MULTI_INVAL_HEAP_LOCK) 10279 9948 r_alloc_heap_fsm = ALLOC_HEAP_CAS; 10280 9949 10281 else if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ)9950 else if (r_cleanup_fsm.read() == CLEANUP_HEAP_REQ) 10282 9951 r_alloc_heap_fsm = ALLOC_HEAP_CLEANUP; 10283 9952 10284 else if (r_multi_ack_fsm.read() == MULTI_ACK_HEAP_REQ)9953 else if (r_multi_ack_fsm.read() == MULTI_ACK_HEAP_REQ) 10285 9954 r_alloc_heap_fsm = ALLOC_HEAP_MULTI_ACK; 10286 9955 10287 else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ)9956 else if (r_xram_rsp_fsm.read() == XRAM_RSP_HEAP_REQ) 10288 9957 r_alloc_heap_fsm = ALLOC_HEAP_XRAM_RSP; 10289 9958 else 10290 9959 m_cpt_heap_unused++; 10291 9960 } 10292 else10293 m_cpt_xram_rsp_fsm_heap_used++;10294 9961 break; 10295 9962 … … 10351 10018 //////////////////////////////////////////////////////////////////////////////////// 10352 10019 10353 if (cc_receive_to_cleanup_fifo_put)10020 if (cc_receive_to_cleanup_fifo_put) 10354 10021 { 10355 if (cc_receive_to_cleanup_fifo_get)10022 if (cc_receive_to_cleanup_fifo_get) 10356 10023 { 10357 10024 m_cc_receive_to_cleanup_fifo.put_and_get( ((uint64_t)(p_dspin_p2m.eop.read()&0x1) << 32) | p_dspin_p2m.data.read() ); … … 10364 10031 else 10365 10032 { 10366 if (cc_receive_to_cleanup_fifo_get)10033 if (cc_receive_to_cleanup_fifo_get) 10367 10034 { 10368 10035 m_cc_receive_to_cleanup_fifo.simple_get(); … … 10377 10044 //////////////////////////////////////////////////////////////////////////////////// 10378 10045 10379 if (cc_receive_to_multi_ack_fifo_put)10046 if (cc_receive_to_multi_ack_fifo_put) 10380 10047 { 10381 if (cc_receive_to_multi_ack_fifo_get)10048 if (cc_receive_to_multi_ack_fifo_get) 10382 10049 { 10383 10050 m_cc_receive_to_multi_ack_fifo.put_and_get( ((uint64_t)(p_dspin_p2m.eop.read()&0x1) << 32) | p_dspin_p2m.data.read() ); … … 10390 10057 else 10391 10058 { 10392 if (cc_receive_to_multi_ack_fifo_get)10059 if (cc_receive_to_multi_ack_fifo_get) 10393 10060 { 10394 10061 m_cc_receive_to_multi_ack_fifo.simple_get(); … … 10446 10113 // The three sources of (increment / decrement) are CONFIG / CLEANUP / IXR_RSP FSMs 10447 10114 //////////////////////////////////////////////////////////////////////////////////// 10448 if ( 10115 if (config_rsp_lines_incr and not 10449 10116 (config_rsp_lines_cleanup_decr or config_rsp_lines_ixr_rsp_decr) ) 10450 10117 { 10451 10118 r_config_rsp_lines = r_config_rsp_lines.read() + 1; 10452 10119 } 10453 if ( 10120 if (not config_rsp_lines_incr and 10454 10121 (config_rsp_lines_cleanup_decr or config_rsp_lines_ixr_rsp_decr) ) 10455 10122 { … … 10462 10129 // r_debug_data); 10463 10130 //#if DEBUG_MEMC_MULTI_ACK 10464 // if (m_debug)10131 // if (m_debug) 10465 10132 // std::cout << " <MEMC " << name() << " DEBUG DATA>" 10466 10133 // << " / data0 = " << r_debug_data[0].read() … … 10522 10189 p_vci_ixr.cfixed = false; 10523 10190 10524 if ( 10191 if ((r_ixr_cmd_fsm.read() == IXR_CMD_READ_SEND) or 10525 10192 (r_ixr_cmd_fsm.read() == IXR_CMD_WRITE_SEND) or 10526 10193 (r_ixr_cmd_fsm.read() == IXR_CMD_CAS_SEND) or … … 10530 10197 p_vci_ixr.cmdval = true; 10531 10198 10532 if ( 10199 if (r_ixr_cmd_get.read() ) // GET 10533 10200 { 10534 10201 p_vci_ixr.cmd = vci_param_ext::CMD_READ; … … 10567 10234 //////////////////////////////////////////////////// 10568 10235 10569 if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ) or10236 if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ) or 10570 10237 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ) 10571 10238 { … … 10667 10334 p_vci_tgt.rspval = true; 10668 10335 10669 if ( 10336 if (is_ll and not r_tgt_rsp_key_sent.read() ) 10670 10337 { 10671 10338 // LL response first flit … … 10689 10356 { 10690 10357 p_vci_tgt.rspval = true; 10691 if (((r_write_to_tgt_rsp_pktid.read() & 0x7) == TYPE_SC) and r_write_to_tgt_rsp_sc_fail.read())10358 if (((r_write_to_tgt_rsp_pktid.read() & 0x7) == TYPE_SC) and r_write_to_tgt_rsp_sc_fail.read()) 10692 10359 p_vci_tgt.rdata = 1; 10693 10360 else … … 10711 10378 p_vci_tgt.rdata = r_cleanup_to_tgt_rsp_ll_key.read(); 10712 10379 } 10713 else if ( 10380 else if (not r_cleanup_to_tgt_rsp_type.read()) 10714 10381 { 10715 10382 p_vci_tgt.rdata = r_cleanup_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read(); … … 10748 10415 p_vci_tgt.rspval = true; 10749 10416 10750 if (is_ll and not r_tgt_rsp_key_sent.read() )10417 if (is_ll and not r_tgt_rsp_key_sent.read() ) 10751 10418 { 10752 10419 // LL response first flit … … 10778 10445 p_vci_tgt.rspval = true; 10779 10446 10780 if (is_ll and not r_tgt_rsp_key_sent.read())10447 if (is_ll and not r_tgt_rsp_key_sent.read()) 10781 10448 { 10782 10449 p_vci_tgt.rdata = r_cleanup_to_tgt_rsp_ll_key.read(); … … 10818 10485 { 10819 10486 uint8_t multi_inval_type; 10820 if (m_config_to_cc_send_inst_fifo.read())10821 { 10822 multi_inval_type = Dspin DhccpParam::TYPE_MULTI_INVAL_INST;10487 if (m_config_to_cc_send_inst_fifo.read()) 10488 { 10489 multi_inval_type = DspinHmesiParam::TYPE_MULTI_INVAL_INST; 10823 10490 } 10824 10491 else 10825 10492 { 10826 multi_inval_type = Dspin DhccpParam::TYPE_MULTI_INVAL_DATA;10493 multi_inval_type = DspinHmesiParam::TYPE_MULTI_INVAL_DATA; 10827 10494 } 10828 10495 10829 10496 uint64_t flit = 0; 10830 10497 uint64_t dest = m_config_to_cc_send_srcid_fifo.read() << 10831 (Dspin DhccpParam::SRCID_WIDTH - vci_param_int::S);10832 10833 Dspin DhccpParam::dspin_set( flit,10498 (DspinHmesiParam::SRCID_WIDTH - vci_param_int::S); 10499 10500 DspinHmesiParam::dspin_set( flit, 10834 10501 dest, 10835 DspinDhccpParam::MULTI_INVAL_DEST); 10836 10837 DspinDhccpParam::dspin_set( flit, 10838 m_cc_global_id , 10839 DspinDhccpParam::MULTI_INVAL_SRCID); 10502 DspinHmesiParam::MULTI_INVAL_DEST); 10840 10503 10841 10504 // MODIFIED FOR CONFIG INVAL (solution 1 bit in flit multi_inval) 10842 Dspin DhccpParam::dspin_set( flit,10505 DspinHmesiParam::dspin_set( flit, 10843 10506 1, 10844 Dspin DhccpParam::MULTI_INVAL_IS_CONFIG);10845 10846 Dspin DhccpParam::dspin_set( flit,10507 DspinHmesiParam::MULTI_INVAL_IS_CONFIG); 10508 10509 DspinHmesiParam::dspin_set( flit, 10847 10510 r_config_to_cc_send_trdid.read(), 10848 Dspin DhccpParam::MULTI_INVAL_UPDT_INDEX);10849 10850 Dspin DhccpParam::dspin_set( flit,10511 DspinHmesiParam::MULTI_INVAL_UPDT_INDEX); 10512 10513 DspinHmesiParam::dspin_set( flit, 10851 10514 multi_inval_type, 10852 Dspin DhccpParam::M2P_TYPE);10515 DspinHmesiParam::M2P_TYPE); 10853 10516 p_dspin_m2p.write = true; 10854 10517 p_dspin_m2p.data = flit; … … 10859 10522 { 10860 10523 uint64_t flit = 0; 10861 Dspin DhccpParam::dspin_set( flit,10524 DspinHmesiParam::dspin_set( flit, 10862 10525 r_config_to_cc_send_nline.read(), 10863 Dspin DhccpParam::MULTI_INVAL_NLINE);10526 DspinHmesiParam::MULTI_INVAL_NLINE); 10864 10527 p_dspin_m2p.eop = true; 10865 10528 p_dspin_m2p.write = true; … … 10870 10533 case CC_SEND_XRAM_RSP_INVAL_HEADER: 10871 10534 { 10872 if (not m_xram_rsp_to_cc_send_inst_fifo.rok()) break;10535 if (not m_xram_rsp_to_cc_send_inst_fifo.rok()) break; 10873 10536 10874 10537 uint8_t multi_inval_type; 10875 if (m_xram_rsp_to_cc_send_inst_fifo.read())10876 { 10877 multi_inval_type = Dspin DhccpParam::TYPE_MULTI_INVAL_INST;10538 if (m_xram_rsp_to_cc_send_inst_fifo.read()) 10539 { 10540 multi_inval_type = DspinHmesiParam::TYPE_MULTI_INVAL_INST; 10878 10541 } 10879 10542 else 10880 10543 { 10881 multi_inval_type = Dspin DhccpParam::TYPE_MULTI_INVAL_DATA;10544 multi_inval_type = DspinHmesiParam::TYPE_MULTI_INVAL_DATA; 10882 10545 } 10883 10546 10884 10547 uint64_t flit = 0; 10885 10548 uint64_t dest = m_xram_rsp_to_cc_send_srcid_fifo.read() << 10886 (Dspin DhccpParam::SRCID_WIDTH - vci_param_int::S);10887 10888 Dspin DhccpParam::dspin_set( flit,10549 (DspinHmesiParam::SRCID_WIDTH - vci_param_int::S); 10550 10551 DspinHmesiParam::dspin_set( flit, 10889 10552 dest, 10890 DspinDhccpParam::MULTI_INVAL_DEST); 10891 10892 DspinDhccpParam::dspin_set( flit, 10893 m_cc_global_id , 10894 DspinDhccpParam::MULTI_INVAL_SRCID); 10895 10896 DspinDhccpParam::dspin_set( flit, 10553 DspinHmesiParam::MULTI_INVAL_DEST); 10554 10555 DspinHmesiParam::dspin_set( flit, 10897 10556 r_xram_rsp_to_cc_send_trdid.read(), 10898 Dspin DhccpParam::MULTI_INVAL_UPDT_INDEX);10899 10900 Dspin DhccpParam::dspin_set( flit,10557 DspinHmesiParam::MULTI_INVAL_UPDT_INDEX); 10558 10559 DspinHmesiParam::dspin_set( flit, 10901 10560 multi_inval_type, 10902 Dspin DhccpParam::M2P_TYPE);10561 DspinHmesiParam::M2P_TYPE); 10903 10562 p_dspin_m2p.write = true; 10904 10563 p_dspin_m2p.data = flit; … … 10911 10570 uint64_t flit = 0; 10912 10571 10913 Dspin DhccpParam::dspin_set( flit,10572 DspinHmesiParam::dspin_set( flit, 10914 10573 r_xram_rsp_to_cc_send_nline.read(), 10915 Dspin DhccpParam::MULTI_INVAL_NLINE);10574 DspinHmesiParam::MULTI_INVAL_NLINE); 10916 10575 p_dspin_m2p.eop = true; 10917 10576 p_dspin_m2p.write = true; … … 10925 10584 uint64_t flit = 0; 10926 10585 10927 Dspin DhccpParam::dspin_set( flit,10586 DspinHmesiParam::dspin_set( flit, 10928 10587 m_broadcast_boundaries, 10929 Dspin DhccpParam::BROADCAST_BOX);10588 DspinHmesiParam::BROADCAST_BOX); 10930 10589 // MODIFIED FOR CONFIG INVAL (solution 1 bit in flit multi_inval) 10931 Dspin DhccpParam::dspin_set( flit,10590 DspinHmesiParam::dspin_set( flit, 10932 10591 1, 10933 DspinDhccpParam::BRDCAST_IS_CONFIG); 10934 10935 DspinDhccpParam::dspin_set( flit, 10936 m_cc_global_id, 10937 DspinDhccpParam::BROADCAST_SRCID); 10938 10939 DspinDhccpParam::dspin_set( flit, 10592 DspinHmesiParam::BRDCAST_IS_CONFIG); 10593 10594 DspinHmesiParam::dspin_set( flit, 10940 10595 1ULL, 10941 Dspin DhccpParam::M2P_BC);10596 DspinHmesiParam::M2P_BC); 10942 10597 p_dspin_m2p.write = true; 10943 10598 p_dspin_m2p.data = flit; … … 10951 10606 uint64_t flit = 0; 10952 10607 10953 Dspin DhccpParam::dspin_set( flit,10608 DspinHmesiParam::dspin_set( flit, 10954 10609 m_broadcast_boundaries, 10955 DspinDhccpParam::BROADCAST_BOX); 10956 10957 DspinDhccpParam::dspin_set( flit, 10958 m_cc_global_id, 10959 DspinDhccpParam::BROADCAST_SRCID); 10960 10961 DspinDhccpParam::dspin_set( flit, 10610 DspinHmesiParam::BROADCAST_BOX); 10611 10612 DspinHmesiParam::dspin_set( flit, 10962 10613 1ULL, 10963 Dspin DhccpParam::M2P_BC);10614 DspinHmesiParam::M2P_BC); 10964 10615 p_dspin_m2p.write = true; 10965 10616 p_dspin_m2p.data = flit; … … 10971 10622 uint64_t flit = 0; 10972 10623 10973 Dspin DhccpParam::dspin_set( flit,10624 DspinHmesiParam::dspin_set( flit, 10974 10625 m_broadcast_boundaries, 10975 Dspin DhccpParam::BROADCAST_BOX);10976 10977 Dspin DhccpParam::dspin_set( flit,10626 DspinHmesiParam::BROADCAST_BOX); 10627 10628 DspinHmesiParam::dspin_set( flit, 10978 10629 r_read_to_cc_send_srcid.read(), // send the srcid itself which demands the request getM 10979 Dspin DhccpParam::BROADCAST_SRCID);10980 10981 Dspin DhccpParam::dspin_set( flit,10630 DspinHmesiParam::BROADCAST_SRCID); 10631 10632 DspinHmesiParam::dspin_set( flit, 10982 10633 1ULL, 10983 Dspin DhccpParam::M2P_BC);10634 DspinHmesiParam::M2P_BC); 10984 10635 p_dspin_m2p.write = true; 10985 10636 p_dspin_m2p.data = flit; … … 10990 10641 { 10991 10642 uint64_t flit = 0; 10992 Dspin DhccpParam::dspin_set( flit,10643 DspinHmesiParam::dspin_set( flit, 10993 10644 r_xram_rsp_to_cc_send_nline.read(), 10994 Dspin DhccpParam::BROADCAST_NLINE);10645 DspinHmesiParam::BROADCAST_NLINE); 10995 10646 p_dspin_m2p.write = true; 10996 10647 p_dspin_m2p.eop = true; … … 11002 10653 { 11003 10654 uint64_t flit = 0; 11004 Dspin DhccpParam::dspin_set( flit,10655 DspinHmesiParam::dspin_set( flit, 11005 10656 r_config_to_cc_send_nline.read(), 11006 Dspin DhccpParam::BROADCAST_NLINE);10657 DspinHmesiParam::BROADCAST_NLINE); 11007 10658 p_dspin_m2p.write = true; 11008 10659 p_dspin_m2p.eop = true; … … 11014 10665 { 11015 10666 uint64_t flit = 0; 11016 Dspin DhccpParam::dspin_set( flit,10667 DspinHmesiParam::dspin_set( flit, 11017 10668 r_read_to_cc_send_nline.read(), 11018 Dspin DhccpParam::BROADCAST_NLINE);10669 DspinHmesiParam::BROADCAST_NLINE); 11019 10670 p_dspin_m2p.write = true; 11020 10671 p_dspin_m2p.eop = true; … … 11027 10678 uint64_t flit = 0; 11028 10679 11029 if (not m_read_to_cc_send_inst_fifo.rok()) break;10680 if (not m_read_to_cc_send_inst_fifo.rok()) break; 11030 10681 uint8_t multi_inval_type; 11031 10682 11032 10683 uint64_t dest = 11033 10684 m_read_to_cc_send_srcid_fifo.read() << 11034 (Dspin DhccpParam::SRCID_WIDTH - vci_param_int::S);10685 (DspinHmesiParam::SRCID_WIDTH - vci_param_int::S); 11035 10686 11036 10687 if (m_read_to_cc_send_inst_fifo.read()) 11037 10688 { 11038 multi_inval_type = Dspin DhccpParam::TYPE_MULTI_INVAL_INST;10689 multi_inval_type = DspinHmesiParam::TYPE_MULTI_INVAL_INST; 11039 10690 } 11040 10691 else 11041 10692 { 11042 multi_inval_type = Dspin DhccpParam::TYPE_MULTI_INVAL_DATA;11043 } 11044 11045 Dspin DhccpParam::dspin_set(10693 multi_inval_type = DspinHmesiParam::TYPE_MULTI_INVAL_DATA; 10694 } 10695 10696 DspinHmesiParam::dspin_set( 11046 10697 flit, 11047 10698 dest, 11048 Dspin DhccpParam::MULTI_INVAL_DEST);11049 11050 Dspin DhccpParam::dspin_set(10699 DspinHmesiParam::MULTI_INVAL_DEST); 10700 10701 DspinHmesiParam::dspin_set( 11051 10702 flit, 11052 10703 r_read_to_cc_send_is_shared.read(), 11053 Dspin DhccpParam::MULTI_INVAL_IS_SHARED);11054 11055 if (r_read_to_cc_send_type.read())11056 { 11057 Dspin DhccpParam::dspin_set(10704 DspinHmesiParam::MULTI_INVAL_IS_SHARED); 10705 10706 if (r_read_to_cc_send_type.read()) 10707 { 10708 DspinHmesiParam::dspin_set( 11058 10709 flit, 11059 10710 multi_inval_type, 11060 Dspin DhccpParam::M2P_TYPE);10711 DspinHmesiParam::M2P_TYPE); 11061 10712 } 11062 10713 else 11063 10714 { 11064 Dspin DhccpParam::dspin_set(10715 DspinHmesiParam::dspin_set( 11065 10716 flit, 11066 Dspin DhccpParam::TYPE_MULTI_UPDT_DATA,11067 Dspin DhccpParam::M2P_TYPE);11068 11069 Dspin DhccpParam::dspin_set(10717 DspinHmesiParam::TYPE_MULTI_UPDT_DATA, 10718 DspinHmesiParam::M2P_TYPE); 10719 10720 DspinHmesiParam::dspin_set( 11070 10721 flit, 11071 10722 r_read_to_cc_send_ivt_index.read(), 11072 Dspin DhccpParam::CC_UPDT_IVT_INDEX);10723 DspinHmesiParam::CC_UPDT_IVT_INDEX); 11073 10724 11074 10725 } … … 11084 10735 uint64_t flit = 0; 11085 10736 11086 Dspin DhccpParam::dspin_set(10737 DspinHmesiParam::dspin_set( 11087 10738 flit, 11088 10739 r_read_to_cc_send_nline.read(), 11089 Dspin DhccpParam::MULTI_INVAL_NLINE);10740 DspinHmesiParam::MULTI_INVAL_NLINE); 11090 10741 11091 10742 … … 11101 10752 { 11102 10753 uint64_t flit = 0; 11103 Dspin DhccpParam::dspin_set( flit,10754 DspinHmesiParam::dspin_set( flit, 11104 10755 r_write_to_cc_send_nline.read(), 11105 Dspin DhccpParam::BROADCAST_NLINE);10756 DspinHmesiParam::BROADCAST_NLINE); 11106 10757 p_dspin_m2p.write = true; 11107 10758 p_dspin_m2p.eop = true; … … 11113 10764 { 11114 10765 uint64_t flit = 0; 11115 Dspin DhccpParam::dspin_set( flit,10766 DspinHmesiParam::dspin_set( flit, 11116 10767 r_cas_to_cc_send_nline.read(), 11117 Dspin DhccpParam::BROADCAST_NLINE);10768 DspinHmesiParam::BROADCAST_NLINE); 11118 10769 p_dspin_m2p.write = true; 11119 10770 p_dspin_m2p.eop = true; … … 11124 10775 case CC_SEND_WRITE_INVAL_HEADER: 11125 10776 { 11126 if (not m_write_to_cc_send_inst_fifo.rok()) break;10777 if (not m_write_to_cc_send_inst_fifo.rok()) break; 11127 10778 11128 10779 uint8_t multi_inval_type; 11129 if (m_write_to_cc_send_inst_fifo.read())11130 { 11131 multi_inval_type = Dspin DhccpParam::TYPE_MULTI_INVAL_INST;10780 if (m_write_to_cc_send_inst_fifo.read()) 10781 { 10782 multi_inval_type = DspinHmesiParam::TYPE_MULTI_INVAL_INST; 11132 10783 } 11133 10784 else 11134 10785 { 11135 multi_inval_type = Dspin DhccpParam::TYPE_MULTI_INVAL_DATA;10786 multi_inval_type = DspinHmesiParam::TYPE_MULTI_INVAL_DATA; 11136 10787 } 11137 10788 … … 11139 10790 uint64_t dest = 11140 10791 m_write_to_cc_send_srcid_fifo.read() << 11141 (Dspin DhccpParam::SRCID_WIDTH - vci_param_int::S);11142 11143 Dspin DhccpParam::dspin_set(10792 (DspinHmesiParam::SRCID_WIDTH - vci_param_int::S); 10793 10794 DspinHmesiParam::dspin_set( 11144 10795 flit, 11145 10796 dest, 11146 DspinDhccpParam::MULTI_INVAL_DEST); 11147 11148 DspinDhccpParam::dspin_set( 11149 flit, 11150 m_cc_global_id, 11151 DspinDhccpParam::MULTI_INVAL_SRCID); 11152 11153 DspinDhccpParam::dspin_set( 10797 DspinHmesiParam::MULTI_INVAL_DEST); 10798 10799 DspinHmesiParam::dspin_set( 11154 10800 flit, 11155 10801 multi_inval_type, 11156 Dspin DhccpParam::M2P_TYPE);10802 DspinHmesiParam::M2P_TYPE); 11157 10803 11158 10804 p_dspin_m2p.write = true; … … 11166 10812 uint64_t flit = 0; 11167 10813 11168 Dspin DhccpParam::dspin_set(10814 DspinHmesiParam::dspin_set( 11169 10815 flit, 11170 10816 r_write_to_cc_send_nline.read(), 11171 Dspin DhccpParam::MULTI_UPDT_NLINE);10817 DspinHmesiParam::MULTI_UPDT_NLINE); 11172 10818 11173 10819 p_dspin_m2p.write = true; … … 11184 10830 11185 10831 uint8_t multi_inval_type; 11186 if (m_cas_to_cc_send_inst_fifo.read())11187 { 11188 multi_inval_type = Dspin DhccpParam::TYPE_MULTI_INVAL_INST;10832 if (m_cas_to_cc_send_inst_fifo.read()) 10833 { 10834 multi_inval_type = DspinHmesiParam::TYPE_MULTI_INVAL_INST; 11189 10835 } 11190 10836 else 11191 10837 { 11192 multi_inval_type = Dspin DhccpParam::TYPE_MULTI_INVAL_DATA;10838 multi_inval_type = DspinHmesiParam::TYPE_MULTI_INVAL_DATA; 11193 10839 } 11194 10840 … … 11196 10842 uint64_t dest = 11197 10843 m_cas_to_cc_send_srcid_fifo.read() << 11198 (Dspin DhccpParam::SRCID_WIDTH - vci_param_int::S);11199 11200 Dspin DhccpParam::dspin_set(10844 (DspinHmesiParam::SRCID_WIDTH - vci_param_int::S); 10845 10846 DspinHmesiParam::dspin_set( 11201 10847 flit, 11202 10848 dest, 11203 DspinDhccpParam::MULTI_UPDT_DEST); 11204 11205 DspinDhccpParam::dspin_set( 11206 flit, 11207 m_cc_global_id, 11208 DspinDhccpParam::MULTI_UPDT_SRCID); 11209 11210 DspinDhccpParam::dspin_set( 10849 DspinHmesiParam::MULTI_UPDT_DEST); 10850 10851 DspinHmesiParam::dspin_set( 11211 10852 flit, 11212 10853 multi_inval_type, 11213 Dspin DhccpParam::M2P_TYPE);10854 DspinHmesiParam::M2P_TYPE); 11214 10855 11215 10856 p_dspin_m2p.write = true; … … 11223 10864 uint64_t flit = 0; 11224 10865 11225 Dspin DhccpParam::dspin_set(10866 DspinHmesiParam::dspin_set( 11226 10867 flit, 11227 10868 r_cas_to_cc_send_nline.read(), 11228 Dspin DhccpParam::MULTI_UPDT_NLINE);10869 DspinHmesiParam::MULTI_UPDT_NLINE); 11229 10870 11230 10871 p_dspin_m2p.write = true; … … 11240 10881 //////////////////////////////////////////////////////////////////// 11241 10882 11242 if ( r_cleanup_fsm.read() == CLEANUP_SEND_CLACK)10883 if (r_cleanup_fsm.read() == CLEANUP_SEND_CLACK) 11243 10884 { 11244 10885 uint8_t cleanup_ack_type; 11245 if (r_cleanup_inst.read())10886 if (r_cleanup_inst.read()) 11246 10887 { 11247 cleanup_ack_type = Dspin DhccpParam::TYPE_CLACK_INST;10888 cleanup_ack_type = DspinHmesiParam::TYPE_CLACK_INST; 11248 10889 } 11249 10890 else 11250 10891 { 11251 cleanup_ack_type = Dspin DhccpParam::TYPE_CLACK_DATA;10892 cleanup_ack_type = DspinHmesiParam::TYPE_CLACK_DATA; 11252 10893 } 11253 10894 11254 10895 uint64_t flit = 0; 11255 10896 uint64_t dest = r_cleanup_srcid.read() << 11256 (Dspin DhccpParam::SRCID_WIDTH - vci_param_int::S);11257 11258 Dspin DhccpParam::dspin_set(10897 (DspinHmesiParam::SRCID_WIDTH - vci_param_int::S); 10898 10899 DspinHmesiParam::dspin_set( 11259 10900 flit, 11260 10901 dest, 11261 Dspin DhccpParam::CLACK_DEST);11262 11263 Dspin DhccpParam::dspin_set(10902 DspinHmesiParam::CLACK_DEST); 10903 10904 DspinHmesiParam::dspin_set( 11264 10905 flit, 11265 10906 r_cleanup_nline.read() & 0xFFFF, 11266 Dspin DhccpParam::CLACK_SET);11267 11268 Dspin DhccpParam::dspin_set(10907 DspinHmesiParam::CLACK_SET); 10908 10909 DspinHmesiParam::dspin_set( 11269 10910 flit, 11270 10911 r_cleanup_way_index.read(), 11271 Dspin DhccpParam::CLACK_WAY);11272 11273 Dspin DhccpParam::dspin_set(10912 DspinHmesiParam::CLACK_WAY); 10913 10914 DspinHmesiParam::dspin_set( 11274 10915 flit, 11275 10916 cleanup_ack_type, 11276 Dspin DhccpParam::CLACK_TYPE);10917 DspinHmesiParam::CLACK_TYPE); 11277 10918 11278 10919 p_dspin_clack.eop = true;
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