Index: /trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp =================================================================== --- /trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 788) +++ /trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 789) @@ -34,7 +34,7 @@ #include "../include/vci_cc_vcache_wrapper.h" -#define DEBUG_DCACHE 1 -#define DEBUG_ICACHE 1 -#define DEBUG_CMD 0 +#define DEBUG_DCACHE 1 +#define DEBUG_ICACHE 1 +#define DEBUG_CMD 0 namespace soclib { @@ -42,5 +42,5 @@ namespace { -const char *icache_fsm_state_str[] = { +const char * icache_fsm_state_str[] = { "ICACHE_IDLE", @@ -68,5 +68,5 @@ }; -const char *dcache_fsm_state_str[] = { +const char * dcache_fsm_state_str[] = { "DCACHE_IDLE", @@ -117,5 +117,5 @@ }; -const char *cmd_fsm_state_str[] = { +const char * cmd_fsm_state_str[] = { "CMD_IDLE", "CMD_INS_MISS", @@ -130,5 +130,5 @@ }; -const char *vci_pktid_type_str[] = { +const char * vci_pktid_type_str[] = { "TYPE_DATA_UNC", "TYPE_READ_DATA_MISS", @@ -141,5 +141,5 @@ }; -const char *vci_cmd_type_str[] = { +const char * vci_cmd_type_str[] = { "NOP or STORE_COND", "READ", @@ -148,5 +148,5 @@ }; -const char *rsp_fsm_state_str[] = { +const char * rsp_fsm_state_str[] = { "RSP_IDLE", "RSP_INS_MISS", @@ -158,5 +158,5 @@ }; -const char *cc_receive_fsm_state_str[] = { +const char * cc_receive_fsm_state_str[] = { "CC_RECEIVE_IDLE", "CC_RECEIVE_BRDCAST_HEADER", @@ -174,5 +174,5 @@ }; -const char *cc_send_fsm_state_str[] = { +const char * cc_send_fsm_state_str[] = { "CC_SEND_IDLE", "CC_SEND_CLEANUP_1", @@ -193,26 +193,26 @@ ///////////////////////////////// tmpl(/**/)::VciCcVCacheWrapper( - sc_module_name name, - const int proc_id, - const MappingTable &mtd, - const IntTab &srcid, - const size_t cc_global_id, - const size_t itlb_ways, - const size_t itlb_sets, - const size_t dtlb_ways, - const size_t dtlb_sets, - const size_t icache_ways, - const size_t icache_sets, - const size_t icache_words, - const size_t dcache_ways, - const size_t dcache_sets, - const size_t dcache_words, - const size_t wbuf_nlines, - const size_t wbuf_nwords, - const size_t x_width, - const size_t y_width, - const uint32_t max_frozen_cycles, - const uint32_t debug_start_cycle, - const bool debug_ok ) + sc_module_name name, + const int proc_id, + const MappingTable &mtd, + const IntTab &srcid, + const size_t cc_global_id, + const size_t itlb_ways, + const size_t itlb_sets, + const size_t dtlb_ways, + const size_t dtlb_sets, + const size_t icache_ways, + const size_t icache_sets, + const size_t icache_words, + const size_t dcache_ways, + const size_t dcache_sets, + const size_t dcache_words, + const size_t wbuf_nlines, + const size_t wbuf_nwords, + const size_t x_width, + const size_t y_width, + const uint32_t max_frozen_cycles, + const uint32_t debug_start_cycle, + const bool debug_ok) : soclib::caba::BaseModule(name), @@ -224,27 +224,27 @@ p_dspin_clack("p_dspin_clack"), - m_cacheability_table( mtd.getCacheabilityTable() ), - m_srcid( mtd.indexForId(srcid) ), - m_cc_global_id( cc_global_id ), - m_nline_width( vci_param::N - (uint32_log2(dcache_words)) - 2 ), - m_itlb_ways( itlb_ways ), - m_itlb_sets( itlb_sets ), - m_dtlb_ways( dtlb_ways ), - m_dtlb_sets( dtlb_sets ), - m_icache_ways( icache_ways ), - m_icache_sets( icache_sets ), - m_icache_yzmask( (~0)<<(uint32_log2(icache_words) + 2) ), - m_icache_words( icache_words ), - m_dcache_ways( dcache_ways ), - m_dcache_sets( dcache_sets ), - m_dcache_yzmask( (~0)<<(uint32_log2(dcache_words) + 2) ), - m_dcache_words( dcache_words ), - m_x_width( x_width ), - m_y_width( y_width ), - m_proc_id( proc_id ), - m_max_frozen_cycles( max_frozen_cycles ), - m_paddr_nbits( vci_param::N ), - m_debug_start_cycle( debug_start_cycle ), - m_debug_ok( debug_ok ), + m_cacheability_table( mtd.getCacheabilityTable()), + m_srcid(mtd.indexForId(srcid)), + m_cc_global_id(cc_global_id), + m_nline_width(vci_param::N - (uint32_log2(dcache_words)) - 2), + m_itlb_ways(itlb_ways), + m_itlb_sets(itlb_sets), + m_dtlb_ways(dtlb_ways), + m_dtlb_sets(dtlb_sets), + m_icache_ways(icache_ways), + m_icache_sets(icache_sets), + m_icache_yzmask((~0) << (uint32_log2(icache_words) + 2)), + m_icache_words(icache_words), + m_dcache_ways(dcache_ways), + m_dcache_sets(dcache_sets), + m_dcache_yzmask((~0) << (uint32_log2(dcache_words) + 2)), + m_dcache_words(dcache_words), + m_x_width(x_width), + m_y_width(y_width), + m_proc_id(proc_id), + m_max_frozen_cycles(max_frozen_cycles), + m_paddr_nbits(vci_param::N), + m_debug_start_cycle(debug_start_cycle), + m_debug_ok(debug_ok), m_dcache_paddr_ext_reset(0), m_icache_paddr_ext_reset(0), @@ -376,6 +376,6 @@ r_vci_rsp_ins_error("r_vci_rsp_ins_error"), r_vci_rsp_data_error("r_vci_rsp_data_error"), - r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth - r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth + r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth + r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth r_cc_send_fsm("r_cc_send_fsm"), @@ -385,7 +385,7 @@ r_cc_receive_data_ins("r_cc_receive_data_ins"), r_cc_receive_word_idx("r_cc_receive_word_idx"), - r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2), // 2 words depth - r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2), // 2 words depth - r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2), // 2 words depth + r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2), // 2 words depth + r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2), // 2 words depth + r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2), // 2 words depth r_cc_receive_icache_req("r_cc_receive_icache_req"), @@ -412,29 +412,29 @@ std::cout << " - Building VciCcVcacheWrapper : " << name << std::endl; - assert( ((icache_words*vci_param::B) < (1< 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and + assert((vci_param::T > 2) and ((1 << (vci_param::T - 1)) >= (wbuf_nlines)) and "Need more TRDID bits."); - assert( (icache_words == dcache_words) and + assert((icache_words == dcache_words) and "icache_words and dcache_words parameters must be equal"); - assert( (itlb_sets == dtlb_sets) and + assert((itlb_sets == dtlb_sets) and "itlb_sets and dtlb_sets parameters must be etqual"); - assert( (itlb_ways == dtlb_ways) and + assert((itlb_ways == dtlb_ways) and "itlb_ways and dtlb_ways parameters must be etqual"); - r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) | (uint32_log2(m_dtlb_sets) << 25) | - (uint32_log2(m_dcache_ways) << 22) | (uint32_log2(m_dcache_sets) << 18) | - (uint32_log2(m_itlb_ways) << 15) | (uint32_log2(m_itlb_sets) << 11) | - (uint32_log2(m_icache_ways) << 8) | (uint32_log2(m_icache_sets) << 4) | - (uint32_log2(m_icache_words<<2)); - - r_mmu_release = (uint32_t)(1 << 16) | 0x1; - - r_dcache_in_tlb = new bool[dcache_ways*dcache_sets]; - r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets]; + r_mmu_params = (uint32_log2(m_dtlb_ways) << 29) | (uint32_log2(m_dtlb_sets) << 25) | + (uint32_log2(m_dcache_ways) << 22) | (uint32_log2(m_dcache_sets) << 18) | + (uint32_log2(m_itlb_ways) << 15) | (uint32_log2(m_itlb_sets) << 11) | + (uint32_log2(m_icache_ways) << 8) | (uint32_log2(m_icache_sets) << 4) | + (uint32_log2(m_icache_words << 2)); + + r_mmu_release = (uint32_t) (1 << 16) | 0x1; + + r_dcache_in_tlb = new bool[dcache_ways * dcache_sets]; + r_dcache_contains_ptd = new bool[dcache_ways * dcache_sets]; SC_METHOD(transition); @@ -448,8 +448,8 @@ typename iss_t::CacheInfo cache_info; cache_info.has_mmu = true; - cache_info.icache_line_size = icache_words*sizeof(uint32_t); + cache_info.icache_line_size = icache_words * sizeof(uint32_t); cache_info.icache_assoc = icache_ways; cache_info.icache_n_lines = icache_sets; - cache_info.dcache_line_size = dcache_words*sizeof(uint32_t); + cache_info.dcache_line_size = dcache_words * sizeof(uint32_t); cache_info.dcache_assoc = dcache_ways; cache_info.dcache_n_lines = dcache_sets; @@ -500,46 +500,46 @@ << " | MMU = " << r_mmu_mode.read(); - if (r_dcache_updt_req.read() ) std::cout << " | P1_UPDT"; - if (r_dcache_wbuf_req.read() ) std::cout << " | P1_WBUF"; + if (r_dcache_updt_req.read()) std::cout << " | P1_UPDT"; + if (r_dcache_wbuf_req.read()) std::cout << " | P1_WBUF"; std::cout << std::endl; - if(mode & 0x01) - { - if ( r_icache_miss_req.read() ) std::cout << " IMISS_REQ" << std::endl; - if ( r_icache_unc_req.read() ) std::cout << " IUNC_REQ" << std::endl; - if ( r_dcache_vci_miss_req.read() ) std::cout << " DMISS_REQ" << std::endl; - if ( r_dcache_vci_unc_req.read() ) std::cout << " DUNC_REQ" << std::endl; - - r_wbuf.printTrace((mode>>1)&1); - } - if(mode & 0x02) + if (mode & 0x01) + { + if (r_icache_miss_req.read()) std::cout << " IMISS_REQ" << std::endl; + if (r_icache_unc_req.read()) std::cout << " IUNC_REQ" << std::endl; + if (r_dcache_vci_miss_req.read()) std::cout << " DMISS_REQ" << std::endl; + if (r_dcache_vci_unc_req.read()) std::cout << " DUNC_REQ" << std::endl; + + r_wbuf.printTrace((mode >> 1) & 1); + } + if (mode & 0x02) { r_iss.dump(); } - if(mode & 0x04) + if (mode & 0x04) { std::cout << " Data Cache" << std::endl; r_dcache.printTrace(); } - if(mode & 0x08) + if (mode & 0x08) { std::cout << " Instruction Cache" << std::endl; r_icache.printTrace(); } - if(mode & 0x10) + if (mode & 0x10) { std::cout << " Data TLB" << std::endl; r_dtlb.printTrace(); } - if(mode & 0x20) + if (mode & 0x20) { std::cout << " Instruction TLB" << std::endl; r_itlb.printTrace(); } - if(mode & 0x40) - { - uint32_t status = r_iss.debugGetRegisterValue( 32 ); + if (mode & 0x40) + { + uint32_t status = r_iss.debugGetRegisterValue(32); std::cout << name(); - if ( status != m_previous_status ) std::cout << " NEW "; + if (status != m_previous_status ) std::cout << " NEW "; std::cout << " status = " << std::hex << status << " " << std::endl; m_previous_status = status; @@ -548,20 +548,20 @@ ////////////////////////////////////////// -tmpl(void)::cache_monitor( paddr_t addr ) +tmpl(void)::cache_monitor(paddr_t addr) ////////////////////////////////////////// { - bool cache_hit; - size_t cache_way = 0; - size_t cache_set = 0; - size_t cache_word = 0; - uint32_t cache_rdata = 0; - - cache_hit = r_dcache.read_neutral( addr, - &cache_rdata, - &cache_way, - &cache_set, - &cache_word ); - - if ( cache_hit != m_debug_previous_d_hit ) + bool cache_hit; + size_t cache_way = 0; + size_t cache_set = 0; + size_t cache_word = 0; + uint32_t cache_rdata = 0; + + cache_hit = r_dcache.read_neutral(addr, + &cache_rdata, + &cache_way, + &cache_set, + &cache_word); + + if (cache_hit != m_debug_previous_d_hit) { std::cout << "Monitor PROC " << name() @@ -571,14 +571,14 @@ << " / DATA = " << cache_rdata << " / WAY = " << cache_way << std::endl; - m_debug_previous_d_hit = cache_hit; - } - - cache_hit = r_icache.read_neutral( addr, - &cache_rdata, - &cache_way, - &cache_set, - &cache_word ); - - if ( cache_hit != m_debug_previous_i_hit ) + m_debug_previous_d_hit = cache_hit; + } + + cache_hit = r_icache.read_neutral(addr, + &cache_rdata, + &cache_way, + &cache_set, + &cache_word); + + if (cache_hit != m_debug_previous_i_hit) { std::cout << "Monitor PROC " << name() @@ -588,5 +588,5 @@ << " / DATA = " << cache_rdata << " / WAY = " << cache_way << std::endl; - m_debug_previous_i_hit = cache_hit; + m_debug_previous_i_hit = cache_hit; } } @@ -742,5 +742,5 @@ ///////////////////////// { - if ( not p_resetn.read() ) + if (not p_resetn.read()) { r_iss.reset(); @@ -751,10 +751,10 @@ r_dtlb.reset(); - r_dcache_fsm = DCACHE_IDLE; - r_icache_fsm = ICACHE_IDLE; - r_vci_cmd_fsm = CMD_IDLE; - r_vci_rsp_fsm = RSP_IDLE; - r_cc_receive_fsm = CC_RECEIVE_IDLE; - r_cc_send_fsm = CC_SEND_IDLE; + r_dcache_fsm = DCACHE_IDLE; + r_icache_fsm = ICACHE_IDLE; + r_vci_cmd_fsm = CMD_IDLE; + r_vci_rsp_fsm = RSP_IDLE; + r_cc_receive_fsm = CC_RECEIVE_IDLE; + r_cc_send_fsm = CC_SEND_IDLE; // reset data physical address extension @@ -765,7 +765,7 @@ // reset dcache directory extension - for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++) - { - r_dcache_in_tlb[i] = false; + for (size_t i = 0; i< m_dcache_ways * m_dcache_sets; i++) + { + r_dcache_in_tlb[i] = false; r_dcache_contains_ptd[i] = false; } @@ -779,5 +779,5 @@ r_mmu_mode = 0x3; - // No request from ICACHE FSM to CMD FSM + // No request from ICACHE FSM to CMD FSM r_icache_miss_req = false; r_icache_unc_req = false; @@ -807,5 +807,5 @@ // No request from DCACHE FSM to CC_SEND FSM - r_dcache_cc_send_req = false; + r_dcache_cc_send_req = false; r_dcache_cleanup_victim_req = false; @@ -836,7 +836,7 @@ m_debug_previous_i_hit = false; m_debug_previous_d_hit = false; - m_debug_icache_fsm = false; - m_debug_dcache_fsm = false; - m_debug_cmd_fsm = false; + m_debug_icache_fsm = false; + m_debug_dcache_fsm = false; + m_debug_cmd_fsm = false; // activity counters @@ -899,18 +899,18 @@ m_cost_data_tlb_occup_cache_frz = 0; - m_cpt_ins_tlb_inval = 0; - m_cpt_data_tlb_inval = 0; - m_cost_ins_tlb_inval_frz = 0; - m_cost_data_tlb_inval_frz = 0; + m_cpt_ins_tlb_inval = 0; + m_cpt_data_tlb_inval = 0; + m_cost_ins_tlb_inval_frz = 0; + m_cost_data_tlb_inval_frz = 0; m_cpt_cc_broadcast = 0; - m_cost_updt_data_frz = 0; - m_cost_inval_ins_frz = 0; - m_cost_inval_data_frz = 0; - m_cost_broadcast_frz = 0; - - m_cpt_cc_cleanup_data = 0; - m_cpt_cc_cleanup_ins = 0; + m_cost_updt_data_frz = 0; + m_cost_inval_ins_frz = 0; + m_cost_inval_data_frz = 0; + m_cost_broadcast_frz = 0; + + m_cpt_cc_cleanup_data = 0; + m_cpt_cc_cleanup_ins = 0; m_cpt_itlbmiss_transaction = 0; @@ -933,15 +933,15 @@ /* m_cpt_dcache_frz_cycles = 0; - m_cpt_read = 0; - m_cpt_write = 0; - m_cpt_cc_update_data = 0; - m_cpt_cc_inval_ins = 0; - m_cpt_cc_inval_data = 0; + m_cpt_read = 0; + m_cpt_write = 0; + m_cpt_cc_update_data = 0; + m_cpt_cc_inval_ins = 0; + m_cpt_cc_inval_data = 0; */ - for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0; - for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0; - for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0; - for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0; + for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_icache[i] = 0; + for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_dcache[i] = 0; + for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_cmd[i] = 0; + for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_rsp[i] = 0; // init the llsc reservation buffer @@ -953,26 +953,26 @@ // Response FIFOs default values - bool vci_rsp_fifo_icache_get = false; - bool vci_rsp_fifo_icache_put = false; - uint32_t vci_rsp_fifo_icache_data = 0; - - bool vci_rsp_fifo_dcache_get = false; - bool vci_rsp_fifo_dcache_put = false; - uint32_t vci_rsp_fifo_dcache_data = 0; + bool vci_rsp_fifo_icache_get = false; + bool vci_rsp_fifo_icache_put = false; + uint32_t vci_rsp_fifo_icache_data = 0; + + bool vci_rsp_fifo_dcache_get = false; + bool vci_rsp_fifo_dcache_put = false; + uint32_t vci_rsp_fifo_dcache_data = 0; // updt fifo - bool cc_receive_updt_fifo_get = false; - bool cc_receive_updt_fifo_put = false; - uint32_t cc_receive_updt_fifo_be = 0; - uint32_t cc_receive_updt_fifo_data = 0; - bool cc_receive_updt_fifo_eop = false; + bool cc_receive_updt_fifo_get = false; + bool cc_receive_updt_fifo_put = false; + uint32_t cc_receive_updt_fifo_be = 0; + uint32_t cc_receive_updt_fifo_data = 0; + bool cc_receive_updt_fifo_eop = false; #ifdef INSTRUMENTATION - m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++; - m_cpt_fsm_icache [r_icache_fsm.read() ] ++; - m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++; - m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++; - m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++; - m_cpt_fsm_cleanup [r_cleanup_cmd_fsm.read()] ++; + m_cpt_fsm_dcache [r_dcache_fsm.read() ] ++; + m_cpt_fsm_icache [r_icache_fsm.read() ] ++; + m_cpt_fsm_cmd [r_vci_cmd_fsm.read()] ++; + m_cpt_fsm_rsp [r_vci_rsp_fsm.read()] ++; + m_cpt_fsm_tgt [r_tgt_fsm.read() ] ++; + m_cpt_fsm_cleanup[r_cleanup_cmd_fsm.read()] ++; #endif @@ -1045,12 +1045,12 @@ // default value for m_irsp - m_irsp.valid = false; - m_irsp.error = false; + m_irsp.valid = false; + m_irsp.error = false; m_irsp.instruction = 0; - switch( r_icache_fsm.read() ) + switch (r_icache_fsm.read()) { ///////////////// - case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests, + case ICACHE_IDLE: // In this state, we handle processor requests, XTN requests, // and coherence requests with a fixed priority: // 1/ Coherence requests => ICACHE_CC_CHECK @@ -1061,5 +1061,5 @@ { // coherence clack interrupt - if ( r_icache_clack_req.read() ) + if (r_icache_clack_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1069,5 +1069,5 @@ // coherence interrupt - if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) + if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1079,24 +1079,24 @@ // These request are not executed in this IDLE state (except XTN_INST_PADDR_EXT), // because they require access to icache or itlb, that are already accessed - if ( r_dcache_xtn_req.read() ) - { - if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR ) - { - r_icache_fsm = ICACHE_XTN_TLB_FLUSH; - } - else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH) + if (r_dcache_xtn_req.read()) + { + if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_PTPR ) + { + r_icache_fsm = ICACHE_XTN_TLB_FLUSH; + } + else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ICACHE_FLUSH) { r_icache_flush_count = 0; - r_icache_fsm = ICACHE_XTN_CACHE_FLUSH; - } - else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL) - { - r_icache_fsm = ICACHE_XTN_TLB_INVAL; - } - else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL) - { - r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA; - } - else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV) + r_icache_fsm = ICACHE_XTN_CACHE_FLUSH; + } + else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ITLB_INVAL) + { + r_icache_fsm = ICACHE_XTN_TLB_INVAL; + } + else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ICACHE_INVAL) + { + r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA; + } + else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_MMU_ICACHE_PA_INV) { if (sizeof(paddr_t) <= 32) @@ -1104,14 +1104,14 @@ assert(r_mmu_word_hi.read() == 0 && "illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr"); - r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read(); + r_icache_vci_paddr = (paddr_t) r_mmu_word_lo.read(); } else { - r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 | - (paddr_t)r_mmu_word_lo.read(); + r_icache_vci_paddr = (paddr_t) r_mmu_word_hi.read() << 32 | + (paddr_t) r_mmu_word_lo.read(); } r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA; } - else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_INST_PADDR_EXT) + else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_INST_PADDR_EXT) { r_icache_paddr_ext = r_dcache_save_wdata.read(); @@ -1120,5 +1120,5 @@ else { - assert( false and + assert(false and "undefined XTN request received by ICACHE FSM"); } @@ -1127,18 +1127,18 @@ // processor request - if ( m_ireq.valid ) - { - bool cacheable; - paddr_t paddr; - bool tlb_hit = false; - pte_info_t tlb_flags; - size_t tlb_way; - size_t tlb_set; - paddr_t tlb_nline; - uint32_t cache_inst = 0; - size_t cache_way; - size_t cache_set; - size_t cache_word; - int cache_state = CACHE_SLOT_STATE_EMPTY; + if (m_ireq.valid ) + { + bool cacheable; + paddr_t paddr; + bool tlb_hit = false; + pte_info_t tlb_flags; + size_t tlb_way; + size_t tlb_set; + paddr_t tlb_nline; + uint32_t cache_inst = 0; + size_t cache_way; + size_t cache_set; + size_t cache_word; + int cache_state = CACHE_SLOT_STATE_EMPTY; // We register processor request @@ -1147,16 +1147,16 @@ // sytematic itlb access (if activated) - if ( r_mmu_mode.read() & INS_TLB_MASK ) + if (r_mmu_mode.read() & INS_TLB_MASK) { #ifdef INSTRUMENTATION -m_cpt_itlb_read++; -#endif - tlb_hit = r_itlb.translate( m_ireq.addr, - &paddr, - &tlb_flags, - &tlb_nline, // unused - &tlb_way, // unused - &tlb_set ); // unused + m_cpt_itlb_read++; +#endif + tlb_hit = r_itlb.translate(m_ireq.addr, + &paddr, + &tlb_flags, + &tlb_nline, // unused + &tlb_way, // unused + &tlb_set); // unused } else if (vci_param::N > 32) @@ -1166,18 +1166,18 @@ // systematic icache access (if activated) - if ( r_mmu_mode.read() & INS_CACHE_MASK ) + if (r_mmu_mode.read() & INS_CACHE_MASK) { #ifdef INSTRUMENTATION -m_cpt_icache_data_read++; -m_cpt_icache_dir_read++; -#endif - r_icache.read( paddr, - &cache_inst, - &cache_way, - &cache_set, - &cache_word, - &cache_state ); + m_cpt_icache_data_read++; + m_cpt_icache_dir_read++; +#endif + r_icache.read(paddr, + &cache_inst, + &cache_way, + &cache_set, + &cache_word, + &cache_state); } @@ -1188,43 +1188,43 @@ // and there is no access rights checking - if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated: + if (not (r_mmu_mode.read() & INS_TLB_MASK)) // tlb not activated: { // cacheability - if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false; - else cacheable = m_cacheability_table[(uint64_t)m_ireq.addr]; - } - else // itlb activated - { - if ( tlb_hit ) // ITLB hit + if (not (r_mmu_mode.read() & INS_CACHE_MASK)) cacheable = false; + else cacheable = m_cacheability_table[(uint64_t) m_ireq.addr]; + } + else // itlb activated + { + if (tlb_hit) // ITLB hit { // cacheability - if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false; + if (not (r_mmu_mode.read() & INS_CACHE_MASK)) cacheable = false; else cacheable = tlb_flags.c; // access rights checking - if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) ) + if (not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER)) { - r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION; - r_mmu_ibvar = m_ireq.addr; - m_irsp.valid = true; - m_irsp.error = true; - m_irsp.instruction = 0; + r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION; + r_mmu_ibvar = m_ireq.addr; + m_irsp.valid = true; + m_irsp.error = true; + m_irsp.instruction = 0; break; } - else if ( not tlb_flags.x ) + else if (not tlb_flags.x) { - r_mmu_ietr = MMU_READ_EXEC_VIOLATION; - r_mmu_ibvar = m_ireq.addr; - m_irsp.valid = true; - m_irsp.error = true; - m_irsp.instruction = 0; + r_mmu_ietr = MMU_READ_EXEC_VIOLATION; + r_mmu_ibvar = m_ireq.addr; + m_irsp.valid = true; + m_irsp.error = true; + m_irsp.instruction = 0; break; } } - else // ITLB miss + else // ITLB miss { #ifdef INSTRUMENTATION -m_cpt_itlb_miss++; + m_cpt_itlb_miss++; #endif r_icache_fsm = ICACHE_TLB_WAIT; @@ -1235,34 +1235,34 @@ // physical address registration - r_icache_vci_paddr = paddr; + r_icache_vci_paddr = paddr; // Finally, we send the response to processor, and compute next state - if ( cacheable ) - { - if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss + if (cacheable) + { + if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss { #ifdef INSTRUMENTATION -m_cpt_icache_miss++; + m_cpt_icache_miss++; #endif // we request a VCI transaction - r_icache_fsm = ICACHE_MISS_SELECT; + r_icache_fsm = ICACHE_MISS_SELECT; #if DEBUG_ICACHE -if ( m_debug_icache_fsm ) -std::cout << " READ MISS in icache" - << " : PADDR = " << std::hex << paddr << std::endl; + if (m_debug_icache_fsm) + std::cout << " READ MISS in icache" + << " : PADDR = " << std::hex << paddr << std::endl; #endif r_icache_miss_req = true; } - else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup + else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup { // stalled until cleanup is acknowledged - r_icache_fsm = ICACHE_IDLE; + r_icache_fsm = ICACHE_IDLE; } - else // cache hit + else // cache hit { #ifdef INSTRUMENTATION -m_cpt_ins_read++; + m_cpt_ins_read++; #endif // return instruction to processor @@ -1271,23 +1271,23 @@ r_icache_fsm = ICACHE_IDLE; #if DEBUG_ICACHE -if ( m_debug_icache_fsm ) -std::cout << " READ HIT in icache" - << " : PADDR = " << std::hex << paddr - << " / INST = " << cache_inst << std::endl; + if (m_debug_icache_fsm) + std::cout << " READ HIT in icache" + << " : PADDR = " << std::hex << paddr + << " / INST = " << cache_inst << std::endl; #endif } } - else // non cacheable read - { - r_icache_unc_req = true; - r_icache_fsm = ICACHE_UNC_WAIT; + else // non cacheable read + { + r_icache_unc_req = true; + r_icache_fsm = ICACHE_UNC_WAIT; #if DEBUG_ICACHE -if ( m_debug_icache_fsm ) -{ - std::cout << " READ UNCACHEABLE in icache" - << " : PADDR = " << std::hex << paddr << std::endl; -} + if (m_debug_icache_fsm) + { + std::cout << " READ UNCACHEABLE in icache" + << " : PADDR = " << std::hex << paddr << std::endl; + } #endif } @@ -1296,5 +1296,5 @@ } ///////////////////// - case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss + case ICACHE_TLB_WAIT: // Waiting the itlb update by the DCACHE FSM after a tlb miss // the itlb is udated by the DCACHE FSM, as well as the // r_mmu_ietr and r_mmu_ibvar registers in case of error. @@ -1304,5 +1304,5 @@ { // coherence clack interrupt - if ( r_icache_clack_req.read() ) + if (r_icache_clack_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1312,5 +1312,5 @@ // coherence interrupt - if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) + if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1319,17 +1319,17 @@ } - if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++; + if (m_ireq.valid) m_cost_ins_tlb_miss_frz++; // DCACHE FSM signals response by reseting the request flip-flop - if ( not r_icache_tlb_miss_req.read() ) - { - if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated + if (not r_icache_tlb_miss_req.read()) + { + if (r_icache_tlb_rsp_error.read()) // error reported : tlb not updated { r_icache_tlb_rsp_error = false; - m_irsp.error = true; - m_irsp.valid = true; - r_icache_fsm = ICACHE_IDLE; - } - else // tlb updated : return to IDLE state + m_irsp.error = true; + m_irsp.valid = true; + r_icache_fsm = ICACHE_IDLE; + } + else // tlb updated : return to IDLE state { r_icache_fsm = ICACHE_IDLE; @@ -1339,22 +1339,22 @@ } ////////////////////////// - case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries + case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries { r_itlb.flush(); - r_dcache_xtn_req = false; - r_icache_fsm = ICACHE_IDLE; + r_dcache_xtn_req = false; + r_icache_fsm = ICACHE_IDLE; break; } //////////////////////////// - case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using + case ICACHE_XTN_CACHE_FLUSH: // Invalidate sequencially all cache lines, using // r_icache_flush_count as a slot counter, - // looping in this state until all slots are visited. + // looping in this state until all slots are visited. // It can require two cycles per slot: // We test here the slot state, and make the actual inval // (if line is valid) in ICACHE_XTN_CACHE_FLUSH_GO state. - // A cleanup request is generated for each valid line + // A cleanup request is generated for each valid line { // coherence clack interrupt - if ( r_icache_clack_req.read() ) + if (r_icache_clack_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1364,5 +1364,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) + if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1371,20 +1371,20 @@ } - if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request is sent - { - int state; - paddr_t tag; - size_t way = r_icache_flush_count.read()/m_icache_sets; - size_t set = r_icache_flush_count.read()%m_icache_sets; + if (not r_icache_cc_send_req.read()) // blocked until previous cc_send request is sent + { + int state; + paddr_t tag; + size_t way = r_icache_flush_count.read()/m_icache_sets; + size_t set = r_icache_flush_count.read()%m_icache_sets; #ifdef INSTRUMENTATION -m_cpt_icache_dir_read++; -#endif - r_icache.read_dir( way, - set, - &tag, - &state ); - - if ( state == CACHE_SLOT_STATE_VALID ) // inval required + m_cpt_icache_dir_read++; +#endif + r_icache.read_dir(way, + set, + &tag, + &state); + + if (state == CACHE_SLOT_STATE_VALID) // inval required { // request cleanup @@ -1395,19 +1395,19 @@ // goes to ICACHE_XTN_CACHE_FLUSH_GO to make inval - r_icache_miss_way = way; - r_icache_miss_set = set; - r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO; - } - else if ( r_icache_flush_count.read() == - (m_icache_sets*m_icache_ways - 1) ) // last slot - { - r_dcache_xtn_req = false; - m_drsp.valid = true; - r_icache_fsm = ICACHE_IDLE; + r_icache_miss_way = way; + r_icache_miss_set = set; + r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO; + } + else if (r_icache_flush_count.read() == + (m_icache_sets*m_icache_ways - 1)) // last slot + { + r_dcache_xtn_req = false; + m_drsp.valid = true; + r_icache_fsm = ICACHE_IDLE; } // saturation counter, to have the same last slot condition // in ICACHE_XTN_CACHE_FLUSH and ICACHE_XTN_CACHE_FLUSH_GO states - if ( r_icache_flush_count.read() < (m_icache_sets*m_icache_ways - 1) ) + if (r_icache_flush_count.read() < (m_icache_sets * m_icache_ways - 1)) { r_icache_flush_count = r_icache_flush_count.read() + 1; @@ -1417,27 +1417,27 @@ } /////////////////////////////// - case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush - { - size_t way = r_icache_miss_way.read(); - size_t set = r_icache_miss_set.read(); + case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush + { + size_t way = r_icache_miss_way.read(); + size_t set = r_icache_miss_set.read(); #ifdef INSTRUMENTATION -m_cpt_icache_dir_write++; -#endif - - r_icache.write_dir( way, - set, - CACHE_SLOT_STATE_ZOMBI ); - - if ( r_icache_flush_count.read() == - (m_icache_sets*m_icache_ways - 1) ) // last slot - { - r_dcache_xtn_req = false; - m_drsp.valid = true; - r_icache_fsm = ICACHE_IDLE; + m_cpt_icache_dir_write++; +#endif + + r_icache.write_dir(way, + set, + CACHE_SLOT_STATE_ZOMBI); + + if (r_icache_flush_count.read() == + (m_icache_sets*m_icache_ways - 1)) // last slot + { + r_dcache_xtn_req = false; + m_drsp.valid = true; + r_icache_fsm = ICACHE_IDLE; } else { - r_icache_fsm = ICACHE_XTN_CACHE_FLUSH; + r_icache_fsm = ICACHE_XTN_CACHE_FLUSH; } break; @@ -1445,50 +1445,49 @@ ////////////////////////// - case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address - // stored in the r_dcache_save_wdata register + case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address + // stored in the r_dcache_save_wdata register { r_itlb.inval(r_dcache_save_wdata.read()); - r_dcache_xtn_req = false; - r_icache_fsm = ICACHE_IDLE; + r_dcache_xtn_req = false; + r_icache_fsm = ICACHE_IDLE; break; } /////////////////////////////// - case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address + case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address // requires 3 cycles (in case of hit on itlb and icache). - // In this state, access TLB to translate virtual address - // stored in the r_dcache_save_wdata register. - { - paddr_t paddr; - bool hit; + // In this state, access TLB to translate virtual address + // stored in the r_dcache_save_wdata register. + { + paddr_t paddr; + bool hit; // read physical address in TLB when MMU activated - if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated + if (r_mmu_mode.read() & INS_TLB_MASK) // itlb activated { #ifdef INSTRUMENTATION -m_cpt_itlb_read++; -#endif - hit = r_itlb.translate(r_dcache_save_wdata.read(), - &paddr); - } - else // itlb not activated - { - paddr = (paddr_t)r_dcache_save_wdata.read(); - hit = true; - } - - if ( hit ) // continue the selective inval process - { - r_icache_vci_paddr = paddr; - r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA; - } - else // miss : send a request to DCACHE FSM + m_cpt_itlb_read++; +#endif + hit = r_itlb.translate(r_dcache_save_wdata.read(), &paddr); + } + else // itlb not activated + { + paddr = (paddr_t) r_dcache_save_wdata.read(); + hit = true; + } + + if (hit) // continue the selective inval process + { + r_icache_vci_paddr = paddr; + r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA; + } + else // miss : send a request to DCACHE FSM { #ifdef INSTRUMENTATION -m_cpt_itlb_miss++; + m_cpt_itlb_miss++; #endif r_icache_tlb_miss_req = true; - r_icache_vaddr_save = r_dcache_save_wdata.read(); + r_icache_vaddr_save = r_dcache_save_wdata.read(); r_icache_fsm = ICACHE_TLB_WAIT; } @@ -1496,15 +1495,15 @@ } /////////////////////////////// - case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address + case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address // require 2 cycles. In this state, we read directory // with address stored in r_icache_vci_paddr register. { - int state; - size_t way; - size_t set; - size_t word; + int state; + size_t way; + size_t set; + size_t word; #ifdef INSTRUMENTATION -m_cpt_icache_dir_read++; + m_cpt_icache_dir_read++; #endif r_icache.read_dir(r_icache_vci_paddr.read(), @@ -1514,5 +1513,5 @@ &word); - if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done + if (state == CACHE_SLOT_STATE_VALID) // inval to be done { r_icache_miss_way = way; @@ -1520,5 +1519,5 @@ r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO; } - else // miss : acknowlege the XTN request and return + else // miss : acknowlege the XTN request and return { r_dcache_xtn_req = false; @@ -1530,23 +1529,23 @@ case ICACHE_XTN_CACHE_INVAL_GO: // Switch slot to ZOMBI state for an XTN inval { - if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request not sent + if (not r_icache_cc_send_req.read()) // blocked until previous cc_send request not sent { #ifdef INSTRUMENTATION -m_cpt_icache_dir_write++; -#endif - r_icache.write_dir( r_icache_miss_way.read(), - r_icache_miss_set.read(), - CACHE_SLOT_STATE_ZOMBI ); + m_cpt_icache_dir_write++; +#endif + r_icache.write_dir(r_icache_miss_way.read(), + r_icache_miss_set.read(), + CACHE_SLOT_STATE_ZOMBI); // request cleanup r_icache_cc_send_req = true; - r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2); + r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words << 2); r_icache_cc_send_way = r_icache_miss_way.read(); r_icache_cc_send_type = CC_TYPE_CLEANUP; // acknowledge the XTN request and return - r_dcache_xtn_req = false; - r_icache_fsm = ICACHE_IDLE; + r_dcache_xtn_req = false; + r_icache_fsm = ICACHE_IDLE; } break; @@ -1566,5 +1565,5 @@ // coherence clack interrupt - if ( r_icache_clack_req.read() ) + if (r_icache_clack_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1574,5 +1573,5 @@ // coherence interrupt - if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) + if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1582,12 +1581,12 @@ - bool found; - bool cleanup; - size_t way; - size_t set; - paddr_t victim; + bool found; + bool cleanup; + size_t way; + size_t set; + paddr_t victim; #ifdef INSTRUMENTATION -m_cpt_icache_dir_read++; + m_cpt_icache_dir_read++; #endif r_icache.read_select(r_icache_vci_paddr.read(), @@ -1596,6 +1595,6 @@ &set, &found, - &cleanup ); - if ( not found ) + &cleanup); + if (not found) { break; @@ -1603,15 +1602,15 @@ else { - r_icache_miss_way = way; - r_icache_miss_set = set; - - if ( cleanup ) - { - if ( not r_icache_cc_send_req.read() ) + r_icache_miss_way = way; + r_icache_miss_set = set; + + if (cleanup) + { + if (not r_icache_cc_send_req.read()) { - r_icache_cc_send_req = true; - r_icache_cc_send_nline = victim; - r_icache_cc_send_way = way; - r_icache_cc_send_type = CC_TYPE_CLEANUP; + r_icache_cc_send_req = true; + r_icache_cc_send_nline = victim; + r_icache_cc_send_way = way; + r_icache_cc_send_type = CC_TYPE_CLEANUP; } else @@ -1621,22 +1620,22 @@ } - r_icache_miss_clack = true; - r_icache_fsm = ICACHE_MISS_CLEAN; + r_icache_miss_clack = true; + r_icache_fsm = ICACHE_MISS_CLEAN; } else { - r_icache_fsm = ICACHE_MISS_WAIT; + r_icache_fsm = ICACHE_MISS_WAIT; } #if DEBUG_ICACHE -if ( m_debug_icache_fsm ) -{ - std::cout << " Select a slot:" << std::dec - << " / WAY = " << way - << " / SET = " << set; - if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl; - else std::cout << std::endl; -} + if (m_debug_icache_fsm) + { + std::cout << " Select a slot:" << std::dec + << " / WAY = " << way + << " / SET = " << set; + if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl; + else std::cout << std::endl; + } #endif } @@ -1644,22 +1643,22 @@ } /////////////////////// - case ICACHE_MISS_CLEAN: // switch the slot to zombi state + case ICACHE_MISS_CLEAN: // switch the slot to zombi state { if (m_ireq.valid) m_cost_ins_miss_frz++; #ifdef INSTRUMENTATION -m_cpt_icache_dir_write++; -#endif - r_icache.write_dir( r_icache_miss_way.read(), - r_icache_miss_set.read(), - CACHE_SLOT_STATE_ZOMBI); + m_cpt_icache_dir_write++; +#endif + r_icache.write_dir(r_icache_miss_way.read(), + r_icache_miss_set.read(), + CACHE_SLOT_STATE_ZOMBI); #if DEBUG_ICACHE -if ( m_debug_icache_fsm ) -{ - std::cout << " Switch to ZOMBI state" << std::dec - << " / WAY = " << r_icache_miss_way.read() - << " / SET = " << r_icache_miss_set.read() << std::endl; -} + if (m_debug_icache_fsm) + { + std::cout << " Switch to ZOMBI state" << std::dec + << " / WAY = " << r_icache_miss_way.read() + << " / SET = " << r_icache_miss_set.read() << std::endl; + } #endif @@ -1668,10 +1667,10 @@ } ////////////////////// - case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM + case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM { if (m_ireq.valid) m_cost_ins_miss_frz++; // send cleanup victim request - if ( r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read() ) + if (r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read()) { r_icache_cc_send_req = true; @@ -1683,5 +1682,5 @@ // coherence clack interrupt - if ( r_icache_clack_req.read() ) + if (r_icache_clack_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1691,5 +1690,5 @@ // coherence interrupt - if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read() ) + if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1698,5 +1697,5 @@ } - if ( r_vci_rsp_ins_error.read() ) // bus error + if (r_vci_rsp_ins_error.read()) // bus error { r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS; @@ -1707,5 +1706,5 @@ r_icache_fsm = ICACHE_IDLE; } - else if ( r_vci_rsp_fifo_icache.rok() ) // response available + else if (r_vci_rsp_fifo_icache.rok()) // response available { r_icache_miss_word = 0; @@ -1715,33 +1714,33 @@ } /////////////////////////// - case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle) - { - if ( m_ireq.valid ) m_cost_ins_miss_frz++; - - if ( r_vci_rsp_fifo_icache.rok() ) // response available + case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle) + { + if (m_ireq.valid) m_cost_ins_miss_frz++; + + if (r_vci_rsp_fifo_icache.rok()) // response available { #ifdef INSTRUMENTATION -m_cpt_icache_data_write++; -#endif - r_icache.write( r_icache_miss_way.read(), - r_icache_miss_set.read(), - r_icache_miss_word.read(), - r_vci_rsp_fifo_icache.read() ); + m_cpt_icache_data_write++; +#endif + r_icache.write(r_icache_miss_way.read(), + r_icache_miss_set.read(), + r_icache_miss_word.read(), + r_vci_rsp_fifo_icache.read()); #if DEBUG_ICACHE -if ( m_debug_icache_fsm ) -{ - std::cout << " Write one word:" - << " WDATA = " << std::hex << r_vci_rsp_fifo_icache.read() - << " WAY = " << r_icache_miss_way.read() - << " SET = " << r_icache_miss_set.read() - << " WORD = " << r_icache_miss_word.read() << std::endl; -} + if (m_debug_icache_fsm) + { + std::cout << " Write one word:" + << " WDATA = " << std::hex << r_vci_rsp_fifo_icache.read() + << " WAY = " << r_icache_miss_way.read() + << " SET = " << r_icache_miss_set.read() + << " WORD = " << r_icache_miss_word.read() << std::endl; + } #endif vci_rsp_fifo_icache_get = true; r_icache_miss_word = r_icache_miss_word.read() + 1; - if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word + if (r_icache_miss_word.read() == m_icache_words - 1) // last word { r_icache_fsm = ICACHE_MISS_DIR_UPDT; @@ -1751,5 +1750,5 @@ } ////////////////////////// - case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted, + case ICACHE_MISS_DIR_UPDT: // Stalled if a victim line has been evicted, // and the cleanup ack has not been received, // as indicated by r_icache_miss_clack. @@ -1759,8 +1758,8 @@ // to ZOMBI state, and send a cleanup request. { - if ( m_ireq.valid ) m_cost_ins_miss_frz++; + if (m_ireq.valid ) m_cost_ins_miss_frz++; // send cleanup victim request - if ( r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read() ) + if (r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read()) { r_icache_cc_send_req = true; @@ -1772,5 +1771,5 @@ // coherence clack interrupt - if ( r_icache_clack_req.read() ) + if (r_icache_clack_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1780,5 +1779,5 @@ // coherence interrupt - if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read() ) + if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1787,33 +1786,33 @@ } - if ( not r_icache_miss_clack.read() ) // waiting cleanup acknowledge for victim line - { - if ( r_icache_miss_inval ) // Switch slot to ZOMBI state, and new cleanup - { - if ( not r_icache_cc_send_req.read() ) + if (not r_icache_miss_clack.read()) // waiting cleanup acknowledge for victim line + { + if (r_icache_miss_inval) // Switch slot to ZOMBI state, and new cleanup + { + if (not r_icache_cc_send_req.read()) { r_icache_miss_inval = false; // request cleanup r_icache_cc_send_req = true; - r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2); + r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words << 2); r_icache_cc_send_way = r_icache_miss_way.read(); r_icache_cc_send_type = CC_TYPE_CLEANUP; #ifdef INSTRUMENTATION -m_cpt_icache_dir_write++; -#endif - r_icache.write_dir( r_icache_vci_paddr.read(), - r_icache_miss_way.read(), - r_icache_miss_set.read(), - CACHE_SLOT_STATE_ZOMBI ); + m_cpt_icache_dir_write++; +#endif + r_icache.write_dir(r_icache_vci_paddr.read(), + r_icache_miss_way.read(), + r_icache_miss_set.read(), + CACHE_SLOT_STATE_ZOMBI); #if DEBUG_ICACHE -if ( m_debug_icache_fsm ) -{ - std::cout << " Switch cache slot to ZOMBI state" - << " PADDR = " << std::hex << r_icache_vci_paddr.read() - << " WAY = " << std::dec << r_icache_miss_way.read() - << " SET = " << r_icache_miss_set.read() << std::endl; -} + if (m_debug_icache_fsm) + { + std::cout << " Switch cache slot to ZOMBI state" + << " PADDR = " << std::hex << r_icache_vci_paddr.read() + << " WAY = " << std::dec << r_icache_miss_way.read() + << " SET = " << r_icache_miss_set.read() << std::endl; + } #endif } @@ -1821,23 +1820,23 @@ break; } - else // Switch slot to VALID state + else // Switch slot to VALID state { #ifdef INSTRUMENTATION -m_cpt_icache_dir_write++; -#endif - r_icache.write_dir( r_icache_vci_paddr.read(), - r_icache_miss_way.read(), - r_icache_miss_set.read(), - CACHE_SLOT_STATE_VALID ); + m_cpt_icache_dir_write++; +#endif + r_icache.write_dir(r_icache_vci_paddr.read(), + r_icache_miss_way.read(), + r_icache_miss_set.read(), + CACHE_SLOT_STATE_VALID); #if DEBUG_ICACHE -if ( m_debug_icache_fsm ) -{ - std::cout << " Switch cache slot to VALID state" - << " PADDR = " << std::hex << r_icache_vci_paddr.read() - << " WAY = " << std::dec << r_icache_miss_way.read() - << " SET = " << r_icache_miss_set.read() << std::endl; -} + if (m_debug_icache_fsm) + { + std::cout << " Switch cache slot to VALID state" + << " PADDR = " << std::hex << r_icache_vci_paddr.read() + << " WAY = " << std::dec << r_icache_miss_way.read() + << " SET = " << r_icache_miss_set.read() << std::endl; + } #endif } @@ -1848,10 +1847,10 @@ } //////////////////// - case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM + case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM { // coherence clack interrupt - if ( r_icache_clack_req.read() ) - { - r_icache_fsm = ICACHE_CC_CHECK; + if (r_icache_clack_req.read()) + { + r_icache_fsm = ICACHE_CC_CHECK; r_icache_fsm_save = r_icache_fsm.read(); break; @@ -1859,12 +1858,12 @@ // coherence interrupt - if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) - { - r_icache_fsm = ICACHE_CC_CHECK; + if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) + { + r_icache_fsm = ICACHE_CC_CHECK; r_icache_fsm_save = r_icache_fsm.read(); break; } - if ( r_vci_rsp_ins_error.read() ) // bus error + if (r_vci_rsp_ins_error.read()) // bus error { r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS; @@ -1875,10 +1874,10 @@ r_icache_fsm = ICACHE_IDLE; } - else if (r_vci_rsp_fifo_icache.rok() ) // instruction available + else if (r_vci_rsp_fifo_icache.rok()) // instruction available { vci_rsp_fifo_icache_get = true; r_icache_fsm = ICACHE_IDLE; - if ( m_ireq.valid and - (m_ireq.addr == r_icache_vaddr_save.read()) ) // request unmodified + if (m_ireq.valid and + (m_ireq.addr == r_icache_vaddr_save.read())) // request unmodified { m_irsp.valid = true; @@ -1889,12 +1888,12 @@ } ///////////////////// - case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm - // handling coherence requests. - // if there is a matching pending miss, it is - // signaled in the r_icache_miss_inval flip-flop. - // The return state is defined in r_icache_fsm_save. - { - paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4; - paddr_t mask = ~((m_icache_words<<2)-1); + case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm + // handling coherence requests. + // if there is a matching pending miss, it is + // signaled in the r_icache_miss_inval flip-flop. + // The return state is defined in r_icache_fsm_save. + { + paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4; + paddr_t mask = ~((m_icache_words << 2) - 1); // CLACK handler @@ -1902,19 +1901,19 @@ // and reset r_icache_miss_clack if the cleanup ack // is matching a pending miss. - if ( r_icache_clack_req.read() ) - { - - if ( m_ireq.valid ) m_cost_ins_miss_frz++; + if (r_icache_clack_req.read()) + { + + if (m_ireq.valid) m_cost_ins_miss_frz++; #ifdef INSTRUMENTATION -m_cpt_icache_dir_write++; -#endif - r_icache.write_dir( 0, - r_icache_clack_way.read(), - r_icache_clack_set.read(), - CACHE_SLOT_STATE_EMPTY); - - if ( (r_icache_miss_set.read() == r_icache_clack_set.read()) and - (r_icache_miss_way.read() == r_icache_clack_way.read()) ) + m_cpt_icache_dir_write++; +#endif + r_icache.write_dir(0, + r_icache_clack_way.read(), + r_icache_clack_set.read(), + CACHE_SLOT_STATE_EMPTY); + + if ((r_icache_miss_set.read() == r_icache_clack_set.read()) and + (r_icache_miss_way.read() == r_icache_clack_way.read())) { r_icache_miss_clack = false; @@ -1927,27 +1926,27 @@ #if DEBUG_ICACHE -if ( m_debug_icache_fsm ) -{ - std::cout << " CC_TYPE_CLACK slot returns to empty state" - << " set = " << r_icache_clack_set.read() - << " / way = " << r_icache_clack_way.read() << std::endl; -} -#endif - - break; - } - - assert ( not r_icache_cc_send_req.read() and "CC_SEND must be available in ICACHE_CC_CHECK"); + if (m_debug_icache_fsm) + { + std::cout << " CC_TYPE_CLACK slot returns to empty state" + << " set = " << r_icache_clack_set.read() + << " / way = " << r_icache_clack_way.read() << std::endl; + } +#endif + + break; + } + + assert(not r_icache_cc_send_req.read() and "CC_SEND must be available in ICACHE_CC_CHECK"); // Match between MISS address and CC address if (r_cc_receive_icache_req.read() and - ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT ) or - (r_icache_fsm_save.read() == ICACHE_MISS_WAIT ) or + ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT) or + (r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or (r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and - ((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching + ((r_icache_vci_paddr.read() & mask) == (paddr & mask))) // matching { // signaling the matching - r_icache_miss_inval = true; + r_icache_miss_inval = true; // in case of update, go to CC_UPDT @@ -1955,6 +1954,6 @@ if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) { - r_icache_fsm = ICACHE_CC_UPDT; - r_icache_cc_word = r_cc_receive_word_idx.read(); + r_icache_fsm = ICACHE_CC_UPDT; + r_icache_cc_word = r_cc_receive_word_idx.read(); // just pop the fifo , don't write in icache @@ -1965,13 +1964,13 @@ { r_cc_receive_icache_req = false; - r_icache_fsm = r_icache_fsm_save.read(); + r_icache_fsm = r_icache_fsm_save.read(); } #if DEBUG_ICACHE -if ( m_debug_icache_fsm ) -{ - std::cout << " Coherence request matching a pending miss:" - << " PADDR = " << std::hex << paddr << std::endl; -} + if (m_debug_icache_fsm) + { + std::cout << " Coherence request matching a pending miss:" + << " PADDR = " << std::hex << paddr << std::endl; + } #endif } @@ -1979,11 +1978,11 @@ // CC request handler - int state = 0; - size_t way = 0; - size_t set = 0; - size_t word = 0; + int state = 0; + size_t way = 0; + size_t set = 0; + size_t word = 0; #ifdef INSTRUMENTATION -m_cpt_icache_dir_read++; + m_cpt_icache_dir_read++; #endif r_icache.read_dir(paddr, @@ -1996,5 +1995,5 @@ r_icache_cc_set = set; - if ( state == CACHE_SLOT_STATE_VALID) // hit + if (state == CACHE_SLOT_STATE_VALID) // hit { // need to update the cache state @@ -2002,10 +2001,10 @@ { r_icache_cc_need_write = true; - r_icache_fsm = ICACHE_CC_UPDT; - r_icache_cc_word = r_cc_receive_word_idx.read(); - } - else if ( r_cc_receive_icache_type.read() == CC_TYPE_INVAL ) // hit inval - { - r_icache_fsm = ICACHE_CC_INVAL; + r_icache_fsm = ICACHE_CC_UPDT; + r_icache_cc_word = r_cc_receive_word_idx.read(); + } + else if (r_cc_receive_icache_type.read() == CC_TYPE_INVAL) // hit inval + { + r_icache_fsm = ICACHE_CC_INVAL; } } @@ -2013,8 +2012,8 @@ { // multicast acknowledgement required in case of update - if(r_cc_receive_icache_type.read() == CC_TYPE_UPDT) - { - r_icache_fsm = ICACHE_CC_UPDT; - r_icache_cc_word = r_cc_receive_word_idx.read(); + if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) + { + r_icache_fsm = ICACHE_CC_UPDT; + r_icache_cc_word = r_cc_receive_word_idx.read(); // just pop the fifo , don't write in icache @@ -2024,5 +2023,5 @@ { r_cc_receive_icache_req = false; - r_icache_fsm = r_icache_fsm_save.read(); + r_icache_fsm = r_icache_fsm_save.read(); } } @@ -2030,5 +2029,5 @@ } ///////////////////// - case ICACHE_CC_INVAL: // hit inval : switch slot to ZOMBI state + case ICACHE_CC_INVAL: // hit inval : switch slot to ZOMBI state { assert (not r_icache_cc_send_req.read() && @@ -2037,11 +2036,11 @@ #ifdef INSTRUMENTATION -m_cpt_icache_dir_read++; + m_cpt_icache_dir_read++; #endif // Switch slot state to ZOMBI and send CLEANUP command - r_icache.write_dir( r_icache_cc_way.read(), - r_icache_cc_set.read(), - CACHE_SLOT_STATE_ZOMBI ); + r_icache.write_dir(r_icache_cc_way.read(), + r_icache_cc_set.read(), + CACHE_SLOT_STATE_ZOMBI); // coherence request completed @@ -2051,14 +2050,14 @@ r_icache_cc_send_type = CC_TYPE_CLEANUP; - r_icache_fsm = r_icache_fsm_save.read(); + r_icache_fsm = r_icache_fsm_save.read(); #if DEBUG_ICACHE -if ( m_debug_icache_fsm ) -{ -std::cout << " slot returns to ZOMBI state" - << " set = " << r_icache_cc_set.read() - << " / way = " << r_icache_cc_way.read() << std::endl; -} + if (m_debug_icache_fsm) + { + std::cout << " slot returns to ZOMBI state" + << " set = " << r_icache_cc_set.read() + << " / way = " << r_icache_cc_way.read() << std::endl; + } #endif @@ -2066,5 +2065,5 @@ } //////////////////// - case ICACHE_CC_UPDT: // hit update : write one word per cycle + case ICACHE_CC_UPDT: // hit update : write one word per cycle { assert (not r_icache_cc_send_req.read() && @@ -2072,44 +2071,44 @@ "must not be set"); - if ( not r_cc_receive_updt_fifo_be.rok() ) break; - - - size_t word = r_icache_cc_word.read(); - size_t way = r_icache_cc_way.read(); - size_t set = r_icache_cc_set.read(); + if (not r_cc_receive_updt_fifo_be.rok()) break; + + + size_t word = r_icache_cc_word.read(); + size_t way = r_icache_cc_way.read(); + size_t set = r_icache_cc_set.read(); if (r_icache_cc_need_write.read()) { - r_icache.write( way, - set, - word, - r_cc_receive_updt_fifo_data.read(), - r_cc_receive_updt_fifo_be.read() ); - - r_icache_cc_word = word+1; + r_icache.write(way, + set, + word, + r_cc_receive_updt_fifo_data.read(), + r_cc_receive_updt_fifo_be.read()); + + r_icache_cc_word = word + 1; #ifdef INSTRUMENTATION -m_cpt_icache_data_write++; + m_cpt_icache_data_write++; #endif #if DEBUG_ICACHE -if ( m_debug_icache_fsm ) -{ - std::cout << " Write one word " - << " set = " << r_icache_cc_set.read() - << " / way = " << r_icache_cc_way.read() - << " / word = " << r_icache_cc_word.read() << std::endl; -} -#endif - } - - if ( r_cc_receive_updt_fifo_eop.read() ) // last word + if (m_debug_icache_fsm) + { + std::cout << " Write one word " + << " set = " << r_icache_cc_set.read() + << " / way = " << r_icache_cc_way.read() + << " / word = " << r_icache_cc_word.read() << std::endl; + } +#endif + } + + if (r_cc_receive_updt_fifo_eop.read()) // last word { // no need to write in the cache anymore - r_icache_cc_need_write = false; + r_icache_cc_need_write = false; // coherence request completed - r_cc_receive_icache_req = false; + r_cc_receive_icache_req = false; // request multicast acknowledgement @@ -2119,8 +2118,8 @@ r_icache_cc_send_type = CC_TYPE_MULTI_ACK; - r_icache_fsm = r_icache_fsm_save.read(); + r_icache_fsm = r_icache_fsm_save.read(); } //consume fifo if not eop - cc_receive_updt_fifo_get = true; + cc_receive_updt_fifo_get = true; break; @@ -2207,5 +2206,5 @@ m_drsp.rdata = 0; - switch ( r_dcache_fsm.read() ) + switch (r_dcache_fsm.read()) { case DCACHE_IDLE: // There are 10 conditions to exit the IDLE state : @@ -2244,90 +2243,90 @@ // updt_request, wbuf_request, wbuf_write_miss. { - paddr_t paddr; - pte_info_t tlb_flags; - size_t tlb_way; - size_t tlb_set; - paddr_t tlb_nline = 0; - size_t cache_way; - size_t cache_set; - size_t cache_word; - uint32_t cache_rdata = 0; - bool tlb_hit = false; - int cache_state = CACHE_SLOT_STATE_EMPTY; - - bool tlb_inval_required = false; // request TLB inval after cache update - bool wbuf_write_miss = false; // miss a WBUF write request - bool updt_request = false; // request DCACHE update in P1 stage - bool wbuf_request = false; // request WBUF write in P1 stage - - // physical address computation : systematic DTLB access if activated) + paddr_t paddr; + pte_info_t tlb_flags; + size_t tlb_way; + size_t tlb_set; + paddr_t tlb_nline = 0; + size_t cache_way; + size_t cache_set; + size_t cache_word; + uint32_t cache_rdata = 0; + bool tlb_hit = false; + int cache_state = CACHE_SLOT_STATE_EMPTY; + + bool tlb_inval_required = false; // request TLB inval after cache update + bool wbuf_write_miss = false; // miss a WBUF write request + bool updt_request = false; // request DCACHE update in P1 stage + bool wbuf_request = false; // request WBUF write in P1 stage + + // physical address computation : systematic DTLB access if activated paddr = (paddr_t) m_dreq.addr; - if ( m_dreq.valid ) - { - if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated - { - tlb_hit = r_dtlb.translate( m_dreq.addr, - &paddr, - &tlb_flags, - &tlb_nline, - &tlb_way, - &tlb_set ); + if (m_dreq.valid) + { + if (r_mmu_mode.read() & DATA_TLB_MASK) // DTLB activated + { + tlb_hit = r_dtlb.translate(m_dreq.addr, + &paddr, + &tlb_flags, + &tlb_nline, + &tlb_way, + &tlb_set); #ifdef INSTRUMENTATION -m_cpt_dtlb_read++; -#endif - } - else // identity mapping + m_cpt_dtlb_read++; +#endif + } + else // identity mapping { // we take into account the paddr extension if (vci_param::N > 32) - paddr = paddr | ((paddr_t)(r_dcache_paddr_ext.read()) << 32); + paddr = paddr | ((paddr_t) (r_dcache_paddr_ext.read()) << 32); } } // end physical address computation // systematic DCACHE access depending on r_dcache_updt_req (if activated) - if ( r_mmu_mode.read() & DATA_CACHE_MASK) - { - - if ( m_dreq.valid and r_dcache_updt_req.read() ) // read DIR and write DATA - { - r_dcache.read_dir( paddr, - &cache_state, - &cache_way, - &cache_set, - &cache_word ); - - r_dcache.write( r_dcache_save_cache_way.read(), - r_dcache_save_cache_set.read(), - r_dcache_save_cache_word.read(), - r_dcache_save_wdata.read(), - r_dcache_save_be.read() ); + if (r_mmu_mode.read() & DATA_CACHE_MASK) + { + + if (m_dreq.valid and r_dcache_updt_req.read()) // read DIR and write DATA + { + r_dcache.read_dir(paddr, + &cache_state, + &cache_way, + &cache_set, + &cache_word); + + r_dcache.write(r_dcache_save_cache_way.read(), + r_dcache_save_cache_set.read(), + r_dcache_save_cache_word.read(), + r_dcache_save_wdata.read(), + r_dcache_save_be.read()); #ifdef INSTRUMENTATION -m_cpt_dcache_dir_read++; -m_cpt_dcache_data_write++; -#endif - } - else if ( m_dreq.valid and not r_dcache_updt_req.read() ) // read DIR and DATA - { - r_dcache.read( paddr, - &cache_rdata, - &cache_way, - &cache_set, - &cache_word, - &cache_state ); + m_cpt_dcache_dir_read++; + m_cpt_dcache_data_write++; +#endif + } + else if (m_dreq.valid and not r_dcache_updt_req.read()) // read DIR and DATA + { + r_dcache.read(paddr, + &cache_rdata, + &cache_way, + &cache_set, + &cache_word, + &cache_state); #ifdef INSTRUMENTATION -m_cpt_dcache_dir_read++; -m_cpt_dcache_data_read++; -#endif - } - else if ( not m_dreq.valid and r_dcache_updt_req.read() ) // write DATA - { - r_dcache.write( r_dcache_save_cache_way.read(), - r_dcache_save_cache_set.read(), - r_dcache_save_cache_word.read(), - r_dcache_save_wdata.read(), - r_dcache_save_be.read() ); + m_cpt_dcache_dir_read++; + m_cpt_dcache_data_read++; +#endif + } + else if (not m_dreq.valid and r_dcache_updt_req.read()) // write DATA + { + r_dcache.write(r_dcache_save_cache_way.read(), + r_dcache_save_cache_set.read(), + r_dcache_save_cache_word.read(), + r_dcache_save_wdata.read(), + r_dcache_save_be.read()); #ifdef INSTRUMENTATION -m_cpt_dcache_data_write++; + m_cpt_dcache_data_write++; #endif } @@ -2335,33 +2334,33 @@ // DCACHE update in P1 stage can require ITLB / DTLB inval or flush - if ( r_dcache_updt_req.read() ) + if (r_dcache_updt_req.read()) { size_t way = r_dcache_save_cache_way.read(); size_t set = r_dcache_save_cache_set.read(); - if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) - { - tlb_inval_required = true; - r_dcache_tlb_inval_set = 0; - r_dcache_tlb_inval_line = r_dcache_save_paddr.read()>> - (uint32_log2(m_dcache_words<<2)); - r_dcache_in_tlb[way*m_dcache_sets+set] = false; - } - else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) + if (r_dcache_in_tlb[way * m_dcache_sets + set]) + { + tlb_inval_required = true; + r_dcache_tlb_inval_set = 0; + r_dcache_tlb_inval_line = r_dcache_save_paddr.read() >> + (uint32_log2(m_dcache_words << 2)); + r_dcache_in_tlb[way * m_dcache_sets + set] = false; + } + else if (r_dcache_contains_ptd[way * m_dcache_sets + set]) { r_itlb.reset(); r_dtlb.reset(); - r_dcache_contains_ptd[way*m_dcache_sets+set] = false; + r_dcache_contains_ptd[way * m_dcache_sets + set] = false; } #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -std::cout << " " - << " Cache update in P1 stage" << std::dec - << " / WAY = " << r_dcache_save_cache_way.read() - << " / SET = " << r_dcache_save_cache_set.read() - << " / WORD = " << r_dcache_save_cache_word.read() << std::hex - << " / WDATA = " << r_dcache_save_wdata.read() - << " / BE = " << r_dcache_save_be.read() << std::endl; + if (m_debug_dcache_fsm) + std::cout << " " + << " Cache update in P1 stage" << std::dec + << " / WAY = " << r_dcache_save_cache_way.read() + << " / SET = " << r_dcache_save_cache_set.read() + << " / WORD = " << r_dcache_save_cache_word.read() << std::hex + << " / WDATA = " << r_dcache_save_wdata.read() + << " / BE = " << r_dcache_save_be.read() << std::endl; #endif } // end test TLB inval @@ -2370,14 +2369,14 @@ // Miss if the write request is non cacheable, and there is a pending // non cacheable write, or if the write buffer is full. - if ( r_dcache_wbuf_req.read() ) - { - bool wok = r_wbuf.write( r_dcache_save_paddr.read(), - r_dcache_save_be.read(), - r_dcache_save_wdata.read(), - true); + if (r_dcache_wbuf_req.read()) + { + bool wok = r_wbuf.write(r_dcache_save_paddr.read(), + r_dcache_save_be.read(), + r_dcache_save_wdata.read(), + true); #ifdef INSTRUMENTATION -m_cpt_wbuf_write++; -#endif - if ( not wok ) // miss if write buffer full + m_cpt_wbuf_write++; +#endif + if (not wok ) // miss if write buffer full { wbuf_write_miss = true; @@ -2389,5 +2388,5 @@ // itlb/dtlb invalidation self-request - if ( tlb_inval_required ) + if (tlb_inval_required) { r_dcache_fsm_scan_save = r_dcache_fsm.read(); @@ -2396,5 +2395,5 @@ // coherence clack request (from DSPIN CLACK) - else if ( r_dcache_clack_req.read() ) + else if (r_dcache_clack_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -2402,5 +2401,5 @@ } // coherence request (from CC_RECEIVE FSM) - else if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + else if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -2411,5 +2410,5 @@ // we don't take the processor request, and registers // are frozen in case of wbuf_write_miss - else if ( m_dreq.valid and not wbuf_write_miss ) + else if (m_dreq.valid and not wbuf_write_miss) { // register processor request and DCACHE response @@ -2427,5 +2426,5 @@ if (m_dreq.type == iss_t::XTN_READ) { - int xtn_opcode = (int)m_dreq.addr/4; + int xtn_opcode = (int)m_dreq.addr / 4; // checking processor mode: @@ -2441,5 +2440,5 @@ else { - switch( xtn_opcode ) + switch (xtn_opcode) { case iss_t::XTN_INS_ERROR_TYPE: @@ -2516,5 +2515,5 @@ default: - r_mmu_detr = MMU_READ_UNDEFINED_XTN; + r_mmu_detr = MMU_READ_UNDEFINED_XTN; r_mmu_dbvar = m_dreq.addr; m_drsp.valid = true; @@ -2534,14 +2533,14 @@ else if (m_dreq.type == iss_t::XTN_WRITE) { - int xtn_opcode = (int)m_dreq.addr/4; + int xtn_opcode = (int)m_dreq.addr / 4; r_dcache_xtn_opcode = xtn_opcode; // checking processor mode: - if ( (m_dreq.mode == iss_t::MODE_USER) && + if ((m_dreq.mode == iss_t::MODE_USER) && (xtn_opcode != iss_t::XTN_SYNC) && (xtn_opcode != iss_t::XTN_DCACHE_INVAL) && (xtn_opcode != iss_t::XTN_DCACHE_FLUSH) && (xtn_opcode != iss_t::XTN_ICACHE_INVAL) && - (xtn_opcode != iss_t::XTN_ICACHE_FLUSH) ) + (xtn_opcode != iss_t::XTN_ICACHE_FLUSH)) { r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION; @@ -2554,32 +2553,32 @@ else { - switch( xtn_opcode ) + switch (xtn_opcode) { - case iss_t::XTN_PTPR: // itlb & dtlb must be flushed + case iss_t::XTN_PTPR: // itlb & dtlb must be flushed r_dcache_xtn_req = true; r_dcache_fsm = DCACHE_XTN_SWITCH; break; - case iss_t::XTN_TLB_MODE: // no cache or tlb access - r_mmu_mode = m_dreq.wdata; - m_drsp.valid = true; - r_dcache_fsm = DCACHE_IDLE; + case iss_t::XTN_TLB_MODE: // no cache or tlb access + r_mmu_mode = m_dreq.wdata; + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; break; - case iss_t::XTN_DTLB_INVAL: // dtlb access - r_dcache_fsm = DCACHE_XTN_DT_INVAL; + case iss_t::XTN_DTLB_INVAL: // dtlb access + r_dcache_fsm = DCACHE_XTN_DT_INVAL; break; - case iss_t::XTN_ITLB_INVAL: // itlb access + case iss_t::XTN_ITLB_INVAL: // itlb access r_dcache_xtn_req = true; r_dcache_fsm = DCACHE_XTN_IT_INVAL; break; - case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access - r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA; + case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access + r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA; break; - case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access - r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA; + case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access + r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA; if (sizeof(paddr_t) <= 32) { @@ -2595,47 +2594,47 @@ break; - case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset + case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset r_dcache_flush_count = 0; - r_dcache_fsm = DCACHE_XTN_DC_FLUSH; + r_dcache_fsm = DCACHE_XTN_DC_FLUSH; break; - case iss_t::XTN_ICACHE_INVAL: // icache and itlb access + case iss_t::XTN_ICACHE_INVAL: // icache and itlb access r_dcache_xtn_req = true; r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA; break; - case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access + case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access r_dcache_xtn_req = true; r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA; break; - case iss_t::XTN_ICACHE_FLUSH: // icache access + case iss_t::XTN_ICACHE_FLUSH: // icache access r_dcache_xtn_req = true; r_dcache_fsm = DCACHE_XTN_IC_FLUSH; break; - case iss_t::XTN_SYNC: // wait until write buffer empty - r_dcache_fsm = DCACHE_XTN_SYNC; + case iss_t::XTN_SYNC: // wait until write buffer empty + r_dcache_fsm = DCACHE_XTN_SYNC; break; - case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access - r_mmu_word_lo = m_dreq.wdata; - m_drsp.valid = true; - r_dcache_fsm = DCACHE_IDLE; + case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access + r_mmu_word_lo = m_dreq.wdata; + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; break; - case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access - r_mmu_word_hi = m_dreq.wdata; - m_drsp.valid = true; - r_dcache_fsm = DCACHE_IDLE; + case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access + r_mmu_word_hi = m_dreq.wdata; + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; break; - case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access + case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access r_dcache_llsc_valid = false; - m_drsp.valid = true; - r_dcache_fsm = DCACHE_IDLE; + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; break; - case iss_t::XTN_DATA_PADDR_EXT: // no cache or tlb access + case iss_t::XTN_DATA_PADDR_EXT: // no cache or tlb access r_dcache_paddr_ext = m_dreq.wdata; m_drsp.valid = true; @@ -2643,13 +2642,13 @@ break; - case iss_t::XTN_INST_PADDR_EXT: // no cache or tlb access + case iss_t::XTN_INST_PADDR_EXT: // no cache or tlb access r_dcache_xtn_req = true; r_dcache_fsm = DCACHE_XTN_IC_PADDR_EXT; break; - case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action - case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action - m_drsp.valid = true; - r_dcache_fsm = DCACHE_IDLE; + case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action + case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; break; @@ -2683,27 +2682,27 @@ else { - bool valid_req; - bool cacheable; - - if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated + bool valid_req; + bool cacheable; + + if (not (r_mmu_mode.read() & DATA_TLB_MASK)) // dtlb not activated { - valid_req = true; - - if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false; + valid_req = true; + + if (not (r_mmu_mode.read() & DATA_CACHE_MASK)) cacheable = false; else cacheable = m_cacheability_table[(uint64_t)m_dreq.addr]; } - else // dtlb activated + else // dtlb activated { - if ( tlb_hit ) // tlb hit + if (tlb_hit) // tlb hit { // cacheability - if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false; + if (not (r_mmu_mode.read() & DATA_CACHE_MASK)) cacheable = false; else cacheable = tlb_flags.c; // access rights checking - if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER)) + if (not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER)) { - if ( (m_dreq.type == iss_t::DATA_READ) or - (m_dreq.type == iss_t::DATA_LL) ) + if ((m_dreq.type == iss_t::DATA_READ) or + (m_dreq.type == iss_t::DATA_LL)) { r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION; @@ -2719,12 +2718,12 @@ m_drsp.rdata = 0; #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -std::cout << " " - << " HIT in dtlb, but privilege violation" << std::endl; + if (m_debug_dcache_fsm) + std::cout << " " + << " HIT in dtlb, but privilege violation" << std::endl; #endif } - else if ( not tlb_flags.w and + else if (not tlb_flags.w and ((m_dreq.type == iss_t::DATA_WRITE) or - (m_dreq.type == iss_t::DATA_SC)) ) + (m_dreq.type == iss_t::DATA_SC))) { r_mmu_detr = MMU_WRITE_ACCES_VIOLATION; @@ -2735,24 +2734,24 @@ m_drsp.rdata = 0; #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -std::cout << " " - << " HIT in dtlb, but writable violation" << std::endl; + if (m_debug_dcache_fsm) + std::cout << " " + << " HIT in dtlb, but writable violation" << std::endl; #endif } else { - valid_req = true; + valid_req = true; } } - else // tlb miss + else // tlb miss { - valid_req = false; - r_dcache_tlb_vaddr = m_dreq.addr; - r_dcache_tlb_ins = false; - r_dcache_fsm = DCACHE_TLB_MISS; + valid_req = false; + r_dcache_tlb_vaddr = m_dreq.addr; + r_dcache_tlb_ins = false; + r_dcache_fsm = DCACHE_TLB_MISS; } } // end DTLB activated - if ( valid_req ) // processor request is valid (after MMU check) + if (valid_req) // processor request is valid (after MMU check) { // READ request @@ -2760,13 +2759,13 @@ // We request a VCI transaction to CMD FSM if miss or uncachable - if ( ((m_dreq.type == iss_t::DATA_READ)) - and not r_dcache_updt_req.read() ) + if (((m_dreq.type == iss_t::DATA_READ)) + and not r_dcache_updt_req.read()) { - if ( cacheable ) // cacheable read + if (cacheable) // cacheable read { - if ( cache_state == CACHE_SLOT_STATE_EMPTY ) // cache miss + if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss { #ifdef INSTRUMENTATION -m_cpt_dcache_miss++; + m_cpt_dcache_miss++; #endif // request a VCI DMISS transaction @@ -2776,19 +2775,19 @@ r_dcache_fsm = DCACHE_MISS_SELECT; #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -std::cout << " " - << " READ MISS in dcache" - << " / PADDR = " << std::hex << paddr << std::endl; + if (m_debug_dcache_fsm) + std::cout << " " + << " READ MISS in dcache" + << " / PADDR = " << std::hex << paddr << std::endl; #endif } - else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup + else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup { // stalled until cleanup is acknowledged r_dcache_fsm = DCACHE_IDLE; #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -std::cout << " " - << " Pending cleanup, stalled until cleanup acknowledge" - << " / PADDR = " << std::hex << paddr << std::endl; + if (m_debug_dcache_fsm) + std::cout << " " + << " Pending cleanup, stalled until cleanup acknowledge" + << " / PADDR = " << std::hex << paddr << std::endl; #endif } @@ -2796,31 +2795,31 @@ { #ifdef INSTRUMENTATION -m_cpt_data_read++; + m_cpt_data_read++; #endif // returns data to processor - m_drsp.valid = true; - m_drsp.error = false; - m_drsp.rdata = cache_rdata; + m_drsp.valid = true; + m_drsp.error = false; + m_drsp.rdata = cache_rdata; #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -std::cout << " " - << " READ HIT in dcache" - << " : PADDR = " << std::hex << paddr - << " / DATA = " << std::hex << cache_rdata << std::endl; + if (m_debug_dcache_fsm) + std::cout << " " + << " READ HIT in dcache" + << " : PADDR = " << std::hex << paddr + << " / DATA = " << std::hex << cache_rdata << std::endl; #endif } } - else // uncacheable read + else // uncacheable read { - r_dcache_vci_paddr = paddr; - r_dcache_vci_unc_be = m_dreq.be; - r_dcache_vci_unc_write = false; - r_dcache_vci_unc_req = true; - r_dcache_fsm = DCACHE_UNC_WAIT; + r_dcache_vci_paddr = paddr; + r_dcache_vci_unc_be = m_dreq.be; + r_dcache_vci_unc_write = false; + r_dcache_vci_unc_req = true; + r_dcache_fsm = DCACHE_UNC_WAIT; #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -std::cout << " " - << " READ UNCACHEABLE in dcache" - << " / PADDR = " << std::hex << paddr << std::endl; + if (m_debug_dcache_fsm) + std::cout << " " + << " READ UNCACHEABLE in dcache" + << " / PADDR = " << std::hex << paddr << std::endl; #endif } @@ -2853,45 +2852,45 @@ // physical address) are registered in r_dcache_save registers, // and the write will be done in the P1 pipeline stage. - else if ( m_dreq.type == iss_t::DATA_WRITE ) + else if (m_dreq.type == iss_t::DATA_WRITE) { - if ( (r_mmu_mode.read() & DATA_TLB_MASK ) - and not tlb_flags.d ) // Dirty bit must be set + if ((r_mmu_mode.read() & DATA_TLB_MASK) + and not tlb_flags.d) // Dirty bit must be set { // The PTE physical address is obtained from the nline value (dtlb), // and from the virtual address (word index) - if ( tlb_flags.b ) // PTE1 + if (tlb_flags.b ) // PTE1 { - r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) | - (paddr_t)((m_dreq.addr>>19) & 0x3c); + r_dcache_dirty_paddr = (paddr_t)(tlb_nline * (m_dcache_words << 2)) | + (paddr_t)((m_dreq.addr >> 19) & 0x3c); } - else // PTE2 + else // PTE2 { - r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) | - (paddr_t)((m_dreq.addr>>9) & 0x38); + r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) | + (paddr_t) ((m_dreq.addr >> 9) & 0x38); } - r_dcache_fsm = DCACHE_DIRTY_GET_PTE; + r_dcache_fsm = DCACHE_DIRTY_GET_PTE; } - else // Write request accepted + else // Write request accepted { #ifdef INSTRUMENTATION -m_cpt_data_write++; + m_cpt_data_write++; #endif // cleaning llsc buffer if address matching - if ( paddr == r_dcache_llsc_paddr.read() ) + if (paddr == r_dcache_llsc_paddr.read()) r_dcache_llsc_valid = false; if (not cacheable) { - r_dcache_vci_paddr = paddr; - r_dcache_vci_wdata = m_dreq.wdata; - r_dcache_vci_unc_write = true; - r_dcache_vci_unc_be = m_dreq.be; - r_dcache_vci_unc_req = true; - r_dcache_fsm = DCACHE_UNC_WAIT; + r_dcache_vci_paddr = paddr; + r_dcache_vci_wdata = m_dreq.wdata; + r_dcache_vci_unc_write = true; + r_dcache_vci_unc_be = m_dreq.be; + r_dcache_vci_unc_req = true; + r_dcache_fsm = DCACHE_UNC_WAIT; } else { // response to processor - m_drsp.valid = true; + m_drsp.valid = true; // activating P1 stage wbuf_request = true; @@ -2911,34 +2910,34 @@ // We don't check a possible write hit in dcache, as the cache update // is done by the coherence transaction induced by the SC... - else if ( m_dreq.type == iss_t::DATA_SC ) + else if (m_dreq.type == iss_t::DATA_SC) { - if ( (r_mmu_mode.read() & DATA_TLB_MASK ) - and not tlb_flags.d ) // Dirty bit must be set + if ((r_mmu_mode.read() & DATA_TLB_MASK) + and not tlb_flags.d) // Dirty bit must be set { // The PTE physical address is obtained from the nline value (dtlb), // and the word index (virtual address) - if ( tlb_flags.b ) // PTE1 + if (tlb_flags.b) // PTE1 { - r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) | - (paddr_t)((m_dreq.addr>>19) & 0x3c); + r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) | + (paddr_t) ((m_dreq.addr >> 19) & 0x3c); } - else // PTE2 + else // PTE2 { - r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) | - (paddr_t)((m_dreq.addr>>9) & 0x38); + r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) | + (paddr_t) ((m_dreq.addr >> 9) & 0x38); } - r_dcache_fsm = DCACHE_DIRTY_GET_PTE; + r_dcache_fsm = DCACHE_DIRTY_GET_PTE; m_drsp.valid = false; m_drsp.error = false; m_drsp.rdata = 0; } - else // SC request accepted + else // SC request accepted { #ifdef INSTRUMENTATION -m_cpt_data_sc++; + m_cpt_data_sc++; #endif // checking local success - if( r_dcache_llsc_valid.read() and - (r_dcache_llsc_paddr.read() == paddr) ) // local success + if (r_dcache_llsc_valid.read() and + (r_dcache_llsc_paddr.read() == paddr)) // local success { // request an SC CMD and go to DCACHE_SC_WAIT state @@ -2948,9 +2947,9 @@ r_dcache_fsm = DCACHE_SC_WAIT; } - else // local fail + else // local fail { - m_drsp.valid = true; - m_drsp.error = false; - m_drsp.rdata = 0x1; + m_drsp.valid = true; + m_drsp.error = false; + m_drsp.rdata = 0x1; } } @@ -2961,5 +2960,5 @@ // itlb miss request - else if ( r_icache_tlb_miss_req.read() and not wbuf_write_miss ) + else if (r_icache_tlb_miss_req.read() and not wbuf_write_miss ) { r_dcache_tlb_ins = true; @@ -2987,29 +2986,29 @@ // r_mmu_ins_* or r_mmu_data* error reporting registers. { - uint32_t ptba = 0; - bool bypass; - paddr_t pte_paddr; + uint32_t ptba = 0; + bool bypass; + paddr_t pte_paddr; // evaluate bypass in order to skip first level page table access - if ( r_dcache_tlb_ins.read() ) // itlb miss + if (r_dcache_tlb_ins.read()) // itlb miss { bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba); } - else // dtlb miss + else // dtlb miss { bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba); } - if ( not bypass ) // Try to read PTE1/PTD1 in dcache - { - pte_paddr = (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2)) | - ((((paddr_t)r_dcache_tlb_vaddr.read()) >> PAGE_M_NBITS) << 2); + if (not bypass) // Try to read PTE1/PTD1 in dcache + { + pte_paddr = (((paddr_t) r_mmu_ptpr.read()) << (INDEX1_NBITS + 2)) | + ((((paddr_t) r_dcache_tlb_vaddr.read()) >> PAGE_M_NBITS) << 2); r_dcache_tlb_paddr = pte_paddr; r_dcache_fsm = DCACHE_TLB_PTE1_GET; } - else // Try to read PTE2 in dcache - { - pte_paddr = (paddr_t)ptba << PAGE_K_NBITS | - (paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3); + else // Try to read PTE2 in dcache + { + pte_paddr = (paddr_t) ptba << PAGE_K_NBITS | + (paddr_t) (r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> (PAGE_K_NBITS - 3); r_dcache_tlb_paddr = pte_paddr; r_dcache_fsm = DCACHE_TLB_PTE2_GET; @@ -3017,15 +3016,15 @@ #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - if ( r_dcache_tlb_ins.read() ) - std::cout << " ITLB miss"; - else - std::cout << " DTLB miss"; - std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read() - << " / ptpr = " << (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2)) - << " / BYPASS = " << bypass - << " / PTE_ADR = " << pte_paddr << std::endl; -} + if (m_debug_dcache_fsm) + { + if (r_dcache_tlb_ins.read()) + std::cout << " ITLB miss"; + else + std::cout << " DTLB miss"; + std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read() + << " / ptpr = " << (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2)) + << " / BYPASS = " << bypass + << " / PTE_ADR = " << pte_paddr << std::endl; + } #endif @@ -3033,8 +3032,8 @@ } ///////////////////////// - case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache + case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache { // coherence clack request (from DSPIN CLACK) - if ( r_dcache_clack_req.read() ) + if (r_dcache_clack_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3044,5 +3043,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3051,24 +3050,24 @@ } - uint32_t entry; - size_t way; - size_t set; - size_t word; - int cache_state; - r_dcache.read( r_dcache_tlb_paddr.read(), - &entry, - &way, - &set, - &word, - &cache_state ); + uint32_t entry; + size_t way; + size_t set; + size_t word; + int cache_state; + r_dcache.read(r_dcache_tlb_paddr.read(), + &entry, + &way, + &set, + &word, + &cache_state); #ifdef INSTRUMENTATION -m_cpt_dcache_data_read++; -m_cpt_dcache_dir_read++; -#endif - if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache - { - if ( not (entry & PTE_V_MASK) ) // unmapped - { - if ( r_dcache_tlb_ins.read() ) + m_cpt_dcache_data_read++; + m_cpt_dcache_dir_read++; +#endif + if (cache_state == CACHE_SLOT_STATE_VALID) // hit in dcache + { + if (not (entry & PTE_V_MASK)) // unmapped + { + if (r_dcache_tlb_ins.read()) { r_mmu_ietr = MMU_READ_PT1_UNMAPPED; @@ -3079,64 +3078,64 @@ else { - r_mmu_detr = MMU_READ_PT1_UNMAPPED; - r_mmu_dbvar = r_dcache_tlb_vaddr.read(); - m_drsp.valid = true; - m_drsp.error = true; + r_mmu_detr = MMU_READ_PT1_UNMAPPED; + r_mmu_dbvar = r_dcache_tlb_vaddr.read(); + m_drsp.valid = true; + m_drsp.error = true; } - r_dcache_fsm = DCACHE_IDLE; + r_dcache_fsm = DCACHE_IDLE; #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " HIT in dcache, but unmapped" - << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() - << std::dec << " / way = " << way - << std::dec << " / set = " << set - << std::dec << " / word = " << word - << std::hex << " / PTE1 = " << entry << std::endl; -} -#endif - - } - else if( entry & PTE_T_MASK ) // PTD : me must access PT2 + if (m_debug_dcache_fsm) + { + std::cout << " HIT in dcache, but unmapped" + << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() + << std::dec << " / way = " << way + << std::dec << " / set = " << set + << std::dec << " / word = " << word + << std::hex << " / PTE1 = " << entry << std::endl; + } +#endif + + } + else if (entry & PTE_T_MASK ) // PTD : me must access PT2 { // mark the cache line ac containing a PTD - r_dcache_contains_ptd[m_dcache_sets*way+set] = true; + r_dcache_contains_ptd[m_dcache_sets * way + set] = true; // register bypass - if ( r_dcache_tlb_ins.read() ) // itlb + if (r_dcache_tlb_ins.read()) // itlb { r_itlb.set_bypass(r_dcache_tlb_vaddr.read(), entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1), - r_dcache_tlb_paddr.read() / (m_icache_words<<2) ); + r_dcache_tlb_paddr.read() / (m_icache_words << 2)); } - else // dtlb + else // dtlb { r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(), entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1), - r_dcache_tlb_paddr.read() / (m_dcache_words<<2) ); + r_dcache_tlb_paddr.read() / (m_dcache_words << 2)); } r_dcache_tlb_paddr = - (paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS | + (paddr_t)(entry & ((1 << (m_paddr_nbits - PAGE_K_NBITS)) - 1)) << PAGE_K_NBITS | (paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); - r_dcache_fsm = DCACHE_TLB_PTE2_GET; + r_dcache_fsm = DCACHE_TLB_PTE2_GET; #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " HIT in dcache" - << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() - << std::dec << " / way = " << way - << std::dec << " / set = " << set - << std::dec << " / word = " << word - << std::hex << " / PTD = " << entry << std::endl; -} -#endif - } - else // PTE1 : we must update the TLB - { - r_dcache_in_tlb[m_icache_sets*way+set] = true; + if (m_debug_dcache_fsm) + { + std::cout << " HIT in dcache" + << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() + << std::dec << " / way = " << way + << std::dec << " / set = " << set + << std::dec << " / word = " << word + << std::hex << " / PTD = " << entry << std::endl; + } +#endif + } + else // PTE1 : we must update the TLB + { + r_dcache_in_tlb[m_icache_sets * way + set] = true; r_dcache_tlb_pte_flags = entry; r_dcache_tlb_cache_way = way; @@ -3146,37 +3145,37 @@ #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " HIT in dcache" - << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() - << std::dec << " / way = " << way - << std::dec << " / set = " << set - << std::dec << " / word = " << word - << std::hex << " / PTE1 = " << entry << std::endl; -} -#endif - } - } - else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup + if (m_debug_dcache_fsm) + { + std::cout << " HIT in dcache" + << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() + << std::dec << " / way = " << way + << std::dec << " / set = " << set + << std::dec << " / word = " << word + << std::hex << " / PTE1 = " << entry << std::endl; + } +#endif + } + } + else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup { // stalled until cleanup is acknowledged - r_dcache_fsm = DCACHE_TLB_PTE1_GET; - } - else // we must load the missing cache line in dcache - { - r_dcache_vci_miss_req = true; - r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); - r_dcache_save_paddr = r_dcache_tlb_paddr.read(); - r_dcache_miss_type = PTE1_MISS; - r_dcache_fsm = DCACHE_MISS_SELECT; + r_dcache_fsm = DCACHE_TLB_PTE1_GET; + } + else // we must load the missing cache line in dcache + { + r_dcache_vci_miss_req = true; + r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); + r_dcache_save_paddr = r_dcache_tlb_paddr.read(); + r_dcache_miss_type = PTE1_MISS; + r_dcache_fsm = DCACHE_MISS_SELECT; #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " MISS in dcache:" - << " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl; -} + if (m_debug_dcache_fsm) + { + std::cout << " MISS in dcache:" + << " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl; + } #endif } @@ -3184,27 +3183,27 @@ } //////////////////////////// - case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1 - { - size_t way; - size_t set; - - if ( r_dcache_tlb_ins.read() ) - { - r_itlb.select( r_dcache_tlb_vaddr.read(), - true, // PTE1 - &way, - &set ); + case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1 + { + size_t way; + size_t set; + + if (r_dcache_tlb_ins.read()) + { + r_itlb.select(r_dcache_tlb_vaddr.read(), + true, // PTE1 + &way, + &set); #ifdef INSTRUMENTATION -m_cpt_itlb_read++; + m_cpt_itlb_read++; #endif } else { - r_dtlb.select( r_dcache_tlb_vaddr.read(), - true, // PTE1 - &way, - &set ); + r_dtlb.select(r_dcache_tlb_vaddr.read(), + true, // PTE1 + &way, + &set); #ifdef INSTRUMENTATION -m_cpt_dtlb_read++; + m_cpt_dtlb_read++; #endif } @@ -3214,20 +3213,20 @@ #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - if ( r_dcache_tlb_ins.read() ) - std::cout << " Select a slot in ITLB:"; - else - std::cout << " Select a slot in DTLB:"; - std::cout << " way = " << std::dec << way - << " / set = " << set << std::endl; -} + if (m_debug_dcache_fsm) + { + if (r_dcache_tlb_ins.read()) + std::cout << " Select a slot in ITLB:"; + else + std::cout << " Select a slot in DTLB:"; + std::cout << " way = " << std::dec << way + << " / set = " << set << std::endl; + } #endif break; } ////////////////////////// - case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit + case DCACHE_TLB_PTE1_UPDT: // write a new PTE1 in tlb after testing the L/R bit // - if L/R bit already set, exit the sub-fsm. // - if not, we update the page table but we dont write @@ -3235,8 +3234,8 @@ // the coherence mechanism. { - paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2); - uint32_t pte = r_dcache_tlb_pte_flags.read(); - bool pt_updt = false; - bool local = true; + paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2); + uint32_t pte = r_dcache_tlb_pte_flags.read(); + bool pt_updt = false; + bool local = true; // We should compute the access locality: @@ -3247,22 +3246,22 @@ // As long as this computation is not done, all access are local. - if ( local ) // local access - { - if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit + if (local) // local access + { + if (not ((pte & PTE_L_MASK) == PTE_L_MASK)) // we must set the L bit { pt_updt = true; - r_dcache_vci_cas_old = pte; - r_dcache_vci_cas_new = pte | PTE_L_MASK; + r_dcache_vci_cas_old = pte; + r_dcache_vci_cas_new = pte | PTE_L_MASK; pte = pte | PTE_L_MASK; r_dcache_tlb_pte_flags = pte; } } - else // remote access - { - if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit + else // remote access + { + if (not ((pte & PTE_R_MASK) == PTE_R_MASK)) // we must set the R bit { pt_updt = true; - r_dcache_vci_cas_old = pte; - r_dcache_vci_cas_new = pte | PTE_R_MASK; + r_dcache_vci_cas_old = pte; + r_dcache_vci_cas_new = pte | PTE_R_MASK; pte = pte | PTE_R_MASK; r_dcache_tlb_pte_flags = pte; @@ -3270,52 +3269,52 @@ } - if ( not pt_updt ) // update TLB and return - { - if ( r_dcache_tlb_ins.read() ) - { - r_itlb.write( true, // 2M page - pte, - 0, // argument unused for a PTE1 - r_dcache_tlb_vaddr.read(), - r_dcache_tlb_way.read(), - r_dcache_tlb_set.read(), - nline ); + if (not pt_updt) // update TLB and return + { + if (r_dcache_tlb_ins.read()) + { + r_itlb.write(true, // 2M page + pte, + 0, // argument unused for a PTE1 + r_dcache_tlb_vaddr.read(), + r_dcache_tlb_way.read(), + r_dcache_tlb_set.read(), + nline); #ifdef INSTRUMENTATION -m_cpt_itlb_write++; + m_cpt_itlb_write++; #endif #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " write PTE1 in ITLB" - << " / set = " << std::dec << r_dcache_tlb_set.read() - << " / way = " << r_dcache_tlb_way.read() << std::endl; - r_itlb.printTrace(); -} + if (m_debug_dcache_fsm) + { + std::cout << " write PTE1 in ITLB" + << " / set = " << std::dec << r_dcache_tlb_set.read() + << " / way = " << r_dcache_tlb_way.read() << std::endl; + r_itlb.printTrace(); + } #endif } else { - r_dtlb.write( true, // 2M page - pte, - 0, // argument unused for a PTE1 - r_dcache_tlb_vaddr.read(), - r_dcache_tlb_way.read(), - r_dcache_tlb_set.read(), - nline ); + r_dtlb.write(true, // 2M page + pte, + 0, // argument unused for a PTE1 + r_dcache_tlb_vaddr.read(), + r_dcache_tlb_way.read(), + r_dcache_tlb_set.read(), + nline); #ifdef INSTRUMENTATION -m_cpt_dtlb_write++; + m_cpt_dtlb_write++; #endif #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " write PTE1 in DTLB" - << " / set = " << std::dec << r_dcache_tlb_set.read() - << " / way = " << r_dcache_tlb_way.read() << std::endl; - r_dtlb.printTrace(); -} + if (m_debug_dcache_fsm) + { + std::cout << " write PTE1 in DTLB" + << " / set = " << std::dec << r_dcache_tlb_set.read() + << " / way = " << r_dcache_tlb_way.read() << std::endl; + r_dtlb.printTrace(); + } #endif } @@ -3327,10 +3326,10 @@ #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " L/R bit update required" - << std::endl; -} + if (m_debug_dcache_fsm) + { + std::cout << " L/R bit update required" + << std::endl; + } #endif } @@ -3338,8 +3337,8 @@ } ///////////////////////// - case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache + case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache { // coherence clack request (from DSPIN CLACK) - if ( r_dcache_clack_req.read() ) + if (r_dcache_clack_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3349,5 +3348,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3356,27 +3355,27 @@ } - uint32_t pte_flags; - uint32_t pte_ppn; - size_t way; - size_t set; - size_t word; - int cache_state; - - r_dcache.read( r_dcache_tlb_paddr.read(), - &pte_flags, - &pte_ppn, - &way, - &set, - &word, - &cache_state ); + uint32_t pte_flags; + uint32_t pte_ppn; + size_t way; + size_t set; + size_t word; + int cache_state; + + r_dcache.read(r_dcache_tlb_paddr.read(), + &pte_flags, + &pte_ppn, + &way, + &set, + &word, + &cache_state); #ifdef INSTRUMENTATION -m_cpt_dcache_data_read++; -m_cpt_dcache_dir_read++; -#endif - if ( cache_state == CACHE_SLOT_STATE_VALID ) // hit in dcache - { - if ( not (pte_flags & PTE_V_MASK) ) // unmapped - { - if ( r_dcache_tlb_ins.read() ) + m_cpt_dcache_data_read++; + m_cpt_dcache_dir_read++; +#endif + if (cache_state == CACHE_SLOT_STATE_VALID) // hit in dcache + { + if (not (pte_flags & PTE_V_MASK)) // unmapped + { + if (r_dcache_tlb_ins.read()) { r_mmu_ietr = MMU_READ_PT2_UNMAPPED; @@ -3387,24 +3386,24 @@ else { - r_mmu_detr = MMU_READ_PT2_UNMAPPED; - r_mmu_dbvar = r_dcache_tlb_vaddr.read(); - m_drsp.valid = true; - m_drsp.error = true; + r_mmu_detr = MMU_READ_PT2_UNMAPPED; + r_mmu_dbvar = r_dcache_tlb_vaddr.read(); + m_drsp.valid = true; + m_drsp.error = true; } - r_dcache_fsm = DCACHE_IDLE; + r_dcache_fsm = DCACHE_IDLE; #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " HIT in dcache, but PTE unmapped" - << " PTE_FLAGS = " << std::hex << pte_flags - << " PTE_PPN = " << std::hex << pte_ppn << std::endl; -} -#endif - } - else // mapped : we must update the TLB - { - r_dcache_in_tlb[m_dcache_sets*way+set] = true; + if (m_debug_dcache_fsm) + { + std::cout << " HIT in dcache, but PTE unmapped" + << " PTE_FLAGS = " << std::hex << pte_flags + << " PTE_PPN = " << std::hex << pte_ppn << std::endl; + } +#endif + } + else // mapped : we must update the TLB + { + r_dcache_in_tlb[m_dcache_sets * way + set] = true; r_dcache_tlb_pte_flags = pte_flags; r_dcache_tlb_pte_ppn = pte_ppn; @@ -3415,15 +3414,15 @@ #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " HIT in dcache:" - << " PTE_FLAGS = " << std::hex << pte_flags - << " PTE_PPN = " << std::hex << pte_ppn << std::endl; -} + if (m_debug_dcache_fsm) + { + std::cout << " HIT in dcache:" + << " PTE_FLAGS = " << std::hex << pte_flags + << " PTE_PPN = " << std::hex << pte_ppn << std::endl; + } #endif } } - else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup + else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup { // stalled until cleanup is acknowledged @@ -3431,10 +3430,10 @@ #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " ZOMBI in dcache: waiting cleanup ack" - << std::endl; -} + if (m_debug_dcache_fsm) + { + std::cout << " ZOMBI in dcache: waiting cleanup ack" + << std::endl; + } #endif } @@ -3448,10 +3447,10 @@ #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " MISS in dcache:" - << " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl; -} + if (m_debug_dcache_fsm) + { + std::cout << " MISS in dcache:" + << " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl; + } #endif } @@ -3464,37 +3463,37 @@ size_t set; - if ( r_dcache_tlb_ins.read() ) - { - r_itlb.select( r_dcache_tlb_vaddr.read(), - false, // PTE2 - &way, - &set ); + if (r_dcache_tlb_ins.read()) + { + r_itlb.select(r_dcache_tlb_vaddr.read(), + false, // PTE2 + &way, + &set); #ifdef INSTRUMENTATION -m_cpt_itlb_read++; + m_cpt_itlb_read++; #endif } else { - r_dtlb.select( r_dcache_tlb_vaddr.read(), - false, // PTE2 - &way, - &set ); + r_dtlb.select(r_dcache_tlb_vaddr.read(), + false, // PTE2 + &way, + &set); #ifdef INSTRUMENTATION -m_cpt_dtlb_read++; + m_cpt_dtlb_read++; #endif } #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - if ( r_dcache_tlb_ins.read() ) - std::cout << " Select a slot in ITLB:"; - else - std::cout << " Select a slot in DTLB:"; - std::cout << " way = " << std::dec << way - << " / set = " << set << std::endl; -} + if (m_debug_dcache_fsm) + { + if (r_dcache_tlb_ins.read()) + std::cout << " Select a slot in ITLB:"; + else + std::cout << " Select a slot in DTLB:"; + std::cout << " way = " << std::dec << way + << " / set = " << set << std::endl; + } #endif r_dcache_tlb_way = way; @@ -3504,5 +3503,5 @@ } ////////////////////////// - case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit + case DCACHE_TLB_PTE2_UPDT: // write a new PTE2 in tlb after testing the L/R bit // - if L/R bit already set, exit the sub-fsm. // - if not, we update the page table but we dont write @@ -3510,9 +3509,9 @@ // the coherence mechanism. { - paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2); - uint32_t pte_flags = r_dcache_tlb_pte_flags.read(); - uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read(); - bool pt_updt = false; - bool local = true; + paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2); + uint32_t pte_flags = r_dcache_tlb_pte_flags.read(); + uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read(); + bool pt_updt = false; + bool local = true; // We should compute the access locality: @@ -3523,7 +3522,7 @@ // As long as this computation is not done, all access are local. - if ( local ) // local access - { - if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit + if (local) // local access + { + if (not ((pte_flags & PTE_L_MASK) == PTE_L_MASK)) // we must set the L bit { pt_updt = true; @@ -3531,10 +3530,10 @@ r_dcache_vci_cas_new = pte_flags | PTE_L_MASK; pte_flags = pte_flags | PTE_L_MASK; - r_dcache_tlb_pte_flags = pte_flags; + r_dcache_tlb_pte_flags = pte_flags; } } else // remote access { - if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit + if (not ((pte_flags & PTE_R_MASK) == PTE_R_MASK)) // we must set the R bit { pt_updt = true; @@ -3542,13 +3541,13 @@ r_dcache_vci_cas_new = pte_flags | PTE_R_MASK; pte_flags = pte_flags | PTE_R_MASK; - r_dcache_tlb_pte_flags = pte_flags; - } - } - - if ( not pt_updt ) // update TLB - { - if ( r_dcache_tlb_ins.read() ) - { - r_itlb.write( false, // 4K page + r_dcache_tlb_pte_flags = pte_flags; + } + } + + if (not pt_updt) // update TLB + { + if (r_dcache_tlb_ins.read()) + { + r_itlb.write( false, // 4K page pte_flags, pte_ppn, @@ -3558,40 +3557,40 @@ nline ); #ifdef INSTRUMENTATION -m_cpt_itlb_write++; + m_cpt_itlb_write++; #endif #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " write PTE2 in ITLB" - << " / set = " << std::dec << r_dcache_tlb_set.read() - << " / way = " << r_dcache_tlb_way.read() << std::endl; - r_itlb.printTrace(); -} + if (m_debug_dcache_fsm) + { + std::cout << " write PTE2 in ITLB" + << " / set = " << std::dec << r_dcache_tlb_set.read() + << " / way = " << r_dcache_tlb_way.read() << std::endl; + r_itlb.printTrace(); + } #endif } else { - r_dtlb.write( false, // 4K page - pte_flags, - pte_ppn, - r_dcache_tlb_vaddr.read(), - r_dcache_tlb_way.read(), - r_dcache_tlb_set.read(), - nline ); + r_dtlb.write(false, // 4K page + pte_flags, + pte_ppn, + r_dcache_tlb_vaddr.read(), + r_dcache_tlb_way.read(), + r_dcache_tlb_set.read(), + nline); #ifdef INSTRUMENTATION -m_cpt_dtlb_write++; + m_cpt_dtlb_write++; #endif #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " write PTE2 in DTLB" - << " / set = " << std::dec << r_dcache_tlb_set.read() - << " / way = " << r_dcache_tlb_way.read() << std::endl; - r_dtlb.printTrace(); -} + if (m_debug_dcache_fsm) + { + std::cout << " write PTE2 in DTLB" + << " / set = " << std::dec << r_dcache_tlb_set.read() + << " / way = " << r_dcache_tlb_way.read() << std::endl; + r_dtlb.printTrace(); + } #endif @@ -3601,12 +3600,12 @@ else // update page table but not TLB { - r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update + r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " L/R bit update required" << std::endl; -} + if (m_debug_dcache_fsm) + { + std::cout << " L/R bit update required" << std::endl; + } #endif } @@ -3617,9 +3616,9 @@ { #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " Update dcache: (L/R) bit" << std::endl; -} + if (m_debug_dcache_fsm) + { + std::cout << " Update dcache: (L/R) bit" << std::endl; + } #endif // r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set @@ -3627,14 +3626,14 @@ // checking llsc reservation buffer - if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() ) + if (r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read()) r_dcache_llsc_valid = false; // request a CAS CMD and go to DCACHE_TLB_LR_WAIT state r_dcache_vci_cas_req = true; - r_dcache_fsm = DCACHE_TLB_LR_WAIT; + r_dcache_fsm = DCACHE_TLB_LR_WAIT; break; } //////////////////////// - case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit. + case DCACHE_TLB_LR_WAIT: // Waiting the response to SC transaction for DIRTY bit. // We consume the response in rsp FIFO, // and exit the sub-fsm, but we don't @@ -3646,5 +3645,5 @@ { // coherence clack request (from DSPIN CLACK) - if ( r_dcache_clack_req.read() ) + if (r_dcache_clack_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3654,5 +3653,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3661,5 +3660,5 @@ } - if ( r_vci_rsp_data_error.read() ) // bus error + if (r_vci_rsp_data_error.read()) // bus error { std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl; @@ -3667,34 +3666,34 @@ exit(0); } - else if ( r_vci_rsp_fifo_dcache.rok() ) // response available + else if (r_vci_rsp_fifo_dcache.rok()) // response available { #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " SC response received" << std::endl; -} + if (m_debug_dcache_fsm) + { + std::cout << " SC response received" << std::endl; + } #endif vci_rsp_fifo_dcache_get = true; - r_dcache_fsm = DCACHE_TLB_RETURN; + r_dcache_fsm = DCACHE_TLB_RETURN; } break; } /////////////////////// - case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type + case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type { #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " TLB MISS completed" << std::endl; -} -#endif - if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false; + if (m_debug_dcache_fsm) + { + std::cout << " TLB MISS completed" << std::endl; + } +#endif + if (r_dcache_tlb_ins.read()) r_icache_tlb_miss_req = false; r_dcache_fsm = DCACHE_IDLE; break; } /////////////////////// - case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written, + case DCACHE_XTN_SWITCH: // The r_ptpr registers must be written, // and both itlb and dtlb must be flushed. // Caution : the itlb miss requests must be taken @@ -3704,5 +3703,5 @@ { // coherence clack request (from DSPIN CLACK) - if ( r_dcache_clack_req.read() ) + if (r_dcache_clack_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3712,5 +3711,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3720,13 +3719,13 @@ // itlb miss request - if ( r_icache_tlb_miss_req.read() ) - { - r_dcache_tlb_ins = true; - r_dcache_tlb_vaddr = r_icache_vaddr_save.read(); - r_dcache_fsm = DCACHE_TLB_MISS; - break; - } - - if ( not r_dcache_xtn_req.read() ) + if (r_icache_tlb_miss_req.read()) + { + r_dcache_tlb_ins = true; + r_dcache_tlb_vaddr = r_icache_vaddr_save.read(); + r_dcache_fsm = DCACHE_TLB_MISS; + break; + } + + if (not r_dcache_xtn_req.read()) { r_dtlb.flush(); @@ -3738,10 +3737,10 @@ } ///////////////////// - case DCACHE_XTN_SYNC: // waiting until write buffer empty - // The coherence request must be taken - // as there is a risk of dead-lock + case DCACHE_XTN_SYNC: // waiting until write buffer empty + // The coherence request must be taken + // as there is a risk of dead-lock { // coherence clack request (from DSPIN CLACK) - if ( r_dcache_clack_req.read() ) + if (r_dcache_clack_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3751,5 +3750,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3758,7 +3757,7 @@ } - if ( r_wbuf.empty() ) - { - m_drsp.valid = true; + if (r_wbuf.empty()) + { + m_drsp.valid = true; r_dcache_fsm = DCACHE_IDLE; } @@ -3774,5 +3773,5 @@ { // coherence clack request (from DSPIN CLACK) - if ( r_dcache_clack_req.read() ) + if (r_dcache_clack_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3782,5 +3781,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3790,14 +3789,14 @@ // itlb miss request - if ( r_icache_tlb_miss_req.read() ) - { - r_dcache_tlb_ins = true; - r_dcache_tlb_vaddr = r_icache_vaddr_save.read(); - r_dcache_fsm = DCACHE_TLB_MISS; + if (r_icache_tlb_miss_req.read()) + { + r_dcache_tlb_ins = true; + r_dcache_tlb_vaddr = r_icache_vaddr_save.read(); + r_dcache_fsm = DCACHE_TLB_MISS; break; } // test if XTN request to icache completed - if ( not r_dcache_xtn_req.read() ) + if (not r_dcache_xtn_req.read()) { r_dcache_fsm = DCACHE_IDLE; @@ -3807,5 +3806,5 @@ } ///////////////////////// - case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using + case DCACHE_XTN_DC_FLUSH: // Invalidate sequencially all cache lines, using // r_dcache_flush_count as a slot counter, // looping in this state until all slots have been visited. @@ -3817,5 +3816,5 @@ { // coherence clack request (from DSPIN CLACK) - if ( r_dcache_clack_req.read() ) + if (r_dcache_clack_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3825,5 +3824,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3832,20 +3831,20 @@ } - if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent - { - int state; - paddr_t tag; - size_t way = r_dcache_flush_count.read()/m_dcache_sets; - size_t set = r_dcache_flush_count.read()%m_dcache_sets; + if (not r_dcache_cc_send_req.read()) // blocked until previous cc_send request is sent + { + int state; + paddr_t tag; + size_t way = r_dcache_flush_count.read()/m_dcache_sets; + size_t set = r_dcache_flush_count.read()%m_dcache_sets; #ifdef INSTRUMENTATION -m_cpt_dcache_dir_read++; -#endif - r_dcache.read_dir( way, - set, - &tag, - &state ); - - if ( state == CACHE_SLOT_STATE_VALID ) // inval required + m_cpt_dcache_dir_read++; +#endif + r_dcache.read_dir(way, + set, + &tag, + &state); + + if (state == CACHE_SLOT_STATE_VALID) // inval required { // request cleanup @@ -3856,10 +3855,10 @@ // goes to DCACHE_XTN_DC_FLUSH_GO to inval directory - r_dcache_miss_way = way; - r_dcache_miss_set = set; - r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO; - } - else if ( r_dcache_flush_count.read() == - (m_dcache_sets*m_dcache_ways - 1) ) // last slot + r_dcache_miss_way = way; + r_dcache_miss_set = set; + r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO; + } + else if (r_dcache_flush_count.read() == + (m_dcache_sets*m_dcache_ways - 1)) // last slot { r_dtlb.reset(); @@ -3870,5 +3869,5 @@ // saturation counter - if ( r_dcache_flush_count.read() < (m_dcache_sets*m_dcache_ways - 1) ) + if (r_dcache_flush_count.read() < (m_dcache_sets * m_dcache_ways - 1)) r_dcache_flush_count = r_dcache_flush_count.read() + 1; } @@ -3883,16 +3882,16 @@ size_t set = r_dcache_miss_set.read(); - r_dcache_in_tlb[m_dcache_sets*way+set] = false; - r_dcache_contains_ptd[m_dcache_sets*way+set] = false; + r_dcache_in_tlb[m_dcache_sets * way + set] = false; + r_dcache_contains_ptd[m_dcache_sets * way + set] = false; #ifdef INSTRUMENTATION -m_cpt_dcache_dir_write++; -#endif - r_dcache.write_dir( way, - set, - CACHE_SLOT_STATE_ZOMBI ); - - if ( r_dcache_flush_count.read() == - (m_dcache_sets*m_dcache_ways - 1) ) // last slot + m_cpt_dcache_dir_write++; +#endif + r_dcache.write_dir(way, + set, + CACHE_SLOT_STATE_ZOMBI); + + if (r_dcache_flush_count.read() == + (m_dcache_sets*m_dcache_ways - 1)) // last slot { r_dtlb.reset(); @@ -3908,9 +3907,9 @@ } ///////////////////////// - case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request + case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request { r_dtlb.inval(r_dcache_save_wdata.read()); - r_dcache_fsm = DCACHE_IDLE; - m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; + m_drsp.valid = true; break; } @@ -3918,50 +3917,50 @@ case DCACHE_XTN_DC_INVAL_VA: // selective cache line invalidate with virtual address // requires 3 cycles: access tlb, read cache, inval cache - // we compute the physical address in this state + // we compute the physical address in this state { paddr_t paddr; - bool hit; - - if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated + bool hit; + + if (r_mmu_mode.read() & DATA_TLB_MASK) // dtlb activated { #ifdef INSTRUMENTATION -m_cpt_dtlb_read++; -#endif - hit = r_dtlb.translate( r_dcache_save_wdata.read(), - &paddr ); - } - else // dtlb not activated + m_cpt_dtlb_read++; +#endif + hit = r_dtlb.translate(r_dcache_save_wdata.read(), + &paddr); + } + else // dtlb not activated { paddr = (paddr_t)r_dcache_save_wdata.read(); if (vci_param::N > 32) paddr = paddr | ((paddr_t)(r_dcache_paddr_ext.read()) << 32); - hit = true; - } - - if ( hit ) // tlb hit + hit = true; + } + + if (hit) // tlb hit { r_dcache_save_paddr = paddr; - r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA; - } - else // tlb miss - { + r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA; + } + else // tlb miss + { #ifdef INSTRUMENTATION -m_cpt_dtlb_miss++; -#endif - r_dcache_tlb_ins = false; // dtlb - r_dcache_tlb_vaddr = r_dcache_save_wdata.read(); - r_dcache_fsm = DCACHE_TLB_MISS; + m_cpt_dtlb_miss++; +#endif + r_dcache_tlb_ins = false; // dtlb + r_dcache_tlb_vaddr = r_dcache_save_wdata.read(); + r_dcache_fsm = DCACHE_TLB_MISS; } #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " Compute physical address" << std::hex - << " / VADDR = " << r_dcache_save_wdata.read() - << " / PADDR = " << paddr << std::endl; -} + if (m_debug_dcache_fsm) + { + std::cout << " Compute physical address" << std::hex + << " / VADDR = " << r_dcache_save_wdata.read() + << " / PADDR = " << paddr << std::endl; + } #endif @@ -3973,40 +3972,40 @@ // In this state we read dcache. { - size_t way; - size_t set; - size_t word; - int state; + size_t way; + size_t set; + size_t word; + int state; #ifdef INSTRUMENTATION -m_cpt_dcache_dir_read++; -#endif - r_dcache.read_dir( r_dcache_save_paddr.read(), - &state, - &way, - &set, - &word ); - - if ( state == CACHE_SLOT_STATE_VALID ) // inval to be done + m_cpt_dcache_dir_read++; +#endif + r_dcache.read_dir(r_dcache_save_paddr.read(), + &state, + &way, + &set, + &word); + + if (state == CACHE_SLOT_STATE_VALID) // inval to be done { r_dcache_xtn_way = way; r_dcache_xtn_set = set; - r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO; - } - else // miss : nothing to do - { - r_dcache_fsm = DCACHE_IDLE; - m_drsp.valid = true; + r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO; + } + else // miss : nothing to do + { + r_dcache_fsm = DCACHE_IDLE; + m_drsp.valid = true; } #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " Test hit in dcache" << std::hex - << " / PADDR = " << r_dcache_save_paddr.read() << std::dec - << " / HIT = " << (state == CACHE_SLOT_STATE_VALID) - << " / SET = " << set - << " / WAY = " << way << std::endl; -} + if (m_debug_dcache_fsm) + { + std::cout << " Test hit in dcache" << std::hex + << " / PADDR = " << r_dcache_save_paddr.read() << std::dec + << " / HIT = " << (state == CACHE_SLOT_STATE_VALID) + << " / SET = " << set + << " / WAY = " << way << std::endl; + } #endif break; @@ -4014,19 +4013,19 @@ //////////////////////////// case DCACHE_XTN_DC_INVAL_GO: // In this state, we invalidate the cache line - // Blocked if previous cleanup not completed + // Blocked if previous cleanup not completed // Test if itlb or dtlb inval is required { - if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent - { - size_t way = r_dcache_xtn_way.read(); - size_t set = r_dcache_xtn_set.read(); - paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2); + if (not r_dcache_cc_send_req.read()) // blocked until previous cc_send request is sent + { + size_t way = r_dcache_xtn_way.read(); + size_t set = r_dcache_xtn_set.read(); + paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words << 2); #ifdef INSTRUMENTATION -m_cpt_dcache_dir_write++; -#endif - r_dcache.write_dir( way, - set, - CACHE_SLOT_STATE_ZOMBI ); + m_cpt_dcache_dir_write++; +#endif + r_dcache.write_dir(way, + set, + CACHE_SLOT_STATE_ZOMBI); // request cleanup @@ -4037,5 +4036,5 @@ // possible itlb & dtlb invalidate - if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) + if (r_dcache_in_tlb[way * m_dcache_sets + set]) { r_dcache_tlb_inval_line = nline; @@ -4043,11 +4042,11 @@ r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END; r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; - r_dcache_in_tlb[way*m_dcache_sets+set] = false; - } - else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) + r_dcache_in_tlb[way * m_dcache_sets + set] = false; + } + else if (r_dcache_contains_ptd[way * m_dcache_sets + set]) { r_itlb.reset(); r_dtlb.reset(); - r_dcache_contains_ptd[way*m_dcache_sets+set] = false; + r_dcache_contains_ptd[way * m_dcache_sets + set] = false; r_dcache_fsm = DCACHE_IDLE; m_drsp.valid = true; @@ -4060,16 +4059,16 @@ #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " Actual dcache inval" << std::hex - << " / PADDR = " << r_dcache_save_paddr.read() << std::endl; -} -#endif - } + if (m_debug_dcache_fsm) + { + std::cout << " Actual dcache inval" << std::hex + << " / PADDR = " << r_dcache_save_paddr.read() << std::endl; + } +#endif + } break; } ////////////////////////////// - case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request + case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request { r_dcache_fsm = DCACHE_IDLE; @@ -4088,8 +4087,8 @@ // when a cleanup is required { - if ( m_dreq.valid) m_cost_data_miss_frz++; + if (m_dreq.valid) m_cost_data_miss_frz++; // coherence clack request (from DSPIN CLACK) - if ( r_dcache_clack_req.read() ) + if (r_dcache_clack_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4099,5 +4098,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4106,21 +4105,21 @@ } - bool found = false; - bool cleanup = false; - size_t way = 0; - size_t set = 0; - paddr_t victim = 0; + bool found = false; + bool cleanup = false; + size_t way = 0; + size_t set = 0; + paddr_t victim = 0; #ifdef INSTRUMENTATION -m_cpt_dcache_dir_read++; -#endif - r_dcache.read_select( r_dcache_save_paddr.read(), - &victim, - &way, - &set, - &found, - &cleanup ); - - if ( not found ) + m_cpt_dcache_dir_read++; +#endif + r_dcache.read_select(r_dcache_save_paddr.read(), + &victim, + &way, + &set, + &found, + &cleanup); + + if (not found) { break; @@ -4131,12 +4130,12 @@ r_dcache_miss_set = set; - if ( cleanup ) - { - if ( not r_dcache_cc_send_req.read() ) + if (cleanup) + { + if (not r_dcache_cc_send_req.read()) { - r_dcache_cc_send_req = true; - r_dcache_cc_send_nline = victim; - r_dcache_cc_send_way = way; - r_dcache_cc_send_type = CC_TYPE_CLEANUP; + r_dcache_cc_send_req = true; + r_dcache_cc_send_nline = victim; + r_dcache_cc_send_way = way; + r_dcache_cc_send_type = CC_TYPE_CLEANUP; } @@ -4147,23 +4146,23 @@ } - r_dcache_miss_clack = true; - r_dcache_fsm = DCACHE_MISS_CLEAN; + r_dcache_miss_clack = true; + r_dcache_fsm = DCACHE_MISS_CLEAN; } else { - r_dcache_fsm = DCACHE_MISS_WAIT; + r_dcache_fsm = DCACHE_MISS_WAIT; } #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " Select a slot:" << std::dec - << " / WAY = " << way - << " / SET = " << set - << " / PADDR = " << std::hex << r_dcache_save_paddr.read(); - if(cleanup) std::cout << " / VICTIM = " << (victim*m_dcache_words*4) << std::endl; - else std::cout << std::endl; -} + if (m_debug_dcache_fsm) + { + std::cout << " Select a slot:" << std::dec + << " / WAY = " << way + << " / SET = " << set + << " / PADDR = " << std::hex << r_dcache_save_paddr.read(); + if (cleanup) std::cout << " / VICTIM = " << (victim*m_dcache_words*4) << std::endl; + else std::cout << std::endl; + } #endif } // end found @@ -4171,47 +4170,47 @@ } /////////////////////// - case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state + case DCACHE_MISS_CLEAN: // switch the slot to ZOMBI state // and possibly request itlb or dtlb invalidate { - if ( m_dreq.valid) m_cost_data_miss_frz++; - - size_t way = r_dcache_miss_way.read(); - size_t set = r_dcache_miss_set.read(); + if (m_dreq.valid) m_cost_data_miss_frz++; + + size_t way = r_dcache_miss_way.read(); + size_t set = r_dcache_miss_set.read(); #ifdef INSTRUMENTATION -m_cpt_dcache_dir_read++; -#endif - r_dcache.write_dir( way, - set, - CACHE_SLOT_STATE_ZOMBI ); + m_cpt_dcache_dir_read++; +#endif + r_dcache.write_dir(way, + set, + CACHE_SLOT_STATE_ZOMBI); #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " Switch to ZOMBI state" << std::dec - << " / way = " << way - << " / set = " << set << std::endl; -} + if (m_debug_dcache_fsm) + { + std::cout << " Switch to ZOMBI state" << std::dec + << " / way = " << way + << " / set = " << set << std::endl; + } #endif // if selective itlb & dtlb invalidate are required // the miss response is not handled before invalidate completed - if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) - { - r_dcache_in_tlb[way*m_dcache_sets+set] = false; - - if( not r_dcache_cleanup_victim_req.read() ) - r_dcache_tlb_inval_line = r_dcache_cc_send_nline.read(); + if (r_dcache_in_tlb[way * m_dcache_sets + set]) + { + r_dcache_in_tlb[way * m_dcache_sets + set] = false; + + if (not r_dcache_cleanup_victim_req.read()) + r_dcache_tlb_inval_line = r_dcache_cc_send_nline.read(); else r_dcache_tlb_inval_line = r_dcache_cleanup_victim_nline.read(); - r_dcache_tlb_inval_set = 0; - r_dcache_fsm_scan_save = DCACHE_MISS_WAIT; - r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; - } - else if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) + r_dcache_tlb_inval_set = 0; + r_dcache_fsm_scan_save = DCACHE_MISS_WAIT; + r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; + } + else if (r_dcache_contains_ptd[way * m_dcache_sets + set]) { r_itlb.reset(); r_dtlb.reset(); - r_dcache_contains_ptd[way*m_dcache_sets+set] = false; + r_dcache_contains_ptd[way * m_dcache_sets + set] = false; r_dcache_fsm = DCACHE_MISS_WAIT; } @@ -4223,12 +4222,12 @@ } ////////////////////// - case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM + case DCACHE_MISS_WAIT: // waiting the response to a miss request from VCI_RSP FSM // This state is in charge of error signaling // There is 5 types of error depending on the requester { - if ( m_dreq.valid) m_cost_data_miss_frz++; + if (m_dreq.valid) m_cost_data_miss_frz++; // send cleanup victim request - if ( r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read() ) + if (r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_cc_send_req = true; @@ -4240,5 +4239,5 @@ // coherence clack request (from DSPIN CLACK) - if ( r_dcache_clack_req.read() ) + if (r_dcache_clack_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4248,5 +4247,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and + if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_cleanup_victim_req.read()) @@ -4257,53 +4256,53 @@ } - if ( r_vci_rsp_data_error.read() ) // bus error - { - switch ( r_dcache_miss_type.read() ) + if (r_vci_rsp_data_error.read()) // bus error + { + switch (r_dcache_miss_type.read()) { case PROC_MISS: { - r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; - r_mmu_dbvar = r_dcache_save_vaddr.read(); - m_drsp.valid = true; - m_drsp.error = true; - r_dcache_fsm = DCACHE_IDLE; + r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; + r_mmu_dbvar = r_dcache_save_vaddr.read(); + m_drsp.valid = true; + m_drsp.error = true; + r_dcache_fsm = DCACHE_IDLE; break; } case PTE1_MISS: { - if ( r_dcache_tlb_ins.read() ) + if (r_dcache_tlb_ins.read()) { - r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS; - r_mmu_ibvar = r_dcache_tlb_vaddr.read(); - r_icache_tlb_miss_req = false; - r_icache_tlb_rsp_error = true; + r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS; + r_mmu_ibvar = r_dcache_tlb_vaddr.read(); + r_icache_tlb_miss_req = false; + r_icache_tlb_rsp_error = true; } else { - r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS; - r_mmu_dbvar = r_dcache_tlb_vaddr.read(); - m_drsp.valid = true; - m_drsp.error = true; + r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS; + r_mmu_dbvar = r_dcache_tlb_vaddr.read(); + m_drsp.valid = true; + m_drsp.error = true; } - r_dcache_fsm = DCACHE_IDLE; + r_dcache_fsm = DCACHE_IDLE; break; } case PTE2_MISS: { - if ( r_dcache_tlb_ins.read() ) + if (r_dcache_tlb_ins.read()) { - r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS; - r_mmu_ibvar = r_dcache_tlb_vaddr.read(); - r_icache_tlb_miss_req = false; - r_icache_tlb_rsp_error = true; + r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS; + r_mmu_ibvar = r_dcache_tlb_vaddr.read(); + r_icache_tlb_miss_req = false; + r_icache_tlb_rsp_error = true; } else { - r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS; - r_mmu_dbvar = r_dcache_tlb_vaddr.read(); - m_drsp.valid = true; - m_drsp.error = true; + r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS; + r_mmu_dbvar = r_dcache_tlb_vaddr.read(); + m_drsp.valid = true; + m_drsp.error = true; } - r_dcache_fsm = DCACHE_IDLE; + r_dcache_fsm = DCACHE_IDLE; break; } @@ -4311,40 +4310,40 @@ r_vci_rsp_data_error = false; } - else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available + else if (r_vci_rsp_fifo_dcache.rok()) // valid response available { r_dcache_miss_word = 0; - r_dcache_fsm = DCACHE_MISS_DATA_UPDT; + r_dcache_fsm = DCACHE_MISS_DATA_UPDT; } break; } ////////////////////////// - case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle) - { - if ( m_dreq.valid) m_cost_data_miss_frz++; - - if ( r_vci_rsp_fifo_dcache.rok() ) // one word available + case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle) + { + if (m_dreq.valid) m_cost_data_miss_frz++; + + if (r_vci_rsp_fifo_dcache.rok()) // one word available { #ifdef INSTRUMENTATION -m_cpt_dcache_data_write++; -#endif - r_dcache.write( r_dcache_miss_way.read(), - r_dcache_miss_set.read(), - r_dcache_miss_word.read(), - r_vci_rsp_fifo_dcache.read() ); + m_cpt_dcache_data_write++; +#endif + r_dcache.write(r_dcache_miss_way.read(), + r_dcache_miss_set.read(), + r_dcache_miss_word.read(), + r_vci_rsp_fifo_dcache.read()); #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " Write one word:" - << " / DATA = " << std::hex << r_vci_rsp_fifo_dcache.read() - << " / WAY = " << std::dec << r_dcache_miss_way.read() - << " / SET = " << r_dcache_miss_set.read() - << " / WORD = " << r_dcache_miss_word.read() << std::endl; -} + if (m_debug_dcache_fsm) + { + std::cout << " Write one word:" + << " / DATA = " << std::hex << r_vci_rsp_fifo_dcache.read() + << " / WAY = " << std::dec << r_dcache_miss_way.read() + << " / SET = " << r_dcache_miss_set.read() + << " / WORD = " << r_dcache_miss_word.read() << std::endl; + } #endif vci_rsp_fifo_dcache_get = true; r_dcache_miss_word = r_dcache_miss_word.read() + 1; - if ( r_dcache_miss_word.read() == (m_dcache_words-1) ) // last word + if (r_dcache_miss_word.read() == (m_dcache_words - 1)) // last word { r_dcache_fsm = DCACHE_MISS_DIR_UPDT; @@ -4362,8 +4361,8 @@ // to ZOMBI state, and send a cleanup request. { - if ( m_dreq.valid) m_cost_data_miss_frz++; + if (m_dreq.valid) m_cost_data_miss_frz++; // send cleanup victim request - if ( r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read() ) + if (r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_cc_send_req = true; @@ -4375,5 +4374,5 @@ // coherence clack request (from DSPIN CLACK) - if ( r_dcache_clack_req.read() ) + if (r_dcache_clack_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4383,7 +4382,7 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and + if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and - not r_dcache_cleanup_victim_req.read() ) + not r_dcache_cleanup_victim_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4392,19 +4391,19 @@ } - if ( not r_dcache_miss_clack.read() ) // waiting cleanup acknowledge - { - if ( r_dcache_miss_inval.read() ) // switch slot to ZOMBI state, and new cleanup - { - if ( not r_dcache_cc_send_req.read() ) // blocked until previous request sent + if (not r_dcache_miss_clack.read()) // waiting cleanup acknowledge + { + if (r_dcache_miss_inval.read()) // switch slot to ZOMBI state, and new cleanup + { + if (not r_dcache_cc_send_req.read()) // blocked until previous request sent { r_dcache_miss_inval = false; // request cleanup r_dcache_cc_send_req = true; - r_dcache_cc_send_nline = r_dcache_save_paddr.read()/(m_dcache_words<<2); + r_dcache_cc_send_nline = r_dcache_save_paddr.read() / (m_dcache_words << 2); r_dcache_cc_send_way = r_dcache_miss_way.read(); r_dcache_cc_send_type = CC_TYPE_CLEANUP; #ifdef INSTRUMENTATION -m_cpt_dcache_dir_write++; + m_cpt_dcache_dir_write++; #endif r_dcache.write_dir( r_dcache_save_paddr.read(), @@ -4413,10 +4412,10 @@ CACHE_SLOT_STATE_ZOMBI ); #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -std::cout << " Switch slot to ZOMBI state" - << " PADDR = " << std::hex << r_dcache_save_paddr.read() - << " / WAY = " << std::dec << r_dcache_miss_way.read() - << " / SET = " << r_dcache_miss_set.read() << std::endl; + if (m_debug_dcache_fsm) + std::cout << " Switch slot to ZOMBI state" + << " PADDR = " << std::hex << r_dcache_save_paddr.read() + << " / WAY = " << std::dec << r_dcache_miss_way.read() + << " / SET = " << r_dcache_miss_set.read() << std::endl; #endif } @@ -4428,24 +4427,24 @@ #ifdef INSTRUMENTATION -m_cpt_dcache_dir_write++; -#endif - r_dcache.write_dir( r_dcache_save_paddr.read(), - r_dcache_miss_way.read(), - r_dcache_miss_set.read(), - CACHE_SLOT_STATE_VALID ); + m_cpt_dcache_dir_write++; +#endif + r_dcache.write_dir(r_dcache_save_paddr.read(), + r_dcache_miss_way.read(), + r_dcache_miss_set.read(), + CACHE_SLOT_STATE_VALID); #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -std::cout << " Switch slot to VALID state" - << " PADDR = " << std::hex << r_dcache_save_paddr.read() - << " / WAY = " << std::dec << r_dcache_miss_way.read() - << " / SET = " << r_dcache_miss_set.read() << std::endl; + if (m_debug_dcache_fsm) + std::cout << " Switch slot to VALID state" + << " PADDR = " << std::hex << r_dcache_save_paddr.read() + << " / WAY = " << std::dec << r_dcache_miss_way.read() + << " / SET = " << r_dcache_miss_set.read() << std::endl; #endif // reset directory extension size_t way = r_dcache_miss_way.read(); size_t set = r_dcache_miss_set.read(); - r_dcache_in_tlb[way*m_dcache_sets+set] = false; - r_dcache_contains_ptd[way*m_dcache_sets+set] = false; + r_dcache_in_tlb[way * m_dcache_sets + set] = false; + r_dcache_contains_ptd[way * m_dcache_sets + set] = false; } if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET; @@ -4459,5 +4458,5 @@ { // coherence clack request (from DSPIN CLACK) - if ( r_dcache_clack_req.read() ) + if (r_dcache_clack_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4467,5 +4466,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4474,10 +4473,10 @@ } - if ( r_vci_rsp_data_error.read() ) // bus error - { - if(r_dcache_vci_unc_write.read()) - r_mmu_detr = MMU_WRITE_DATA_ILLEGAL_ACCESS; + if (r_vci_rsp_data_error.read()) // bus error + { + if (r_dcache_vci_unc_write.read()) + r_mmu_detr = MMU_WRITE_DATA_ILLEGAL_ACCESS; else - r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; + r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; r_mmu_dbvar = m_dreq.addr; @@ -4488,6 +4487,6 @@ break; } - else if ( r_vci_rsp_fifo_dcache.rok() ) // data available - { + else if (r_vci_rsp_fifo_dcache.rok()) // data available + { // consume data vci_rsp_fifo_dcache_get = true; @@ -4495,11 +4494,11 @@ // acknowledge the processor request if it has not been modified - if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) ) - { - m_drsp.valid = true; - m_drsp.error = false; - m_drsp.rdata = r_vci_rsp_fifo_dcache.read(); - } - } + if (m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read())) + { + m_drsp.valid = true; + m_drsp.error = false; + m_drsp.rdata = r_vci_rsp_fifo_dcache.read(); + } + } break; } @@ -4508,5 +4507,5 @@ { // coherence clack request (from DSPIN CLACK) - if ( r_dcache_clack_req.read() ) + if (r_dcache_clack_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4516,5 +4515,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4523,5 +4522,5 @@ } - if ( r_vci_rsp_data_error.read() ) // bus error + if (r_vci_rsp_data_error.read()) // bus error { r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; @@ -4533,34 +4532,34 @@ break; } - else if ( r_vci_rsp_fifo_dcache.rok() ) // data available - { + else if (r_vci_rsp_fifo_dcache.rok()) // data available + { // consume data vci_rsp_fifo_dcache_get = true; - if(r_dcache_ll_rsp_count.read() == 0) // first flit + if (r_dcache_ll_rsp_count.read() == 0) // first flit { // set key value in llsc reservation buffer r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read(); - r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1 ; + r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1; } else // last flit { // acknowledge the processor request if it has not been modified - if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) ) + if (m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read())) { - m_drsp.valid = true; - m_drsp.error = false; - m_drsp.rdata = r_vci_rsp_fifo_dcache.read(); + m_drsp.valid = true; + m_drsp.error = false; + m_drsp.rdata = r_vci_rsp_fifo_dcache.read(); } r_dcache_fsm = DCACHE_IDLE; } - } + } break; } //////////////////// - case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction + case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction { // coherence clack request (from DSPIN CLACK) - if ( r_dcache_clack_req.read() ) + if (r_dcache_clack_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4570,5 +4569,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4577,5 +4576,5 @@ } - if ( r_vci_rsp_data_error.read() ) // bus error + if (r_vci_rsp_data_error.read()) // bus error { r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; @@ -4587,6 +4586,6 @@ break; } - else if ( r_vci_rsp_fifo_dcache.rok() ) // response available - { + else if (r_vci_rsp_fifo_dcache.rok()) // response available + { // consume response vci_rsp_fifo_dcache_get = true; @@ -4594,13 +4593,13 @@ m_drsp.rdata = r_vci_rsp_fifo_dcache.read(); r_dcache_fsm = DCACHE_IDLE; - } + } break; } ////////////////////////// - case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory - // before handling a processor WRITE or SC request - // Input argument is r_dcache_dirty_paddr - // In this first state, we get PTE value in dcache - // and post a CAS request to CMD FSM + case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory + // before handling a processor WRITE or SC request + // Input argument is r_dcache_dirty_paddr + // In this first state, we get PTE value in dcache + // and post a CAS request to CMD FSM { // get PTE in dcache @@ -4612,13 +4611,13 @@ #ifdef INSTRUMENTATION -m_cpt_dcache_data_read++; -m_cpt_dcache_dir_read++; -#endif - r_dcache.read( r_dcache_dirty_paddr.read(), - &pte, - &way, - &set, - &word, - &state ); + m_cpt_dcache_data_read++; + m_cpt_dcache_dir_read++; +#endif + r_dcache.read(r_dcache_dirty_paddr.read(), + &pte, + &way, + &set, + &word, + &state); assert( (state == CACHE_SLOT_STATE_VALID) and @@ -4626,9 +4625,9 @@ // request CAS transaction to CMD_FSM - r_dcache_dirty_way = way; - r_dcache_dirty_set = set; + r_dcache_dirty_way = way; + r_dcache_dirty_set = set; // check llsc reservation buffer - if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read() ) + if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read()) r_dcache_llsc_valid = false; @@ -4641,26 +4640,26 @@ #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " CAS request" << std::hex - << " / PTE_PADDR = " << r_dcache_dirty_paddr.read() - << " / PTE_VALUE = " << pte << std::dec - << " / SET = " << set - << " / WAY = " << way << std::endl; -} + if (m_debug_dcache_fsm) + { + std::cout << " CAS request" << std::hex + << " / PTE_PADDR = " << r_dcache_dirty_paddr.read() + << " / PTE_VALUE = " << pte << std::dec + << " / SET = " << set + << " / WAY = " << way << std::endl; + } #endif break; } /////////////////////// - case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit, - // and return to IDLE state when response is received. - // we don't care if the CAS is a failure: - // - if the CAS is a success, the coherence mechanism - // updates the local copy. - // - if the CAS is a failure, we just retry the write. + case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit, + // and return to IDLE state when response is received. + // we don't care if the CAS is a failure: + // - if the CAS is a success, the coherence mechanism + // updates the local copy. + // - if the CAS is a failure, we just retry the write. { // coherence clack request (from DSPIN CLACK) - if ( r_dcache_clack_req.read() ) + if (r_dcache_clack_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4670,5 +4669,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4677,5 +4676,5 @@ } - if ( r_vci_rsp_data_error.read() ) // bus error + if (r_vci_rsp_data_error.read()) // bus error { std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl; @@ -4683,5 +4682,5 @@ exit(0); } - else if ( r_vci_rsp_fifo_dcache.rok() ) // response available + else if (r_vci_rsp_fifo_dcache.rok()) // response available { vci_rsp_fifo_dcache_get = true; @@ -4689,9 +4688,9 @@ #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " CAS completed" << std::endl; -} + if (m_debug_dcache_fsm) + { + std::cout << " CAS completed" << std::endl; + } #endif } @@ -4707,24 +4706,24 @@ // The return state is defined in r_dcache_fsm_cc_save { - paddr_t paddr = r_cc_receive_dcache_nline.read() * m_dcache_words * 4; - paddr_t mask = ~((m_dcache_words<<2)-1); + paddr_t paddr = r_cc_receive_dcache_nline.read() * m_dcache_words * 4; + paddr_t mask = ~((m_dcache_words << 2) - 1); // CLACK handler // We switch the directory slot to EMPTY state and reset // r_dcache_miss_clack if the cleanup ack is matching a pending miss. - if ( r_dcache_clack_req.read() ) - { - if ( m_dreq.valid ) m_cost_data_miss_frz++; + if (r_dcache_clack_req.read()) + { + if (m_dreq.valid ) m_cost_data_miss_frz++; #ifdef INSTRUMENTATION -m_cpt_dcache_dir_write++; -#endif - r_dcache.write_dir( 0, - r_dcache_clack_way.read(), - r_dcache_clack_set.read(), - CACHE_SLOT_STATE_EMPTY); - - if ( (r_dcache_miss_set.read() == r_dcache_clack_set.read()) and - (r_dcache_miss_way.read() == r_dcache_clack_way.read()) ) + m_cpt_dcache_dir_write++; +#endif + r_dcache.write_dir(0, + r_dcache_clack_way.read(), + r_dcache_clack_set.read(), + CACHE_SLOT_STATE_EMPTY); + + if ((r_dcache_miss_set.read() == r_dcache_clack_set.read()) and + (r_dcache_miss_way.read() == r_dcache_clack_way.read())) { r_dcache_miss_clack = false; @@ -4737,12 +4736,12 @@ #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " CLACK for PADDR " << paddr - << " Switch slot to EMPTY state : " - << " set = " << r_dcache_clack_set.read() - << " / way = " << r_dcache_clack_way.read() << std::endl; -} + if (m_debug_dcache_fsm) + { + std::cout << " CLACK for PADDR " << paddr + << " Switch slot to EMPTY state : " + << " set = " << r_dcache_clack_set.read() + << " / way = " << r_dcache_clack_way.read() << std::endl; + } #endif break; @@ -4754,6 +4753,6 @@ // Match between MISS address and CC address if (r_cc_receive_dcache_req.read() and - ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT ) or - (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT ) or + ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT) or + (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))) // matching @@ -4766,6 +4765,6 @@ if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) { - r_dcache_fsm = DCACHE_CC_UPDT; - r_dcache_cc_word = r_cc_receive_word_idx.read(); + r_dcache_fsm = DCACHE_CC_UPDT; + r_dcache_cc_word = r_cc_receive_word_idx.read(); // just pop the fifo , don't write in icache @@ -4780,10 +4779,10 @@ #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " Coherence request matching a pending miss:" - << " PADDR = " << std::hex << paddr << std::endl; -} + if (m_debug_dcache_fsm) + { + std::cout << " Coherence request matching a pending miss:" + << " PADDR = " << std::hex << paddr << std::endl; + } #endif } @@ -4797,16 +4796,16 @@ #ifdef INSTRUMENTATION -m_cpt_dcache_dir_read++; -#endif - r_dcache.read_dir( paddr, - &state, - &way, - &set, - &word ); // unused + m_cpt_dcache_dir_read++; +#endif + r_dcache.read_dir(paddr, + &state, + &way, + &set, + &word); // unused r_dcache_cc_way = way; r_dcache_cc_set = set; - if ( state == CACHE_SLOT_STATE_VALID) // hit + if (state == CACHE_SLOT_STATE_VALID) // hit { // need to update the cache state @@ -4817,7 +4816,7 @@ r_dcache_cc_word = r_cc_receive_word_idx.read(); } - else if ( r_cc_receive_dcache_type.read() == CC_TYPE_INVAL ) // hit inval - { - r_dcache_fsm = DCACHE_CC_INVAL; + else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval + { + r_dcache_fsm = DCACHE_CC_INVAL; } } @@ -4825,8 +4824,8 @@ { // multicast acknowledgement required in case of update - if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) - { - r_dcache_fsm = DCACHE_CC_UPDT; - r_dcache_cc_word = r_cc_receive_word_idx.read(); + if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) + { + r_dcache_fsm = DCACHE_CC_UPDT; + r_dcache_cc_word = r_cc_receive_word_idx.read(); // just pop the fifo , don't write in icache @@ -4836,17 +4835,17 @@ { r_cc_receive_dcache_req = false; - r_dcache_fsm = r_dcache_fsm_cc_save.read(); + r_dcache_fsm = r_dcache_fsm_cc_save.read(); } } #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " Coherence request received:" - << " PADDR = " << std::hex << paddr - << " / TYPE = " << std::dec << r_cc_receive_dcache_type.read() - << " / HIT = " << (state == CACHE_SLOT_STATE_VALID) << std::endl; -} + if (m_debug_dcache_fsm) + { + std::cout << " Coherence request received:" + << " PADDR = " << std::hex << paddr + << " / TYPE = " << std::dec << r_cc_receive_dcache_type.read() + << " / HIT = " << (state == CACHE_SLOT_STATE_VALID) << std::endl; + } #endif @@ -4858,40 +4857,40 @@ // TLBs { - size_t way = r_dcache_cc_way.read(); - size_t set = r_dcache_cc_set.read(); - - if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval - { - r_dcache_in_tlb[way*m_dcache_sets+set] = false; - r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); - r_dcache_tlb_inval_set = 0; - r_dcache_fsm_scan_save = r_dcache_fsm.read(); - r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; - break; - } - - if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush + size_t way = r_dcache_cc_way.read(); + size_t set = r_dcache_cc_set.read(); + + if (r_dcache_in_tlb[way * m_dcache_sets + set]) // selective TLB inval + { + r_dcache_in_tlb[way * m_dcache_sets + set] = false; + r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); + r_dcache_tlb_inval_set = 0; + r_dcache_fsm_scan_save = r_dcache_fsm.read(); + r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; + break; + } + + if (r_dcache_contains_ptd[way * m_dcache_sets + set]) // TLB flush { r_itlb.reset(); r_dtlb.reset(); - r_dcache_contains_ptd[way*m_dcache_sets+set] = false; + r_dcache_contains_ptd[way * m_dcache_sets + set] = false; #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " Flush DTLB & ITLB" << std::endl; -} -#endif - } - - assert (not r_dcache_cc_send_req.read() && + if (m_debug_dcache_fsm) + { + std::cout << " Flush DTLB & ITLB" << std::endl; + } +#endif + } + + assert(not r_dcache_cc_send_req.read() && "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req " "must not be set"); // Switch slot state to ZOMBI and send CLEANUP command - r_dcache.write_dir( way, - set, - CACHE_SLOT_STATE_ZOMBI ); + r_dcache.write_dir(way, + set, + CACHE_SLOT_STATE_ZOMBI); // coherence request completed @@ -4904,25 +4903,25 @@ #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " Switch slot to EMPTY state:" << std::dec - << " / WAY = " << way - << " / SET = " << set << std::endl; -} + if (m_debug_dcache_fsm) + { + std::cout << " Switch slot to EMPTY state:" << std::dec + << " / WAY = " << way + << " / SET = " << set << std::endl; + } #endif break; } /////////////////// - case DCACHE_CC_UPDT: // hit update: write one word per cycle, - // after possible invalidation of copies in TLBs - { - size_t word = r_dcache_cc_word.read(); - size_t way = r_dcache_cc_way.read(); - size_t set = r_dcache_cc_set.read(); - - if ( r_dcache_in_tlb[way*m_dcache_sets+set] ) // selective TLB inval - { - r_dcache_in_tlb[way*m_dcache_sets+set] = false; + case DCACHE_CC_UPDT: // hit update: write one word per cycle, + // after possible invalidation of copies in TLBs + { + size_t word = r_dcache_cc_word.read(); + size_t way = r_dcache_cc_way.read(); + size_t set = r_dcache_cc_set.read(); + + if (r_dcache_in_tlb[way * m_dcache_sets + set]) // selective TLB inval + { + r_dcache_in_tlb[way * m_dcache_sets + set] = false; r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); r_dcache_tlb_inval_set = 0; @@ -4933,16 +4932,16 @@ } - if ( r_dcache_contains_ptd[way*m_dcache_sets+set] ) // TLB flush + if (r_dcache_contains_ptd[way * m_dcache_sets + set]) // TLB flush { r_itlb.reset(); r_dtlb.reset(); - r_dcache_contains_ptd[way*m_dcache_sets+set] = false; + r_dcache_contains_ptd[way * m_dcache_sets + set] = false; #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " Flush DTLB & ITLB" << std::endl; -} + if (m_debug_dcache_fsm) + { + std::cout << " Flush DTLB & ITLB" << std::endl; + } #endif } @@ -4952,5 +4951,5 @@ "must not be set"); - if ( not r_cc_receive_updt_fifo_be.rok() ) break; + if (not r_cc_receive_updt_fifo_be.rok()) break; if (r_dcache_cc_need_write.read()) @@ -4958,28 +4957,28 @@ #ifdef INSTRUMENTATION -m_cpt_dcache_data_write++; -#endif - r_dcache.write( way, - set, - word, - r_cc_receive_updt_fifo_data.read(), - r_cc_receive_updt_fifo_be.read() ); + m_cpt_dcache_data_write++; +#endif + r_dcache.write(way, + set, + word, + r_cc_receive_updt_fifo_data.read(), + r_cc_receive_updt_fifo_be.read()); r_dcache_cc_word = word + 1; #if DEBUG_DCACHE -if ( m_debug_dcache_fsm ) -{ - std::cout << " Write one word" << std::dec - << " / WAY = " << way - << " / SET = " << set - << " / WORD = " << word - << " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl; -} -#endif - } - - if ( r_cc_receive_updt_fifo_eop.read() ) // last word + if (m_debug_dcache_fsm) + { + std::cout << " Write one word" << std::dec + << " / WAY = " << way + << " / SET = " << set + << " / WORD = " << word + << " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl; + } +#endif + } + + if (r_cc_receive_updt_fifo_eop.read()) // last word { // no need to write in the cache anymore @@ -4994,5 +4993,4 @@ r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read(); r_dcache_cc_send_type = CC_TYPE_MULTI_ACK; - r_dcache_fsm = r_dcache_fsm_cc_save.read(); } @@ -5004,57 +5002,57 @@ } /////////////////////////// - case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB - // It makes assumption: m_itlb_sets == m_dtlb_sets - // All ways are handled in parallel. - // We enter this state when a DCACHE line is modified, - // and there is a copy in itlb or dtlb. - // It can be caused by: - // - a coherence inval or updt transaction, - // - a line inval caused by a cache miss - // - a processor XTN inval request, - // - a WRITE hit, - // - a Dirty bit update - // Input arguments are: - // - r_dcache_tlb_inval_line - // - r_dcache_tlb_inval_set - // - r_dcache_fsm_scan_save - { - paddr_t line = r_dcache_tlb_inval_line.read(); - size_t set = r_dcache_tlb_inval_set.read(); - size_t way; - bool ok; - - for ( way = 0 ; way < m_itlb_ways ; way++ ) - { - ok = r_itlb.inval( line, way, set ); + case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB + // It makes assumption: m_itlb_sets == m_dtlb_sets + // All ways are handled in parallel. + // We enter this state when a DCACHE line is modified, + // and there is a copy in itlb or dtlb. + // It can be caused by: + // - a coherence inval or updt transaction, + // - a line inval caused by a cache miss + // - a processor XTN inval request, + // - a WRITE hit, + // - a Dirty bit update + // Input arguments are: + // - r_dcache_tlb_inval_line + // - r_dcache_tlb_inval_set + // - r_dcache_fsm_scan_save + { + paddr_t line = r_dcache_tlb_inval_line.read(); + size_t set = r_dcache_tlb_inval_set.read(); + size_t way; + bool ok; + + for (way = 0; way < m_itlb_ways; way++) + { + ok = r_itlb.inval(line, way, set); #if DEBUG_DCACHE -if ( m_debug_dcache_fsm and ok ) -{ - std::cout << " Invalidate ITLB entry:" << std::hex - << " line = " << line << std::dec - << " / set = " << set - << " / way = " << way << std::endl; -} -#endif - } - - for ( way = 0 ; way < m_dtlb_ways ; way++ ) - { - ok = r_dtlb.inval( line, way, set ); + if (m_debug_dcache_fsm and ok) + { + std::cout << " Invalidate ITLB entry:" << std::hex + << " line = " << line << std::dec + << " / set = " << set + << " / way = " << way << std::endl; + } +#endif + } + + for (way = 0; way < m_dtlb_ways; way++) + { + ok = r_dtlb.inval( line, way, set); #if DEBUG_DCACHE -if ( m_debug_dcache_fsm and ok ) -std::cout << " " - << " Invalidate DTLB entry" << std::hex - << " / line = " << line << std::dec - << " / set = " << set - << " / way = " << way << std::endl; + if (m_debug_dcache_fsm and ok) + std::cout << " " + << " Invalidate DTLB entry" << std::hex + << " / line = " << line << std::dec + << " / set = " << set + << " / way = " << way << std::endl; #endif } // return to the calling state when TLB inval completed - if ( r_dcache_tlb_inval_set.read() == (m_dtlb_sets-1) ) + if (r_dcache_tlb_inval_set.read() == (m_dtlb_sets - 1)) { r_dcache_fsm = r_dcache_fsm_scan_save.read(); @@ -5075,9 +5073,9 @@ // The simulation exit if the number of consecutive frozen cycles // is larger than the m_max_frozen_cycles (constructor parameter) - if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) ) - { - m_cpt_frz_cycles++; // used for instrumentation - m_cpt_stop_simulation++; // used for debug - if ( m_cpt_stop_simulation > m_max_frozen_cycles ) + if ((m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid)) + { + m_cpt_frz_cycles++; // used for instrumentation + m_cpt_stop_simulation++; // used for debug + if (m_cpt_stop_simulation > m_max_frozen_cycles) { std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl @@ -5096,7 +5094,7 @@ /////////// execute one iss cycle ///////////////////////////////// { - uint32_t it = 0; - for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it |= (1<" - << " / dmiss_req = " << dcache_miss_req - << " / imiss_req = " << icache_miss_req - << std::endl; -} + if (m_debug_cmd_fsm ) + { + std::cout << " " + << " / dmiss_req = " << dcache_miss_req + << " / imiss_req = " << icache_miss_req + << std::endl; + } #endif break; @@ -5264,11 +5252,11 @@ case CMD_DATA_WRITE: { - if ( p_vci.cmdack.read() ) + if (p_vci.cmdack.read()) { r_vci_cmd_cpt = r_vci_cmd_cpt + 1; if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent { - r_vci_cmd_fsm = CMD_IDLE ; - r_wbuf.sent() ; + r_vci_cmd_fsm = CMD_IDLE; + r_wbuf.sent(); } } @@ -5280,5 +5268,5 @@ { // The CAS and SC VCI commands contain two flits - if ( p_vci.cmdack.read() ) + if (p_vci.cmdack.read()) { r_vci_cmd_cpt = r_vci_cmd_cpt + 1; @@ -5296,5 +5284,5 @@ { // all read VCI commands contain one single flit - if ( p_vci.cmdack.read() ) { + if (p_vci.cmdack.read()) { r_vci_cmd_fsm = CMD_IDLE; } @@ -5331,42 +5319,42 @@ ////////////////////////////////////////////////////////////////////////// - switch ( r_vci_rsp_fsm.read() ) + switch (r_vci_rsp_fsm.read()) { ////////////// case RSP_IDLE: { - if ( p_vci.rspval.read() ) + if (p_vci.rspval.read()) { r_vci_rsp_cpt = 0; - if ( (p_vci.rpktid.read() & 0x7) == TYPE_DATA_UNC ) + if ((p_vci.rpktid.read() & 0x7) == TYPE_DATA_UNC) { r_vci_rsp_fsm = RSP_DATA_UNC; } - else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS ) + else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS) { r_vci_rsp_fsm = RSP_DATA_MISS; } - else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC ) + else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC) { r_vci_rsp_fsm = RSP_INS_UNC; } - else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS ) + else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS) { r_vci_rsp_fsm = RSP_INS_MISS; } - else if ( (p_vci.rpktid.read() & 0x7) == TYPE_WRITE ) + else if ((p_vci.rpktid.read() & 0x7) == TYPE_WRITE) { r_vci_rsp_fsm = RSP_DATA_WRITE; } - else if ( (p_vci.rpktid.read() & 0x7) == TYPE_CAS ) + else if ((p_vci.rpktid.read() & 0x7) == TYPE_CAS) { r_vci_rsp_fsm = RSP_DATA_UNC; } - else if ( (p_vci.rpktid.read() & 0x7) == TYPE_LL ) + else if ((p_vci.rpktid.read() & 0x7) == TYPE_LL) { r_vci_rsp_fsm = RSP_DATA_LL; } - else if ( (p_vci.rpktid.read() & 0x7) == TYPE_SC ) + else if ((p_vci.rpktid.read() & 0x7) == TYPE_SC) { r_vci_rsp_fsm = RSP_DATA_UNC; @@ -5382,16 +5370,16 @@ case RSP_INS_MISS: { - if ( p_vci.rspval.read() ) - { - if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported + if (p_vci.rspval.read()) + { + if ((p_vci.rerror.read() & 0x1) != 0) // error reported { r_vci_rsp_ins_error = true; - if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE; + if (p_vci.reop.read()) r_vci_rsp_fsm = RSP_IDLE; } else // no error reported { - if ( r_vci_rsp_fifo_icache.wok() ) + if (r_vci_rsp_fifo_icache.wok()) { - if ( r_vci_rsp_cpt.read() >= m_icache_words ) + if (r_vci_rsp_cpt.read() >= m_icache_words) { std::cout << "ERROR in VCI_CC_VCACHE " << name() @@ -5400,10 +5388,10 @@ exit(0); } - r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; - vci_rsp_fifo_icache_put = true, - vci_rsp_fifo_icache_data = p_vci.rdata.read(); - if ( p_vci.reop.read() ) + r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; + vci_rsp_fifo_icache_put = true, + vci_rsp_fifo_icache_data = p_vci.rdata.read(); + if (p_vci.reop.read()) { - if ( r_vci_rsp_cpt.read() != (m_icache_words - 1) ) + if (r_vci_rsp_cpt.read() != (m_icache_words - 1)) { std::cout << "ERROR in VCI_CC_VCACHE " << name() @@ -5412,5 +5400,5 @@ exit(0); } - r_vci_rsp_fsm = RSP_IDLE; + r_vci_rsp_fsm = RSP_IDLE; } } @@ -5422,10 +5410,10 @@ case RSP_INS_UNC: { - if (p_vci.rspval.read() ) - { - assert( p_vci.reop.read() and + if (p_vci.rspval.read()) + { + assert(p_vci.reop.read() and "illegal VCI response packet for uncachable instruction"); - if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported + if ((p_vci.rerror.read() & 0x1) != 0) // error reported { r_vci_rsp_ins_error = true; @@ -5434,8 +5422,8 @@ else // no error reported { - if ( r_vci_rsp_fifo_icache.wok()) + if (r_vci_rsp_fifo_icache.wok()) { - vci_rsp_fifo_icache_put = true; - vci_rsp_fifo_icache_data = p_vci.rdata.read(); + vci_rsp_fifo_icache_put = true; + vci_rsp_fifo_icache_data = p_vci.rdata.read(); r_vci_rsp_fsm = RSP_IDLE; } @@ -5447,27 +5435,27 @@ case RSP_DATA_MISS: { - if ( p_vci.rspval.read() ) - { - if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported + if (p_vci.rspval.read()) + { + if ((p_vci.rerror.read() & 0x1) != 0) // error reported { r_vci_rsp_data_error = true; - if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE; + if (p_vci.reop.read()) r_vci_rsp_fsm = RSP_IDLE; } else // no error reported { - if ( r_vci_rsp_fifo_dcache.wok() ) + if (r_vci_rsp_fifo_dcache.wok()) { - assert( (r_vci_rsp_cpt.read() < m_dcache_words) and + assert((r_vci_rsp_cpt.read() < m_dcache_words) and "The VCI response packet for data miss is too long"); - r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; - vci_rsp_fifo_dcache_put = true, - vci_rsp_fifo_dcache_data = p_vci.rdata.read(); - if ( p_vci.reop.read() ) + r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; + vci_rsp_fifo_dcache_put = true, + vci_rsp_fifo_dcache_data = p_vci.rdata.read(); + if (p_vci.reop.read()) { - assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and + assert((r_vci_rsp_cpt.read() == m_dcache_words - 1) and "The VCI response packet for data miss is too short"); - r_vci_rsp_fsm = RSP_IDLE; + r_vci_rsp_fsm = RSP_IDLE; } } @@ -5479,20 +5467,20 @@ case RSP_DATA_UNC: { - if (p_vci.rspval.read() ) - { - assert( p_vci.reop.read() and + if (p_vci.rspval.read()) + { + assert(p_vci.reop.read() and "illegal VCI response packet for uncachable read data"); - if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported + if ((p_vci.rerror.read() & 0x1) != 0) // error reported { r_vci_rsp_data_error = true; r_vci_rsp_fsm = RSP_IDLE; } - else // no error reported + else // no error reported { - if ( r_vci_rsp_fifo_dcache.wok()) + if (r_vci_rsp_fifo_dcache.wok()) { - vci_rsp_fifo_dcache_put = true; - vci_rsp_fifo_dcache_data = p_vci.rdata.read(); + vci_rsp_fifo_dcache_put = true; + vci_rsp_fifo_dcache_data = p_vci.rdata.read(); r_vci_rsp_fsm = RSP_IDLE; } @@ -5504,7 +5492,7 @@ case RSP_DATA_LL: { - if ( p_vci.rspval.read() ) - { - if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported + if (p_vci.rspval.read()) + { + if ((p_vci.rerror.read() & 0x1) != 0) // error reported { r_vci_rsp_data_error = true; @@ -5514,5 +5502,5 @@ if (r_vci_rsp_cpt.read() == 0) //first flit { - if(r_vci_rsp_fifo_dcache.wok()) + if (r_vci_rsp_fifo_dcache.wok()) { assert(!p_vci.reop.read() && @@ -5526,5 +5514,5 @@ else // last flit { - if(r_vci_rsp_fifo_dcache.wok()) + if (r_vci_rsp_fifo_dcache.wok()) { assert(p_vci.reop.read() && @@ -5544,11 +5532,11 @@ if (p_vci.rspval.read()) { - assert( p_vci.reop.read() and + assert(p_vci.reop.read() and "a VCI response packet must contain one flit for a write transaction"); r_vci_rsp_fsm = RSP_IDLE; - uint32_t wbuf_index = p_vci.rtrdid.read(); + uint32_t wbuf_index = p_vci.rtrdid.read(); r_wbuf.completed(wbuf_index); - if ( (p_vci.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr(); + if ((p_vci.rerror.read() & 0x1) != 0) r_iss.setWriteBerr(); } break; @@ -5563,5 +5551,5 @@ // soon as the request has been sent. ///////////////////////////////////////////////////////////////////////////////////// - switch ( r_cc_send_fsm.read() ) + switch (r_cc_send_fsm.read()) { /////////////////////////// @@ -5575,5 +5563,5 @@ /////////////////////////////////////////////////////// bool update_last_client = r_cc_send_last_client.read(); - if ( r_cc_send_last_client.read() == 0 ) // last client was dcache + if (r_cc_send_last_client.read() == 0) // last client was dcache { if (r_icache_cc_send_req.read()) // request from icache @@ -5591,17 +5579,17 @@ { // the new client is dcache and has a cleanup request - if ( (update_last_client == 0) and + if ((update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP)) r_cc_send_fsm = CC_SEND_CLEANUP_1; // the new client is dcache and has a multi acknowledgement request - else if ( (update_last_client == 0) and + else if ((update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK)) r_cc_send_fsm = CC_SEND_MULTI_ACK; // the new client is icache and has a cleanup request - else if ( (update_last_client == 1) and + else if ((update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_CLEANUP)) r_cc_send_fsm = CC_SEND_CLEANUP_1; // the new client is icache and has a multi acknowledgement request - else if ( (update_last_client == 1) and + else if ((update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK)) r_cc_send_fsm = CC_SEND_MULTI_ACK; @@ -5638,7 +5626,7 @@ { // wait for the flit to be consumed - if(p_dspin_p2m.read.read()) - { - if(r_cc_send_last_client.read() == 0) // dcache active request + if (p_dspin_p2m.read.read()) + { + if (r_cc_send_last_client.read() == 0) // dcache active request r_dcache_cc_send_req = false; // reset dcache request else // icache active request @@ -5661,5 +5649,5 @@ // - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE) ////////////////////////////////////////////////////////////////////////////// - switch( r_cc_receive_fsm.read() ) + switch (r_cc_receive_fsm.read()) { ///////////////////// @@ -5722,10 +5710,10 @@ // request dcache to handle the BROADCAST r_cc_receive_dcache_req = true; - r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data, + r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data, DspinDhccpParam::BROADCAST_NLINE); r_cc_receive_dcache_type = CC_TYPE_INVAL; // request icache to handle the BROADCAST r_cc_receive_icache_req = true; - r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data, + r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data, DspinDhccpParam::BROADCAST_NLINE); r_cc_receive_icache_type = CC_TYPE_INVAL; @@ -5758,5 +5746,5 @@ // for data INVAL, wait for dcache to take the request if (p_dspin_m2p.write.read() and - not r_cc_receive_dcache_req.read() ) + not r_cc_receive_dcache_req.read()) { // request dcache to handle the INVAL @@ -5777,5 +5765,5 @@ // for ins INVAL, wait for icache to take the request if (p_dspin_m2p.write.read() and - not r_cc_receive_icache_req.read() ) + not r_cc_receive_icache_req.read()) { // request icache to handle the INVAL @@ -5798,5 +5786,5 @@ if (not r_cc_receive_dcache_req.read()) { - r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX); + r_cc_receive_dcache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX); r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_NLINE; break; @@ -5813,5 +5801,5 @@ if (not r_cc_receive_icache_req.read()) { - r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX); + r_cc_receive_icache_updt_tab_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_UPDT_INDEX); r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_NLINE; break; @@ -5827,11 +5815,11 @@ // for data INVAL, wait for dcache to take the request and fifo to // be empty - if ( r_cc_receive_updt_fifo_be.empty() and - p_dspin_m2p.write.read() ) - { - r_cc_receive_dcache_req = true; - r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE); - r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX); - r_cc_receive_dcache_type = CC_TYPE_UPDT; + if (r_cc_receive_updt_fifo_be.empty() and + p_dspin_m2p.write.read()) + { + r_cc_receive_dcache_req = true; + r_cc_receive_dcache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE); + r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX); + r_cc_receive_dcache_type = CC_TYPE_UPDT; // get back to idle state r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_DATA; @@ -5847,11 +5835,11 @@ // for ins INVAL, wait for icache to take the request and fifo to be // empty - if ( r_cc_receive_updt_fifo_be.empty() and - p_dspin_m2p.write.read() ) - { - r_cc_receive_icache_req = true; - r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE); - r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX); - r_cc_receive_icache_type = CC_TYPE_UPDT; + if (r_cc_receive_updt_fifo_be.empty() and + p_dspin_m2p.write.read()) + { + r_cc_receive_icache_req = true; + r_cc_receive_icache_nline = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_NLINE); + r_cc_receive_word_idx = DspinDhccpParam::dspin_get(receive_data,DspinDhccpParam::MULTI_UPDT_WORD_INDEX); + r_cc_receive_icache_type = CC_TYPE_UPDT; // get back to idle state r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_DATA; @@ -5872,5 +5860,5 @@ cc_receive_updt_fifo_eop = receive_eop; cc_receive_updt_fifo_put = true; - if ( receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE; + if (receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE; } break; @@ -5888,5 +5876,5 @@ cc_receive_updt_fifo_eop = receive_eop; cc_receive_updt_fifo_put = true; - if ( receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE; + if (receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE; } break; @@ -5900,11 +5888,11 @@ DspinDhccpParam::CLACK_TYPE); - size_t clack_way = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), + size_t clack_way = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), DspinDhccpParam::CLACK_WAY); - size_t clack_set = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), + size_t clack_set = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), DspinDhccpParam::CLACK_SET); - bool dspin_clack_get = false; + bool dspin_clack_get = false; bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA); bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST); @@ -5913,13 +5901,15 @@ { // CLACK DATA: Send request to DCACHE FSM - if (dcache_clack_request and not r_dcache_clack_req.read()){ + if (dcache_clack_request and not r_dcache_clack_req.read()) + { r_dcache_clack_req = true; - r_dcache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1); - r_dcache_clack_set = clack_set & ((1ULL<<(uint32_log2(m_dcache_sets)))-1); + r_dcache_clack_way = clack_way & ((1ULL << (uint32_log2(m_dcache_ways))) - 1); + r_dcache_clack_set = clack_set & ((1ULL << (uint32_log2(m_dcache_sets))) - 1); dspin_clack_get = true; } // CLACK INST: Send request to ICACHE FSM - else if (icache_clack_request and not r_icache_clack_req.read()){ + else if (icache_clack_request and not r_icache_clack_req.read()) + { r_icache_clack_req = true; r_icache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1); @@ -5971,5 +5961,5 @@ bool is_sc_or_cas = (r_vci_cmd_fsm.read() == CMD_DATA_CAS) or - (r_vci_cmd_fsm.read() == CMD_DATA_SC ); + (r_vci_cmd_fsm.read() == CMD_DATA_SC); p_vci.pktid = 0; @@ -5981,8 +5971,8 @@ p_vci.cfixed = false; - if ( m_monitor_ok ) { - if ( p_vci.cmdack.read() == true and p_vci.cmdval == true) { + if (m_monitor_ok) { + if (p_vci.cmdack.read() == true and p_vci.cmdval == true) { if (((p_vci.address.read()) >= m_monitor_base) and - ((p_vci.address.read()) < m_monitor_base + m_monitor_length) ) { + ((p_vci.address.read()) < m_monitor_base + m_monitor_length)) { std::cout << "CC_VCACHE Monitor " << name() << std::hex << " Access type = " << vci_cmd_type_str[p_vci.cmd.read()] @@ -5990,5 +5980,5 @@ << " : address = " << p_vci.address.read() << " / be = " << p_vci.be.read(); - if ( p_vci.cmd.read() == vci_param::CMD_WRITE ) { + if (p_vci.cmd.read() == vci_param::CMD_WRITE ) { std::cout << " / data = " << p_vci.wdata.read(); } @@ -5998,5 +5988,5 @@ } - switch ( r_vci_cmd_fsm.read() ) { + switch (r_vci_cmd_fsm.read()) { case CMD_IDLE: @@ -6099,6 +6089,6 @@ p_vci.cmdval = true; p_vci.address = r_dcache_vci_paddr.read() & ~0x3; - if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_llsc_key.read(); - else p_vci.wdata = r_dcache_vci_sc_data.read(); + if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_dcache_llsc_key.read(); + else p_vci.wdata = r_dcache_vci_sc_data.read(); p_vci.be = 0xF; p_vci.trdid = 0; @@ -6112,6 +6102,6 @@ p_vci.cmdval = true; p_vci.address = r_dcache_vci_paddr.read() & ~0x3; - if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_vci_cas_old.read(); - else p_vci.wdata = r_dcache_vci_cas_new.read(); + if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_dcache_vci_cas_old.read(); + else p_vci.wdata = r_dcache_vci_cas_new.read(); p_vci.be = 0xF; p_vci.trdid = 0; @@ -6126,5 +6116,5 @@ // it depends on the VCI_RSP FSM - switch (r_vci_rsp_fsm.read() ) + switch (r_vci_rsp_fsm.read()) { case RSP_DATA_WRITE : p_vci.rspack = true; break; @@ -6142,5 +6132,5 @@ uint64_t dspin_send_data = 0; - switch ( r_cc_send_fsm.read() ) + switch (r_cc_send_fsm.read()) { ////////////////// @@ -6154,7 +6144,4 @@ { // initialize dspin send data -// DspinDhccpParam::dspin_set(dspin_send_data, -// 0, -// DspinDhccpParam::P2M_EOP); DspinDhccpParam::dspin_set(dspin_send_data, m_cc_global_id, @@ -6164,5 +6151,5 @@ DspinDhccpParam::P2M_BC); - if(r_cc_send_last_client.read() == 0) // dcache active request + if (r_cc_send_last_client.read() == 0) // dcache active request { uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read() @@ -6197,5 +6184,5 @@ DspinDhccpParam::dspin_set(dspin_send_data, - (r_icache_cc_send_nline.read() & 0x300000000ULL)>>32, + (r_icache_cc_send_nline.read() & 0x300000000ULL) >> 32, DspinDhccpParam::CLEANUP_NLINE_MSB); @@ -6218,9 +6205,6 @@ { // initialize dspin send data -// DspinDhccpParam::dspin_set(dspin_send_data, -// 1, -// DspinDhccpParam::P2M_EOP); - - if(r_cc_send_last_client.read() == 0) // dcache active request + + if (r_cc_send_last_client.read() == 0) // dcache active request { DspinDhccpParam::dspin_set(dspin_send_data, @@ -6244,7 +6228,4 @@ { // initialize dspin send data -// DspinDhccpParam::dspin_set(dspin_send_data, -// 1, -// DspinDhccpParam::P2M_EOP); DspinDhccpParam::dspin_set(dspin_send_data, 0, @@ -6254,5 +6235,5 @@ DspinDhccpParam::P2M_TYPE); - if(r_cc_send_last_client.read() == 0) // dcache active request + if (r_cc_send_last_client.read() == 0) // dcache active request { uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read() @@ -6294,5 +6275,5 @@ // Receive coherence packets // It depends on the CC_RECEIVE FSM - switch( r_cc_receive_fsm.read() ) + switch (r_cc_receive_fsm.read()) { ///////////////////// @@ -6350,5 +6331,5 @@ case CC_RECEIVE_INS_UPDT_HEADER: { - if ( not r_cc_receive_icache_req.read()) + if (not r_cc_receive_icache_req.read()) p_dspin_m2p.read = true; else @@ -6360,5 +6341,5 @@ case CC_RECEIVE_INS_UPDT_NLINE: { - if(r_cc_receive_updt_fifo_be.empty()) + if (r_cc_receive_updt_fifo_be.empty()) p_dspin_m2p.read = true; else @@ -6382,5 +6363,5 @@ DspinDhccpParam::CLACK_TYPE); - bool dspin_clack_get = false; + bool dspin_clack_get = false; bool dcache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_DATA); bool icache_clack_request = (clack_type == DspinDhccpParam::TYPE_CLACK_INST); @@ -6411,12 +6392,12 @@ // This version of monitor print both Read and Write request { - m_monitor_ok = true; - m_monitor_base = base; - m_monitor_length = length; + m_monitor_ok = true; + m_monitor_base = base; + m_monitor_length = length; } tmpl(void)::stop_monitor() { - m_monitor_ok = false; + m_monitor_ok = false; } Index: /trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp =================================================================== --- /trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 788) +++ /trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 789) @@ -827,7 +827,9 @@ { m_cpt_reset_count = m_cpt_cycles; + m_cpt_read_local = 0; m_cpt_read_remote = 0; m_cpt_read_cost = 0; + m_cpt_write_local = 0; m_cpt_write_remote = 0; @@ -835,28 +837,38 @@ m_cpt_write_flits_remote = 0; m_cpt_write_cost = 0; + m_cpt_ll_local = 0; m_cpt_ll_remote = 0; m_cpt_ll_cost = 0; + m_cpt_sc_local = 0; m_cpt_sc_remote = 0; m_cpt_sc_cost = 0; + m_cpt_cas_local = 0; m_cpt_cas_remote = 0; m_cpt_cas_cost = 0; + m_cpt_update = 0; m_cpt_update_local = 0; m_cpt_update_remote = 0; m_cpt_update_cost = 0; + m_cpt_minval = 0; m_cpt_minval_local = 0; m_cpt_minval_remote = 0; m_cpt_minval_cost = 0; + m_cpt_binval = 0; + m_cpt_write_broadcast = 0; + m_cpt_cleanup_local = 0; m_cpt_cleanup_remote = 0; m_cpt_cleanup_cost = 0; + m_cpt_read_miss = 0; m_cpt_write_miss = 0; m_cpt_write_dirty = 0; + m_cpt_trt_rb = 0; m_cpt_trt_full = 0; @@ -915,13 +927,17 @@ << "[080] BROADCAT INVAL = " << m_cpt_binval << std::endl << "[081] WRITE BROADCAST = " << m_cpt_write_broadcast << std::endl + << "[082] GETM BROADCAST = " << "0" << std::endl << std::endl << "[090] LOCAL CLEANUP = " << m_cpt_cleanup_local << std::endl << "[091] REMOTE CLEANUP = " << m_cpt_cleanup_remote << std::endl << "[092] CLNUP COST (FLITS * DIST) = " << m_cpt_cleanup_cost << std::endl - << "[093] CLEANUP DATA = " << "0" << std::endl + << "[093] LOCAL CLEANUP DATA = " << "0" << std::endl + << "[094] REMOTE CLEANUP DATA = " << "0" << std::endl + << "[095] CLEANUP DATA COST = " << "0" << std::endl << std::endl << "[100] READ MISS = " << m_cpt_read_miss << std::endl << "[101] WRITE MISS = " << m_cpt_write_miss << std::endl << "[102] WRITE DIRTY = " << m_cpt_write_dirty << std::endl + << "[103] GETM MISS = " << "0" << std::endl << std::endl << "[110] RD BLOCKED BY HIT IN TRT = " << m_cpt_trt_rb << std::endl @@ -933,56 +949,15 @@ << "[140] NCC TO CC (READ) = " << "0" << std::endl << "[141] NCC TO CC (WRITE) = " << "0" << std::endl + << std::endl + << "[150] LOCAL GETM = " << "0" << std::endl + << "[151] REMOTE GETM = " << "0" << std::endl + << "[152] GETM COST (FLITS * DIST) = " << "0" << std::endl + << std::endl + << "[160] LOCAL INVAL RO = " << "0" << std::endl + << "[161] REMOTE INVAL RO = " << "0" << std::endl + << "[162] INVAL RO COST = " << "0" << std::endl << std::endl; } - - if (stats) { - std::cout << "----------------------------------" << std::dec << std::endl; - std::cout << "--- Calculated Stats ---" << std::dec << std::endl; - std::cout << "----------------------------------" << std::dec << std::endl; - std::cout - << "[300] READ TOTAL = " << m_cpt_read_local + m_cpt_read_remote << std::endl - << "[301] READ RATE = " << (double) (m_cpt_read_local + m_cpt_read_remote) / m_cpt_cycles << std::endl - << "[302] LOCAL READ RATE = " << (double) m_cpt_read_local / m_cpt_cycles << std::endl - << "[303] REMOTE READ RATE = " << (double) m_cpt_read_remote / m_cpt_cycles << std::endl - << "[304] READ MISS RATE = " << (double) m_cpt_read_miss / (m_cpt_read_local + m_cpt_read_remote) << std::endl - << std::endl - << "[305] WRITE TOTAL = " << m_cpt_write_local + m_cpt_write_remote << std::endl - << "[306] WRITE RATE = " << (double) (m_cpt_write_local + m_cpt_write_remote) / m_cpt_cycles << std::endl - << "[307] LOCAL WRITE RATE = " << (double) m_cpt_write_local / m_cpt_cycles << std::endl - << "[308] REMOTE WRITE RATE = " << (double) m_cpt_write_remote / m_cpt_cycles << std::endl - << "[309] WRITE MISS RATE = " << (double) m_cpt_write_miss / (m_cpt_write_local + m_cpt_write_remote) << std::endl - << "[310] WRITE BURST TOTAL = " << m_cpt_write_flits_local + m_cpt_write_flits_remote << std::endl - << "[311] WRITE BURST AVERAGE = " << (double) (m_cpt_write_flits_local + m_cpt_write_flits_remote) / (m_cpt_write_local + m_cpt_write_remote) << std::endl - << "[312] LOCAL WRITE BURST AV. = " << (double) m_cpt_write_flits_local / (m_cpt_write_local + m_cpt_write_remote) << std::endl - << "[313] REMOTE WRITE BURST AV = " << (double) m_cpt_write_flits_remote / (m_cpt_write_local + m_cpt_write_remote) << std::endl - << std::endl - << "[314] UPDATE RATE = " << (double) m_cpt_update / m_cpt_cycles << std::endl - << "[315] AV. UPDATE PER UP REQ = " << (double) (m_cpt_update_local + m_cpt_update_remote) / m_cpt_update << std::endl - << "[316] AV. LOC UPDT PER UP REQ = " << (double) m_cpt_update_local / m_cpt_update << std::endl - << "[317] AV. REMOTE UPDT PER UP REQ = " << (double) m_cpt_update_remote / m_cpt_update << std::endl - << std::endl - << "[318] INVAL MULTICAST RATE = " << (double) m_cpt_minval / m_cpt_cycles << std::endl - << "[319] AVE. INVAL PER M_INV = " << (double) (m_cpt_minval_local + m_cpt_minval_remote) / m_cpt_minval << std::endl - << "[320] AV. LOC INV PER M_INV = " << (double) m_cpt_minval_local / m_cpt_minval << std::endl - << "[321] AV. REM INV PER M_INV = " << (double) m_cpt_minval_remote / m_cpt_minval << std::endl - << std::endl - << "[322] INVAL BROADCAST RATE = " << (double) m_cpt_binval / m_cpt_cycles << std::endl - << "[323] WRITE DIRTY RATE = " << (double) m_cpt_write_dirty / m_cpt_cycles << std::endl - << std::endl - << "[324] CLEANUP RATE = " << (double) (m_cpt_cleanup_local + m_cpt_cleanup_remote) / m_cpt_cycles << std::endl - << "[325] LOCAL CLEANUP RATE = " << (double) m_cpt_cleanup_local / m_cpt_cycles << std::endl - << "[326] REMOTE CLEANUP RATE = " << (double) m_cpt_cleanup_remote / m_cpt_cycles << std::endl - << "[327] LL RATE = " << (double) (m_cpt_ll_local + m_cpt_ll_remote) / m_cpt_cycles << std::endl - << "[328] LOCAL LL RATE = " << (double) m_cpt_ll_local / m_cpt_cycles << std::endl - << "[329] REMOTE LL RATE = " << (double) m_cpt_ll_remote / m_cpt_cycles << std::endl - << "[330] SC RATE = " << (double) (m_cpt_sc_local + m_cpt_sc_remote) / m_cpt_cycles << std::endl - << "[331] LOCAL SC RATE = " << (double) m_cpt_sc_local / m_cpt_cycles << std::endl - << "[332] REMOTE SC RATE = " << (double) m_cpt_sc_remote / m_cpt_cycles << std::endl - << "[333] CAS RATE = " << (double) (m_cpt_cas_local + m_cpt_cas_remote) / m_cpt_cycles << std::endl - << "[334] LOCAL CAS RATE = " << (double) m_cpt_cas_local / m_cpt_cycles << std::endl - << "[335] REMOTE CAS RATE = " << (double) m_cpt_cas_remote / m_cpt_cycles << std::endl - << std::endl - << std::endl; - } + // No more computed stats } @@ -1141,7 +1116,9 @@ m_cpt_cycles = 0; m_cpt_reset_count = 0; + m_cpt_read_local = 0; m_cpt_read_remote = 0; m_cpt_read_cost = 0; + m_cpt_write_local = 0; m_cpt_write_remote = 0; @@ -1149,34 +1126,42 @@ m_cpt_write_flits_remote = 0; m_cpt_write_cost = 0; + m_cpt_ll_local = 0; m_cpt_ll_remote = 0; m_cpt_ll_cost = 0; + m_cpt_sc_local = 0; m_cpt_sc_remote = 0; m_cpt_sc_cost = 0; + m_cpt_cas_local = 0; m_cpt_cas_remote = 0; m_cpt_cas_cost = 0; + m_cpt_update = 0; m_cpt_update_local = 0; m_cpt_update_remote = 0; m_cpt_update_cost = 0; + m_cpt_minval = 0; m_cpt_minval_local = 0; m_cpt_minval_remote = 0; m_cpt_minval_cost = 0; + m_cpt_binval = 0; + m_cpt_write_broadcast = 0; + m_cpt_cleanup_local = 0; m_cpt_cleanup_remote = 0; m_cpt_cleanup_cost = 0; - m_cpt_read_miss = 0; - m_cpt_write_miss = 0; - m_cpt_write_dirty = 0; - m_cpt_write_broadcast = 0; - m_cpt_trt_rb = 0; - m_cpt_trt_full = 0; - m_cpt_get = 0; - m_cpt_put = 0; + m_cpt_read_miss = 0; + m_cpt_write_miss = 0; + m_cpt_write_dirty = 0; + + m_cpt_trt_rb = 0; + m_cpt_trt_full = 0; + m_cpt_get = 0; + m_cpt_put = 0; return; @@ -1692,12 +1677,26 @@ // if (p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) { - if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_ll_local++; - else m_cpt_ll_remote++; - m_cpt_ll_cost += req_distance(p_vci_tgt.srcid.read()); // LL on a single word + if (is_local_req(p_vci_tgt.srcid.read())) + { + m_cpt_ll_local++; + } + else + { + m_cpt_ll_remote++; + } + // (1 (CMD) + 2 (RSP)) VCI flits for LL => 2 + 3 dspin flits + m_cpt_ll_cost += 5 * req_distance(p_vci_tgt.srcid.read()); } else { - if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_read_local++; - else m_cpt_read_remote++; - m_cpt_read_cost += req_distance(p_vci_tgt.srcid.read()); + if (is_local_req(p_vci_tgt.srcid.read())) + { + m_cpt_read_local++; + } + else + { + m_cpt_read_remote++; + } + // (1 (CMD) + m_words (RSP)) flits VCI => 2 + m_words + 1 flits dspin + m_cpt_read_cost += (3 + m_words) * req_distance(p_vci_tgt.srcid.read()); } // @@ -1710,5 +1709,5 @@ if (p_vci_tgt.cmdval and m_cmd_write_addr_fifo.wok()) { - + uint32_t plen = p_vci_tgt.plen.read(); #if DEBUG_MEMC_TGT_CMD if (m_debug) @@ -1725,10 +1724,18 @@ // if (p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP) { - m_cpt_sc_cost += req_distance(p_vci_tgt.srcid.read()); + // (2 (CMD) + 1 (RSP)) flits VCI => 4 + (1 (success) || 2 (failure)) flits dspin + m_cpt_sc_cost += 5 * req_distance(p_vci_tgt.srcid.read()); } else { - if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_write_flits_local++; - else m_cpt_write_flits_remote++; - m_cpt_write_cost += req_distance(p_vci_tgt.srcid.read()); + if (is_local_req(p_vci_tgt.srcid.read())) + { + m_cpt_write_flits_local++; + } + else + { + m_cpt_write_flits_remote++; + } + // (burst_size (CMD) + 1 (RSP) flits VCI => 2 + burst_size + 1 flits dspin + m_cpt_write_cost += (3 + (plen >> 2)) * req_distance(p_vci_tgt.srcid.read()); } // @@ -1737,11 +1744,22 @@ // if (p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP) { - if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_sc_local++; - else m_cpt_sc_remote++; - + if (is_local_req(p_vci_tgt.srcid.read())) + { + m_cpt_sc_local++; + } + else + { + m_cpt_sc_remote++; + } } else { - if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_write_local++; - else m_cpt_write_remote++; + if (is_local_req(p_vci_tgt.srcid.read())) + { + m_cpt_write_local++; + } + else + { + m_cpt_write_remote++; + } } // @@ -1777,7 +1795,14 @@ if (p_vci_tgt.eop) { // - if (is_local_req(p_vci_tgt.srcid.read())) m_cpt_cas_local++; - else m_cpt_cas_remote++; - m_cpt_cas_cost += req_distance(p_vci_tgt.srcid.read()); + if (is_local_req(p_vci_tgt.srcid.read())) + { + m_cpt_cas_local++; + } + else + { + m_cpt_cas_remote++; + } + // (2 (CMD) + 1 (RSP)) flits VCI => 4 + (1 (success) || 2 (failure)) flits dspin + m_cpt_cas_cost += 5 * req_distance(p_vci_tgt.srcid.read()); // r_tgt_cmd_fsm = TGT_CMD_IDLE; @@ -6575,6 +6600,7 @@ { m_cpt_minval_remote++; - m_cpt_minval_cost += req_distance(m_config_to_cc_send_srcid_fifo.read()); - } + } + // 2 flits for multi inval + m_cpt_minval_cost += 2 * req_distance(m_config_to_cc_send_srcid_fifo.read()); // r_cc_send_fsm = CC_SEND_CONFIG_INVAL_NLINE; @@ -6642,6 +6668,7 @@ { m_cpt_minval_remote++; - m_cpt_minval_cost += req_distance(m_xram_rsp_to_cc_send_srcid_fifo.read()); - } + } + // 2 flits for multi inval + m_cpt_minval_cost += 2 * req_distance(m_xram_rsp_to_cc_send_srcid_fifo.read()); // r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_NLINE; @@ -6737,6 +6764,7 @@ { m_cpt_update_remote++; - m_cpt_update_cost += req_distance(m_write_to_cc_send_srcid_fifo.read()); - } + } + // 2 flits for multi update + m_cpt_update_cost += 2 * req_distance(m_write_to_cc_send_srcid_fifo.read()); // @@ -6826,6 +6854,7 @@ { m_cpt_update_remote++; - m_cpt_update_cost += req_distance(m_cas_to_cc_send_srcid_fifo.read()); - } + } + // 2 flits for multi update + m_cpt_update_cost += 2 * req_distance(m_cas_to_cc_send_srcid_fifo.read()); // r_cc_send_fsm = CC_SEND_CAS_UPDT_NLINE; @@ -6951,6 +6980,7 @@ else { m_cpt_cleanup_remote++; - m_cpt_cleanup_cost += req_distance(srcid); - } + } + // 2 flits for cleanup without data + m_cpt_cleanup_cost += 2 * req_distance(srcid); //