Index: /trunk/modules/vci_synthetic_initator/caba/metadata/vci_synthetic_initator.sd =================================================================== --- /trunk/modules/vci_synthetic_initator/caba/metadata/vci_synthetic_initator.sd (revision 77) +++ /trunk/modules/vci_synthetic_initator/caba/metadata/vci_synthetic_initator.sd (revision 78) @@ -1,9 +1,9 @@ # -*- python -*- -Module('caba:vci_traffic_generator', - classname = 'soclib::caba::VciTrafficGenerator', +Module('caba:vci_synthetic_initiator', + classname = 'soclib::caba::VciSyntheticInitiator', tmpl_parameters = [parameter.Module('vci_param', default = 'caba:vci_param'),], - header_files = ['../source/include/vci_traffic_generator.h',], - implementation_files = ['../source/src/vci_traffic_generator.cpp',], + header_files = ['../source/include/vci_synthetic_initiator.h',], + implementation_files = ['../source/src/vci_synthetic_initiator.cpp',], uses = [Uses('caba:base_module'), Uses('common:loader'), Index: /trunk/modules/vci_synthetic_initator/caba/sources/include/vci_synthetic_initator.h =================================================================== --- /trunk/modules/vci_synthetic_initator/caba/sources/include/vci_synthetic_initator.h (revision 77) +++ /trunk/modules/vci_synthetic_initator/caba/sources/include/vci_synthetic_initator.h (revision 78) @@ -73,10 +73,19 @@ VciSyntheticInitiator( - sc_module_name name, // Instance Name - const soclib::common::MappingTable &mtp, // Mapping table for primary requets - const soclib::common::IntTab &vci_index, // VCI port to PROC (initiator) - size_t nways, // Number of ways per set - size_t nsets, // Number of sets - size_t nwords); // Number of words per line + sc_module_name name, + size_t length, // Packet length (flit numbers) + float rho, // Packets ratio on the network + size_t depth, // Fifo depth + size_t x, // + size_t y, // + size_t xmesh, + size_t ymesh, + size_t bc_period, // Broadcast period, if no broadcast => 0 + size_t xmin, + size_t xmax, + size_t ymin, + size_t ymax + const soclib::common::IntTab &vci_index, + ); ~VciSyntheticInitiator(); @@ -91,24 +100,19 @@ // Component attributes - const size_t m_initiators; // Number of initiators - const size_t m_ways; // Number of ways in a set - const size_t m_sets; // Number of cache sets - const size_t m_words; // Number of words in a line - const size_t m_srcid; // Srcid for requests to processors + const size_t m_length; // Number of flits of a packet + const size_t m_rho; // Rate of packets in the network wanted + const size_t m_depth, // Fifo depth + const size_t m_x, // + const size_t m_y, // + const size_t m_xmesh, + const size_t m_ymesh, + const size_t m_bc_period, // Broadcast period, if no broadcast => 0 + const size_t m_xmin, + const size_t m_xmax, + const size_t m_ymin, + const size_t m_ymax - data_t ***m_cache_data; // data array[set][way][word] - - // adress masks - const soclib::common::AddressMaskingTable m_x; - const soclib::common::AddressMaskingTable m_y; - const soclib::common::AddressMaskingTable m_z; - const soclib::common::AddressMaskingTable m_nline; - - ////////////////////////////////////////////////// - // Registers controlled by the TGT_CMD fsm - ////////////////////////////////////////////////// - - // Fifo between TGT_CMD fsm and READ fsm - GenericFifo m_cmd_read_addr_fifo; + // Fifo transmitting date to the VCI FSM + GenericFifo m_date_fifo; sc_signal r_vci_fsm; @@ -116,5 +120,5 @@ sc_signal r_index; - }; // end class VciMemCache + }; // end class VciSyntheticInitiator }} Index: /trunk/modules/vci_synthetic_initator/caba/sources/src/vci_synthetic_initator.cpp =================================================================== --- /trunk/modules/vci_synthetic_initator/caba/sources/src/vci_synthetic_initator.cpp (revision 77) +++ /trunk/modules/vci_synthetic_initator/caba/sources/src/vci_synthetic_initator.cpp (revision 78) @@ -28,5 +28,5 @@ */ -#include "../include/vci_traffic_generator.h" +#include "../include/vci_synthetic_initiator.h" @@ -35,22 +35,27 @@ -#define tmpl(x) template x VciTrafficGenerator - - +#define tmpl(x) template x VciSyntheticInitiator + + //using soclib::common::uint32_log2; + //////////////////////////////// // Constructor //////////////////////////////// - tmpl(/**/)::VciTrafficGenerator( + tmpl(/**/)::VciSyntheticInitiator( sc_module_name name, - const soclib::common::MappingTable &mtp, - const soclib::common::MappingTable &mtc, - const soclib::common::MappingTable &mtx, - const soclib::common::IntTab &vci_ixr_index, - const soclib::common::IntTab &vci_ini_index, - const soclib::common::IntTab &vci_tgt_index, - size_t nways, - size_t nsets, - size_t nwords) + size_t length, // Packet length (flit numbers) + float rho, // Packets ratio on the network + size_t depth, // Fifo depth + size_t x, // + size_t y, // + size_t xmesh, + size_t ymesh, + size_t bc_period, // Broadcast period, if no broadcast => 0 + size_t xmin, + size_t xmax, + size_t ymin, + size_t ymax + ) : soclib::caba::BaseModule(name), @@ -62,49 +67,8 @@ m_srcid_ini( mtc.indexForId(vci_ini_index) ), // FIFOs - m_cmd_read_addr_fifo("m_cmd_read_addr_fifo", 4), + m_date_fifo("m_date_fifo", depth), r_tgt_cmd_fsm("r_tgt_cmd_fsm"), { - assert(IS_POW_OF_2(nsets)); - assert(IS_POW_OF_2(nwords)); - assert(IS_POW_OF_2(nways)); - assert(nsets); - assert(nwords); - assert(nways); - assert(nsets <= 1024); - assert(nwords <= 32); - assert(nways <= 32); - - // Get the segments associated to the MemCache - //std::list segList(mtp.getSegmentList(vci_tgt_index)); - std::list::iterator seg; - /* - for(seg = segList.begin(); seg != segList.end() ; seg++) { - if( seg->size() > 8 ) m_mem_segment = *seg; - else m_reg_segment = *seg; - nseg++; - } - */ - - for(seg = m_seglist.begin(); seg != m_seglist.end() ; seg++) { - if( seg->size() > 8 ) nseg++; - } - //assert( (nseg == 2) && (m_reg_segment.size() == 8) ); - - m_seg = new soclib::common::Segment*[nseg]; - size_t i = 0; - for ( seg = m_seglist.begin() ; seg != m_seglist.end() ; seg++ ) { - if ( seg->size() > 8 ) - { - m_seg[i] = &(*seg); - i++; - } - else - { - m_reg_segment = *seg; - } - } - - assert( (m_reg_segment.size() == 8) ); // Memory cache allocation & initialisation @@ -122,26 +86,4 @@ } - // Allocation for IXR_RSP FSM - r_ixr_rsp_to_xram_rsp_rok = new sc_signal[TRANSACTION_TAB_LINES]; - - // Allocation for XRAM_RSP FSM - r_xram_rsp_victim_data = new sc_signal[nwords]; - r_xram_rsp_to_tgt_rsp_data = new sc_signal[nwords]; - r_xram_rsp_to_tgt_rsp_val = new sc_signal[nwords]; - r_xram_rsp_to_xram_cmd_data = new sc_signal[nwords]; - - // Allocation for READ FSM - r_read_data = new sc_signal[nwords]; - r_read_to_tgt_rsp_data = new sc_signal[nwords]; - r_read_to_tgt_rsp_val = new sc_signal[nwords]; - - // Allocation for WRITE FSM - r_write_data = new sc_signal[nwords]; - r_write_be = new sc_signal[nwords]; - r_write_to_init_cmd_data = new sc_signal[nwords]; - r_write_to_init_cmd_we = new sc_signal[nwords]; - - // Simulation - SC_METHOD(transition); dont_initialize(); @@ -154,55 +96,9 @@ } // end constructor - ///////////////////////////////////////// - // This function prints the statistics - ///////////////////////////////////////// - - tmpl(void)::print_stats() - { - std::cout << "----------------------------------" << std::dec << std::endl; - std::cout << "MEM_CACHE " << m_srcid_ini << " / Time = " << m_cpt_cycles << std::endl - << "- READ RATE = " << (float)m_cpt_read/m_cpt_cycles << std::endl - << "- READ MISS RATE = " << (float)m_cpt_read_miss/m_cpt_read << std::endl - << "- WRITE RATE = " << (float)m_cpt_write/m_cpt_cycles << std::endl - << "- WRITE MISS RATE = " << (float)m_cpt_write_miss/m_cpt_write << std::endl - << "- WRITE BURST LENGTH = " << (float)m_cpt_write_cells/m_cpt_write << std::endl - << "- UPDATE RATE = " << (float)m_cpt_update/m_cpt_cycles << std::endl - << "- UPDATE ARITY = " << (float)m_cpt_update_mult/m_cpt_update << std::endl - << "- INVAL RATE = " << (float)m_cpt_inval/m_cpt_cycles << std::endl - << "- INVAL ARITY = " << (float)m_cpt_inval_mult/m_cpt_inval << std::endl - << "- SAVE DIRTY RATE = " << (float)m_cpt_write_dirty/m_cpt_cycles << std::endl - << "- CLEANUP RATE = " << (float)m_cpt_cleanup/m_cpt_cycles << std::endl - << "- LL RATE = " << (float)m_cpt_ll/m_cpt_cycles << std::endl - << "- SC RATE = " << (float)m_cpt_sc/m_cpt_cycles << std::endl; - } ///////////////////////////////// - tmpl(/**/)::~VciTrafficGenerator() + tmpl(/**/)::~VciSyntheticInitiator() ///////////////////////////////// { - for(size_t i=0; icontains(p_vci_tgt.address.read()) ) { - reached = true; - r_index = index; - } - } - - if ( !reached ) - { - std::cout << "Out of segment access in VCI_MEM_CACHE" << std::endl; - std::cout << "Faulty address = " << p_vci_tgt.address.read() << std::endl; - std::cout << "Faulty initiator = " << p_vci_tgt.srcid.read() << std::endl; - exit(0); - } - else if ( p_vci_tgt.cmd.read() == vci_param::CMD_READ ) - { - r_tgt_cmd_fsm = TGT_CMD_READ; - } - else if (( p_vci_tgt.cmd.read() == vci_param::CMD_WRITE ) && ( p_vci_tgt.trdid.read() == 0x0 ) ) - { - r_tgt_cmd_fsm = TGT_CMD_WRITE; - } - else if ((p_vci_tgt.cmd.read() == vci_param::CMD_LOCKED_READ) || - (p_vci_tgt.cmd.read() == vci_param::CMD_STORE_COND) ) - { - r_tgt_cmd_fsm = TGT_CMD_ATOMIC; - } - else if (( p_vci_tgt.cmd.read() == vci_param::CMD_WRITE ) && ( p_vci_tgt.trdid.read() == 0x1 )) - { - r_tgt_cmd_fsm = TGT_CMD_CLEANUP; - } - } + case VCI_IDLE: + { break; } ////////////////// - case TGT_CMD_READ: - { - assert(((p_vci_tgt.plen.read() == 4) || (p_vci_tgt.plen.read() == m_words*4)) - && "All read request to the MemCache must have PLEN = 4 or PLEN = 4*nwords"); - - if ( p_vci_tgt.cmdval && m_cmd_read_addr_fifo.wok() ) { - cmd_read_fifo_put = true; - if ( p_vci_tgt.eop ) r_tgt_cmd_fsm = TGT_CMD_IDLE; - else r_tgt_cmd_fsm = TGT_CMD_READ_EOP; - } + case VCI_SINGLE_SEND: + { break; } ////////////////////// - case TGT_CMD_READ_EOP: - { - if ( p_vci_tgt.cmdval && p_vci_tgt.eop ){ - r_tgt_cmd_fsm = TGT_CMD_IDLE; - } + case VCI_SINGLE_RECEIVE: + { break; } /////////////////// - case TGT_CMD_WRITE: - { - if ( p_vci_tgt.cmdval && m_cmd_write_addr_fifo.wok() ) { - cmd_write_fifo_put = true; - if( p_vci_tgt.eop ) r_tgt_cmd_fsm = TGT_CMD_IDLE; - } + case VCI_BC_SEND: + { break; } //////////////////// - case TGT_CMD_ATOMIC: - { - assert(p_vci_tgt.eop && "Memory Cache Error: LL or SC command with length > 1 "); - - if ( p_vci_tgt.cmdval && m_cmd_llsc_addr_fifo.wok() ) { - cmd_llsc_fifo_put = true; - r_tgt_cmd_fsm = TGT_CMD_IDLE; - } - break; - } - ///////////////////// - case TGT_CMD_CLEANUP: - { - assert(p_vci_tgt.eop && "Memory Cache Error: CLEANUP request with length > 1 "); - - if ( p_vci_tgt.cmdval && m_cmd_cleanup_nline_fifo.wok() ) { - cmd_cleanup_fifo_put = true; - r_tgt_cmd_fsm = TGT_CMD_IDLE; - } - break; - } - } // end switch tgt_cmd_fsm + case VCI_BC_RECEIVE: + { + break; + } + } // end switch vci_fsm @@ -456,265 +200,32 @@ - p_vci_ixr.be = 0xF; - p_vci_ixr.pktid = 0; - p_vci_ixr.srcid = m_srcid_ixr; - p_vci_ixr.cons = false; - p_vci_ixr.wrap = false; - p_vci_ixr.contig = true; - p_vci_ixr.clen = 0; - p_vci_ixr.cfixed = false; - - if ( r_xram_cmd_fsm.read() == XRAM_CMD_READ_NLINE ) { - p_vci_ixr.cmd = vci_param::CMD_READ; - p_vci_ixr.cmdval = true; - p_vci_ixr.address = (r_read_to_xram_cmd_nline.read()*m_words*4); - p_vci_ixr.plen = m_words*4; - p_vci_ixr.wdata = 0x00000000; - p_vci_ixr.trdid = r_read_to_xram_cmd_trdid.read(); - p_vci_ixr.eop = true; - } - else if ( r_xram_cmd_fsm.read() == XRAM_CMD_LLSC_NLINE ) { - p_vci_ixr.cmd = vci_param::CMD_READ; - p_vci_ixr.cmdval = true; - p_vci_ixr.address = (r_llsc_to_xram_cmd_nline.read()*m_words*4); - p_vci_ixr.plen = m_words*4; - p_vci_ixr.wdata = 0x00000000; - p_vci_ixr.trdid = r_llsc_to_xram_cmd_trdid.read(); - p_vci_ixr.eop = true; - } - else if ( r_xram_cmd_fsm.read() == XRAM_CMD_WRITE_NLINE ) { - p_vci_ixr.cmd = vci_param::CMD_READ; - p_vci_ixr.cmdval = true; - p_vci_ixr.address = (r_write_to_xram_cmd_nline.read()*m_words*4); - p_vci_ixr.plen = m_words*4; - p_vci_ixr.wdata = 0x00000000; - p_vci_ixr.trdid = r_write_to_xram_cmd_trdid.read(); - p_vci_ixr.eop = true; - } - else if ( r_xram_cmd_fsm.read() == XRAM_CMD_XRAM_DATA ) { - p_vci_ixr.cmd = vci_param::CMD_WRITE; - p_vci_ixr.cmdval = true; - p_vci_ixr.address = ((r_xram_rsp_to_xram_cmd_nline.read()*m_words+r_xram_cmd_cpt.read())*4); - p_vci_ixr.plen = m_words*4; - p_vci_ixr.wdata = r_xram_rsp_to_xram_cmd_data[r_xram_cmd_cpt.read()].read(); - p_vci_ixr.trdid = r_xram_rsp_to_xram_cmd_trdid.read(); - p_vci_ixr.eop = (r_xram_cmd_cpt == (m_words-1)); - } else { - p_vci_ixr.cmdval = false; - p_vci_ixr.address = 0; - p_vci_ixr.plen = 0; - p_vci_ixr.wdata = 0; - p_vci_ixr.trdid = 0; - p_vci_ixr.eop = false; - } - - //////////////////////////////////////////////////// - // Response signals on the p_vci_ixr port - //////////////////////////////////////////////////// - - if ( ((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) && - (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ)) || - (r_ixr_rsp_fsm.read() == IXR_RSP_ACK) ) p_vci_ixr.rspack = true; - else p_vci_ixr.rspack = false; - - //////////////////////////////////////////////////// - // Command signals on the p_vci_tgt port - //////////////////////////////////////////////////// - - switch ((tgt_cmd_fsm_state_e)r_tgt_cmd_fsm.read()) { - case TGT_CMD_IDLE: - p_vci_tgt.cmdack = false; - break; - case TGT_CMD_READ: - p_vci_tgt.cmdack = m_cmd_read_addr_fifo.wok(); - break; - case TGT_CMD_READ_EOP: - p_vci_tgt.cmdack = true; - break; - case TGT_CMD_WRITE: - p_vci_tgt.cmdack = m_cmd_write_addr_fifo.wok(); - break; - case TGT_CMD_ATOMIC: - p_vci_tgt.cmdack = m_cmd_llsc_addr_fifo.wok(); - break; - case TGT_CMD_CLEANUP: - p_vci_tgt.cmdack = m_cmd_cleanup_nline_fifo.wok(); - break; - default: - p_vci_tgt.cmdack = false; - break; - } - - //////////////////////////////////////////////////// - // Response signals on the p_vci_tgt port - //////////////////////////////////////////////////// - switch ( r_tgt_rsp_fsm.read() ) { - - case TGT_RSP_READ_IDLE: - case TGT_RSP_WRITE_IDLE: - case TGT_RSP_LLSC_IDLE: - case TGT_RSP_CLEANUP_IDLE: - case TGT_RSP_XRAM_IDLE: - case TGT_RSP_INIT_IDLE: - case TGT_RSP_READ_TEST: - case TGT_RSP_XRAM_TEST: - - p_vci_tgt.rspval = false; - p_vci_tgt.rsrcid = 0; - p_vci_tgt.rdata = 0; - p_vci_tgt.rpktid = 0; - p_vci_tgt.rtrdid = 0; - p_vci_tgt.rerror = 0; - p_vci_tgt.reop = false; - break; - case TGT_RSP_READ_LINE: - p_vci_tgt.rspval = true; - p_vci_tgt.rdata = r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read(); - p_vci_tgt.rsrcid = r_read_to_tgt_rsp_srcid.read(); - p_vci_tgt.rtrdid = r_read_to_tgt_rsp_trdid.read(); - p_vci_tgt.rpktid = r_read_to_tgt_rsp_pktid.read(); - p_vci_tgt.rerror = 0; - p_vci_tgt.reop = (r_tgt_rsp_cpt.read()==(m_words-1)); - break; - case TGT_RSP_READ_WORD: - p_vci_tgt.rspval = true; - p_vci_tgt.rdata = r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read(); - p_vci_tgt.rsrcid = r_read_to_tgt_rsp_srcid.read(); - p_vci_tgt.rtrdid = r_read_to_tgt_rsp_trdid.read(); - p_vci_tgt.rpktid = r_read_to_tgt_rsp_pktid.read(); - p_vci_tgt.rerror = 0; - p_vci_tgt.reop = true; - break; - case TGT_RSP_WRITE: - p_vci_tgt.rspval = true; - p_vci_tgt.rdata = 0; - p_vci_tgt.rsrcid = r_write_to_tgt_rsp_srcid.read(); - p_vci_tgt.rtrdid = r_write_to_tgt_rsp_trdid.read(); - p_vci_tgt.rpktid = r_write_to_tgt_rsp_pktid.read(); - p_vci_tgt.rerror = 0; - p_vci_tgt.reop = true; - break; - case TGT_RSP_CLEANUP: - p_vci_tgt.rspval = true; - p_vci_tgt.rdata = 0; - p_vci_tgt.rsrcid = r_cleanup_to_tgt_rsp_srcid.read(); - p_vci_tgt.rtrdid = r_cleanup_to_tgt_rsp_trdid.read(); - p_vci_tgt.rpktid = r_cleanup_to_tgt_rsp_pktid.read(); - p_vci_tgt.rerror = 0; - p_vci_tgt.reop = true; - break; - case TGT_RSP_LLSC: - p_vci_tgt.rspval = true; - p_vci_tgt.rdata = r_llsc_to_tgt_rsp_data.read(); - p_vci_tgt.rsrcid = r_llsc_to_tgt_rsp_srcid.read(); - p_vci_tgt.rtrdid = r_llsc_to_tgt_rsp_trdid.read(); - p_vci_tgt.rpktid = r_llsc_to_tgt_rsp_pktid.read(); - p_vci_tgt.rerror = 0; - p_vci_tgt.reop = true; - break; - case TGT_RSP_XRAM_LINE: - p_vci_tgt.rspval = true; - p_vci_tgt.rdata = r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read(); - p_vci_tgt.rsrcid = r_xram_rsp_to_tgt_rsp_srcid.read(); - p_vci_tgt.rtrdid = r_xram_rsp_to_tgt_rsp_trdid.read(); - p_vci_tgt.rpktid = r_xram_rsp_to_tgt_rsp_pktid.read(); - p_vci_tgt.rerror = 0; - p_vci_tgt.reop = (r_tgt_rsp_cpt.read()==(m_words-1)); - break; - case TGT_RSP_XRAM_WORD: - p_vci_tgt.rspval = true; - p_vci_tgt.rdata = r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read(); - p_vci_tgt.rsrcid = r_xram_rsp_to_tgt_rsp_srcid.read(); - p_vci_tgt.rtrdid = r_xram_rsp_to_tgt_rsp_trdid.read(); - p_vci_tgt.rpktid = r_xram_rsp_to_tgt_rsp_pktid.read(); - p_vci_tgt.rerror = 0; - p_vci_tgt.reop = true; - break; - case TGT_RSP_INIT: - p_vci_tgt.rspval = true; - p_vci_tgt.rdata = 0; - p_vci_tgt.rsrcid = r_init_rsp_to_tgt_rsp_srcid.read(); - p_vci_tgt.rtrdid = r_init_rsp_to_tgt_rsp_trdid.read(); - p_vci_tgt.rpktid = r_init_rsp_to_tgt_rsp_pktid.read(); - p_vci_tgt.rerror = 0; - p_vci_tgt.reop = true; - break; - } // end switch r_tgt_rsp_fsm - - /////////////////////////////////////////////////// - // Command signals on the p_vci_ini port - /////////////////////////////////////////////////// - - p_vci_ini.cmd = vci_param::CMD_WRITE; - p_vci_ini.srcid = m_srcid_ini; - p_vci_ini.pktid = 0; - p_vci_ini.cons = true; - p_vci_ini.wrap = false; - p_vci_ini.contig = false; - p_vci_ini.clen = 0; - p_vci_ini.cfixed = false; - - switch ( r_init_cmd_fsm.read() ) { - - case INIT_CMD_UPDT_IDLE: - case INIT_CMD_INVAL_IDLE: - case INIT_CMD_UPDT_SEL: - case INIT_CMD_INVAL_SEL: - p_vci_ini.cmdval = false; - p_vci_ini.address = 0; - p_vci_ini.wdata = 0; - p_vci_ini.be = 0; - p_vci_ini.plen = 0; - p_vci_ini.trdid = 0; - p_vci_ini.eop = false; - break; - case INIT_CMD_INVAL_NLINE: - p_vci_ini.cmdval = true; - p_vci_ini.address = m_coherence_table[r_init_cmd_target.read()]; - p_vci_ini.wdata = r_xram_rsp_to_init_cmd_nline.read(); - p_vci_ini.be = 0xF; - p_vci_ini.plen = 4; - p_vci_ini.trdid = r_xram_rsp_to_init_cmd_trdid.read(); - p_vci_ini.eop = true; - break; - case INIT_CMD_UPDT_NLINE: - p_vci_ini.cmdval = true; - p_vci_ini.address = m_coherence_table[r_init_cmd_target.read()] + 4; - p_vci_ini.wdata = r_write_to_init_cmd_nline.read(); - p_vci_ini.be = 0xF; - p_vci_ini.plen = 4 * (r_write_to_init_cmd_count.read() + 2); - p_vci_ini.trdid = r_write_to_init_cmd_trdid.read(); - p_vci_ini.eop = false; - break; - case INIT_CMD_UPDT_INDEX: - p_vci_ini.cmdval = true; - p_vci_ini.address = m_coherence_table[r_init_cmd_target.read()] + 4; - p_vci_ini.wdata = r_write_to_init_cmd_index.read(); - p_vci_ini.be = 0xF; - p_vci_ini.plen = 4 * (r_write_to_init_cmd_count.read() + 2); - p_vci_ini.trdid = r_write_to_init_cmd_trdid.read(); - p_vci_ini.eop = false; - break; - case INIT_CMD_UPDT_DATA: - p_vci_ini.cmdval = true; - p_vci_ini.address = m_coherence_table[r_init_cmd_target.read()] + 4; - p_vci_ini.wdata = r_write_to_init_cmd_data[r_init_cmd_cpt.read() + - r_write_to_init_cmd_index.read()].read(); - if(r_write_to_init_cmd_we[r_init_cmd_cpt.read() + - r_write_to_init_cmd_index.read()].read()) - p_vci_ini.be = 0xF; - else p_vci_ini.be = 0x0; - p_vci_ini.plen = 4 * (r_write_to_init_cmd_count.read() + 2); - p_vci_ini.trdid = r_write_to_init_cmd_trdid.read(); - p_vci_ini.eop = ( r_init_cmd_cpt.read() == (r_write_to_init_cmd_count.read()-1) ); - break; - } // end switch r_init_cmd_fsm - - ////////////////////////////////////////////////////// - // Response signals on the p_vci_ini port - ////////////////////////////////////////////////////// - - if ( r_init_rsp_fsm.read() == INIT_RSP_IDLE ) p_vci_ini.rspack = true; - else p_vci_ini.rspack = false; + switch ( r_vci_fsm.read() ) { + + ////////////////// + case VCI_IDLE: + { + break; + } + ////////////////// + case VCI_SINGLE_SEND: + { + break; + } + ////////////////////// + case VCI_SINGLE_RECEIVE: + { + break; + } + /////////////////// + case VCI_BC_SEND: + { + break; + } + //////////////////// + case VCI_BC_RECEIVE: + { + break; + } + } // end switch vci_fsm } // end genMoore()