Changeset 79 for trunk/modules/vci_cc_vcache_wrapper2_v1
- Timestamp:
- Aug 27, 2010, 10:47:54 PM (14 years ago)
- Location:
- trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source
- Files:
-
- 2 edited
-
include/vci_cc_vcache_wrapper2_v1.h (modified) (2 diffs)
-
src/vci_cc_vcache_wrapper2_v1.cpp (modified) (51 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/include/vci_cc_vcache_wrapper2_v1.h
r68 r79 114 114 DCACHE_SC_DIRTY_WAIT, // 19 115 115 DCACHE_WRITE_UPDT, // 1a 116 DCACHE_WRITE_REQ, // 1b 117 DCACHE_MISS_WAIT, // 1c 118 DCACHE_MISS_UPDT, // 1d 119 DCACHE_UNC_WAIT, // 1e 120 DCACHE_ERROR, // 1f 121 DCACHE_ITLB_READ, // 20 122 DCACHE_ITLB_UPDT, // 21 123 DCACHE_ITLB_LL_WAIT, // 22 124 DCACHE_ITLB_SC_WAIT, // 23 125 DCACHE_CC_CHECK, // 24 126 DCACHE_CC_INVAL, // 25 127 DCACHE_CC_UPDT, // 26 128 DCACHE_CC_NOP, // 27 129 DCACHE_TLB_CC_INVAL, // 28 130 DCACHE_ITLB_CLEANUP, // 29 116 DCACHE_WRITE_DIRTY, // 1b 117 DCACHE_WRITE_REQ, // 1c 118 DCACHE_MISS_WAIT, // 1d 119 DCACHE_MISS_UPDT, // 1e 120 DCACHE_UNC_WAIT, // 1f 121 DCACHE_ERROR, // 20 122 DCACHE_ITLB_READ, // 21 123 DCACHE_ITLB_UPDT, // 22 124 DCACHE_ITLB_LL_WAIT, // 23 125 DCACHE_ITLB_SC_WAIT, // 24 126 DCACHE_CC_CHECK, // 25 127 DCACHE_CC_INVAL, // 26 128 DCACHE_CC_UPDT, // 27 129 DCACHE_CC_NOP, // 28 130 DCACHE_TLB_CC_INVAL, // 29 131 DCACHE_ITLB_CLEANUP, // 2a 131 132 }; 132 133 … … 309 310 sc_signal<bool> r_dcache_tlb_ll_dirty_req; // used for tlb dirty bit update 310 311 sc_signal<bool> r_dcache_tlb_sc_dirty_req; // used for tlb dirty bit update 312 sc_signal<bool> r_dcache_sc_updt_dirty; // used for tlb dirty bit update 311 313 sc_signal<bool> r_dcache_tlb_ptba_read; // used for tlb ptba read when write dirty bit 312 314 sc_signal<bool> r_dcache_xtn_req; // used for xtn write for ICACHE -
trunk/modules/vci_cc_vcache_wrapper2_v1/caba/source/src/vci_cc_vcache_wrapper2_v1.cpp
r73 r79 85 85 "DCACHE_SC_DIRTY_WAIT", 86 86 "DCACHE_WRITE_UPDT", 87 "DCACHE_WRITE_DIRTY", 87 88 "DCACHE_WRITE_REQ", 88 89 "DCACHE_MISS_WAIT", … … 459 460 r_dcache_tlb_sc_acc_req = false; 460 461 r_dcache_tlb_ll_dirty_req = false; 461 r_dcache_tlb_sc_dirty_req = false; 462 r_dcache_tlb_sc_dirty_req = false; 463 r_dcache_sc_updt_dirty = false; 462 464 r_dcache_itlb_ll_acc_req = false; 463 465 r_dcache_itlb_sc_acc_req = false; … … 1007 1009 else // MMU activated 1008 1010 { 1009 size_t c_way, c_set;1010 1011 m_cpt_ins_tlb_read++; 1011 1012 icache_hit_t = icache_tlb.cctranslate(ireq.addr, &tlb_ipaddr, &icache_pte_info, … … 1015 1016 spc_ipaddr = ((paddr_t)r_icache_ppn_save << PAGE_K_NBITS) | (paddr_t)(ireq.addr & PAGE_K_MASK); 1016 1017 icache_cached = icache_pte_info.c; 1017 if (icache_hit_t) {1018 if (!r_dcache.read(icache_tlb_nline << (uint32_log2(m_dcache_words) + 2), &icache_ins, &c_way, &c_set)) {1019 std::cout << "itlb PTE " << std::hex << icache_tlb_nline << " " << (icache_tlb_nline << (uint32_log2(m_dcache_words) + 2)) << " not in cache" << std::endl;1020 abort();1021 }1022 if (!r_dcache_in_itlb[m_dcache_sets*c_way+c_set]) {1023 std::cout << "itlb PTE " << std::hex << icache_tlb_nline << " "1024 << (icache_tlb_nline << (uint32_log2(m_dcache_words) + 2)) <<1025 " " << c_way << "," << c_set << " @" << &r_dcache_in_itlb[m_dcache_sets*c_way+c_set] << " not in_itlb" << std::endl;1026 abort();1027 }1028 }1029 1018 } 1030 1019 … … 1329 1318 } 1330 1319 } 1331 1332 if ( r_icache_inval_tlb_rsp ) // TLB miss read response and invalidation 1320 else // TLB miss read response and invalidation 1333 1321 { 1334 1322 if ( r_dcache_rsp_itlb_error ) … … 1385 1373 } 1386 1374 } 1387 1388 if ( r_icache_inval_tlb_rsp) // TLB ET write response and invalidation 1375 else // TLB ET write response and invalidation 1389 1376 { 1390 1377 if ( r_dcache_rsp_itlb_error ) … … 1531 1518 } 1532 1519 } 1533 1534 if ( r_icache_inval_tlb_rsp ) // TLB miss read response and invalidation 1520 else // TLB miss read response and invalidation 1535 1521 { 1536 1522 if ( r_dcache_rsp_itlb_error ) … … 1587 1573 } 1588 1574 } 1589 1590 if ( r_icache_inval_tlb_rsp ) // TLB ET write response and invalidation 1575 else // TLB ET write response and invalidation 1591 1576 { 1592 1577 if ( r_dcache_rsp_itlb_error ) … … 2034 2019 m_cost_ins_miss_frz++; 2035 2020 } 2036 if( (( r_icache_fsm_save == ICACHE_TLB1_READ ) || ( r_icache_fsm_save == ICACHE_TLB2_READ ) 2021 if( (( r_icache_fsm_save == ICACHE_TLB1_READ ) || ( r_icache_fsm_save == ICACHE_TLB2_READ ) || 2037 2022 ( r_icache_fsm_save == ICACHE_TLB1_WRITE ) || ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) || 2038 2023 ( r_icache_fsm_save == ICACHE_TLB1_UPDT ) || ( r_icache_fsm_save == ICACHE_TLB2_UPDT )) && (ireq.valid) ) … … 2044 2029 // invalidate cache 2045 2030 if( (( r_icache_fsm_save == ICACHE_TLB1_READ ) || ( r_icache_fsm_save == ICACHE_TLB2_READ ) || 2046 ( r_icache_fsm_save == ICACHE_TLB1_WRITE )|| ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) ||2031 ( r_icache_fsm_save == ICACHE_TLB1_WRITE )|| ( r_icache_fsm_save == ICACHE_TLB2_WRITE ) || 2047 2032 ( r_icache_fsm_save == ICACHE_TLB1_UPDT ) || ( r_icache_fsm_save == ICACHE_TLB2_UPDT )) && 2048 2033 (((r_icache_paddr_save.read() & ~((m_icache_words<<2)-1)) >> (uint32_log2(m_icache_words) + 2) ) == r_dcache_itlb_inval_line.read()) ) … … 2569 2554 else // MMU activated 2570 2555 { 2571 size_t c_way, c_set;2572 2556 m_cpt_data_tlb_read++; 2573 2557 dcache_hit_t = dcache_tlb.cctranslate(dreq.addr, &tlb_dpaddr, &dcache_pte_info, … … 2579 2563 ((dreq.type != iss_t::DATA_LL) && (dreq.type != iss_t::DATA_SC) && 2580 2564 (dreq.type != iss_t::XTN_READ) && (dreq.type != iss_t::XTN_WRITE)); 2581 if (dcache_hit_t) {2582 if (!r_dcache.read(dcache_tlb_nline << (uint32_log2(m_dcache_words) + 2), &dcache_rdata, &c_way, &c_set)) {2583 std::cout << "dtlb PTE " << std::hex << dcache_tlb_nline << " " << (dcache_tlb_nline << (uint32_log2(m_dcache_words) + 2)) << " not in cache" << std::endl;2584 abort();2585 }2586 if (!r_dcache_in_dtlb[m_dcache_sets*c_way+c_set]) {2587 std::cout << "dtlb PTE " << std::hex << dcache_tlb_nline <<2588 " " << c_way << "," << c_set << " not in_dtlb" <<2589 std::endl;2590 abort();2591 }2592 }2593 2565 } 2594 2566 … … 2704 2676 else 2705 2677 { 2706 if (dreq.type == iss_t::DATA_SC && 2707 (r_mmu_mode.read() & DATA_TLB_MASK) && 2708 !dcache_pte_info.d) 2678 if ((dreq.type == iss_t::DATA_SC) && !dcache_pte_info.d && (r_mmu_mode.read() & DATA_TLB_MASK)) 2709 2679 { 2710 /* dirty bit update */2711 m_cpt_data_tlb_update_dirty++;2712 m_cost_data_tlb_update_dirty_frz++;2713 2714 2715 2716 2717 2718 2719 2720 2721 2722 2723 2724 2725 2726 2727 2728 2729 2730 2731 2732 2733 2734 2735 2736 } 2680 m_cpt_data_tlb_update_dirty++; 2681 m_cost_data_tlb_update_dirty_frz++; 2682 r_dcache_sc_updt_dirty = true; 2683 if ( dcache_tlb.getpagesize(dcache_tlb_way, dcache_tlb_set) ) // 2M page size, one level page table 2684 { 2685 r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK; 2686 r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2); 2687 r_dcache_tlb_ll_dirty_req = true; 2688 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 2689 } 2690 else // 4k page size, two levels page table 2691 { 2692 if (dcache_hit_p) 2693 { 2694 r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK; 2695 r_dcache_tlb_paddr = (paddr_t)r_dcache_ptba_save | (paddr_t)(((dreq.addr&PTD_ID2_MASK)>>PAGE_K_NBITS) << 3); 2696 r_dcache_tlb_ll_dirty_req = true; 2697 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 2698 } 2699 else // get PTBA to calculate the physical address of PTE 2700 { 2701 r_dcache_pte_update = dcache_tlb.getpte(dcache_tlb_way, dcache_tlb_set) | PTE_D_MASK; 2702 r_dcache_tlb_paddr = (paddr_t)r_mmu_ptpr << (INDEX1_NBITS+2) | (paddr_t)((dreq.addr>>PAGE_M_NBITS)<<2); 2703 r_dcache_tlb_ptba_read = true; 2704 r_dcache_fsm = DCACHE_DTLB1_READ_CACHE; 2705 } 2706 } 2737 2707 } 2738 2708 else 2739 { 2709 { 2740 2710 r_dcache_unc_req = true; 2741 2711 r_dcache_fsm = DCACHE_UNC_WAIT; 2742 2712 m_cpt_unc_read++; 2743 m_cost_unc_read_frz++;2744 2713 } 2714 m_cost_unc_read_frz++; 2745 2715 } 2746 2716 } … … 3022 2992 if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false; 3023 2993 if (r_dcache_inval_rsp) r_dcache_inval_rsp = false; 2994 if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false; 3024 2995 } 3025 2996 else … … 3040 3011 if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false; 3041 3012 if (r_dcache_inval_rsp) r_dcache_inval_rsp = false; 3013 if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false; 3042 3014 } 3043 3015 else if ( r_dcache_inval_tlb_rsp ) … … 3045 3017 r_dcache_inval_tlb_rsp = false; 3046 3018 r_dcache_fsm = DCACHE_IDLE; 3019 if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false; 3047 3020 } 3048 3021 else if ( r_dcache_inval_rsp ) … … 3050 3023 r_dcache_inval_rsp = false; 3051 3024 r_dcache_fsm = DCACHE_IDLE; 3025 if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false; 3052 3026 } 3053 3027 else … … 3090 3064 if (r_dcache_inval_tlb_rsp) r_dcache_inval_tlb_rsp = false; 3091 3065 if (r_dcache_inval_rsp) r_dcache_inval_rsp = false; 3066 if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false; 3092 3067 } 3093 3068 else … … 3099 3074 r_dcache_fsm = DCACHE_IDLE; 3100 3075 if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false; 3076 if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false; 3101 3077 } 3102 3078 else if ( r_dcache_inval_rsp ) 3103 3079 { 3104 3080 r_dcache_inval_rsp = false; 3081 r_dcache_fsm = DCACHE_IDLE; 3105 3082 if (r_dcache_tlb_sc_fail) r_dcache_tlb_sc_fail = false; 3106 r_dcache_fsm = DCACHE_IDLE;3083 if (r_dcache_sc_updt_dirty) r_dcache_sc_updt_dirty = false; 3107 3084 } 3108 3085 else if ( r_dcache_tlb_sc_fail ) … … 3115 3092 else 3116 3093 { 3117 /* 3118 * SC succeeded, but has updated the cache and 3119 * invalidated the TLB entry. Redo the translation 3120 */ 3121 r_dcache_fsm = DCACHE_IDLE; 3094 bool write_hit = r_dcache.write(r_dcache_tlb_paddr, r_dcache_pte_update); 3095 assert(write_hit && "Write on miss ignores data for data MMU update dirty bit"); 3096 r_dcache_fsm = DCACHE_WRITE_DIRTY; 3097 m_cpt_dcache_data_write++; 3122 3098 } 3123 3099 } … … 3147 3123 3148 3124 data_t tlb_data = 0; 3149 bool write_hit = false;3150 3125 bool tlb_hit_cache = r_dcache.read(r_dcache_tlb_paddr, &tlb_data); 3151 3126 … … 3177 3152 { 3178 3153 r_dcache_tlb_ptba_read = false; 3154 //write_hit = r_dcache.write(((paddr_t)(tlb_data & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3)), r_dcache_pte_update); 3155 //assert(write_hit && "Write on miss ignores data"); 3179 3156 r_dcache_tlb_ll_dirty_req = true; 3180 3157 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 3181 m_cpt_dcache_data_write++;3158 //m_cpt_dcache_data_write++; 3182 3159 m_cost_data_tlb_update_dirty_frz++; 3183 3160 } … … 3202 3179 r_dcache_pte_update = tlb_data | PTE_L_MASK; 3203 3180 r_dcache_tlb_ll_acc_req = true; 3181 //write_hit = r_dcache.write(r_dcache_tlb_paddr,(tlb_data | PTE_L_MASK)); 3182 //assert(write_hit && "Write on miss ignores data"); 3204 3183 r_dcache_fsm = DCACHE_TLB1_LL_WAIT; 3205 m_cpt_dcache_data_write++;3184 //m_cpt_dcache_data_write++; 3206 3185 m_cpt_data_tlb_update_acc++; 3207 3186 m_cost_data_tlb_update_acc_frz++; … … 3219 3198 r_dcache_pte_update = tlb_data | PTE_R_MASK; 3220 3199 r_dcache_tlb_ll_acc_req = true; 3200 //write_hit = r_dcache.write(r_dcache_tlb_paddr,(tlb_data | PTE_R_MASK)); 3201 //assert(write_hit && "Write on miss ignores data"); 3221 3202 r_dcache_fsm = DCACHE_TLB1_LL_WAIT; 3222 m_cpt_dcache_data_write++;3203 //m_cpt_dcache_data_write++; 3223 3204 m_cpt_data_tlb_update_acc++; 3224 3205 m_cost_data_tlb_update_acc_frz++; … … 3359 3340 else 3360 3341 { 3342 bool write_hit = r_dcache.write(r_dcache_tlb_paddr,r_dcache_pte_update); 3343 assert(write_hit && "Write on miss ignores data for data MMU update data access bit"); 3361 3344 r_dcache_fsm = DCACHE_TLB1_UPDT; 3345 m_cpt_dcache_data_write++; 3362 3346 } 3363 3347 } … … 3447 3431 data_t rsp_dtlb_miss = 0; 3448 3432 paddr_t victim_index = 0; 3449 bool write_hit = false;3433 //bool write_hit = false; 3450 3434 size_t way = 0; 3451 3435 size_t set = 0; … … 3512 3496 { 3513 3497 r_dcache_tlb_ptba_read = false; 3498 //write_hit = r_dcache.write(((paddr_t)(rsp_dtlb_miss & ((1<<(m_paddr_nbits - PAGE_K_NBITS))-1)) << PAGE_K_NBITS | (paddr_t)(((dreq.addr & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3)),r_dcache_pte_update); 3499 //assert(write_hit && "Write on miss ignores data"); 3514 3500 r_dcache_tlb_ll_dirty_req = true; 3515 3501 r_dcache_fsm = DCACHE_LL_DIRTY_WAIT; 3516 m_cpt_dcache_data_write++;3502 //m_cpt_dcache_data_write++; 3517 3503 m_cpt_data_tlb_update_dirty++; 3518 3504 m_cost_data_tlb_update_dirty_frz++; … … 3537 3523 r_dcache_pte_update = rsp_dtlb_miss | PTE_L_MASK; 3538 3524 r_dcache_tlb_ll_acc_req = true; 3525 //write_hit = r_dcache.write(r_dcache_tlb_paddr,(rsp_dtlb_miss | PTE_L_MASK)); 3526 //assert(write_hit && "Write on miss ignores data"); 3539 3527 r_dcache_fsm = DCACHE_TLB1_LL_WAIT; 3540 m_cpt_dcache_data_write++;3528 //m_cpt_dcache_data_write++; 3541 3529 m_cpt_data_tlb_update_acc++; 3542 3530 m_cost_data_tlb_update_acc_frz++; … … 3554 3542 r_dcache_pte_update = rsp_dtlb_miss | PTE_R_MASK; 3555 3543 r_dcache_tlb_ll_acc_req = true; 3544 //write_hit = r_dcache.write(r_dcache_tlb_paddr,(rsp_dtlb_miss | PTE_R_MASK)); 3545 //assert(write_hit && "Write on miss ignores data"); 3556 3546 r_dcache_fsm = DCACHE_TLB1_LL_WAIT; 3557 m_cpt_dcache_data_write++;3547 //m_cpt_dcache_data_write++; 3558 3548 m_cpt_data_tlb_update_acc++; 3559 3549 m_cost_data_tlb_update_acc_frz++; … … 3582 3572 if (dcache_tlb.update(r_dcache_pte_update,dreq.addr,(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index)) 3583 3573 { 3584 r_dcache.setinbit((paddr_t)victim_index << (uint32_log2(m_dcache_words) +2), r_dcache_in_dtlb, false);3574 r_dcache.setinbit((paddr_t)victim_index << (uint32_log2(m_dcache_words)+2), r_dcache_in_dtlb, false); 3585 3575 } 3586 3576 r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true); … … 3618 3608 data_t tlb_data = 0; 3619 3609 data_t tlb_data_ppn = 0; 3620 bool write_hit = false;3610 //bool write_hit = false; 3621 3611 bool tlb_hit_cache = r_dcache.read(r_dcache_tlb_paddr, &tlb_data); 3622 3612 … … 3665 3655 r_dcache_ppn_update = tlb_data_ppn; 3666 3656 r_dcache_tlb_ll_acc_req = true; 3657 //write_hit = r_dcache.write(r_dcache_tlb_paddr,(tlb_data | PTE_L_MASK)); 3658 //assert(write_hit && "Write on miss ignores data"); 3667 3659 r_dcache_fsm = DCACHE_TLB2_LL_WAIT; 3668 m_cpt_dcache_data_write++;3660 //m_cpt_dcache_data_write++; 3669 3661 m_cpt_data_tlb_update_acc++; 3670 3662 m_cost_data_tlb_update_acc_frz++; … … 3684 3676 r_dcache_ppn_update = tlb_data_ppn; 3685 3677 r_dcache_tlb_ll_acc_req = true; 3678 //write_hit = r_dcache.write(r_dcache_tlb_paddr,(tlb_data | PTE_R_MASK)); 3679 //assert(write_hit && "Write on miss ignores data"); 3686 3680 r_dcache_fsm = DCACHE_TLB2_LL_WAIT; 3687 m_cpt_dcache_data_write++;3681 //m_cpt_dcache_data_write++; 3688 3682 m_cpt_data_tlb_update_acc++; 3689 3683 m_cost_data_tlb_update_acc_frz++; … … 3825 3819 else 3826 3820 { 3821 bool write_hit = r_dcache.write(r_dcache_tlb_paddr,r_dcache_pte_update); 3822 assert(write_hit && "Write on miss ignores data for data MMU update data access bit"); 3827 3823 r_dcache_fsm = DCACHE_TLB2_UPDT; 3824 m_cpt_dcache_data_write++; 3828 3825 } 3829 3826 } … … 3913 3910 data_t rsp_dtlb_miss; 3914 3911 data_t tlb_data_ppn; 3915 bool write_hit = false;3912 //bool write_hit = false; 3916 3913 paddr_t victim_index = 0; 3917 3914 size_t way = 0; … … 3992 3989 r_dcache_ppn_update = tlb_data_ppn; 3993 3990 r_dcache_tlb_ll_acc_req = true; 3991 //write_hit = r_dcache.write(r_dcache_tlb_paddr,(rsp_dtlb_miss | PTE_L_MASK)); 3992 //assert(write_hit && "Write on miss ignores data"); 3994 3993 r_dcache_fsm = DCACHE_TLB2_LL_WAIT; 3995 m_cpt_dcache_data_write++;3994 //m_cpt_dcache_data_write++; 3996 3995 m_cpt_data_tlb_update_acc++; 3997 3996 m_cost_data_tlb_update_acc_frz++; … … 4011 4010 r_dcache_ppn_update = tlb_data_ppn; 4012 4011 r_dcache_tlb_ll_acc_req = true; 4012 //write_hit = r_dcache.write(r_dcache_tlb_paddr,(rsp_dtlb_miss | PTE_R_MASK)); 4013 //assert(write_hit && "Write on miss ignores data"); 4013 4014 r_dcache_fsm = DCACHE_TLB2_LL_WAIT; 4014 m_cpt_dcache_data_write++;4015 //m_cpt_dcache_data_write++; 4015 4016 m_cpt_data_tlb_update_acc++; 4016 4017 m_cost_data_tlb_update_acc_frz++; … … 4039 4040 if (dcache_tlb.update(r_dcache_pte_update,r_dcache_ppn_update,dreq.addr,(r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2)),&victim_index)) 4040 4041 { 4041 r_dcache.setinbit((paddr_t)victim_index << (uint32_log2(m_dcache_words) +2), r_dcache_in_dtlb, false);4042 r_dcache.setinbit((paddr_t)victim_index << (uint32_log2(m_dcache_words)+2), r_dcache_in_dtlb, false); 4042 4043 } 4043 4044 r_dcache.setinbit(r_dcache_tlb_paddr, r_dcache_in_dtlb, true); … … 4062 4063 if ( r_dcache_itlb_cleanup_req ) 4063 4064 { 4064 r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read() << (uint32_log2(m_dcache_words) +2)), r_dcache_in_itlb, false);4065 r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read() << (uint32_log2(m_dcache_words)+2)), r_dcache_in_itlb, false); 4065 4066 r_dcache_itlb_cleanup_req = false; 4066 4067 } … … 4072 4073 if(dcache_tlb.checkcleanup(way, set, &victim_index)) 4073 4074 { 4074 /* 4075 * this is correct because checkcleanup returns true only 4076 * if none of the PTE entries of the line is global. 4077 */ 4078 r_dcache.setinbit((paddr_t)victim_index << (uint32_log2(m_dcache_words) + 2), r_dcache_in_dtlb, false); 4075 r_dcache.setinbit((paddr_t)(victim_index << (uint32_log2(m_dcache_words)+2)), r_dcache_in_dtlb, false); 4079 4076 } 4080 4077 } … … 4173 4170 if ( dcache_tlb.inval(r_dcache_wdata_save, &victim_index) ) 4174 4171 { 4175 r_dcache.setinbit((paddr_t)(victim_index << (uint32_log2(m_dcache_words) +2)), r_dcache_in_dtlb, false);4172 r_dcache.setinbit((paddr_t)(victim_index << (uint32_log2(m_dcache_words)+2)), r_dcache_in_dtlb, false); 4176 4173 } 4177 4174 r_dtlb_translation_valid = false; … … 4409 4406 r_dcache_cleanup_line = victim_index; 4410 4407 m_cpt_cc_cleanup_data++; 4411 r_dcache_fsm = DCACHE_TLB_CC_INVAL; 4412 r_dcache_fsm_save = r_dcache_fsm; 4413 break; 4408 if ( r_dcache_in_itlb[m_dcache_sets*way+set] || r_dcache_in_dtlb[m_dcache_sets*way+set] ) 4409 { 4410 r_dcache_fsm = DCACHE_TLB_CC_INVAL; 4411 r_dcache_fsm_save = r_dcache_fsm; 4412 break; 4413 } 4414 4414 } 4415 4415 m_cpt_dcache_dir_write++; … … 4523 4523 break; 4524 4524 } 4525 //////////////////////// 4526 case DCACHE_WRITE_DIRTY: 4527 { 4528 m_cost_data_tlb_update_dirty_frz++; 4529 4530 // external cache invalidate request 4531 if ( r_tgt_dcache_req ) 4532 { 4533 r_dcache_fsm = DCACHE_CC_CHECK; 4534 r_dcache_fsm_save = r_dcache_fsm; 4535 break; 4536 } 4537 4538 if ( r_dcache_inval_tlb_rsp ) // Miss read response and tlb invalidation 4539 { 4540 r_dcache_fsm = DCACHE_IDLE; 4541 if ( r_dcache_sc_updt_dirty ) r_dcache_sc_updt_dirty = false; 4542 r_dcache_inval_tlb_rsp = false; 4543 break; 4544 } 4545 4546 if ( r_dcache_inval_rsp ) // TLB miss response and cache invalidation 4547 { 4548 r_dcache_fsm = DCACHE_IDLE; 4549 if ( r_dcache_sc_updt_dirty ) r_dcache_sc_updt_dirty = false; 4550 r_dcache_inval_rsp = false; 4551 break; 4552 } 4553 4554 dcache_tlb.setdirty(r_dcache_tlb_way_save, r_dcache_tlb_set_save); 4555 if ( r_dcache_sc_updt_dirty ) 4556 { 4557 r_dcache_sc_updt_dirty = false; 4558 r_dcache_unc_req = true; 4559 r_dcache_fsm = DCACHE_UNC_WAIT; 4560 m_cpt_unc_read++; 4561 } 4562 else 4563 { 4564 r_dcache_fsm = DCACHE_WRITE_REQ; 4565 drsp.valid = true; 4566 drsp.rdata = 0; 4567 } 4568 break; 4569 } 4525 4570 ///////////////// 4526 4571 case DCACHE_ERROR: … … 4623 4668 r_dcache_cleanup_line = victim_index; 4624 4669 m_cpt_cc_cleanup_data++; 4625 r_dcache_fsm = DCACHE_TLB_CC_INVAL; 4626 r_dcache_fsm_save = r_dcache_fsm; 4627 break; 4670 if ( r_dcache_in_itlb[m_dcache_sets*way+set] || r_dcache_in_dtlb[m_dcache_sets*way+set] ) 4671 { 4672 r_dcache_fsm = DCACHE_TLB_CC_INVAL; 4673 r_dcache_fsm_save = r_dcache_fsm; 4674 break; 4675 } 4628 4676 } 4629 4677 … … 4733 4781 else 4734 4782 { 4783 bool write_hit = r_dcache.write(r_icache_paddr_save, r_icache_pte_update); 4784 assert(write_hit && "Write on miss ignores data for data MMU update ins access bit"); 4735 4785 r_itlb_acc_dcache_req = false; 4736 4786 r_dcache_fsm = DCACHE_IDLE; … … 4761 4811 } 4762 4812 4763 // DCACHE_TLB1_LL_WAIT DCACHE_TLB1_SC_WAIT DCACHE_LL_DIRTY_WAIT DCACHE_ ITLB_LL_WAIT DCACHE_ITLB_SC_WAIT4813 // DCACHE_TLB1_LL_WAIT DCACHE_TLB1_SC_WAIT DCACHE_LL_DIRTY_WAIT DCACHE_WRITE_DIRTY DCACHE_ITLB_LL_WAIT DCACHE_ITLB_SC_WAIT 4764 4814 // DCACHE_TLB2_LL_WAIT DCACHE_TLB2_SC_WAIT DCACHE_SC_DIRTY_WAIT 4765 4815 if((( /*( r_dcache_fsm_save == DCACHE_UNC_WAIT ) ||*/ … … 4767 4817 ( (r_dcache_paddr_save.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1)))) 4768 4818 || (( ( r_dcache_fsm_save == DCACHE_TLB1_READ ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ ) || 4769 ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT) /* || 4819 ( r_dcache_fsm_save == DCACHE_TLB1_READ_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_READ_UPDT ) || 4820 ( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT ) /* || 4770 4821 ( r_dcache_fsm_save == DCACHE_TLB1_LL_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_LL_WAIT ) || 4771 4822 ( r_dcache_fsm_save == DCACHE_TLB1_SC_WAIT ) || ( r_dcache_fsm_save == DCACHE_TLB2_SC_WAIT ) || 4772 ( r_dcache_fsm_save == DCACHE_LL_DIRTY_WAIT ) || ( r_dcache_fsm_save == DCACHE_SC_DIRTY_WAIT ) */ ) && 4823 ( r_dcache_fsm_save == DCACHE_LL_DIRTY_WAIT ) || ( r_dcache_fsm_save == DCACHE_SC_DIRTY_WAIT ) || 4824 ( r_dcache_fsm_save == DCACHE_WRITE_DIRTY )*/ ) && 4773 4825 ( (r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1))) ) 4774 4826 || (( ( r_dcache_fsm_save == DCACHE_ITLB_READ ) || ( r_dcache_fsm_save == DCACHE_ITLB_UPDT ) /*|| … … 4776 4828 ( (r_icache_paddr_save.read() & ~((m_dcache_words<<2)-1)) == (r_tgt_addr.read() & ~((m_dcache_words<<2)-1))) ) ) 4777 4829 { 4778 data_t dcache_rdata = 0;4779 size_t way = 0;4780 size_t set = 0;4781 bool dcache_hit = r_dcache.read(r_tgt_addr.read(), &dcache_rdata, &way, &set);4782 assert(!dcache_hit && "ignored update req should not be in dcache");4783 4784 4830 r_dcache_inval_rsp = true; 4785 4831 r_tgt_dcache_req = false; … … 4804 4850 if ( dcache_hit ) 4805 4851 { 4806 if (((r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) ==4807 (r_tgt_addr.read() & ~((m_dcache_words<<2)-1))) &&4808 (r_dcache_fsm_save == DCACHE_TLB1_UPDT ||4809 r_dcache_fsm_save == DCACHE_TLB2_UPDT))4810 r_dcache_inval_rsp = true;4811 4852 if ( r_dcache_in_dtlb[m_dcache_sets*way+set] || r_dcache_in_itlb[m_dcache_sets*way+set] ) 4812 4853 { … … 4953 4994 ( r_dcache_fsm_save == DCACHE_TLB1_UPDT ) || ( r_dcache_fsm_save == DCACHE_TLB2_UPDT ) || 4954 4995 ( r_dcache_fsm_save == DCACHE_DTLB1_READ_CACHE ) || ( r_dcache_fsm_save == DCACHE_DTLB2_READ_CACHE ) || 4955 ( r_dcache_fsm_save == DCACHE_LL_DIRTY_WAIT ) || ( r_dcache_fsm_save == DCACHE_SC_DIRTY_WAIT ) ) && 4996 ( r_dcache_fsm_save == DCACHE_LL_DIRTY_WAIT ) || ( r_dcache_fsm_save == DCACHE_SC_DIRTY_WAIT ) || 4997 ( r_dcache_fsm_save == DCACHE_WRITE_DIRTY )) && 4956 4998 (((r_dcache_tlb_paddr.read() & ~((m_dcache_words<<2)-1)) >> (uint32_log2(m_dcache_words) + 2)) == r_dcache_dtlb_inval_line.read()) ) 4957 4999 { … … 4984 5026 if ( dreq.valid ) m_cost_data_miss_frz++; 4985 5027 4986 r_dcache.setinbit(( paddr_t)r_dcache_itlb_cleanup_line.read() << (uint32_log2(m_dcache_words) + 2), r_dcache_in_itlb, false);5028 r_dcache.setinbit(((paddr_t)r_dcache_itlb_cleanup_line.read()<<(uint32_log2(m_dcache_words)+2)), r_dcache_in_itlb, false); 4987 5029 r_dcache_itlb_cleanup_req = false; 4988 5030 r_dcache_fsm = DCACHE_IDLE;
Note: See TracChangeset
for help on using the changeset viewer.
