Index: /trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp =================================================================== --- /trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 798) +++ /trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 799) @@ -330,36 +330,36 @@ tmpl(/**/)::VciMemCache( - sc_module_name name, - const MappingTable &mtp, // mapping table for direct network - const MappingTable &mtx, // mapping table for external network - const IntTab &srcid_x, // global index on external network - const IntTab &tgtid_d, // global index on direct network - const size_t x_width, // number of x bits in platform - const size_t y_width, // number of x bits in platform - const size_t nways, // number of ways per set - const size_t nsets, // number of associative sets - const size_t nwords, // number of words in cache line - const size_t max_copies, // max number of copies in heap - const size_t heap_size, // number of heap entries - const size_t trt_lines, // number of TRT entries - const size_t upt_lines, // number of UPT entries - const size_t ivt_lines, // number of IVT entries - const size_t debug_start_cycle, - const bool debug_ok) + sc_module_name name, + const MappingTable &mtp, // mapping table for direct network + const MappingTable &mtx, // mapping table for external network + const IntTab &srcid_x, // global index on external network + const IntTab &tgtid_d, // global index on direct network + const size_t x_width, // number of x bits in platform + const size_t y_width, // number of x bits in platform + const size_t nways, // number of ways per set + const size_t nsets, // number of associative sets + const size_t nwords, // number of words in cache line + const size_t max_copies, // max number of copies in heap + const size_t heap_size, // number of heap entries + const size_t trt_lines, // number of TRT entries + const size_t upt_lines, // number of UPT entries + const size_t ivt_lines, // number of IVT entries + const size_t debug_start_cycle, + const bool debug_ok) : soclib::caba::BaseModule(name), - p_clk( "p_clk" ), - p_resetn( "p_resetn" ), - p_irq ( "p_irq" ), - p_vci_tgt( "p_vci_tgt" ), - p_vci_ixr( "p_vci_ixr" ), - p_dspin_p2m( "p_dspin_p2m" ), - p_dspin_m2p( "p_dspin_m2p" ), - p_dspin_clack( "p_dspin_clack" ), + p_clk("p_clk"), + p_resetn("p_resetn"), + p_irq ("p_irq"), + p_vci_tgt("p_vci_tgt"), + p_vci_ixr("p_vci_ixr"), + p_dspin_p2m("p_dspin_p2m"), + p_dspin_m2p("p_dspin_m2p"), + p_dspin_clack("p_dspin_clack"), m_seglist(mtp.getSegmentList(tgtid_d)), m_nseg(0), - m_srcid_x( mtx.indexForId(srcid_x)), + m_srcid_x(mtx.indexForId(srcid_x)), m_initiators(1 << vci_param_int::S), m_heap_size(heap_size), @@ -394,10 +394,10 @@ // CONFIG interface - m_config_addr_mask((1<<12)-1), + m_config_addr_mask((1 << 12) - 1), m_config_regr_width(7), m_config_func_width(3), - m_config_regr_idx_mask((1< 0) and + assert((m_nseg > 0) and "MEMC ERROR : At least one segment must be mapped to this component"); @@ -534,5 +534,5 @@ for (seg = m_seglist.begin(); seg != m_seglist.end(); seg++) { - if (seg->special() ) m_seg_config = i; + if (seg->special()) m_seg_config = i; m_seg[i] = & (*seg); i++; @@ -587,6 +587,6 @@ size_t way = 0; size_t set = 0; - size_t word = ((size_t)addr & 0x3F) >> 2; - + size_t word = ((size_t) addr & 0x3F) >> 2; + DirectoryEntry entry = m_cache_directory.read_neutral(addr, &way, &set); @@ -595,9 +595,9 @@ if (entry.valid) { - if (single_word ) + if (single_word) { m_debug_data[word] = m_cache_data.read(way, set, word); - if ( m_debug_previous_valid and - (m_debug_data[word] != m_debug_previous_data[word]) ) + if (m_debug_previous_valid and + (m_debug_data[word] != m_debug_previous_data[word])) { data_change = true; @@ -609,6 +609,6 @@ { m_debug_data[wcur] = m_cache_data.read(way, set, wcur); - if ( m_debug_previous_valid and - (m_debug_data[wcur] != m_debug_previous_data[wcur]) ) + if (m_debug_previous_valid and + (m_debug_data[wcur] != m_debug_previous_data[wcur])) { data_change = true; @@ -620,6 +620,6 @@ // print values if any change if ((entry.valid != m_debug_previous_valid) or - (entry.valid and (entry.count != m_debug_previous_count)) or - (entry.valid and (entry.dirty != m_debug_previous_dirty)) or data_change) + (entry.valid and (entry.count != m_debug_previous_count)) or + (entry.valid and (entry.dirty != m_debug_previous_dirty)) or data_change) { std::cout << "Monitor MEMC " << name() @@ -628,8 +628,8 @@ << " / VAL = " << std::dec << entry.valid << " / WAY = " << way - << " / COUNT = " << entry.count + << " / COUNT = " << entry.count << " / DIRTY = " << entry.dirty - << " / DATA_CHANGE = " << data_change; - if ( single_word ) + << " / DATA_CHANGE = " << data_change; + if (single_word) { std::cout << std::hex << " / value = " << m_debug_data[word] << std::endl; @@ -662,9 +662,11 @@ m_debug_previous_valid = entry.valid; m_debug_previous_dirty = entry.dirty; - for (size_t wcur = 0; wcur < m_words; wcur++) + for (size_t wcur = 0; wcur < m_words; wcur++) + { m_debug_previous_data[wcur] = m_debug_data[wcur]; + } } - + ///////////////////////////////////////////////////// tmpl(uint32_t)::req_distance(uint32_t req_srcid) @@ -795,5 +797,5 @@ ////////////////////////////////////////////////// - tmpl(void)::print_trace( size_t detailed ) + tmpl(void)::print_trace(size_t detailed) ////////////////////////////////////////////////// { @@ -818,8 +820,8 @@ << " | " << alloc_heap_fsm_str[r_alloc_heap_fsm.read()] << std::endl; - if ( detailed ) m_trt.print(0); + if (detailed) m_trt.print(0); } - + ///////////////////////////////////////// tmpl(void)::reset_counters() @@ -866,5 +868,5 @@ m_cpt_cleanup_remote = 0; m_cpt_cleanup_cost = 0; - + m_cpt_read_miss = 0; m_cpt_write_miss = 0; @@ -884,5 +886,6 @@ std::cout << "*** MEM_CACHE " << name() << std::endl; std::cout << "**********************************" << std::dec << std::endl; - if (activity_counters) { + if (activity_counters) + { std::cout << "----------------------------------" << std::dec << std::endl; std::cout << "--- Activity Counters ---" << std::dec << std::endl; @@ -992,5 +995,5 @@ ////////////////////////////////// - tmpl(void) ::transition() + tmpl(void)::transition() ////////////////////////////////// { @@ -998,5 +1001,5 @@ // RESET - if (! p_resetn.read()) + if (!p_resetn.read()) { @@ -1054,6 +1057,6 @@ m_cmd_cas_eop_fifo.init() ; - r_config_cmd = MEMC_CMD_NOP; - r_config_lock = false; + r_config_cmd = MEMC_CMD_NOP; + r_config_lock = false; m_config_to_cc_send_inst_fifo.init(); @@ -1159,5 +1162,5 @@ m_cpt_write_miss = 0; m_cpt_write_dirty = 0; - + m_cpt_trt_rb = 0; m_cpt_trt_full = 0; @@ -1196,5 +1199,5 @@ bool config_rsp_lines_cleanup_decr = false; bool config_rsp_lines_ixr_rsp_decr = false; - + bool config_to_cc_send_fifo_put = false; bool config_to_cc_send_fifo_get = false; @@ -1253,5 +1256,5 @@ // The READ/WRITE commands accepted in the configuration segment are targeting // configuration or status registers. They must contain one single flit. - // - For almost all addressable registers, the response is returned immediately. + // - For almost all addressable registers, the response is returned immediately. // - For MEMC_CMD_TYPE, the response is delayed until the operation is completed. //////////////////////////////////////////////////////////////////////////////////// @@ -1266,8 +1269,10 @@ #if DEBUG_MEMC_TGT_CMD if (m_debug) + { std::cout << " Receive command from srcid " << std::hex << p_vci_tgt.srcid.read() << " / address " << std::hex << p_vci_tgt.address.read() << std::endl; + } #endif // checking segmentation violation @@ -1285,10 +1290,10 @@ } - if (config) /////////// configuration command + if (config) /////////// configuration command { if (!p_vci_tgt.eop.read()) r_tgt_cmd_fsm = TGT_CMD_ERROR; else r_tgt_cmd_fsm = TGT_CMD_CONFIG; } - else //////////// memory access + else //////////// memory access { if (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) @@ -1334,6 +1339,12 @@ "The type specified in the pktid field is incompatible with the NOP CMD"); - if ((p_vci_tgt.pktid.read() & 0x7) == TYPE_CAS) r_tgt_cmd_fsm = TGT_CMD_CAS; - else r_tgt_cmd_fsm = TGT_CMD_WRITE; + if ((p_vci_tgt.pktid.read() & 0x7) == TYPE_CAS) + { + r_tgt_cmd_fsm = TGT_CMD_CAS; + } + else + { + r_tgt_cmd_fsm = TGT_CMD_WRITE; + } } else @@ -1363,4 +1374,5 @@ #if DEBUG_MEMC_TGT_CMD if (m_debug) + { std::cout << " Segmentation violation:" @@ -1370,6 +1382,6 @@ << " / pktid = " << p_vci_tgt.pktid.read() << " / plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; -#endif - + } +#endif } break; @@ -1377,263 +1389,253 @@ //////////////////// case TGT_CMD_CONFIG: // execute config request and return response - { - /////////////////////////////////////////////////////////// - // Decoding CONFIG interface commands // - // // - // VCI ADDRESS // - // ================================================ // - // GLOBAL | LOCAL | ... | FUNC_IDX | REGS_IDX | 00 // - // IDX | IDX | | (3 bits) | (7 bits) | // - // ================================================ // - // // - // For instrumentation : FUNC_IDX = 0b001 // - // // - // REGS_IDX // - // ============================================ // - // Z | Y | X | W // - // (1 bit) | (2 bits) | (3 bits) | (1 bit) // - // ============================================ // - // // - // Z : DIRECT / COHERENCE // - // Y : SUBTYPE ( LOCAL, REMOTE, OTHER ) // - // X : REGISTER INDEX // - // W : HI / LO // - // // - // For configuration: FUNC_IDX = 0b000 // - // // - // REGS_IDX // - // ============================================ // - // RESERVED | X | // - // (4 bits) | (3 bits) | // - // ============================================ // - // // - // X : REGISTER INDEX // - // // - // For WRITE MISS error signaling: FUNC = 0x010 // - // // - // REGS_IDX // - // ============================================ // - // RESERVED | X | // - // (4 bits) | (3 bits) | // - // ============================================ // - // // - // X : REGISTER INDEX // - // // - /////////////////////////////////////////////////////////// - - addr_t addr_lsb = p_vci_tgt.address.read() & - m_config_addr_mask; - - addr_t cell = (addr_lsb / vci_param_int::B); - - size_t regr = cell & - m_config_regr_idx_mask; - - size_t func = (cell >> m_config_regr_width) & - m_config_func_idx_mask; - - bool need_rsp; - int error; - uint32_t rdata = 0; // default value - uint32_t wdata = p_vci_tgt.wdata.read(); - - switch(func) - { - // memory operation - case MEMC_CONFIG: + { + /////////////////////////////////////////////////////////// + // Decoding CONFIG interface commands // + // // + // VCI ADDRESS // + // ================================================ // + // GLOBAL | LOCAL | ... | FUNC_IDX | REGS_IDX | 00 // + // IDX | IDX | | (3 bits) | (7 bits) | // + // ================================================ // + // // + // For instrumentation : FUNC_IDX = 0b001 // + // // + // REGS_IDX // + // ============================================ // + // Z | Y | X | W // + // (1 bit) | (2 bits) | (3 bits) | (1 bit) // + // ============================================ // + // // + // Z : DIRECT / COHERENCE // + // Y : SUBTYPE (LOCAL, REMOTE, OTHER) // + // X : REGISTER INDEX // + // W : HI / LO // + // // + // For configuration: FUNC_IDX = 0b000 // + // // + // REGS_IDX // + // ============================================ // + // RESERVED | X | // + // (4 bits) | (3 bits) | // + // ============================================ // + // // + // X : REGISTER INDEX // + // // + // For WRITE MISS error signaling: FUNC = 0x010 // + // // + // REGS_IDX // + // ============================================ // + // RESERVED | X | // + // (4 bits) | (3 bits) | // + // ============================================ // + // // + // X : REGISTER INDEX // + // // + /////////////////////////////////////////////////////////// + + addr_t addr_lsb = p_vci_tgt.address.read() & m_config_addr_mask; + + addr_t cell = (addr_lsb / vci_param_int::B); + + size_t regr = cell & m_config_regr_idx_mask; + + size_t func = (cell >> m_config_regr_width) & m_config_func_idx_mask; + + bool need_rsp; + int error; + uint32_t rdata = 0; // default value + uint32_t wdata = p_vci_tgt.wdata.read(); + + switch (func) + { + // memory operation + case MEMC_CONFIG: + { + if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) // get lock + and (regr == MEMC_LOCK)) { - if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) // get lock - and (regr == MEMC_LOCK)) - { - rdata = (uint32_t) r_config_lock.read(); - need_rsp = true; - error = 0; - r_config_lock = true; - } - else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // release lock - and (regr == MEMC_LOCK)) - { - need_rsp = true; - error = 0; - r_config_lock = false; - } - else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_lo - and (regr == MEMC_ADDR_LO)) - { - assert( ((wdata % (m_words * vci_param_int::B)) == 0) and - "VCI_MEM_CACHE CONFIG ERROR: The buffer must be aligned on a cache line"); - - need_rsp = true; - error = 0; - r_config_address = (r_config_address.read() & 0xFFFFFFFF00000000LL) | - ((addr_t)wdata); - } - else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_hi - and (regr == MEMC_ADDR_HI)) - - { - need_rsp = true; - error = 0; - r_config_address = (r_config_address.read() & 0x00000000FFFFFFFFLL) | - (((addr_t) wdata) << 32); - } - else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set buf_lines - and (regr == MEMC_BUF_LENGTH)) - { - need_rsp = true; - error = 0; - size_t lines = wdata / (m_words << 2); - if (wdata % (m_words << 2)) lines++; - r_config_cmd_lines = lines; - r_config_rsp_lines = 0; - } - else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set cmd type - and (regr == MEMC_CMD_TYPE)) - { - need_rsp = false; - error = 0; - r_config_cmd = wdata; - - // prepare delayed response from CONFIG FSM - r_config_srcid = p_vci_tgt.srcid.read(); - r_config_trdid = p_vci_tgt.trdid.read(); - r_config_pktid = p_vci_tgt.pktid.read(); - } - else - { - need_rsp = true; - error = 1; - } - - break; + rdata = (uint32_t) r_config_lock.read(); + need_rsp = true; + error = 0; + r_config_lock = true; } - - // instrumentation registers - case MEMC_INSTRM: - { - need_rsp = true; - - if (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) - { - error = read_instrumentation(regr, rdata); - } - else - { - error = 1; - } - - break; - } - - // xram GET bus error registers - case MEMC_RERROR: + else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // release lock + and (regr == MEMC_LOCK)) { need_rsp = true; error = 0; - - if (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) - { - switch (regr) - { - case MEMC_RERROR_IRQ_ENABLE: - r_xram_rsp_rerror_irq_enable = - (p_vci_tgt.wdata.read() != 0); - - break; - - default: - error = 1; - break; - } - } - else if (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) - { - switch (regr) - { - case MEMC_RERROR_SRCID: - rdata = (uint32_t) - r_xram_rsp_rerror_rsrcid.read(); - - break; - - case MEMC_RERROR_ADDR_LO: - rdata = (uint32_t) - (r_xram_rsp_rerror_address.read()) & - ((1ULL<<32)-1); - - break; - - case MEMC_RERROR_ADDR_HI: - rdata = (uint32_t) - (r_xram_rsp_rerror_address.read() >> 32) & - ((1ULL<<32)-1); - - break; - - case MEMC_RERROR_IRQ_RESET: - if (not r_xram_rsp_rerror_irq.read()) break; - - r_xram_rsp_rerror_irq = false; - - break; - - case MEMC_RERROR_IRQ_ENABLE: - rdata = (uint32_t) - (r_xram_rsp_rerror_irq_enable.read()) ? 1 : 0; - - break; - - default: - error = 1; - break; - } - } - else - { - error = 1; - } - - break; + r_config_lock = false; } - - //unknown function - default: + else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_lo + and (regr == MEMC_ADDR_LO)) + { + assert(((wdata % (m_words * vci_param_int::B)) == 0) and + "VCI_MEM_CACHE CONFIG ERROR: The buffer must be aligned on a cache line"); + + need_rsp = true; + error = 0; + r_config_address = (r_config_address.read() & 0xFFFFFFFF00000000LL) | + ((addr_t)wdata); + } + else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set addr_hi + and (regr == MEMC_ADDR_HI)) + + { + need_rsp = true; + error = 0; + r_config_address = (r_config_address.read() & 0x00000000FFFFFFFFLL) | + (((addr_t) wdata) << 32); + } + else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set buf_lines + and (regr == MEMC_BUF_LENGTH)) + { + need_rsp = true; + error = 0; + size_t lines = wdata / (m_words << 2); + if (wdata % (m_words << 2)) lines++; + r_config_cmd_lines = lines; + r_config_rsp_lines = 0; + } + else if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) // set cmd type + and (regr == MEMC_CMD_TYPE)) + { + need_rsp = false; + error = 0; + r_config_cmd = wdata; + + // prepare delayed response from CONFIG FSM + r_config_srcid = p_vci_tgt.srcid.read(); + r_config_trdid = p_vci_tgt.trdid.read(); + r_config_pktid = p_vci_tgt.pktid.read(); + } + else { need_rsp = true; error = 1; - - break; } - } - - if (need_rsp) - { - // blocked if previous pending request to TGT_RSP FSM - if (r_tgt_cmd_to_tgt_rsp_req.read()) break; - - r_tgt_cmd_to_tgt_rsp_srcid = p_vci_tgt.srcid.read(); - r_tgt_cmd_to_tgt_rsp_trdid = p_vci_tgt.trdid.read(); - r_tgt_cmd_to_tgt_rsp_pktid = p_vci_tgt.pktid.read(); - r_tgt_cmd_to_tgt_rsp_req = true; - r_tgt_cmd_to_tgt_rsp_error = error; - r_tgt_cmd_to_tgt_rsp_rdata = rdata; - } - - r_tgt_cmd_fsm = TGT_CMD_IDLE; + + break; + } + + // instrumentation registers + case MEMC_INSTRM: + { + need_rsp = true; + + if (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) + { + error = read_instrumentation(regr, rdata); + } + else + { + error = 1; + } + + break; + } + + // xram GET bus error registers + case MEMC_RERROR: + { + need_rsp = true; + error = 0; + + if (p_vci_tgt.cmd.read() == vci_param_int::CMD_WRITE) + { + switch (regr) + { + case MEMC_RERROR_IRQ_ENABLE: + r_xram_rsp_rerror_irq_enable = + (p_vci_tgt.wdata.read() != 0); + + break; + + default: + error = 1; + break; + } + } + else if (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ) + { + switch (regr) + { + case MEMC_RERROR_SRCID: + rdata = (uint32_t) + r_xram_rsp_rerror_rsrcid.read(); + break; + + case MEMC_RERROR_ADDR_LO: + rdata = (uint32_t) + (r_xram_rsp_rerror_address.read()) & ((1ULL << 32) - 1); + + break; + + case MEMC_RERROR_ADDR_HI: + rdata = (uint32_t) + (r_xram_rsp_rerror_address.read() >> 32) & ((1ULL << 32) - 1); + break; + + case MEMC_RERROR_IRQ_RESET: + if (not r_xram_rsp_rerror_irq.read()) break; + r_xram_rsp_rerror_irq = false; + break; + + case MEMC_RERROR_IRQ_ENABLE: + rdata = (uint32_t) (r_xram_rsp_rerror_irq_enable.read()) ? 1 : 0; + break; + + default: + error = 1; + break; + } + } + else + { + error = 1; + } + + break; + } + + //unknown function + default: + { + need_rsp = true; + error = 1; + break; + } + } + + if (need_rsp) + { + // blocked if previous pending request to TGT_RSP FSM + if (r_tgt_cmd_to_tgt_rsp_req.read()) break; + + r_tgt_cmd_to_tgt_rsp_srcid = p_vci_tgt.srcid.read(); + r_tgt_cmd_to_tgt_rsp_trdid = p_vci_tgt.trdid.read(); + r_tgt_cmd_to_tgt_rsp_pktid = p_vci_tgt.pktid.read(); + r_tgt_cmd_to_tgt_rsp_req = true; + r_tgt_cmd_to_tgt_rsp_error = error; + r_tgt_cmd_to_tgt_rsp_rdata = rdata; + } + + r_tgt_cmd_fsm = TGT_CMD_IDLE; #if DEBUG_MEMC_TGT_CMD - if (m_debug) - std::cout << " Configuration request:" - << " address = " << std::hex << p_vci_tgt.address.read() - << " / func = " << func - << " / regr = " << regr - << " / rdata = " << rdata - << " / wdata = " << p_vci_tgt.wdata.read() - << " / need_rsp = " << need_rsp - << " / error = " << error << std::endl; -#endif - break; - } - ////////////////// + if (m_debug) + { + std::cout << " Configuration request:" + << " address = " << std::hex << p_vci_tgt.address.read() + << " / func = " << func + << " / regr = " << regr + << " / rdata = " << rdata + << " / wdata = " << p_vci_tgt.wdata.read() + << " / need_rsp = " << need_rsp + << " / error = " << error << std::endl; + } +#endif + break; + } + ////////////////// case TGT_CMD_READ: // Push a read request into read fifo @@ -1652,7 +1654,7 @@ << " read command packet must contain one single flit" << std::endl; exit(0); - } + } // check plen for LL - if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) and + if ((p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) and (p_vci_tgt.plen.read() != 8)) { @@ -1667,4 +1669,5 @@ #if DEBUG_MEMC_TGT_CMD if (m_debug) + { std::cout << " Push into read_fifo:" << " address = " << std::hex << p_vci_tgt.address.read() @@ -1673,8 +1676,10 @@ << " / pktid = " << p_vci_tgt.pktid.read() << " / plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; + } #endif cmd_read_fifo_put = true; // - if (p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) { + if (p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) + { if (is_local_req(p_vci_tgt.srcid.read())) { @@ -1689,9 +1694,9 @@ } else { - if (is_local_req(p_vci_tgt.srcid.read())) + if (is_local_req(p_vci_tgt.srcid.read())) { m_cpt_read_local++; } - else + else { m_cpt_read_remote++; @@ -1712,4 +1717,5 @@ #if DEBUG_MEMC_TGT_CMD if (m_debug) + { std::cout << " Push into write_fifo:" << " address = " << std::hex << p_vci_tgt.address.read() @@ -1720,13 +1726,15 @@ << " / be = " << p_vci_tgt.be.read() << " / plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; + } #endif cmd_write_fifo_put = true; // - if (p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP) { + if (p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP) + { // (2 (CMD) + 1 (RSP)) flits VCI => 4 + (1 (success) || 2 (failure)) flits dspin m_cpt_sc_cost += 5 * req_distance(p_vci_tgt.srcid.read()); } else { - if (is_local_req(p_vci_tgt.srcid.read())) + if (is_local_req(p_vci_tgt.srcid.read())) { m_cpt_write_flits_local++; @@ -1741,7 +1749,9 @@ // - if (p_vci_tgt.eop) { + if (p_vci_tgt.eop) + { // - if (p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP) { + if (p_vci_tgt.cmd.read() == vci_param_int::CMD_NOP) + { if (is_local_req(p_vci_tgt.srcid.read())) { @@ -1783,4 +1793,5 @@ #if DEBUG_MEMC_TGT_CMD if (m_debug) + { std::cout << " Pushing command into cmd_cas_fifo:" << " address = " << std::hex << p_vci_tgt.address.read() @@ -1791,7 +1802,9 @@ << " be = " << p_vci_tgt.be.read() << " plen = " << std::dec << p_vci_tgt.plen.read() << std::endl; + } #endif cmd_cas_fifo_put = true; - if (p_vci_tgt.eop) { + if (p_vci_tgt.eop) + { // if (is_local_req(p_vci_tgt.srcid.read())) @@ -1799,5 +1812,5 @@ m_cpt_cas_local++; } - else + else { m_cpt_cas_remote++; @@ -1815,5 +1828,5 @@ // MULTI_ACK FSM ///////////////////////////////////////////////////////////////////////// - // This FSM controls the response to the multicast update requests sent + // This FSM controls the response to the multicast update requests sent // by the memory cache to the L1 caches and update the UPT. // @@ -1827,151 +1840,155 @@ //////////////////////////////////////////////////////////////////////// - //std::cout << std::endl << "multi_ack_fsm" << std::endl; - - switch(r_multi_ack_fsm.read()) + switch (r_multi_ack_fsm.read()) { //////////////////// case MULTI_ACK_IDLE: - { - bool multi_ack_fifo_rok = m_cc_receive_to_multi_ack_fifo.rok(); - - // No CC_RECEIVE FSM request and no WRITE FSM request - if (not multi_ack_fifo_rok and not r_write_to_multi_ack_req.read()) - break; - - uint8_t updt_index; - - // handling WRITE FSM request to decrement update table response - // counter if no CC_RECEIVE FSM request - if (not multi_ack_fifo_rok) - { - updt_index = r_write_to_multi_ack_upt_index.read(); - r_write_to_multi_ack_req = false; - } - // Handling CC_RECEIVE FSM request + { + bool multi_ack_fifo_rok = m_cc_receive_to_multi_ack_fifo.rok(); + + // No CC_RECEIVE FSM request and no WRITE FSM request + if (not multi_ack_fifo_rok and not r_write_to_multi_ack_req.read()) + break; + + uint8_t updt_index; + + // handling WRITE FSM request to decrement update table response + // counter if no CC_RECEIVE FSM request + if (not multi_ack_fifo_rok) + { + updt_index = r_write_to_multi_ack_upt_index.read(); + r_write_to_multi_ack_req = false; + } + // Handling CC_RECEIVE FSM request + else + { + uint64_t flit = m_cc_receive_to_multi_ack_fifo.read(); + updt_index = DspinDhccpParam::dspin_get(flit, + DspinDhccpParam::MULTI_ACK_UPDT_INDEX); + + cc_receive_to_multi_ack_fifo_get = true; + } + + assert((updt_index < m_upt.size()) and + "VCI_MEM_CACHE ERROR in MULTI_ACK_IDLE : " + "index too large for UPT"); + + r_multi_ack_upt_index = updt_index; + r_multi_ack_fsm = MULTI_ACK_UPT_LOCK; + +#if DEBUG_MEMC_MULTI_ACK + if (m_debug) + { + if (multi_ack_fifo_rok) + { + std::cout << " Response for UPT entry " + << (size_t) updt_index << std::endl; + } else { - uint64_t flit = m_cc_receive_to_multi_ack_fifo.read(); - updt_index = DspinDhccpParam::dspin_get(flit, - DspinDhccpParam::MULTI_ACK_UPDT_INDEX); - - cc_receive_to_multi_ack_fifo_get = true; - } - - assert((updt_index < m_upt.size()) and - "VCI_MEM_CACHE ERROR in MULTI_ACK_IDLE : " - "index too large for UPT"); - - r_multi_ack_upt_index = updt_index; - r_multi_ack_fsm = MULTI_ACK_UPT_LOCK; + std::cout << " Write FSM request to decrement UPT entry " + << updt_index << std::endl; + } + } +#endif + break; + } + + //////////////////////// + case MULTI_ACK_UPT_LOCK: + { + // get lock to the UPDATE table + if (r_alloc_upt_fsm.read() != ALLOC_UPT_MULTI_ACK) break; + + // decrement the number of expected responses + size_t count = 0; + bool valid = m_upt.decrement(r_multi_ack_upt_index.read(), count); + + if (not valid) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() + << " MULTI_ACK_UPT_LOCK state" << std::endl + << "unsuccessful access to decrement the UPT" << std::endl; + exit(0); + } + + if (count == 0) + { + r_multi_ack_fsm = MULTI_ACK_UPT_CLEAR; + } + else + { + r_multi_ack_fsm = MULTI_ACK_IDLE; + } #if DEBUG_MEMC_MULTI_ACK - if (m_debug) - { - if (multi_ack_fifo_rok) - { - std::cout << " Response for UPT entry " - << (size_t)updt_index << std::endl; - } - else - { - std::cout << " Write FSM request to decrement UPT entry " - << updt_index << std::endl; - } - } -#endif - break; - } - - //////////////////////// - case MULTI_ACK_UPT_LOCK: - { - // get lock to the UPDATE table - if (r_alloc_upt_fsm.read() != ALLOC_UPT_MULTI_ACK) break; - - // decrement the number of expected responses - size_t count = 0; - bool valid = m_upt.decrement(r_multi_ack_upt_index.read(), count); - - if (not valid) - { - std::cout << "VCI_MEM_CACHE ERROR " << name() - << " MULTI_ACK_UPT_LOCK state" << std::endl - << "unsuccessful access to decrement the UPT" << std::endl; - exit(0); - } - - if (count == 0) - { - r_multi_ack_fsm = MULTI_ACK_UPT_CLEAR; - } - else - { - r_multi_ack_fsm = MULTI_ACK_IDLE; - } + if (m_debug) + { + std::cout << " Decrement the responses counter for UPT:" + << " entry = " << r_multi_ack_upt_index.read() + << " / rsp_count = " << std::dec << count << std::endl; + } +#endif + break; + } + + ///////////////////////// + case MULTI_ACK_UPT_CLEAR: // Clear UPT entry / Test if rsp or ack required + { + if (r_alloc_upt_fsm.read() != ALLOC_UPT_MULTI_ACK) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() + << " MULTI_ACK_UPT_CLEAR state" + << " bad UPT allocation" << std::endl; + exit(0); + } + + r_multi_ack_srcid = m_upt.srcid(r_multi_ack_upt_index.read()); + r_multi_ack_trdid = m_upt.trdid(r_multi_ack_upt_index.read()); + r_multi_ack_pktid = m_upt.pktid(r_multi_ack_upt_index.read()); + r_multi_ack_nline = m_upt.nline(r_multi_ack_upt_index.read()); + bool need_rsp = m_upt.need_rsp(r_multi_ack_upt_index.read()); + + // clear the UPT entry + m_upt.clear(r_multi_ack_upt_index.read()); + + if (need_rsp) r_multi_ack_fsm = MULTI_ACK_WRITE_RSP; + else r_multi_ack_fsm = MULTI_ACK_IDLE; #if DEBUG_MEMC_MULTI_ACK - if (m_debug) - std::cout << " Decrement the responses counter for UPT:" - << " entry = " << r_multi_ack_upt_index.read() - << " / rsp_count = " << std::dec << count << std::endl; -#endif - break; - } - - ///////////////////////// - case MULTI_ACK_UPT_CLEAR: // Clear UPT entry / Test if rsp or ack required - { - if (r_alloc_upt_fsm.read() != ALLOC_UPT_MULTI_ACK) - { - std::cout << "VCI_MEM_CACHE ERROR " << name() - << " MULTI_ACK_UPT_CLEAR state" - << " bad UPT allocation" << std::endl; - exit(0); - } - - r_multi_ack_srcid = m_upt.srcid(r_multi_ack_upt_index.read()); - r_multi_ack_trdid = m_upt.trdid(r_multi_ack_upt_index.read()); - r_multi_ack_pktid = m_upt.pktid(r_multi_ack_upt_index.read()); - r_multi_ack_nline = m_upt.nline(r_multi_ack_upt_index.read()); - bool need_rsp = m_upt.need_rsp(r_multi_ack_upt_index.read()); - - // clear the UPT entry - m_upt.clear(r_multi_ack_upt_index.read()); - - if ( need_rsp ) r_multi_ack_fsm = MULTI_ACK_WRITE_RSP; - else r_multi_ack_fsm = MULTI_ACK_IDLE; + if (m_debug) + { + std::cout << " Clear UPT entry " + << std::dec << r_multi_ack_upt_index.read() << std::endl; + } +#endif + break; + } + ///////////////////////// + case MULTI_ACK_WRITE_RSP: // Post a response request to TGT_RSP FSM + // Wait if pending request + { + if (r_multi_ack_to_tgt_rsp_req.read()) break; + + r_multi_ack_to_tgt_rsp_req = true; + r_multi_ack_to_tgt_rsp_srcid = r_multi_ack_srcid.read(); + r_multi_ack_to_tgt_rsp_trdid = r_multi_ack_trdid.read(); + r_multi_ack_to_tgt_rsp_pktid = r_multi_ack_pktid.read(); + r_multi_ack_fsm = MULTI_ACK_IDLE; #if DEBUG_MEMC_MULTI_ACK - if (m_debug) - std::cout << " Clear UPT entry " - << std::dec << r_multi_ack_upt_index.read() << std::endl; -#endif - break; - } - ///////////////////////// - case MULTI_ACK_WRITE_RSP: // Post a response request to TGT_RSP FSM - // Wait if pending request - { - if (r_multi_ack_to_tgt_rsp_req.read()) break; - - r_multi_ack_to_tgt_rsp_req = true; - r_multi_ack_to_tgt_rsp_srcid = r_multi_ack_srcid.read(); - r_multi_ack_to_tgt_rsp_trdid = r_multi_ack_trdid.read(); - r_multi_ack_to_tgt_rsp_pktid = r_multi_ack_pktid.read(); - r_multi_ack_fsm = MULTI_ACK_IDLE; - -#if DEBUG_MEMC_MULTI_ACK - if (m_debug) - std::cout << " " - << " Request TGT_RSP FSM to send a response to srcid " - << std::hex << r_multi_ack_srcid.read() << std::endl; -#endif - break; - } + if (m_debug) + { + std::cout << " " + << " Request TGT_RSP FSM to send a response to srcid " + << std::hex << r_multi_ack_srcid.read() << std::endl; + } +#endif + break; + } } // end switch r_multi_ack_fsm @@ -1989,8 +2006,8 @@ // - uint32_t r_config_rsp_lines : number of lines not completed // - // For both INVAL and SYNC commands, the CONFIG FSM contains the loop handling + // For both INVAL and SYNC commands, the CONFIG FSM contains the loop handling // all cache lines covered by the buffer. The various lines of a given buffer // can be pipelined: the CONFIG FSM does not wait the response for line (n) to send - // the command for line (n+1). It decrements the r_config_cmd_lines counter until + // the command for line (n+1). It decrements the r_config_cmd_lines counter until // the last request has been registered in TRT (for a SYNC), or in IVT (for an INVAL). // The r_config_rsp_lines counter contains the number of expected responses from @@ -2002,6 +2019,6 @@ // // - INVAL request: - // For each line, it access to the DIR. - // In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. + // For each line, it access to the DIR. + // In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. // In case of hit, with no copies in L1 caches, the line is invalidated and // a response is requested to TGT_RSP FSM. @@ -2014,8 +2031,8 @@ // This constraint can be released, but it requires to make 2 PUT transactions // for the first and the last line... - // + // // - SYNC request: - // For each line, it access to the DIR. - // In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. + // For each line, it access to the DIR. + // In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. // In case of hit, a PUT transaction is registered in TRT and a request is sent // to IXR_CMD FSM. The IXR_RSP FSM decrements the r_config_rsp_lines counter @@ -2024,5 +2041,5 @@ // // From the software point of view, a configuration request is a sequence - // of 6 atomic accesses in an uncached segment. A dedicated lock is used + // of 6 atomic accesses in an uncached segment. A dedicated lock is used // to handle only one configuration command at a given time: // - Read MEMC_LOCK : Get the lock @@ -2036,19 +2053,21 @@ //std::cout << std::endl << "config_fsm" << std::endl; - switch( r_config_fsm.read()) + switch (r_config_fsm.read()) { ///////////////// - case CONFIG_IDLE: // waiting a config request - { - if (r_config_cmd.read() != MEMC_CMD_NOP ) - { - r_config_fsm = CONFIG_LOOP; + case CONFIG_IDLE: // waiting a config request + { + if (r_config_cmd.read() != MEMC_CMD_NOP) + { + r_config_fsm = CONFIG_LOOP; #if DEBUG_MEMC_CONFIG -if (m_debug) - std::cout << " Config Request received" - << " / address = " << std::hex << r_config_address.read() - << " / lines = " << std::dec << r_config_cmd_lines.read() - << " / type = " << r_config_cmd.read() << std::endl; + if (m_debug) + { + std::cout << " Config Request received" + << " / address = " << std::hex << r_config_address.read() + << " / lines = " << std::dec << r_config_cmd_lines.read() + << " / type = " << r_config_cmd.read() << std::endl; + } #endif } @@ -2058,5 +2077,5 @@ case CONFIG_LOOP: // test if last line to be handled { - if (r_config_cmd_lines.read() == 0 ) + if (r_config_cmd_lines.read() == 0) { r_config_cmd = MEMC_CMD_NOP; @@ -2069,16 +2088,18 @@ #if DEBUG_MEMC_CONFIG -if (m_debug) -std::cout << " " - << " / address = " << std::hex << r_config_address.read() - << " / lines not handled = " << std::dec << r_config_cmd_lines.read() - << " / command = " << r_config_cmd.read() << std::endl; + if (m_debug) + { + std::cout << " " + << " / address = " << std::hex << r_config_address.read() + << " / lines not handled = " << std::dec << r_config_cmd_lines.read() + << " / command = " << r_config_cmd.read() << std::endl; + } #endif break; } ///////////////// - case CONFIG_WAIT: // wait completion (last response) - { - if (r_config_rsp_lines.read() == 0 ) // last response received + case CONFIG_WAIT: // wait completion (last response) + { + if (r_config_rsp_lines.read() == 0) // last response received { r_config_fsm = CONFIG_RSP; @@ -2086,29 +2107,33 @@ #if DEBUG_MEMC_CONFIG -if (m_debug) -std::cout << " " - << " / lines to do = " << std::dec << r_config_rsp_lines.read() << std::endl; + if (m_debug) + { + std::cout << " " + << " / lines to do = " << std::dec << r_config_rsp_lines.read() << std::endl; + } #endif break; } //////////////// - case CONFIG_RSP: // request TGT_RSP FSM to return response + case CONFIG_RSP: // request TGT_RSP FSM to return response { if (not r_config_to_tgt_rsp_req.read()) { - r_config_to_tgt_rsp_srcid = r_config_srcid.read(); - r_config_to_tgt_rsp_trdid = r_config_trdid.read(); - r_config_to_tgt_rsp_pktid = r_config_pktid.read(); - r_config_to_tgt_rsp_error = false; - r_config_to_tgt_rsp_req = true; - r_config_fsm = CONFIG_IDLE; + r_config_to_tgt_rsp_srcid = r_config_srcid.read(); + r_config_to_tgt_rsp_trdid = r_config_trdid.read(); + r_config_to_tgt_rsp_pktid = r_config_pktid.read(); + r_config_to_tgt_rsp_error = false; + r_config_to_tgt_rsp_req = true; + r_config_fsm = CONFIG_IDLE; #if DEBUG_MEMC_CONFIG -if (m_debug) -std::cout << " Request TGT_RSP FSM to send response:" - << " error = " << r_config_to_tgt_rsp_error.read() - << " / rsrcid = " << std::hex << r_config_srcid.read() - << " / rtrdid = " << std::hex << r_config_trdid.read() - << " / rpktid = " << std::hex << r_config_pktid.read() << std::endl; + if (m_debug) + { + std::cout << " Request TGT_RSP FSM to send response:" + << " error = " << r_config_to_tgt_rsp_error.read() + << " / rsrcid = " << std::hex << r_config_srcid.read() + << " / rtrdid = " << std::hex << r_config_trdid.read() + << " / rpktid = " << std::hex << r_config_pktid.read() << std::endl; + } #endif } @@ -2118,5 +2143,5 @@ case CONFIG_DIR_REQ: // Request directory lock { - if (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG ) + if (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) { r_config_fsm = CONFIG_DIR_ACCESS; @@ -2124,7 +2149,9 @@ #if DEBUG_MEMC_CONFIG -if (m_debug) -std::cout << " " - << " Request DIR access" << std::endl; + if (m_debug) + { + std::cout << " " + << " Request DIR access" << std::endl; + } #endif break; @@ -2133,5 +2160,5 @@ case CONFIG_DIR_ACCESS: // Access directory and decode config command { - assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and + assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and "MEMC ERROR in CONFIG_DIR_ACCESS state: bad DIR allocation"); @@ -2147,30 +2174,32 @@ r_config_dir_ptr = entry.ptr; - if (entry.valid and // hit & inval command - (r_config_cmd.read() == MEMC_CMD_INVAL)) - { - r_config_fsm = CONFIG_IVT_LOCK; - } - else if (entry.valid and // hit & sync command + if (entry.valid and // hit & inval command + (r_config_cmd.read() == MEMC_CMD_INVAL)) + { + r_config_fsm = CONFIG_IVT_LOCK; + } + else if (entry.valid and // hit & sync command entry.dirty and (r_config_cmd.read() == MEMC_CMD_SYNC)) - { - r_config_fsm = CONFIG_TRT_LOCK; - } - else // miss : return to LOOP + { + r_config_fsm = CONFIG_TRT_LOCK; + } + else // miss : return to LOOP { r_config_cmd_lines = r_config_cmd_lines.read() - 1; - r_config_address = r_config_address.read() + (m_words<<2); + r_config_address = r_config_address.read() + (m_words << 2); r_config_fsm = CONFIG_LOOP; } #if DEBUG_MEMC_CONFIG -if (m_debug) -std::cout << " Accessing directory: " - << " address = " << std::hex << r_config_address.read() - << " / hit = " << std::dec << entry.valid - << " / dirty = " << entry.dirty - << " / count = " << entry.count - << " / is_cnt = " << entry.is_cnt << std::endl; + if (m_debug) + { + std::cout << " Accessing directory: " + << " address = " << std::hex << r_config_address.read() + << " / hit = " << std::dec << entry.valid + << " / dirty = " << entry.dirty + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt << std::endl; + } #endif break; @@ -2178,5 +2207,5 @@ ///////////////////// case CONFIG_TRT_LOCK: // enter this state in case of SYNC command - // to a dirty cache line + // to a dirty cache line // keep DIR lock, and try to get TRT lock // return to LOOP state if TRT full @@ -2184,13 +2213,13 @@ // transaction in TRT if not full. { - assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and + assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and "MEMC ERROR in CONFIG_TRT_LOCK state: bad DIR allocation"); - if (r_alloc_trt_fsm.read() == ALLOC_TRT_CONFIG ) + if (r_alloc_trt_fsm.read() == ALLOC_TRT_CONFIG) { size_t index = 0; - bool wok = not m_trt.full(index); - - if (not wok ) + bool wok = not m_trt.full(index); + + if (not wok) { r_config_fsm = CONFIG_LOOP; @@ -2198,6 +2227,6 @@ else { - size_t way = r_config_dir_way.read(); - size_t set = m_y[r_config_address.read()]; + size_t way = r_config_dir_way.read(); + size_t set = m_y[r_config_address.read()]; // reset dirty bit in DIR @@ -2212,5 +2241,5 @@ entry.owner.inst = r_config_dir_copy_inst.read(); entry.owner.srcid = r_config_dir_copy_srcid.read(); - m_cache_directory.write( set, way, entry ); + m_cache_directory.write(set, way, entry); r_config_trt_index = index; @@ -2219,8 +2248,10 @@ #if DEBUG_MEMC_CONFIG -if (m_debug) -std::cout << " Access TRT: " - << " wok = " << std::dec << wok - << " index = " << index << std::endl; + if (m_debug) + { + std::cout << " Access TRT: " + << " wok = " << std::dec << wok + << " index = " << index << std::endl; + } #endif } @@ -2231,43 +2262,45 @@ // and post a PUT request in TRT { - assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and + assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and "MEMC ERROR in CONFIG_TRT_SET state: bad DIR allocation"); - assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_CONFIG) and + assert((r_alloc_trt_fsm.read() == ALLOC_TRT_CONFIG) and "MEMC ERROR in CONFIG_TRT_SET state: bad TRT allocation"); // read data into cache - size_t way = r_config_dir_way.read(); - size_t set = m_y[r_config_address.read()]; + size_t way = r_config_dir_way.read(); + size_t set = m_y[r_config_address.read()]; std::vector data_vector; data_vector.clear(); - for(size_t word=0; word(m_words,0xF), // byte-enable: unused - data_vector, // data to be written - 0, // ll_key: unused - true ); // requested by config FSM + m_trt.set(r_config_trt_index.read(), + false, // PUT transaction + m_nline[r_config_address.read()], // line index + 0, // srcid: unused + 0, // trdid: unused + 0, // pktid: unused + false, // not proc_read + 0, // read_length: unused + 0, // word_index: unused + std::vector(m_words, 0xF), // byte-enable: unused + data_vector, // data to be written + 0, // ll_key: unused + true); // requested by config FSM config_rsp_lines_incr = true; r_config_fsm = CONFIG_PUT_REQ; #if DEBUG_MEMC_CONFIG -if (m_debug) -std::cout << " PUT request in TRT:" - << " address = " << std::hex << r_config_address.read() - << " index = " << std::dec << r_config_trt_index.read() << std::endl; + if (m_debug) + { + std::cout << " PUT request in TRT:" + << " address = " << std::hex << r_config_address.read() + << " index = " << std::dec << r_config_trt_index.read() << std::endl; + } #endif break; @@ -2282,12 +2315,14 @@ // prepare next iteration - r_config_cmd_lines = r_config_cmd_lines.read() - 1; - r_config_address = r_config_address.read() + (m_words<<2); - r_config_fsm = CONFIG_LOOP; + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_address = r_config_address.read() + (m_words << 2); + r_config_fsm = CONFIG_LOOP; #if DEBUG_MEMC_CONFIG -if (m_debug) -std::cout << " post PUT request to IXR_CMD_FSM" - << " / address = " << std::hex << r_config_address.read() << std::endl; + if (m_debug) + { + std::cout << " post PUT request to IXR_CMD_FSM" + << " / address = " << std::hex << r_config_address.read() << std::endl; + } #endif } @@ -2299,63 +2334,73 @@ // Return to LOOP state if IVT full. // Register inval in IVT, and invalidate the - // directory if IVT not full. - { - assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and + // directory if IVT not full. + { + assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and "MEMC ERROR in CONFIG_IVT_LOCK state: bad DIR allocation"); - if (r_alloc_ivt_fsm.read() == ALLOC_IVT_CONFIG ) - { - size_t set = m_y[(addr_t)(r_config_address.read())]; - size_t way = r_config_dir_way.read(); - - if (r_config_dir_count.read() == 0 ) // inval DIR and return to LOOP - { - m_cache_directory.inval( way, set ); - r_config_cmd_lines = r_config_cmd_lines.read() - 1; - r_config_address = r_config_address.read() + (m_words<<2); - r_config_fsm = CONFIG_LOOP; + if (r_alloc_ivt_fsm.read() == ALLOC_IVT_CONFIG) + { + size_t set = m_y[(addr_t) (r_config_address.read())]; + size_t way = r_config_dir_way.read(); + + if (r_config_dir_count.read() == 0) // inval DIR and return to LOOP + { + m_cache_directory.inval(way, set); + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_address = r_config_address.read() + (m_words << 2); + r_config_fsm = CONFIG_LOOP; #if DEBUG_MEMC_CONFIG -if (m_debug) -std::cout << " " - << " No copies in L1 : inval DIR entry" << std::endl; + if (m_debug) + { + std::cout << " " + << " No copies in L1 : inval DIR entry" << std::endl; + } #endif } else // try to register inval in IVT { - bool wok = false; - size_t index = 0; - bool broadcast = r_config_dir_is_cnt.read(); - size_t srcid = r_config_srcid.read(); - size_t trdid = r_config_trdid.read(); - size_t pktid = r_config_pktid.read(); - addr_t nline = m_nline[(addr_t)(r_config_address.read())]; - size_t nb_copies = r_config_dir_count.read(); - - wok = m_ivt.set( false, // it's an inval transaction - broadcast, - false, // no response required - true, // acknowledge required - srcid, - trdid, - pktid, - nline, - nb_copies, - index ); - - if (wok ) // IVT success => inval DIR slot + bool wok = false; + size_t index = 0; + bool broadcast = r_config_dir_is_cnt.read(); + size_t srcid = r_config_srcid.read(); + size_t trdid = r_config_trdid.read(); + size_t pktid = r_config_pktid.read(); + addr_t nline = m_nline[(addr_t) (r_config_address.read())]; + size_t nb_copies = r_config_dir_count.read(); + + wok = m_ivt.set(false, // it's an inval transaction + broadcast, + false, // no response required + true, // acknowledge required + srcid, + trdid, + pktid, + nline, + nb_copies, + index); + + if (wok) // IVT success => inval DIR slot { - m_cache_directory.inval( way, set ); - r_config_ivt_index = index; + m_cache_directory.inval(way, set); + r_config_ivt_index = index; config_rsp_lines_incr = true; - if (broadcast ) r_config_fsm = CONFIG_BC_SEND; - else r_config_fsm = CONFIG_INVAL_SEND; + if (broadcast) + { + r_config_fsm = CONFIG_BC_SEND; + } + else + { + r_config_fsm = CONFIG_INVAL_SEND; + } #if DEBUG_MEMC_CONFIG -if (m_debug) -std::cout << " " - << " Inval DIR entry and register inval in IVT" - << " / index = " << std::dec << index - << " / broadcast = " << broadcast << std::endl; + if (m_debug) + { + std::cout << " " + << " Inval DIR entry and register inval in IVT" + << " / index = " << std::dec << index + << " / broadcast = " << broadcast << std::endl; + } #endif } @@ -2365,7 +2410,9 @@ #if DEBUG_MEMC_CONFIG -if (m_debug) -std::cout << " " - << " IVT full : release DIR & IVT locks and retry" << std::endl; + if (m_debug) + { + std::cout << " " + << " IVT full : release DIR & IVT locks and retry" << std::endl; + } #endif } @@ -2377,9 +2424,9 @@ case CONFIG_BC_SEND: // Post a broadcast inval request to CC_SEND FSM { - if (not r_config_to_cc_send_multi_req.read() and + if (not r_config_to_cc_send_multi_req.read() and not r_config_to_cc_send_brdcast_req.read()) { // post bc inval request - r_config_to_cc_send_multi_req = false; + r_config_to_cc_send_multi_req = false; r_config_to_cc_send_brdcast_req = true; r_config_to_cc_send_trdid = r_config_ivt_index.read(); @@ -2387,13 +2434,15 @@ // prepare next iteration - r_config_cmd_lines = r_config_cmd_lines.read() - 1; - r_config_address = r_config_address.read() + (m_words << 2); - r_config_fsm = CONFIG_LOOP; + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_address = r_config_address.read() + (m_words << 2); + r_config_fsm = CONFIG_LOOP; #if DEBUG_MEMC_CONFIG -if (m_debug) -std::cout << " " - << " Post a broadcast inval request to CC_SEND FSM" - << " / address = " << r_config_address.read() <" + << " Post a broadcast inval request to CC_SEND FSM" + << " / address = " << r_config_address.read() <" - << " Post multi inval request to CC_SEND FSM" - << " / address = " << std::hex << r_config_address.read() - << " / copy = " << r_config_dir_copy_srcid.read() - << " / inst = " << std::dec << r_config_dir_copy_inst.read() << std::endl; + if (m_debug) + { + std::cout << " " + << " Post multi inval request to CC_SEND FSM" + << " / address = " << std::hex << r_config_address.read() + << " / copy = " << r_config_dir_copy_srcid.read() + << " / inst = " << std::dec << r_config_dir_copy_inst.read() << std::endl; + } #endif } @@ -2443,46 +2494,49 @@ case CONFIG_HEAP_REQ: // Try to get access to Heap { - if (r_alloc_heap_fsm.read() == ALLOC_HEAP_CONFIG ) - { - r_config_fsm = CONFIG_HEAP_SCAN; + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_CONFIG) + { + r_config_fsm = CONFIG_HEAP_SCAN; r_config_heap_next = r_config_dir_ptr.read(); } #if DEBUG_MEMC_CONFIG -if (m_debug) -std::cout << " " - << " Requesting HEAP lock" << std::endl; + if (m_debug) + { + std::cout << " " + << " Requesting HEAP lock" << std::endl; + } #endif break; } ////////////////////// - case CONFIG_HEAP_SCAN: // scan HEAP and send inval to CC_SEND FSM - { - HeapEntry entry = m_heap.read( r_config_heap_next.read()); - bool last_copy = (entry.next == r_config_heap_next.read()); + case CONFIG_HEAP_SCAN: // scan HEAP and send inval to CC_SEND FSM + { + HeapEntry entry = m_heap.read(r_config_heap_next.read()); + bool last_copy = (entry.next == r_config_heap_next.read()); config_to_cc_send_fifo_srcid = entry.owner.srcid; - config_to_cc_send_fifo_inst = entry.owner.inst; - // config_to_cc_send_fifo_last = last_copy; - config_to_cc_send_fifo_put = true; + config_to_cc_send_fifo_inst = entry.owner.inst; + config_to_cc_send_fifo_put = true; if (m_config_to_cc_send_inst_fifo.wok()) // inval request accepted { r_config_heap_next = entry.next; - if (last_copy ) r_config_fsm = CONFIG_HEAP_LAST; + if (last_copy) r_config_fsm = CONFIG_HEAP_LAST; } #if DEBUG_MEMC_CONFIG -if (m_debug) -std::cout << " " - << " Post multi inval request to CC_SEND FSM" - << " / address = " << std::hex << r_config_address.read() - << " / copy = " << entry.owner.srcid - << " / inst = " << std::dec << entry.owner.inst << std::endl; + if (m_debug) + { + std::cout << " " + << " Post multi inval request to CC_SEND FSM" + << " / address = " << std::hex << r_config_address.read() + << " / copy = " << entry.owner.srcid + << " / inst = " << std::dec << entry.owner.inst << std::endl; + } #endif break; } ////////////////////// - case CONFIG_HEAP_LAST: // HEAP housekeeping + case CONFIG_HEAP_LAST: // HEAP housekeeping { size_t free_pointer = m_heap.next_free_ptr(); @@ -2497,20 +2551,22 @@ } else - { + { last_entry.next = free_pointer; } - m_heap.write_free_ptr( r_config_dir_ptr.read()); - m_heap.write( r_config_heap_next.read(), last_entry ); + m_heap.write_free_ptr(r_config_dir_ptr.read()); + m_heap.write(r_config_heap_next.read(), last_entry); // prepare next iteration - r_config_cmd_lines = r_config_cmd_lines.read() - 1; - r_config_address = r_config_address.read() + (m_words<<2); - r_config_fsm = CONFIG_LOOP; + r_config_cmd_lines = r_config_cmd_lines.read() - 1; + r_config_address = r_config_address.read() + (m_words << 2); + r_config_fsm = CONFIG_LOOP; #if DEBUG_MEMC_CONFIG -if (m_debug) -std::cout << " " - << " Heap housekeeping" << std::endl; + if (m_debug) + { + std::cout << " " + << " Heap housekeeping" << std::endl; + } #endif break; @@ -2518,5 +2574,5 @@ } // end switch r_config_fsm - + //////////////////////////////////////////////////////////////////////////////////// @@ -2549,79 +2605,268 @@ /////////////// case READ_IDLE: // waiting a read request - { - if (m_cmd_read_addr_fifo.rok()) - { - -#if DEBUG_MEMC_READ - if (m_debug) - std::cout << " Read request" - << " : address = " << std::hex << m_cmd_read_addr_fifo.read() - << " / srcid = " << m_cmd_read_srcid_fifo.read() - << " / trdid = " << m_cmd_read_trdid_fifo.read() - << " / pktid = " << m_cmd_read_pktid_fifo.read() - << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; -#endif - r_read_fsm = READ_DIR_REQ; - } - break; - } - ////////////////// - case READ_DIR_REQ: // Get the lock to the directory - { - if (r_alloc_dir_fsm.read() == ALLOC_DIR_READ) - { - r_read_fsm = READ_DIR_LOCK; - } + { + if (m_cmd_read_addr_fifo.rok()) + { #if DEBUG_MEMC_READ if (m_debug) - std::cout << " Requesting DIR lock " << std::endl; -#endif - break; - } - - /////////////////// + { + std::cout << " Read request" + << " : address = " << std::hex << m_cmd_read_addr_fifo.read() + << " / srcid = " << m_cmd_read_srcid_fifo.read() + << " / trdid = " << m_cmd_read_trdid_fifo.read() + << " / pktid = " << m_cmd_read_pktid_fifo.read() + << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; + } +#endif + r_read_fsm = READ_DIR_REQ; + } + break; + } + ////////////////// + case READ_DIR_REQ: // Get the lock to the directory + { + if (r_alloc_dir_fsm.read() == ALLOC_DIR_READ) + { + r_read_fsm = READ_DIR_LOCK; + } + +#if DEBUG_MEMC_READ + if (m_debug) + { + std::cout << " Requesting DIR lock " << std::endl; + } +#endif + break; + } + + /////////////////// case READ_DIR_LOCK: // check directory for hit / miss - { - assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_READ) and - "MEMC ERROR in READ_DIR_LOCK state: Bad DIR allocation"); - - size_t way = 0; - DirectoryEntry entry = m_cache_directory.read(m_cmd_read_addr_fifo.read(), way); - - // access the global table ONLY when we have an LL cmd - if ((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) - { - r_read_ll_key = m_llsc_table.ll(m_cmd_read_addr_fifo.read()); - } - r_read_is_cnt = entry.is_cnt; - r_read_dirty = entry.dirty; - r_read_lock = entry.lock; - r_read_tag = entry.tag; - r_read_way = way; - r_read_count = entry.count; - r_read_copy = entry.owner.srcid; - r_read_copy_inst = entry.owner.inst; - r_read_ptr = entry.ptr; // pointer to the heap - - // check if this is a cached read, this means pktid is either - // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding - // TYPE_READ_INS_MISS 0bX011 with TSAR encoding - bool cached_read = (m_cmd_read_pktid_fifo.read() & 0x1); - if (entry.valid) // hit - { - // test if we need to register a new copy in the heap - if (entry.is_cnt or (entry.count == 0) or !cached_read) + { + assert((r_alloc_dir_fsm.read() == ALLOC_DIR_READ) and + "MEMC ERROR in READ_DIR_LOCK state: Bad DIR allocation"); + + size_t way = 0; + DirectoryEntry entry = m_cache_directory.read(m_cmd_read_addr_fifo.read(), way); + + // access the global table ONLY when we have an LL cmd + if ((m_cmd_read_pktid_fifo.read() & 0x7) == TYPE_LL) + { + r_read_ll_key = m_llsc_table.ll(m_cmd_read_addr_fifo.read()); + } + r_read_is_cnt = entry.is_cnt; + r_read_dirty = entry.dirty; + r_read_lock = entry.lock; + r_read_tag = entry.tag; + r_read_way = way; + r_read_count = entry.count; + r_read_copy = entry.owner.srcid; + r_read_copy_inst = entry.owner.inst; + r_read_ptr = entry.ptr; // pointer to the heap + + // check if this is a cached read, this means pktid is either + // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding + // TYPE_READ_INS_MISS 0bX011 with TSAR encoding + bool cached_read = (m_cmd_read_pktid_fifo.read() & 0x1); + if (entry.valid) // hit + { + // test if we need to register a new copy in the heap + if (entry.is_cnt or (entry.count == 0) or !cached_read) + { + r_read_fsm = READ_DIR_HIT; + } + else + { + r_read_fsm = READ_HEAP_REQ; + } + } + else // miss + { + r_read_fsm = READ_TRT_LOCK; + } + +#if DEBUG_MEMC_READ + if (m_debug) + { + std::cout << " Accessing directory: " + << " address = " << std::hex << m_cmd_read_addr_fifo.read() + << " / hit = " << std::dec << entry.valid + << " / count = " < we must update the copies + { + if (!is_cnt) // Not counter mode + { + entry.owner.srcid = m_cmd_read_srcid_fifo.read(); + entry.owner.inst = inst_read; + entry.count = r_read_count.read() + 1; + } + else // Counter mode + { + entry.owner.srcid = 0; + entry.owner.inst = false; + entry.count = r_read_count.read() + 1; + } + } + else // Uncached read + { + entry.owner.srcid = r_read_copy.read(); + entry.owner.inst = r_read_copy_inst.read(); + entry.count = r_read_count.read(); + } + +#if DEBUG_MEMC_READ + if (m_debug) + { + std::cout << " Update directory entry:" + << " addr = " << std::hex << m_cmd_read_addr_fifo.read() + << " / set = " << std::dec << set + << " / way = " << way + << " / owner_id = " << std::hex << entry.owner.srcid + << " / owner_ins = " << std::dec << entry.owner.inst + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt << std::endl; + } +#endif + m_cache_directory.write(set, way, entry); + r_read_fsm = READ_RSP; + break; + } + /////////////////// + case READ_HEAP_REQ: // Get the lock to the HEAP directory + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) + { + r_read_fsm = READ_HEAP_LOCK; + } + +#if DEBUG_MEMC_READ + if (m_debug) + { + std::cout << " " + << " Requesting HEAP lock " << std::endl; + } +#endif + break; + } + + //////////////////// + case READ_HEAP_LOCK: // read data in cache, update the directory + // and prepare the HEAP update + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) + { + // enter counter mode when we reach the limit of copies or the heap is full + bool go_cnt = (r_read_count.read() >= m_max_copies) or m_heap.is_full(); + + // read data in the cache + size_t set = m_y[(addr_t) (m_cmd_read_addr_fifo.read())]; + size_t way = r_read_way.read(); + + m_cache_data.read_line(way, set, r_read_data); + + // update the cache directory + DirectoryEntry entry; + entry.valid = true; + entry.is_cnt = go_cnt; + entry.dirty = r_read_dirty.read(); + entry.tag = r_read_tag.read(); + entry.lock = r_read_lock.read(); + entry.count = r_read_count.read() + 1; + + if (not go_cnt) // Not entering counter mode + { + entry.owner.srcid = r_read_copy.read(); + entry.owner.inst = r_read_copy_inst.read(); + entry.ptr = m_heap.next_free_ptr(); // set pointer on the heap + } + else // Entering Counter mode + { + entry.owner.srcid = 0; + entry.owner.inst = false; + entry.ptr = 0; + } + + m_cache_directory.write(set, way, entry); + + // prepare the heap update (add an entry, or clear the linked list) + if (not go_cnt) // not switching to counter mode + { + // We test if the next free entry in the heap is the last + HeapEntry heap_entry = m_heap.next_free_entry(); + r_read_next_ptr = heap_entry.next; + r_read_last_free = (heap_entry.next == m_heap.next_free_ptr()); + + r_read_fsm = READ_HEAP_WRITE; // add an entry in the HEAP + } + else // switching to counter mode + { + if (r_read_count.read() > 1) // heap must be cleared { - r_read_fsm = READ_DIR_HIT; + HeapEntry next_entry = m_heap.read(r_read_ptr.read()); + r_read_next_ptr = m_heap.next_free_ptr(); + m_heap.write_free_ptr(r_read_ptr.read()); + + if (next_entry.next == r_read_ptr.read()) // last entry + { + r_read_fsm = READ_HEAP_LAST; // erase the entry + } + else // not the last entry + { + r_read_ptr = next_entry.next; + r_read_fsm = READ_HEAP_ERASE; // erase the list + } } - else + else // the heap is not used / nothing to do { - r_read_fsm = READ_HEAP_REQ; + r_read_fsm = READ_RSP; } - } - else // miss - { - r_read_fsm = READ_TRT_LOCK; } @@ -2629,393 +2874,234 @@ if (m_debug) { - std::cout << " Accessing directory: " - << " address = " << std::hex << m_cmd_read_addr_fifo.read() - << " / hit = " << std::dec << entry.valid - << " / count = " < we must update the copies - { - if (!is_cnt) // Not counter mode - { - entry.owner.srcid = m_cmd_read_srcid_fifo.read(); - entry.owner.inst = inst_read; - entry.count = r_read_count.read() + 1; - } - else // Counter mode - { - entry.owner.srcid = 0; - entry.owner.inst = false; - entry.count = r_read_count.read() + 1; - } - } - else // Uncached read - { - entry.owner.srcid = r_read_copy.read(); - entry.owner.inst = r_read_copy_inst.read(); - entry.count = r_read_count.read(); - } + std::cout << " Update directory:" + << " tag = " << std::hex << entry.tag + << " set = " << std::dec << set + << " way = " << way + << " count = " << entry.count + << " is_cnt = " << entry.is_cnt << std::endl; + } +#endif + } + else + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_LOCK" + << "Bad HEAP allocation" << std::endl; + exit(0); + } + break; + } + ///////////////////// + case READ_HEAP_WRITE: // add an entry in the heap + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) + { + HeapEntry heap_entry; + heap_entry.owner.srcid = m_cmd_read_srcid_fifo.read(); + heap_entry.owner.inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); + + if (r_read_count.read() == 1) // creation of a new linked list + { + heap_entry.next = m_heap.next_free_ptr(); + } + else // head insertion in existing list + { + heap_entry.next = r_read_ptr.read(); + } + m_heap.write_free_entry(heap_entry); + m_heap.write_free_ptr(r_read_next_ptr.read()); + if (r_read_last_free.read()) { + m_heap.set_full(); + } + + r_read_fsm = READ_RSP; #if DEBUG_MEMC_READ if (m_debug) - std::cout << " Update directory entry:" - << " addr = " << std::hex << m_cmd_read_addr_fifo.read() - << " / set = " << std::dec << set - << " / way = " << way - << " / owner_id = " << std::hex << entry.owner.srcid - << " / owner_ins = " << std::dec << entry.owner.inst - << " / count = " << entry.count - << " / is_cnt = " << entry.is_cnt << std::endl; -#endif - m_cache_directory.write(set, way, entry); - r_read_fsm = READ_RSP; - break; - } - /////////////////// - case READ_HEAP_REQ: // Get the lock to the HEAP directory - { - if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) - { - r_read_fsm = READ_HEAP_LOCK; - } + { + std::cout << " Add an entry in the heap:" + << " owner_id = " << std::hex << heap_entry.owner.srcid + << " owner_ins = " << std::dec << heap_entry.owner.inst << std::endl; + } +#endif + } + else + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_WRITE" + << "Bad HEAP allocation" << std::endl; + exit(0); + } + break; + } + ///////////////////// + case READ_HEAP_ERASE: + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) + { + HeapEntry next_entry = m_heap.read(r_read_ptr.read()); + if (next_entry.next == r_read_ptr.read()) + { + r_read_fsm = READ_HEAP_LAST; + } + else + { + r_read_ptr = next_entry.next; + r_read_fsm = READ_HEAP_ERASE; + } + } + else + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_ERASE" + << "Bad HEAP allocation" << std::endl; + exit(0); + } + break; + } + + //////////////////// + case READ_HEAP_LAST: + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) + { + HeapEntry last_entry; + last_entry.owner.srcid = 0; + last_entry.owner.inst = false; + + if (m_heap.is_full()) + { + last_entry.next = r_read_ptr.read(); + m_heap.unset_full(); + } + else + { + last_entry.next = r_read_next_ptr.read(); + } + m_heap.write(r_read_ptr.read(),last_entry); + r_read_fsm = READ_RSP; + } + else + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_LAST" + << "Bad HEAP allocation" << std::endl; + exit(0); + } + break; + } + ////////////// + case READ_RSP: // request the TGT_RSP FSM to return data + { + if (!r_read_to_tgt_rsp_req) + { + for (size_t i = 0; i < m_words; i++) + { + r_read_to_tgt_rsp_data[i] = r_read_data[i]; + } + r_read_to_tgt_rsp_word = m_x[(addr_t) m_cmd_read_addr_fifo.read()]; + r_read_to_tgt_rsp_length = m_cmd_read_length_fifo.read(); + r_read_to_tgt_rsp_srcid = m_cmd_read_srcid_fifo.read(); + r_read_to_tgt_rsp_trdid = m_cmd_read_trdid_fifo.read(); + r_read_to_tgt_rsp_pktid = m_cmd_read_pktid_fifo.read(); + r_read_to_tgt_rsp_ll_key = r_read_ll_key.read(); + cmd_read_fifo_get = true; + r_read_to_tgt_rsp_req = true; + r_read_fsm = READ_IDLE; #if DEBUG_MEMC_READ if (m_debug) - std::cout << " " - << " Requesting HEAP lock " << std::endl; -#endif - break; - } - - //////////////////// - case READ_HEAP_LOCK: // read data in cache, update the directory - // and prepare the HEAP update - { - if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) - { - // enter counter mode when we reach the limit of copies or the heap is full - bool go_cnt = (r_read_count.read() >= m_max_copies) or m_heap.is_full(); - - // read data in the cache - size_t set = m_y[(addr_t)(m_cmd_read_addr_fifo.read())]; - size_t way = r_read_way.read(); - - m_cache_data.read_line(way, set, r_read_data); - - // update the cache directory - DirectoryEntry entry; - entry.valid = true; - entry.is_cnt = go_cnt; - entry.dirty = r_read_dirty.read(); - entry.tag = r_read_tag.read(); - entry.lock = r_read_lock.read(); - entry.count = r_read_count.read() + 1; - - if (not go_cnt) // Not entering counter mode - { - entry.owner.srcid = r_read_copy.read(); - entry.owner.inst = r_read_copy_inst.read(); - entry.ptr = m_heap.next_free_ptr(); // set pointer on the heap - } - else // Entering Counter mode - { - entry.owner.srcid = 0; - entry.owner.inst = false; - entry.ptr = 0; - } - - m_cache_directory.write(set, way, entry); - - // prepare the heap update (add an entry, or clear the linked list) - if (not go_cnt) // not switching to counter mode - { - // We test if the next free entry in the heap is the last - HeapEntry heap_entry = m_heap.next_free_entry(); - r_read_next_ptr = heap_entry.next; - r_read_last_free = (heap_entry.next == m_heap.next_free_ptr()); - - r_read_fsm = READ_HEAP_WRITE; // add an entry in the HEAP - } - else // switching to counter mode - { - if (r_read_count.read() >1) // heap must be cleared - { - HeapEntry next_entry = m_heap.read(r_read_ptr.read()); - r_read_next_ptr = m_heap.next_free_ptr(); - m_heap.write_free_ptr(r_read_ptr.read()); - - if (next_entry.next == r_read_ptr.read()) // last entry - { - r_read_fsm = READ_HEAP_LAST; // erase the entry - } - else // not the last entry - { - r_read_ptr = next_entry.next; - r_read_fsm = READ_HEAP_ERASE; // erase the list - } - } - else // the heap is not used / nothing to do - { - r_read_fsm = READ_RSP; - } - } + { + std::cout << " Request TGT_RSP FSM to return data:" + << " rsrcid = " << std::hex << m_cmd_read_srcid_fifo.read() + << " / address = " << std::hex << m_cmd_read_addr_fifo.read() + << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; + } +#endif + } + break; + } + /////////////////// + case READ_TRT_LOCK: // read miss : check the Transaction Table + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_READ) + { + size_t index = 0; + addr_t addr = (addr_t) m_cmd_read_addr_fifo.read(); + bool hit_read = m_trt.hit_read(m_nline[addr], index); + bool hit_write = m_trt.hit_write(m_nline[addr]); + bool wok = not m_trt.full(index); + + if (hit_read or !wok or hit_write) // line already requested or no space + { + if (!wok) m_cpt_trt_full++; + if (hit_read or hit_write) m_cpt_trt_rb++; + r_read_fsm = READ_IDLE; + } + else // missing line is requested to the XRAM + { + m_cpt_read_miss++; + r_read_trt_index = index; + r_read_fsm = READ_TRT_SET; + } #if DEBUG_MEMC_READ - if (m_debug) - std::cout << " Update directory:" - << " tag = " << std::hex << entry.tag - << " set = " << std::dec << set - << " way = " << way - << " count = " << entry.count - << " is_cnt = " << entry.is_cnt << std::endl; -#endif - } - else - { - std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_LOCK" - << "Bad HEAP allocation" << std::endl; - exit(0); - } - break; - } - ///////////////////// - case READ_HEAP_WRITE: // add an entry in the heap - { - if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) - { - HeapEntry heap_entry; - heap_entry.owner.srcid = m_cmd_read_srcid_fifo.read(); - heap_entry.owner.inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); - - if (r_read_count.read() == 1) // creation of a new linked list - { - heap_entry.next = m_heap.next_free_ptr(); - } - else // head insertion in existing list - { - heap_entry.next = r_read_ptr.read(); - } - m_heap.write_free_entry(heap_entry); - m_heap.write_free_ptr(r_read_next_ptr.read()); - if (r_read_last_free.read()) m_heap.set_full(); - - r_read_fsm = READ_RSP; - + if (m_debug) + { + std::cout << " Check TRT:" + << " hit_read = " << hit_read + << " / hit_write = " << hit_write + << " / full = " << !wok << std::endl; + } +#endif + } + break; + } + ////////////////// + case READ_TRT_SET: // register get transaction in TRT + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_READ) + { + m_trt.set(r_read_trt_index.read(), + true, // GET + m_nline[(addr_t) (m_cmd_read_addr_fifo.read())], + m_cmd_read_srcid_fifo.read(), + m_cmd_read_trdid_fifo.read(), + m_cmd_read_pktid_fifo.read(), + true, // proc read + m_cmd_read_length_fifo.read(), + m_x[(addr_t) (m_cmd_read_addr_fifo.read())], + std::vector (m_words, 0), + std::vector (m_words, 0), + r_read_ll_key.read()); #if DEBUG_MEMC_READ - if (m_debug) - std::cout << " Add an entry in the heap:" - << " owner_id = " << std::hex << heap_entry.owner.srcid - << " owner_ins = " << std::dec << heap_entry.owner.inst << std::endl; -#endif - } - else - { - std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_WRITE" - << "Bad HEAP allocation" << std::endl; - exit(0); - } - break; - } - ///////////////////// - case READ_HEAP_ERASE: - { - if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) - { - HeapEntry next_entry = m_heap.read(r_read_ptr.read()); - if (next_entry.next == r_read_ptr.read()) - { - r_read_fsm = READ_HEAP_LAST; - } - else - { - r_read_ptr = next_entry.next; - r_read_fsm = READ_HEAP_ERASE; - } - } - else - { - std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_ERASE" - << "Bad HEAP allocation" << std::endl; - exit(0); - } - break; - } - - //////////////////// - case READ_HEAP_LAST: - { - if (r_alloc_heap_fsm.read() == ALLOC_HEAP_READ) - { - HeapEntry last_entry; - last_entry.owner.srcid = 0; - last_entry.owner.inst = false; - - if (m_heap.is_full()) - { - last_entry.next = r_read_ptr.read(); - m_heap.unset_full(); - } - else - { - last_entry.next = r_read_next_ptr.read(); - } - m_heap.write(r_read_ptr.read(),last_entry); - r_read_fsm = READ_RSP; - } - else - { - std::cout << "VCI_MEM_CACHE ERROR " << name() << " READ_HEAP_LAST" - << "Bad HEAP allocation" << std::endl; - exit(0); - } - break; - } - ////////////// - case READ_RSP: // request the TGT_RSP FSM to return data - { - if (!r_read_to_tgt_rsp_req) - { - for(size_t i=0 ; i Set a GET in TRT:" + << " address = " << std::hex << m_cmd_read_addr_fifo.read() + << " / srcid = " << std::hex << m_cmd_read_srcid_fifo.read() << std::endl; + } +#endif + r_read_fsm = READ_TRT_REQ; + } + break; + } + + ////////////////// + case READ_TRT_REQ: // consume the read request in FIFO and send it to IXR_CMD_FSM + { + if (not r_read_to_ixr_cmd_req) + { + cmd_read_fifo_get = true; + r_read_to_ixr_cmd_req = true; + r_read_to_ixr_cmd_index = r_read_trt_index.read(); + r_read_fsm = READ_IDLE; #if DEBUG_MEMC_READ - if (m_debug) - std::cout << " Request TGT_RSP FSM to return data:" - << " rsrcid = " << std::hex << m_cmd_read_srcid_fifo.read() - << " / address = " << std::hex << m_cmd_read_addr_fifo.read() - << " / nwords = " << std::dec << m_cmd_read_length_fifo.read() << std::endl; -#endif - } - break; - } - /////////////////// - case READ_TRT_LOCK: // read miss : check the Transaction Table - { - if (r_alloc_trt_fsm.read() == ALLOC_TRT_READ) - { - size_t index = 0; - addr_t addr = (addr_t) m_cmd_read_addr_fifo.read(); - bool hit_read = m_trt.hit_read(m_nline[addr], index); - bool hit_write = m_trt.hit_write(m_nline[addr]); - bool wok = not m_trt.full(index); - - if (hit_read or !wok or hit_write) // line already requested or no space - { - if (!wok) m_cpt_trt_full++; - if (hit_read or hit_write) m_cpt_trt_rb++; - r_read_fsm = READ_IDLE; - } - else // missing line is requested to the XRAM - { - m_cpt_read_miss++; - r_read_trt_index = index; - r_read_fsm = READ_TRT_SET; - } - -#if DEBUG_MEMC_READ - if (m_debug) - std::cout << " Check TRT:" - << " hit_read = " << hit_read - << " / hit_write = " << hit_write - << " / full = " << !wok << std::endl; -#endif - } - break; - } - ////////////////// - case READ_TRT_SET: // register get transaction in TRT - { - if (r_alloc_trt_fsm.read() == ALLOC_TRT_READ) - { - m_trt.set( r_read_trt_index.read(), - true, // GET - m_nline[(addr_t)(m_cmd_read_addr_fifo.read())], - m_cmd_read_srcid_fifo.read(), - m_cmd_read_trdid_fifo.read(), - m_cmd_read_pktid_fifo.read(), - true, // proc read - m_cmd_read_length_fifo.read(), - m_x[(addr_t)(m_cmd_read_addr_fifo.read())], - std::vector (m_words,0), - std::vector (m_words,0), - r_read_ll_key.read()); -#if DEBUG_MEMC_READ - if (m_debug) - std::cout << " Set a GET in TRT:" - << " address = " << std::hex << m_cmd_read_addr_fifo.read() - << " / srcid = " << std::hex << m_cmd_read_srcid_fifo.read() << std::endl; -#endif - r_read_fsm = READ_TRT_REQ; - } - break; - } - - ////////////////// - case READ_TRT_REQ: // consume the read request in FIFO and send it to IXR_CMD_FSM - { - if (not r_read_to_ixr_cmd_req) - { - cmd_read_fifo_get = true; - r_read_to_ixr_cmd_req = true; - r_read_to_ixr_cmd_index = r_read_trt_index.read(); - r_read_fsm = READ_IDLE; - -#if DEBUG_MEMC_READ - if (m_debug) - std::cout << " Request GET transaction for address " - << std::hex << m_cmd_read_addr_fifo.read() << std::endl; -#endif - } - break; - } + if (m_debug) + { + std::cout << " Request GET transaction for address " + << std::hex << m_cmd_read_addr_fifo.read() << std::endl; + } +#endif + } + break; + } } // end switch read_fsm @@ -3053,263 +3139,603 @@ ///////////////////////////////////////////////////////////////////////////////////// - //std::cout << std::endl << "write_fsm" << std::endl; - - switch(r_write_fsm.read()) + switch (r_write_fsm.read()) { //////////////// case WRITE_IDLE: // copy first word of a write burst in local buffer - { - if (not m_cmd_write_addr_fifo.rok()) break; - - // consume a word in the FIFO & write it in the local buffer - cmd_write_fifo_get = true; - size_t index = m_x[(addr_t)(m_cmd_write_addr_fifo.read())]; - - r_write_address = (addr_t)(m_cmd_write_addr_fifo.read()); - r_write_word_index = index; - r_write_word_count = 0; - r_write_data[index] = m_cmd_write_data_fifo.read(); - r_write_srcid = m_cmd_write_srcid_fifo.read(); - r_write_trdid = m_cmd_write_trdid_fifo.read(); - r_write_pktid = m_cmd_write_pktid_fifo.read(); - - // if SC command, get the SC key - if ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC) - { - assert( not m_cmd_write_eop_fifo.read() && - "MEMC ERROR in WRITE_IDLE state: " - "invalid packet format for SC command"); - - r_write_sc_key = m_cmd_write_data_fifo.read(); - } - - // initialize the be field for all words - for(size_t word=0 ; word Write request " - << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read() - << " / address = " << std::hex << m_cmd_write_addr_fifo.read() - << " / data = " << m_cmd_write_data_fifo.read() << std::endl; -#endif - break; - } - //////////////// + if (m_debug) + { + std::cout << " Write request " + << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read() + << " / address = " << std::hex << m_cmd_write_addr_fifo.read() + << " / data = " << m_cmd_write_data_fifo.read() << std::endl; + } +#endif + break; + } + //////////////// case WRITE_NEXT: // copy next word of a write burst in local buffer - { - if (not m_cmd_write_addr_fifo.rok()) break; - - // check that the next word is in the same cache line - assert((m_nline[(addr_t)(r_write_address.read())] == + { + if (not m_cmd_write_addr_fifo.rok()) break; + + // check that the next word is in the same cache line + assert((m_nline[(addr_t)(r_write_address.read())] == m_nline[(addr_t)(m_cmd_write_addr_fifo.read())]) && - "MEMC ERROR in WRITE_NEXT state: Illegal write burst"); - - size_t index = m_x[(addr_t)(m_cmd_write_addr_fifo.read())]; - bool is_sc = ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC); - - // check that SC command has constant address - assert((not is_sc or (index == r_write_word_index)) && - "MEMC ERROR in WRITE_NEXT state: " - "the address must be constant on a SC command"); - - // check that SC command has two flits - assert((not is_sc or m_cmd_write_eop_fifo.read()) && - "MEMC ERROR in WRITE_NEXT state: " - "invalid packet format for SC command"); - - // consume a word in the FIFO & write it in the local buffer - cmd_write_fifo_get = true; - - r_write_be[index] = m_cmd_write_be_fifo.read(); - r_write_data[index] = m_cmd_write_data_fifo.read(); - - // the first flit of a SC command is the reservation key and - // therefore it must not be counted as a data to write - if (not is_sc) - { - r_write_word_count = r_write_word_count.read() + 1; - } - - if (m_cmd_write_eop_fifo.read()) r_write_fsm = WRITE_DIR_REQ; + "MEMC ERROR in WRITE_NEXT state: Illegal write burst"); + + size_t index = m_x[(addr_t)(m_cmd_write_addr_fifo.read())]; + bool is_sc = ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC); + + // check that SC command has constant address + assert((not is_sc or (index == r_write_word_index)) && + "MEMC ERROR in WRITE_NEXT state: " + "the address must be constant on a SC command"); + + // check that SC command has two flits + assert((not is_sc or m_cmd_write_eop_fifo.read()) && + "MEMC ERROR in WRITE_NEXT state: " + "invalid packet format for SC command"); + + // consume a word in the FIFO & write it in the local buffer + cmd_write_fifo_get = true; + + r_write_be[index] = m_cmd_write_be_fifo.read(); + r_write_data[index] = m_cmd_write_data_fifo.read(); + + // the first flit of a SC command is the reservation key and + // therefore it must not be counted as a data to write + if (not is_sc) + { + r_write_word_count = r_write_word_count.read() + 1; + } + + if (m_cmd_write_eop_fifo.read()) + { + r_write_fsm = WRITE_DIR_REQ; + } #if DEBUG_MEMC_WRITE - if (m_debug) - std::cout << " Write another word in local buffer" - << std::endl; -#endif - break; - } - /////////////////// + if (m_debug) + { + std::cout << " Write another word in local buffer" + << std::endl; + } +#endif + break; + } + /////////////////// case WRITE_DIR_REQ: // Get the lock to the directory // and access the llsc_global_table - { - if (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE ) break; - + { + if (r_alloc_dir_fsm.read() != ALLOC_DIR_WRITE) break; + + if ((r_write_pktid.read() & 0x7) == TYPE_SC) + { + // test address and key match of the SC command on the + // LL/SC table without removing reservation. The reservation + // will be erased after in this FSM. + bool sc_success = m_llsc_table.check(r_write_address.read(), + r_write_sc_key.read()); + + r_write_sc_fail = not sc_success; + + if (not sc_success) r_write_fsm = WRITE_RSP; + else r_write_fsm = WRITE_DIR_LOCK; + } + else + { + // write burst +#define L2 soclib::common::uint32_log2 + addr_t min = r_write_address.read(); + addr_t max = r_write_address.read() + + (r_write_word_count.read() << L2(vci_param_int::B)); +#undef L2 + + m_llsc_table.sw(min, max); + + r_write_fsm = WRITE_DIR_LOCK; + } + +#if DEBUG_MEMC_WRITE + if (m_debug) + { + std::cout << " Requesting DIR lock " + << std::endl; + } +#endif + break; + } + //////////////////// + case WRITE_DIR_LOCK: // access directory to check hit/miss + { + assert((r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and + "MEMC ERROR in ALLOC_DIR_LOCK state: Bad DIR allocation"); + + size_t way = 0; + DirectoryEntry entry(m_cache_directory.read(r_write_address.read(), way)); + + if (entry.valid) // hit + { + // copy directory entry in local buffer in case of hit + r_write_is_cnt = entry.is_cnt; + r_write_lock = entry.lock; + r_write_tag = entry.tag; + r_write_copy = entry.owner.srcid; + r_write_copy_inst = entry.owner.inst; + r_write_count = entry.count; + r_write_ptr = entry.ptr; + r_write_way = way; + + if (entry.is_cnt and entry.count) r_write_fsm = WRITE_BC_DIR_READ; + else r_write_fsm = WRITE_DIR_HIT; + } + else // miss + { + r_write_fsm = WRITE_MISS_TRT_LOCK; + } + +#if DEBUG_MEMC_WRITE + if (m_debug) + { + std::cout << " Check the directory: " + << " address = " << std::hex << r_write_address.read() + << " / hit = " << std::dec << entry.valid + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt ; if ((r_write_pktid.read() & 0x7) == TYPE_SC) { - // test address and key match of the SC command on the - // LL/SC table without removing reservation. The reservation - // will be erased after in this FSM. - bool sc_success = m_llsc_table.check(r_write_address.read(), - r_write_sc_key.read()); - - r_write_sc_fail = not sc_success; - - if (not sc_success) r_write_fsm = WRITE_RSP; - else r_write_fsm = WRITE_DIR_LOCK; + std::cout << " / SC access" << std::endl; } else { - // write burst -#define L2 soclib::common::uint32_log2 - addr_t min = r_write_address.read(); - addr_t max = r_write_address.read() + - (r_write_word_count.read() << L2(vci_param_int::B)); -#undef L2 - - m_llsc_table.sw(min, max); - - r_write_fsm = WRITE_DIR_LOCK; - } + std::cout << " / SW access" << std::endl; + } + } +#endif + break; + } + /////////////////// + case WRITE_DIR_HIT: // update the cache directory with Dirty bit + // and update data cache + { + assert((r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and + "MEMC ERROR in ALLOC_DIR_HIT state: Bad DIR allocation"); + + DirectoryEntry entry; + entry.valid = true; + entry.dirty = true; + entry.tag = r_write_tag.read(); + entry.is_cnt = r_write_is_cnt.read(); + entry.lock = r_write_lock.read(); + entry.owner.srcid = r_write_copy.read(); + entry.owner.inst = r_write_copy_inst.read(); + entry.count = r_write_count.read(); + entry.ptr = r_write_ptr.read(); + + size_t set = m_y[(addr_t) (r_write_address.read())]; + size_t way = r_write_way.read(); + + // update directory + m_cache_directory.write(set, way, entry); + + // owner is true when the the first registered copy is the writer itself + bool owner = ((r_write_copy.read() == r_write_srcid.read()) + and not r_write_copy_inst.read()); + + // no_update is true when there is no need for coherence transaction + bool no_update = ((r_write_count.read() == 0) or + (owner and (r_write_count.read() == 1) and + ((r_write_pktid.read() & 0x7) != TYPE_SC))); + + // write data in the cache if no coherence transaction + if (no_update) + { + // SC command but zero copies + if ((r_write_pktid.read() & 0x7) == TYPE_SC) + { + m_llsc_table.sc(r_write_address.read(), + r_write_sc_key.read()); + } + + for (size_t word = 0; word < m_words; word++) + { + m_cache_data.write(way, + set, + word, + r_write_data[word].read(), + r_write_be[word].read()); + } + } + + if (owner and not no_update and ((r_write_pktid.read() & 0x7) != TYPE_SC)) + { + r_write_count = r_write_count.read() - 1; + } + + if (no_update) // Write transaction completed + { + r_write_fsm = WRITE_RSP; + } + else // coherence update required + { + if (!r_write_to_cc_send_multi_req.read() and + !r_write_to_cc_send_brdcast_req.read()) + { + r_write_fsm = WRITE_UPT_LOCK; + } + else + { + r_write_fsm = WRITE_WAIT; + } + } #if DEBUG_MEMC_WRITE - if (m_debug) - std::cout << " Requesting DIR lock " - << std::endl; -#endif - break; - } - //////////////////// - case WRITE_DIR_LOCK: // access directory to check hit/miss - { - assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and - "MEMC ERROR in ALLOC_DIR_LOCK state: Bad DIR allocation"); - - size_t way = 0; - DirectoryEntry entry(m_cache_directory.read(r_write_address.read(), way)); - - if (entry.valid) // hit - { - // copy directory entry in local buffer in case of hit - r_write_is_cnt = entry.is_cnt; - r_write_lock = entry.lock; - r_write_tag = entry.tag; - r_write_copy = entry.owner.srcid; - r_write_copy_inst = entry.owner.inst; - r_write_count = entry.count; - r_write_ptr = entry.ptr; - r_write_way = way; - - if (entry.is_cnt and entry.count) r_write_fsm = WRITE_BC_DIR_READ; - else r_write_fsm = WRITE_DIR_HIT; - } - else // miss - { - r_write_fsm = WRITE_MISS_TRT_LOCK; - } - -#if DEBUG_MEMC_WRITE - if (m_debug) - { - std::cout << " Check the directory: " - << " address = " << std::hex << r_write_address.read() - << " / hit = " << std::dec << entry.valid - << " / count = " << entry.count - << " / is_cnt = " << entry.is_cnt ; - if ((r_write_pktid.read() & 0x7) == TYPE_SC) - std::cout << " / SC access" << std::endl; - else - std::cout << " / SW access" << std::endl; - } -#endif - break; - } - /////////////////// - case WRITE_DIR_HIT: // update the cache directory with Dirty bit - // and update data cache - { - assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and - "MEMC ERROR in ALLOC_DIR_HIT state: Bad DIR allocation"); - - DirectoryEntry entry; - entry.valid = true; - entry.dirty = true; - entry.tag = r_write_tag.read(); - entry.is_cnt = r_write_is_cnt.read(); - entry.lock = r_write_lock.read(); - entry.owner.srcid = r_write_copy.read(); - entry.owner.inst = r_write_copy_inst.read(); - entry.count = r_write_count.read(); - entry.ptr = r_write_ptr.read(); - - size_t set = m_y[(addr_t)(r_write_address.read())]; - size_t way = r_write_way.read(); - - // update directory - m_cache_directory.write(set, way, entry); - - // owner is true when the the first registered copy is the writer itself - bool owner = ( (r_write_copy.read() == r_write_srcid.read()) - and not r_write_copy_inst.read()); - - // no_update is true when there is no need for coherence transaction - bool no_update = ( (r_write_count.read() == 0) or - (owner and (r_write_count.read() == 1) and - ((r_write_pktid.read() & 0x7) != TYPE_SC))); - - // write data in the cache if no coherence transaction + if (m_debug) + { if (no_update) { - // SC command but zero copies + std::cout << " Write into cache / No coherence transaction" << std::endl; + } + else + { + std::cout << " Coherence update required:" + << " is_cnt = " << r_write_is_cnt.read() + << " nb_copies = " << std::dec << r_write_count.read() << std::endl; + if (owner) + { + std::cout << " ... but the first copy is the writer" << std::endl; + } + } + } +#endif + break; + } + //////////////////// + case WRITE_UPT_LOCK: // Try to register the update request in UPT + { + if (r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE) + { + bool wok = false; + size_t index = 0; + size_t srcid = r_write_srcid.read(); + size_t trdid = r_write_trdid.read(); + size_t pktid = r_write_pktid.read(); + addr_t nline = m_nline[(addr_t) (r_write_address.read())]; + size_t nb_copies = r_write_count.read(); + size_t set = m_y[(addr_t) (r_write_address.read())]; + size_t way = r_write_way.read(); + + wok = m_upt.set(true, // it's an update transaction + false, // it's not a broadcast + true, // response required + false, // no acknowledge required + srcid, + trdid, + pktid, + nline, + nb_copies, + index); + + if (wok) // write data in cache + { if ((r_write_pktid.read() & 0x7) == TYPE_SC) { m_llsc_table.sc(r_write_address.read(), - r_write_sc_key.read()); + r_write_sc_key.read()); } - for(size_t word=0 ; word Register the multicast update in UPT / " + << " nb_copies = " << r_write_count.read() << std::endl; + } +#endif + r_write_upt_index = index; + // releases the lock protecting UPT and the DIR if no entry... + if (wok) r_write_fsm = WRITE_UPT_HEAP_LOCK; + else r_write_fsm = WRITE_WAIT; + } + break; + } + + ///////////////////////// + case WRITE_UPT_HEAP_LOCK: // get access to heap + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE) + { + +#if DEBUG_MEMC_WRITE + if (m_debug) + { + std::cout << " Get acces to the HEAP" << std::endl; + } +#endif + r_write_fsm = WRITE_UPT_REQ; + } + break; + } + + ////////////////// + case WRITE_UPT_REQ: // prepare the coherence transaction for the CC_SEND FSM + // and write the first copy in the FIFO + // send the request if only one copy + { + assert(not r_write_to_cc_send_multi_req.read() and + not r_write_to_cc_send_brdcast_req.read() and + "Error in VCI_MEM_CACHE : pending multicast or broadcast\n" + "transaction in WRITE_UPT_REQ state"); + + r_write_to_cc_send_brdcast_req = false; + r_write_to_cc_send_trdid = r_write_upt_index.read(); + r_write_to_cc_send_nline = m_nline[(addr_t)(r_write_address.read())]; + r_write_to_cc_send_index = r_write_word_index.read(); + r_write_to_cc_send_count = r_write_word_count.read(); + + for (size_t i = 0; i < m_words; i++) + { + r_write_to_cc_send_be[i] = r_write_be[i].read(); + } + + size_t min = r_write_word_index.read(); + size_t max = r_write_word_index.read() + r_write_word_count.read(); + for (size_t i = min; i <= max; i++) + { + r_write_to_cc_send_data[i] = r_write_data[i]; + } + + if ((r_write_copy.read() != r_write_srcid.read()) or + ((r_write_pktid.read() & 0x7) == TYPE_SC) or + r_write_copy_inst.read()) + { + // put the first srcid in the fifo + write_to_cc_send_fifo_put = true; + write_to_cc_send_fifo_inst = r_write_copy_inst.read(); + write_to_cc_send_fifo_srcid = r_write_copy.read(); + if (r_write_count.read() == 1) + { + r_write_fsm = WRITE_IDLE; + r_write_to_cc_send_multi_req = true; + } + else + { + r_write_fsm = WRITE_UPT_NEXT; + r_write_to_dec = false; + + } + } + else + { + r_write_fsm = WRITE_UPT_NEXT; + r_write_to_dec = false; + } + +#if DEBUG_MEMC_WRITE + if (m_debug) + { + std::cout + << " Post first request to CC_SEND FSM" + << " / srcid = " << std::dec << r_write_copy.read() + << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; + + if (r_write_count.read() == 1) + { + std::cout << " ... and this is the last" << std::endl; + } + } +#endif + break; + } + + /////////////////// + case WRITE_UPT_NEXT: + { + // continue the multi-update request to CC_SEND fsm + // when there is copies in the heap. + // if one copy in the heap is the writer itself + // the corresponding SRCID should not be written in the fifo, + // but the UPT counter must be decremented. + // As this decrement is done in the WRITE_UPT_DEC state, + // after the last copy has been found, the decrement request + // must be registered in the r_write_to_dec flip-flop. + + HeapEntry entry = m_heap.read(r_write_ptr.read()); + + bool dec_upt_counter; + + // put the next srcid in the fifo + if ((entry.owner.srcid != r_write_srcid.read()) or + ((r_write_pktid.read() & 0x7) == TYPE_SC) or + entry.owner.inst) + { + dec_upt_counter = false; + write_to_cc_send_fifo_put = true; + write_to_cc_send_fifo_inst = entry.owner.inst; + write_to_cc_send_fifo_srcid = entry.owner.srcid; + +#if DEBUG_MEMC_WRITE + if (m_debug) + { + std::cout << " Post another request to CC_SEND FSM" + << " / heap_index = " << std::dec << r_write_ptr.read() + << " / srcid = " << std::dec << r_write_copy.read() + << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; + if (entry.next == r_write_ptr.read()) { - r_write_fsm = WRITE_UPT_LOCK; + std::cout << " ... and this is the last" << std::endl; + } + } +#endif + } + else // the UPT counter must be decremented + { + dec_upt_counter = true; +#if DEBUG_MEMC_WRITE + if (m_debug) + { + std::cout << " Skip one entry in heap matching the writer" + << " / heap_index = " << std::dec << r_write_ptr.read() + << " / srcid = " << std::dec << r_write_copy.read() + << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; + if (entry.next == r_write_ptr.read()) + { + std::cout << " ... and this is the last" << std::endl; + } + } +#endif + } + + // register the possible UPT decrement request + r_write_to_dec = dec_upt_counter or r_write_to_dec.read(); + + if (not m_write_to_cc_send_inst_fifo.wok()) + { + std::cout << "*** VCI_MEM_CACHE ERROR " << name() << " WRITE_UPT_NEXT state" << std::endl + << "The write_to_cc_send_fifo should not be full" << std::endl + << "as the depth should be larger than the max number of copies" << std::endl; + exit(0); + } + + r_write_ptr = entry.next; + + if (entry.next == r_write_ptr.read()) // last copy + { + r_write_to_cc_send_multi_req = true; + if (r_write_to_dec.read() or dec_upt_counter) r_write_fsm = WRITE_UPT_DEC; + else r_write_fsm = WRITE_IDLE; + } + break; + } + + ////////////////// + case WRITE_UPT_DEC: + { + // If the initial writer has a copy, it should not + // receive an update request, but the counter in the + // update table must be decremented by the MULTI_ACK FSM. + + if (!r_write_to_multi_ack_req.read()) + { + r_write_to_multi_ack_req = true; + r_write_to_multi_ack_upt_index = r_write_upt_index.read(); + r_write_fsm = WRITE_IDLE; + } + break; + } + + /////////////// + case WRITE_RSP: // Post a request to TGT_RSP FSM to acknowledge the write + // In order to increase the Write requests throughput, + // we don't wait to return in the IDLE state to consume + // a new request in the write FIFO + { + if (not r_write_to_tgt_rsp_req.read()) + { + // post the request to TGT_RSP_FSM + r_write_to_tgt_rsp_req = true; + r_write_to_tgt_rsp_srcid = r_write_srcid.read(); + r_write_to_tgt_rsp_trdid = r_write_trdid.read(); + r_write_to_tgt_rsp_pktid = r_write_pktid.read(); + r_write_to_tgt_rsp_sc_fail = r_write_sc_fail.read(); + + // try to get a new write request from the FIFO + if (not m_cmd_write_addr_fifo.rok()) + { + r_write_fsm = WRITE_IDLE; + } + else + { + // consume a word in the FIFO & write it in the local buffer + cmd_write_fifo_get = true; + size_t index = m_x[(addr_t) (m_cmd_write_addr_fifo.read())]; + + r_write_address = (addr_t) (m_cmd_write_addr_fifo.read()); + r_write_word_index = index; + r_write_word_count = 0; + r_write_data[index] = m_cmd_write_data_fifo.read(); + r_write_srcid = m_cmd_write_srcid_fifo.read(); + r_write_trdid = m_cmd_write_trdid_fifo.read(); + r_write_pktid = m_cmd_write_pktid_fifo.read(); + + // if SC command, get the SC key + if ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC) + { + assert(not m_cmd_write_eop_fifo.read() && + "MEMC ERROR in WRITE_RSP state: " + "invalid packet format for SC command"); + + r_write_sc_key = m_cmd_write_data_fifo.read(); + } + + // initialize the be field for all words + for (size_t word = 0; word < m_words; word++) + { + if (word == index) r_write_be[word] = m_cmd_write_be_fifo.read(); + else r_write_be[word] = 0x0; + } + + if (m_cmd_write_eop_fifo.read()) + { + r_write_fsm = WRITE_DIR_REQ; } else { - r_write_fsm = WRITE_WAIT; + r_write_fsm = WRITE_NEXT; } } @@ -3318,708 +3744,418 @@ if (m_debug) { - if (no_update) + std::cout << " Post a request to TGT_RSP FSM" + << " : rsrcid = " << std::hex << r_write_srcid.read() << std::endl; + if (m_cmd_write_addr_fifo.rok()) { - std::cout << " Write into cache / No coherence transaction" << std::endl; + std::cout << " New Write request: " + << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read() + << " / address = " << m_cmd_write_addr_fifo.read() + << " / data = " << m_cmd_write_data_fifo.read() << std::endl; } - else - { - std::cout << " Coherence update required:" - << " is_cnt = " << r_write_is_cnt.read() - << " nb_copies = " << std::dec << r_write_count.read() << std::endl; - if (owner) std::cout << " ... but the first copy is the writer" << std::endl; - } - } -#endif - break; - } - //////////////////// - case WRITE_UPT_LOCK: // Try to register the update request in UPT - { - if (r_alloc_upt_fsm.read() == ALLOC_UPT_WRITE) - { - bool wok = false; - size_t index = 0; - size_t srcid = r_write_srcid.read(); - size_t trdid = r_write_trdid.read(); - size_t pktid = r_write_pktid.read(); - addr_t nline = m_nline[(addr_t)(r_write_address.read())]; - size_t nb_copies = r_write_count.read(); - size_t set = m_y[(addr_t)(r_write_address.read())]; - size_t way = r_write_way.read(); - - wok = m_upt.set( true, // it's an update transaction - false, // it's not a broadcast - true, // response required - false, // no acknowledge required - srcid, - trdid, - pktid, - nline, - nb_copies, - index); - - if (wok ) // write data in cache - { - - if ((r_write_pktid.read() & 0x7) == TYPE_SC) - { - m_llsc_table.sc(r_write_address.read(), - r_write_sc_key.read()); - } - - for(size_t word=0 ; word Register the multicast update in UPT / " - << " nb_copies = " << r_write_count.read() << std::endl; - } -#endif - r_write_upt_index = index; - // releases the lock protecting UPT and the DIR if no entry... - if (wok) r_write_fsm = WRITE_UPT_HEAP_LOCK; - else r_write_fsm = WRITE_WAIT; - } - break; - } - - ///////////////////////// - case WRITE_UPT_HEAP_LOCK: // get access to heap - { - if (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE) - { - -#if DEBUG_MEMC_WRITE - if (m_debug) - std::cout << " Get acces to the HEAP" << std::endl; -#endif - r_write_fsm = WRITE_UPT_REQ; - } - break; - } - - ////////////////// - case WRITE_UPT_REQ: // prepare the coherence transaction for the CC_SEND FSM - // and write the first copy in the FIFO - // send the request if only one copy - { - assert(not r_write_to_cc_send_multi_req.read() and - not r_write_to_cc_send_brdcast_req.read() and - "Error in VCI_MEM_CACHE : pending multicast or broadcast\n" - "transaction in WRITE_UPT_REQ state" - ); - - r_write_to_cc_send_brdcast_req = false; - r_write_to_cc_send_trdid = r_write_upt_index.read(); - r_write_to_cc_send_nline = m_nline[(addr_t)(r_write_address.read())]; - r_write_to_cc_send_index = r_write_word_index.read(); - r_write_to_cc_send_count = r_write_word_count.read(); - - for(size_t i=0; i Post first request to CC_SEND FSM" - << " / srcid = " << std::dec << r_write_copy.read() - << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; - - if (r_write_count.read() == 1) - std::cout << " ... and this is the last" << std::endl; - } -#endif - break; - } - - /////////////////// - case WRITE_UPT_NEXT: - { - // continue the multi-update request to CC_SEND fsm - // when there is copies in the heap. - // if one copy in the heap is the writer itself - // the corresponding SRCID should not be written in the fifo, - // but the UPT counter must be decremented. - // As this decrement is done in the WRITE_UPT_DEC state, - // after the last copy has been found, the decrement request - // must be registered in the r_write_to_dec flip-flop. - - HeapEntry entry = m_heap.read(r_write_ptr.read()); - - bool dec_upt_counter; - - // put the next srcid in the fifo - if ((entry.owner.srcid != r_write_srcid.read()) or - ((r_write_pktid.read() & 0x7) == TYPE_SC) or - entry.owner.inst) - { - dec_upt_counter = false; - write_to_cc_send_fifo_put = true; - write_to_cc_send_fifo_inst = entry.owner.inst; - write_to_cc_send_fifo_srcid = entry.owner.srcid; + std::cout << " Check the TRT" << std::endl; + } +#endif + size_t hit_index = 0; + size_t wok_index = 0; + addr_t addr = (addr_t) r_write_address.read(); + bool hit_read = m_trt.hit_read(m_nline[addr], hit_index); + bool hit_write = m_trt.hit_write(m_nline[addr]); + bool wok = not m_trt.full(wok_index); + + // wait an empty entry in TRT + if (not hit_read and (not wok or hit_write)) + { + r_write_fsm = WRITE_WAIT; + m_cpt_trt_full++; + + break; + } + + if ((r_write_pktid.read() & 0x7) == TYPE_SC) + { + m_llsc_table.sc(r_write_address.read(), + r_write_sc_key.read()); + } + + // register the modified data in TRT + if (hit_read) + { + r_write_trt_index = hit_index; + r_write_fsm = WRITE_MISS_TRT_DATA; + m_cpt_write_miss++; + break; + } + + // set a new entry in TRT + if (wok and not hit_write) + { + r_write_trt_index = wok_index; + r_write_fsm = WRITE_MISS_TRT_SET; + m_cpt_write_miss++; + break; + } + + assert(false && "VCI_MEM_CACHE ERROR: this part must not be reached"); + } + break; + } + + //////////////// + case WRITE_WAIT: // release the locks protecting the shared ressources + { #if DEBUG_MEMC_WRITE - if (m_debug) - { - std::cout << " Post another request to CC_SEND FSM" - << " / heap_index = " << std::dec << r_write_ptr.read() - << " / srcid = " << std::dec << r_write_copy.read() - << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; - if (entry.next == r_write_ptr.read()) - std::cout << " ... and this is the last" << std::endl; - } -#endif - } - else // the UPT counter must be decremented - { - dec_upt_counter = true; - -#if DEBUG_MEMC_WRITE - if (m_debug) - { - std::cout << " Skip one entry in heap matching the writer" - << " / heap_index = " << std::dec << r_write_ptr.read() - << " / srcid = " << std::dec << r_write_copy.read() - << " / inst = " << std::dec << r_write_copy_inst.read() << std::endl; - if (entry.next == r_write_ptr.read()) - std::cout << " ... and this is the last" << std::endl; - } -#endif - } - - // register the possible UPT decrement request - r_write_to_dec = dec_upt_counter or r_write_to_dec.read(); - - if (not m_write_to_cc_send_inst_fifo.wok()) - { - std::cout << "VCI_MEM_CACHE ERROR " << name() << " WRITE_UPT_NEXT state" << std::endl - << "The write_to_cc_send_fifo should not be full" << std::endl - << "as the depth should be larger than the max number of copies" << std::endl; - exit(0); - } - - r_write_ptr = entry.next; - - if (entry.next == r_write_ptr.read()) // last copy - { - r_write_to_cc_send_multi_req = true; - if (r_write_to_dec.read() or dec_upt_counter) r_write_fsm = WRITE_UPT_DEC; - else r_write_fsm = WRITE_IDLE; - } - break; - } - - ////////////////// - case WRITE_UPT_DEC: - { - // If the initial writer has a copy, it should not - // receive an update request, but the counter in the - // update table must be decremented by the MULTI_ACK FSM. - - if (!r_write_to_multi_ack_req.read()) - { - r_write_to_multi_ack_req = true; - r_write_to_multi_ack_upt_index = r_write_upt_index.read(); - r_write_fsm = WRITE_IDLE; - } - break; - } - - /////////////// - case WRITE_RSP: // Post a request to TGT_RSP FSM to acknowledge the write - // In order to increase the Write requests throughput, - // we don't wait to return in the IDLE state to consume - // a new request in the write FIFO - { - if (not r_write_to_tgt_rsp_req.read()) - { - // post the request to TGT_RSP_FSM - r_write_to_tgt_rsp_req = true; - r_write_to_tgt_rsp_srcid = r_write_srcid.read(); - r_write_to_tgt_rsp_trdid = r_write_trdid.read(); - r_write_to_tgt_rsp_pktid = r_write_pktid.read(); - r_write_to_tgt_rsp_sc_fail = r_write_sc_fail.read(); - - // try to get a new write request from the FIFO - if (not m_cmd_write_addr_fifo.rok()) - { - r_write_fsm = WRITE_IDLE; - } - else - { - // consume a word in the FIFO & write it in the local buffer - cmd_write_fifo_get = true; - size_t index = m_x[(addr_t) (m_cmd_write_addr_fifo.read())]; - - r_write_address = (addr_t) (m_cmd_write_addr_fifo.read()); - r_write_word_index = index; - r_write_word_count = 0; - r_write_data[index] = m_cmd_write_data_fifo.read(); - r_write_srcid = m_cmd_write_srcid_fifo.read(); - r_write_trdid = m_cmd_write_trdid_fifo.read(); - r_write_pktid = m_cmd_write_pktid_fifo.read(); - - // if SC command, get the SC key - if ((m_cmd_write_pktid_fifo.read() & 0x7) == TYPE_SC) - { - assert( not m_cmd_write_eop_fifo.read() && - "MEMC ERROR in WRITE_RSP state: " - "invalid packet format for SC command"); - - r_write_sc_key = m_cmd_write_data_fifo.read(); - } - - // initialize the be field for all words - for(size_t word=0 ; word Post a request to TGT_RSP FSM" - << " : rsrcid = " << std::hex << r_write_srcid.read() << std::endl; - if (m_cmd_write_addr_fifo.rok()) - { - std::cout << " New Write request: " - << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read() - << " / address = " << m_cmd_write_addr_fifo.read() - << " / data = " << m_cmd_write_data_fifo.read() << std::endl; - } - } -#endif - } - break; - } - - ///////////////////////// - case WRITE_MISS_TRT_LOCK: // Miss : check Transaction Table - { - if (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) - { - -#if DEBUG_MEMC_WRITE - if (m_debug) - std::cout << " Check the TRT" << std::endl; -#endif - size_t hit_index = 0; - size_t wok_index = 0; - addr_t addr = (addr_t) r_write_address.read(); - bool hit_read = m_trt.hit_read(m_nline[addr], hit_index); - bool hit_write = m_trt.hit_write(m_nline[addr]); - bool wok = not m_trt.full(wok_index); - - // wait an empty entry in TRT - if(not hit_read and (not wok or hit_write)) - { - r_write_fsm = WRITE_WAIT; - m_cpt_trt_full++; - - break; - } - - if ((r_write_pktid.read() & 0x7) == TYPE_SC) - { - m_llsc_table.sc(r_write_address.read(), - r_write_sc_key.read()); - } - - // register the modified data in TRT - if (hit_read) - { - r_write_trt_index = hit_index; - r_write_fsm = WRITE_MISS_TRT_DATA; - m_cpt_write_miss++; - break; - } - - // set a new entry in TRT - if (wok and not hit_write) - { - r_write_trt_index = wok_index; - r_write_fsm = WRITE_MISS_TRT_SET; - m_cpt_write_miss++; - break; - } - - assert(false && "VCI_MEM_CACHE ERROR: this part must not be reached"); - } - break; - } - - //////////////// - case WRITE_WAIT: // release the locks protecting the shared ressources - { + if (m_debug) + { + std::cout << " Releases the locks before retry" << std::endl; + } +#endif + r_write_fsm = WRITE_DIR_REQ; + break; + } + + //////////////////////// + case WRITE_MISS_TRT_SET: // register a new transaction in TRT (Write Buffer) + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) + { + std::vector be_vector; + std::vector data_vector; + be_vector.clear(); + data_vector.clear(); + for (size_t i = 0; i < m_words; i++) + { + be_vector.push_back(r_write_be[i]); + data_vector.push_back(r_write_data[i]); + } + m_trt.set(r_write_trt_index.read(), + true, // read request to XRAM + m_nline[(addr_t)(r_write_address.read())], + r_write_srcid.read(), + r_write_trdid.read(), + r_write_pktid.read(), + false, // not a processor read + 0, // not a single word + 0, // word index + be_vector, + data_vector); + r_write_fsm = WRITE_MISS_XRAM_REQ; #if DEBUG_MEMC_WRITE if (m_debug) - std::cout << " Releases the locks before retry" << std::endl; -#endif - r_write_fsm = WRITE_DIR_REQ; - break; - } - - //////////////////////// - case WRITE_MISS_TRT_SET: // register a new transaction in TRT (Write Buffer) - { - if (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) - { - std::vector be_vector; - std::vector data_vector; - be_vector.clear(); - data_vector.clear(); - for(size_t i=0; i Set a new entry in TRT" << std::endl; + } +#endif + } + break; + } + + ///////////////////////// + case WRITE_MISS_TRT_DATA: // update an entry in TRT (used as a Write Buffer) + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) + { + std::vector be_vector; + std::vector data_vector; + be_vector.clear(); + data_vector.clear(); + for (size_t i = 0; i < m_words; i++) + { + be_vector.push_back(r_write_be[i]); + data_vector.push_back(r_write_data[i]); + } + m_trt.write_data_mask(r_write_trt_index.read(), + be_vector, + data_vector); + r_write_fsm = WRITE_RSP; #if DEBUG_MEMC_WRITE - if (m_debug) - std::cout << " Set a new entry in TRT" << std::endl; -#endif - } - break; - } - - ///////////////////////// - case WRITE_MISS_TRT_DATA: // update an entry in TRT (used as a Write Buffer) - { - if (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) - { - std::vector be_vector; - std::vector data_vector; - be_vector.clear(); - data_vector.clear(); - for(size_t i=0; i Modify an existing entry in TRT" << std::endl; + } +#endif + } + break; + } + ///////////////////////// + case WRITE_MISS_XRAM_REQ: // send a GET request to IXR_CMD FSM + { + if (not r_write_to_ixr_cmd_req.read()) + { + r_write_to_ixr_cmd_req = true; + r_write_to_ixr_cmd_index = r_write_trt_index.read(); + r_write_fsm = WRITE_RSP; #if DEBUG_MEMC_WRITE - if (m_debug) - std::cout << " Modify an existing entry in TRT" << std::endl; -#endif - } - break; - } - ///////////////////////// - case WRITE_MISS_XRAM_REQ: // send a GET request to IXR_CMD FSM - { - if (not r_write_to_ixr_cmd_req.read()) - { - r_write_to_ixr_cmd_req = true; - r_write_to_ixr_cmd_index = r_write_trt_index.read(); - r_write_fsm = WRITE_RSP; - -#if DEBUG_MEMC_WRITE - if (m_debug) - std::cout << " Post a GET request to the" - << " IXR_CMD FSM" << std::endl; -#endif - } - break; - } - /////////////////////// + if (m_debug) + { + std::cout << " Post a GET request to the" + << " IXR_CMD FSM" << std::endl; + } +#endif + } + break; + } + /////////////////////// case WRITE_BC_DIR_READ: // enter this state if a broadcast-inval is required // the cache line must be erased in mem-cache, and written // into XRAM. - { - assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and - "MEMC ERROR in WRITE_BC_DIR_READ state: Bad DIR allocation"); - - // write enable signal for data buffer. - r_write_bc_data_we = true; - - r_write_fsm = WRITE_BC_TRT_LOCK; - + { + assert((r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and + "MEMC ERROR in WRITE_BC_DIR_READ state: Bad DIR allocation"); + + // write enable signal for data buffer. + r_write_bc_data_we = true; + + r_write_fsm = WRITE_BC_TRT_LOCK; + +#if DEBUG_MEMC_WRITE + if (m_debug) + { + std::cout << " " + << " Read the cache to complete local buffer" << std::endl; + } +#endif + break; + } + /////////////////////// + case WRITE_BC_TRT_LOCK: // get TRT lock to check TRT not full + { + assert((r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and + "MEMC ERROR in WRITE_BC_TRT_LOCK state: Bad DIR allocation"); + + // We read the cache and complete the buffer. As the DATA cache uses a + // synchronous RAM, the read DATA request has been performed in the + // WRITE_BC_DIR_READ state but the data is available in this state. + if (r_write_bc_data_we.read()) + { + size_t set = m_y[(addr_t) (r_write_address.read())]; + size_t way = r_write_way.read(); + for (size_t word = 0; word < m_words ; word++) + { + data_t mask = 0; + if (r_write_be[word].read() & 0x1) mask = mask | 0x000000FF; + if (r_write_be[word].read() & 0x2) mask = mask | 0x0000FF00; + if (r_write_be[word].read() & 0x4) mask = mask | 0x00FF0000; + if (r_write_be[word].read() & 0x8) mask = mask | 0xFF000000; + + // complete only if mask is not null (for energy consumption) + r_write_data[word] = + (r_write_data[word].read() & mask) | + (m_cache_data.read(way, set, word) & ~mask); + } #if DEBUG_MEMC_WRITE if (m_debug) - std::cout << " " - << " Read the cache to complete local buffer" << std::endl; -#endif + { + std::cout << " Complete data buffer" << std::endl; + } +#endif + } + + if (r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE) + { + // if we loop in this state, the data does not need to be + // rewritten (for energy consuption) + r_write_bc_data_we = false; break; } - /////////////////////// - case WRITE_BC_TRT_LOCK: // get TRT lock to check TRT not full - { - assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and - "MEMC ERROR in WRITE_BC_TRT_LOCK state: Bad DIR allocation"); - - // We read the cache and complete the buffer. As the DATA cache uses a - // synchronous RAM, the read DATA request has been performed in the - // WRITE_BC_DIR_READ state but the data is available in this state. - if (r_write_bc_data_we.read()) - { - size_t set = m_y[(addr_t)(r_write_address.read())]; - size_t way = r_write_way.read(); - for(size_t word=0 ; word Complete data buffer" << std::endl; -#endif - } - - if (r_alloc_trt_fsm.read() != ALLOC_TRT_WRITE) - { - // if we loop in this state, the data does not need to be - // rewritten (for energy consuption) - r_write_bc_data_we = false; - break; - } - - size_t wok_index = 0; - bool wok = not m_trt.full(wok_index); - if (wok ) - { - r_write_trt_index = wok_index; - r_write_fsm = WRITE_BC_IVT_LOCK; - } - else // wait an empty slot in TRT - { - r_write_fsm = WRITE_WAIT; - } + if (m_debug) + { + std::cout << " Check TRT : wok = " << wok + << " / index = " << wok_index << std::endl; + } +#endif + break; + } + ////////////////////// + case WRITE_BC_IVT_LOCK: // get IVT lock and register BC transaction in IVT + { + assert((r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and + "MEMC ERROR in WRITE_BC_IVT_LOCK state: Bad DIR allocation"); + + assert((r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) and + "MEMC ERROR in WRITE_BC_IVT_LOCK state: Bad TRT allocation"); + + if (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) + { + bool wok = false; + size_t index = 0; + size_t srcid = r_write_srcid.read(); + size_t trdid = r_write_trdid.read(); + size_t pktid = r_write_pktid.read(); + addr_t nline = m_nline[(addr_t) (r_write_address.read())]; + size_t nb_copies = r_write_count.read(); + + wok = m_ivt.set(false, // it's an inval transaction + true, // it's a broadcast + true, // response required + false, // no acknowledge required + srcid, + trdid, + pktid, + nline, + nb_copies, + index); +#if DEBUG_MEMC_WRITE + if (m_debug and wok) + { + std::cout << " Register broadcast inval in IVT" + << " / nb_copies = " << r_write_count.read() << std::endl; + } +#endif + r_write_upt_index = index; + + if (wok) r_write_fsm = WRITE_BC_DIR_INVAL; + else r_write_fsm = WRITE_WAIT; + } + break; + } + //////////////////////// + case WRITE_BC_DIR_INVAL: // Register a put transaction in TRT + // and invalidate the line in directory + { + assert((r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and + "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad DIR allocation"); + + assert((r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) and + "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad TRT allocation"); + + assert((r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) and + "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad IVT allocation"); + + // register PUT request in TRT + std::vector data_vector; + data_vector.clear(); + for (size_t i = 0; i < m_words; i++) + { + data_vector.push_back(r_write_data[i].read()); + } + m_trt.set(r_write_trt_index.read(), + false, // PUT request + m_nline[(addr_t) (r_write_address.read())], + 0, // unused + 0, // unused + 0, // unused + false, // not a processor read + 0, // unused + 0, // unused + std::vector (m_words, 0), + data_vector); + + // invalidate directory entry + DirectoryEntry entry; + entry.valid = false; + entry.dirty = false; + entry.tag = 0; + entry.is_cnt = false; + entry.lock = false; + entry.owner.srcid = 0; + entry.owner.inst = false; + entry.ptr = 0; + entry.count = 0; + size_t set = m_y[(addr_t) (r_write_address.read())]; + size_t way = r_write_way.read(); + + m_cache_directory.write(set, way, entry); + + if ((r_write_pktid.read() & 0x7) == TYPE_SC) + { + m_llsc_table.sc(r_write_address.read(), r_write_sc_key.read()); + } + +#if DEBUG_MEMC_WRITE + if (m_debug) + { + std::cout << " Inval DIR and register in TRT:" + << " address = " << std::hex << r_write_address.read() << std::endl; + } +#endif + r_write_fsm = WRITE_BC_CC_SEND; + break; + } + + ////////////////////// + case WRITE_BC_CC_SEND: // Post a coherence broadcast request to CC_SEND FSM + { + if (!r_write_to_cc_send_multi_req.read() and !r_write_to_cc_send_brdcast_req.read()) + { + r_write_to_cc_send_multi_req = false; + r_write_to_cc_send_brdcast_req = true; + r_write_to_cc_send_trdid = r_write_upt_index.read(); + r_write_to_cc_send_nline = m_nline[(addr_t) (r_write_address.read())]; + r_write_to_cc_send_index = 0; + r_write_to_cc_send_count = 0; + + for (size_t i = 0; i < m_words; i++) // à quoi sert ce for? (AG) + { + r_write_to_cc_send_be[i] = 0; + r_write_to_cc_send_data[i] = 0; + } + r_write_fsm = WRITE_BC_XRAM_REQ; #if DEBUG_MEMC_WRITE if (m_debug) - std::cout << " Check TRT : wok = " << wok - << " / index = " << wok_index << std::endl; -#endif - break; - } - ////////////////////// - case WRITE_BC_IVT_LOCK: // get IVT lock and register BC transaction in IVT - { - assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and - "MEMC ERROR in WRITE_BC_IVT_LOCK state: Bad DIR allocation"); - - assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) and - "MEMC ERROR in WRITE_BC_IVT_LOCK state: Bad TRT allocation"); - - if (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) - { - bool wok = false; - size_t index = 0; - size_t srcid = r_write_srcid.read(); - size_t trdid = r_write_trdid.read(); - size_t pktid = r_write_pktid.read(); - addr_t nline = m_nline[(addr_t)(r_write_address.read())]; - size_t nb_copies = r_write_count.read(); - - wok = m_ivt.set(false, // it's an inval transaction - true, // it's a broadcast - true, // response required - false, // no acknowledge required - srcid, - trdid, - pktid, - nline, - nb_copies, - index); -#if DEBUG_MEMC_WRITE - if (m_debug and wok ) - std::cout << " Register broadcast inval in IVT" - << " / nb_copies = " << r_write_count.read() << std::endl; -#endif - r_write_upt_index = index; - - if (wok ) r_write_fsm = WRITE_BC_DIR_INVAL; - else r_write_fsm = WRITE_WAIT; - } - break; - } - //////////////////////// - case WRITE_BC_DIR_INVAL: // Register a put transaction in TRT - // and invalidate the line in directory - { - assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_WRITE) and - "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad DIR allocation"); - - assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE) and - "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad TRT allocation"); - - assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) and - "MEMC ERROR in WRITE_BC_DIR_INVAL state: Bad IVT allocation"); - - // register PUT request in TRT - std::vector data_vector; - data_vector.clear(); - for(size_t i=0; i (m_words,0), - data_vector ); - - // invalidate directory entry - DirectoryEntry entry; - entry.valid = false; - entry.dirty = false; - entry.tag = 0; - entry.is_cnt = false; - entry.lock = false; - entry.owner.srcid = 0; - entry.owner.inst = false; - entry.ptr = 0; - entry.count = 0; - size_t set = m_y[(addr_t)(r_write_address.read())]; - size_t way = r_write_way.read(); - - m_cache_directory.write(set, way, entry); - - if ((r_write_pktid.read() & 0x7) == TYPE_SC) - { - m_llsc_table.sc(r_write_address.read(), - r_write_sc_key.read()); - } + { + std::cout << " Post a broadcast request to CC_SEND FSM" << std::endl; + } +#endif + } + break; + } + + /////////////////////// + case WRITE_BC_XRAM_REQ: // Post a PUT request to IXR_CMD FSM + { + if (not r_write_to_ixr_cmd_req.read()) + { + r_write_to_ixr_cmd_req = true; + r_write_to_ixr_cmd_index = r_write_trt_index.read(); + r_write_fsm = WRITE_IDLE; #if DEBUG_MEMC_WRITE if (m_debug) - std::cout << " Inval DIR and register in TRT:" - << " address = " << std::hex << r_write_address.read() << std::endl; -#endif - r_write_fsm = WRITE_BC_CC_SEND; - break; - } - - ////////////////////// - case WRITE_BC_CC_SEND: // Post a coherence broadcast request to CC_SEND FSM - { - if (!r_write_to_cc_send_multi_req.read() and !r_write_to_cc_send_brdcast_req.read()) - { - r_write_to_cc_send_multi_req = false; - r_write_to_cc_send_brdcast_req = true; - r_write_to_cc_send_trdid = r_write_upt_index.read(); - r_write_to_cc_send_nline = m_nline[(addr_t)(r_write_address.read())]; - r_write_to_cc_send_index = 0; - r_write_to_cc_send_count = 0; - - for(size_t i=0; i Post a broadcast request to CC_SEND FSM" << std::endl; -#endif - } - break; - } - - /////////////////////// - case WRITE_BC_XRAM_REQ: // Post a PUT request to IXR_CMD FSM - { - if (not r_write_to_ixr_cmd_req.read()) - { - r_write_to_ixr_cmd_req = true; - r_write_to_ixr_cmd_index = r_write_trt_index.read(); - r_write_fsm = WRITE_IDLE; - -#if DEBUG_MEMC_WRITE - if (m_debug) - std::cout << " Post a put request to IXR_CMD FSM" << std::endl; -#endif - } - break; - } + { + std::cout << " Post a put request to IXR_CMD FSM" << std::endl; + } +#endif + } + break; + } } // end switch r_write_fsm @@ -4032,5 +4168,5 @@ // // - It sends a single flit VCI read to the XRAM in case of - // GET request posted by the READ, WRITE or CAS FSMs. + // GET request posted by the READ, WRITE or CAS FSMs. // - It sends a multi-flit VCI write in case of PUT request posted by // the XRAM_RSP, WRITE, CAS, or CONFIG FSMs. @@ -4045,278 +4181,228 @@ //////////////////////////////////////////////////////////////////////// - //std::cout << std::endl << "ixr_cmd_fsm" << std::endl; - - switch(r_ixr_cmd_fsm.read()) + switch (r_ixr_cmd_fsm.read()) { /////////////////////// case IXR_CMD_READ_IDLE: - { - if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; - else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; - else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; - else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; - else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; - break; - } - //////////////////////// + { + if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; + else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; + else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; + else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; + else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; + break; + } + //////////////////////// case IXR_CMD_WRITE_IDLE: - { - if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; - else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; - else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; - else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; - else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; - break; - } - ////////////////////// + { + if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; + else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; + else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; + else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; + else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; + break; + } + ////////////////////// case IXR_CMD_CAS_IDLE: - { - if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; - else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; - else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; - else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; - else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; - break; - } - /////////////////////// + { + if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; + else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; + else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; + else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; + else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; + break; + } + /////////////////////// case IXR_CMD_XRAM_IDLE: - { - if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; - else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; - else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; - else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; - else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; - break; - } - ///////////////////////// + { + if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; + else if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; + else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; + else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; + else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; + break; + } + ///////////////////////// case IXR_CMD_CONFIG_IDLE: - { - if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; - else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; - else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; - else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; - else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; - break; - } - - ////////////////////// + { + if (r_read_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_READ_TRT; + else if (r_write_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_WRITE_TRT; + else if (r_cas_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CAS_TRT; + else if (r_xram_rsp_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_XRAM_TRT; + else if (r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; + break; + } + + ////////////////////// case IXR_CMD_READ_TRT: // access TRT for a GET - { - if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) - { - TransactionTabEntry entry = m_trt.read( r_read_to_ixr_cmd_index.read()); - r_ixr_cmd_address = entry.nline * (m_words<<2); - r_ixr_cmd_trdid = r_read_to_ixr_cmd_index.read(); - r_ixr_cmd_get = true; - r_ixr_cmd_word = 0; - r_ixr_cmd_fsm = IXR_CMD_READ_SEND; + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD) + { + TransactionTabEntry entry = m_trt.read(r_read_to_ixr_cmd_index.read()); + r_ixr_cmd_address = entry.nline * (m_words << 2); + r_ixr_cmd_trdid = r_read_to_ixr_cmd_index.read(); + r_ixr_cmd_get = true; + r_ixr_cmd_word = 0; + r_ixr_cmd_fsm = IXR_CMD_READ_SEND; #if DEBUG_MEMC_IXR_CMD - if (m_debug) - std::cout << " TRT access" - << " index = " << std::dec << r_read_to_ixr_cmd_index.read() - << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; -#endif - } - break; - } - /////////////////////// - case IXR_CMD_WRITE_TRT: // access TRT for a PUT or a GET - { - if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) - { - TransactionTabEntry entry = m_trt.read( r_write_to_ixr_cmd_index.read()); - r_ixr_cmd_address = entry.nline * (m_words<<2); - r_ixr_cmd_trdid = r_write_to_ixr_cmd_index.read(); - r_ixr_cmd_get = entry.xram_read; - r_ixr_cmd_word = 0; - r_ixr_cmd_fsm = IXR_CMD_WRITE_SEND; - - // Read data from TRT if PUT transaction - if (not entry.xram_read) + if (m_debug) + { + std::cout << " TRT access" + << " index = " << std::dec << r_read_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline * (m_words << 2)) << std::endl; + } +#endif + } + break; + } + /////////////////////// + case IXR_CMD_WRITE_TRT: // access TRT for a PUT or a GET + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD) + { + TransactionTabEntry entry = m_trt.read(r_write_to_ixr_cmd_index.read()); + r_ixr_cmd_address = entry.nline * (m_words << 2); + r_ixr_cmd_trdid = r_write_to_ixr_cmd_index.read(); + r_ixr_cmd_get = entry.xram_read; + r_ixr_cmd_word = 0; + r_ixr_cmd_fsm = IXR_CMD_WRITE_SEND; + + // Read data from TRT if PUT transaction + if (not entry.xram_read) + { + for (size_t i = 0; i < m_words; i++) { - for( size_t i=0 ; i TRT access" - << " index = " << std::dec << r_write_to_ixr_cmd_index.read() - << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; -#endif - } - break; - } - ///////////////////// - case IXR_CMD_CAS_TRT: // access TRT for a PUT or a GET - { - if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) - { - TransactionTabEntry entry = m_trt.read( r_cas_to_ixr_cmd_index.read()); - r_ixr_cmd_address = entry.nline * (m_words<<2); - r_ixr_cmd_trdid = r_cas_to_ixr_cmd_index.read(); - r_ixr_cmd_get = entry.xram_read; - r_ixr_cmd_word = 0; - r_ixr_cmd_fsm = IXR_CMD_CAS_SEND; - - // Read data from TRT if PUT transaction - if (not entry.xram_read) + if (m_debug) + { + std::cout << " TRT access" + << " index = " << std::dec << r_write_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline * (m_words << 2)) << std::endl; + } +#endif + } + break; + } + ///////////////////// + case IXR_CMD_CAS_TRT: // access TRT for a PUT or a GET + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD) + { + TransactionTabEntry entry = m_trt.read(r_cas_to_ixr_cmd_index.read()); + r_ixr_cmd_address = entry.nline * (m_words << 2); + r_ixr_cmd_trdid = r_cas_to_ixr_cmd_index.read(); + r_ixr_cmd_get = entry.xram_read; + r_ixr_cmd_word = 0; + r_ixr_cmd_fsm = IXR_CMD_CAS_SEND; + + // Read data from TRT if PUT transaction + if (not entry.xram_read) + { + for (size_t i = 0; i < m_words; i++) { - for( size_t i=0 ; i TRT access" - << " index = " << std::dec << r_cas_to_ixr_cmd_index.read() - << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; -#endif - } - break; - } - ////////////////////// - case IXR_CMD_XRAM_TRT: // access TRT for a PUT - { - if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) - { - TransactionTabEntry entry = m_trt.read( r_xram_rsp_to_ixr_cmd_index.read()); - r_ixr_cmd_address = entry.nline * (m_words<<2); - r_ixr_cmd_trdid = r_xram_rsp_to_ixr_cmd_index.read(); - r_ixr_cmd_get = false; - r_ixr_cmd_word = 0; - r_ixr_cmd_fsm = IXR_CMD_XRAM_SEND; - for( size_t i=0 ; i TRT access" + << " index = " << std::dec << r_cas_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline * (m_words << 2)) << std::endl; + } +#endif + } + break; + } + ////////////////////// + case IXR_CMD_XRAM_TRT: // access TRT for a PUT + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD) + { + TransactionTabEntry entry = m_trt.read(r_xram_rsp_to_ixr_cmd_index.read()); + r_ixr_cmd_address = entry.nline * (m_words << 2); + r_ixr_cmd_trdid = r_xram_rsp_to_ixr_cmd_index.read(); + r_ixr_cmd_get = false; + r_ixr_cmd_word = 0; + r_ixr_cmd_fsm = IXR_CMD_XRAM_SEND; + for (size_t i = 0; i < m_words; i++) + { + r_ixr_cmd_wdata[i] = entry.wdata[i]; + } #if DEBUG_MEMC_IXR_CMD - if (m_debug) - std::cout << " TRT access" - << " index = " << std::dec << r_xram_rsp_to_ixr_cmd_index.read() - << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; -#endif - } - break; - } - //////////////////////// + if (m_debug) + { + std::cout << " TRT access" + << " index = " << std::dec << r_xram_rsp_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; + } +#endif + } + break; + } + //////////////////////// case IXR_CMD_CONFIG_TRT: // access TRT for a PUT - { - if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) - { - TransactionTabEntry entry = m_trt.read( r_config_to_ixr_cmd_index.read()); - r_ixr_cmd_address = entry.nline * (m_words<<2); - r_ixr_cmd_trdid = r_config_to_ixr_cmd_index.read(); - r_ixr_cmd_get = false; - r_ixr_cmd_word = 0; - r_ixr_cmd_fsm = IXR_CMD_CONFIG_SEND; - for( size_t i=0 ; i TRT access" - << " index = " << std::dec << r_config_to_ixr_cmd_index.read() - << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; -#endif - } - break; - } - - /////////////////////// + if (m_debug) + { + std::cout << " TRT access" + << " index = " << std::dec << r_config_to_ixr_cmd_index.read() + << " / address = " << std::hex << (entry.nline*(m_words<<2)) << std::endl; + } +#endif + } + break; + } + + /////////////////////// case IXR_CMD_READ_SEND: // send a get from READ FSM - { - if (p_vci_ixr.cmdack) - { - r_ixr_cmd_fsm = IXR_CMD_READ_IDLE; - r_read_to_ixr_cmd_req = false; + { + if (p_vci_ixr.cmdack) + { + r_ixr_cmd_fsm = IXR_CMD_READ_IDLE; + r_read_to_ixr_cmd_req = false; #if DEBUG_MEMC_IXR_CMD - if (m_debug) - std::cout << " GET request:" << std::hex - << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; -#endif - } - break; - } - //////////////////////// + if (m_debug) + { + std::cout << " GET request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; + } +#endif + } + break; + } + //////////////////////// case IXR_CMD_WRITE_SEND: // send a put or get from WRITE FSM - { - if (p_vci_ixr.cmdack) - { - if (not r_ixr_cmd_get.read()) // PUT - { - if (r_ixr_cmd_word.read() == (m_words - 2)) - { - r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE; - r_write_to_ixr_cmd_req = false; - } - else - { - r_ixr_cmd_word = r_ixr_cmd_word.read() + 2; - } - -#if DEBUG_MEMC_IXR_CMD - if (m_debug) - std::cout << " PUT request:" << std::hex - << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; -#endif - } - else // GET + { + if (p_vci_ixr.cmdack) + { + if (not r_ixr_cmd_get.read()) // PUT + { + if (r_ixr_cmd_word.read() == (m_words - 2)) { r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE; r_write_to_ixr_cmd_req = false; - -#if DEBUG_MEMC_IXR_CMD - if (m_debug) - std::cout << " GET request:" << std::hex - << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; -#endif - } - } - break; - } - ////////////////////// - case IXR_CMD_CAS_SEND: // send a put or get command from CAS FSM - { - if (p_vci_ixr.cmdack) - { - if (not r_ixr_cmd_get.read()) // PUT - { - if (r_ixr_cmd_word.read() == (m_words - 2)) - { - r_ixr_cmd_fsm = IXR_CMD_CAS_IDLE; - r_cas_to_ixr_cmd_req = false; - } - else - { - r_ixr_cmd_word = r_ixr_cmd_word.read() + 2; - } - -#if DEBUG_MEMC_IXR_CMD - if (m_debug) - std::cout << " PUT request:" << std::hex - << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; -#endif - } - else // GET - { - r_ixr_cmd_fsm = IXR_CMD_CAS_IDLE; - r_cas_to_ixr_cmd_req = false; - -#if DEBUG_MEMC_IXR_CMD - if (m_debug) - std::cout << " GET request:" << std::hex - << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; -#endif - } - } - break; - } - /////////////////////// - case IXR_CMD_XRAM_SEND: // send a put from XRAM_RSP FSM - { - if (p_vci_ixr.cmdack.read()) - { - if (r_ixr_cmd_word.read() == (m_words - 2)) - { - r_ixr_cmd_fsm = IXR_CMD_XRAM_IDLE; - r_xram_rsp_to_ixr_cmd_req = false; } else @@ -4327,19 +4413,37 @@ #if DEBUG_MEMC_IXR_CMD if (m_debug) - std::cout << " PUT request:" << std::hex + { + std::cout << " PUT request:" << std::hex << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; -#endif - } - break; - } - ///////////////////////// - case IXR_CMD_CONFIG_SEND: // send a put from CONFIG FSM - { - if (p_vci_ixr.cmdack.read()) + } +#endif + } + else // GET + { + r_ixr_cmd_fsm = IXR_CMD_WRITE_IDLE; + r_write_to_ixr_cmd_req = false; + +#if DEBUG_MEMC_IXR_CMD + if (m_debug) + { + std::cout << " GET request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; + } +#endif + } + } + break; + } + ////////////////////// + case IXR_CMD_CAS_SEND: // send a put or get command from CAS FSM + { + if (p_vci_ixr.cmdack) + { + if (not r_ixr_cmd_get.read()) // PUT { if (r_ixr_cmd_word.read() == (m_words - 2)) { - r_ixr_cmd_fsm = IXR_CMD_CONFIG_IDLE; - r_config_to_ixr_cmd_req = false; + r_ixr_cmd_fsm = IXR_CMD_CAS_IDLE; + r_cas_to_ixr_cmd_req = false; } else @@ -4350,10 +4454,76 @@ #if DEBUG_MEMC_IXR_CMD if (m_debug) - std::cout << " PUT request:" << std::hex - << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; -#endif - } - break; - } + { + std::cout << " PUT request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read() << 2) << std::endl; + } +#endif + } + else // GET + { + r_ixr_cmd_fsm = IXR_CMD_CAS_IDLE; + r_cas_to_ixr_cmd_req = false; + +#if DEBUG_MEMC_IXR_CMD + if (m_debug) + { + std::cout << " GET request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read() << 2) << std::endl; + } +#endif + } + } + break; + } + /////////////////////// + case IXR_CMD_XRAM_SEND: // send a put from XRAM_RSP FSM + { + if (p_vci_ixr.cmdack.read()) + { + if (r_ixr_cmd_word.read() == (m_words - 2)) + { + r_ixr_cmd_fsm = IXR_CMD_XRAM_IDLE; + r_xram_rsp_to_ixr_cmd_req = false; + } + else + { + r_ixr_cmd_word = r_ixr_cmd_word.read() + 2; + } + +#if DEBUG_MEMC_IXR_CMD + if (m_debug) + { + std::cout << " PUT request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read() << 2) << std::endl; + } +#endif + } + break; + } + ///////////////////////// + case IXR_CMD_CONFIG_SEND: // send a put from CONFIG FSM + { + if (p_vci_ixr.cmdack.read()) + { + if (r_ixr_cmd_word.read() == (m_words - 2)) + { + r_ixr_cmd_fsm = IXR_CMD_CONFIG_IDLE; + r_config_to_ixr_cmd_req = false; + } + else + { + r_ixr_cmd_word = r_ixr_cmd_word.read() + 2; + } + +#if DEBUG_MEMC_IXR_CMD + if (m_debug) + { + std::cout << " PUT request:" << std::hex + << " address = " << r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2) << std::endl; + } +#endif + } + break; + } } // end switch r_ixr_cmd_fsm @@ -4368,5 +4538,5 @@ // The FSM takes the lock protecting the TRT, and the corresponding // entry is erased. If an acknowledge was required (in case of software SYNC) - // the r_config_rsp_lines counter is decremented. + // the r_config_rsp_lines counter is decremented. // // - A response to a GET request is a multi-cell VCI packet. @@ -4375,5 +4545,5 @@ // The FSM takes the lock protecting the TRT to store the line in the TRT // (taking into account the write requests already stored in the TRT). - // When the line is completely written, the r_ixr_rsp_to_xram_rsp_rok[index] + // When the line is completely written, the r_ixr_rsp_to_xram_rsp_rok[index] // signal is set to inform the XRAM_RSP FSM. /////////////////////////////////////////////////////////////////////////////// @@ -4385,34 +4555,36 @@ ////////////////// case IXR_RSP_IDLE: // test transaction type: PUT/GET - { - if (p_vci_ixr.rspval.read()) - { - r_ixr_rsp_cpt = 0; - r_ixr_rsp_trt_index = p_vci_ixr.rtrdid.read(); - - if (p_vci_ixr.reop.read() and not + { + if (p_vci_ixr.rspval.read()) + { + r_ixr_rsp_cpt = 0; + r_ixr_rsp_trt_index = p_vci_ixr.rtrdid.read(); + + if (p_vci_ixr.reop.read() and not p_vci_ixr.rerror.read()) // PUT + { + r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE; + +#if DEBUG_MEMC_IXR_RSP + if (m_debug) + std::cout << " Response from XRAM to a put transaction" << std::endl; +#endif + } + else // GET + { + r_ixr_rsp_fsm = IXR_RSP_TRT_READ; + +#if DEBUG_MEMC_IXR_RSP + if (m_debug) { - r_ixr_rsp_fsm = IXR_RSP_TRT_ERASE; - -#if DEBUG_MEMC_IXR_RSP -if (m_debug) -std::cout << " Response from XRAM to a put transaction" << std::endl; -#endif + std::cout << " Response from XRAM to a get transaction" << std::endl; } - else // GET - { - r_ixr_rsp_fsm = IXR_RSP_TRT_READ; - -#if DEBUG_MEMC_IXR_RSP -if (m_debug) -std::cout << " Response from XRAM to a get transaction" << std::endl; -#endif - } - } - break; - } +#endif + } + } + break; + } //////////////////////// case IXR_RSP_TRT_ERASE: // erase the entry in the TRT @@ -4421,7 +4593,7 @@ if (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) { - size_t index = r_ixr_rsp_trt_index.read(); - - if (m_trt.is_config(index)) // it's a config transaction + size_t index = r_ixr_rsp_trt_index.read(); + + if (m_trt.is_config(index)) // it's a config transaction { config_rsp_lines_ixr_rsp_decr = true; @@ -4432,7 +4604,9 @@ #if DEBUG_MEMC_IXR_RSP -if (m_debug) -std::cout << " Erase TRT entry " - << r_ixr_rsp_trt_index.read() << std::endl; + if (m_debug) + { + std::cout << " Erase TRT entry " + << r_ixr_rsp_trt_index.read() << std::endl; + } #endif } @@ -4440,22 +4614,22 @@ } ////////////////////// - case IXR_RSP_TRT_READ: // write a 64 bits data word in TRT - { - if ((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and p_vci_ixr.rspval) - { - size_t index = r_ixr_rsp_trt_index.read(); - size_t word = r_ixr_rsp_cpt.read(); - bool eop = p_vci_ixr.reop.read(); - wide_data_t data = p_vci_ixr.rdata.read(); - bool rerror = ((p_vci_ixr.rerror.read() & 0x1) == 1); - - assert(((eop == (word == (m_words-2))) or rerror) and + case IXR_RSP_TRT_READ: // write a 64 bits data word in TRT + { + if ((r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) and p_vci_ixr.rspval) + { + size_t index = r_ixr_rsp_trt_index.read(); + size_t word = r_ixr_rsp_cpt.read(); + bool eop = p_vci_ixr.reop.read(); + wide_data_t data = p_vci_ixr.rdata.read(); + bool rerror = ((p_vci_ixr.rerror.read() & 0x1) == 1); + + assert(((eop == (word == (m_words - 2))) or rerror) and "MEMC ERROR in IXR_RSP_TRT_READ state : invalid response from XRAM"); - m_trt.write_rsp( index, word, data, rerror ); + m_trt.write_rsp(index, word, data, rerror); r_ixr_rsp_cpt = word + 2; - if (eop ) + if (eop) { r_ixr_rsp_to_xram_rsp_rok[r_ixr_rsp_trt_index.read()] = true; @@ -4464,9 +4638,11 @@ #if DEBUG_MEMC_IXR_RSP -if (m_debug) -std::cout << " Writing 2 words in TRT : " - << " index = " << std::dec << index - << " / word = " << word - << " / data = " << std::hex << data << std::endl; + if (m_debug) + { + std::cout << " Writing 2 words in TRT : " + << " index = " << std::dec << index + << " / word = " << word + << " / data = " << std::hex << data << std::endl; + } #endif } @@ -4481,5 +4657,5 @@ // The cache line has been written in the TRT by the IXR_CMD_FSM. // As the IXR_RSP FSM and the XRAM_RSP FSM are running in parallel, - // there is as many flip-flops r_ixr_rsp_to_xram_rsp_rok[i] as the number + // there is as many flip-flops r_ixr_rsp_to_xram_rsp_rok[i] as the number // of entries in the TRT, that are handled with a round-robin priority... // @@ -4498,436 +4674,454 @@ /////////////////////////////////////////////////////////////////////////////// - //std::cout << std::endl << "xram_rsp_fsm" << std::endl; - switch(r_xram_rsp_fsm.read()) { /////////////////// case XRAM_RSP_IDLE: // scan the XRAM responses / select a TRT index (round robin) - { - size_t old = r_xram_rsp_trt_index.read(); - size_t lines = m_trt_lines; - for(size_t i=0 ; i" - << " Available cache line in TRT:" - << " index = " << std::dec << index << std::endl; -#endif - break; - } - } - break; - } - /////////////////////// - case XRAM_RSP_DIR_LOCK: // Takes the DIR lock and the TRT lock - // Copy the TRT entry in a local buffer - { - if ((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and - (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP)) - { - // copy the TRT entry in the r_xram_rsp_trt_buf local buffer - size_t index = r_xram_rsp_trt_index.read(); - r_xram_rsp_trt_buf.copy( m_trt.read(index)); - r_xram_rsp_fsm = XRAM_RSP_TRT_COPY; + { + size_t old = r_xram_rsp_trt_index.read(); + size_t lines = m_trt_lines; + for (size_t i = 0; i < lines; i++) + { + size_t index = (i + old + 1) % lines; + if (r_ixr_rsp_to_xram_rsp_rok[index]) + { + r_xram_rsp_trt_index = index; + r_ixr_rsp_to_xram_rsp_rok[index] = false; + r_xram_rsp_fsm = XRAM_RSP_DIR_LOCK; #if DEBUG_MEMC_XRAM_RSP if (m_debug) - std::cout << " " - << " Get access to DIR and TRT" << std::endl; -#endif - } - break; - } - /////////////////////// - case XRAM_RSP_TRT_COPY: // Select a victim cache line - // and copy it in a local buffer - { - assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and - "MEMC ERROR in XRAM_RSP_TRT_COPY state: Bad DIR allocation"); - - assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and - "MEMC ERROR in XRAM_RSP_TRT_COPY state: Bad TRT allocation"); - - // selects & extracts a victim line from cache - size_t way = 0; - size_t set = m_y[(addr_t)(r_xram_rsp_trt_buf.nline * m_words * 4)]; - - DirectoryEntry victim(m_cache_directory.select(set, way)); - - bool inval = (victim.count and victim.valid) ; - - // copy the victim line in a local buffer (both data dir) - m_cache_data.read_line(way, set, r_xram_rsp_victim_data); - - r_xram_rsp_victim_copy = victim.owner.srcid; - r_xram_rsp_victim_copy_inst = victim.owner.inst; - r_xram_rsp_victim_count = victim.count; - r_xram_rsp_victim_ptr = victim.ptr; - r_xram_rsp_victim_way = way; - r_xram_rsp_victim_set = set; - r_xram_rsp_victim_nline = (addr_t)victim.tag*m_sets + set; - r_xram_rsp_victim_is_cnt = victim.is_cnt; - r_xram_rsp_victim_inval = inval ; - r_xram_rsp_victim_dirty = victim.dirty; - - if (not r_xram_rsp_trt_buf.rerror ) r_xram_rsp_fsm = XRAM_RSP_IVT_LOCK; - else r_xram_rsp_fsm = XRAM_RSP_ERROR_ERASE; + { + std::cout << " " + << " Available cache line in TRT:" + << " index = " << std::dec << index << std::endl; + } +#endif + break; + } + } + break; + } + /////////////////////// + case XRAM_RSP_DIR_LOCK: // Takes the DIR lock and the TRT lock + // Copy the TRT entry in a local buffer + { + if ((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and + (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP)) + { + // copy the TRT entry in the r_xram_rsp_trt_buf local buffer + size_t index = r_xram_rsp_trt_index.read(); + r_xram_rsp_trt_buf.copy(m_trt.read(index)); + r_xram_rsp_fsm = XRAM_RSP_TRT_COPY; #if DEBUG_MEMC_XRAM_RSP if (m_debug) - std::cout << " " - << " Select a victim slot: " - << " way = " << std::dec << way - << " / set = " << set - << " / inval_required = " << inval << std::endl; -#endif - break; - } - /////////////////////// - case XRAM_RSP_IVT_LOCK: // Keep DIR and TRT locks and take the IVT lock - // to check a possible pending inval - { - assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and - "MEMC ERROR in XRAM_RSP_IVT_LOCK state: Bad DIR allocation"); - - assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and - "MEMC ERROR in XRAM_RSP_IVT_LOCK state: Bad TRT allocation"); - - if (r_alloc_ivt_fsm == ALLOC_IVT_XRAM_RSP) - { - size_t index = 0; - if (m_ivt.search_inval(r_xram_rsp_trt_buf.nline, index)) // pending inval + { + std::cout << " " + << " Get access to DIR and TRT" << std::endl; + } +#endif + } + break; + } + /////////////////////// + case XRAM_RSP_TRT_COPY: // Select a victim cache line + // and copy it in a local buffer + { + assert((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and + "MEMC ERROR in XRAM_RSP_TRT_COPY state: Bad DIR allocation"); + + assert((r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and + "MEMC ERROR in XRAM_RSP_TRT_COPY state: Bad TRT allocation"); + + // selects & extracts a victim line from cache + size_t way = 0; + size_t set = m_y[(addr_t) (r_xram_rsp_trt_buf.nline * m_words * 4)]; + + DirectoryEntry victim(m_cache_directory.select(set, way)); + + bool inval = (victim.count and victim.valid) ; + + // copy the victim line in a local buffer (both data dir) + m_cache_data.read_line(way, set, r_xram_rsp_victim_data); + + r_xram_rsp_victim_copy = victim.owner.srcid; + r_xram_rsp_victim_copy_inst = victim.owner.inst; + r_xram_rsp_victim_count = victim.count; + r_xram_rsp_victim_ptr = victim.ptr; + r_xram_rsp_victim_way = way; + r_xram_rsp_victim_set = set; + r_xram_rsp_victim_nline = (addr_t)victim.tag*m_sets + set; + r_xram_rsp_victim_is_cnt = victim.is_cnt; + r_xram_rsp_victim_inval = inval ; + r_xram_rsp_victim_dirty = victim.dirty; + + if (not r_xram_rsp_trt_buf.rerror) r_xram_rsp_fsm = XRAM_RSP_IVT_LOCK; + else r_xram_rsp_fsm = XRAM_RSP_ERROR_ERASE; + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + { + std::cout << " " + << " Select a victim slot: " + << " way = " << std::dec << way + << " / set = " << set + << " / inval_required = " << inval << std::endl; + } +#endif + break; + } + /////////////////////// + case XRAM_RSP_IVT_LOCK: // Keep DIR and TRT locks and take the IVT lock + // to check a possible pending inval + { + assert((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and + "MEMC ERROR in XRAM_RSP_IVT_LOCK state: Bad DIR allocation"); + + assert((r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and + "MEMC ERROR in XRAM_RSP_IVT_LOCK state: Bad TRT allocation"); + + if (r_alloc_ivt_fsm == ALLOC_IVT_XRAM_RSP) + { + size_t index = 0; + if (m_ivt.search_inval(r_xram_rsp_trt_buf.nline, index)) // pending inval + { + r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) { - r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; + std::cout << " " + << " Get acces to IVT, but line invalidation registered" + << " / address = " << std::hex << r_xram_rsp_trt_buf.nline * m_words * 4 + << " / index = " << std::dec << index << std::endl; + } +#endif + + } + else if (m_ivt.is_full() and r_xram_rsp_victim_inval.read()) // IVT full + { + r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; #if DEBUG_MEMC_XRAM_RSP - if (m_debug) - std::cout << " " - << " Get acces to IVT, but line invalidation registered" - << " / address = " << std::hex << r_xram_rsp_trt_buf.nline*m_words*4 - << " / index = " << std::dec << index << std::endl; -#endif - + if (m_debug) + { + std::cout << " " + << " Get acces to IVT, but inval required and IVT full" << std::endl; } - else if (m_ivt.is_full() and r_xram_rsp_victim_inval.read()) // IVT full +#endif + } + else + { + r_xram_rsp_fsm = XRAM_RSP_DIR_UPDT; + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) { - r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; + std::cout << " " + << " Get acces to IVT / no pending inval request" << std::endl; + } +#endif + } + } + break; + } + ///////////////////////// + case XRAM_RSP_INVAL_WAIT: // release all locks and returns to DIR_LOCK to retry + { #if DEBUG_MEMC_XRAM_RSP - if (m_debug) - std::cout << " " - << " Get acces to IVT, but inval required and IVT full" << std::endl; -#endif - } - else - { - r_xram_rsp_fsm = XRAM_RSP_DIR_UPDT; + if (m_debug) + { + std::cout << " " + << " Release all locks and retry" << std::endl; + } +#endif + r_xram_rsp_fsm = XRAM_RSP_DIR_LOCK; + break; + } + /////////////////////// + case XRAM_RSP_DIR_UPDT: // updates the cache (both data & directory), + // erases the TRT entry if victim not dirty, + // and set inval request in IVT if required + { + assert((r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and + "MEMC ERROR in XRAM_RSP_DIR_UPDT state: Bad DIR allocation"); + + assert((r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and + "MEMC ERROR in XRAM_RSP_DIR_UPDT state: Bad TRT allocation"); + + assert((r_alloc_ivt_fsm.read() == ALLOC_IVT_XRAM_RSP) and + "MEMC ERROR in XRAM_RSP_DIR_UPDT state: Bad IVT allocation"); + + // check if this is an instruction read, this means pktid is either + // TYPE_READ_INS_UNC 0bX010 with TSAR encoding + // TYPE_READ_INS_MISS 0bX011 with TSAR encoding + bool inst_read = (r_xram_rsp_trt_buf.pktid & 0x2) and r_xram_rsp_trt_buf.proc_read; + + // check if this is a cached read, this means pktid is either + // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding + // TYPE_READ_INS_MISS 0bX011 with TSAR encoding + bool cached_read = (r_xram_rsp_trt_buf.pktid & 0x1) and r_xram_rsp_trt_buf.proc_read; + + bool dirty = false; + + // update cache data + size_t set = r_xram_rsp_victim_set.read(); + size_t way = r_xram_rsp_victim_way.read(); + + for (size_t word = 0; word < m_words; word++) + { + m_cache_data.write(way, set, word, r_xram_rsp_trt_buf.wdata[word]); + dirty = dirty or (r_xram_rsp_trt_buf.wdata_be[word] != 0); + } + + // update cache directory + DirectoryEntry entry; + entry.valid = true; + entry.is_cnt = false; + entry.lock = false; + entry.dirty = dirty; + entry.tag = r_xram_rsp_trt_buf.nline / m_sets; + entry.ptr = 0; + if (cached_read) + { + entry.owner.srcid = r_xram_rsp_trt_buf.srcid; + entry.owner.inst = inst_read; + entry.count = 1; + } + else + { + entry.owner.srcid = 0; + entry.owner.inst = 0; + entry.count = 0; + } + m_cache_directory.write(set, way, entry); + + // register invalid request in IVT for victim line if required + if (r_xram_rsp_victim_inval.read()) + { + bool broadcast = r_xram_rsp_victim_is_cnt.read(); + size_t index = 0; + size_t count_copies = r_xram_rsp_victim_count.read(); + + bool wok = m_ivt.set(false, // it's an inval transaction + broadcast, // set broadcast bit + false, // no response required + false, // no acknowledge required + 0, // srcid + 0, // trdid + 0, // pktid + r_xram_rsp_victim_nline.read(), + count_copies, + index); + + r_xram_rsp_ivt_index = index; + + assert(wok and "MEMC ERROR in XRAM_RSP_DIR_UPDT state: IVT should not be full"); + } #if DEBUG_MEMC_XRAM_RSP - if (m_debug) - std::cout << " " - << " Get acces to IVT / no pending inval request" << std::endl; -#endif - } - } - break; - } - ///////////////////////// - case XRAM_RSP_INVAL_WAIT: // release all locks and returns to DIR_LOCK to retry - { + if (m_debug) + { + std::cout << " " + << " Cache update: " + << " way = " << std::dec << way + << " / set = " << set + << " / owner_id = " << std::hex << entry.owner.srcid + << " / owner_ins = " << std::dec << entry.owner.inst + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt << std::endl; + if (r_xram_rsp_victim_inval.read()) + { + std::cout << " Invalidation request for address " + << std::hex << r_xram_rsp_victim_nline.read() * m_words * 4 + << " / broadcast = " << r_xram_rsp_victim_is_cnt.read() << std::endl; + } + } +#endif + + // If the victim is not dirty, we don't need to reuse the TRT entry for + // another PUT transaction, and we can erase the TRT entry + if (not r_xram_rsp_victim_dirty.read()) + { + m_trt.erase(r_xram_rsp_trt_index.read()); + } + + // Next state + if (r_xram_rsp_victim_dirty.read()) r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY; + else if (r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_DIR_RSP; + else if (r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; + else r_xram_rsp_fsm = XRAM_RSP_IDLE; + break; + } + //////////////////////// + case XRAM_RSP_TRT_DIRTY: // set the TRT entry (PUT to XRAM) if the victim is dirty + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) + { + std::vector data_vector; + data_vector.clear(); + for (size_t i = 0; i < m_words; i++) + { + data_vector.push_back(r_xram_rsp_victim_data[i].read()); + } + m_trt.set(r_xram_rsp_trt_index.read(), + false, // PUT + r_xram_rsp_victim_nline.read(), // line index + 0, // unused + 0, // unused + 0, // unused + false, // not proc_read + 0, // unused + 0, // unused + std::vector(m_words,0xF), + data_vector); #if DEBUG_MEMC_XRAM_RSP if (m_debug) - std::cout << " " - << " Release all locks and retry" << std::endl; -#endif - r_xram_rsp_fsm = XRAM_RSP_DIR_LOCK; - break; - } - /////////////////////// - case XRAM_RSP_DIR_UPDT: // updates the cache (both data & directory), - // erases the TRT entry if victim not dirty, - // and set inval request in IVT if required - { - assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_XRAM_RSP) and - "MEMC ERROR in XRAM_RSP_DIR_UPDT state: Bad DIR allocation"); - - assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) and - "MEMC ERROR in XRAM_RSP_DIR_UPDT state: Bad TRT allocation"); - - assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_XRAM_RSP) and - "MEMC ERROR in XRAM_RSP_DIR_UPDT state: Bad IVT allocation"); - - // check if this is an instruction read, this means pktid is either - // TYPE_READ_INS_UNC 0bX010 with TSAR encoding - // TYPE_READ_INS_MISS 0bX011 with TSAR encoding - bool inst_read = (r_xram_rsp_trt_buf.pktid & 0x2) and r_xram_rsp_trt_buf.proc_read; - - // check if this is a cached read, this means pktid is either - // TYPE_READ_DATA_MISS 0bX001 with TSAR encoding - // TYPE_READ_INS_MISS 0bX011 with TSAR encoding - bool cached_read = (r_xram_rsp_trt_buf.pktid & 0x1) and r_xram_rsp_trt_buf.proc_read; - - bool dirty = false; - - // update cache data - size_t set = r_xram_rsp_victim_set.read(); - size_t way = r_xram_rsp_victim_way.read(); - - for(size_t word=0; word" + << " Set TRT entry for the put transaction" + << " / address = " << (r_xram_rsp_victim_nline.read() * m_words * 4) << std::endl; + } +#endif + if (r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_DIR_RSP; + else if (r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; + else r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; + } + break; + } + ////////////////////// + case XRAM_RSP_DIR_RSP: // Request a response to TGT_RSP FSM + { + if (not r_xram_rsp_to_tgt_rsp_req.read()) + { + r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid; + r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid; + r_xram_rsp_to_tgt_rsp_pktid = r_xram_rsp_trt_buf.pktid; + for (size_t i = 0; i < m_words; i++) + { + r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i]; + } + r_xram_rsp_to_tgt_rsp_word = r_xram_rsp_trt_buf.word_index; + r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length; + r_xram_rsp_to_tgt_rsp_ll_key = r_xram_rsp_trt_buf.ll_key; + r_xram_rsp_to_tgt_rsp_rerror = false; + r_xram_rsp_to_tgt_rsp_req = true; + + if (r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; + else if (r_xram_rsp_victim_dirty.read()) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; + else r_xram_rsp_fsm = XRAM_RSP_IDLE; #if DEBUG_MEMC_XRAM_RSP if (m_debug) { - std::cout << " " - << " Cache update: " - << " way = " << std::dec << way - << " / set = " << set - << " / owner_id = " << std::hex << entry.owner.srcid - << " / owner_ins = " << std::dec << entry.owner.inst - << " / count = " << entry.count - << " / is_cnt = " << entry.is_cnt << std::endl; - if (r_xram_rsp_victim_inval.read()) - std::cout << " Invalidation request for address " - << std::hex << r_xram_rsp_victim_nline.read()*m_words*4 - << " / broadcast = " << r_xram_rsp_victim_is_cnt.read() << std::endl; - } -#endif - - // If the victim is not dirty, we don't need to reuse the TRT entry for - // another PUT transaction, and we can erase the TRT entry - if (not r_xram_rsp_victim_dirty.read()) - { - m_trt.erase(r_xram_rsp_trt_index.read()); - } - - // Next state - if (r_xram_rsp_victim_dirty.read()) r_xram_rsp_fsm = XRAM_RSP_TRT_DIRTY; - else if (r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_DIR_RSP; - else if (r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; - else r_xram_rsp_fsm = XRAM_RSP_IDLE; - break; - } - //////////////////////// - case XRAM_RSP_TRT_DIRTY: // set the TRT entry (PUT to XRAM) if the victim is dirty - { - if (r_alloc_trt_fsm.read() == ALLOC_TRT_XRAM_RSP) - { - std::vector data_vector; - data_vector.clear(); - for(size_t i=0; i(m_words,0xF), - data_vector); - -#if DEBUG_MEMC_XRAM_RSP - if (m_debug) - std::cout << " " - << " Set TRT entry for the put transaction" - << " / address = " << (r_xram_rsp_victim_nline.read()*m_words*4) << std::endl; -#endif - if (r_xram_rsp_trt_buf.proc_read) r_xram_rsp_fsm = XRAM_RSP_DIR_RSP; - else if (r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; - else r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; - } - break; - } - ////////////////////// - case XRAM_RSP_DIR_RSP: // Request a response to TGT_RSP FSM - { - if (not r_xram_rsp_to_tgt_rsp_req.read()) - { - r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid; - r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid; - r_xram_rsp_to_tgt_rsp_pktid = r_xram_rsp_trt_buf.pktid; - for(size_t i=0; i < m_words; i++) - { - r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i]; - } - r_xram_rsp_to_tgt_rsp_word = r_xram_rsp_trt_buf.word_index; - r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length; - r_xram_rsp_to_tgt_rsp_ll_key = r_xram_rsp_trt_buf.ll_key; - r_xram_rsp_to_tgt_rsp_rerror = false; - r_xram_rsp_to_tgt_rsp_req = true; - - if (r_xram_rsp_victim_inval.read()) r_xram_rsp_fsm = XRAM_RSP_INVAL; - else if (r_xram_rsp_victim_dirty.read()) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; - else r_xram_rsp_fsm = XRAM_RSP_IDLE; - -#if DEBUG_MEMC_XRAM_RSP - if (m_debug) - std::cout << " " - << " Request the TGT_RSP FSM to return data:" - << " rsrcid = " << std::hex << r_xram_rsp_trt_buf.srcid - << " / address = " << std::hex << r_xram_rsp_trt_buf.nline*m_words*4 - << " / nwords = " << std::dec << r_xram_rsp_trt_buf.read_length << std::endl; -#endif - } - break; - } - //////////////////// + std::cout << " " + << " Request the TGT_RSP FSM to return data:" + << " rsrcid = " << std::hex << r_xram_rsp_trt_buf.srcid + << " / address = " << std::hex << r_xram_rsp_trt_buf.nline * m_words * 4 + << " / nwords = " << std::dec << r_xram_rsp_trt_buf.read_length << std::endl; + } +#endif + } + break; + } + //////////////////// case XRAM_RSP_INVAL: // send invalidate request to CC_SEND FSM - { - if (!r_xram_rsp_to_cc_send_multi_req.read() and - !r_xram_rsp_to_cc_send_brdcast_req.read()) - { - bool multi_req = !r_xram_rsp_victim_is_cnt.read(); - bool last_multi_req = multi_req and (r_xram_rsp_victim_count.read() == 1); - bool not_last_multi_req = multi_req and (r_xram_rsp_victim_count.read() != 1); - - r_xram_rsp_to_cc_send_multi_req = last_multi_req; - r_xram_rsp_to_cc_send_brdcast_req = r_xram_rsp_victim_is_cnt.read(); - r_xram_rsp_to_cc_send_nline = r_xram_rsp_victim_nline.read(); - r_xram_rsp_to_cc_send_trdid = r_xram_rsp_ivt_index; - xram_rsp_to_cc_send_fifo_srcid = r_xram_rsp_victim_copy.read(); - xram_rsp_to_cc_send_fifo_inst = r_xram_rsp_victim_copy_inst.read(); - xram_rsp_to_cc_send_fifo_put = multi_req; - r_xram_rsp_next_ptr = r_xram_rsp_victim_ptr.read(); - - if (r_xram_rsp_victim_dirty) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; - else if (not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ; - else r_xram_rsp_fsm = XRAM_RSP_IDLE; - -#if DEBUG_MEMC_XRAM_RSP - if (m_debug) - std::cout << " " - << " Send an inval request to CC_SEND FSM" - << " / address = " << r_xram_rsp_victim_nline.read()*m_words*4 << std::endl; -#endif - } - break; - } - ////////////////////////// - case XRAM_RSP_WRITE_DIRTY: // send a write request to IXR_CMD FSM - { - if (not r_xram_rsp_to_ixr_cmd_req.read()) - { - r_xram_rsp_to_ixr_cmd_req = true; - r_xram_rsp_to_ixr_cmd_index = r_xram_rsp_trt_index.read(); - - m_cpt_write_dirty++; - - bool multi_req = not r_xram_rsp_victim_is_cnt.read() and - r_xram_rsp_victim_inval.read(); - bool not_last_multi_req = multi_req and (r_xram_rsp_victim_count.read() != 1); - - if (not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ; - else r_xram_rsp_fsm = XRAM_RSP_IDLE; - -#if DEBUG_MEMC_XRAM_RSP - if (m_debug) - std::cout << " " - << " Send the put request to IXR_CMD FSM" - << " / address = " << r_xram_rsp_victim_nline.read()*m_words*4 << std::endl; -#endif - } - break; - } - ///////////////////////// - case XRAM_RSP_HEAP_REQ: // Get the lock to the HEAP - { - if (r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP) - { - r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE; - } + { + if (!r_xram_rsp_to_cc_send_multi_req.read() and + !r_xram_rsp_to_cc_send_brdcast_req.read()) + { + bool multi_req = !r_xram_rsp_victim_is_cnt.read(); + bool last_multi_req = multi_req and (r_xram_rsp_victim_count.read() == 1); + bool not_last_multi_req = multi_req and (r_xram_rsp_victim_count.read() != 1); + + r_xram_rsp_to_cc_send_multi_req = last_multi_req; + r_xram_rsp_to_cc_send_brdcast_req = r_xram_rsp_victim_is_cnt.read(); + r_xram_rsp_to_cc_send_nline = r_xram_rsp_victim_nline.read(); + r_xram_rsp_to_cc_send_trdid = r_xram_rsp_ivt_index; + xram_rsp_to_cc_send_fifo_srcid = r_xram_rsp_victim_copy.read(); + xram_rsp_to_cc_send_fifo_inst = r_xram_rsp_victim_copy_inst.read(); + xram_rsp_to_cc_send_fifo_put = multi_req; + r_xram_rsp_next_ptr = r_xram_rsp_victim_ptr.read(); + + if (r_xram_rsp_victim_dirty) r_xram_rsp_fsm = XRAM_RSP_WRITE_DIRTY; + else if (not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ; + else r_xram_rsp_fsm = XRAM_RSP_IDLE; #if DEBUG_MEMC_XRAM_RSP if (m_debug) - std::cout << " " - << " Requesting HEAP lock" << std::endl; -#endif - break; - } - ///////////////////////// + { + std::cout << " " + << " Send an inval request to CC_SEND FSM" + << " / address = " << r_xram_rsp_victim_nline.read()*m_words*4 << std::endl; + } +#endif + } + break; + } + ////////////////////////// + case XRAM_RSP_WRITE_DIRTY: // send a write request to IXR_CMD FSM + { + if (not r_xram_rsp_to_ixr_cmd_req.read()) + { + r_xram_rsp_to_ixr_cmd_req = true; + r_xram_rsp_to_ixr_cmd_index = r_xram_rsp_trt_index.read(); + + m_cpt_write_dirty++; + + bool multi_req = not r_xram_rsp_victim_is_cnt.read() and + r_xram_rsp_victim_inval.read(); + bool not_last_multi_req = multi_req and (r_xram_rsp_victim_count.read() != 1); + + if (not_last_multi_req) r_xram_rsp_fsm = XRAM_RSP_HEAP_REQ; + else r_xram_rsp_fsm = XRAM_RSP_IDLE; + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + { + std::cout << " " + << " Send the put request to IXR_CMD FSM" + << " / address = " << r_xram_rsp_victim_nline.read() * m_words * 4 << std::endl; + } +#endif + } + break; + } + ///////////////////////// + case XRAM_RSP_HEAP_REQ: // Get the lock to the HEAP + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP) + { + r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE; + } + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + { + std::cout << " " + << " Requesting HEAP lock" << std::endl; + } +#endif + break; + } + ///////////////////////// case XRAM_RSP_HEAP_ERASE: // erase the copies and send invalidations - { - if (r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP) - { - HeapEntry entry = m_heap.read(r_xram_rsp_next_ptr.read()); - - xram_rsp_to_cc_send_fifo_srcid = entry.owner.srcid; - xram_rsp_to_cc_send_fifo_inst = entry.owner.inst; - xram_rsp_to_cc_send_fifo_put = true; - if (m_xram_rsp_to_cc_send_inst_fifo.wok()) + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_XRAM_RSP) + { + HeapEntry entry = m_heap.read(r_xram_rsp_next_ptr.read()); + + xram_rsp_to_cc_send_fifo_srcid = entry.owner.srcid; + xram_rsp_to_cc_send_fifo_inst = entry.owner.inst; + xram_rsp_to_cc_send_fifo_put = true; + if (m_xram_rsp_to_cc_send_inst_fifo.wok()) + { + r_xram_rsp_next_ptr = entry.next; + if (entry.next == r_xram_rsp_next_ptr.read()) // last copy { - r_xram_rsp_next_ptr = entry.next; - if (entry.next == r_xram_rsp_next_ptr.read()) // last copy - { - r_xram_rsp_to_cc_send_multi_req = true; - r_xram_rsp_fsm = XRAM_RSP_HEAP_LAST; - } - else - { - r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE; - } + r_xram_rsp_to_cc_send_multi_req = true; + r_xram_rsp_fsm = XRAM_RSP_HEAP_LAST; } else @@ -4935,41 +5129,130 @@ r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE; } + } + else + { + r_xram_rsp_fsm = XRAM_RSP_HEAP_ERASE; + } + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + { + std::cout << " " + << " Erase copy:" + << " srcid = " << std::hex << entry.owner.srcid + << " / inst = " << std::dec << entry.owner.inst << std::endl; + } +#endif + } + break; + } + ///////////////////////// + case XRAM_RSP_HEAP_LAST: // last copy + { + if (r_alloc_heap_fsm.read() != ALLOC_HEAP_XRAM_RSP) + { + std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_HEAP_LAST" + << " bad HEAP allocation" << std::endl; + exit(0); + } + size_t free_pointer = m_heap.next_free_ptr(); + + HeapEntry last_entry; + last_entry.owner.srcid = 0; + last_entry.owner.inst = false; + if (m_heap.is_full()) + { + last_entry.next = r_xram_rsp_next_ptr.read(); + m_heap.unset_full(); + } + else + { + last_entry.next = free_pointer; + } + + m_heap.write_free_ptr(r_xram_rsp_victim_ptr.read()); + m_heap.write(r_xram_rsp_next_ptr.read(),last_entry); + + r_xram_rsp_fsm = XRAM_RSP_IDLE; + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + { + std::cout << " " + << " Heap housekeeping" << std::endl; + } +#endif + break; + } + ////////////////////////// + case XRAM_RSP_ERROR_ERASE: // erase TRT entry in case of error + { + m_trt.erase(r_xram_rsp_trt_index.read()); + + // Next state + if (r_xram_rsp_trt_buf.proc_read) + { + r_xram_rsp_fsm = XRAM_RSP_ERROR_RSP; + } + else + { + // Trigger an interruption to signal a bus error from + // the XRAM because a processor WRITE MISS (XRAM GET + // transaction and not processor read). + // + // To avoid deadlocks we do not wait an error to be + // acknowledged before signaling another one. + // Therefore, when there is an active error, and other + // errors arrive, these are not considered + + if (!r_xram_rsp_rerror_irq.read() && r_xram_rsp_rerror_irq_enable.read() + && r_xram_rsp_trt_buf.xram_read) + { + r_xram_rsp_rerror_irq = true; + r_xram_rsp_rerror_address = r_xram_rsp_trt_buf.nline * m_words * 4; + r_xram_rsp_rerror_rsrcid = r_xram_rsp_trt_buf.srcid; #if DEBUG_MEMC_XRAM_RSP if (m_debug) - std::cout << " " - << " Erase copy:" - << " srcid = " << std::hex << entry.owner.srcid - << " / inst = " << std::dec << entry.owner.inst << std::endl; -#endif - } - break; - } - ///////////////////////// - case XRAM_RSP_HEAP_LAST: // last copy - { - if (r_alloc_heap_fsm.read() != ALLOC_HEAP_XRAM_RSP) - { - std::cout << "VCI_MEM_CACHE ERROR " << name() << " XRAM_RSP_HEAP_LAST" - << " bad HEAP allocation" << std::endl; - exit(0); - } - size_t free_pointer = m_heap.next_free_ptr(); - - HeapEntry last_entry; - last_entry.owner.srcid = 0; - last_entry.owner.inst = false; - if (m_heap.is_full()) - { - last_entry.next = r_xram_rsp_next_ptr.read(); - m_heap.unset_full(); - } - else - { - last_entry.next = free_pointer; - } - - m_heap.write_free_ptr(r_xram_rsp_victim_ptr.read()); - m_heap.write(r_xram_rsp_next_ptr.read(),last_entry); + { + std::cout + << " " + << " Triggering interrupt to signal WRITE MISS bus error" + << " / irq_enable = " << r_xram_rsp_rerror_irq_enable.read() + << " / nline = " << r_xram_rsp_trt_buf.nline + << " / rsrcid = " << r_xram_rsp_trt_buf.srcid + << std::endl; + } +#endif + } + + r_xram_rsp_fsm = XRAM_RSP_IDLE; + } + +#if DEBUG_MEMC_XRAM_RSP + if (m_debug) + { + std::cout << " " + << " Error reported by XRAM / erase the TRT entry" << std::endl; + } +#endif + break; + } + //////////////////////// + case XRAM_RSP_ERROR_RSP: // Request an error response to TGT_RSP FSM + { + if (!r_xram_rsp_to_tgt_rsp_req.read()) + { + r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid; + r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid; + r_xram_rsp_to_tgt_rsp_pktid = r_xram_rsp_trt_buf.pktid; + for (size_t i = 0; i < m_words; i++) + { + r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i]; + } + r_xram_rsp_to_tgt_rsp_word = r_xram_rsp_trt_buf.word_index; + r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length; + r_xram_rsp_to_tgt_rsp_rerror = true; + r_xram_rsp_to_tgt_rsp_req = true; r_xram_rsp_fsm = XRAM_RSP_IDLE; @@ -4977,87 +5260,13 @@ #if DEBUG_MEMC_XRAM_RSP if (m_debug) - std::cout << " " - << " Heap housekeeping" << std::endl; -#endif - break; - } - ////////////////////////// - case XRAM_RSP_ERROR_ERASE: // erase TRT entry in case of error - { - m_trt.erase(r_xram_rsp_trt_index.read()); - - // Next state - if (r_xram_rsp_trt_buf.proc_read) - { - r_xram_rsp_fsm = XRAM_RSP_ERROR_RSP; - } - else - { - // Trigger an interruption to signal a bus error from - // the XRAM because a processor WRITE MISS (XRAM GET - // transaction and not processor read). - // - // To avoid deadlocks we do not wait an error to be - // acknowledged before signaling another one. - // Therefore, when there is an active error, and other - // errors arrive, these are not considered - - if (!r_xram_rsp_rerror_irq.read() && r_xram_rsp_rerror_irq_enable.read() - && r_xram_rsp_trt_buf.xram_read ) - { - r_xram_rsp_rerror_irq = true; - r_xram_rsp_rerror_address = r_xram_rsp_trt_buf.nline * m_words * 4; - r_xram_rsp_rerror_rsrcid = r_xram_rsp_trt_buf.srcid; - -#if DEBUG_MEMC_XRAM_RSP - if (m_debug) - std::cout - << " " - << " Triggering interrupt to signal WRITE MISS bus error" - << " / irq_enable = " << r_xram_rsp_rerror_irq_enable.read() - << " / nline = " << r_xram_rsp_trt_buf.nline - << " / rsrcid = " << r_xram_rsp_trt_buf.srcid - << std::endl; -#endif - } - - r_xram_rsp_fsm = XRAM_RSP_IDLE; - } - -#if DEBUG_MEMC_XRAM_RSP - if (m_debug) - std::cout << " " - << " Error reported by XRAM / erase the TRT entry" << std::endl; -#endif - break; - } - //////////////////////// - case XRAM_RSP_ERROR_RSP: // Request an error response to TGT_RSP FSM - { - if (!r_xram_rsp_to_tgt_rsp_req.read()) - { - r_xram_rsp_to_tgt_rsp_srcid = r_xram_rsp_trt_buf.srcid; - r_xram_rsp_to_tgt_rsp_trdid = r_xram_rsp_trt_buf.trdid; - r_xram_rsp_to_tgt_rsp_pktid = r_xram_rsp_trt_buf.pktid; - for(size_t i=0; i < m_words; i++) - { - r_xram_rsp_to_tgt_rsp_data[i] = r_xram_rsp_trt_buf.wdata[i]; - } - r_xram_rsp_to_tgt_rsp_word = r_xram_rsp_trt_buf.word_index; - r_xram_rsp_to_tgt_rsp_length = r_xram_rsp_trt_buf.read_length; - r_xram_rsp_to_tgt_rsp_rerror = true; - r_xram_rsp_to_tgt_rsp_req = true; - - r_xram_rsp_fsm = XRAM_RSP_IDLE; - -#if DEBUG_MEMC_XRAM_RSP - if (m_debug) - std::cout << " Request a response error to TGT_RSP FSM:" - << " srcid = " << std::dec << r_xram_rsp_trt_buf.srcid << std::endl; -#endif - } - break; - } + { + std::cout << " Request a response error to TGT_RSP FSM:" + << " srcid = " << std::dec << r_xram_rsp_trt_buf.srcid << std::endl; + } +#endif + } + break; + } } // end swich r_xram_rsp_fsm @@ -5073,540 +5282,570 @@ ////////////////// case CLEANUP_IDLE: // Get first DSPIN flit of the CLEANUP command - { - if (not m_cc_receive_to_cleanup_fifo.rok()) break; - - uint64_t flit = m_cc_receive_to_cleanup_fifo.read(); - - uint32_t srcid = DspinDhccpParam::dspin_get(flit, - DspinDhccpParam::CLEANUP_SRCID); - - uint8_t type = DspinDhccpParam::dspin_get(flit, - DspinDhccpParam::P2M_TYPE); - - r_cleanup_way_index = DspinDhccpParam::dspin_get(flit, - DspinDhccpParam::CLEANUP_WAY_INDEX); - - r_cleanup_nline = DspinDhccpParam::dspin_get(flit, - DspinDhccpParam::CLEANUP_NLINE_MSB) << 32; - - r_cleanup_inst = (type == DspinDhccpParam::TYPE_CLEANUP_INST); - r_cleanup_srcid = srcid; - - assert((srcid < m_initiators) and - "MEMC ERROR in CLEANUP_IDLE state : illegal SRCID value"); - - cc_receive_to_cleanup_fifo_get = true; - r_cleanup_fsm = CLEANUP_GET_NLINE; + { + if (not m_cc_receive_to_cleanup_fifo.rok()) break; + + uint64_t flit = m_cc_receive_to_cleanup_fifo.read(); + + uint32_t srcid = DspinDhccpParam::dspin_get(flit, + DspinDhccpParam::CLEANUP_SRCID); + + uint8_t type = DspinDhccpParam::dspin_get(flit, + DspinDhccpParam::P2M_TYPE); + + r_cleanup_way_index = DspinDhccpParam::dspin_get(flit, + DspinDhccpParam::CLEANUP_WAY_INDEX); + + r_cleanup_nline = DspinDhccpParam::dspin_get(flit, + DspinDhccpParam::CLEANUP_NLINE_MSB) << 32; + + r_cleanup_inst = (type == DspinDhccpParam::TYPE_CLEANUP_INST); + r_cleanup_srcid = srcid; + + assert((srcid < m_initiators) and + "MEMC ERROR in CLEANUP_IDLE state : illegal SRCID value"); + + cc_receive_to_cleanup_fifo_get = true; + r_cleanup_fsm = CLEANUP_GET_NLINE; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + { + std::cout << " Cleanup request:" << std::hex + << " owner_id = " << srcid + << " / owner_ins = " << (type == DspinDhccpParam::TYPE_CLEANUP_INST) << std::endl; + } +#endif + break; + } + /////////////////////// + case CLEANUP_GET_NLINE: // GET second DSPIN flit of the cleanup command + { + if (not m_cc_receive_to_cleanup_fifo.rok()) break; + + uint64_t flit = m_cc_receive_to_cleanup_fifo.read(); + + addr_t nline = r_cleanup_nline.read() | + DspinDhccpParam::dspin_get(flit, DspinDhccpParam::CLEANUP_NLINE_LSB); + + cc_receive_to_cleanup_fifo_get = true; + r_cleanup_nline = nline; + r_cleanup_fsm = CLEANUP_DIR_REQ; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + { + std::cout << " Cleanup request:" + << " address = " << std::hex << nline * m_words * 4 << std::endl; + } +#endif + break; + } + ///////////////////// + case CLEANUP_DIR_REQ: // Get the lock to the directory + { + if (r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP) break; + + r_cleanup_fsm = CLEANUP_DIR_LOCK; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + { + std::cout << " Requesting DIR lock" << std::endl; + } +#endif + break; + } + ////////////////////// + case CLEANUP_DIR_LOCK: // test directory status + { + assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CLEANUP) and + "MEMC ERROR in CLEANUP_DIR_LOCK: bad DIR allocation"); + + // Read the directory + size_t way = 0; + addr_t cleanup_address = r_cleanup_nline.read() * m_words * 4; + DirectoryEntry entry = m_cache_directory.read(cleanup_address , way); + r_cleanup_is_cnt = entry.is_cnt; + r_cleanup_dirty = entry.dirty; + r_cleanup_tag = entry.tag; + r_cleanup_lock = entry.lock; + r_cleanup_way = way; + r_cleanup_count = entry.count; + r_cleanup_ptr = entry.ptr; + r_cleanup_copy = entry.owner.srcid; + r_cleanup_copy_inst = entry.owner.inst; + + if (entry.valid) // hit : the copy must be cleared + { + assert((entry.count > 0) and + "MEMC ERROR in CLEANUP_DIR_LOCK state, CLEANUP on valid entry with no copies"); + + if ((entry.count == 1) or (entry.is_cnt)) // no access to the heap + { + r_cleanup_fsm = CLEANUP_DIR_WRITE; + } + else // access to the heap + { + r_cleanup_fsm = CLEANUP_HEAP_REQ; + } + } + else // miss : check IVT for a pending inval + { + r_cleanup_fsm = CLEANUP_IVT_LOCK; + } + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + { + std::cout << " Test directory status: " + << std::hex << " address = " << cleanup_address + << " / hit = " << entry.valid + << " / dir_id = " << entry.owner.srcid + << " / dir_ins = " << entry.owner.inst + << " / search_id = " << r_cleanup_srcid.read() + << " / search_ins = " << r_cleanup_inst.read() + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt << std::endl; + } +#endif + break; + } + /////////////////////// + case CLEANUP_DIR_WRITE: // Update the directory entry without heap access + { + assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CLEANUP) and + "MEMC ERROR in CLEANUP_DIR_LOCK: bad DIR allocation"); + + size_t way = r_cleanup_way.read(); + size_t set = m_y[(addr_t) (r_cleanup_nline.read() * m_words * 4)]; + bool match_srcid = (r_cleanup_copy.read() == r_cleanup_srcid.read()); + bool match_inst = (r_cleanup_copy_inst.read() == r_cleanup_inst.read()); + bool match = match_srcid and match_inst; + + assert((r_cleanup_is_cnt.read() or match) and + "MEMC ERROR in CLEANUP_DIR_LOCK: illegal CLEANUP on valid entry"); + + // update the cache directory (for the copies) + DirectoryEntry entry; + entry.valid = true; + entry.is_cnt = r_cleanup_is_cnt.read(); + entry.dirty = r_cleanup_dirty.read(); + entry.tag = r_cleanup_tag.read(); + entry.lock = r_cleanup_lock.read(); + entry.ptr = r_cleanup_ptr.read(); + entry.count = r_cleanup_count.read() - 1; + entry.owner.srcid = 0; + entry.owner.inst = 0; + + m_cache_directory.write(set, way, entry); + + r_cleanup_fsm = CLEANUP_SEND_CLACK; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + { + std::cout << " Update directory:" + << std::hex << " address = " << r_cleanup_nline.read() * m_words * 4 + << " / dir_id = " << entry.owner.srcid + << " / dir_ins = " << entry.owner.inst + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt << std::endl; + } +#endif + + break; + } + ////////////////////// + case CLEANUP_HEAP_REQ: // get the lock to the HEAP directory + { + if (r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP) break; + + r_cleanup_fsm = CLEANUP_HEAP_LOCK; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + { + std::cout << " HEAP lock acquired " << std::endl; + } +#endif + break; + } + ////////////////////// + case CLEANUP_HEAP_LOCK: // two cases are handled in this state : + // 1. the matching copy is directly in the directory + // 2. the matching copy is the first copy in the heap + { + assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and + "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation"); + + size_t way = r_cleanup_way.read(); + size_t set = m_y[(addr_t)(r_cleanup_nline.read() * m_words * 4)]; + + HeapEntry heap_entry = m_heap.read(r_cleanup_ptr.read()); + bool last = (heap_entry.next == r_cleanup_ptr.read()); + + // match_dir computation + bool match_dir_srcid = (r_cleanup_copy.read() == r_cleanup_srcid.read()); + bool match_dir_inst = (r_cleanup_copy_inst.read() == r_cleanup_inst.read()); + bool match_dir = match_dir_srcid and match_dir_inst; + + // match_heap computation + bool match_heap_srcid = (heap_entry.owner.srcid == r_cleanup_srcid.read()); + bool match_heap_inst = (heap_entry.owner.inst == r_cleanup_inst.read()); + bool match_heap = match_heap_srcid and match_heap_inst; + + r_cleanup_prev_ptr = r_cleanup_ptr.read(); + r_cleanup_prev_srcid = heap_entry.owner.srcid; + r_cleanup_prev_inst = heap_entry.owner.inst; + + assert((not last or match_dir or match_heap) and + "MEMC ERROR in CLEANUP_HEAP_LOCK state: hit but no copy found"); + + assert((not match_dir or not match_heap) and + "MEMC ERROR in CLEANUP_HEAP_LOCK state: two matching copies found"); + + DirectoryEntry dir_entry; + dir_entry.valid = true; + dir_entry.is_cnt = r_cleanup_is_cnt.read(); + dir_entry.dirty = r_cleanup_dirty.read(); + dir_entry.tag = r_cleanup_tag.read(); + dir_entry.lock = r_cleanup_lock.read(); + dir_entry.count = r_cleanup_count.read() - 1; + + // the matching copy is registered in the directory and + // it must be replaced by the first copy registered in + // the heap. The corresponding entry must be freed + if (match_dir) + { + dir_entry.ptr = heap_entry.next; + dir_entry.owner.srcid = heap_entry.owner.srcid; + dir_entry.owner.inst = heap_entry.owner.inst; + r_cleanup_next_ptr = r_cleanup_ptr.read(); + r_cleanup_fsm = CLEANUP_HEAP_FREE; + } + + // the matching copy is the first copy in the heap + // It must be freed and the copy registered in directory + // must point to the next copy in heap + else if (match_heap) + { + dir_entry.ptr = heap_entry.next; + dir_entry.owner.srcid = r_cleanup_copy.read(); + dir_entry.owner.inst = r_cleanup_copy_inst.read(); + r_cleanup_next_ptr = r_cleanup_ptr.read(); + r_cleanup_fsm = CLEANUP_HEAP_FREE; + } + + // The matching copy is in the heap, but is not the first copy + // The directory entry must be modified to decrement count + else + { + dir_entry.ptr = r_cleanup_ptr.read(); + dir_entry.owner.srcid = r_cleanup_copy.read(); + dir_entry.owner.inst = r_cleanup_copy_inst.read(); + r_cleanup_next_ptr = heap_entry.next; + r_cleanup_fsm = CLEANUP_HEAP_SEARCH; + } + + m_cache_directory.write(set,way,dir_entry); + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + { + std::cout << " Checks matching:" + << " address = " << r_cleanup_nline.read() * m_words * 4 + << " / dir_id = " << r_cleanup_copy.read() + << " / dir_ins = " << r_cleanup_copy_inst.read() + << " / heap_id = " << heap_entry.owner.srcid + << " / heap_ins = " << heap_entry.owner.inst + << " / search_id = " << r_cleanup_srcid.read() + << " / search_ins = " << r_cleanup_inst.read() << std::endl; + } +#endif + break; + } + //////////////////////// + case CLEANUP_HEAP_SEARCH: // This state is handling the case where the copy + // is in the heap, but not the first in linked list + { + assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and + "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation"); + + HeapEntry heap_entry = m_heap.read(r_cleanup_next_ptr.read()); + + bool last = (heap_entry.next == r_cleanup_next_ptr.read()); + bool match_heap_srcid = (heap_entry.owner.srcid == r_cleanup_srcid.read()); + bool match_heap_inst = (heap_entry.owner.inst == r_cleanup_inst.read()); + bool match_heap = match_heap_srcid and match_heap_inst; + + assert((not last or match_heap) and + "MEMC ERROR in CLEANUP_HEAP_SEARCH state: no copy found"); + + // the matching copy must be removed + if (match_heap) + { + // re-use ressources + r_cleanup_ptr = heap_entry.next; + r_cleanup_fsm = CLEANUP_HEAP_CLEAN; + } + // test the next in the linked list + else + { + r_cleanup_prev_ptr = r_cleanup_next_ptr.read(); + r_cleanup_prev_srcid = heap_entry.owner.srcid; + r_cleanup_prev_inst = heap_entry.owner.inst; + r_cleanup_next_ptr = heap_entry.next; + r_cleanup_fsm = CLEANUP_HEAP_SEARCH; + } + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + { + if (not match_heap) + { + std::cout + << " Matching copy not found, search next:" + << std::endl; + } + else + { + std::cout + << " Matching copy found:" + << std::endl; + } + std::cout + << " address = " << r_cleanup_nline.read() * m_words * 4 + << " / heap_id = " << heap_entry.owner.srcid + << " / heap_ins = " << heap_entry.owner.inst + << " / search_id = " << r_cleanup_srcid.read() + << " / search_ins = " << r_cleanup_inst.read() + << " / last = " << last + << std::endl; + } +#endif + break; + } + //////////////////////// + case CLEANUP_HEAP_CLEAN: // remove a copy in the linked list + { + assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and + "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation"); + + HeapEntry heap_entry; + heap_entry.owner.srcid = r_cleanup_prev_srcid.read(); + heap_entry.owner.inst = r_cleanup_prev_inst.read(); + bool last = (r_cleanup_next_ptr.read() == r_cleanup_ptr.read()); + + if (last) // this is the last entry of the list of copies + { + heap_entry.next = r_cleanup_prev_ptr.read(); + } + else // this is not the last entry + { + heap_entry.next = r_cleanup_ptr.read(); + } + + m_heap.write(r_cleanup_prev_ptr.read(), heap_entry); + + r_cleanup_fsm = CLEANUP_HEAP_FREE; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + { + std::cout << " " + << " Remove the copy in the linked list" << std::endl; + } +#endif + break; + } + /////////////////////// + case CLEANUP_HEAP_FREE: // The heap entry pointed by r_cleanup_next_ptr is freed + // and becomes the head of the list of free entries + { + assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and + "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation"); + + HeapEntry heap_entry; + heap_entry.owner.srcid = 0; + heap_entry.owner.inst = false; + + if (m_heap.is_full()) + { + heap_entry.next = r_cleanup_next_ptr.read(); + } + else + { + heap_entry.next = m_heap.next_free_ptr(); + } + + m_heap.write(r_cleanup_next_ptr.read(),heap_entry); + m_heap.write_free_ptr(r_cleanup_next_ptr.read()); + m_heap.unset_full(); + + r_cleanup_fsm = CLEANUP_SEND_CLACK; + +#if DEBUG_MEMC_CLEANUP + if (m_debug) + { + std::cout << " " + << " Update the list of free entries" << std::endl; + } +#endif + break; + } + ////////////////////// + case CLEANUP_IVT_LOCK: // get the lock protecting the IVT to search a pending + // invalidate transaction matching the cleanup + { + if (r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) break; + + size_t index = 0; + bool match_inval; + + match_inval = m_ivt.search_inval(r_cleanup_nline.read(), index); + + if (not match_inval) // no pending inval in IVT + { + r_cleanup_fsm = CLEANUP_SEND_CLACK; #if DEBUG_MEMC_CLEANUP if (m_debug) - std::cout << " Cleanup request:" << std::hex - << " owner_id = " << srcid - << " / owner_ins = " << (type == DspinDhccpParam::TYPE_CLEANUP_INST) << std::endl; -#endif - break; - } - /////////////////////// - case CLEANUP_GET_NLINE: // GET second DSPIN flit of the cleanup command - { - if (not m_cc_receive_to_cleanup_fifo.rok()) break; - - uint64_t flit = m_cc_receive_to_cleanup_fifo.read(); - - addr_t nline = r_cleanup_nline.read() | - DspinDhccpParam::dspin_get(flit, DspinDhccpParam::CLEANUP_NLINE_LSB); - - cc_receive_to_cleanup_fifo_get = true; - r_cleanup_nline = nline; - r_cleanup_fsm = CLEANUP_DIR_REQ; + { + std::cout << " " + << " Unexpected cleanup with no corresponding IVT entry:" + << " address = " << std::hex << (r_cleanup_nline.read() * 4 * m_words) << std::endl; + } +#endif + } + else // pending inval in IVT + { + r_cleanup_write_srcid = m_ivt.srcid(index); + r_cleanup_write_trdid = m_ivt.trdid(index); + r_cleanup_write_pktid = m_ivt.pktid(index); + r_cleanup_need_rsp = m_ivt.need_rsp(index); + r_cleanup_need_ack = m_ivt.need_ack(index); + r_cleanup_index = index; + r_cleanup_fsm = CLEANUP_IVT_DECREMENT; #if DEBUG_MEMC_CLEANUP if (m_debug) - std::cout << " Cleanup request:" - << " address = " << std::hex << nline * m_words * 4 << std::endl; -#endif - break; - } - ///////////////////// - case CLEANUP_DIR_REQ: // Get the lock to the directory - { - if (r_alloc_dir_fsm.read() != ALLOC_DIR_CLEANUP) break; - - r_cleanup_fsm = CLEANUP_DIR_LOCK; + { + std::cout << " " + << " Cleanup matching pending invalidate transaction on IVT:" + << " address = " << std::hex << (r_cleanup_nline.read() * m_words * 4) + << " / ivt_entry = " << index << std::endl; + } +#endif + } + break; + } + /////////////////////////// + case CLEANUP_IVT_DECREMENT: // decrement response counter in IVT matching entry + // and test if last + { + assert((r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP) and + "MEMC ERROR in CLEANUP_IVT_DECREMENT state: Bad IVT allocation"); + + size_t count = 0; + m_ivt.decrement(r_cleanup_index.read(), count); + + if (count == 0) r_cleanup_fsm = CLEANUP_IVT_CLEAR; + else r_cleanup_fsm = CLEANUP_SEND_CLACK ; #if DEBUG_MEMC_CLEANUP - if (m_debug) - std::cout << " Requesting DIR lock" << std::endl; -#endif - break; - } - ////////////////////// - case CLEANUP_DIR_LOCK: // test directory status - { - assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CLEANUP) and - "MEMC ERROR in CLEANUP_DIR_LOCK: bad DIR allocation"); - - // Read the directory - size_t way = 0; - addr_t cleanup_address = r_cleanup_nline.read() * m_words * 4; - DirectoryEntry entry = m_cache_directory.read(cleanup_address , way); - r_cleanup_is_cnt = entry.is_cnt; - r_cleanup_dirty = entry.dirty; - r_cleanup_tag = entry.tag; - r_cleanup_lock = entry.lock; - r_cleanup_way = way; - r_cleanup_count = entry.count; - r_cleanup_ptr = entry.ptr; - r_cleanup_copy = entry.owner.srcid; - r_cleanup_copy_inst = entry.owner.inst; - - if (entry.valid) // hit : the copy must be cleared - { - assert( (entry.count > 0) and - "MEMC ERROR in CLEANUP_DIR_LOCK state, CLEANUP on valid entry with no copies"); - - if ((entry.count == 1) or (entry.is_cnt)) // no access to the heap - { - r_cleanup_fsm = CLEANUP_DIR_WRITE; - } - else // access to the heap - { - r_cleanup_fsm = CLEANUP_HEAP_REQ; - } - } - else // miss : check IVT for a pending inval - { - r_cleanup_fsm = CLEANUP_IVT_LOCK; - } + if (m_debug) + { + std::cout << " " + << " Decrement response counter in IVT:" + << " IVT_index = " << r_cleanup_index.read() + << " / rsp_count = " << count << std::endl; + } +#endif + break; + } + /////////////////////// + case CLEANUP_IVT_CLEAR: // Clear IVT entry + // Acknowledge CONFIG FSM if required + { + assert((r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP) and + "MEMC ERROR in CLEANUP_IVT_CLEAR state : bad IVT allocation"); + + m_ivt.clear(r_cleanup_index.read()); + + if (r_cleanup_need_ack.read()) + { + assert((r_config_rsp_lines.read() > 0) and + "MEMC ERROR in CLEANUP_IVT_CLEAR state"); + + config_rsp_lines_cleanup_decr = true; + } + + if (r_cleanup_need_rsp.read()) r_cleanup_fsm = CLEANUP_WRITE_RSP; + else r_cleanup_fsm = CLEANUP_SEND_CLACK; #if DEBUG_MEMC_CLEANUP - if (m_debug) - std::cout << " Test directory status: " - << std::hex << " address = " << cleanup_address - << " / hit = " << entry.valid - << " / dir_id = " << entry.owner.srcid - << " / dir_ins = " << entry.owner.inst - << " / search_id = " << r_cleanup_srcid.read() - << " / search_ins = " << r_cleanup_inst.read() - << " / count = " << entry.count - << " / is_cnt = " << entry.is_cnt << std::endl; -#endif - break; - } - /////////////////////// - case CLEANUP_DIR_WRITE: // Update the directory entry without heap access - { - assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CLEANUP) and - "MEMC ERROR in CLEANUP_DIR_LOCK: bad DIR allocation"); - - size_t way = r_cleanup_way.read(); - size_t set = m_y[(addr_t)(r_cleanup_nline.read()*m_words*4)]; - bool match_srcid = (r_cleanup_copy.read() == r_cleanup_srcid.read()); - bool match_inst = (r_cleanup_copy_inst.read() == r_cleanup_inst.read()); - bool match = match_srcid and match_inst; - - assert( (r_cleanup_is_cnt.read() or match) and - "MEMC ERROR in CLEANUP_DIR_LOCK: illegal CLEANUP on valid entry"); - - // update the cache directory (for the copies) - DirectoryEntry entry; - entry.valid = true; - entry.is_cnt = r_cleanup_is_cnt.read(); - entry.dirty = r_cleanup_dirty.read(); - entry.tag = r_cleanup_tag.read(); - entry.lock = r_cleanup_lock.read(); - entry.ptr = r_cleanup_ptr.read(); - entry.count = r_cleanup_count.read() - 1; - entry.owner.srcid = 0; - entry.owner.inst = 0; - - m_cache_directory.write(set, way, entry); - - r_cleanup_fsm = CLEANUP_SEND_CLACK; + if (m_debug) + { + std::cout << " Clear entry in IVT:" + << " IVT_index = " << r_cleanup_index.read() << std::endl; + } +#endif + break; + } + /////////////////////// + case CLEANUP_WRITE_RSP: // response to a previous write on the direct network + // wait if pending request to the TGT_RSP FSM + { + if (r_cleanup_to_tgt_rsp_req.read()) break; + + // no pending request + r_cleanup_to_tgt_rsp_req = true; + r_cleanup_to_tgt_rsp_srcid = r_cleanup_write_srcid.read(); + r_cleanup_to_tgt_rsp_trdid = r_cleanup_write_trdid.read(); + r_cleanup_to_tgt_rsp_pktid = r_cleanup_write_pktid.read(); + r_cleanup_fsm = CLEANUP_SEND_CLACK; #if DEBUG_MEMC_CLEANUP - if (m_debug) - std::cout << " Update directory:" - << std::hex << " address = " << r_cleanup_nline.read() * m_words * 4 - << " / dir_id = " << entry.owner.srcid - << " / dir_ins = " << entry.owner.inst - << " / count = " << entry.count - << " / is_cnt = " << entry.is_cnt << std::endl; -#endif - - break; - } - ////////////////////// - case CLEANUP_HEAP_REQ: // get the lock to the HEAP directory - { - if (r_alloc_heap_fsm.read() != ALLOC_HEAP_CLEANUP) break; - - r_cleanup_fsm = CLEANUP_HEAP_LOCK; + if (m_debug) + { + std::cout << " " + << " Send a response to a previous write request: " + << " rsrcid = " << std::hex << r_cleanup_write_srcid.read() + << " / rtrdid = " << r_cleanup_write_trdid.read() + << " / rpktid = " << r_cleanup_write_pktid.read() << std::endl; + } +#endif + break; + } + //////////////////////// + case CLEANUP_SEND_CLACK: // acknowledgement to a cleanup command + // on the coherence CLACK network. + { + if (not p_dspin_clack.read) break; + + r_cleanup_fsm = CLEANUP_IDLE; #if DEBUG_MEMC_CLEANUP - if (m_debug) - std::cout << " HEAP lock acquired " << std::endl; -#endif - break; - } - ////////////////////// - case CLEANUP_HEAP_LOCK: // two cases are handled in this state : - // 1. the matching copy is directly in the directory - // 2. the matching copy is the first copy in the heap - { - assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and - "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation"); - - size_t way = r_cleanup_way.read(); - size_t set = m_y[(addr_t)(r_cleanup_nline.read() *m_words*4)]; - - HeapEntry heap_entry = m_heap.read(r_cleanup_ptr.read()); - bool last = (heap_entry.next == r_cleanup_ptr.read()); - - // match_dir computation - bool match_dir_srcid = (r_cleanup_copy.read() == r_cleanup_srcid.read()); - bool match_dir_inst = (r_cleanup_copy_inst.read() == r_cleanup_inst.read()); - bool match_dir = match_dir_srcid and match_dir_inst; - - // match_heap computation - bool match_heap_srcid = (heap_entry.owner.srcid == r_cleanup_srcid.read()); - bool match_heap_inst = (heap_entry.owner.inst == r_cleanup_inst.read()); - bool match_heap = match_heap_srcid and match_heap_inst; - - r_cleanup_prev_ptr = r_cleanup_ptr.read(); - r_cleanup_prev_srcid = heap_entry.owner.srcid; - r_cleanup_prev_inst = heap_entry.owner.inst; - - assert( (not last or match_dir or match_heap) and - "MEMC ERROR in CLEANUP_HEAP_LOCK state: hit but no copy found"); - - assert( (not match_dir or not match_heap) and - "MEMC ERROR in CLEANUP_HEAP_LOCK state: two matching copies found"); - - DirectoryEntry dir_entry; - dir_entry.valid = true; - dir_entry.is_cnt = r_cleanup_is_cnt.read(); - dir_entry.dirty = r_cleanup_dirty.read(); - dir_entry.tag = r_cleanup_tag.read(); - dir_entry.lock = r_cleanup_lock.read(); - dir_entry.count = r_cleanup_count.read()-1; - - // the matching copy is registered in the directory and - // it must be replaced by the first copy registered in - // the heap. The corresponding entry must be freed - if (match_dir) - { - dir_entry.ptr = heap_entry.next; - dir_entry.owner.srcid = heap_entry.owner.srcid; - dir_entry.owner.inst = heap_entry.owner.inst; - r_cleanup_next_ptr = r_cleanup_ptr.read(); - r_cleanup_fsm = CLEANUP_HEAP_FREE; - } - - // the matching copy is the first copy in the heap - // It must be freed and the copy registered in directory - // must point to the next copy in heap - else if (match_heap) - { - dir_entry.ptr = heap_entry.next; - dir_entry.owner.srcid = r_cleanup_copy.read(); - dir_entry.owner.inst = r_cleanup_copy_inst.read(); - r_cleanup_next_ptr = r_cleanup_ptr.read(); - r_cleanup_fsm = CLEANUP_HEAP_FREE; - } - - // The matching copy is in the heap, but is not the first copy - // The directory entry must be modified to decrement count - else - { - dir_entry.ptr = r_cleanup_ptr.read(); - dir_entry.owner.srcid = r_cleanup_copy.read(); - dir_entry.owner.inst = r_cleanup_copy_inst.read(); - r_cleanup_next_ptr = heap_entry.next; - r_cleanup_fsm = CLEANUP_HEAP_SEARCH; - } - - m_cache_directory.write(set,way,dir_entry); - -#if DEBUG_MEMC_CLEANUP - if (m_debug) - std::cout << " Checks matching:" - << " address = " << r_cleanup_nline.read() * m_words * 4 - << " / dir_id = " << r_cleanup_copy.read() - << " / dir_ins = " << r_cleanup_copy_inst.read() - << " / heap_id = " << heap_entry.owner.srcid - << " / heap_ins = " << heap_entry.owner.inst - << " / search_id = " << r_cleanup_srcid.read() - << " / search_ins = " << r_cleanup_inst.read() << std::endl; -#endif - break; - } - //////////////////////// - case CLEANUP_HEAP_SEARCH: // This state is handling the case where the copy - // is in the heap, but not the first in linked list - { - assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and - "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation"); - - HeapEntry heap_entry = m_heap.read(r_cleanup_next_ptr.read()); - - bool last = (heap_entry.next == r_cleanup_next_ptr.read()); - bool match_heap_srcid = (heap_entry.owner.srcid == r_cleanup_srcid.read()); - bool match_heap_inst = (heap_entry.owner.inst == r_cleanup_inst.read()); - bool match_heap = match_heap_srcid and match_heap_inst; - - assert( (not last or match_heap) and - "MEMC ERROR in CLEANUP_HEAP_SEARCH state: no copy found"); - - // the matching copy must be removed - if (match_heap) - { - // re-use ressources - r_cleanup_ptr = heap_entry.next; - r_cleanup_fsm = CLEANUP_HEAP_CLEAN; - } - // test the next in the linked list - else - { - r_cleanup_prev_ptr = r_cleanup_next_ptr.read(); - r_cleanup_prev_srcid = heap_entry.owner.srcid; - r_cleanup_prev_inst = heap_entry.owner.inst; - r_cleanup_next_ptr = heap_entry.next; - r_cleanup_fsm = CLEANUP_HEAP_SEARCH; - } - -#if DEBUG_MEMC_CLEANUP - if (m_debug) - { - if (not match_heap) - { - std::cout - << " Matching copy not found, search next:" - << std::endl; - } - else - { - std::cout - << " Matching copy found:" - << std::endl; - } - std::cout - << " address = " << r_cleanup_nline.read() * m_words * 4 - << " / heap_id = " << heap_entry.owner.srcid - << " / heap_ins = " << heap_entry.owner.inst - << " / search_id = " << r_cleanup_srcid.read() - << " / search_ins = " << r_cleanup_inst.read() - << " / last = " << last - << std::endl; - } -#endif - break; - } - //////////////////////// - case CLEANUP_HEAP_CLEAN: // remove a copy in the linked list - { - assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and - "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation"); - - HeapEntry heap_entry; - heap_entry.owner.srcid = r_cleanup_prev_srcid.read(); - heap_entry.owner.inst = r_cleanup_prev_inst.read(); - bool last = (r_cleanup_next_ptr.read() == r_cleanup_ptr.read()); - - if (last) // this is the last entry of the list of copies - { - heap_entry.next = r_cleanup_prev_ptr.read(); - } - else // this is not the last entry - { - heap_entry.next = r_cleanup_ptr.read(); - } - - m_heap.write(r_cleanup_prev_ptr.read(), heap_entry); - - r_cleanup_fsm = CLEANUP_HEAP_FREE; - -#if DEBUG_MEMC_CLEANUP - if (m_debug) - std::cout << " " - << " Remove the copy in the linked list" << std::endl; -#endif - break; - } - /////////////////////// - case CLEANUP_HEAP_FREE: // The heap entry pointed by r_cleanup_next_ptr is freed - // and becomes the head of the list of free entries - { - assert( (r_alloc_heap_fsm.read() == ALLOC_HEAP_CLEANUP) and - "MEMC ERROR in CLEANUP_HEAP_LOCK state: bad HEAP allocation"); - - HeapEntry heap_entry; - heap_entry.owner.srcid = 0; - heap_entry.owner.inst = false; - - if (m_heap.is_full()) - { - heap_entry.next = r_cleanup_next_ptr.read(); - } - else - { - heap_entry.next = m_heap.next_free_ptr(); - } - - m_heap.write(r_cleanup_next_ptr.read(),heap_entry); - m_heap.write_free_ptr(r_cleanup_next_ptr.read()); - m_heap.unset_full(); - - r_cleanup_fsm = CLEANUP_SEND_CLACK; - -#if DEBUG_MEMC_CLEANUP - if (m_debug) - std::cout << " " - << " Update the list of free entries" << std::endl; -#endif - break; - } - ////////////////////// - case CLEANUP_IVT_LOCK: // get the lock protecting the IVT to search a pending - // invalidate transaction matching the cleanup - { - if (r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) break; - - size_t index = 0; - bool match_inval; - - match_inval = m_ivt.search_inval(r_cleanup_nline.read(), index); - - if (not match_inval ) // no pending inval in IVT - { - r_cleanup_fsm = CLEANUP_SEND_CLACK; - -#if DEBUG_MEMC_CLEANUP - if (m_debug) - std::cout << " " - << " Unexpected cleanup with no corresponding IVT entry:" - << " address = " << std::hex << (r_cleanup_nline.read()*4*m_words) << std::endl; -#endif - } - else // pending inval in IVT - { - r_cleanup_write_srcid = m_ivt.srcid(index); - r_cleanup_write_trdid = m_ivt.trdid(index); - r_cleanup_write_pktid = m_ivt.pktid(index); - r_cleanup_need_rsp = m_ivt.need_rsp(index); - r_cleanup_need_ack = m_ivt.need_ack(index); - r_cleanup_index = index; - r_cleanup_fsm = CLEANUP_IVT_DECREMENT; - -#if DEBUG_MEMC_CLEANUP - if (m_debug) - std::cout << " " - << " Cleanup matching pending invalidate transaction on IVT:" - << " address = " << std::hex << (r_cleanup_nline.read()*m_words*4) - << " / ivt_entry = " << index << std::endl; -#endif - } - break; - } - /////////////////////////// - case CLEANUP_IVT_DECREMENT: // decrement response counter in IVT matching entry - // and test if last - { - assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP) and - "MEMC ERROR in CLEANUP_IVT_DECREMENT state: Bad IVT allocation"); - - size_t count = 0; - m_ivt.decrement(r_cleanup_index.read(), count); - - if (count == 0) r_cleanup_fsm = CLEANUP_IVT_CLEAR; - else r_cleanup_fsm = CLEANUP_SEND_CLACK ; - -#if DEBUG_MEMC_CLEANUP - if (m_debug) - std::cout << " " - << " Decrement response counter in IVT:" - << " IVT_index = " << r_cleanup_index.read() - << " / rsp_count = " << count << std::endl; -#endif - break; - } - /////////////////////// - case CLEANUP_IVT_CLEAR: // Clear IVT entry - // Acknowledge CONFIG FSM if required - { - assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP) and - "MEMC ERROR in CLEANUP_IVT_CLEAR state : bad IVT allocation"); - - m_ivt.clear(r_cleanup_index.read()); - - if (r_cleanup_need_ack.read()) - { - assert( (r_config_rsp_lines.read() > 0) and - "MEMC ERROR in CLEANUP_IVT_CLEAR state"); - - config_rsp_lines_cleanup_decr = true; - } - - if (r_cleanup_need_rsp.read()) r_cleanup_fsm = CLEANUP_WRITE_RSP; - else r_cleanup_fsm = CLEANUP_SEND_CLACK; - -#if DEBUG_MEMC_CLEANUP - if (m_debug) - std::cout << " Clear entry in IVT:" - << " IVT_index = " << r_cleanup_index.read() << std::endl; -#endif - break; - } - /////////////////////// - case CLEANUP_WRITE_RSP: // response to a previous write on the direct network - // wait if pending request to the TGT_RSP FSM - { - if (r_cleanup_to_tgt_rsp_req.read()) break; - - // no pending request - r_cleanup_to_tgt_rsp_req = true; - r_cleanup_to_tgt_rsp_srcid = r_cleanup_write_srcid.read(); - r_cleanup_to_tgt_rsp_trdid = r_cleanup_write_trdid.read(); - r_cleanup_to_tgt_rsp_pktid = r_cleanup_write_pktid.read(); - r_cleanup_fsm = CLEANUP_SEND_CLACK; - -#if DEBUG_MEMC_CLEANUP - if (m_debug) - std::cout << " " - << " Send a response to a previous write request: " - << " rsrcid = " << std::hex << r_cleanup_write_srcid.read() - << " / rtrdid = " << r_cleanup_write_trdid.read() - << " / rpktid = " << r_cleanup_write_pktid.read() << std::endl; -#endif - break; - } - //////////////////////// - case CLEANUP_SEND_CLACK: // acknowledgement to a cleanup command - // on the coherence CLACK network. - { - if (not p_dspin_clack.read) break; - - r_cleanup_fsm = CLEANUP_IDLE; - -#if DEBUG_MEMC_CLEANUP - if (m_debug) - std::cout << " Send the response to a cleanup request:" - << " address = " << std::hex << r_cleanup_nline.read()*m_words*4 - << " / way = " << std::dec << r_cleanup_way.read() - << " / srcid = " << std::hex << r_cleanup_srcid.read() - << std::endl; -#endif - break; - } + if (m_debug) + { + std::cout << " Send the response to a cleanup request:" + << " address = " << std::hex << r_cleanup_nline.read() * m_words * 4 + << " / way = " << std::dec << r_cleanup_way.read() + << " / srcid = " << std::hex << r_cleanup_srcid.read() + << std::endl; + } +#endif + break; + } } // end switch cleanup fsm @@ -5637,712 +5876,770 @@ //std::cout << std::endl << "cas_fsm" << std::endl; - switch(r_cas_fsm.read()) + switch (r_cas_fsm.read()) { //////////// case CAS_IDLE: // fill the local rdata buffers - { - if (m_cmd_cas_addr_fifo.rok()) - { - -#if DEBUG_MEMC_CAS - if (m_debug) - std::cout << " CAS command: " << std::hex - << " srcid = " << std::dec << m_cmd_cas_srcid_fifo.read() - << " addr = " << std::hex << m_cmd_cas_addr_fifo.read() - << " wdata = " << m_cmd_cas_wdata_fifo.read() - << " eop = " << std::dec << m_cmd_cas_eop_fifo.read() - << " cpt = " << std::dec << r_cas_cpt.read() << std::endl; -#endif - if (m_cmd_cas_eop_fifo.read()) - { - r_cas_fsm = CAS_DIR_REQ; - } - else // we keep the last word in the FIFO - { - cmd_cas_fifo_get = true; - } - - // We fill the two buffers - if (r_cas_cpt.read() < 2) // 32 bits access - r_cas_rdata[r_cas_cpt.read()] = m_cmd_cas_wdata_fifo.read(); - - if ((r_cas_cpt.read() == 1) and m_cmd_cas_eop_fifo.read()) - r_cas_wdata = m_cmd_cas_wdata_fifo.read(); - - assert( (r_cas_cpt.read() <= 3) and // no more than 4 flits... - "MEMC ERROR in CAS_IDLE state: illegal CAS command"); - - if (r_cas_cpt.read() ==2) - r_cas_wdata = m_cmd_cas_wdata_fifo.read(); - - r_cas_cpt = r_cas_cpt.read() +1; - } - break; - } - ///////////////// - case CAS_DIR_REQ: - { - if (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) - { - r_cas_fsm = CAS_DIR_LOCK; - } + { + if (m_cmd_cas_addr_fifo.rok()) + { #if DEBUG_MEMC_CAS if (m_debug) - std::cout << " Requesting DIR lock " << std::endl; -#endif - break; - } - ///////////////// + { + std::cout << " CAS command: " << std::hex + << " srcid = " << std::dec << m_cmd_cas_srcid_fifo.read() + << " addr = " << std::hex << m_cmd_cas_addr_fifo.read() + << " wdata = " << m_cmd_cas_wdata_fifo.read() + << " eop = " << std::dec << m_cmd_cas_eop_fifo.read() + << " cpt = " << std::dec << r_cas_cpt.read() << std::endl; + } +#endif + if (m_cmd_cas_eop_fifo.read()) + { + r_cas_fsm = CAS_DIR_REQ; + } + else // we keep the last word in the FIFO + { + cmd_cas_fifo_get = true; + } + + // We fill the two buffers + if (r_cas_cpt.read() < 2) // 32 bits access + { + r_cas_rdata[r_cas_cpt.read()] = m_cmd_cas_wdata_fifo.read(); + } + + if ((r_cas_cpt.read() == 1) and m_cmd_cas_eop_fifo.read()) + { + r_cas_wdata = m_cmd_cas_wdata_fifo.read(); + } + + assert((r_cas_cpt.read() <= 3) and // no more than 4 flits... + "MEMC ERROR in CAS_IDLE state: illegal CAS command"); + + if (r_cas_cpt.read() == 2) + { + r_cas_wdata = m_cmd_cas_wdata_fifo.read(); + } + + r_cas_cpt = r_cas_cpt.read() + 1; + } + break; + } + ///////////////// + case CAS_DIR_REQ: + { + if (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) + { + r_cas_fsm = CAS_DIR_LOCK; + } + +#if DEBUG_MEMC_CAS + if (m_debug) + { + std::cout << " Requesting DIR lock " << std::endl; + } +#endif + break; + } + ///////////////// case CAS_DIR_LOCK: // Read the directory - { - assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and - "MEMC ERROR in CAS_DIR_LOCK: Bad DIR allocation"); - - size_t way = 0; - DirectoryEntry entry(m_cache_directory.read(m_cmd_cas_addr_fifo.read(), way)); - - r_cas_is_cnt = entry.is_cnt; - r_cas_dirty = entry.dirty; - r_cas_tag = entry.tag; - r_cas_way = way; - r_cas_copy = entry.owner.srcid; - r_cas_copy_inst = entry.owner.inst; - r_cas_ptr = entry.ptr; - r_cas_count = entry.count; - - if (entry.valid) r_cas_fsm = CAS_DIR_HIT_READ; - else r_cas_fsm = CAS_MISS_TRT_LOCK; + { + assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and + "MEMC ERROR in CAS_DIR_LOCK: Bad DIR allocation"); + + size_t way = 0; + DirectoryEntry entry(m_cache_directory.read(m_cmd_cas_addr_fifo.read(), way)); + + r_cas_is_cnt = entry.is_cnt; + r_cas_dirty = entry.dirty; + r_cas_tag = entry.tag; + r_cas_way = way; + r_cas_copy = entry.owner.srcid; + r_cas_copy_inst = entry.owner.inst; + r_cas_ptr = entry.ptr; + r_cas_count = entry.count; + + if (entry.valid) r_cas_fsm = CAS_DIR_HIT_READ; + else r_cas_fsm = CAS_MISS_TRT_LOCK; #if DEBUG_MEMC_CAS - if (m_debug) - std::cout << " Directory acces" - << " / address = " << std::hex << m_cmd_cas_addr_fifo.read() - << " / hit = " << std::dec << entry.valid - << " / count = " << entry.count - << " / is_cnt = " << entry.is_cnt << std::endl; -#endif - - break; - } - ///////////////////// + if (m_debug) + { + std::cout << " Directory acces" + << " / address = " << std::hex << m_cmd_cas_addr_fifo.read() + << " / hit = " << std::dec << entry.valid + << " / count = " << entry.count + << " / is_cnt = " << entry.is_cnt << std::endl; + } +#endif + + break; + } + ///////////////////// case CAS_DIR_HIT_READ: // update directory for lock and dirty bit - // and check data change in cache - { - assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and - "MEMC ERROR in CAS_DIR_HIT_READ: Bad DIR allocation"); - - size_t way = r_cas_way.read(); - size_t set = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())]; - - // update directory (lock & dirty bits) - DirectoryEntry entry; - entry.valid = true; - entry.is_cnt = r_cas_is_cnt.read(); - entry.dirty = true; - entry.lock = true; - entry.tag = r_cas_tag.read(); - entry.owner.srcid = r_cas_copy.read(); - entry.owner.inst = r_cas_copy_inst.read(); - entry.count = r_cas_count.read(); - entry.ptr = r_cas_ptr.read(); - - m_cache_directory.write(set, way, entry); - - // Store data from cache in buffer to do the comparison in next state - m_cache_data.read_line(way, set, r_cas_data); - - r_cas_fsm = CAS_DIR_HIT_COMPARE; + // and check data change in cache + { + assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and + "MEMC ERROR in CAS_DIR_HIT_READ: Bad DIR allocation"); + + size_t way = r_cas_way.read(); + size_t set = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())]; + + // update directory (lock & dirty bits) + DirectoryEntry entry; + entry.valid = true; + entry.is_cnt = r_cas_is_cnt.read(); + entry.dirty = true; + entry.lock = true; + entry.tag = r_cas_tag.read(); + entry.owner.srcid = r_cas_copy.read(); + entry.owner.inst = r_cas_copy_inst.read(); + entry.count = r_cas_count.read(); + entry.ptr = r_cas_ptr.read(); + + m_cache_directory.write(set, way, entry); + + // Store data from cache in buffer to do the comparison in next state + m_cache_data.read_line(way, set, r_cas_data); + + r_cas_fsm = CAS_DIR_HIT_COMPARE; #if DEBUG_MEMC_CAS - if (m_debug) - std::cout << " Read data from " - << " cache and store it in buffer" << std::endl; -#endif - break; - } - //////////////////////// + if (m_debug) + { + std::cout << " Read data from " + << " cache and store it in buffer" << std::endl; + } +#endif + break; + } + //////////////////////// case CAS_DIR_HIT_COMPARE: - { - size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]; - - // check data change - bool ok = (r_cas_rdata[0].read() == r_cas_data[word].read()); - - if (r_cas_cpt.read() == 4) // 64 bits CAS - ok &= (r_cas_rdata[1] == r_cas_data[word+1]); - - // to avoid livelock, force the atomic access to fail pseudo-randomly - bool forced_fail = ((r_cas_lfsr % (64) == 0) and RANDOMIZE_CAS); - r_cas_lfsr = (r_cas_lfsr >> 1) ^ ((- (r_cas_lfsr & 1)) & 0xd0000001); - - if (ok and not forced_fail) r_cas_fsm = CAS_DIR_HIT_WRITE; - else r_cas_fsm = CAS_RSP_FAIL; + { + size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]; + + // check data change + bool ok = (r_cas_rdata[0].read() == r_cas_data[word].read()); + + if (r_cas_cpt.read() == 4) // 64 bits CAS + ok &= (r_cas_rdata[1] == r_cas_data[word+1]); + + // to avoid livelock, force the atomic access to fail pseudo-randomly + bool forced_fail = ((r_cas_lfsr % (64) == 0) and RANDOMIZE_CAS); + r_cas_lfsr = (r_cas_lfsr >> 1) ^ ((- (r_cas_lfsr & 1)) & 0xd0000001); + + if (ok and not forced_fail) r_cas_fsm = CAS_DIR_HIT_WRITE; + else r_cas_fsm = CAS_RSP_FAIL; #if DEBUG_MEMC_CAS - if (m_debug) - std::cout << " Compare old and new data" - << " / expected value = " << std::hex << r_cas_rdata[0].read() - << " / actual value = " << std::hex << r_cas_data[word].read() - << " / forced_fail = " << std::dec << forced_fail << std::endl; -#endif - break; - } - ////////////////////// + if (m_debug) + { + std::cout << " Compare old and new data" + << " / expected value = " << std::hex << r_cas_rdata[0].read() + << " / actual value = " << std::hex << r_cas_data[word].read() + << " / forced_fail = " << std::dec << forced_fail << std::endl; + } +#endif + break; + } + ////////////////////// case CAS_DIR_HIT_WRITE: // test if a CC transaction is required - // write data in cache if no CC request - { - assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and - "MEMC ERROR in CAS_DIR_HIT_WRITE: Bad DIR allocation"); - - // The CAS is a success => sw access to the llsc_global_table - m_llsc_table.sw(m_cmd_cas_addr_fifo.read(), m_cmd_cas_addr_fifo.read()); - - // test coherence request - if (r_cas_count.read()) // replicated line - { - if (r_cas_is_cnt.read()) - { - r_cas_fsm = CAS_BC_TRT_LOCK; // broadcast invalidate required - -#if DEBUG_MEMC_CAS - if (m_debug) - std::cout << " " - << " Broacast Inval required" - << " / copies = " << r_cas_count.read() << std::endl; -#endif - } - else if (not r_cas_to_cc_send_multi_req.read() and - not r_cas_to_cc_send_brdcast_req.read()) - { - r_cas_fsm = CAS_UPT_LOCK; // multi update required - -#if DEBUG_MEMC_CAS - if (m_debug) - std::cout << " " - << " Multi Inval required" - << " / copies = " << r_cas_count.read() << std::endl; -#endif - } - else - { - r_cas_fsm = CAS_WAIT; - -#if DEBUG_MEMC_CAS - if (m_debug) - std::cout << " " - << " CC_SEND FSM busy: release all locks and retry" << std::endl; -#endif - } - } - else // no copies - { - size_t way = r_cas_way.read(); - size_t set = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())]; - size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]; - - // cache update - m_cache_data.write(way, set, word, r_cas_wdata.read()); - if (r_cas_cpt.read() == 4) - m_cache_data.write(way, set, word+1, m_cmd_cas_wdata_fifo.read()); - - r_cas_fsm = CAS_RSP_SUCCESS; - -#if DEBUG_MEMC_CAS - if (m_debug) - std::cout << " Update cache:" - << " way = " << std::dec << way - << " / set = " << set - << " / word = " << word - << " / value = " << r_cas_wdata.read() - << " / count = " << r_cas_count.read() - << " / global_llsc_table access" << std::endl; -#endif - } - break; - } - ///////////////// - case CAS_UPT_LOCK: // try to register the transaction in UPT - // and write data in cache if successful registration - // releases locks to retry later if UPT full - { - if (r_alloc_upt_fsm.read() == ALLOC_UPT_CAS) - { - bool wok = false; - size_t index = 0; - size_t srcid = m_cmd_cas_srcid_fifo.read(); - size_t trdid = m_cmd_cas_trdid_fifo.read(); - size_t pktid = m_cmd_cas_pktid_fifo.read(); - addr_t nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; - size_t nb_copies = r_cas_count.read(); - - wok = m_upt.set( true, // it's an update transaction - false, // it's not a broadcast - true, // response required - false, // no acknowledge required - srcid, - trdid, - pktid, - nline, - nb_copies, - index); - if (wok) // coherence transaction registered in UPT - { - // cache update - size_t way = r_cas_way.read(); - size_t set = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())]; - size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]; - - m_cache_data.write(way, set, word, r_cas_wdata.read()); - if (r_cas_cpt.read() ==4) - m_cache_data.write(way, set, word+1, m_cmd_cas_wdata_fifo.read()); - - r_cas_upt_index = index; - r_cas_fsm = CAS_UPT_HEAP_LOCK; - } - else // releases the locks protecting UPT and DIR UPT full - { - r_cas_fsm = CAS_WAIT; - } - -#if DEBUG_MEMC_CAS - if (m_debug) - std::cout << " Register multi-update transaction in UPT" - << " / wok = " << wok - << " / address = " << std::hex << nline*m_words*4 - << " / count = " << nb_copies << std::endl; -#endif - } - break; - } - ///////////// - case CAS_WAIT: // release all locks and retry from beginning - { - -#if DEBUG_MEMC_CAS - if (m_debug) - std::cout << " Release all locks" << std::endl; -#endif - r_cas_fsm = CAS_DIR_REQ; - break; - } - ////////////////////// - case CAS_UPT_HEAP_LOCK: // lock the heap - { - if (r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS) - { + // write data in cache if no CC request + { + assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and + "MEMC ERROR in CAS_DIR_HIT_WRITE: Bad DIR allocation"); + + // The CAS is a success => sw access to the llsc_global_table + m_llsc_table.sw(m_cmd_cas_addr_fifo.read(), m_cmd_cas_addr_fifo.read()); + + // test coherence request + if (r_cas_count.read()) // replicated line + { + if (r_cas_is_cnt.read()) + { + r_cas_fsm = CAS_BC_TRT_LOCK; // broadcast invalidate required #if DEBUG_MEMC_CAS if (m_debug) { - std::cout << " Get access to the heap" << std::endl; + std::cout << " " + << " Broacast Inval required" + << " / copies = " << r_cas_count.read() << std::endl; } #endif - r_cas_fsm = CAS_UPT_REQ; - } - break; - } - //////////////// - case CAS_UPT_REQ: // send a first update request to CC_SEND FSM - { - assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS) and - "VCI_MEM_CACHE ERROR : bad HEAP allocation"); - - if (!r_cas_to_cc_send_multi_req.read() and !r_cas_to_cc_send_brdcast_req.read()) - { - r_cas_to_cc_send_brdcast_req = false; - r_cas_to_cc_send_trdid = r_cas_upt_index.read(); - r_cas_to_cc_send_nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; - r_cas_to_cc_send_index = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]; - r_cas_to_cc_send_wdata = r_cas_wdata.read(); - - if (r_cas_cpt.read() == 4) - { - r_cas_to_cc_send_is_long = true; - r_cas_to_cc_send_wdata_high = m_cmd_cas_wdata_fifo.read(); - } - else - { - r_cas_to_cc_send_is_long = false; - r_cas_to_cc_send_wdata_high = 0; - } - - // We put the first copy in the fifo - cas_to_cc_send_fifo_put = true; - cas_to_cc_send_fifo_inst = r_cas_copy_inst.read(); - cas_to_cc_send_fifo_srcid = r_cas_copy.read(); - if (r_cas_count.read() == 1) // one single copy - { - r_cas_fsm = CAS_IDLE; // Response will be sent after receiving - // update responses - cmd_cas_fifo_get = true; - r_cas_to_cc_send_multi_req = true; - r_cas_cpt = 0; - } - else // several copies - { - r_cas_fsm = CAS_UPT_NEXT; - } + } + else if (not r_cas_to_cc_send_multi_req.read() and + not r_cas_to_cc_send_brdcast_req.read()) + { + r_cas_fsm = CAS_UPT_LOCK; // multi update required #if DEBUG_MEMC_CAS if (m_debug) { - std::cout << " Send the first update request to CC_SEND FSM " - << " / address = " << std::hex << m_cmd_cas_addr_fifo.read() - << " / wdata = " << std::hex << r_cas_wdata.read() - << " / srcid = " << std::dec << r_cas_copy.read() - << " / inst = " << std::dec << r_cas_copy_inst.read() << std::endl; + std::cout << " " + << " Multi Inval required" + << " / copies = " << r_cas_count.read() << std::endl; } #endif } - break; - } - ///////////////// - case CAS_UPT_NEXT: // send a multi-update request to CC_SEND FSM - { - assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS) - and "VCI_MEM_CACHE ERROR : bad HEAP allocation"); - - HeapEntry entry = m_heap.read(r_cas_ptr.read()); - cas_to_cc_send_fifo_srcid = entry.owner.srcid; - cas_to_cc_send_fifo_inst = entry.owner.inst; - cas_to_cc_send_fifo_put = true; - - if (m_cas_to_cc_send_inst_fifo.wok()) // request accepted by CC_SEND FSM - { - r_cas_ptr = entry.next; - if (entry.next == r_cas_ptr.read()) // last copy + else + { + r_cas_fsm = CAS_WAIT; + +#if DEBUG_MEMC_CAS + if (m_debug) { - r_cas_to_cc_send_multi_req = true; - r_cas_fsm = CAS_IDLE; // Response will be sent after receiving - // all update responses - cmd_cas_fifo_get = true; - r_cas_cpt = 0; + std::cout << " " + << " CC_SEND FSM busy: release all locks and retry" << std::endl; } - } +#endif + } + } + else // no copies + { + size_t way = r_cas_way.read(); + size_t set = m_y[(addr_t) (m_cmd_cas_addr_fifo.read())]; + size_t word = m_x[(addr_t) (m_cmd_cas_addr_fifo.read())]; + + // cache update + m_cache_data.write(way, set, word, r_cas_wdata.read()); + if (r_cas_cpt.read() == 4) + { + m_cache_data.write(way, set, word + 1, m_cmd_cas_wdata_fifo.read()); + } + + r_cas_fsm = CAS_RSP_SUCCESS; #if DEBUG_MEMC_CAS if (m_debug) { - std::cout << " Send the next update request to CC_SEND FSM " + std::cout << " Update cache:" + << " way = " << std::dec << way + << " / set = " << set + << " / word = " << word + << " / value = " << r_cas_wdata.read() + << " / count = " << r_cas_count.read() + << " / global_llsc_table access" << std::endl; + } +#endif + } + break; + } + ///////////////// + case CAS_UPT_LOCK: // try to register the transaction in UPT + // and write data in cache if successful registration + // releases locks to retry later if UPT full + { + if (r_alloc_upt_fsm.read() == ALLOC_UPT_CAS) + { + bool wok = false; + size_t index = 0; + size_t srcid = m_cmd_cas_srcid_fifo.read(); + size_t trdid = m_cmd_cas_trdid_fifo.read(); + size_t pktid = m_cmd_cas_pktid_fifo.read(); + addr_t nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; + size_t nb_copies = r_cas_count.read(); + + wok = m_upt.set(true, // it's an update transaction + false, // it's not a broadcast + true, // response required + false, // no acknowledge required + srcid, + trdid, + pktid, + nline, + nb_copies, + index); + if (wok) // coherence transaction registered in UPT + { + // cache update + size_t way = r_cas_way.read(); + size_t set = m_y[(addr_t) (m_cmd_cas_addr_fifo.read())]; + size_t word = m_x[(addr_t) (m_cmd_cas_addr_fifo.read())]; + + m_cache_data.write(way, set, word, r_cas_wdata.read()); + if (r_cas_cpt.read() == 4) + { + m_cache_data.write(way, set, word + 1, m_cmd_cas_wdata_fifo.read()); + } + + r_cas_upt_index = index; + r_cas_fsm = CAS_UPT_HEAP_LOCK; + } + else // releases the locks protecting UPT and DIR UPT full + { + r_cas_fsm = CAS_WAIT; + } + +#if DEBUG_MEMC_CAS + if (m_debug) + { + std::cout << " Register multi-update transaction in UPT" + << " / wok = " << wok + << " / address = " << std::hex << nline * m_words * 4 + << " / count = " << nb_copies << std::endl; + } +#endif + } + break; + } + ///////////// + case CAS_WAIT: // release all locks and retry from beginning + { + +#if DEBUG_MEMC_CAS + if (m_debug) + { + std::cout << " Release all locks" << std::endl; + } +#endif + r_cas_fsm = CAS_DIR_REQ; + break; + } + ////////////////////// + case CAS_UPT_HEAP_LOCK: // lock the heap + { + if (r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS) + { + +#if DEBUG_MEMC_CAS + if (m_debug) + { + std::cout << " Get access to the heap" << std::endl; + } +#endif + r_cas_fsm = CAS_UPT_REQ; + } + break; + } + //////////////// + case CAS_UPT_REQ: // send a first update request to CC_SEND FSM + { + assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS) and + "VCI_MEM_CACHE ERROR : bad HEAP allocation"); + + if (!r_cas_to_cc_send_multi_req.read() and !r_cas_to_cc_send_brdcast_req.read()) + { + r_cas_to_cc_send_brdcast_req = false; + r_cas_to_cc_send_trdid = r_cas_upt_index.read(); + r_cas_to_cc_send_nline = m_nline[(addr_t) (m_cmd_cas_addr_fifo.read())]; + r_cas_to_cc_send_index = m_x[(addr_t) (m_cmd_cas_addr_fifo.read())]; + r_cas_to_cc_send_wdata = r_cas_wdata.read(); + + if (r_cas_cpt.read() == 4) + { + r_cas_to_cc_send_is_long = true; + r_cas_to_cc_send_wdata_high = m_cmd_cas_wdata_fifo.read(); + } + else + { + r_cas_to_cc_send_is_long = false; + r_cas_to_cc_send_wdata_high = 0; + } + + // We put the first copy in the fifo + cas_to_cc_send_fifo_put = true; + cas_to_cc_send_fifo_inst = r_cas_copy_inst.read(); + cas_to_cc_send_fifo_srcid = r_cas_copy.read(); + if (r_cas_count.read() == 1) // one single copy + { + r_cas_fsm = CAS_IDLE; // Response will be sent after receiving + // update responses + cmd_cas_fifo_get = true; + r_cas_to_cc_send_multi_req = true; + r_cas_cpt = 0; + } + else // several copies + { + r_cas_fsm = CAS_UPT_NEXT; + } + +#if DEBUG_MEMC_CAS + if (m_debug) + { + std::cout << " Send the first update request to CC_SEND FSM " << " / address = " << std::hex << m_cmd_cas_addr_fifo.read() << " / wdata = " << std::hex << r_cas_wdata.read() - << " / srcid = " << std::dec << entry.owner.srcid - << " / inst = " << std::dec << entry.owner.inst << std::endl; - } -#endif - break; - } - ///////////////////// - case CAS_BC_TRT_LOCK: // get TRT lock to check TRT not full - { - assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and - "MEMC ERROR in CAS_BC_TRT_LOCK state: Bas DIR allocation"); - - if (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) - { - size_t wok_index = 0; - bool wok = !m_trt.full(wok_index); - if (wok ) - { - r_cas_trt_index = wok_index; - r_cas_fsm = CAS_BC_IVT_LOCK; - } - else - { - r_cas_fsm = CAS_WAIT; - } + << " / srcid = " << std::dec << r_cas_copy.read() + << " / inst = " << std::dec << r_cas_copy_inst.read() << std::endl; + } +#endif + } + break; + } + ///////////////// + case CAS_UPT_NEXT: // send a multi-update request to CC_SEND FSM + { + assert((r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS) + and "VCI_MEM_CACHE ERROR : bad HEAP allocation"); + + HeapEntry entry = m_heap.read(r_cas_ptr.read()); + cas_to_cc_send_fifo_srcid = entry.owner.srcid; + cas_to_cc_send_fifo_inst = entry.owner.inst; + cas_to_cc_send_fifo_put = true; + + if (m_cas_to_cc_send_inst_fifo.wok()) // request accepted by CC_SEND FSM + { + r_cas_ptr = entry.next; + if (entry.next == r_cas_ptr.read()) // last copy + { + r_cas_to_cc_send_multi_req = true; + r_cas_fsm = CAS_IDLE; // Response will be sent after receiving + // all update responses + cmd_cas_fifo_get = true; + r_cas_cpt = 0; + } + } #if DEBUG_MEMC_CAS - if (m_debug) - std::cout << " Check TRT" - << " : wok = " << wok << " / index = " << wok_index << std::endl; -#endif - } - break; - } - ///////////////////// - case CAS_BC_IVT_LOCK: // get IVT lock and register BC transaction in IVT - { - assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and - "MEMC ERROR in CAS_BC_IVT_LOCK state: Bas DIR allocation"); - - assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and - "MEMC ERROR in CAS_BC_IVT_LOCK state: Bas TRT allocation"); - - if (r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS ) - { - // register broadcast inval transaction in IVT - bool wok = false; - size_t index = 0; - size_t srcid = m_cmd_cas_srcid_fifo.read(); - size_t trdid = m_cmd_cas_trdid_fifo.read(); - size_t pktid = m_cmd_cas_pktid_fifo.read(); - addr_t nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; - size_t nb_copies = r_cas_count.read(); - - wok = m_ivt.set( false, // it's an inval transaction - true, // it's a broadcast - true, // response required - false, // no acknowledge required - srcid, - trdid, - pktid, - nline, - nb_copies, - index); -#if DEBUG_MEMC_CAS - if (m_debug and wok ) - std::cout << " Register broadcast inval in IVT" - << " / copies = " << r_cas_count.read() << std::endl; -#endif - r_cas_upt_index = index; - if (wok ) r_cas_fsm = CAS_BC_DIR_INVAL; - else r_cas_fsm = CAS_WAIT; - } - break; - } - ////////////////////// - case CAS_BC_DIR_INVAL: // Register PUT transaction in TRT, - // and inval the DIR entry - { - assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and - "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad DIR allocation"); - - assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and - "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad TRT allocation"); - - assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS) and - "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad IVT allocation"); - - // set TRT - std::vector data_vector; - data_vector.clear(); - size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]; - for(size_t i=0; i (m_words,0), - data_vector ); - - // invalidate directory entry - DirectoryEntry entry; - entry.valid = false; - entry.dirty = false; - entry.tag = 0; - entry.is_cnt = false; - entry.lock = false; - entry.count = 0; - entry.owner.srcid = 0; - entry.owner.inst = false; - entry.ptr = 0; - size_t set = m_y[(addr_t)(m_cmd_cas_addr_fifo.read())]; - size_t way = r_cas_way.read(); - - m_cache_directory.write(set, way, entry); - - r_cas_fsm = CAS_BC_CC_SEND; + if (m_debug) + { + std::cout << " Send the next update request to CC_SEND FSM " + << " / address = " << std::hex << m_cmd_cas_addr_fifo.read() + << " / wdata = " << std::hex << r_cas_wdata.read() + << " / srcid = " << std::dec << entry.owner.srcid + << " / inst = " << std::dec << entry.owner.inst << std::endl; + } +#endif + break; + } + ///////////////////// + case CAS_BC_TRT_LOCK: // get TRT lock to check TRT not full + { + assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and + "MEMC ERROR in CAS_BC_TRT_LOCK state: Bas DIR allocation"); + + if (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) + { + size_t wok_index = 0; + bool wok = !m_trt.full(wok_index); + if (wok) + { + r_cas_trt_index = wok_index; + r_cas_fsm = CAS_BC_IVT_LOCK; + } + else + { + r_cas_fsm = CAS_WAIT; + } #if DEBUG_MEMC_CAS if (m_debug) - std::cout << " Inval DIR & register in TRT:" - << " address = " << m_cmd_cas_addr_fifo.read() << std::endl; -#endif - break; - } - /////////////////// + { + std::cout << " Check TRT" + << " : wok = " << wok << " / index = " << wok_index << std::endl; + } +#endif + } + break; + } + ///////////////////// + case CAS_BC_IVT_LOCK: // get IVT lock and register BC transaction in IVT + { + assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and + "MEMC ERROR in CAS_BC_IVT_LOCK state: Bas DIR allocation"); + + assert((r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and + "MEMC ERROR in CAS_BC_IVT_LOCK state: Bas TRT allocation"); + + if (r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS) + { + // register broadcast inval transaction in IVT + bool wok = false; + size_t index = 0; + size_t srcid = m_cmd_cas_srcid_fifo.read(); + size_t trdid = m_cmd_cas_trdid_fifo.read(); + size_t pktid = m_cmd_cas_pktid_fifo.read(); + addr_t nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; + size_t nb_copies = r_cas_count.read(); + + wok = m_ivt.set(false, // it's an inval transaction + true, // it's a broadcast + true, // response required + false, // no acknowledge required + srcid, + trdid, + pktid, + nline, + nb_copies, + index); +#if DEBUG_MEMC_CAS + if (m_debug and wok) + { + std::cout << " Register broadcast inval in IVT" + << " / copies = " << r_cas_count.read() << std::endl; + } +#endif + r_cas_upt_index = index; + if (wok) r_cas_fsm = CAS_BC_DIR_INVAL; + else r_cas_fsm = CAS_WAIT; + } + break; + } + ////////////////////// + case CAS_BC_DIR_INVAL: // Register PUT transaction in TRT, + // and inval the DIR entry + { + assert((r_alloc_dir_fsm.read() == ALLOC_DIR_CAS) and + "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad DIR allocation"); + + assert((r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and + "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad TRT allocation"); + + assert((r_alloc_ivt_fsm.read() == ALLOC_IVT_CAS) and + "MEMC ERROR in CAS_BC_DIR_INVAL state: Bad IVT allocation"); + + // set TRT + std::vector data_vector; + data_vector.clear(); + size_t word = m_x[(addr_t)(m_cmd_cas_addr_fifo.read())]; + for (size_t i = 0; i < m_words; i++) + { + if (i == word) + { + // first modified word + data_vector.push_back(r_cas_wdata.read()); + } + else if ((i == word + 1) and (r_cas_cpt.read() == 4)) + { + // second modified word + data_vector.push_back(m_cmd_cas_wdata_fifo.read()); + } + else { + // unmodified words + data_vector.push_back(r_cas_data[i].read()); + } + } + m_trt.set(r_cas_trt_index.read(), + false, // PUT request + m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())], + 0, + 0, + 0, + false, // not a processor read + 0, + 0, + std::vector (m_words,0), + data_vector); + + // invalidate directory entry + DirectoryEntry entry; + entry.valid = false; + entry.dirty = false; + entry.tag = 0; + entry.is_cnt = false; + entry.lock = false; + entry.count = 0; + entry.owner.srcid = 0; + entry.owner.inst = false; + entry.ptr = 0; + size_t set = m_y[(addr_t) (m_cmd_cas_addr_fifo.read())]; + size_t way = r_cas_way.read(); + + m_cache_directory.write(set, way, entry); + + r_cas_fsm = CAS_BC_CC_SEND; + +#if DEBUG_MEMC_CAS + if (m_debug) + { + std::cout << " Inval DIR & register in TRT:" + << " address = " << m_cmd_cas_addr_fifo.read() << std::endl; + } +#endif + break; + } + /////////////////// case CAS_BC_CC_SEND: // Request the broadcast inval to CC_SEND FSM - { - if (not r_cas_to_cc_send_multi_req.read() and - not r_cas_to_cc_send_brdcast_req.read()) - { - r_cas_to_cc_send_multi_req = false; - r_cas_to_cc_send_brdcast_req = true; - r_cas_to_cc_send_trdid = r_cas_upt_index.read(); - r_cas_to_cc_send_nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; - r_cas_to_cc_send_index = 0; - r_cas_to_cc_send_wdata = 0; - - r_cas_fsm = CAS_BC_XRAM_REQ; - -#if DEBUG_MEMC_CAS - if (m_debug) - std::cout << " Post a broadcast request to CC_SEND FSM" << std::endl; -#endif - } - break; - } - //////////////////// - case CAS_BC_XRAM_REQ: // request the IXR FSM to start a PUT transaction - { - if (not r_cas_to_ixr_cmd_req.read()) - { - r_cas_to_ixr_cmd_req = true; - r_cas_to_ixr_cmd_index = r_cas_trt_index.read(); - r_cas_fsm = CAS_IDLE; - cmd_cas_fifo_get = true; - r_cas_cpt = 0; - -#if DEBUG_MEMC_CAS - if (m_debug) - std::cout << " Request a PUT transaction to IXR_CMD FSM" << std::hex - << " / address = " << (addr_t) m_cmd_cas_addr_fifo.read() - << " / trt_index = " << r_cas_trt_index.read() << std::endl; -#endif - } - break; - } - ///////////////// - case CAS_RSP_FAIL: // request TGT_RSP FSM to send a failure response - { - if (not r_cas_to_tgt_rsp_req.read()) - { - cmd_cas_fifo_get = true; - r_cas_cpt = 0; - r_cas_to_tgt_rsp_req = true; - r_cas_to_tgt_rsp_data = 1; - r_cas_to_tgt_rsp_srcid = m_cmd_cas_srcid_fifo.read(); - r_cas_to_tgt_rsp_trdid = m_cmd_cas_trdid_fifo.read(); - r_cas_to_tgt_rsp_pktid = m_cmd_cas_pktid_fifo.read(); - r_cas_fsm = CAS_IDLE; - -#if DEBUG_MEMC_CAS - if (m_debug) - std::cout << " Request TGT_RSP to send a failure response" << std::endl; -#endif - } - break; - } - //////////////////// - case CAS_RSP_SUCCESS: // request TGT_RSP FSM to send a success response - { - if (not r_cas_to_tgt_rsp_req.read()) - { - cmd_cas_fifo_get = true; - r_cas_cpt = 0; - r_cas_to_tgt_rsp_req = true; - r_cas_to_tgt_rsp_data = 0; - r_cas_to_tgt_rsp_srcid = m_cmd_cas_srcid_fifo.read(); - r_cas_to_tgt_rsp_trdid = m_cmd_cas_trdid_fifo.read(); - r_cas_to_tgt_rsp_pktid = m_cmd_cas_pktid_fifo.read(); - r_cas_fsm = CAS_IDLE; - -#if DEBUG_MEMC_CAS - if (m_debug) - std::cout << " Request TGT_RSP to send a success response" << std::endl; -#endif - } - break; - } - /////////////////////// - case CAS_MISS_TRT_LOCK: // cache miss : request access to transaction Table - { - if (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) - { - size_t index = 0; - bool hit_read = m_trt.hit_read( - m_nline[(addr_t) m_cmd_cas_addr_fifo.read()],index); - bool hit_write = m_trt.hit_write( - m_nline[(addr_t) m_cmd_cas_addr_fifo.read()]); - bool wok = not m_trt.full(index); - -#if DEBUG_MEMC_CAS - if (m_debug) - std::cout << " Check TRT state" - << " / hit_read = " << hit_read - << " / hit_write = " << hit_write - << " / wok = " << wok - << " / index = " << index << std::endl; -#endif - - if (hit_read or !wok or hit_write) // missing line already requested or TRT full - { - r_cas_fsm = CAS_WAIT; - } - else - { - r_cas_trt_index = index; - r_cas_fsm = CAS_MISS_TRT_SET; - } - } - break; - } - ////////////////////// - case CAS_MISS_TRT_SET: // register the GET transaction in TRT - { - assert( (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and - "MEMC ERROR in CAS_MISS_TRT_SET state: Bad TRT allocation"); - - std::vector be_vector; - std::vector data_vector; - be_vector.clear(); - data_vector.clear(); - for(size_t i=0; i(m_words,0), - std::vector(m_words,0)); - - r_cas_fsm = CAS_MISS_XRAM_REQ; + { + if (not r_cas_to_cc_send_multi_req.read() and + not r_cas_to_cc_send_brdcast_req.read()) + { + r_cas_to_cc_send_multi_req = false; + r_cas_to_cc_send_brdcast_req = true; + r_cas_to_cc_send_trdid = r_cas_upt_index.read(); + r_cas_to_cc_send_nline = m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())]; + r_cas_to_cc_send_index = 0; + r_cas_to_cc_send_wdata = 0; + + r_cas_fsm = CAS_BC_XRAM_REQ; #if DEBUG_MEMC_CAS if (m_debug) - std::cout << " Register GET transaction in TRT" - << " / address = " << std::hex << (addr_t)m_cmd_cas_addr_fifo.read() + { + std::cout << " Post a broadcast request to CC_SEND FSM" << std::endl; + } +#endif + } + break; + } + //////////////////// + case CAS_BC_XRAM_REQ: // request the IXR FSM to start a PUT transaction + { + if (not r_cas_to_ixr_cmd_req.read()) + { + r_cas_to_ixr_cmd_req = true; + r_cas_to_ixr_cmd_index = r_cas_trt_index.read(); + r_cas_fsm = CAS_IDLE; + cmd_cas_fifo_get = true; + r_cas_cpt = 0; + +#if DEBUG_MEMC_CAS + if (m_debug) + { + std::cout << " Request a PUT transaction to IXR_CMD FSM" << std::hex + << " / address = " << (addr_t) m_cmd_cas_addr_fifo.read() + << " / trt_index = " << r_cas_trt_index.read() << std::endl; + } +#endif + } + break; + } + ///////////////// + case CAS_RSP_FAIL: // request TGT_RSP FSM to send a failure response + { + if (not r_cas_to_tgt_rsp_req.read()) + { + cmd_cas_fifo_get = true; + r_cas_cpt = 0; + r_cas_to_tgt_rsp_req = true; + r_cas_to_tgt_rsp_data = 1; + r_cas_to_tgt_rsp_srcid = m_cmd_cas_srcid_fifo.read(); + r_cas_to_tgt_rsp_trdid = m_cmd_cas_trdid_fifo.read(); + r_cas_to_tgt_rsp_pktid = m_cmd_cas_pktid_fifo.read(); + r_cas_fsm = CAS_IDLE; + +#if DEBUG_MEMC_CAS + if (m_debug) + std::cout << " Request TGT_RSP to send a failure response" << std::endl; +#endif + } + break; + } + //////////////////// + case CAS_RSP_SUCCESS: // request TGT_RSP FSM to send a success response + { + if (not r_cas_to_tgt_rsp_req.read()) + { + cmd_cas_fifo_get = true; + r_cas_cpt = 0; + r_cas_to_tgt_rsp_req = true; + r_cas_to_tgt_rsp_data = 0; + r_cas_to_tgt_rsp_srcid = m_cmd_cas_srcid_fifo.read(); + r_cas_to_tgt_rsp_trdid = m_cmd_cas_trdid_fifo.read(); + r_cas_to_tgt_rsp_pktid = m_cmd_cas_pktid_fifo.read(); + r_cas_fsm = CAS_IDLE; + +#if DEBUG_MEMC_CAS + if (m_debug) + { + std::cout << " Request TGT_RSP to send a success response" << std::endl; + } +#endif + } + break; + } + /////////////////////// + case CAS_MISS_TRT_LOCK: // cache miss : request access to transaction Table + { + if (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) + { + size_t index = 0; + bool hit_read = m_trt.hit_read( + m_nline[(addr_t) m_cmd_cas_addr_fifo.read()],index); + bool hit_write = m_trt.hit_write( + m_nline[(addr_t) m_cmd_cas_addr_fifo.read()]); + bool wok = not m_trt.full(index); + +#if DEBUG_MEMC_CAS + if (m_debug) + { + std::cout << " Check TRT state" + << " / hit_read = " << hit_read + << " / hit_write = " << hit_write + << " / wok = " << wok + << " / index = " << index << std::endl; + } +#endif + + if (hit_read or !wok or hit_write) // missing line already requested or TRT full + { + r_cas_fsm = CAS_WAIT; + } + else + { + r_cas_trt_index = index; + r_cas_fsm = CAS_MISS_TRT_SET; + } + } + break; + } + ////////////////////// + case CAS_MISS_TRT_SET: // register the GET transaction in TRT + { + assert((r_alloc_trt_fsm.read() == ALLOC_TRT_CAS) and + "MEMC ERROR in CAS_MISS_TRT_SET state: Bad TRT allocation"); + + std::vector be_vector; + std::vector data_vector; + be_vector.clear(); + data_vector.clear(); + for (size_t i = 0; i < m_words; i++) + { + be_vector.push_back(0); + data_vector.push_back(0); + } + + m_trt.set(r_cas_trt_index.read(), + true, // GET + m_nline[(addr_t) m_cmd_cas_addr_fifo.read()], + m_cmd_cas_srcid_fifo.read(), + m_cmd_cas_trdid_fifo.read(), + m_cmd_cas_pktid_fifo.read(), + false, // write request from processor + 0, + 0, + std::vector(m_words, 0), + std::vector(m_words, 0)); + + r_cas_fsm = CAS_MISS_XRAM_REQ; + +#if DEBUG_MEMC_CAS + if (m_debug) + { + std::cout << " Register GET transaction in TRT" + << " / address = " << std::hex << (addr_t)m_cmd_cas_addr_fifo.read() + << " / trt_index = " << std::dec << r_cas_trt_index.read() << std::endl; + } +#endif + break; + } + ////////////////////// + case CAS_MISS_XRAM_REQ: // request the IXR_CMD FSM a GET request + { + if (not r_cas_to_ixr_cmd_req.read()) + { + r_cas_to_ixr_cmd_req = true; + r_cas_to_ixr_cmd_index = r_cas_trt_index.read(); + r_cas_fsm = CAS_WAIT; + +#if DEBUG_MEMC_CAS + if (m_debug) + { + std::cout << " Request a GET transaction" + << " / address = " << std::hex << (addr_t) m_cmd_cas_addr_fifo.read() << " / trt_index = " << std::dec << r_cas_trt_index.read() << std::endl; -#endif - break; - } - ////////////////////// - case CAS_MISS_XRAM_REQ: // request the IXR_CMD FSM a GET request - { - if (not r_cas_to_ixr_cmd_req.read()) - { - r_cas_to_ixr_cmd_req = true; - r_cas_to_ixr_cmd_index = r_cas_trt_index.read(); - r_cas_fsm = CAS_WAIT; - -#if DEBUG_MEMC_CAS - if (m_debug) - std::cout << " Request a GET transaction" - << " / address = " << std::hex << (addr_t) m_cmd_cas_addr_fifo.read() - << " / trt_index = " << std::dec << r_cas_trt_index.read() << std::endl; -#endif - } - break; - } + } +#endif + } + break; + } } // end switch r_cas_fsm @@ -6355,5 +6652,5 @@ // // It implements a round-robin priority between the four possible client FSMs - // XRAM_RSP > CAS > WRITE > CONFIG + // XRAM_RSP > CAS > WRITE > CONFIG // // Each FSM can request the next services: @@ -6366,5 +6663,5 @@ // - r_config_to_cc_send_multi_req : multi-inval // r_config_to_cc_send_brdcast_req : broadcast-inval - // + // // An inval request is a double DSPIN flit command containing: // 1. the index of the line to be invalidated. @@ -6376,540 +6673,552 @@ /////////////////////////////////////////////////////////////////////////////// - //std::cout << std::endl << "cc_send_fsm" << std::endl; - - switch(r_cc_send_fsm.read()) + switch (r_cc_send_fsm.read()) { ///////////////////////// case CC_SEND_CONFIG_IDLE: // XRAM_RSP FSM has highest priority - { - // XRAM_RSP - if (m_xram_rsp_to_cc_send_inst_fifo.rok() or - r_xram_rsp_to_cc_send_multi_req.read()) - { - r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER; - break; - } - if (r_xram_rsp_to_cc_send_brdcast_req.read()) - { - r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER; - break; - } - // CAS - if (m_cas_to_cc_send_inst_fifo.rok() or - r_cas_to_cc_send_multi_req.read()) - { - r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; - break; - } - if (r_cas_to_cc_send_brdcast_req.read()) - { - r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER; - break; - } - // WRITE - if (m_write_to_cc_send_inst_fifo.rok() or - r_write_to_cc_send_multi_req.read()) - { - r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER; - break; - } - if (r_write_to_cc_send_brdcast_req.read()) - { - r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER; - break; - } - // CONFIG - if (r_config_to_cc_send_multi_req.read()) - { - r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; - break; - } - if (r_config_to_cc_send_brdcast_req.read()) - { - r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; - break; - } + { + // XRAM_RSP + if (m_xram_rsp_to_cc_send_inst_fifo.rok() or + r_xram_rsp_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER; break; } - //////////////////////// + if (r_xram_rsp_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER; + break; + } + // CAS + if (m_cas_to_cc_send_inst_fifo.rok() or + r_cas_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; + break; + } + if (r_cas_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER; + break; + } + // WRITE + if (m_write_to_cc_send_inst_fifo.rok() or + r_write_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER; + break; + } + if (r_write_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER; + break; + } + // CONFIG + if (r_config_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; + break; + } + if (r_config_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; + break; + } + break; + } + //////////////////////// case CC_SEND_WRITE_IDLE: // CONFIG FSM has highest priority - { - // CONFIG - if (r_config_to_cc_send_multi_req.read()) - { - r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; - break; - } - if (r_config_to_cc_send_brdcast_req.read()) - { - r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; - break; - } - // XRAM_RSP - if (m_xram_rsp_to_cc_send_inst_fifo.rok() or - r_xram_rsp_to_cc_send_multi_req.read()) - { - r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER; - break; - } - if (r_xram_rsp_to_cc_send_brdcast_req.read()) - { - r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER; - break; - } - // CAS - if (m_cas_to_cc_send_inst_fifo.rok() or - r_cas_to_cc_send_multi_req.read()) - { - r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; - break; - } - if (r_cas_to_cc_send_brdcast_req.read()) - { - r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER; - break; - } - // WRITE - if (m_write_to_cc_send_inst_fifo.rok() or - r_write_to_cc_send_multi_req.read()) - { - r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER; - break; - } - if (r_write_to_cc_send_brdcast_req.read()) - { - r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER; - break; - } + { + // CONFIG + if (r_config_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; break; } - /////////////////////////// + if (r_config_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; + break; + } + // XRAM_RSP + if (m_xram_rsp_to_cc_send_inst_fifo.rok() or + r_xram_rsp_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER; + break; + } + if (r_xram_rsp_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER; + break; + } + // CAS + if (m_cas_to_cc_send_inst_fifo.rok() or + r_cas_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; + break; + } + if (r_cas_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER; + break; + } + // WRITE + if (m_write_to_cc_send_inst_fifo.rok() or + r_write_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER; + break; + } + if (r_write_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER; + break; + } + break; + } + /////////////////////////// case CC_SEND_XRAM_RSP_IDLE: // CAS FSM has highest priority - { - // CAS - if (m_cas_to_cc_send_inst_fifo.rok() or - r_cas_to_cc_send_multi_req.read()) - { - r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; - break; - } - if (r_cas_to_cc_send_brdcast_req.read()) - { - r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER; - break; - } - // WRITE - if (m_write_to_cc_send_inst_fifo.rok() or - r_write_to_cc_send_multi_req.read()) - { - r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER; - break; - } - - if (r_write_to_cc_send_brdcast_req.read()) - { - r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER; - break; - } - // CONFIG - if (r_config_to_cc_send_multi_req.read()) - { - r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; - break; - } - if (r_config_to_cc_send_brdcast_req.read()) - { - r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; - break; - } - // XRAM_RSP - if (m_xram_rsp_to_cc_send_inst_fifo.rok() or - r_xram_rsp_to_cc_send_multi_req.read()) - { - r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER; - break; - } - if (r_xram_rsp_to_cc_send_brdcast_req.read()) - { - r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER; - break; - } + { + // CAS + if (m_cas_to_cc_send_inst_fifo.rok() or + r_cas_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; break; } - ////////////////////// + if (r_cas_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER; + break; + } + // WRITE + if (m_write_to_cc_send_inst_fifo.rok() or + r_write_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER; + break; + } + + if (r_write_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER; + break; + } + // CONFIG + if (r_config_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; + break; + } + if (r_config_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; + break; + } + // XRAM_RSP + if (m_xram_rsp_to_cc_send_inst_fifo.rok() or + r_xram_rsp_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER; + break; + } + if (r_xram_rsp_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER; + break; + } + break; + } + ////////////////////// case CC_SEND_CAS_IDLE: // CLEANUP FSM has highest priority - { - if (m_write_to_cc_send_inst_fifo.rok() or - r_write_to_cc_send_multi_req.read()) - { - r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER; - break; - } - if (r_write_to_cc_send_brdcast_req.read()) - { - r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER; - break; - } - // CONFIG - if (r_config_to_cc_send_multi_req.read()) - { - r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; - break; - } - if (r_config_to_cc_send_brdcast_req.read()) - { - r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; - break; - } - if (m_xram_rsp_to_cc_send_inst_fifo.rok() or - r_xram_rsp_to_cc_send_multi_req.read()) - { - r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER; - break; - } - if (r_xram_rsp_to_cc_send_brdcast_req.read()) - { - r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER; - break; - } - if (m_cas_to_cc_send_inst_fifo.rok() or - r_cas_to_cc_send_multi_req.read()) - { - r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; - break; - } - if (r_cas_to_cc_send_brdcast_req.read()) - { - r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER; - break; - } + { + if (m_write_to_cc_send_inst_fifo.rok() or + r_write_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER; break; } - ///////////////////////////////// + if (r_write_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_HEADER; + break; + } + // CONFIG + if (r_config_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; + break; + } + if (r_config_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_HEADER; + break; + } + if (m_xram_rsp_to_cc_send_inst_fifo.rok() or + r_xram_rsp_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER; + break; + } + if (r_xram_rsp_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_HEADER; + break; + } + if (m_cas_to_cc_send_inst_fifo.rok() or + r_cas_to_cc_send_multi_req.read()) + { + r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; + break; + } + if (r_cas_to_cc_send_brdcast_req.read()) + { + r_cc_send_fsm = CC_SEND_CAS_BRDCAST_HEADER; + break; + } + break; + } + ///////////////////////////////// case CC_SEND_CONFIG_INVAL_HEADER: // send first flit multi-inval (from CONFIG FSM) - { - if (m_config_to_cc_send_inst_fifo.rok()) - { - if (not p_dspin_m2p.read) break; - // - if (is_local_req(m_config_to_cc_send_srcid_fifo.read())) - { - m_cpt_minval_local++; - } - else - { - m_cpt_minval_remote++; - } - // 2 flits for multi inval - m_cpt_minval_cost += 2 * req_distance(m_config_to_cc_send_srcid_fifo.read()); - // - r_cc_send_fsm = CC_SEND_CONFIG_INVAL_NLINE; - break; - } - if (r_config_to_cc_send_multi_req.read()) r_config_to_cc_send_multi_req = false; - // - m_cpt_minval++; - // - r_cc_send_fsm = CC_SEND_CONFIG_IDLE; - break; - } - //////////////////////////////// - case CC_SEND_CONFIG_INVAL_NLINE: // send second flit multi-inval (from CONFIG FSM) - { - if (not p_dspin_m2p.read) break; - config_to_cc_send_fifo_get = true; - r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; - -#if DEBUG_MEMC_CC_SEND - if (m_debug) - std::cout << " multi-inval for line " - << std::hex << r_config_to_cc_send_nline.read() << std::endl; -#endif - break; - } - /////////////////////////////////// - case CC_SEND_CONFIG_BRDCAST_HEADER: // send first flit BC-inval (from CONFIG FSM) - { - if (not p_dspin_m2p.read) break; - r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_NLINE; - break; - } - ////////////////////////////////// - case CC_SEND_CONFIG_BRDCAST_NLINE: // send second flit BC-inval (from CONFIG FSM) + { + if (m_config_to_cc_send_inst_fifo.rok()) { if (not p_dspin_m2p.read) break; // - m_cpt_binval++; + if (is_local_req(m_config_to_cc_send_srcid_fifo.read())) + { + m_cpt_minval_local++; + } + else + { + m_cpt_minval_remote++; + } + // 2 flits for multi inval + m_cpt_minval_cost += 2 * req_distance(m_config_to_cc_send_srcid_fifo.read()); // - r_config_to_cc_send_brdcast_req = false; - r_cc_send_fsm = CC_SEND_CONFIG_IDLE; + r_cc_send_fsm = CC_SEND_CONFIG_INVAL_NLINE; + break; + } + if (r_config_to_cc_send_multi_req.read()) r_config_to_cc_send_multi_req = false; + // + m_cpt_minval++; + // + r_cc_send_fsm = CC_SEND_CONFIG_IDLE; + break; + } + //////////////////////////////// + case CC_SEND_CONFIG_INVAL_NLINE: // send second flit multi-inval (from CONFIG FSM) + { + if (not p_dspin_m2p.read) break; + config_to_cc_send_fifo_get = true; + r_cc_send_fsm = CC_SEND_CONFIG_INVAL_HEADER; #if DEBUG_MEMC_CC_SEND - if (m_debug) - std::cout << " BC-Inval for line " - << std::hex << r_config_to_cc_send_nline.read() << std::endl; -#endif - break; - } - /////////////////////////////////// + if (m_debug) + { + std::cout << " multi-inval for line " + << std::hex << r_config_to_cc_send_nline.read() << std::endl; + } +#endif + break; + } + /////////////////////////////////// + case CC_SEND_CONFIG_BRDCAST_HEADER: // send first flit BC-inval (from CONFIG FSM) + { + if (not p_dspin_m2p.read) break; + r_cc_send_fsm = CC_SEND_CONFIG_BRDCAST_NLINE; + break; + } + ////////////////////////////////// + case CC_SEND_CONFIG_BRDCAST_NLINE: // send second flit BC-inval (from CONFIG FSM) + { + if (not p_dspin_m2p.read) break; + // + m_cpt_binval++; + // + r_config_to_cc_send_brdcast_req = false; + r_cc_send_fsm = CC_SEND_CONFIG_IDLE; + +#if DEBUG_MEMC_CC_SEND + if (m_debug) + std::cout << " BC-Inval for line " + << std::hex << r_config_to_cc_send_nline.read() << std::endl; +#endif + break; + } + /////////////////////////////////// case CC_SEND_XRAM_RSP_INVAL_HEADER: // send first flit multi-inval (from XRAM_RSP FSM) - { - if (m_xram_rsp_to_cc_send_inst_fifo.rok()) - { - if (not p_dspin_m2p.read) break; - // - if (is_local_req(m_xram_rsp_to_cc_send_srcid_fifo.read())) - { - m_cpt_minval_local++; - } - else - { - m_cpt_minval_remote++; - } - // 2 flits for multi inval - m_cpt_minval_cost += 2 * req_distance(m_xram_rsp_to_cc_send_srcid_fifo.read()); - // - r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_NLINE; - break; - } - if (r_xram_rsp_to_cc_send_multi_req.read()) r_xram_rsp_to_cc_send_multi_req = false; - // - m_cpt_minval++; - // - r_cc_send_fsm = CC_SEND_XRAM_RSP_IDLE; - break; - } - ////////////////////////////////// - case CC_SEND_XRAM_RSP_INVAL_NLINE: // send second flit multi-inval (from XRAM_RSP FSM) - { - if (not p_dspin_m2p.read) break; - xram_rsp_to_cc_send_fifo_get = true; - r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER; - -#if DEBUG_MEMC_CC_SEND - if (m_debug) - std::cout << " Multicast-Inval for line " - << std::hex << r_xram_rsp_to_cc_send_nline.read() << std::endl; -#endif - break; - } - ///////////////////////////////////// - case CC_SEND_XRAM_RSP_BRDCAST_HEADER: // send first flit broadcast-inval (from XRAM_RSP FSM) - { - if (not p_dspin_m2p.read) break; - r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_NLINE; - break; - } - //////////////////////////////////// - case CC_SEND_XRAM_RSP_BRDCAST_NLINE: // send second flit broadcast-inval (from XRAM_RSP FSM) + { + if (m_xram_rsp_to_cc_send_inst_fifo.rok()) { if (not p_dspin_m2p.read) break; // - m_cpt_binval++; + if (is_local_req(m_xram_rsp_to_cc_send_srcid_fifo.read())) + { + m_cpt_minval_local++; + } + else + { + m_cpt_minval_remote++; + } + // 2 flits for multi inval + m_cpt_minval_cost += 2 * req_distance(m_xram_rsp_to_cc_send_srcid_fifo.read()); // - r_xram_rsp_to_cc_send_brdcast_req = false; - r_cc_send_fsm = CC_SEND_XRAM_RSP_IDLE; + r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_NLINE; + break; + } + if (r_xram_rsp_to_cc_send_multi_req.read()) r_xram_rsp_to_cc_send_multi_req = false; + // + m_cpt_minval++; + // + r_cc_send_fsm = CC_SEND_XRAM_RSP_IDLE; + break; + } + ////////////////////////////////// + case CC_SEND_XRAM_RSP_INVAL_NLINE: // send second flit multi-inval (from XRAM_RSP FSM) + { + if (not p_dspin_m2p.read) break; + xram_rsp_to_cc_send_fifo_get = true; + r_cc_send_fsm = CC_SEND_XRAM_RSP_INVAL_HEADER; #if DEBUG_MEMC_CC_SEND - if (m_debug) - std::cout << " BC-Inval for line " - << std::hex << r_xram_rsp_to_cc_send_nline.read() << std::endl; -#endif - break; - } - ////////////////////////////////// + if (m_debug) + { + std::cout << " Multicast-Inval for line " + << std::hex << r_xram_rsp_to_cc_send_nline.read() << std::endl; + } +#endif + break; + } + ///////////////////////////////////// + case CC_SEND_XRAM_RSP_BRDCAST_HEADER: // send first flit broadcast-inval (from XRAM_RSP FSM) + { + if (not p_dspin_m2p.read) break; + r_cc_send_fsm = CC_SEND_XRAM_RSP_BRDCAST_NLINE; + break; + } + //////////////////////////////////// + case CC_SEND_XRAM_RSP_BRDCAST_NLINE: // send second flit broadcast-inval (from XRAM_RSP FSM) + { + if (not p_dspin_m2p.read) break; + // + m_cpt_binval++; + // + r_xram_rsp_to_cc_send_brdcast_req = false; + r_cc_send_fsm = CC_SEND_XRAM_RSP_IDLE; + +#if DEBUG_MEMC_CC_SEND + if (m_debug) + { + std::cout << " BC-Inval for line " + << std::hex << r_xram_rsp_to_cc_send_nline.read() << std::endl; + } +#endif + break; + } + ////////////////////////////////// case CC_SEND_WRITE_BRDCAST_HEADER: // send first flit broadcast-inval (from WRITE FSM) - { - if (not p_dspin_m2p.read) break; - r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_NLINE; - break; - } - ///////////////////////////////// + { + if (not p_dspin_m2p.read) break; + r_cc_send_fsm = CC_SEND_WRITE_BRDCAST_NLINE; + break; + } + ///////////////////////////////// case CC_SEND_WRITE_BRDCAST_NLINE: // send second flit broadcast-inval (from WRITE FSM) - { - if (not p_dspin_m2p.read) break; - - // - m_cpt_binval++; - m_cpt_write_broadcast++; - // - - r_write_to_cc_send_brdcast_req = false; - r_cc_send_fsm = CC_SEND_WRITE_IDLE; + { + if (not p_dspin_m2p.read) break; + + // + m_cpt_binval++; + m_cpt_write_broadcast++; + // + + r_write_to_cc_send_brdcast_req = false; + r_cc_send_fsm = CC_SEND_WRITE_IDLE; #if DEBUG_MEMC_CC_SEND - if (m_debug) - std::cout << " BC-Inval for line " - << std::hex << r_write_to_cc_send_nline.read() << std::endl; -#endif - break; - } - /////////////////////////////// + if (m_debug) + { + std::cout << " BC-Inval for line " + << std::hex << r_write_to_cc_send_nline.read() << std::endl; + } +#endif + break; + } + /////////////////////////////// case CC_SEND_WRITE_UPDT_HEADER: // send first flit for a multi-update (from WRITE FSM) - { - if (m_write_to_cc_send_inst_fifo.rok()) - { - if (not p_dspin_m2p.read) break; - // - if (is_local_req(m_write_to_cc_send_srcid_fifo.read())) - { - m_cpt_update_local++; - } - else - { - m_cpt_update_remote++; - } - // 2 flits for multi update - m_cpt_update_cost += 2 * req_distance(m_write_to_cc_send_srcid_fifo.read()); - // - - r_cc_send_fsm = CC_SEND_WRITE_UPDT_NLINE; - break; - } - - if (r_write_to_cc_send_multi_req.read()) - { - r_write_to_cc_send_multi_req = false; - } - - // - m_cpt_update++; - // - r_cc_send_fsm = CC_SEND_WRITE_IDLE; - break; - } - ////////////////////////////// - case CC_SEND_WRITE_UPDT_NLINE: // send second flit for a multi-update (from WRITE FSM) - { - if (not p_dspin_m2p.read) break; - - r_cc_send_cpt = 0; - r_cc_send_fsm = CC_SEND_WRITE_UPDT_DATA; - -#if DEBUG_MEMC_CC_SEND - if (m_debug) - std::cout << " Multicast-Update for address " - << r_write_to_cc_send_nline.read()*m_words*4 << std::endl; -#endif - break; - } - ///////////////////////////// - case CC_SEND_WRITE_UPDT_DATA: // send data flits for multi-update (from WRITE FSM) - { - if (not p_dspin_m2p.read) break; - if (r_cc_send_cpt.read() == r_write_to_cc_send_count.read()) - { - write_to_cc_send_fifo_get = true; - r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER; - break; - } - - r_cc_send_cpt = r_cc_send_cpt.read() + 1; - break; - } - //////////////////////////////// - case CC_SEND_CAS_BRDCAST_HEADER: // send first flit broadcast-inval (from CAS FSM) - { - if (not p_dspin_m2p.read) break; - r_cc_send_fsm = CC_SEND_CAS_BRDCAST_NLINE; - break; - } - /////////////////////////////// - case CC_SEND_CAS_BRDCAST_NLINE: // send second flit broadcast-inval (from CAS FSM) + { + if (m_write_to_cc_send_inst_fifo.rok()) { if (not p_dspin_m2p.read) break; // - m_cpt_binval++; + if (is_local_req(m_write_to_cc_send_srcid_fifo.read())) + { + m_cpt_update_local++; + } + else + { + m_cpt_update_remote++; + } + // 2 flits for multi update + m_cpt_update_cost += 2 * req_distance(m_write_to_cc_send_srcid_fifo.read()); // - r_cas_to_cc_send_brdcast_req = false; - r_cc_send_fsm = CC_SEND_CAS_IDLE; + r_cc_send_fsm = CC_SEND_WRITE_UPDT_NLINE; + break; + } + + if (r_write_to_cc_send_multi_req.read()) + { + r_write_to_cc_send_multi_req = false; + } + + // + m_cpt_update++; + // + r_cc_send_fsm = CC_SEND_WRITE_IDLE; + break; + } + ////////////////////////////// + case CC_SEND_WRITE_UPDT_NLINE: // send second flit for a multi-update (from WRITE FSM) + { + if (not p_dspin_m2p.read) break; + + r_cc_send_cpt = 0; + r_cc_send_fsm = CC_SEND_WRITE_UPDT_DATA; #if DEBUG_MEMC_CC_SEND - if (m_debug) - std::cout << " Broadcast-Inval for address: " - << r_cas_to_cc_send_nline.read()*m_words*4 << std::endl; -#endif + if (m_debug) + { + std::cout << " Multicast-Update for address " + << r_write_to_cc_send_nline.read() * m_words * 4 << std::endl; + } +#endif + break; + } + ///////////////////////////// + case CC_SEND_WRITE_UPDT_DATA: // send data flits for multi-update (from WRITE FSM) + { + if (not p_dspin_m2p.read) break; + if (r_cc_send_cpt.read() == r_write_to_cc_send_count.read()) + { + write_to_cc_send_fifo_get = true; + r_cc_send_fsm = CC_SEND_WRITE_UPDT_HEADER; break; } - ///////////////////////////// + + r_cc_send_cpt = r_cc_send_cpt.read() + 1; + break; + } + //////////////////////////////// + case CC_SEND_CAS_BRDCAST_HEADER: // send first flit broadcast-inval (from CAS FSM) + { + if (not p_dspin_m2p.read) break; + r_cc_send_fsm = CC_SEND_CAS_BRDCAST_NLINE; + break; + } + /////////////////////////////// + case CC_SEND_CAS_BRDCAST_NLINE: // send second flit broadcast-inval (from CAS FSM) + { + if (not p_dspin_m2p.read) break; + // + m_cpt_binval++; + // + + r_cas_to_cc_send_brdcast_req = false; + r_cc_send_fsm = CC_SEND_CAS_IDLE; + +#if DEBUG_MEMC_CC_SEND + if (m_debug) + { + std::cout << " Broadcast-Inval for address: " + << r_cas_to_cc_send_nline.read() * m_words * 4 << std::endl; + } +#endif + break; + } + ///////////////////////////// case CC_SEND_CAS_UPDT_HEADER: // send first flit for a multi-update (from CAS FSM) - { - if (m_cas_to_cc_send_inst_fifo.rok()) - { - if (not p_dspin_m2p.read) break; - // - if (is_local_req(m_cas_to_cc_send_srcid_fifo.read())) - { - m_cpt_update_local++; - } - else - { - m_cpt_update_remote++; - } - // 2 flits for multi update - m_cpt_update_cost += 2 * req_distance(m_cas_to_cc_send_srcid_fifo.read()); - // - r_cc_send_fsm = CC_SEND_CAS_UPDT_NLINE; - break; - } - - // no more packets to send for the multi-update - if (r_cas_to_cc_send_multi_req.read()) - { - r_cas_to_cc_send_multi_req = false; - } - + { + if (m_cas_to_cc_send_inst_fifo.rok()) + { + if (not p_dspin_m2p.read) break; // - m_cpt_update++; + if (is_local_req(m_cas_to_cc_send_srcid_fifo.read())) + { + m_cpt_update_local++; + } + else + { + m_cpt_update_remote++; + } + // 2 flits for multi update + m_cpt_update_cost += 2 * req_distance(m_cas_to_cc_send_srcid_fifo.read()); // - r_cc_send_fsm = CC_SEND_CAS_IDLE; + r_cc_send_fsm = CC_SEND_CAS_UPDT_NLINE; break; } - //////////////////////////// + + // no more packets to send for the multi-update + if (r_cas_to_cc_send_multi_req.read()) + { + r_cas_to_cc_send_multi_req = false; + } + + // + m_cpt_update++; + // + r_cc_send_fsm = CC_SEND_CAS_IDLE; + break; + } + //////////////////////////// case CC_SEND_CAS_UPDT_NLINE: // send second flit for a multi-update (from CAS FSM) - { - if (not p_dspin_m2p.read) break; - r_cc_send_cpt = 0; - r_cc_send_fsm = CC_SEND_CAS_UPDT_DATA; + { + if (not p_dspin_m2p.read) break; + r_cc_send_cpt = 0; + r_cc_send_fsm = CC_SEND_CAS_UPDT_DATA; #if DEBUG_MEMC_CC_SEND - if (m_debug) - std::cout << " Multicast-Update for address " - << r_cas_to_cc_send_nline.read()*m_words*4 << std::endl; -#endif + if (m_debug) + { + std::cout << " Multicast-Update for address " + << r_cas_to_cc_send_nline.read() * m_words * 4 << std::endl; + } +#endif + break; + } + /////////////////////////// + case CC_SEND_CAS_UPDT_DATA: // send first data for a multi-update (from CAS FSM) + { + if (not p_dspin_m2p.read) break; + + if (r_cas_to_cc_send_is_long.read()) + { + r_cc_send_fsm = CC_SEND_CAS_UPDT_DATA_HIGH; break; } - /////////////////////////// - case CC_SEND_CAS_UPDT_DATA: // send first data for a multi-update (from CAS FSM) - { - if (not p_dspin_m2p.read) break; - - if (r_cas_to_cc_send_is_long.read()) - { - r_cc_send_fsm = CC_SEND_CAS_UPDT_DATA_HIGH; - break; - } - - cas_to_cc_send_fifo_get = true; - r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; - break; - } - //////////////////////////////// + + cas_to_cc_send_fifo_get = true; + r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; + break; + } + //////////////////////////////// case CC_SEND_CAS_UPDT_DATA_HIGH: // send second data for multi-update (from CAS FSM) - { - if (not p_dspin_m2p.read) break; - cas_to_cc_send_fifo_get = true; - r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; - break; - } + { + if (not p_dspin_m2p.read) break; + cas_to_cc_send_fifo_get = true; + r_cc_send_fsm = CC_SEND_CAS_UPDT_HEADER; + break; + } } // end switch r_cc_send_fsm @@ -6922,104 +7231,103 @@ ////////////////////////////////////////////////////////////////////////////// - //std::cout << std::endl << "cc_receive_fsm" << std::endl; - - switch(r_cc_receive_fsm.read()) + switch (r_cc_receive_fsm.read()) { ///////////////////// case CC_RECEIVE_IDLE: - { - if (not p_dspin_p2m.write) break; - - uint8_t type = - DspinDhccpParam::dspin_get( - p_dspin_p2m.data.read(), - DspinDhccpParam::P2M_TYPE); - - if ((type == DspinDhccpParam::TYPE_CLEANUP_DATA) or - (type == DspinDhccpParam::TYPE_CLEANUP_INST)) - { - r_cc_receive_fsm = CC_RECEIVE_CLEANUP; - break; - } - - if (type == DspinDhccpParam::TYPE_MULTI_ACK) - { - r_cc_receive_fsm = CC_RECEIVE_MULTI_ACK; - break; - } - - assert(false and - "VCI_MEM_CACHE ERROR in CC_RECEIVE : " - "Illegal type in coherence request"); - + { + if (not p_dspin_p2m.write) break; + + uint8_t type = + DspinDhccpParam::dspin_get( + p_dspin_p2m.data.read(), + DspinDhccpParam::P2M_TYPE); + + if ((type == DspinDhccpParam::TYPE_CLEANUP_DATA) or + (type == DspinDhccpParam::TYPE_CLEANUP_INST)) + { + r_cc_receive_fsm = CC_RECEIVE_CLEANUP; break; } - //////////////////////// + + if (type == DspinDhccpParam::TYPE_MULTI_ACK) + { + r_cc_receive_fsm = CC_RECEIVE_MULTI_ACK; + break; + } + + assert(false and + "VCI_MEM_CACHE ERROR in CC_RECEIVE : " + "Illegal type in coherence request"); + + break; + } + //////////////////////// case CC_RECEIVE_CLEANUP: - { - // write first CLEANUP flit in CC_RECEIVE to CLEANUP fifo - - if (not p_dspin_p2m.write or not m_cc_receive_to_cleanup_fifo.wok()) - break; - - assert(not p_dspin_p2m.eop.read() and - "VCI_MEM_CACHE ERROR in CC_RECEIVE : " - "CLEANUP command must have two flits"); - - cc_receive_to_cleanup_fifo_put = true; - r_cc_receive_fsm = CC_RECEIVE_CLEANUP_EOP; - - // - uint32_t srcid = DspinDhccpParam::dspin_get( - p_dspin_p2m.data.read(), - DspinDhccpParam::CLEANUP_SRCID); - - if (is_local_req(srcid)) { - m_cpt_cleanup_local++; - } - else { - m_cpt_cleanup_remote++; - } - // 2 flits for cleanup without data - m_cpt_cleanup_cost += 2 * req_distance(srcid); - // - + { + // write first CLEANUP flit in CC_RECEIVE to CLEANUP fifo + + if (not p_dspin_p2m.write or not m_cc_receive_to_cleanup_fifo.wok()) break; - } - //////////////////////////// + + assert(not p_dspin_p2m.eop.read() and + "VCI_MEM_CACHE ERROR in CC_RECEIVE : " + "CLEANUP command must have two flits"); + + cc_receive_to_cleanup_fifo_put = true; + r_cc_receive_fsm = CC_RECEIVE_CLEANUP_EOP; + + // + uint32_t srcid = DspinDhccpParam::dspin_get( + p_dspin_p2m.data.read(), + DspinDhccpParam::CLEANUP_SRCID); + + if (is_local_req(srcid)) + { + m_cpt_cleanup_local++; + } + else { + m_cpt_cleanup_remote++; + } + // 2 flits for cleanup without data + m_cpt_cleanup_cost += 2 * req_distance(srcid); + // + + break; + } + //////////////////////////// case CC_RECEIVE_CLEANUP_EOP: - { - // write second CLEANUP flit in CC_RECEIVE to CLEANUP fifo - - if (not p_dspin_p2m.write or not m_cc_receive_to_cleanup_fifo.wok()) - break; - - assert(p_dspin_p2m.eop.read() and - "VCI_MEM_CACHE ERROR in CC_RECEIVE : " - "CLEANUP command must have two flits"); - - cc_receive_to_cleanup_fifo_put = true; - r_cc_receive_fsm = CC_RECEIVE_IDLE; - + { + // write second CLEANUP flit in CC_RECEIVE to CLEANUP fifo + + if (not p_dspin_p2m.write or not m_cc_receive_to_cleanup_fifo.wok()) break; - } - - ////////////////////////// + + assert(p_dspin_p2m.eop.read() and + "VCI_MEM_CACHE ERROR in CC_RECEIVE : " + "CLEANUP command must have two flits"); + + cc_receive_to_cleanup_fifo_put = true; + r_cc_receive_fsm = CC_RECEIVE_IDLE; + + break; + } + + ////////////////////////// case CC_RECEIVE_MULTI_ACK: - { - // write MULTI_ACK flit in CC_RECEIVE to MULTI_ACK fifo - - // wait for a WOK in the CC_RECEIVE to MULTI_ACK fifo - if (not p_dspin_p2m.write or not m_cc_receive_to_multi_ack_fifo.wok()) - break; - - assert(p_dspin_p2m.eop.read() and - "VCI_MEM_CACHE ERROR in CC_RECEIVE : " - "MULTI_ACK command must have one flit"); - - cc_receive_to_multi_ack_fifo_put = true; - r_cc_receive_fsm = CC_RECEIVE_IDLE; + { + // write MULTI_ACK flit in CC_RECEIVE to MULTI_ACK fifo + + // wait for a WOK in the CC_RECEIVE to MULTI_ACK fifo + if (not p_dspin_p2m.write or not m_cc_receive_to_multi_ack_fifo.wok()) break; - } + + assert(p_dspin_p2m.eop.read() and + "VCI_MEM_CACHE ERROR in CC_RECEIVE : " + "MULTI_ACK command must have one flit"); + + cc_receive_to_multi_ack_fifo_put = true; + r_cc_receive_fsm = CC_RECEIVE_IDLE; + break; + } } @@ -7042,385 +7350,393 @@ ////////////////////////////////////////////////////////////////////////// - //std::cout << std::endl << "tgt_rsp_fsm" << std::endl; - - switch(r_tgt_rsp_fsm.read()) + switch (r_tgt_rsp_fsm.read()) { ///////////////////////// case TGT_RSP_CONFIG_IDLE: // tgt_cmd requests have the highest priority - { - if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; - else if (r_read_to_tgt_rsp_req) - { - r_tgt_rsp_fsm = TGT_RSP_READ; - r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); - } - else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; - else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; - else if (r_xram_rsp_to_tgt_rsp_req) - { - r_tgt_rsp_fsm = TGT_RSP_XRAM; - r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); - } - else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; - else if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; - else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; - break; - } - ////////////////////////// + { + if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + else if (r_read_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_READ; + r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); + } + else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; + else if (r_xram_rsp_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_XRAM; + r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); + } + else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; + else if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + break; + } + ////////////////////////// case TGT_RSP_TGT_CMD_IDLE: // read requests have the highest priority - { - if (r_read_to_tgt_rsp_req) - { - r_tgt_rsp_fsm = TGT_RSP_READ; - r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); - } - else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; - else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; - else if (r_xram_rsp_to_tgt_rsp_req) - { - r_tgt_rsp_fsm = TGT_RSP_XRAM; - r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); - } - else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; - else if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; - else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; - else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; - break; - } - /////////////////////// + { + if (r_read_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_READ; + r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); + } + else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; + else if (r_xram_rsp_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_XRAM; + r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); + } + else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; + else if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + break; + } + /////////////////////// case TGT_RSP_READ_IDLE: // write requests have the highest priority - { - if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; - else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; - else if (r_xram_rsp_to_tgt_rsp_req) - { - r_tgt_rsp_fsm = TGT_RSP_XRAM; - r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); - } - else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; - else if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; - else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; - else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; - else if (r_read_to_tgt_rsp_req) - { - r_tgt_rsp_fsm = TGT_RSP_READ; - r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); - } - break; - } - //////////////////////// + { + if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; + else if (r_xram_rsp_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_XRAM; + r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); + } + else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; + else if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + else if (r_read_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_READ; + r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); + } + break; + } + //////////////////////// case TGT_RSP_WRITE_IDLE: // cas requests have the highest priority - { - if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; - else if (r_xram_rsp_to_tgt_rsp_req) - { - r_tgt_rsp_fsm = TGT_RSP_XRAM; - r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); - } - else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; - else if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; - else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; - else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; - else if (r_read_to_tgt_rsp_req) - { - r_tgt_rsp_fsm = TGT_RSP_READ; - r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); - } - else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; - break; - } - /////////////////////// + { + if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS; + else if (r_xram_rsp_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_XRAM; + r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); + } + else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; + else if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + else if (r_read_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_READ; + r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); + } + else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + break; + } + /////////////////////// case TGT_RSP_CAS_IDLE: // xram_rsp requests have the highest priority - { - if (r_xram_rsp_to_tgt_rsp_req) - { - r_tgt_rsp_fsm = TGT_RSP_XRAM; - r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); - } - else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK ; - else if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; - else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; - else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; - else if (r_read_to_tgt_rsp_req) - { - r_tgt_rsp_fsm = TGT_RSP_READ; - r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); - } - else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; - else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; - break; - } - /////////////////////// + { + if (r_xram_rsp_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_XRAM; + r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); + } + else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK ; + else if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + else if (r_read_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_READ; + r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); + } + else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; + break; + } + /////////////////////// case TGT_RSP_XRAM_IDLE: // multi ack requests have the highest priority - { - - if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK ; - else if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; - else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; - else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; - else if (r_read_to_tgt_rsp_req) - { - r_tgt_rsp_fsm = TGT_RSP_READ; - r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); - } - else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; - else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; - else if (r_xram_rsp_to_tgt_rsp_req) - { - r_tgt_rsp_fsm = TGT_RSP_XRAM; - r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); - } - break; - } - //////////////////////////// + { + + if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK ; + else if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + else if (r_read_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_READ; + r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); + } + else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; + else if (r_xram_rsp_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_XRAM; + r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); + } + break; + } + //////////////////////////// case TGT_RSP_MULTI_ACK_IDLE: // cleanup requests have the highest priority - { - if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; - else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; - else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; - else if (r_read_to_tgt_rsp_req) - { - r_tgt_rsp_fsm = TGT_RSP_READ; - r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); - } - else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; - else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; - else if (r_xram_rsp_to_tgt_rsp_req) - { - r_tgt_rsp_fsm = TGT_RSP_XRAM; - r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); - } - else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; - break; - } - ////////////////////////// + { + if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + else if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + else if (r_read_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_READ; + r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); + } + else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; + else if (r_xram_rsp_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_XRAM; + r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); + } + else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; + break; + } + ////////////////////////// case TGT_RSP_CLEANUP_IDLE: // tgt cmd requests have the highest priority - { - if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; - else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; - else if (r_read_to_tgt_rsp_req) - { - r_tgt_rsp_fsm = TGT_RSP_READ; - r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); - } - else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; - else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; - else if (r_xram_rsp_to_tgt_rsp_req) - { - r_tgt_rsp_fsm = TGT_RSP_XRAM; - r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); - } - else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK ; - else if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; - break; - } - //////////////////// + { + if (r_config_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CONFIG; + else if (r_tgt_cmd_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_TGT_CMD; + else if (r_read_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_READ; + r_tgt_rsp_cpt = r_read_to_tgt_rsp_word.read(); + } + else if (r_write_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_WRITE; + else if (r_cas_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CAS ; + else if (r_xram_rsp_to_tgt_rsp_req) + { + r_tgt_rsp_fsm = TGT_RSP_XRAM; + r_tgt_rsp_cpt = r_xram_rsp_to_tgt_rsp_word.read(); + } + else if (r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK ; + else if (r_cleanup_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_CLEANUP; + break; + } + //////////////////// case TGT_RSP_CONFIG: // send the response for a config transaction - { - if (p_vci_tgt.rspack ) - { - r_config_to_tgt_rsp_req = false; - r_tgt_rsp_fsm = TGT_RSP_CONFIG_IDLE; + { + if (p_vci_tgt.rspack) + { + r_config_to_tgt_rsp_req = false; + r_tgt_rsp_fsm = TGT_RSP_CONFIG_IDLE; #if DEBUG_MEMC_TGT_RSP - if (m_debug ) + if (m_debug) + { + std::cout + << " Config transaction completed response" + << " / rsrcid = " << std::hex << r_config_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_config_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_config_to_tgt_rsp_pktid.read() + << std::endl; + } +#endif + } + break; + } + ///////////////////// + case TGT_RSP_TGT_CMD: // send the response for a configuration access + { + if (p_vci_tgt.rspack) + { + r_tgt_cmd_to_tgt_rsp_req = false; + r_tgt_rsp_fsm = TGT_RSP_TGT_CMD_IDLE; + +#if DEBUG_MEMC_TGT_RSP + if (m_debug) + { + std::cout + << " Send response for a configuration access" + << " / rsrcid = " << std::hex << r_tgt_cmd_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_tgt_cmd_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_tgt_cmd_to_tgt_rsp_pktid.read() + << " / error = " << r_tgt_cmd_to_tgt_rsp_error.read() + << std::endl; + } +#endif + } + break; + } + ////////////////// + case TGT_RSP_READ: // send the response to a read + { + if (p_vci_tgt.rspack) + { + +#if DEBUG_MEMC_TGT_RSP + if (m_debug) + { + std::cout + << " Read response" + << " / rsrcid = " << std::hex << r_read_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_read_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_read_to_tgt_rsp_pktid.read() + << " / rdata = " << r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read() + << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl; + } +#endif + + uint32_t last_word_idx = r_read_to_tgt_rsp_word.read() + + r_read_to_tgt_rsp_length.read() - 1; + bool is_last_word = (r_tgt_rsp_cpt.read() == last_word_idx); + bool is_ll = ((r_read_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL); + + if ((is_last_word and not is_ll) or + (r_tgt_rsp_key_sent.read() and is_ll)) + { + // Last word in case of READ or second flit in case if LL + r_tgt_rsp_key_sent = false; + r_read_to_tgt_rsp_req = false; + r_tgt_rsp_fsm = TGT_RSP_READ_IDLE; + } + else + { + if (is_ll) { - std::cout - << " Config transaction completed response" - << " / rsrcid = " << std::hex << r_config_to_tgt_rsp_srcid.read() - << " / rtrdid = " << r_config_to_tgt_rsp_trdid.read() - << " / rpktid = " << r_config_to_tgt_rsp_pktid.read() - << std::endl; - } -#endif - } - break; - } - ///////////////////// - case TGT_RSP_TGT_CMD: // send the response for a configuration access - { - if (p_vci_tgt.rspack ) - { - r_tgt_cmd_to_tgt_rsp_req = false; - r_tgt_rsp_fsm = TGT_RSP_TGT_CMD_IDLE; - -#if DEBUG_MEMC_TGT_RSP - if (m_debug ) - { - std::cout - << " Send response for a configuration access" - << " / rsrcid = " << std::hex << r_tgt_cmd_to_tgt_rsp_srcid.read() - << " / rtrdid = " << r_tgt_cmd_to_tgt_rsp_trdid.read() - << " / rpktid = " << r_tgt_cmd_to_tgt_rsp_pktid.read() - << " / error = " << r_tgt_cmd_to_tgt_rsp_error.read() - << std::endl; - } -#endif - } - break; - } - ////////////////// - case TGT_RSP_READ: // send the response to a read - { - if (p_vci_tgt.rspack ) - { - -#if DEBUG_MEMC_TGT_RSP - if (m_debug ) - { - std::cout - << " Read response" - << " / rsrcid = " << std::hex << r_read_to_tgt_rsp_srcid.read() - << " / rtrdid = " << r_read_to_tgt_rsp_trdid.read() - << " / rpktid = " << r_read_to_tgt_rsp_pktid.read() - << " / rdata = " << r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read() - << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl; - } -#endif - - uint32_t last_word_idx = r_read_to_tgt_rsp_word.read() + - r_read_to_tgt_rsp_length.read() - 1; - bool is_last_word = (r_tgt_rsp_cpt.read() == last_word_idx); - bool is_ll = ((r_read_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL); - - if ((is_last_word and not is_ll) or - (r_tgt_rsp_key_sent.read() and is_ll)) - { - // Last word in case of READ or second flit in case if LL - r_tgt_rsp_key_sent = false; - r_read_to_tgt_rsp_req = false; - r_tgt_rsp_fsm = TGT_RSP_READ_IDLE; + r_tgt_rsp_key_sent = true; // Send second flit of ll } else { - if (is_ll) - { - r_tgt_rsp_key_sent = true; // Send second flit of ll - } - else - { - r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1; // Send next word of read - } + r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1; // Send next word of read } } - break; - } - ////////////////// + } + break; + } + ////////////////// case TGT_RSP_WRITE: // send the write acknowledge - { - if (p_vci_tgt.rspack) - { + { + if (p_vci_tgt.rspack) + { #if DEBUG_MEMC_TGT_RSP - if (m_debug) - std::cout << " Write response" - << " / rsrcid = " << std::hex << r_write_to_tgt_rsp_srcid.read() - << " / rtrdid = " << r_write_to_tgt_rsp_trdid.read() - << " / rpktid = " << r_write_to_tgt_rsp_pktid.read() << std::endl; -#endif - r_tgt_rsp_fsm = TGT_RSP_WRITE_IDLE; - r_write_to_tgt_rsp_req = false; - } - break; - } - ///////////////////// + if (m_debug) + { + std::cout << " Write response" + << " / rsrcid = " << std::hex << r_write_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_write_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_write_to_tgt_rsp_pktid.read() << std::endl; + } +#endif + r_tgt_rsp_fsm = TGT_RSP_WRITE_IDLE; + r_write_to_tgt_rsp_req = false; + } + break; + } + ///////////////////// case TGT_RSP_CLEANUP: // pas clair pour moi (AG) - { - if (p_vci_tgt.rspack) - { + { + if (p_vci_tgt.rspack) + { #if DEBUG_MEMC_TGT_RSP - if (m_debug) - std::cout << " Cleanup response" - << " / rsrcid = " << std::hex << r_cleanup_to_tgt_rsp_srcid.read() - << " / rtrdid = " << r_cleanup_to_tgt_rsp_trdid.read() - << " / rpktid = " << r_cleanup_to_tgt_rsp_pktid.read() << std::endl; -#endif - r_tgt_rsp_fsm = TGT_RSP_CLEANUP_IDLE; - r_cleanup_to_tgt_rsp_req = false; - } - break; - } - ///////////////// + if (m_debug) + { + std::cout << " Cleanup response" + << " / rsrcid = " << std::hex << r_cleanup_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_cleanup_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_cleanup_to_tgt_rsp_pktid.read() << std::endl; + } +#endif + r_tgt_rsp_fsm = TGT_RSP_CLEANUP_IDLE; + r_cleanup_to_tgt_rsp_req = false; + } + break; + } + ///////////////// case TGT_RSP_CAS: // send one atomic word response - { - if (p_vci_tgt.rspack) - { + { + if (p_vci_tgt.rspack) + { #if DEBUG_MEMC_TGT_RSP - if (m_debug) - std::cout << " CAS response" - << " / rsrcid = " << std::hex << r_cas_to_tgt_rsp_srcid.read() - << " / rtrdid = " << r_cas_to_tgt_rsp_trdid.read() - << " / rpktid = " << r_cas_to_tgt_rsp_pktid.read() << std::endl; -#endif - r_tgt_rsp_fsm = TGT_RSP_CAS_IDLE; - r_cas_to_tgt_rsp_req = false; - } - break; - } - ////////////////// + if (m_debug) + { + std::cout << " CAS response" + << " / rsrcid = " << std::hex << r_cas_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_cas_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_cas_to_tgt_rsp_pktid.read() << std::endl; + } +#endif + r_tgt_rsp_fsm = TGT_RSP_CAS_IDLE; + r_cas_to_tgt_rsp_req = false; + } + break; + } + ////////////////// case TGT_RSP_XRAM: // send the response after XRAM access - { - if (p_vci_tgt.rspack ) - { + { + if (p_vci_tgt.rspack) + { #if DEBUG_MEMC_TGT_RSP - if (m_debug ) - std::cout << " Response following XRAM access" - << " / rsrcid = " << std::hex << r_xram_rsp_to_tgt_rsp_srcid.read() - << " / rtrdid = " << r_xram_rsp_to_tgt_rsp_trdid.read() - << " / rpktid = " << r_xram_rsp_to_tgt_rsp_pktid.read() - << " / rdata = " << r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read() - << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl; -#endif - uint32_t last_word_idx = r_xram_rsp_to_tgt_rsp_word.read() + - r_xram_rsp_to_tgt_rsp_length.read() - 1; - bool is_last_word = (r_tgt_rsp_cpt.read() == last_word_idx); - bool is_ll = ((r_xram_rsp_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL); - bool is_error = r_xram_rsp_to_tgt_rsp_rerror.read(); - - if (((is_last_word or is_error) and not is_ll) or - (r_tgt_rsp_key_sent.read() and is_ll)) + if (m_debug) + { + std::cout << " Response following XRAM access" + << " / rsrcid = " << std::hex << r_xram_rsp_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_xram_rsp_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_xram_rsp_to_tgt_rsp_pktid.read() + << " / rdata = " << r_xram_rsp_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read() + << " / cpt = " << std::dec << r_tgt_rsp_cpt.read() << std::endl; + } +#endif + uint32_t last_word_idx = r_xram_rsp_to_tgt_rsp_word.read() + + r_xram_rsp_to_tgt_rsp_length.read() - 1; + bool is_last_word = (r_tgt_rsp_cpt.read() == last_word_idx); + bool is_ll = ((r_xram_rsp_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL); + bool is_error = r_xram_rsp_to_tgt_rsp_rerror.read(); + + if (((is_last_word or is_error) and not is_ll) or + (r_tgt_rsp_key_sent.read() and is_ll)) + { + // Last word sent in case of READ or second flit sent in case if LL + r_tgt_rsp_key_sent = false; + r_xram_rsp_to_tgt_rsp_req = false; + r_tgt_rsp_fsm = TGT_RSP_XRAM_IDLE; + } + else + { + if (is_ll) { - // Last word sent in case of READ or second flit sent in case if LL - r_tgt_rsp_key_sent = false; - r_xram_rsp_to_tgt_rsp_req = false; - r_tgt_rsp_fsm = TGT_RSP_XRAM_IDLE; + r_tgt_rsp_key_sent = true; // Send second flit of ll } else { - if (is_ll) - { - r_tgt_rsp_key_sent = true; // Send second flit of ll - } - else - { - r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1; // Send next word of read - } + r_tgt_rsp_cpt = r_tgt_rsp_cpt.read() + 1; // Send next word of read } } - break; - } - /////////////////////// + } + break; + } + /////////////////////// case TGT_RSP_MULTI_ACK: // send the write response after coherence transaction - { - if (p_vci_tgt.rspack) - { + { + if (p_vci_tgt.rspack) + { #if DEBUG_MEMC_TGT_RSP - if (m_debug) - std::cout << " Write response after coherence transaction" - << " / rsrcid = " << std::hex << r_multi_ack_to_tgt_rsp_srcid.read() - << " / rtrdid = " << r_multi_ack_to_tgt_rsp_trdid.read() - << " / rpktid = " << r_multi_ack_to_tgt_rsp_pktid.read() << std::endl; -#endif - r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK_IDLE; - r_multi_ack_to_tgt_rsp_req = false; - } - break; - } + if (m_debug) + { + std::cout << " Write response after coherence transaction" + << " / rsrcid = " << std::hex << r_multi_ack_to_tgt_rsp_srcid.read() + << " / rtrdid = " << r_multi_ack_to_tgt_rsp_trdid.read() + << " / rpktid = " << r_multi_ack_to_tgt_rsp_pktid.read() << std::endl; + } +#endif + r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK_IDLE; + r_multi_ack_to_tgt_rsp_req = false; + } + break; + } } // end switch tgt_rsp_fsm @@ -7489,5 +7805,5 @@ // - The XRAM_RSP FSM initiates broadcast/multicast invalidate transaction and sets // a new entry in the IVT - // - The CONFIG FSM does the same thing as the XRAM_RSP FSM + // - The CONFIG FSM does the same thing as the XRAM_RSP FSM // - The CLEANUP FSM complete those trasactions and erase the IVT entry. // The resource is always allocated. @@ -7536,5 +7852,5 @@ /////////////////////// case ALLOC_IVT_CLEANUP: // allocated to CLEANUP FSM - if ((r_cleanup_fsm.read() != CLEANUP_IVT_LOCK ) and + if ((r_cleanup_fsm.read() != CLEANUP_IVT_LOCK) and (r_cleanup_fsm.read() != CLEANUP_IVT_DECREMENT)) { @@ -7619,9 +7935,9 @@ ////////////////////// case ALLOC_DIR_CONFIG: // allocated to CONFIG FSM - if ((r_config_fsm.read() != CONFIG_DIR_REQ) and - (r_config_fsm.read() != CONFIG_DIR_ACCESS) and - (r_config_fsm.read() != CONFIG_TRT_LOCK) and - (r_config_fsm.read() != CONFIG_TRT_SET) and - (r_config_fsm.read() != CONFIG_IVT_LOCK)) + if ((r_config_fsm.read() != CONFIG_DIR_REQ) and + (r_config_fsm.read() != CONFIG_DIR_ACCESS) and + (r_config_fsm.read() != CONFIG_TRT_LOCK) and + (r_config_fsm.read() != CONFIG_TRT_SET) and + (r_config_fsm.read() != CONFIG_IVT_LOCK)) { if (r_read_fsm.read() == READ_DIR_REQ) @@ -7644,11 +7960,11 @@ //////////////////// case ALLOC_DIR_READ: // allocated to READ FSM - if (((r_read_fsm.read() != READ_DIR_REQ) and - (r_read_fsm.read() != READ_DIR_LOCK) and - (r_read_fsm.read() != READ_TRT_LOCK) and - (r_read_fsm.read() != READ_HEAP_REQ)) - or - ((r_read_fsm.read() == READ_TRT_LOCK) and - (r_alloc_trt_fsm.read() == ALLOC_TRT_READ))) + if (((r_read_fsm.read() != READ_DIR_REQ) and + (r_read_fsm.read() != READ_DIR_LOCK) and + (r_read_fsm.read() != READ_TRT_LOCK) and + (r_read_fsm.read() != READ_HEAP_REQ)) + or + ((r_read_fsm.read() == READ_TRT_LOCK) and + (r_alloc_trt_fsm.read() == ALLOC_TRT_READ))) { if (r_write_fsm.read() == WRITE_DIR_REQ) @@ -7671,19 +7987,19 @@ ///////////////////// case ALLOC_DIR_WRITE: // allocated to WRITE FSM - if (((r_write_fsm.read() != WRITE_DIR_REQ) and - (r_write_fsm.read() != WRITE_DIR_LOCK) and - (r_write_fsm.read() != WRITE_BC_DIR_READ) and - (r_write_fsm.read() != WRITE_DIR_HIT) and - (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and - (r_write_fsm.read() != WRITE_BC_IVT_LOCK) and - (r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and - (r_write_fsm.read() != WRITE_UPT_LOCK) and - (r_write_fsm.read() != WRITE_UPT_HEAP_LOCK)) - or - ((r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) and - (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE)) - or - ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) and - (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE))) + if (((r_write_fsm.read() != WRITE_DIR_REQ) and + (r_write_fsm.read() != WRITE_DIR_LOCK) and + (r_write_fsm.read() != WRITE_BC_DIR_READ) and + (r_write_fsm.read() != WRITE_DIR_HIT) and + (r_write_fsm.read() != WRITE_BC_TRT_LOCK) and + (r_write_fsm.read() != WRITE_BC_IVT_LOCK) and + (r_write_fsm.read() != WRITE_MISS_TRT_LOCK) and + (r_write_fsm.read() != WRITE_UPT_LOCK) and + (r_write_fsm.read() != WRITE_UPT_HEAP_LOCK)) + or + ((r_write_fsm.read() == WRITE_UPT_HEAP_LOCK) and + (r_alloc_heap_fsm.read() == ALLOC_HEAP_WRITE)) + or + ((r_write_fsm.read() == WRITE_MISS_TRT_LOCK) and + (r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE))) { if (r_cas_fsm.read() == CAS_DIR_REQ) @@ -7706,23 +8022,23 @@ /////////////////// case ALLOC_DIR_CAS: // allocated to CAS FSM - if (((r_cas_fsm.read() != CAS_DIR_REQ) and - (r_cas_fsm.read() != CAS_DIR_LOCK) and - (r_cas_fsm.read() != CAS_DIR_HIT_READ) and - (r_cas_fsm.read() != CAS_DIR_HIT_COMPARE) and - (r_cas_fsm.read() != CAS_DIR_HIT_WRITE) and - (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and - (r_cas_fsm.read() != CAS_BC_IVT_LOCK) and - (r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and - (r_cas_fsm.read() != CAS_UPT_LOCK) and - (r_cas_fsm.read() != CAS_UPT_HEAP_LOCK)) - or - ((r_cas_fsm.read() == CAS_UPT_HEAP_LOCK) and - (r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS)) - or - ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) and - (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS))) + if (((r_cas_fsm.read() != CAS_DIR_REQ) and + (r_cas_fsm.read() != CAS_DIR_LOCK) and + (r_cas_fsm.read() != CAS_DIR_HIT_READ) and + (r_cas_fsm.read() != CAS_DIR_HIT_COMPARE) and + (r_cas_fsm.read() != CAS_DIR_HIT_WRITE) and + (r_cas_fsm.read() != CAS_BC_TRT_LOCK) and + (r_cas_fsm.read() != CAS_BC_IVT_LOCK) and + (r_cas_fsm.read() != CAS_MISS_TRT_LOCK) and + (r_cas_fsm.read() != CAS_UPT_LOCK) and + (r_cas_fsm.read() != CAS_UPT_HEAP_LOCK)) + or + ((r_cas_fsm.read() == CAS_UPT_HEAP_LOCK) and + (r_alloc_heap_fsm.read() == ALLOC_HEAP_CAS)) + or + ((r_cas_fsm.read() == CAS_MISS_TRT_LOCK) and + (r_alloc_trt_fsm.read() == ALLOC_TRT_CAS))) { if (r_cleanup_fsm.read() == CLEANUP_DIR_REQ) - r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; + r_alloc_dir_fsm = ALLOC_DIR_CLEANUP; else if (r_xram_rsp_fsm.read() == XRAM_RSP_DIR_LOCK) @@ -7829,5 +8145,5 @@ r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; - else if (r_config_fsm.read() == CONFIG_TRT_LOCK ) + else if (r_config_fsm.read() == CONFIG_TRT_LOCK) r_alloc_trt_fsm = ALLOC_TRT_CONFIG; } @@ -7859,5 +8175,5 @@ r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; - else if (r_config_fsm.read() == CONFIG_TRT_LOCK ) + else if (r_config_fsm.read() == CONFIG_TRT_LOCK) r_alloc_trt_fsm = ALLOC_TRT_CONFIG; @@ -7888,5 +8204,5 @@ r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; - else if (r_config_fsm.read() == CONFIG_TRT_LOCK ) + else if (r_config_fsm.read() == CONFIG_TRT_LOCK) r_alloc_trt_fsm = ALLOC_TRT_CONFIG; @@ -7916,5 +8232,5 @@ r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; - else if (r_config_fsm.read() == CONFIG_TRT_LOCK ) + else if (r_config_fsm.read() == CONFIG_TRT_LOCK) r_alloc_trt_fsm = ALLOC_TRT_CONFIG; @@ -7944,5 +8260,5 @@ r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; - else if (r_config_fsm.read() == CONFIG_TRT_LOCK ) + else if (r_config_fsm.read() == CONFIG_TRT_LOCK) r_alloc_trt_fsm = ALLOC_TRT_CONFIG; @@ -8208,13 +8524,13 @@ ///////////////////////////////////////////////////////////////////// - m_cmd_read_addr_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, + m_cmd_read_addr_fifo.update(cmd_read_fifo_get, cmd_read_fifo_put, p_vci_tgt.address.read()); - m_cmd_read_length_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, - p_vci_tgt.plen.read() >> 2 ); - m_cmd_read_srcid_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, + m_cmd_read_length_fifo.update(cmd_read_fifo_get, cmd_read_fifo_put, + p_vci_tgt.plen.read() >> 2); + m_cmd_read_srcid_fifo.update(cmd_read_fifo_get, cmd_read_fifo_put, p_vci_tgt.srcid.read()); - m_cmd_read_trdid_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, + m_cmd_read_trdid_fifo.update(cmd_read_fifo_get, cmd_read_fifo_put, p_vci_tgt.trdid.read()); - m_cmd_read_pktid_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, + m_cmd_read_pktid_fifo.update(cmd_read_fifo_get, cmd_read_fifo_put, p_vci_tgt.pktid.read()); @@ -8223,17 +8539,17 @@ ///////////////////////////////////////////////////////////////////// - m_cmd_write_addr_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put, + m_cmd_write_addr_fifo.update(cmd_write_fifo_get, cmd_write_fifo_put, (addr_t)p_vci_tgt.address.read()); - m_cmd_write_eop_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put, + m_cmd_write_eop_fifo.update(cmd_write_fifo_get, cmd_write_fifo_put, p_vci_tgt.eop.read()); - m_cmd_write_srcid_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put, + m_cmd_write_srcid_fifo.update(cmd_write_fifo_get, cmd_write_fifo_put, p_vci_tgt.srcid.read()); - m_cmd_write_trdid_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put, + m_cmd_write_trdid_fifo.update(cmd_write_fifo_get, cmd_write_fifo_put, p_vci_tgt.trdid.read()); - m_cmd_write_pktid_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put, + m_cmd_write_pktid_fifo.update(cmd_write_fifo_get, cmd_write_fifo_put, p_vci_tgt.pktid.read()); - m_cmd_write_data_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put, + m_cmd_write_data_fifo.update(cmd_write_fifo_get, cmd_write_fifo_put, p_vci_tgt.wdata.read()); - m_cmd_write_be_fifo.update( cmd_write_fifo_get, cmd_write_fifo_put, + m_cmd_write_be_fifo.update(cmd_write_fifo_get, cmd_write_fifo_put, p_vci_tgt.be.read()); @@ -8242,15 +8558,15 @@ //////////////////////////////////////////////////////////////////////////////////// - m_cmd_cas_addr_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put, + m_cmd_cas_addr_fifo.update(cmd_cas_fifo_get, cmd_cas_fifo_put, (addr_t)p_vci_tgt.address.read()); - m_cmd_cas_eop_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put, + m_cmd_cas_eop_fifo.update(cmd_cas_fifo_get, cmd_cas_fifo_put, p_vci_tgt.eop.read()); - m_cmd_cas_srcid_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put, + m_cmd_cas_srcid_fifo.update(cmd_cas_fifo_get, cmd_cas_fifo_put, p_vci_tgt.srcid.read()); - m_cmd_cas_trdid_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put, + m_cmd_cas_trdid_fifo.update(cmd_cas_fifo_get, cmd_cas_fifo_put, p_vci_tgt.trdid.read()); - m_cmd_cas_pktid_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put, + m_cmd_cas_pktid_fifo.update(cmd_cas_fifo_get, cmd_cas_fifo_put, p_vci_tgt.pktid.read()); - m_cmd_cas_wdata_fifo.update( cmd_cas_fifo_get, cmd_cas_fifo_put, + m_cmd_cas_wdata_fifo.update(cmd_cas_fifo_get, cmd_cas_fifo_put, p_vci_tgt.wdata.read()); @@ -8259,6 +8575,6 @@ //////////////////////////////////////////////////////////////////////////////////// - m_cc_receive_to_cleanup_fifo.update( cc_receive_to_cleanup_fifo_get, - cc_receive_to_cleanup_fifo_put, + m_cc_receive_to_cleanup_fifo.update(cc_receive_to_cleanup_fifo_get, + cc_receive_to_cleanup_fifo_put, p_dspin_p2m.data.read()); @@ -8267,6 +8583,6 @@ //////////////////////////////////////////////////////////////////////////////////// - m_cc_receive_to_multi_ack_fifo.update( cc_receive_to_multi_ack_fifo_get, - cc_receive_to_multi_ack_fifo_put, + m_cc_receive_to_multi_ack_fifo.update(cc_receive_to_multi_ack_fifo_get, + cc_receive_to_multi_ack_fifo_put, p_dspin_p2m.data.read()); @@ -8275,10 +8591,10 @@ //////////////////////////////////////////////////////////////////////////////////// - m_write_to_cc_send_inst_fifo.update( write_to_cc_send_fifo_get, + m_write_to_cc_send_inst_fifo.update(write_to_cc_send_fifo_get, write_to_cc_send_fifo_put, - write_to_cc_send_fifo_inst ); - m_write_to_cc_send_srcid_fifo.update( write_to_cc_send_fifo_get, + write_to_cc_send_fifo_inst); + m_write_to_cc_send_srcid_fifo.update(write_to_cc_send_fifo_get, write_to_cc_send_fifo_put, - write_to_cc_send_fifo_srcid ); + write_to_cc_send_fifo_srcid); //////////////////////////////////////////////////////////////////////////////////// @@ -8286,10 +8602,10 @@ //////////////////////////////////////////////////////////////////////////////////// - m_config_to_cc_send_inst_fifo.update( config_to_cc_send_fifo_get, + m_config_to_cc_send_inst_fifo.update(config_to_cc_send_fifo_get, config_to_cc_send_fifo_put, - config_to_cc_send_fifo_inst ); - m_config_to_cc_send_srcid_fifo.update( config_to_cc_send_fifo_get, + config_to_cc_send_fifo_inst); + m_config_to_cc_send_srcid_fifo.update(config_to_cc_send_fifo_get, config_to_cc_send_fifo_put, - config_to_cc_send_fifo_srcid ); + config_to_cc_send_fifo_srcid); //////////////////////////////////////////////////////////////////////////////////// @@ -8297,10 +8613,10 @@ //////////////////////////////////////////////////////////////////////////////////// - m_xram_rsp_to_cc_send_inst_fifo.update( xram_rsp_to_cc_send_fifo_get, + m_xram_rsp_to_cc_send_inst_fifo.update(xram_rsp_to_cc_send_fifo_get, xram_rsp_to_cc_send_fifo_put, - xram_rsp_to_cc_send_fifo_inst ); - m_xram_rsp_to_cc_send_srcid_fifo.update( xram_rsp_to_cc_send_fifo_get, + xram_rsp_to_cc_send_fifo_inst); + m_xram_rsp_to_cc_send_srcid_fifo.update(xram_rsp_to_cc_send_fifo_get, xram_rsp_to_cc_send_fifo_put, - xram_rsp_to_cc_send_fifo_srcid ); + xram_rsp_to_cc_send_fifo_srcid); //////////////////////////////////////////////////////////////////////////////////// @@ -8308,10 +8624,10 @@ //////////////////////////////////////////////////////////////////////////////////// - m_cas_to_cc_send_inst_fifo.update( cas_to_cc_send_fifo_get, + m_cas_to_cc_send_inst_fifo.update(cas_to_cc_send_fifo_get, cas_to_cc_send_fifo_put, - cas_to_cc_send_fifo_inst ); - m_cas_to_cc_send_srcid_fifo.update( cas_to_cc_send_fifo_get, + cas_to_cc_send_fifo_inst); + m_cas_to_cc_send_srcid_fifo.update(cas_to_cc_send_fifo_get, cas_to_cc_send_fifo_put, - cas_to_cc_send_fifo_srcid ); + cas_to_cc_send_fifo_srcid); m_cpt_cycles++; @@ -8320,11 +8636,11 @@ // The three sources of (increment / decrement) are CONFIG / CLEANUP / IXR_RSP FSMs //////////////////////////////////////////////////////////////////////////////////// - if ( config_rsp_lines_incr and not - (config_rsp_lines_cleanup_decr or config_rsp_lines_ixr_rsp_decr) ) + if (config_rsp_lines_incr and not + (config_rsp_lines_cleanup_decr or config_rsp_lines_ixr_rsp_decr)) { r_config_rsp_lines = r_config_rsp_lines.read() + 1; } - if ( not config_rsp_lines_incr and - (config_rsp_lines_cleanup_decr or config_rsp_lines_ixr_rsp_decr) ) + if (not config_rsp_lines_incr and + (config_rsp_lines_cleanup_decr or config_rsp_lines_ixr_rsp_decr)) { r_config_rsp_lines = r_config_rsp_lines.read() - 1; @@ -8338,22 +8654,22 @@ { #if MONITOR_MEMCACHE_FSM == 1 - p_read_fsm.write (r_read_fsm.read() ); - p_write_fsm.write (r_write_fsm.read() ); - p_xram_rsp_fsm.write (r_xram_rsp_fsm.read() ); - p_cas_fsm.write (r_cas_fsm.read() ); - p_cleanup_fsm.write (r_cleanup_fsm.read() ); - p_config_fsm.write (r_config_fsm.read() ); - p_alloc_heap_fsm.write (r_alloc_heap_fsm.read() ); - p_alloc_dir_fsm.write (r_alloc_dir_fsm.read() ); - p_alloc_trt_fsm.write (r_alloc_trt_fsm.read() ); - p_alloc_upt_fsm.write (r_alloc_upt_fsm.read() ); - p_alloc_ivt_fsm.write (r_alloc_ivt_fsm.read() ); - p_tgt_cmd_fsm.write (r_tgt_cmd_fsm.read() ); - p_tgt_rsp_fsm.write (r_tgt_rsp_fsm.read() ); - p_ixr_cmd_fsm.write (r_ixr_cmd_fsm.read() ); - p_ixr_rsp_fsm.write (r_ixr_rsp_fsm.read() ); - p_cc_send_fsm.write (r_cc_send_fsm.read() ); - p_cc_receive_fsm.write (r_cc_receive_fsm.read() ); - p_multi_ack_fsm.write (r_multi_ack_fsm.read() ); + p_read_fsm.write (r_read_fsm.read()); + p_write_fsm.write (r_write_fsm.read()); + p_xram_rsp_fsm.write (r_xram_rsp_fsm.read()); + p_cas_fsm.write (r_cas_fsm.read()); + p_cleanup_fsm.write (r_cleanup_fsm.read()); + p_config_fsm.write (r_config_fsm.read()); + p_alloc_heap_fsm.write(r_alloc_heap_fsm.read()); + p_alloc_dir_fsm.write (r_alloc_dir_fsm.read()); + p_alloc_trt_fsm.write (r_alloc_trt_fsm.read()); + p_alloc_upt_fsm.write (r_alloc_upt_fsm.read()); + p_alloc_ivt_fsm.write (r_alloc_ivt_fsm.read()); + p_tgt_cmd_fsm.write (r_tgt_cmd_fsm.read()); + p_tgt_rsp_fsm.write (r_tgt_rsp_fsm.read()); + p_ixr_cmd_fsm.write (r_ixr_cmd_fsm.read()); + p_ixr_rsp_fsm.write (r_ixr_rsp_fsm.read()); + p_cc_send_fsm.write (r_cc_send_fsm.read()); + p_cc_receive_fsm.write(r_cc_receive_fsm.read()); + p_multi_ack_fsm.write (r_multi_ack_fsm.read()); #endif @@ -8364,17 +8680,17 @@ // DATA width is 8 bytes // The following values are not transmitted to XRAM - // p_vci_ixr.be - // p_vci_ixr.pktid - // p_vci_ixr.cons - // p_vci_ixr.wrap - // p_vci_ixr.contig - // p_vci_ixr.clen - // p_vci_ixr.cfixed + // p_vci_ixr.be + // p_vci_ixr.pktid + // p_vci_ixr.cons + // p_vci_ixr.wrap + // p_vci_ixr.contig + // p_vci_ixr.clen + // p_vci_ixr.cfixed p_vci_ixr.plen = 64; p_vci_ixr.srcid = m_srcid_x; p_vci_ixr.trdid = r_ixr_cmd_trdid.read(); - p_vci_ixr.address = (addr_t)r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2); - p_vci_ixr.be = 0xFF; + p_vci_ixr.address = (addr_t)r_ixr_cmd_address.read() + (r_ixr_cmd_word.read() << 2); + p_vci_ixr.be = 0xFF; p_vci_ixr.pktid = 0; p_vci_ixr.cons = false; @@ -8394,15 +8710,15 @@ if (r_ixr_cmd_get.read()) // GET { - p_vci_ixr.cmd = vci_param_ext::CMD_READ; - p_vci_ixr.wdata = 0; - p_vci_ixr.eop = true; + p_vci_ixr.cmd = vci_param_ext::CMD_READ; + p_vci_ixr.wdata = 0; + p_vci_ixr.eop = true; } else // PUT { - size_t word = r_ixr_cmd_word.read(); - p_vci_ixr.cmd = vci_param_ext::CMD_WRITE; - p_vci_ixr.wdata = ((wide_data_t)(r_ixr_cmd_wdata[word].read())) | - ((wide_data_t)(r_ixr_cmd_wdata[word+1].read()) << 32); - p_vci_ixr.eop = (word == (m_words-2)); + size_t word = r_ixr_cmd_word.read(); + p_vci_ixr.cmd = vci_param_ext::CMD_WRITE; + p_vci_ixr.wdata = ((wide_data_t)(r_ixr_cmd_wdata[word].read())) | + ((wide_data_t) (r_ixr_cmd_wdata[word + 1].read()) << 32); + p_vci_ixr.eop = (word == (m_words - 2)); } } @@ -8418,5 +8734,5 @@ if ((r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ) or (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE)) - { + { p_vci_ixr.rspack = (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP); } @@ -8430,5 +8746,5 @@ //////////////////////////////////////////////////// - switch((tgt_cmd_fsm_state_e) r_tgt_cmd_fsm.read()) + switch ((tgt_cmd_fsm_state_e) r_tgt_cmd_fsm.read()) { case TGT_CMD_IDLE: @@ -8443,11 +8759,10 @@ addr_t cell = (addr_lsb / vci_param_int::B); - size_t regr = cell & - m_config_regr_idx_mask; + size_t regr = cell & m_config_regr_idx_mask; size_t func = (cell >> m_config_regr_width) & m_config_func_idx_mask; - switch(func) + switch (func) { case MEMC_CONFIG: @@ -8491,5 +8806,5 @@ //////////////////////////////////////////////////// - switch(r_tgt_rsp_fsm.read()) + switch (r_tgt_rsp_fsm.read()) { case TGT_RSP_CONFIG_IDLE: @@ -8501,96 +8816,94 @@ case TGT_RSP_MULTI_ACK_IDLE: case TGT_RSP_CLEANUP_IDLE: - { - p_vci_tgt.rspval = false; - p_vci_tgt.rsrcid = 0; - p_vci_tgt.rdata = 0; - p_vci_tgt.rpktid = 0; - p_vci_tgt.rtrdid = 0; - p_vci_tgt.rerror = 0; - p_vci_tgt.reop = false; - break; - } + { + p_vci_tgt.rspval = false; + p_vci_tgt.rsrcid = 0; + p_vci_tgt.rdata = 0; + p_vci_tgt.rpktid = 0; + p_vci_tgt.rtrdid = 0; + p_vci_tgt.rerror = 0; + p_vci_tgt.reop = false; + break; + } case TGT_RSP_CONFIG: - { - p_vci_tgt.rspval = true; - p_vci_tgt.rdata = 0; - p_vci_tgt.rsrcid = r_config_to_tgt_rsp_srcid.read(); - p_vci_tgt.rtrdid = r_config_to_tgt_rsp_trdid.read(); - p_vci_tgt.rpktid = r_config_to_tgt_rsp_pktid.read(); - p_vci_tgt.rerror = r_config_to_tgt_rsp_error.read(); - p_vci_tgt.reop = true; - - break; - } + { + p_vci_tgt.rspval = true; + p_vci_tgt.rdata = 0; + p_vci_tgt.rsrcid = r_config_to_tgt_rsp_srcid.read(); + p_vci_tgt.rtrdid = r_config_to_tgt_rsp_trdid.read(); + p_vci_tgt.rpktid = r_config_to_tgt_rsp_pktid.read(); + p_vci_tgt.rerror = r_config_to_tgt_rsp_error.read(); + p_vci_tgt.reop = true; + break; + } case TGT_RSP_TGT_CMD: - { - p_vci_tgt.rspval = true; - p_vci_tgt.rdata = r_tgt_cmd_to_tgt_rsp_rdata.read(); - p_vci_tgt.rsrcid = r_tgt_cmd_to_tgt_rsp_srcid.read(); - p_vci_tgt.rtrdid = r_tgt_cmd_to_tgt_rsp_trdid.read(); - p_vci_tgt.rpktid = r_tgt_cmd_to_tgt_rsp_pktid.read(); - p_vci_tgt.rerror = r_tgt_cmd_to_tgt_rsp_error.read(); - p_vci_tgt.reop = true; - - break; - } + { + p_vci_tgt.rspval = true; + p_vci_tgt.rdata = r_tgt_cmd_to_tgt_rsp_rdata.read(); + p_vci_tgt.rsrcid = r_tgt_cmd_to_tgt_rsp_srcid.read(); + p_vci_tgt.rtrdid = r_tgt_cmd_to_tgt_rsp_trdid.read(); + p_vci_tgt.rpktid = r_tgt_cmd_to_tgt_rsp_pktid.read(); + p_vci_tgt.rerror = r_tgt_cmd_to_tgt_rsp_error.read(); + p_vci_tgt.reop = true; + break; + } case TGT_RSP_READ: - { - uint32_t last_word_idx = r_read_to_tgt_rsp_word.read() + r_read_to_tgt_rsp_length - 1; - bool is_last_word = (r_tgt_rsp_cpt.read() == last_word_idx); - bool is_ll = ((r_read_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL); - - p_vci_tgt.rspval = true; - - if (is_ll and not r_tgt_rsp_key_sent.read()) - { - // LL response first flit - p_vci_tgt.rdata = r_read_to_tgt_rsp_ll_key.read(); - } - else - { - // LL response second flit or READ response - p_vci_tgt.rdata = r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read(); - } - - p_vci_tgt.rsrcid = r_read_to_tgt_rsp_srcid.read(); - p_vci_tgt.rtrdid = r_read_to_tgt_rsp_trdid.read(); - p_vci_tgt.rpktid = r_read_to_tgt_rsp_pktid.read(); - p_vci_tgt.rerror = 0; - p_vci_tgt.reop = (is_last_word and not is_ll) or (r_tgt_rsp_key_sent.read() and is_ll); - break; - } + { + uint32_t last_word_idx = r_read_to_tgt_rsp_word.read() + r_read_to_tgt_rsp_length - 1; + bool is_last_word = (r_tgt_rsp_cpt.read() == last_word_idx); + bool is_ll = ((r_read_to_tgt_rsp_pktid.read() & 0x7) == TYPE_LL); + + p_vci_tgt.rspval = true; + + if (is_ll and not r_tgt_rsp_key_sent.read()) + { + // LL response first flit + p_vci_tgt.rdata = r_read_to_tgt_rsp_ll_key.read(); + } + else + { + // LL response second flit or READ response + p_vci_tgt.rdata = r_read_to_tgt_rsp_data[r_tgt_rsp_cpt.read()].read(); + } + + p_vci_tgt.rsrcid = r_read_to_tgt_rsp_srcid.read(); + p_vci_tgt.rtrdid = r_read_to_tgt_rsp_trdid.read(); + p_vci_tgt.rpktid = r_read_to_tgt_rsp_pktid.read(); + p_vci_tgt.rerror = 0; + p_vci_tgt.reop = (is_last_word and not is_ll) or (r_tgt_rsp_key_sent.read() and is_ll); + break; + } case TGT_RSP_WRITE: - p_vci_tgt.rspval = true; + p_vci_tgt.rspval = true; if (((r_write_to_tgt_rsp_pktid.read() & 0x7) == TYPE_SC) and r_write_to_tgt_rsp_sc_fail.read()) - p_vci_tgt.rdata = 1; + p_vci_tgt.rdata = 1; else - p_vci_tgt.rdata = 0; - p_vci_tgt.rsrcid = r_write_to_tgt_rsp_srcid.read(); - p_vci_tgt.rtrdid = r_write_to_tgt_rsp_trdid.read(); - p_vci_tgt.rpktid = r_write_to_tgt_rsp_pktid.read(); - p_vci_tgt.rerror = 0; - p_vci_tgt.reop = true; + p_vci_tgt.rdata = 0; + p_vci_tgt.rsrcid = r_write_to_tgt_rsp_srcid.read(); + p_vci_tgt.rtrdid = r_write_to_tgt_rsp_trdid.read(); + p_vci_tgt.rpktid = r_write_to_tgt_rsp_pktid.read(); + p_vci_tgt.rerror = 0; + p_vci_tgt.reop = true; break; case TGT_RSP_CLEANUP: - p_vci_tgt.rspval = true; - p_vci_tgt.rdata = 0; - p_vci_tgt.rsrcid = r_cleanup_to_tgt_rsp_srcid.read(); - p_vci_tgt.rtrdid = r_cleanup_to_tgt_rsp_trdid.read(); - p_vci_tgt.rpktid = r_cleanup_to_tgt_rsp_pktid.read(); - p_vci_tgt.rerror = 0; // Can be a CAS rsp - p_vci_tgt.reop = true; + p_vci_tgt.rspval = true; + p_vci_tgt.rdata = 0; + p_vci_tgt.rsrcid = r_cleanup_to_tgt_rsp_srcid.read(); + p_vci_tgt.rtrdid = r_cleanup_to_tgt_rsp_trdid.read(); + p_vci_tgt.rpktid = r_cleanup_to_tgt_rsp_pktid.read(); + p_vci_tgt.rerror = 0; // Can be a CAS rsp + p_vci_tgt.reop = true; break; case TGT_RSP_CAS: - p_vci_tgt.rspval = true; - p_vci_tgt.rdata = r_cas_to_tgt_rsp_data.read(); - p_vci_tgt.rsrcid = r_cas_to_tgt_rsp_srcid.read(); - p_vci_tgt.rtrdid = r_cas_to_tgt_rsp_trdid.read(); - p_vci_tgt.rpktid = r_cas_to_tgt_rsp_pktid.read(); - p_vci_tgt.rerror = 0; - p_vci_tgt.reop = true; + p_vci_tgt.rspval = true; + p_vci_tgt.rdata = r_cas_to_tgt_rsp_data.read(); + p_vci_tgt.rsrcid = r_cas_to_tgt_rsp_srcid.read(); + p_vci_tgt.rtrdid = r_cas_to_tgt_rsp_trdid.read(); + p_vci_tgt.rpktid = r_cas_to_tgt_rsp_pktid.read(); + p_vci_tgt.rerror = 0; + p_vci_tgt.reop = true; break; @@ -8602,7 +8915,8 @@ bool is_error = r_xram_rsp_to_tgt_rsp_rerror.read(); - p_vci_tgt.rspval = true; - - if (is_ll and not r_tgt_rsp_key_sent.read()) { + p_vci_tgt.rspval = true; + + if (is_ll and not r_tgt_rsp_key_sent.read()) + { // LL response first flit p_vci_tgt.rdata = r_xram_rsp_to_tgt_rsp_ll_key.read(); @@ -8613,9 +8927,9 @@ } - p_vci_tgt.rsrcid = r_xram_rsp_to_tgt_rsp_srcid.read(); - p_vci_tgt.rtrdid = r_xram_rsp_to_tgt_rsp_trdid.read(); - p_vci_tgt.rpktid = r_xram_rsp_to_tgt_rsp_pktid.read(); - p_vci_tgt.rerror = is_error; - p_vci_tgt.reop = (((is_last_word or is_error) and not is_ll) or + p_vci_tgt.rsrcid = r_xram_rsp_to_tgt_rsp_srcid.read(); + p_vci_tgt.rtrdid = r_xram_rsp_to_tgt_rsp_trdid.read(); + p_vci_tgt.rpktid = r_xram_rsp_to_tgt_rsp_pktid.read(); + p_vci_tgt.rerror = is_error; + p_vci_tgt.reop = (((is_last_word or is_error) and not is_ll) or (r_tgt_rsp_key_sent.read() and is_ll)); break; @@ -8623,11 +8937,11 @@ case TGT_RSP_MULTI_ACK: - p_vci_tgt.rspval = true; - p_vci_tgt.rdata = 0; // Can be a CAS or SC rsp - p_vci_tgt.rsrcid = r_multi_ack_to_tgt_rsp_srcid.read(); - p_vci_tgt.rtrdid = r_multi_ack_to_tgt_rsp_trdid.read(); - p_vci_tgt.rpktid = r_multi_ack_to_tgt_rsp_pktid.read(); - p_vci_tgt.rerror = 0; - p_vci_tgt.reop = true; + p_vci_tgt.rspval = true; + p_vci_tgt.rdata = 0; // Can be a CAS or SC rsp + p_vci_tgt.rsrcid = r_multi_ack_to_tgt_rsp_srcid.read(); + p_vci_tgt.rtrdid = r_multi_ack_to_tgt_rsp_trdid.read(); + p_vci_tgt.rpktid = r_multi_ack_to_tgt_rsp_pktid.read(); + p_vci_tgt.rerror = 0; + p_vci_tgt.reop = true; break; } // end switch r_tgt_rsp_fsm @@ -8651,5 +8965,5 @@ p_dspin_m2p.data = 0; - switch(r_cc_send_fsm.read()) + switch (r_cc_send_fsm.read()) { /////////////////////////// @@ -8658,357 +8972,355 @@ case CC_SEND_WRITE_IDLE: case CC_SEND_CAS_IDLE: - { - break; - } - //////////////////////////////// + { + break; + } + //////////////////////////////// case CC_SEND_CONFIG_INVAL_HEADER: - { - uint8_t multi_inval_type; - if (m_config_to_cc_send_inst_fifo.read()) - { - multi_inval_type = DspinDhccpParam::TYPE_MULTI_INVAL_INST; - } - else - { - multi_inval_type = DspinDhccpParam::TYPE_MULTI_INVAL_DATA; - } - - uint64_t flit = 0; - uint64_t dest = m_config_to_cc_send_srcid_fifo.read() << - (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); - - DspinDhccpParam::dspin_set( flit, - dest, - DspinDhccpParam::MULTI_INVAL_DEST); - - DspinDhccpParam::dspin_set( flit, - r_config_to_cc_send_trdid.read(), - DspinDhccpParam::MULTI_INVAL_UPDT_INDEX); - - DspinDhccpParam::dspin_set( flit, - multi_inval_type, - DspinDhccpParam::M2P_TYPE); - p_dspin_m2p.write = true; - p_dspin_m2p.data = flit; - break; - } - //////////////////////////////// + { + uint8_t multi_inval_type; + if (m_config_to_cc_send_inst_fifo.read()) + { + multi_inval_type = DspinDhccpParam::TYPE_MULTI_INVAL_INST; + } + else + { + multi_inval_type = DspinDhccpParam::TYPE_MULTI_INVAL_DATA; + } + + uint64_t flit = 0; + uint64_t dest = m_config_to_cc_send_srcid_fifo.read() << + (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); + + DspinDhccpParam::dspin_set(flit, + dest, + DspinDhccpParam::MULTI_INVAL_DEST); + + DspinDhccpParam::dspin_set(flit, + r_config_to_cc_send_trdid.read(), + DspinDhccpParam::MULTI_INVAL_UPDT_INDEX); + + DspinDhccpParam::dspin_set(flit, + multi_inval_type, + DspinDhccpParam::M2P_TYPE); + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; + break; + } + //////////////////////////////// case CC_SEND_CONFIG_INVAL_NLINE: - { - uint64_t flit = 0; - DspinDhccpParam::dspin_set( flit, - r_config_to_cc_send_nline.read(), - DspinDhccpParam::MULTI_INVAL_NLINE); - p_dspin_m2p.eop = true; - p_dspin_m2p.write = true; - p_dspin_m2p.data = flit; - break; - } - /////////////////////////////////// + { + uint64_t flit = 0; + DspinDhccpParam::dspin_set(flit, + r_config_to_cc_send_nline.read(), + DspinDhccpParam::MULTI_INVAL_NLINE); + p_dspin_m2p.eop = true; + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; + break; + } + /////////////////////////////////// case CC_SEND_XRAM_RSP_INVAL_HEADER: - { - if (not m_xram_rsp_to_cc_send_inst_fifo.rok()) break; - - uint8_t multi_inval_type; - if (m_xram_rsp_to_cc_send_inst_fifo.read()) - { - multi_inval_type = DspinDhccpParam::TYPE_MULTI_INVAL_INST; - } - else - { - multi_inval_type = DspinDhccpParam::TYPE_MULTI_INVAL_DATA; - } - - uint64_t flit = 0; - uint64_t dest = m_xram_rsp_to_cc_send_srcid_fifo.read() << - (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); - - DspinDhccpParam::dspin_set( flit, - dest, - DspinDhccpParam::MULTI_INVAL_DEST); - - DspinDhccpParam::dspin_set( flit, - r_xram_rsp_to_cc_send_trdid.read(), - DspinDhccpParam::MULTI_INVAL_UPDT_INDEX); - - DspinDhccpParam::dspin_set( flit, - multi_inval_type, - DspinDhccpParam::M2P_TYPE); - p_dspin_m2p.write = true; - p_dspin_m2p.data = flit; - break; - } - - ////////////////////////////////// + { + if (not m_xram_rsp_to_cc_send_inst_fifo.rok()) break; + + uint8_t multi_inval_type; + if (m_xram_rsp_to_cc_send_inst_fifo.read()) + { + multi_inval_type = DspinDhccpParam::TYPE_MULTI_INVAL_INST; + } + else + { + multi_inval_type = DspinDhccpParam::TYPE_MULTI_INVAL_DATA; + } + + uint64_t flit = 0; + uint64_t dest = m_xram_rsp_to_cc_send_srcid_fifo.read() << + (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); + + DspinDhccpParam::dspin_set(flit, + dest, + DspinDhccpParam::MULTI_INVAL_DEST); + + DspinDhccpParam::dspin_set(flit, + r_xram_rsp_to_cc_send_trdid.read(), + DspinDhccpParam::MULTI_INVAL_UPDT_INDEX); + + DspinDhccpParam::dspin_set(flit, + multi_inval_type, + DspinDhccpParam::M2P_TYPE); + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; + break; + } + + ////////////////////////////////// case CC_SEND_XRAM_RSP_INVAL_NLINE: - { - uint64_t flit = 0; - - DspinDhccpParam::dspin_set( flit, - r_xram_rsp_to_cc_send_nline.read(), - DspinDhccpParam::MULTI_INVAL_NLINE); - p_dspin_m2p.eop = true; - p_dspin_m2p.write = true; - p_dspin_m2p.data = flit; - break; - } - - ///////////////////////////////////// + { + uint64_t flit = 0; + + DspinDhccpParam::dspin_set(flit, + r_xram_rsp_to_cc_send_nline.read(), + DspinDhccpParam::MULTI_INVAL_NLINE); + p_dspin_m2p.eop = true; + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; + break; + } + + ///////////////////////////////////// case CC_SEND_CONFIG_BRDCAST_HEADER: case CC_SEND_XRAM_RSP_BRDCAST_HEADER: case CC_SEND_WRITE_BRDCAST_HEADER: case CC_SEND_CAS_BRDCAST_HEADER: - { - uint64_t flit = 0; - - DspinDhccpParam::dspin_set( flit, - m_broadcast_boundaries, - DspinDhccpParam::BROADCAST_BOX); - - DspinDhccpParam::dspin_set( flit, - 1ULL, - DspinDhccpParam::M2P_BC); - p_dspin_m2p.write = true; - p_dspin_m2p.data = flit; - break; - } - //////////////////////////////////// + { + uint64_t flit = 0; + + DspinDhccpParam::dspin_set(flit, + m_broadcast_boundaries, + DspinDhccpParam::BROADCAST_BOX); + + DspinDhccpParam::dspin_set(flit, + 1ULL, + DspinDhccpParam::M2P_BC); + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; + break; + } + //////////////////////////////////// case CC_SEND_XRAM_RSP_BRDCAST_NLINE: - { - uint64_t flit = 0; - DspinDhccpParam::dspin_set( flit, - r_xram_rsp_to_cc_send_nline.read(), - DspinDhccpParam::BROADCAST_NLINE); - p_dspin_m2p.write = true; - p_dspin_m2p.eop = true; - p_dspin_m2p.data = flit; - break; - } - ////////////////////////////////// + { + uint64_t flit = 0; + DspinDhccpParam::dspin_set(flit, + r_xram_rsp_to_cc_send_nline.read(), + DspinDhccpParam::BROADCAST_NLINE); + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; + break; + } + ////////////////////////////////// case CC_SEND_CONFIG_BRDCAST_NLINE: - { - uint64_t flit = 0; - DspinDhccpParam::dspin_set( flit, - r_config_to_cc_send_nline.read(), - DspinDhccpParam::BROADCAST_NLINE); - p_dspin_m2p.write = true; - p_dspin_m2p.eop = true; - p_dspin_m2p.data = flit; - break; - } - ///////////////////////////////// + { + uint64_t flit = 0; + DspinDhccpParam::dspin_set(flit, + r_config_to_cc_send_nline.read(), + DspinDhccpParam::BROADCAST_NLINE); + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; + break; + } + ///////////////////////////////// case CC_SEND_WRITE_BRDCAST_NLINE: - { - uint64_t flit = 0; - DspinDhccpParam::dspin_set( flit, - r_write_to_cc_send_nline.read(), - DspinDhccpParam::BROADCAST_NLINE); - p_dspin_m2p.write = true; - p_dspin_m2p.eop = true; - p_dspin_m2p.data = flit; - break; - } - /////////////////////////////// + { + uint64_t flit = 0; + DspinDhccpParam::dspin_set(flit, + r_write_to_cc_send_nline.read(), + DspinDhccpParam::BROADCAST_NLINE); + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; + break; + } + /////////////////////////////// case CC_SEND_CAS_BRDCAST_NLINE: - { - uint64_t flit = 0; - DspinDhccpParam::dspin_set( flit, - r_cas_to_cc_send_nline.read(), - DspinDhccpParam::BROADCAST_NLINE); - p_dspin_m2p.write = true; - p_dspin_m2p.eop = true; - p_dspin_m2p.data = flit; - break; - } - /////////////////////////////// + { + uint64_t flit = 0; + DspinDhccpParam::dspin_set(flit, + r_cas_to_cc_send_nline.read(), + DspinDhccpParam::BROADCAST_NLINE); + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; + break; + } + /////////////////////////////// case CC_SEND_WRITE_UPDT_HEADER: - { - if (not m_write_to_cc_send_inst_fifo.rok()) break; - - uint8_t multi_updt_type; - if (m_write_to_cc_send_inst_fifo.read()) - { - multi_updt_type = DspinDhccpParam::TYPE_MULTI_UPDT_INST; - } - else - { - multi_updt_type = DspinDhccpParam::TYPE_MULTI_UPDT_DATA; - } - - uint64_t flit = 0; - uint64_t dest = - m_write_to_cc_send_srcid_fifo.read() << - (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); - - DspinDhccpParam::dspin_set( - flit, - dest, - DspinDhccpParam::MULTI_UPDT_DEST); - - DspinDhccpParam::dspin_set( - flit, - r_write_to_cc_send_trdid.read(), - DspinDhccpParam::MULTI_UPDT_UPDT_INDEX); - - DspinDhccpParam::dspin_set( - flit, - multi_updt_type, - DspinDhccpParam::M2P_TYPE); - - p_dspin_m2p.write = true; - p_dspin_m2p.data = flit; - - break; - } - ////////////////////////////// + { + if (not m_write_to_cc_send_inst_fifo.rok()) break; + + uint8_t multi_updt_type; + if (m_write_to_cc_send_inst_fifo.read()) + { + multi_updt_type = DspinDhccpParam::TYPE_MULTI_UPDT_INST; + } + else + { + multi_updt_type = DspinDhccpParam::TYPE_MULTI_UPDT_DATA; + } + + uint64_t flit = 0; + uint64_t dest = + m_write_to_cc_send_srcid_fifo.read() << + (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); + + DspinDhccpParam::dspin_set( + flit, + dest, + DspinDhccpParam::MULTI_UPDT_DEST); + + DspinDhccpParam::dspin_set( + flit, + r_write_to_cc_send_trdid.read(), + DspinDhccpParam::MULTI_UPDT_UPDT_INDEX); + + DspinDhccpParam::dspin_set( + flit, + multi_updt_type, + DspinDhccpParam::M2P_TYPE); + + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; + + break; + } + ////////////////////////////// case CC_SEND_WRITE_UPDT_NLINE: - { - uint64_t flit = 0; - - DspinDhccpParam::dspin_set( - flit, - r_write_to_cc_send_index.read(), - DspinDhccpParam::MULTI_UPDT_WORD_INDEX); - - DspinDhccpParam::dspin_set( - flit, - r_write_to_cc_send_nline.read(), - DspinDhccpParam::MULTI_UPDT_NLINE); - - p_dspin_m2p.write = true; - p_dspin_m2p.data = flit; - - break; - } - ///////////////////////////// + { + uint64_t flit = 0; + + DspinDhccpParam::dspin_set( + flit, + r_write_to_cc_send_index.read(), + DspinDhccpParam::MULTI_UPDT_WORD_INDEX); + + DspinDhccpParam::dspin_set( + flit, + r_write_to_cc_send_nline.read(), + DspinDhccpParam::MULTI_UPDT_NLINE); + + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; + + break; + } + ///////////////////////////// case CC_SEND_WRITE_UPDT_DATA: - { - - uint8_t multi_updt_cpt = - r_cc_send_cpt.read() + r_write_to_cc_send_index.read(); - - uint8_t multi_updt_be = r_write_to_cc_send_be[multi_updt_cpt].read(); - uint32_t multi_updt_data = r_write_to_cc_send_data[multi_updt_cpt].read(); - - uint64_t flit = 0; - - DspinDhccpParam::dspin_set( - flit, - multi_updt_be, - DspinDhccpParam::MULTI_UPDT_BE); - - DspinDhccpParam::dspin_set( - flit, - multi_updt_data, - DspinDhccpParam::MULTI_UPDT_DATA); - - p_dspin_m2p.write = true; - p_dspin_m2p.eop = (r_cc_send_cpt.read() == r_write_to_cc_send_count.read()); - p_dspin_m2p.data = flit; - - break; - } - //////////////////////////// + { + + uint8_t multi_updt_cpt = r_cc_send_cpt.read() + r_write_to_cc_send_index.read(); + uint8_t multi_updt_be = r_write_to_cc_send_be[multi_updt_cpt].read(); + uint32_t multi_updt_data = r_write_to_cc_send_data[multi_updt_cpt].read(); + + uint64_t flit = 0; + + DspinDhccpParam::dspin_set( + flit, + multi_updt_be, + DspinDhccpParam::MULTI_UPDT_BE); + + DspinDhccpParam::dspin_set( + flit, + multi_updt_data, + DspinDhccpParam::MULTI_UPDT_DATA); + + p_dspin_m2p.write = true; + p_dspin_m2p.eop = (r_cc_send_cpt.read() == r_write_to_cc_send_count.read()); + p_dspin_m2p.data = flit; + + break; + } + //////////////////////////// case CC_SEND_CAS_UPDT_HEADER: - { - if (not m_cas_to_cc_send_inst_fifo.rok()) break; - - uint8_t multi_updt_type; - if (m_cas_to_cc_send_inst_fifo.read()) - { - multi_updt_type = DspinDhccpParam::TYPE_MULTI_UPDT_INST; - } - else - { - multi_updt_type = DspinDhccpParam::TYPE_MULTI_UPDT_DATA; - } - - uint64_t flit = 0; - uint64_t dest = - m_cas_to_cc_send_srcid_fifo.read() << - (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); - - DspinDhccpParam::dspin_set( - flit, - dest, - DspinDhccpParam::MULTI_UPDT_DEST); - - DspinDhccpParam::dspin_set( - flit, - r_cas_to_cc_send_trdid.read(), - DspinDhccpParam::MULTI_UPDT_UPDT_INDEX); - - DspinDhccpParam::dspin_set( - flit, - multi_updt_type, - DspinDhccpParam::M2P_TYPE); - - p_dspin_m2p.write = true; - p_dspin_m2p.data = flit; - - break; - } - //////////////////////////// + { + if (not m_cas_to_cc_send_inst_fifo.rok()) break; + + uint8_t multi_updt_type; + if (m_cas_to_cc_send_inst_fifo.read()) + { + multi_updt_type = DspinDhccpParam::TYPE_MULTI_UPDT_INST; + } + else + { + multi_updt_type = DspinDhccpParam::TYPE_MULTI_UPDT_DATA; + } + + uint64_t flit = 0; + uint64_t dest = + m_cas_to_cc_send_srcid_fifo.read() << + (DspinDhccpParam::SRCID_WIDTH - vci_param_int::S); + + DspinDhccpParam::dspin_set( + flit, + dest, + DspinDhccpParam::MULTI_UPDT_DEST); + + DspinDhccpParam::dspin_set( + flit, + r_cas_to_cc_send_trdid.read(), + DspinDhccpParam::MULTI_UPDT_UPDT_INDEX); + + DspinDhccpParam::dspin_set( + flit, + multi_updt_type, + DspinDhccpParam::M2P_TYPE); + + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; + + break; + } + //////////////////////////// case CC_SEND_CAS_UPDT_NLINE: - { - uint64_t flit = 0; - - DspinDhccpParam::dspin_set( - flit, - r_cas_to_cc_send_index.read(), - DspinDhccpParam::MULTI_UPDT_WORD_INDEX); - - DspinDhccpParam::dspin_set( - flit, - r_cas_to_cc_send_nline.read(), - DspinDhccpParam::MULTI_UPDT_NLINE); - - p_dspin_m2p.write = true; - p_dspin_m2p.data = flit; - - break; - } - /////////////////////////// + { + uint64_t flit = 0; + + DspinDhccpParam::dspin_set( + flit, + r_cas_to_cc_send_index.read(), + DspinDhccpParam::MULTI_UPDT_WORD_INDEX); + + DspinDhccpParam::dspin_set( + flit, + r_cas_to_cc_send_nline.read(), + DspinDhccpParam::MULTI_UPDT_NLINE); + + p_dspin_m2p.write = true; + p_dspin_m2p.data = flit; + + break; + } + /////////////////////////// case CC_SEND_CAS_UPDT_DATA: - { - uint64_t flit = 0; - - DspinDhccpParam::dspin_set( - flit, - 0xF, - DspinDhccpParam::MULTI_UPDT_BE); - - DspinDhccpParam::dspin_set( - flit, - r_cas_to_cc_send_wdata.read(), - DspinDhccpParam::MULTI_UPDT_DATA); - - p_dspin_m2p.write = true; - p_dspin_m2p.eop = not r_cas_to_cc_send_is_long.read(); - p_dspin_m2p.data = flit; - - break; - } - //////////////////////////////// + { + uint64_t flit = 0; + + DspinDhccpParam::dspin_set( + flit, + 0xF, + DspinDhccpParam::MULTI_UPDT_BE); + + DspinDhccpParam::dspin_set( + flit, + r_cas_to_cc_send_wdata.read(), + DspinDhccpParam::MULTI_UPDT_DATA); + + p_dspin_m2p.write = true; + p_dspin_m2p.eop = not r_cas_to_cc_send_is_long.read(); + p_dspin_m2p.data = flit; + + break; + } + //////////////////////////////// case CC_SEND_CAS_UPDT_DATA_HIGH: - { - uint64_t flit = 0; - - DspinDhccpParam::dspin_set( - flit, - 0xF, - DspinDhccpParam::MULTI_UPDT_BE); - - DspinDhccpParam::dspin_set( - flit, - r_cas_to_cc_send_wdata_high.read(), - DspinDhccpParam::MULTI_UPDT_DATA); - - p_dspin_m2p.write = true; - p_dspin_m2p.eop = true; - p_dspin_m2p.data = flit; - - break; - } + { + uint64_t flit = 0; + + DspinDhccpParam::dspin_set( + flit, + 0xF, + DspinDhccpParam::MULTI_UPDT_BE); + + DspinDhccpParam::dspin_set( + flit, + r_cas_to_cc_send_wdata_high.read(), + DspinDhccpParam::MULTI_UPDT_DATA); + + p_dspin_m2p.write = true; + p_dspin_m2p.eop = true; + p_dspin_m2p.data = flit; + + break; + } } @@ -9068,22 +9380,22 @@ /////////////////////////////////////////////////////////////////// // - switch(r_cc_receive_fsm.read()) + switch (r_cc_receive_fsm.read()) { case CC_RECEIVE_IDLE: - { - p_dspin_p2m.read = false; - break; - } + { + p_dspin_p2m.read = false; + break; + } case CC_RECEIVE_CLEANUP: case CC_RECEIVE_CLEANUP_EOP: - { - p_dspin_p2m.read = m_cc_receive_to_cleanup_fifo.wok(); - break; - } + { + p_dspin_p2m.read = m_cc_receive_to_cleanup_fifo.wok(); + break; + } case CC_RECEIVE_MULTI_ACK: - { - p_dspin_p2m.read = m_cc_receive_to_multi_ack_fifo.wok(); - break; - } + { + p_dspin_p2m.read = m_cc_receive_to_multi_ack_fifo.wok(); + break; + } } // end switch r_cc_send_fsm