Changeset 805 for branches/RWT/modules/vci_cc_vcache_wrapper/caba/source
- Timestamp:
- Sep 15, 2014, 11:43:32 AM (10 years ago)
- Location:
- branches/RWT/modules/vci_cc_vcache_wrapper/caba/source
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
r771 r805 114 114 DCACHE_XTN_IC_FLUSH, 115 115 DCACHE_XTN_IC_INVAL_PA, 116 DCACHE_XTN_IC_PADDR_EXT, 116 117 DCACHE_XTN_IT_INVAL, 117 118 DCACHE_XTN_DC_FLUSH, … … 329 330 bool m_debug_ok; 330 331 332 uint32_t m_dcache_paddr_ext_reset; 333 uint32_t m_icache_paddr_ext_reset; 334 331 335 //////////////////////////////////////// 332 336 // Communication with processor ISS … … 396 400 sc_signal<bool> r_icache_tlb_rsp_error; // tlb miss response error 397 401 402 // Flip-Flop in ICACHE FSM for saving the cleanup victim request 403 sc_signal<bool> r_icache_cleanup_victim_req; 404 sc_signal<paddr_t> r_icache_cleanup_victim_nline; 398 405 399 406 // communication between ICACHE FSM and CC_SEND FSM … … 403 410 sc_signal<size_t> r_icache_cc_send_way; // ICACHE cc_send way 404 411 sc_signal<size_t> r_icache_cc_send_updt_tab_idx; // ICACHE cc_send update table index 405 406 // Filp-Flop in ICACHE FSM for saving the cleanup victim request 407 sc_signal<bool> r_icache_cleanup_victim_req; 408 sc_signal<paddr_t> r_icache_cleanup_victim_nline; 412 413 // Physical address extension for data access 414 sc_signal<uint32_t> r_icache_paddr_ext; // CP2 register (if vci_address > 32) 409 415 410 416 /////////////////////////////// … … 468 474 sc_signal<bool> r_dcache_cc_need_write; // activate the cache for writing 469 475 sc_signal<paddr_t> r_dcache_cc_inval_addr; // address for a cleanup transaction 470 sc_signal<uint32_t> r_dcache_cc_inval_data_cpt; 476 sc_signal<uint32_t> r_dcache_cc_inval_data_cpt; 471 477 472 478 // coherence clack handling … … 503 509 // Filp-Flop in DCACHE FSM for saving the cleanup victim request 504 510 sc_signal<bool> r_dcache_cleanup_victim_req; 505 sc_signal<bool> r_dcache_cleanup_victim_line_ncc; 506 sc_signal<bool> r_dcache_cleanup_victim_updt_data; 511 sc_signal<bool> r_dcache_cleanup_victim_line_ncc; 512 sc_signal<bool> r_dcache_cleanup_victim_updt_data; 507 513 sc_signal<paddr_t> r_dcache_cleanup_victim_nline; 508 514 … … 513 519 sc_signal<size_t> r_dcache_cc_send_way; // DCACHE cc_send way 514 520 sc_signal<size_t> r_dcache_cc_send_updt_tab_idx; // DCACHE cc_send update table index 515 521 516 522 // special registers for RWT 517 523 sc_signal<bool> r_dcache_cc_cleanup_updt_data; // Register for cleanup with data (wb updt) … … 519 525 sc_signal<bool> r_dcache_miss_victim_no_coherence; // Register for victim in no coherence mode 520 526 sc_signal<bool> r_dcache_line_no_coherence; // Register for line current in no coherence mode 521 sc_signal<bool> r_dcache_dirty_save; 527 sc_signal<bool> r_dcache_dirty_save; 522 528 sc_signal<uint32_t> r_cc_send_cpt_word; 523 529 sc_signal<uint32_t> r_dcache_miss_data_cpt; … … 559 565 GenericFifo<uint32_t> r_vci_rsp_fifo_icache; // response FIFO to ICACHE FSM 560 566 GenericFifo<uint32_t> r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM 561 567 562 568 563 569 //RWT 564 570 GenericFifo<bool> r_vci_rsp_fifo_rpktid; 565 GenericFifo<uint32_t> r_cc_send_data_fifo; 571 GenericFifo<uint32_t> r_cc_send_data_fifo; 566 572 567 573 /////////////////////////////////// … … 626 632 sc_signal<bool> r_dcache_llsc_valid; 627 633 628 634 629 635 sc_signal<bool> r_cache_frozen; 630 636 … … 806 812 } 807 813 814 ///////////////////////////////////////////////////////////// 815 // Set the m_dcache_paddr_ext_reset attribute 816 // 817 // The r_dcache_paddr_ext register will be initialized after 818 // reset with the m_dcache_paddr_ext_reset value 819 ///////////////////////////////////////////////////////////// 820 inline void set_dcache_paddr_ext_reset(uint32_t v) 821 { 822 m_dcache_paddr_ext_reset = v; 823 } 824 825 ///////////////////////////////////////////////////////////// 826 // Set the m_icache_paddr_ext_reset attribute 827 // 828 // The r_icache_paddr_ext register will be initialized after 829 // reset with the m_icache_paddr_ext_reset value 830 ///////////////////////////////////////////////////////////// 831 inline void set_icache_paddr_ext_reset(uint32_t v) 832 { 833 m_icache_paddr_ext_reset = v; 834 } 835 808 836 private: 809 837 void transition(); -
branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r773 r805 29 29 30 30 #include <cassert> 31 #include <signal.h> 32 31 33 #include "arithmetics.h" 32 34 #include "../include/vci_cc_vcache_wrapper.h" … … 86 88 "DCACHE_XTN_IC_FLUSH", 87 89 "DCACHE_XTN_IC_INVAL_PA", 90 "DCACHE_XTN_IC_PADDR_EXT", 88 91 "DCACHE_XTN_IT_INVAL", 89 92 "DCACHE_XTN_DC_FLUSH", … … 161 164 162 165 const char *cc_receive_fsm_state_str[] = { 163 "CC_RECEIVE_IDLE", 164 "CC_RECEIVE_BRDCAST_HEADER", 165 "CC_RECEIVE_BRDCAST_NLINE", 166 "CC_RECEIVE_INS_INVAL_HEADER", 167 "CC_RECEIVE_INS_INVAL_NLINE", 168 "CC_RECEIVE_INS_UPDT_HEADER", 169 "CC_RECEIVE_INS_UPDT_NLINE", 170 "CC_RECEIVE_INS_UPDT_DATA", 171 "CC_RECEIVE_DATA_INVAL_HEADER", 172 "CC_RECEIVE_DATA_INVAL_NLINE", 173 "CC_RECEIVE_DATA_UPDT_HEADER", 174 "CC_RECEIVE_DATA_UPDT_NLINE", 175 "CC_RECEIVE_DATA_UPDT_DATA", 166 "CC_RECEIVE_IDLE", 167 "CC_RECEIVE_BRDCAST_HEADER", 168 "CC_RECEIVE_BRDCAST_NLINE", 169 "CC_RECEIVE_INS_INVAL_HEADER", 170 "CC_RECEIVE_INS_INVAL_NLINE", 171 "CC_RECEIVE_INS_UPDT_HEADER", 172 "CC_RECEIVE_INS_UPDT_NLINE", 173 "CC_RECEIVE_INS_UPDT_DATA", 174 "CC_RECEIVE_DATA_INVAL_HEADER", 175 "CC_RECEIVE_DATA_INVAL_NLINE", 176 "CC_RECEIVE_DATA_UPDT_HEADER", 177 "CC_RECEIVE_DATA_UPDT_NLINE", 178 "CC_RECEIVE_DATA_UPDT_DATA", 176 179 }; 177 180 … … 250 253 m_debug_start_cycle( debug_start_cycle ), 251 254 m_debug_ok( debug_ok ), 255 m_dcache_paddr_ext_reset(0), 256 m_icache_paddr_ext_reset(0), 252 257 253 258 r_mmu_ptpr("r_mmu_ptpr"), … … 284 289 r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"), 285 290 291 r_icache_cleanup_victim_req("r_icache_cleanup_victim_req"), 292 r_icache_cleanup_victim_nline("r_icache_cleanup_victim_nline"), 293 286 294 r_icache_cc_send_req("r_icache_cc_send_req"), 287 295 r_icache_cc_send_type("r_icache_cc_send_type"), … … 289 297 r_icache_cc_send_way("r_icache_cc_send_way"), 290 298 r_icache_cc_send_updt_tab_idx("r_icache_cc_send_updt_tab_idx"), 291 292 r_icache_cleanup_victim_req("r_icache_cleanup_victim_req"),293 r_icache_cleanup_victim_nline("r_icache_cleanup_victim_nline"),294 299 295 300 r_dcache_fsm("r_dcache_fsm"), … … 354 359 r_dcache_xtn_req("r_dcache_xtn_req"), 355 360 r_dcache_xtn_opcode("r_dcache_xtn_opcode"), 356 361 357 362 r_dcache_cleanup_victim_req("r_dcache_cleanup_victim_req"), 358 363 r_dcache_cleanup_victim_nline("r_dcache_cleanup_victim_nline"), 359 364 360 365 r_dcache_cc_send_req("r_dcache_cc_send_req"), 361 366 r_dcache_cc_send_type("r_dcache_cc_send_type"), … … 487 492 { 488 493 // b0 : write buffer trace 489 // b1 : write buffer verbose494 // b1 : dump processor registers 490 495 // b2 : dcache trace 491 496 // b3 : icache trace 492 497 // b4 : dtlb trace 493 498 // b5 : itlb trace 499 494 500 std::cout << std::dec << "PROC " << name() << std::endl; 495 501 … … 508 514 << " | " << cc_send_fsm_state_str[r_cc_send_fsm.read()] 509 515 << " | MMU = " << r_mmu_mode.read(); 516 510 517 if (r_dcache_updt_req.read() ) std::cout << " | P1_UPDT"; 511 518 if (r_dcache_wbuf_req.read() ) std::cout << " | P1_WBUF"; … … 514 521 if(mode & 0x01) 515 522 { 523 if ( r_icache_miss_req.read() ) std::cout << " IMISS_REQ" << std::endl; 524 if ( r_icache_unc_req.read() ) std::cout << " IUNC_REQ" << std::endl; 525 if ( r_dcache_vci_miss_req.read() ) std::cout << " DMISS_REQ" << std::endl; 526 if ( r_dcache_vci_unc_req.read() ) std::cout << " DUNC_REQ" << std::endl; 527 516 528 r_wbuf.printTrace((mode>>1)&1); 529 } 530 if(mode & 0x02) 531 { 532 r_iss.dump(); 517 533 } 518 534 if(mode & 0x04) … … 772 788 773 789 // reset data physical address extension 774 r_dcache_paddr_ext = 0; 790 r_dcache_paddr_ext = m_dcache_paddr_ext_reset; 791 792 // reset inst physical address extension 793 r_icache_paddr_ext = m_icache_paddr_ext_reset; 775 794 776 795 // reset dcache directory extension … … 800 819 // No request from ICACHE_FSM to CC_SEND FSM 801 820 r_icache_cc_send_req = false; 821 r_icache_cleanup_victim_req = false; 802 822 803 823 r_icache_clack_req = false; … … 879 899 m_cpt_data_write_back = 0; 880 900 m_cpt_data_cleanup = 0; 881 m_cpt_cleanup_data_not_dirty = 0; 901 m_cpt_cleanup_data_not_dirty = 0; 882 902 m_cpt_ins_miss = 0; 883 903 m_cpt_unc_read = 0; … … 1111 1131 1112 1132 // XTN requests sent by DCACHE FSM 1113 // These request are not executed in this IDLE state , because1114 // they require access to icache or itlb, that are already accessed1133 // These request are not executed in this IDLE state (except XTN_INST_PADDR_EXT), 1134 // because they require access to icache or itlb, that are already accessed 1115 1135 if ( r_dcache_xtn_req.read() ) 1116 1136 { … … 1134 1154 else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV) 1135 1155 { 1136 1156 if (sizeof(paddr_t) <= 32) 1137 1157 { 1138 1139 1140 1158 assert(r_mmu_word_hi.read() == 0 && 1159 "illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr"); 1160 r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read(); 1141 1161 } 1142 1162 else 1143 1163 { 1144 r_icache_vci_paddr = (uint64_t)r_mmu_word_hi.read() << 32 | 1145 (paddr_t)r_mmu_word_lo.read(); 1146 } 1147 r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA; 1164 r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 | 1165 (paddr_t)r_mmu_word_lo.read(); 1166 } 1167 r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA; 1168 } 1169 else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_INST_PADDR_EXT) 1170 { 1171 r_icache_paddr_ext = r_dcache_save_wdata.read(); 1172 r_dcache_xtn_req = false; 1148 1173 } 1149 1174 else … … 1185 1210 &paddr, 1186 1211 &tlb_flags, 1187 &tlb_nline, // unused 1188 &tlb_way, // unused 1189 &tlb_set ); // unused 1190 } 1191 // Not yet supported 1192 //else if (vci_param::N > 32) 1193 //{ 1194 // paddr = paddr | ((paddr_t) r_icache_paddr_ext.read() << 32); 1195 //} 1196 1212 &tlb_nline, // unused 1213 &tlb_way, // unused 1214 &tlb_set ); // unused 1215 } 1216 else if (vci_param::N > 32) 1217 { 1218 paddr = paddr | ((paddr_t) r_icache_paddr_ext.read() << 32); 1219 } 1197 1220 1198 1221 // systematic icache access (if activated) … … 1271 1294 if ( cacheable ) 1272 1295 { 1296 1273 1297 if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss 1274 1298 { … … 1304 1328 if ( m_debug_activated ) 1305 1329 std::cout << " <PROC " << name() << " ICACHE_IDLE> READ HIT in icache" 1306 << " : PADDR = " << std::hex << paddr << std::endl; 1330 << " : PADDR = " << std::hex << paddr 1331 << " / INST = " << cache_inst << std::dec << std::endl; 1307 1332 #endif 1308 1333 } … … 1607 1632 break; 1608 1633 } 1634 1609 1635 1610 1636 bool found; … … 1755 1781 std::cout << " <PROC " << name() 1756 1782 << " ICACHE_MISS_DATA_UPDT> Write one word:" 1757 << " WDATA = " << r_vci_rsp_fifo_icache.read()1783 << " WDATA = " << std::hex << r_vci_rsp_fifo_icache.read() 1758 1784 << " WAY = " << r_icache_miss_way.read() 1759 1785 << " SET = " << r_icache_miss_set.read() … … 1782 1808 if ( m_ireq.valid ) m_cost_ins_miss_frz++; 1783 1809 1810 // send cleanup victim request 1784 1811 if ( r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read() ) 1785 1812 { … … 2315 2342 // we take into account the paddr extension 2316 2343 if (vci_param::N > 32) 2317 paddr = paddr | (( uint64_t)(r_dcache_paddr_ext.read()) << 32);2344 paddr = paddr | ((paddr_t)(r_dcache_paddr_ext.read()) << 32); 2318 2345 } 2319 2346 } // end physical address computation … … 2322 2349 if ( r_mmu_mode.read() & DATA_CACHE_MASK) 2323 2350 { 2351 2324 2352 if ( m_dreq.valid and r_dcache_updt_req.read() ) // read DIR and write DATA 2325 2353 { … … 2541 2569 case iss_t::XTN_DATA_PADDR_EXT: 2542 2570 m_drsp.rdata = r_dcache_paddr_ext.read(); 2571 m_drsp.valid = true; 2572 m_drsp.error = false; 2573 break; 2574 2575 case iss_t::XTN_INST_PADDR_EXT: 2576 m_drsp.rdata = r_icache_paddr_ext.read(); 2543 2577 m_drsp.valid = true; 2544 2578 m_drsp.error = false; … … 2620 2654 else 2621 2655 { 2622 r_dcache_save_paddr = ( uint64_t)r_mmu_word_hi.read() << 32 |2656 r_dcache_save_paddr = (paddr_t)r_mmu_word_hi.read() << 32 | 2623 2657 (paddr_t)r_mmu_word_lo.read(); 2624 2658 } … … 2671 2705 m_drsp.valid = true; 2672 2706 r_dcache_fsm = DCACHE_IDLE; 2707 break; 2708 2709 case iss_t::XTN_INST_PADDR_EXT: // no cache or tlb access 2710 r_dcache_xtn_req = true; 2711 r_dcache_fsm = DCACHE_XTN_IC_PADDR_EXT; 2673 2712 break; 2674 2713 … … 2822 2861 std::cout << " <PROC " << name() << " DCACHE_IDLE>" 2823 2862 << " READ HIT in dcache" 2824 << " / PADDR = " << std::hex << paddr << std::endl; 2863 << " : PADDR = " << std::hex << paddr 2864 << " / DATA = " << std::hex << cache_rdata << std::dec << std::endl; 2825 2865 #endif 2826 2866 } … … 3483 3523 r_cas_local_set = set; 3484 3524 r_cas_local_word = word; 3485 3525 3486 3526 #if DEBUG_DCACHE 3487 3527 if ( m_debug_activated ) … … 3878 3918 } 3879 3919 //////////////////////// 3880 case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM 3881 case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken 3882 case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache 3883 case DCACHE_XTN_IT_INVAL: // can generate an itlb miss, 3884 // and because it can exist a simultaneous ITLB miss 3920 case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM 3921 case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken 3922 case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache 3923 case DCACHE_XTN_IC_PADDR_EXT: // can generate an itlb miss, 3924 case DCACHE_XTN_IT_INVAL: // and because it can exist a simultaneous ITLB miss 3925 3885 3926 { 3886 3927 // coherence clack request (from DSPIN CLACK) … … 4111 4152 { 4112 4153 paddr = (paddr_t)r_dcache_save_wdata.read(); 4154 if (vci_param::N > 32) 4155 paddr = paddr | ((paddr_t)(r_dcache_paddr_ext.read()) << 32); 4113 4156 hit = true; 4114 4157 } … … 4284 4327 } 4285 4328 4286 /* ODCCP*/4329 /*RWT*/ 4287 4330 ////////////////////////////// 4288 4331 case DCACHE_XTN_DC_INVAL_DATA: … … 6041 6084 if (p_vci.rspval.read()) 6042 6085 { 6043 /**/6044 if( p_vci.reop.read() ==0)6045 {6046 std::cout << "PROC " << m_srcid6047 << "/ CYCLE " << m_cpt_total_cycles6048 <<std::endl;6049 }6050 6086 assert( p_vci.reop.read() and 6051 6087 "a VCI response packet must contain one flit for a write transaction");
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