Index: branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
===================================================================
--- branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 771)
+++ branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 805)
@@ -114,4 +114,5 @@
         DCACHE_XTN_IC_FLUSH,
         DCACHE_XTN_IC_INVAL_PA,
+        DCACHE_XTN_IC_PADDR_EXT,
         DCACHE_XTN_IT_INVAL,
         DCACHE_XTN_DC_FLUSH,
@@ -329,4 +330,7 @@
     bool                                m_debug_ok;
 
+    uint32_t                            m_dcache_paddr_ext_reset;
+    uint32_t                            m_icache_paddr_ext_reset;
+
     ////////////////////////////////////////
     // Communication with processor ISS
@@ -396,4 +400,7 @@
     sc_signal<bool>         r_icache_tlb_rsp_error;      // tlb miss response error
 
+    // Flip-Flop in ICACHE FSM for saving the cleanup victim request
+    sc_signal<bool>         r_icache_cleanup_victim_req; 
+    sc_signal<paddr_t>      r_icache_cleanup_victim_nline;
 
     // communication between ICACHE FSM and CC_SEND FSM
@@ -403,8 +410,7 @@
     sc_signal<size_t>       r_icache_cc_send_way;           // ICACHE cc_send way
     sc_signal<size_t>       r_icache_cc_send_updt_tab_idx;  // ICACHE cc_send update table index
-    
-    // Filp-Flop in ICACHE FSM for saving the cleanup victim request
-    sc_signal<bool>         r_icache_cleanup_victim_req; 
-    sc_signal<paddr_t>      r_icache_cleanup_victim_nline;
+
+    // Physical address extension for data access
+    sc_signal<uint32_t>     r_icache_paddr_ext;             // CP2 register (if vci_address > 32)
 
     ///////////////////////////////
@@ -468,5 +474,5 @@
     sc_signal<bool>         r_dcache_cc_need_write;     // activate the cache for writing
     sc_signal<paddr_t>      r_dcache_cc_inval_addr;     // address for a cleanup transaction
-    sc_signal<uint32_t>     r_dcache_cc_inval_data_cpt;  
+    sc_signal<uint32_t>     r_dcache_cc_inval_data_cpt;
 
     // coherence clack handling
@@ -503,6 +509,6 @@
     // Filp-Flop in DCACHE FSM for saving the cleanup victim request
     sc_signal<bool>         r_dcache_cleanup_victim_req; 
-    sc_signal<bool>         r_dcache_cleanup_victim_line_ncc; 
-    sc_signal<bool>         r_dcache_cleanup_victim_updt_data; 
+    sc_signal<bool>         r_dcache_cleanup_victim_line_ncc;
+    sc_signal<bool>         r_dcache_cleanup_victim_updt_data;
     sc_signal<paddr_t>      r_dcache_cleanup_victim_nline;
 
@@ -513,5 +519,5 @@
     sc_signal<size_t>       r_dcache_cc_send_way;           // DCACHE cc_send way
     sc_signal<size_t>       r_dcache_cc_send_updt_tab_idx;  // DCACHE cc_send update table index
-    
+
     // special registers for RWT
     sc_signal<bool>         r_dcache_cc_cleanup_updt_data;     // Register for cleanup with data (wb updt)
@@ -519,5 +525,5 @@
     sc_signal<bool>         r_dcache_miss_victim_no_coherence; // Register for victim in no coherence mode
     sc_signal<bool>         r_dcache_line_no_coherence;        // Register for line current in no coherence mode
-    sc_signal<bool>         r_dcache_dirty_save;             
+    sc_signal<bool>         r_dcache_dirty_save;
     sc_signal<uint32_t>     r_cc_send_cpt_word;
     sc_signal<uint32_t>     r_dcache_miss_data_cpt;
@@ -559,9 +565,9 @@
     GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;	        // response FIFO to ICACHE FSM
     GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;	        // response FIFO to DCACHE FSM
-    
+
 
     //RWT
     GenericFifo<bool>       r_vci_rsp_fifo_rpktid;
-    GenericFifo<uint32_t>   r_cc_send_data_fifo;   
+    GenericFifo<uint32_t>   r_cc_send_data_fifo;
 
     ///////////////////////////////////
@@ -626,5 +632,5 @@
     sc_signal<bool>                        r_dcache_llsc_valid;
 
-    
+
     sc_signal<bool>                        r_cache_frozen;
 
@@ -806,4 +812,26 @@
     }
 
+    /////////////////////////////////////////////////////////////
+    // Set the m_dcache_paddr_ext_reset attribute
+    //
+    // The r_dcache_paddr_ext register will be initialized after
+    // reset with the m_dcache_paddr_ext_reset value
+    /////////////////////////////////////////////////////////////
+    inline void set_dcache_paddr_ext_reset(uint32_t v)
+    {
+        m_dcache_paddr_ext_reset = v;
+    }
+
+    /////////////////////////////////////////////////////////////
+    // Set the m_icache_paddr_ext_reset attribute
+    //
+    // The r_icache_paddr_ext register will be initialized after
+    // reset with the m_icache_paddr_ext_reset value
+    /////////////////////////////////////////////////////////////
+    inline void set_icache_paddr_ext_reset(uint32_t v)
+    {
+        m_icache_paddr_ext_reset = v;
+    }
+
 private:
     void transition();
