Index: /branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h =================================================================== --- /branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (revision 804) +++ /branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (revision 805) @@ -114,4 +114,5 @@ DCACHE_XTN_IC_FLUSH, DCACHE_XTN_IC_INVAL_PA, + DCACHE_XTN_IC_PADDR_EXT, DCACHE_XTN_IT_INVAL, DCACHE_XTN_DC_FLUSH, @@ -329,4 +330,7 @@ bool m_debug_ok; + uint32_t m_dcache_paddr_ext_reset; + uint32_t m_icache_paddr_ext_reset; + //////////////////////////////////////// // Communication with processor ISS @@ -396,4 +400,7 @@ sc_signal r_icache_tlb_rsp_error; // tlb miss response error + // Flip-Flop in ICACHE FSM for saving the cleanup victim request + sc_signal r_icache_cleanup_victim_req; + sc_signal r_icache_cleanup_victim_nline; // communication between ICACHE FSM and CC_SEND FSM @@ -403,8 +410,7 @@ sc_signal r_icache_cc_send_way; // ICACHE cc_send way sc_signal r_icache_cc_send_updt_tab_idx; // ICACHE cc_send update table index - - // Filp-Flop in ICACHE FSM for saving the cleanup victim request - sc_signal r_icache_cleanup_victim_req; - sc_signal r_icache_cleanup_victim_nline; + + // Physical address extension for data access + sc_signal r_icache_paddr_ext; // CP2 register (if vci_address > 32) /////////////////////////////// @@ -468,5 +474,5 @@ sc_signal r_dcache_cc_need_write; // activate the cache for writing sc_signal r_dcache_cc_inval_addr; // address for a cleanup transaction - sc_signal r_dcache_cc_inval_data_cpt; + sc_signal r_dcache_cc_inval_data_cpt; // coherence clack handling @@ -503,6 +509,6 @@ // Filp-Flop in DCACHE FSM for saving the cleanup victim request sc_signal r_dcache_cleanup_victim_req; - sc_signal r_dcache_cleanup_victim_line_ncc; - sc_signal r_dcache_cleanup_victim_updt_data; + sc_signal r_dcache_cleanup_victim_line_ncc; + sc_signal r_dcache_cleanup_victim_updt_data; sc_signal r_dcache_cleanup_victim_nline; @@ -513,5 +519,5 @@ sc_signal r_dcache_cc_send_way; // DCACHE cc_send way sc_signal r_dcache_cc_send_updt_tab_idx; // DCACHE cc_send update table index - + // special registers for RWT sc_signal r_dcache_cc_cleanup_updt_data; // Register for cleanup with data (wb updt) @@ -519,5 +525,5 @@ sc_signal r_dcache_miss_victim_no_coherence; // Register for victim in no coherence mode sc_signal r_dcache_line_no_coherence; // Register for line current in no coherence mode - sc_signal r_dcache_dirty_save; + sc_signal r_dcache_dirty_save; sc_signal r_cc_send_cpt_word; sc_signal r_dcache_miss_data_cpt; @@ -559,9 +565,9 @@ GenericFifo r_vci_rsp_fifo_icache; // response FIFO to ICACHE FSM GenericFifo r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM - + //RWT GenericFifo r_vci_rsp_fifo_rpktid; - GenericFifo r_cc_send_data_fifo; + GenericFifo r_cc_send_data_fifo; /////////////////////////////////// @@ -626,5 +632,5 @@ sc_signal r_dcache_llsc_valid; - + sc_signal r_cache_frozen; @@ -806,4 +812,26 @@ } + ///////////////////////////////////////////////////////////// + // Set the m_dcache_paddr_ext_reset attribute + // + // The r_dcache_paddr_ext register will be initialized after + // reset with the m_dcache_paddr_ext_reset value + ///////////////////////////////////////////////////////////// + inline void set_dcache_paddr_ext_reset(uint32_t v) + { + m_dcache_paddr_ext_reset = v; + } + + ///////////////////////////////////////////////////////////// + // Set the m_icache_paddr_ext_reset attribute + // + // The r_icache_paddr_ext register will be initialized after + // reset with the m_icache_paddr_ext_reset value + ///////////////////////////////////////////////////////////// + inline void set_icache_paddr_ext_reset(uint32_t v) + { + m_icache_paddr_ext_reset = v; + } + private: void transition(); Index: /branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp =================================================================== --- /branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 804) +++ /branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 805) @@ -29,4 +29,6 @@ #include +#include + #include "arithmetics.h" #include "../include/vci_cc_vcache_wrapper.h" @@ -86,4 +88,5 @@ "DCACHE_XTN_IC_FLUSH", "DCACHE_XTN_IC_INVAL_PA", + "DCACHE_XTN_IC_PADDR_EXT", "DCACHE_XTN_IT_INVAL", "DCACHE_XTN_DC_FLUSH", @@ -161,17 +164,17 @@ const char *cc_receive_fsm_state_str[] = { - "CC_RECEIVE_IDLE", - "CC_RECEIVE_BRDCAST_HEADER", - "CC_RECEIVE_BRDCAST_NLINE", - "CC_RECEIVE_INS_INVAL_HEADER", - "CC_RECEIVE_INS_INVAL_NLINE", - "CC_RECEIVE_INS_UPDT_HEADER", - "CC_RECEIVE_INS_UPDT_NLINE", - "CC_RECEIVE_INS_UPDT_DATA", - "CC_RECEIVE_DATA_INVAL_HEADER", - "CC_RECEIVE_DATA_INVAL_NLINE", - "CC_RECEIVE_DATA_UPDT_HEADER", - "CC_RECEIVE_DATA_UPDT_NLINE", - "CC_RECEIVE_DATA_UPDT_DATA", + "CC_RECEIVE_IDLE", + "CC_RECEIVE_BRDCAST_HEADER", + "CC_RECEIVE_BRDCAST_NLINE", + "CC_RECEIVE_INS_INVAL_HEADER", + "CC_RECEIVE_INS_INVAL_NLINE", + "CC_RECEIVE_INS_UPDT_HEADER", + "CC_RECEIVE_INS_UPDT_NLINE", + "CC_RECEIVE_INS_UPDT_DATA", + "CC_RECEIVE_DATA_INVAL_HEADER", + "CC_RECEIVE_DATA_INVAL_NLINE", + "CC_RECEIVE_DATA_UPDT_HEADER", + "CC_RECEIVE_DATA_UPDT_NLINE", + "CC_RECEIVE_DATA_UPDT_DATA", }; @@ -250,4 +253,6 @@ m_debug_start_cycle( debug_start_cycle ), m_debug_ok( debug_ok ), + m_dcache_paddr_ext_reset(0), + m_icache_paddr_ext_reset(0), r_mmu_ptpr("r_mmu_ptpr"), @@ -284,4 +289,7 @@ r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"), + r_icache_cleanup_victim_req("r_icache_cleanup_victim_req"), + r_icache_cleanup_victim_nline("r_icache_cleanup_victim_nline"), + r_icache_cc_send_req("r_icache_cc_send_req"), r_icache_cc_send_type("r_icache_cc_send_type"), @@ -289,7 +297,4 @@ r_icache_cc_send_way("r_icache_cc_send_way"), r_icache_cc_send_updt_tab_idx("r_icache_cc_send_updt_tab_idx"), - - r_icache_cleanup_victim_req("r_icache_cleanup_victim_req"), - r_icache_cleanup_victim_nline("r_icache_cleanup_victim_nline"), r_dcache_fsm("r_dcache_fsm"), @@ -354,8 +359,8 @@ r_dcache_xtn_req("r_dcache_xtn_req"), r_dcache_xtn_opcode("r_dcache_xtn_opcode"), - + r_dcache_cleanup_victim_req("r_dcache_cleanup_victim_req"), r_dcache_cleanup_victim_nline("r_dcache_cleanup_victim_nline"), - + r_dcache_cc_send_req("r_dcache_cc_send_req"), r_dcache_cc_send_type("r_dcache_cc_send_type"), @@ -487,9 +492,10 @@ { // b0 : write buffer trace - // b1 : write buffer verbose + // b1 : dump processor registers // b2 : dcache trace // b3 : icache trace // b4 : dtlb trace // b5 : itlb trace + std::cout << std::dec << "PROC " << name() << std::endl; @@ -508,4 +514,5 @@ << " | " << cc_send_fsm_state_str[r_cc_send_fsm.read()] << " | MMU = " << r_mmu_mode.read(); + if (r_dcache_updt_req.read() ) std::cout << " | P1_UPDT"; if (r_dcache_wbuf_req.read() ) std::cout << " | P1_WBUF"; @@ -514,5 +521,14 @@ if(mode & 0x01) { + if ( r_icache_miss_req.read() ) std::cout << " IMISS_REQ" << std::endl; + if ( r_icache_unc_req.read() ) std::cout << " IUNC_REQ" << std::endl; + if ( r_dcache_vci_miss_req.read() ) std::cout << " DMISS_REQ" << std::endl; + if ( r_dcache_vci_unc_req.read() ) std::cout << " DUNC_REQ" << std::endl; + r_wbuf.printTrace((mode>>1)&1); + } + if(mode & 0x02) + { + r_iss.dump(); } if(mode & 0x04) @@ -772,5 +788,8 @@ // reset data physical address extension - r_dcache_paddr_ext = 0; + r_dcache_paddr_ext = m_dcache_paddr_ext_reset; + + // reset inst physical address extension + r_icache_paddr_ext = m_icache_paddr_ext_reset; // reset dcache directory extension @@ -800,4 +819,5 @@ // No request from ICACHE_FSM to CC_SEND FSM r_icache_cc_send_req = false; + r_icache_cleanup_victim_req = false; r_icache_clack_req = false; @@ -879,5 +899,5 @@ m_cpt_data_write_back = 0; m_cpt_data_cleanup = 0; - m_cpt_cleanup_data_not_dirty = 0; + m_cpt_cleanup_data_not_dirty = 0; m_cpt_ins_miss = 0; m_cpt_unc_read = 0; @@ -1111,6 +1131,6 @@ // XTN requests sent by DCACHE FSM - // These request are not executed in this IDLE state, because - // they require access to icache or itlb, that are already accessed + // These request are not executed in this IDLE state (except XTN_INST_PADDR_EXT), + // because they require access to icache or itlb, that are already accessed if ( r_dcache_xtn_req.read() ) { @@ -1134,16 +1154,21 @@ else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV) { - if (sizeof(paddr_t) <= 32) + if (sizeof(paddr_t) <= 32) { - assert(r_mmu_word_hi.read() == 0 && - "illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr"); - r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read(); + assert(r_mmu_word_hi.read() == 0 && + "illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr"); + r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read(); } else { - r_icache_vci_paddr = (uint64_t)r_mmu_word_hi.read() << 32 | - (paddr_t)r_mmu_word_lo.read(); - } - r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA; + r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 | + (paddr_t)r_mmu_word_lo.read(); + } + r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA; + } + else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_INST_PADDR_EXT) + { + r_icache_paddr_ext = r_dcache_save_wdata.read(); + r_dcache_xtn_req = false; } else @@ -1185,14 +1210,12 @@ &paddr, &tlb_flags, - &tlb_nline, // unused - &tlb_way, // unused - &tlb_set ); // unused - } - // Not yet supported - //else if (vci_param::N > 32) - //{ - // paddr = paddr | ((paddr_t) r_icache_paddr_ext.read() << 32); - //} - + &tlb_nline, // unused + &tlb_way, // unused + &tlb_set ); // unused + } + else if (vci_param::N > 32) + { + paddr = paddr | ((paddr_t) r_icache_paddr_ext.read() << 32); + } // systematic icache access (if activated) @@ -1271,4 +1294,5 @@ if ( cacheable ) { + if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss { @@ -1304,5 +1328,6 @@ if ( m_debug_activated ) std::cout << " READ HIT in icache" - << " : PADDR = " << std::hex << paddr << std::endl; + << " : PADDR = " << std::hex << paddr + << " / INST = " << cache_inst << std::dec << std::endl; #endif } @@ -1607,4 +1632,5 @@ break; } + bool found; @@ -1755,5 +1781,5 @@ std::cout << " Write one word:" - << " WDATA = " << r_vci_rsp_fifo_icache.read() + << " WDATA = " << std::hex << r_vci_rsp_fifo_icache.read() << " WAY = " << r_icache_miss_way.read() << " SET = " << r_icache_miss_set.read() @@ -1782,4 +1808,5 @@ if ( m_ireq.valid ) m_cost_ins_miss_frz++; + // send cleanup victim request if ( r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read() ) { @@ -2315,5 +2342,5 @@ // we take into account the paddr extension if (vci_param::N > 32) - paddr = paddr | ((uint64_t)(r_dcache_paddr_ext.read()) << 32); + paddr = paddr | ((paddr_t)(r_dcache_paddr_ext.read()) << 32); } } // end physical address computation @@ -2322,4 +2349,5 @@ if ( r_mmu_mode.read() & DATA_CACHE_MASK) { + if ( m_dreq.valid and r_dcache_updt_req.read() ) // read DIR and write DATA { @@ -2541,4 +2569,10 @@ case iss_t::XTN_DATA_PADDR_EXT: m_drsp.rdata = r_dcache_paddr_ext.read(); + m_drsp.valid = true; + m_drsp.error = false; + break; + + case iss_t::XTN_INST_PADDR_EXT: + m_drsp.rdata = r_icache_paddr_ext.read(); m_drsp.valid = true; m_drsp.error = false; @@ -2620,5 +2654,5 @@ else { - r_dcache_save_paddr = (uint64_t)r_mmu_word_hi.read() << 32 | + r_dcache_save_paddr = (paddr_t)r_mmu_word_hi.read() << 32 | (paddr_t)r_mmu_word_lo.read(); } @@ -2671,4 +2705,9 @@ m_drsp.valid = true; r_dcache_fsm = DCACHE_IDLE; + break; + + case iss_t::XTN_INST_PADDR_EXT: // no cache or tlb access + r_dcache_xtn_req = true; + r_dcache_fsm = DCACHE_XTN_IC_PADDR_EXT; break; @@ -2822,5 +2861,6 @@ std::cout << " " << " READ HIT in dcache" - << " / PADDR = " << std::hex << paddr << std::endl; + << " : PADDR = " << std::hex << paddr + << " / DATA = " << std::hex << cache_rdata << std::dec << std::endl; #endif } @@ -3483,5 +3523,5 @@ r_cas_local_set = set; r_cas_local_word = word; - + #if DEBUG_DCACHE if ( m_debug_activated ) @@ -3878,9 +3918,10 @@ } //////////////////////// - case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM - case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken - case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache - case DCACHE_XTN_IT_INVAL: // can generate an itlb miss, - // and because it can exist a simultaneous ITLB miss + case DCACHE_XTN_IC_FLUSH: // Waiting completion of an XTN request to the ICACHE FSM + case DCACHE_XTN_IC_INVAL_VA: // Caution : the itlb miss requests must be taken + case DCACHE_XTN_IC_INVAL_PA: // because the XTN_ICACHE_INVAL request to icache + case DCACHE_XTN_IC_PADDR_EXT: // can generate an itlb miss, + case DCACHE_XTN_IT_INVAL: // and because it can exist a simultaneous ITLB miss + { // coherence clack request (from DSPIN CLACK) @@ -4111,4 +4152,6 @@ { paddr = (paddr_t)r_dcache_save_wdata.read(); + if (vci_param::N > 32) + paddr = paddr | ((paddr_t)(r_dcache_paddr_ext.read()) << 32); hit = true; } @@ -4284,5 +4327,5 @@ } - /*ODCCP*/ + /*RWT*/ ////////////////////////////// case DCACHE_XTN_DC_INVAL_DATA: @@ -6041,11 +6084,4 @@ if (p_vci.rspval.read()) { - /**/ - if( p_vci.reop.read() ==0) - { - std::cout << "PROC " << m_srcid - << "/ CYCLE " << m_cpt_total_cycles - <