Index: branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h
===================================================================
--- branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h	(revision 748)
+++ branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h	(revision 806)
@@ -1,5 +1,5 @@
 //////////////////////////////////////////////////////////////////////////////
 // File: tsar_iob_cluster.h
-// Author: Alain Greiner 
+// Author: Alain Greiner
 // Copyright: UPMC/LIP6
 // Date : april 2013
@@ -37,11 +37,11 @@
 
 ///////////////////////////////////////////////////////////////////////////
-template<typename vci_param_int, 
+template<typename vci_param_int,
          typename vci_param_ext,
-         size_t   dspin_int_cmd_width, 
+         size_t   dspin_int_cmd_width,
          size_t   dspin_int_rsp_width,
          size_t   dspin_ram_cmd_width,
          size_t   dspin_ram_rsp_width>
-class TsarIobCluster 
+class TsarIobCluster
 ///////////////////////////////////////////////////////////////////////////
     : public soclib::caba::BaseModule
@@ -56,5 +56,5 @@
     // Thes two ports are used to connect IOB to IOX nework in top cell
     soclib::caba::VciInitiator<vci_param_ext>*         p_vci_iob_iox_ini;
-    soclib::caba::VciTarget<vci_param_ext>*            p_vci_iob_iox_tgt; 
+    soclib::caba::VciTarget<vci_param_ext>*            p_vci_iob_iox_tgt;
 
     // These arrays of ports are used to connect the INT & RAM networks in top cell
@@ -74,21 +74,21 @@
     sc_signal<bool>                       signal_irq_mdma[8];
     sc_signal<bool>                       signal_irq_memc;
-    
+
     // INT network DSPIN signals between DSPIN routers and DSPIN local_crossbars
-    DspinSignals<dspin_int_cmd_width>     signal_int_dspin_cmd_l2g_d; 
-    DspinSignals<dspin_int_cmd_width>     signal_int_dspin_cmd_g2l_d; 
+    DspinSignals<dspin_int_cmd_width>     signal_int_dspin_cmd_l2g_d;
+    DspinSignals<dspin_int_cmd_width>     signal_int_dspin_cmd_g2l_d;
     DspinSignals<dspin_int_cmd_width>     signal_int_dspin_m2p_l2g_c;
-    DspinSignals<dspin_int_cmd_width>     signal_int_dspin_m2p_g2l_c; 
+    DspinSignals<dspin_int_cmd_width>     signal_int_dspin_m2p_g2l_c;
     DspinSignals<dspin_int_cmd_width>     signal_int_dspin_clack_l2g_c;
     DspinSignals<dspin_int_cmd_width>     signal_int_dspin_clack_g2l_c;
-    DspinSignals<dspin_int_rsp_width>     signal_int_dspin_rsp_l2g_d; 
-    DspinSignals<dspin_int_rsp_width>     signal_int_dspin_rsp_g2l_d; 
+    DspinSignals<dspin_int_rsp_width>     signal_int_dspin_rsp_l2g_d;
+    DspinSignals<dspin_int_rsp_width>     signal_int_dspin_rsp_g2l_d;
     DspinSignals<dspin_int_rsp_width>     signal_int_dspin_p2m_l2g_c;
     DspinSignals<dspin_int_rsp_width>     signal_int_dspin_p2m_g2l_c;
 
     // INT network VCI signals between VCI components and VCI local crossbar
-    VciSignals<vci_param_int>             signal_int_vci_ini_proc[8]; 
-    VciSignals<vci_param_int>             signal_int_vci_ini_mdma; 
-    VciSignals<vci_param_int>             signal_int_vci_ini_iobx; 
+    VciSignals<vci_param_int>             signal_int_vci_ini_proc[8];
+    VciSignals<vci_param_int>             signal_int_vci_ini_mdma;
+    VciSignals<vci_param_int>             signal_int_vci_ini_iobx;
 
     VciSignals<vci_param_int>             signal_int_vci_tgt_memc;
@@ -101,5 +101,5 @@
     VciSignals<vci_param_int>             signal_int_vci_g2l;
 
-    // Coherence DSPIN signals between DSPIN local crossbars and CC components 
+    // Coherence DSPIN signals between DSPIN local crossbars and CC components
     DspinSignals<dspin_int_cmd_width>     signal_int_dspin_m2p_memc;
     DspinSignals<dspin_int_cmd_width>     signal_int_dspin_clack_memc;
@@ -115,5 +115,5 @@
 
     // RAM network DSPIN signals between VCI/DSPIN wrappers, RAM dspin crossbar
-    // and routers 
+    // and routers
     DspinSignals<dspin_ram_cmd_width>     signal_ram_dspin_cmd_xram_t;
     DspinSignals<dspin_ram_rsp_width>     signal_ram_dspin_rsp_xram_t;
@@ -126,9 +126,9 @@
     DspinSignals<dspin_ram_cmd_width>     signal_ram_dspin_cmd_false;
     DspinSignals<dspin_ram_rsp_width>     signal_ram_dspin_rsp_false;
-  
+
     //////////////////////////////////////
     // Hardwate Components (pointers)
     //////////////////////////////////////
-    VciCcVCacheWrapper<vci_param_int, 
+    VciCcVCacheWrapper<vci_param_int,
                        dspin_int_cmd_width,
                        dspin_int_rsp_width,
@@ -136,6 +136,6 @@
 
     VciMemCache<vci_param_int,
-                vci_param_ext, 
-                dspin_int_rsp_width, 
+                vci_param_ext,
+                dspin_int_rsp_width,
                 dspin_int_cmd_width>*                 memc;
 
@@ -151,5 +151,5 @@
 
     VciLocalCrossbar<vci_param_int>*                  int_xbar_d;
-    
+
     VciDspinInitiatorWrapper<vci_param_int,
                              dspin_int_cmd_width,
@@ -172,5 +172,5 @@
                           dspin_ram_cmd_width,
                           dspin_ram_rsp_width>*       xram_ram_wt;
-    
+
     DspinRouter<dspin_ram_cmd_width>*                 ram_router_cmd;
     DspinRouter<dspin_ram_rsp_width>*                 ram_router_rsp;
@@ -178,5 +178,5 @@
     DspinLocalCrossbar<dspin_ram_cmd_width>*          ram_xbar_cmd;
     DspinLocalCrossbar<dspin_ram_rsp_width>*          ram_xbar_rsp;
-    
+
 
     // IO Network Components (not instanciated in all clusters)
@@ -191,10 +191,12 @@
     // cluster constructor
     TsarIobCluster( sc_module_name                     insname,
-                    size_t                             nb_procs,   
-                    size_t                             nb_dmas,  
+                    size_t                             nb_procs,
+                    size_t                             nb_dmas,
                     size_t                             x,             // x coordinate
                     size_t                             y,             // y coordinate
-                    size_t                             xmax,
-                    size_t                             ymax,
+                    size_t                             x_size,
+                    size_t                             y_size,
+
+                    size_t                             p_width,       // pid field bits
 
                     const soclib::common::MappingTable &mt_int,
@@ -226,8 +228,8 @@
                     size_t                             memc_sets,
                     size_t                             l1_i_ways,
-                    size_t                             l1_i_sets, 
+                    size_t                             l1_i_sets,
                     size_t                             l1_d_ways,
-                    size_t                             l1_d_sets,   
-                    size_t                             xram_latency, 
+                    size_t                             l1_d_sets,
+                    size_t                             xram_latency,
                     size_t                             xcu_nb_inputs,
 
@@ -236,9 +238,9 @@
                     const Loader                       &loader,       // loader for XRAM
 
-                    uint32_t                           frozen_cycles, 
+                    uint32_t                           frozen_cycles,
                     uint32_t                           start_debug_cycle,
-                    bool                               memc_debug_ok, 
-                    bool                               proc_debug_ok, 
-                    bool                               iob0_debug_ok ); 
+                    bool                               memc_debug_ok,
+                    bool                               proc_debug_ok,
+                    bool                               iob0_debug_ok );
 
   protected:
@@ -247,5 +249,5 @@
 
     void init();
- 
+
 
 };
