Index: branches/reconfiguration/platforms/tsar_generic_iob/scripts/arch.py =================================================================== --- branches/reconfiguration/platforms/tsar_generic_iob/scripts/arch.py (revision 805) +++ branches/reconfiguration/platforms/tsar_generic_iob/scripts/arch.py (revision 806) @@ -1,4 +1,4 @@ #!/usr/bin/env python -import sys +from math import log from mapping import * @@ -28,4 +28,5 @@ # - x_width : number of bits for x coordinate # - y_width : number of bits for y coordinate +# - p_width : number of bits for processor local id field # - paddr_width : number of bits for physical address # - irq_per_proc : number of input IRQs per processor @@ -48,4 +49,5 @@ x_width = 4 y_width = 4 + p_width = log(nb_procs, 2) paddr_width = 40 irq_per_proc = 4 @@ -355,5 +357,5 @@ ################################# platform test ####################################################### - +import sys if __name__ == '__main__': main( x_size = int(sys.argv[1]), Index: branches/reconfiguration/platforms/tsar_generic_iob/top.cpp =================================================================== --- branches/reconfiguration/platforms/tsar_generic_iob/top.cpp (revision 805) +++ branches/reconfiguration/platforms/tsar_generic_iob/top.cpp (revision 806) @@ -55,5 +55,5 @@ // - IRQ_IN[4] : DMA channel 3 // -// All clusters are identical, but cluster(0,0) and cluster(XMAX-1,YMAX-1) +// All clusters are identical, but cluster(0,0) and cluster(X_SIZE-1,Y_SIZE-1) // contain an extra IO bridge component. These IOB0 & IOB1 components are // connected to the three networks (INT, RAM, IOX). @@ -101,5 +101,5 @@ // All physical segments base addresses are multiple of 1 Mbytes // (=> the 24 LSB bits = 0, and the 16 MSB bits define the target) -// The (x_width + y_width) MSB bits (left aligned) define +// The (X_WIDTH + Y_WIDTH) MSB bits (left aligned) define // the cluster index, and the LADR bits define the local index: // |X_ID|Y_ID| LADR | OFFSET | @@ -191,7 +191,4 @@ //////////////////////i///////////////////////////////////// -#define XMAX X_SIZE -#define YMAX Y_SIZE - #define XRAM_LATENCY 0 @@ -237,5 +234,5 @@ // in the hard_config.h file. For replicated segments, the // base address is incremented by a cluster offset: -// offset = cluster(x,y) << (address_width-x_width-y_width); +// offset = cluster(x,y) << (address_width-X_WIDTH-Y_WIDTH); //////////////////////////////////////////////////////////////////////// @@ -336,7 +333,5 @@ uint32_t frozen_cycles = MAX_FROZEN_CYCLES; // monitoring frozen processor size_t cluster_iob0 = cluster(0,0); // cluster containing IOB0 - size_t cluster_iob1 = cluster(XMAX-1,YMAX-1); // cluster containing IOB1 - size_t x_width = 4; // at most 256 clusters - size_t y_width = 4; // at most 256 clusters + size_t cluster_iob1 = cluster(X_SIZE-1,Y_SIZE-1); // cluster containing IOB1 assert( (X_WIDTH == 4) and (Y_WIDTH == 4) and @@ -370,7 +365,7 @@ size_t x = debug_memc_id >> 4; size_t y = debug_memc_id & 0xF; - if( (x>=XMAX) || (y>=YMAX) ) + if( (x>=X_SIZE) || (y>=Y_SIZE) ) { - std::cout << "MEMCID parameter does'nt fit XMAX/YMAX" << std::endl; + std::cout << "MEMCID parameter does'nt fit X_SIZE/Y_SIZE" << std::endl; exit(0); } @@ -381,7 +376,7 @@ size_t x = debug_xram_id >> 4; size_t y = debug_xram_id & 0xF; - if( (x>=XMAX) || (y>=YMAX) ) + if( (x>=X_SIZE) || (y>=Y_SIZE) ) { - std::cout << "XRAMID parameter does'nt fit XMAX/YMAX" << std::endl; + std::cout << "XRAMID parameter does'nt fit X_SIZE/Y_SIZE" << std::endl; exit(0); } @@ -397,7 +392,7 @@ size_t x = cluster_xy >> 4; size_t y = cluster_xy & 0xF; - if( (x>=XMAX) || (y>=YMAX) ) + if( (x>=X_SIZE) || (y>=Y_SIZE) ) { - std::cout << "PROCID parameter does'nt fit XMAX/YMAX" << std::endl; + std::cout << "PROCID parameter does'nt fit X_SIZE/Y_SIZE" << std::endl; exit(0); } @@ -446,9 +441,9 @@ // checking hardware parameters - assert( (XMAX <= 16) and - "The XMAX parameter cannot be larger than 16" ); - - assert( (YMAX <= 16) and - "The YMAX parameter cannot be larger than 16" ); + assert( (X_SIZE <= (1 << X_WIDTH)) and + "The X_SIZE parameter cannot be larger than 16" ); + + assert( (Y_SIZE <= (1 << Y_WIDTH)) and + "The Y_SIZE parameter cannot be larger than 16" ); assert( (NB_PROCS_MAX <= 8) and @@ -465,6 +460,6 @@ std::cout << std::endl << std::dec - << " - XMAX = " << XMAX << std::endl - << " - YMAX = " << YMAX << std::endl + << " - X_SIZE = " << X_SIZE << std::endl + << " - Y_SIZE = " << Y_SIZE << std::endl << " - NB_PROCS_MAX = " << NB_PROCS_MAX << std::endl << " - NB_TTY_CHANNELS = " << NB_TTY_CHANNELS << std::endl @@ -519,14 +514,14 @@ ///////////////////////////////////////////////////////////////////// MappingTable maptab_int( vci_address_width, - IntTab(x_width + y_width, 16 - x_width - y_width), - IntTab(x_width + y_width, vci_srcid_width - x_width - y_width), + IntTab(X_WIDTH + Y_WIDTH, 16 - X_WIDTH - Y_WIDTH), + IntTab(X_WIDTH + Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH), 0x00FF000000); - for (size_t x = 0; x < XMAX; x++) + for (size_t x = 0; x < X_SIZE; x++) { - for (size_t y = 0; y < YMAX; y++) + for (size_t y = 0; y < Y_SIZE; y++) { uint64_t offset = ((uint64_t)cluster(x,y)) - << (vci_address_width-x_width-y_width); + << (vci_address_width-X_WIDTH-Y_WIDTH); bool config = true; bool cacheable = true; @@ -632,14 +627,14 @@ //////////////////////////////////////////////////////////////////////// MappingTable maptab_ram( vci_address_width, - IntTab(x_width+y_width, 0), - IntTab(x_width+y_width, vci_srcid_width - x_width - y_width), + IntTab(X_WIDTH+Y_WIDTH, 0), + IntTab(X_WIDTH+Y_WIDTH, vci_srcid_width - X_WIDTH - Y_WIDTH), 0x00FF000000); - for (size_t x = 0; x < XMAX; x++) + for (size_t x = 0; x < X_SIZE; x++) { - for (size_t y = 0; y < YMAX ; y++) + for (size_t y = 0; y < Y_SIZE ; y++) { uint64_t offset = ((uint64_t)cluster(x,y)) - << (vci_address_width-x_width-y_width); + << (vci_address_width-X_WIDTH-Y_WIDTH); std::ostringstream sxram; @@ -692,6 +687,6 @@ MappingTable maptab_iox( vci_address_width, - IntTab(x_width + y_width - 1, 16 - x_width - y_width + 1), - IntTab(x_width + y_width , vci_param_ext::S - x_width - y_width), + IntTab(X_WIDTH + Y_WIDTH - 1, 16 - X_WIDTH - Y_WIDTH + 1), + IntTab(X_WIDTH + Y_WIDTH , vci_param_ext::S - X_WIDTH - Y_WIDTH), 0x00FF000000); @@ -701,5 +696,5 @@ const uint64_t iob0_base = ((uint64_t)cluster_iob0) - << (vci_address_width - x_width - y_width); + << (vci_address_width - X_WIDTH - Y_WIDTH); maptab_iox.add(Segment("iox_seg_mtty_0", SEG_TTY_BASE + iob0_base, SEG_TTY_SIZE, @@ -721,5 +716,5 @@ { const uint64_t iob1_base = ((uint64_t)cluster_iob1) - << (vci_address_width - x_width - y_width); + << (vci_address_width - X_WIDTH - Y_WIDTH); maptab_iox.add(Segment("iox_seg_mtty_1", SEG_TTY_BASE + iob1_base, SEG_TTY_SIZE, @@ -743,7 +738,7 @@ // As IOMMU is not activated, addresses are 40 bits (physical addresses), // and the choice depends on address bit A[32]. - for (size_t x = 0; x < XMAX; x++) + for (size_t x = 0; x < X_SIZE; x++) { - for (size_t y = 0; y < YMAX ; y++) + for (size_t y = 0; y < Y_SIZE ; y++) { const bool wti = true; @@ -751,5 +746,5 @@ const uint64_t offset = ((uint64_t)cluster(x,y)) - << (vci_address_width-x_width-y_width); + << (vci_address_width-X_WIDTH-Y_WIDTH); const uint64_t xicu_base = SEG_XCU_BASE + offset; @@ -835,62 +830,62 @@ // Horizontal inter-clusters INT network DSPIN DspinSignals*** signal_dspin_int_cmd_h_inc = - alloc_elems >("signal_dspin_int_cmd_h_inc", XMAX-1, YMAX, 3); + alloc_elems >("signal_dspin_int_cmd_h_inc", X_SIZE-1, Y_SIZE, 3); DspinSignals*** signal_dspin_int_cmd_h_dec = - alloc_elems >("signal_dspin_int_cmd_h_dec", XMAX-1, YMAX, 3); + alloc_elems >("signal_dspin_int_cmd_h_dec", X_SIZE-1, Y_SIZE, 3); DspinSignals*** signal_dspin_int_rsp_h_inc = - alloc_elems >("signal_dspin_int_rsp_h_inc", XMAX-1, YMAX, 2); + alloc_elems >("signal_dspin_int_rsp_h_inc", X_SIZE-1, Y_SIZE, 2); DspinSignals*** signal_dspin_int_rsp_h_dec = - alloc_elems >("signal_dspin_int_rsp_h_dec", XMAX-1, YMAX, 2); + alloc_elems >("signal_dspin_int_rsp_h_dec", X_SIZE-1, Y_SIZE, 2); // Vertical inter-clusters INT network DSPIN DspinSignals*** signal_dspin_int_cmd_v_inc = - alloc_elems >("signal_dspin_int_cmd_v_inc", XMAX, YMAX-1, 3); + alloc_elems >("signal_dspin_int_cmd_v_inc", X_SIZE, Y_SIZE-1, 3); DspinSignals*** signal_dspin_int_cmd_v_dec = - alloc_elems >("signal_dspin_int_cmd_v_dec", XMAX, YMAX-1, 3); + alloc_elems >("signal_dspin_int_cmd_v_dec", X_SIZE, Y_SIZE-1, 3); DspinSignals*** signal_dspin_int_rsp_v_inc = - alloc_elems >("signal_dspin_int_rsp_v_inc", XMAX, YMAX-1, 2); + alloc_elems >("signal_dspin_int_rsp_v_inc", X_SIZE, Y_SIZE-1, 2); DspinSignals*** signal_dspin_int_rsp_v_dec = - alloc_elems >("signal_dspin_int_rsp_v_dec", XMAX, YMAX-1, 2); + alloc_elems >("signal_dspin_int_rsp_v_dec", X_SIZE, Y_SIZE-1, 2); // Mesh boundaries INT network DSPIN DspinSignals**** signal_dspin_false_int_cmd_in = - alloc_elems >("signal_dspin_false_int_cmd_in", XMAX, YMAX, 4, 3); + alloc_elems >("signal_dspin_false_int_cmd_in", X_SIZE, Y_SIZE, 4, 3); DspinSignals**** signal_dspin_false_int_cmd_out = - alloc_elems >("signal_dspin_false_int_cmd_out", XMAX, YMAX, 4, 3); + alloc_elems >("signal_dspin_false_int_cmd_out", X_SIZE, Y_SIZE, 4, 3); DspinSignals**** signal_dspin_false_int_rsp_in = - alloc_elems >("signal_dspin_false_int_rsp_in", XMAX, YMAX, 4, 2); + alloc_elems >("signal_dspin_false_int_rsp_in", X_SIZE, Y_SIZE, 4, 2); DspinSignals**** signal_dspin_false_int_rsp_out = - alloc_elems >("signal_dspin_false_int_rsp_out", XMAX, YMAX, 4, 2); + alloc_elems >("signal_dspin_false_int_rsp_out", X_SIZE, Y_SIZE, 4, 2); // Horizontal inter-clusters RAM network DSPIN DspinSignals** signal_dspin_ram_cmd_h_inc = - alloc_elems >("signal_dspin_ram_cmd_h_inc", XMAX-1, YMAX); + alloc_elems >("signal_dspin_ram_cmd_h_inc", X_SIZE-1, Y_SIZE); DspinSignals** signal_dspin_ram_cmd_h_dec = - alloc_elems >("signal_dspin_ram_cmd_h_dec", XMAX-1, YMAX); + alloc_elems >("signal_dspin_ram_cmd_h_dec", X_SIZE-1, Y_SIZE); DspinSignals** signal_dspin_ram_rsp_h_inc = - alloc_elems >("signal_dspin_ram_rsp_h_inc", XMAX-1, YMAX); + alloc_elems >("signal_dspin_ram_rsp_h_inc", X_SIZE-1, Y_SIZE); DspinSignals** signal_dspin_ram_rsp_h_dec = - alloc_elems >("signal_dspin_ram_rsp_h_dec", XMAX-1, YMAX); + alloc_elems >("signal_dspin_ram_rsp_h_dec", X_SIZE-1, Y_SIZE); // Vertical inter-clusters RAM network DSPIN DspinSignals** signal_dspin_ram_cmd_v_inc = - alloc_elems >("signal_dspin_ram_cmd_v_inc", XMAX, YMAX-1); + alloc_elems >("signal_dspin_ram_cmd_v_inc", X_SIZE, Y_SIZE-1); DspinSignals** signal_dspin_ram_cmd_v_dec = - alloc_elems >("signal_dspin_ram_cmd_v_dec", XMAX, YMAX-1); + alloc_elems >("signal_dspin_ram_cmd_v_dec", X_SIZE, Y_SIZE-1); DspinSignals** signal_dspin_ram_rsp_v_inc = - alloc_elems >("signal_dspin_ram_rsp_v_inc", XMAX, YMAX-1); + alloc_elems >("signal_dspin_ram_rsp_v_inc", X_SIZE, Y_SIZE-1); DspinSignals** signal_dspin_ram_rsp_v_dec = - alloc_elems >("signal_dspin_ram_rsp_v_dec", XMAX, YMAX-1); + alloc_elems >("signal_dspin_ram_rsp_v_dec", X_SIZE, Y_SIZE-1); // Mesh boundaries RAM network DSPIN DspinSignals*** signal_dspin_false_ram_cmd_in = - alloc_elems >("signal_dspin_false_ram_cmd_in", XMAX, YMAX, 4); + alloc_elems >("signal_dspin_false_ram_cmd_in", X_SIZE, Y_SIZE, 4); DspinSignals*** signal_dspin_false_ram_cmd_out = - alloc_elems >("signal_dspin_false_ram_cmd_out", XMAX, YMAX, 4); + alloc_elems >("signal_dspin_false_ram_cmd_out", X_SIZE, Y_SIZE, 4); DspinSignals*** signal_dspin_false_ram_rsp_in = - alloc_elems >("signal_dspin_false_ram_rsp_in", XMAX, YMAX, 4); + alloc_elems >("signal_dspin_false_ram_rsp_in", X_SIZE, Y_SIZE, 4); DspinSignals*** signal_dspin_false_ram_rsp_out = - alloc_elems >("signal_dspin_false_ram_rsp_out", XMAX, YMAX, 4); + alloc_elems >("signal_dspin_false_ram_rsp_out", X_SIZE, Y_SIZE, 4); //////////////////////////// @@ -1003,5 +998,5 @@ dspin_int_rsp_width, dspin_ram_cmd_width, - dspin_ram_rsp_width>* clusters[XMAX][YMAX]; + dspin_ram_rsp_width>* clusters[X_SIZE][Y_SIZE]; #if USE_OPENMP @@ -1010,8 +1005,8 @@ #pragma omp for #endif - for(size_t i = 0; i < (XMAX * YMAX); i++) + for(size_t i = 0; i < (X_SIZE * Y_SIZE); i++) { - size_t x = i / YMAX; - size_t y = i % YMAX; + size_t x = i / Y_SIZE; + size_t y = i % Y_SIZE; #if USE_OPENMP @@ -1048,6 +1043,8 @@ x, y, - XMAX, - YMAX, + X_SIZE, + Y_SIZE, + + P_WIDTH, maptab_int, @@ -1055,7 +1052,7 @@ maptab_iox, - x_width, - y_width, - vci_srcid_width - x_width - y_width, // l_id width, + X_WIDTH, + Y_WIDTH, + vci_srcid_width - X_WIDTH - Y_WIDTH, // l_id width, INT_MEMC_TGT_ID, @@ -1216,12 +1213,12 @@ if ( cluster_iob0 != cluster_iob1 ) { - (*clusters[XMAX-1][YMAX-1]->p_vci_iob_iox_ini) (signal_vci_ini_iob1); - (*clusters[XMAX-1][YMAX-1]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob1); + (*clusters[X_SIZE-1][Y_SIZE-1]->p_vci_iob_iox_ini) (signal_vci_ini_iob1); + (*clusters[X_SIZE-1][Y_SIZE-1]->p_vci_iob_iox_tgt) (signal_vci_tgt_iob1); } // All clusters Clock & RESET connexions - for ( size_t x = 0; x < (XMAX); x++ ) + for ( size_t x = 0; x < (X_SIZE); x++ ) { - for (size_t y = 0; y < YMAX; y++) + for (size_t y = 0; y < Y_SIZE; y++) { clusters[x][y]->p_clk (signal_clk); @@ -1231,9 +1228,9 @@ // Inter Clusters horizontal connections - if (XMAX > 1) + if (X_SIZE > 1) { - for (size_t x = 0; x < (XMAX-1); x++) + for (size_t x = 0; x < (X_SIZE-1); x++) { - for (size_t y = 0; y < YMAX; y++) + for (size_t y = 0; y < Y_SIZE; y++) { for (size_t k = 0; k < 3; k++) @@ -1268,9 +1265,9 @@ // Inter Clusters vertical connections - if (YMAX > 1) + if (Y_SIZE > 1) { - for (size_t y = 0; y < (YMAX-1); y++) + for (size_t y = 0; y < (Y_SIZE-1); y++) { - for (size_t x = 0; x < XMAX; x++) + for (size_t x = 0; x < X_SIZE; x++) { for (size_t k = 0; k < 3; k++) @@ -1305,5 +1302,5 @@ // East & West boundary cluster connections - for (size_t y = 0; y < YMAX; y++) + for (size_t y = 0; y < Y_SIZE; y++) { for (size_t k = 0; k < 3; k++) @@ -1311,6 +1308,6 @@ clusters[0][y]->p_dspin_int_cmd_in[WEST][k] (signal_dspin_false_int_cmd_in[0][y][WEST][k]); clusters[0][y]->p_dspin_int_cmd_out[WEST][k] (signal_dspin_false_int_cmd_out[0][y][WEST][k]); - clusters[XMAX-1][y]->p_dspin_int_cmd_in[EAST][k] (signal_dspin_false_int_cmd_in[XMAX-1][y][EAST][k]); - clusters[XMAX-1][y]->p_dspin_int_cmd_out[EAST][k] (signal_dspin_false_int_cmd_out[XMAX-1][y][EAST][k]); + clusters[X_SIZE-1][y]->p_dspin_int_cmd_in[EAST][k] (signal_dspin_false_int_cmd_in[X_SIZE-1][y][EAST][k]); + clusters[X_SIZE-1][y]->p_dspin_int_cmd_out[EAST][k] (signal_dspin_false_int_cmd_out[X_SIZE-1][y][EAST][k]); } @@ -1319,6 +1316,6 @@ clusters[0][y]->p_dspin_int_rsp_in[WEST][k] (signal_dspin_false_int_rsp_in[0][y][WEST][k]); clusters[0][y]->p_dspin_int_rsp_out[WEST][k] (signal_dspin_false_int_rsp_out[0][y][WEST][k]); - clusters[XMAX-1][y]->p_dspin_int_rsp_in[EAST][k] (signal_dspin_false_int_rsp_in[XMAX-1][y][EAST][k]); - clusters[XMAX-1][y]->p_dspin_int_rsp_out[EAST][k] (signal_dspin_false_int_rsp_out[XMAX-1][y][EAST][k]); + clusters[X_SIZE-1][y]->p_dspin_int_rsp_in[EAST][k] (signal_dspin_false_int_rsp_in[X_SIZE-1][y][EAST][k]); + clusters[X_SIZE-1][y]->p_dspin_int_rsp_out[EAST][k] (signal_dspin_false_int_rsp_out[X_SIZE-1][y][EAST][k]); } @@ -1328,8 +1325,8 @@ clusters[0][y]->p_dspin_ram_rsp_out[WEST] (signal_dspin_false_ram_rsp_out[0][y][WEST]); - clusters[XMAX-1][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_false_ram_cmd_in[XMAX-1][y][EAST]); - clusters[XMAX-1][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_false_ram_cmd_out[XMAX-1][y][EAST]); - clusters[XMAX-1][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_false_ram_rsp_in[XMAX-1][y][EAST]); - clusters[XMAX-1][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_false_ram_rsp_out[XMAX-1][y][EAST]); + clusters[X_SIZE-1][y]->p_dspin_ram_cmd_in[EAST] (signal_dspin_false_ram_cmd_in[X_SIZE-1][y][EAST]); + clusters[X_SIZE-1][y]->p_dspin_ram_cmd_out[EAST] (signal_dspin_false_ram_cmd_out[X_SIZE-1][y][EAST]); + clusters[X_SIZE-1][y]->p_dspin_ram_rsp_in[EAST] (signal_dspin_false_ram_rsp_in[X_SIZE-1][y][EAST]); + clusters[X_SIZE-1][y]->p_dspin_ram_rsp_out[EAST] (signal_dspin_false_ram_rsp_out[X_SIZE-1][y][EAST]); } @@ -1337,5 +1334,5 @@ // North & South boundary clusters connections - for (size_t x = 0; x < XMAX; x++) + for (size_t x = 0; x < X_SIZE; x++) { for (size_t k = 0; k < 3; k++) @@ -1343,6 +1340,6 @@ clusters[x][0]->p_dspin_int_cmd_in[SOUTH][k] (signal_dspin_false_int_cmd_in[x][0][SOUTH][k]); clusters[x][0]->p_dspin_int_cmd_out[SOUTH][k] (signal_dspin_false_int_cmd_out[x][0][SOUTH][k]); - clusters[x][YMAX-1]->p_dspin_int_cmd_in[NORTH][k] (signal_dspin_false_int_cmd_in[x][YMAX-1][NORTH][k]); - clusters[x][YMAX-1]->p_dspin_int_cmd_out[NORTH][k] (signal_dspin_false_int_cmd_out[x][YMAX-1][NORTH][k]); + clusters[x][Y_SIZE-1]->p_dspin_int_cmd_in[NORTH][k] (signal_dspin_false_int_cmd_in[x][Y_SIZE-1][NORTH][k]); + clusters[x][Y_SIZE-1]->p_dspin_int_cmd_out[NORTH][k] (signal_dspin_false_int_cmd_out[x][Y_SIZE-1][NORTH][k]); } @@ -1351,6 +1348,6 @@ clusters[x][0]->p_dspin_int_rsp_in[SOUTH][k] (signal_dspin_false_int_rsp_in[x][0][SOUTH][k]); clusters[x][0]->p_dspin_int_rsp_out[SOUTH][k] (signal_dspin_false_int_rsp_out[x][0][SOUTH][k]); - clusters[x][YMAX-1]->p_dspin_int_rsp_in[NORTH][k] (signal_dspin_false_int_rsp_in[x][YMAX-1][NORTH][k]); - clusters[x][YMAX-1]->p_dspin_int_rsp_out[NORTH][k] (signal_dspin_false_int_rsp_out[x][YMAX-1][NORTH][k]); + clusters[x][Y_SIZE-1]->p_dspin_int_rsp_in[NORTH][k] (signal_dspin_false_int_rsp_in[x][Y_SIZE-1][NORTH][k]); + clusters[x][Y_SIZE-1]->p_dspin_int_rsp_out[NORTH][k] (signal_dspin_false_int_rsp_out[x][Y_SIZE-1][NORTH][k]); } @@ -1360,8 +1357,8 @@ clusters[x][0]->p_dspin_ram_rsp_out[SOUTH] (signal_dspin_false_ram_rsp_out[x][0][SOUTH]); - clusters[x][YMAX-1]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_false_ram_cmd_in[x][YMAX-1][NORTH]); - clusters[x][YMAX-1]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_false_ram_cmd_out[x][YMAX-1][NORTH]); - clusters[x][YMAX-1]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_false_ram_rsp_in[x][YMAX-1][NORTH]); - clusters[x][YMAX-1]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_false_ram_rsp_out[x][YMAX-1][NORTH]); + clusters[x][Y_SIZE-1]->p_dspin_ram_cmd_in[NORTH] (signal_dspin_false_ram_cmd_in[x][Y_SIZE-1][NORTH]); + clusters[x][Y_SIZE-1]->p_dspin_ram_cmd_out[NORTH] (signal_dspin_false_ram_cmd_out[x][Y_SIZE-1][NORTH]); + clusters[x][Y_SIZE-1]->p_dspin_ram_rsp_in[NORTH] (signal_dspin_false_ram_rsp_in[x][Y_SIZE-1][NORTH]); + clusters[x][Y_SIZE-1]->p_dspin_ram_rsp_out[NORTH] (signal_dspin_false_ram_rsp_out[x][Y_SIZE-1][NORTH]); } @@ -1378,7 +1375,7 @@ // network boundaries signals - for (size_t x = 0; x < XMAX ; x++) + for (size_t x = 0; x < X_SIZE ; x++) { - for (size_t y = 0; y < YMAX ; y++) + for (size_t y = 0; y < Y_SIZE ; y++) { for (size_t a = 0; a < 4; a++) @@ -1525,5 +1522,5 @@ { clusters[0][0]->iob->print_trace(); - clusters[XMAX-1][YMAX-1]->iob->print_trace(); + clusters[X_SIZE-1][Y_SIZE-1]->iob->print_trace(); // clusters[0][0]->signal_int_vci_tgt_iobx.print_trace( "[SIG]IOB0_INT_TGT"); // clusters[0][0]->signal_int_vci_ini_iobx.print_trace( "[SIG]IOB0_INT_INI"); Index: branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h =================================================================== --- branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h (revision 805) +++ branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/include/tsar_iob_cluster.h (revision 806) @@ -1,5 +1,5 @@ ////////////////////////////////////////////////////////////////////////////// // File: tsar_iob_cluster.h -// Author: Alain Greiner +// Author: Alain Greiner // Copyright: UPMC/LIP6 // Date : april 2013 @@ -37,11 +37,11 @@ /////////////////////////////////////////////////////////////////////////// -template -class TsarIobCluster +class TsarIobCluster /////////////////////////////////////////////////////////////////////////// : public soclib::caba::BaseModule @@ -56,5 +56,5 @@ // Thes two ports are used to connect IOB to IOX nework in top cell soclib::caba::VciInitiator* p_vci_iob_iox_ini; - soclib::caba::VciTarget* p_vci_iob_iox_tgt; + soclib::caba::VciTarget* p_vci_iob_iox_tgt; // These arrays of ports are used to connect the INT & RAM networks in top cell @@ -74,21 +74,21 @@ sc_signal signal_irq_mdma[8]; sc_signal signal_irq_memc; - + // INT network DSPIN signals between DSPIN routers and DSPIN local_crossbars - DspinSignals signal_int_dspin_cmd_l2g_d; - DspinSignals signal_int_dspin_cmd_g2l_d; + DspinSignals signal_int_dspin_cmd_l2g_d; + DspinSignals signal_int_dspin_cmd_g2l_d; DspinSignals signal_int_dspin_m2p_l2g_c; - DspinSignals signal_int_dspin_m2p_g2l_c; + DspinSignals signal_int_dspin_m2p_g2l_c; DspinSignals signal_int_dspin_clack_l2g_c; DspinSignals signal_int_dspin_clack_g2l_c; - DspinSignals signal_int_dspin_rsp_l2g_d; - DspinSignals signal_int_dspin_rsp_g2l_d; + DspinSignals signal_int_dspin_rsp_l2g_d; + DspinSignals signal_int_dspin_rsp_g2l_d; DspinSignals signal_int_dspin_p2m_l2g_c; DspinSignals signal_int_dspin_p2m_g2l_c; // INT network VCI signals between VCI components and VCI local crossbar - VciSignals signal_int_vci_ini_proc[8]; - VciSignals signal_int_vci_ini_mdma; - VciSignals signal_int_vci_ini_iobx; + VciSignals signal_int_vci_ini_proc[8]; + VciSignals signal_int_vci_ini_mdma; + VciSignals signal_int_vci_ini_iobx; VciSignals signal_int_vci_tgt_memc; @@ -101,5 +101,5 @@ VciSignals signal_int_vci_g2l; - // Coherence DSPIN signals between DSPIN local crossbars and CC components + // Coherence DSPIN signals between DSPIN local crossbars and CC components DspinSignals signal_int_dspin_m2p_memc; DspinSignals signal_int_dspin_clack_memc; @@ -115,5 +115,5 @@ // RAM network DSPIN signals between VCI/DSPIN wrappers, RAM dspin crossbar - // and routers + // and routers DspinSignals signal_ram_dspin_cmd_xram_t; DspinSignals signal_ram_dspin_rsp_xram_t; @@ -126,9 +126,9 @@ DspinSignals signal_ram_dspin_cmd_false; DspinSignals signal_ram_dspin_rsp_false; - + ////////////////////////////////////// // Hardwate Components (pointers) ////////////////////////////////////// - VciCcVCacheWrapper* memc; @@ -151,5 +151,5 @@ VciLocalCrossbar* int_xbar_d; - + VciDspinInitiatorWrapper* xram_ram_wt; - + DspinRouter* ram_router_cmd; DspinRouter* ram_router_rsp; @@ -178,5 +178,5 @@ DspinLocalCrossbar* ram_xbar_cmd; DspinLocalCrossbar* ram_xbar_rsp; - + // IO Network Components (not instanciated in all clusters) @@ -191,10 +191,12 @@ // cluster constructor TsarIobCluster( sc_module_name insname, - size_t nb_procs, - size_t nb_dmas, + size_t nb_procs, + size_t nb_dmas, size_t x, // x coordinate size_t y, // y coordinate - size_t xmax, - size_t ymax, + size_t x_size, + size_t y_size, + + size_t p_width, // pid field bits const soclib::common::MappingTable &mt_int, @@ -226,8 +228,8 @@ size_t memc_sets, size_t l1_i_ways, - size_t l1_i_sets, + size_t l1_i_sets, size_t l1_d_ways, - size_t l1_d_sets, - size_t xram_latency, + size_t l1_d_sets, + size_t xram_latency, size_t xcu_nb_inputs, @@ -236,9 +238,9 @@ const Loader &loader, // loader for XRAM - uint32_t frozen_cycles, + uint32_t frozen_cycles, uint32_t start_debug_cycle, - bool memc_debug_ok, - bool proc_debug_ok, - bool iob0_debug_ok ); + bool memc_debug_ok, + bool proc_debug_ok, + bool iob0_debug_ok ); protected: @@ -247,5 +249,5 @@ void init(); - + }; Index: branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp =================================================================== --- branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp (revision 805) +++ branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/source/src/tsar_iob_cluster.cpp (revision 806) @@ -1,14 +1,14 @@ ////////////////////////////////////////////////////////////////////////////// // File: tsar_iob_cluster.cpp -// Author: Alain Greiner +// Author: Alain Greiner // Copyright: UPMC/LIP6 // Date : april 2013 // This program is released under the GNU public license ////////////////////////////////////////////////////////////////////////////// -// Cluster(0,0) & Cluster(xmax-1,ymax-1) contains the IOB0 & IOB1 components. +// Cluster(0,0) & Cluster(x_size-1,y_size-1) contains the IOB0 & IOB1 components. // These two clusters contain 6 extra components: // - 1 vci_io_bridge (connected to the 3 networks. // - 3 vci_dspin_wrapper for the IOB. -// - 2 dspin_local_crossbar for commands and responses. +// - 2 dspin_local_crossbar for commands and responses. ////////////////////////////////////////////////////////////////////////////// @@ -30,64 +30,69 @@ ////////////////////////////////////////////////////////////////////////// tmpl(/**/)::TsarIobCluster( -////////////////////////////////////////////////////////////////////////// - sc_module_name insname, - size_t nb_procs, - size_t nb_dmas, - size_t x_id, - size_t y_id, - size_t xmax, - size_t ymax, - - const soclib::common::MappingTable &mt_int, - const soclib::common::MappingTable &mt_ram, - const soclib::common::MappingTable &mt_iox, - - size_t x_width, - size_t y_width, - size_t l_width, - - size_t int_memc_tgt_id, // local index - size_t int_xicu_tgt_id, // local index - size_t int_mdma_tgt_id, // local index - size_t int_brom_tgt_id, // local index - size_t int_iobx_tgt_id, // local index - - size_t int_proc_ini_id, // local index - size_t int_mdma_ini_id, // local index - size_t int_iobx_ini_id, // local index - - size_t ram_xram_tgt_id, // local index - size_t ram_memc_ini_id, // local index - size_t ram_iobx_ini_id, // local index - - bool is_io, // is IO cluster (IOB)? - size_t iox_iobx_tgt_id, // local_index - size_t iox_iobx_ini_id, // local index - - size_t memc_ways, - size_t memc_sets, - size_t l1_i_ways, - size_t l1_i_sets, - size_t l1_d_ways, - size_t l1_d_sets, - size_t xram_latency, - size_t xcu_nb_inputs, - - bool distboot, - - const Loader &loader, - - uint32_t frozen_cycles, - uint32_t debug_start_cycle, - bool memc_debug_ok, - bool proc_debug_ok, - bool iob_debug_ok ) - : soclib::caba::BaseModule(insname), - p_clk("clk"), - p_resetn("resetn") + sc_module_name insname, + size_t nb_procs, + size_t nb_dmas, + size_t x_id, + size_t y_id, + size_t x_size, + size_t y_size, + + size_t p_width, + + const soclib::common::MappingTable &mt_int, + const soclib::common::MappingTable &mt_ram, + const soclib::common::MappingTable &mt_iox, + + size_t x_width, + size_t y_width, + size_t l_width, + + size_t int_memc_tgt_id, // local index + size_t int_xicu_tgt_id, // local index + size_t int_mdma_tgt_id, // local index + size_t int_brom_tgt_id, // local index + size_t int_iobx_tgt_id, // local index + + size_t int_proc_ini_id, // local index + size_t int_mdma_ini_id, // local index + size_t int_iobx_ini_id, // local index + + size_t ram_xram_tgt_id, // local index + size_t ram_memc_ini_id, // local index + size_t ram_iobx_ini_id, // local index + + bool is_io, // is IO cluster (IOB)? + size_t iox_iobx_tgt_id, // local_index + size_t iox_iobx_ini_id, // local index + + size_t memc_ways, + size_t memc_sets, + size_t l1_i_ways, + size_t l1_i_sets, + size_t l1_d_ways, + size_t l1_d_sets, + size_t xram_latency, + size_t xcu_nb_inputs, + + bool distboot, + + const Loader &loader, + + uint32_t frozen_cycles, + uint32_t debug_start_cycle, + bool memc_debug_ok, + bool proc_debug_ok, + bool iob_debug_ok ) : + + // constructor initialization list + + soclib::caba::BaseModule(insname), + p_clk("clk"), + p_resetn("resetn") { - assert( (x_id < xmax) and (y_id < ymax) and "Illegal cluster coordinates"); - - size_t cluster_id = (x_id<<4) + y_id; + + assert( (x_id < x_size) and (y_id < y_size) and "Illegal cluster coordinates"); + + size_t cluster_id = (x_id << x_width) | y_id; // Vectors of DSPIN ports for inter-cluster communications @@ -103,8 +108,8 @@ // VCI ports from IOB to IOX network (only in IO clusters) - if ( is_io ) + if (is_io) { p_vci_iob_iox_ini = new soclib::caba::VciInitiator; - p_vci_iob_iox_tgt = new soclib::caba::VciTarget; + p_vci_iob_iox_tgt = new soclib::caba::VciTarget; } @@ -115,5 +120,5 @@ //////////// PROCS for (size_t p = 0; p < nb_procs; p++) - { + { std::ostringstream s_proc; s_proc << "proc_" << x_id << "_" << y_id << "_" << p; @@ -123,8 +128,8 @@ GdbServer >( s_proc.str().c_str(), - cluster_id*nb_procs + p, // GLOBAL PROC_ID + (cluster_id << p_width) | p, // GLOBAL PROC_ID mt_int, // Mapping Table INT network IntTab(cluster_id,p), // SRCID - (cluster_id << l_width) + p, // CC_GLOBAL_ID + (cluster_id << l_width) | p, // CC_GLOBAL_ID 8, // ITLB ways 8, // ITLB sets @@ -135,6 +140,6 @@ 4, // WBUF nlines 4, // WBUF nwords - x_width, - y_width, + x_width, // number of bits for x coordinate + y_width, // number of bits for y coordinate frozen_cycles, // max frozen cycles debug_start_cycle, @@ -150,5 +155,5 @@ } - /////////// MEMC + /////////// MEMC std::ostringstream s_memc; s_memc << "memc_" << x_id << "_" << y_id; @@ -225,5 +230,5 @@ cluster_id, // cluster id nb_direct_initiators, // number of local initiators - nb_direct_targets, // number of local targets + nb_direct_targets, // number of local targets 0 ); // default target @@ -255,6 +260,6 @@ x_width, y_width, l_width, // several dests 1, // number of local sources - nb_procs, // number of local dests - 2, 2, // fifo depths + nb_procs, // number of local dests + 2, 2, // fifo depths true, // pseudo CMD false, // no routing table @@ -270,8 +275,8 @@ nb_procs, // number of local sources 1, // number of local dests - 2, 2, // fifo depths + 2, 2, // fifo depths false, // pseudo RSP false, // no routing table - false ); // no broacast + false ); // no broacast std::ostringstream s_int_xbar_clack_c; @@ -283,5 +288,5 @@ x_width, y_width, l_width, 1, // number of local sources - nb_procs, // number of local targets + nb_procs, // number of local targets 1, 1, // fifo depths true, // CMD @@ -297,5 +302,5 @@ x_width, y_width, // x & y fields width 3, // nb virtual channels - 4,4); // input & output fifo depths + 4, 4); // input & output fifo depths std::ostringstream s_int_router_rsp; @@ -306,5 +311,5 @@ x_width, y_width, // x & y fields width 2, // nb virtual channels - 4,4); // input & output fifo depths + 4, 4); // input & output fifo depths ////////////// XRAM @@ -351,7 +356,7 @@ /////////// IO_BRIDGE std::ostringstream s_iob; - s_iob << "iob_" << x_id << "_" << y_id; + s_iob << "iob_" << x_id << "_" << y_id; iob = new VciIoBridge( + vci_param_ext>( s_iob.str().c_str(), mt_ram, // EXT network maptab @@ -367,7 +372,7 @@ debug_start_cycle, iob_debug_ok ); - + std::ostringstream s_iob_ram_wi; - s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id; + s_iob_ram_wi << "iob_ram_wi_" << x_id << "_" << y_id; iob_ram_wi = new VciDspinInitiatorWrapperp_clk (this->p_clk); @@ -438,5 +443,5 @@ int_router_cmd->p_in[4][1] (signal_int_dspin_m2p_l2g_c); int_router_cmd->p_in[4][2] (signal_int_dspin_clack_l2g_c); - + int_router_rsp->p_out[4][0] (signal_int_dspin_rsp_g2l_d); int_router_rsp->p_out[4][1] (signal_int_dspin_p2m_g2l_c); @@ -475,5 +480,5 @@ int_wt_gate_d->p_dspin_cmd (signal_int_dspin_cmd_g2l_d); int_wt_gate_d->p_dspin_rsp (signal_int_dspin_rsp_l2g_d); - + ////////////////////// M2P DSPIN local crossbar coherence int_xbar_m2p_c->p_clk (this->p_clk); @@ -482,5 +487,5 @@ int_xbar_m2p_c->p_global_in (signal_int_dspin_m2p_g2l_c); int_xbar_m2p_c->p_local_in[0] (signal_int_dspin_m2p_memc); - for (size_t p = 0; p < nb_procs; p++) + for (size_t p = 0; p < nb_procs; p++) int_xbar_m2p_c->p_local_out[p] (signal_int_dspin_m2p_proc[p]); @@ -491,5 +496,5 @@ int_xbar_p2m_c->p_global_in (signal_int_dspin_p2m_g2l_c); int_xbar_p2m_c->p_local_out[0] (signal_int_dspin_p2m_memc); - for (size_t p = 0; p < nb_procs; p++) + for (size_t p = 0; p < nb_procs; p++) int_xbar_p2m_c->p_local_in[p] (signal_int_dspin_p2m_proc[p]); @@ -533,5 +538,5 @@ else if ( i <= nb_dmas ) xicu->p_hwi[i] (signal_irq_mdma[i-1]); else xicu->p_hwi[i] (signal_false); - } + } ///////////////////////////////////// MEMC @@ -603,6 +608,6 @@ ram_router_rsp->p_out[4] (signal_ram_dspin_rsp_memc_i); } - - ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. + + ///////////////////////// IOB exists only in cluster_iob0 & cluster_iob1. if ( is_io ) {