Index: /trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
===================================================================
--- /trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 808)
+++ /trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 809)
@@ -1205,18 +1205,30 @@
                     if (not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER))
                     {
-                        r_mmu_ietr         = MMU_READ_PRIVILEGE_VIOLATION;
-                        r_mmu_ibvar        = m_ireq.addr;
-                        m_irsp.valid       = true;
-                        m_irsp.error       = true;
-                        m_irsp.instruction = 0;
+
+#if DEBUG_ICACHE
+if ( m_debug_icache_fsm )
+std::cout << "  <PROC " << name() << " ICACHE_IDLE> MMU Privilege Violation" 
+          << " : PADDR = " << std::hex << paddr << std::endl;
+#endif
+                        r_mmu_ietr          = MMU_READ_PRIVILEGE_VIOLATION;
+                        r_mmu_ibvar         = m_ireq.addr;
+                        m_irsp.valid        = true;
+                        m_irsp.error        = true;
+                        m_irsp.instruction  = 0;
                         break;
                     }
                     else if (not tlb_flags.x)
                     {
-                        r_mmu_ietr         = MMU_READ_EXEC_VIOLATION;
-                        r_mmu_ibvar        = m_ireq.addr;
-                        m_irsp.valid       = true;
-                        m_irsp.error       = true;
-                        m_irsp.instruction = 0;
+
+#if DEBUG_ICACHE
+if ( m_debug_icache_fsm )
+std::cout << "  <PROC " << name() << " ICACHE_IDLE> MMU Executable Violation" 
+          << " : PADDR = " << std::hex << paddr << std::endl;
+#endif
+                        r_mmu_ietr          = MMU_READ_EXEC_VIOLATION;
+                        r_mmu_ibvar         = m_ireq.addr;
+                        m_irsp.valid        = true;
+                        m_irsp.error        = true;
+                        m_irsp.instruction  = 0;
                         break;
                     }