Index: branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
===================================================================
--- branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	(revision 787)
+++ branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	(revision 814)
@@ -25,5 +25,5 @@
  * SOCLIB_LGPL_HEADER_END
  *
- * Maintainers: alain.greiner@lip6.fr 
+ * Maintainers: alain.greiner@lip6.fr
  *              eric.guthmuller@polytechnique.edu
  *              cesar.fuguet-tortolero@lip6.fr
@@ -62,5 +62,5 @@
   using namespace sc_core;
 
-  template<typename vci_param_int, 
+  template<typename vci_param_int,
            typename vci_param_ext,
            size_t   dspin_in_width,
@@ -416,5 +416,5 @@
       };
 
-      // debug variables 
+      // debug variables
       bool     m_debug;
       bool     m_debug_previous_valid;
@@ -479,5 +479,5 @@
       uint32_t m_cpt_heap_unused;             // NB cycles HEAP LOCK unused
       uint32_t m_cpt_heap_slot_available;     // NB HEAP slot available refresh at each cycles
-      uint32_t m_cpt_heap_min_slot_available; // NB HEAP : Min of slot available 
+      uint32_t m_cpt_heap_min_slot_available; // NB HEAP : Min of slot available
 
       uint32_t m_cpt_ncc_to_cc_read;         // NB change from NCC to CC caused by a READ
@@ -525,22 +525,22 @@
 
 #if MONITOR_MEMCACHE_FSM == 1
-      sc_out<int> p_read_fsm; 
-      sc_out<int> p_write_fsm; 
-      sc_out<int> p_xram_rsp_fsm; 
-      sc_out<int> p_cas_fsm; 
-      sc_out<int> p_cleanup_fsm; 
-      sc_out<int> p_config_fsm; 
-      sc_out<int> p_alloc_heap_fsm; 
-      sc_out<int> p_alloc_dir_fsm; 
-      sc_out<int> p_alloc_trt_fsm; 
-      sc_out<int> p_alloc_upt_fsm; 
-      sc_out<int> p_alloc_ivt_fsm; 
-      sc_out<int> p_tgt_cmd_fsm; 
-      sc_out<int> p_tgt_rsp_fsm; 
-      sc_out<int> p_ixr_cmd_fsm; 
-      sc_out<int> p_ixr_rsp_fsm; 
-      sc_out<int> p_cc_send_fsm; 
-      sc_out<int> p_cc_receive_fsm; 
-      sc_out<int> p_multi_ack_fsm; 
+      sc_out<int> p_read_fsm;
+      sc_out<int> p_write_fsm;
+      sc_out<int> p_xram_rsp_fsm;
+      sc_out<int> p_cas_fsm;
+      sc_out<int> p_cleanup_fsm;
+      sc_out<int> p_config_fsm;
+      sc_out<int> p_alloc_heap_fsm;
+      sc_out<int> p_alloc_dir_fsm;
+      sc_out<int> p_alloc_trt_fsm;
+      sc_out<int> p_alloc_upt_fsm;
+      sc_out<int> p_alloc_ivt_fsm;
+      sc_out<int> p_tgt_cmd_fsm;
+      sc_out<int> p_tgt_rsp_fsm;
+      sc_out<int> p_ixr_cmd_fsm;
+      sc_out<int> p_ixr_rsp_fsm;
+      sc_out<int> p_cc_send_fsm;
+      sc_out<int> p_cc_receive_fsm;
+      sc_out<int> p_multi_ack_fsm;
 #endif
 
@@ -558,7 +558,7 @@
           const size_t                       max_copies,      // max number of copies
           const size_t                       heap_size=HEAP_ENTRIES,
-          const size_t                       trt_lines=TRT_ENTRIES, 
-          const size_t                       upt_lines=UPT_ENTRIES,     
-          const size_t                       ivt_lines=IVT_ENTRIES,     
+          const size_t                       trt_lines=TRT_ENTRIES,
+          const size_t                       upt_lines=UPT_ENTRIES,
+          const size_t                       ivt_lines=IVT_ENTRIES,
           const size_t                       debug_start_cycle=0,
           const bool                         debug_ok=false );
@@ -584,5 +584,5 @@
 
       // Component attributes
-      std::list<soclib::common::Segment> m_seglist;          // segments allocated 
+      std::list<soclib::common::Segment> m_seglist;          // segments allocated
       size_t                             m_nseg;             // number of segments
       soclib::common::Segment            **m_seg;            // array of segments pointers
@@ -657,5 +657,5 @@
       // Fifo between CC_RECEIVE fsm and CLEANUP fsm
       GenericFifo<uint64_t>  m_cc_receive_to_cleanup_fifo;
-      
+
       // Fifo between CC_RECEIVE fsm and MULTI_ACK fsm
       GenericFifo<uint64_t>  m_cc_receive_to_multi_ack_fifo;
@@ -686,5 +686,5 @@
       sc_signal<int>      r_config_fsm;               // FSM state
       sc_signal<bool>     r_config_lock;              // lock protecting exclusive access
-      sc_signal<int>      r_config_cmd;               // config request type  
+      sc_signal<int>      r_config_cmd;               // config request type
       sc_signal<addr_t>   r_config_address;           // target buffer physical address
       sc_signal<size_t>   r_config_srcid;             // config request srcid
@@ -702,5 +702,5 @@
       sc_signal<size_t>   r_config_heap_next;         // current pointer to scan HEAP
       sc_signal<size_t>   r_config_trt_index;         // selected entry in TRT
-      sc_signal<size_t>   r_config_ivt_index;         // selected entry in IVT 
+      sc_signal<size_t>   r_config_ivt_index;         // selected entry in IVT
 
       // Buffer between CONFIG fsm and IXR_CMD fsm
@@ -744,5 +744,5 @@
       sc_signal<addr_t>   r_read_ll_key;              // LL key from llsc_global_table
 
-      // Buffer between READ fsm and IXR_CMD fsm 
+      // Buffer between READ fsm and IXR_CMD fsm
       sc_signal<bool>     r_read_to_ixr_cmd_req;      // valid request
       sc_signal<size_t>   r_read_to_ixr_cmd_index;    // TRT index
@@ -764,5 +764,5 @@
       sc_signal<bool>     r_read_to_cc_send_inst;
 
-      //RWT: Buffer between READ fsm and CLEANUP fsm (wait for the data coming from L1 cache) 
+      //RWT: Buffer between READ fsm and CLEANUP fsm (wait for the data coming from L1 cache)
       sc_signal<bool>     r_read_to_cleanup_req;    // valid request
       sc_signal<addr_t>   r_read_to_cleanup_nline;  // cache line index
@@ -771,5 +771,5 @@
       sc_signal<size_t>   r_read_to_cleanup_length;
       sc_signal<size_t>   r_read_to_cleanup_first_word;
-      sc_signal<bool>     r_read_to_cleanup_cached_read;    
+      sc_signal<bool>     r_read_to_cleanup_cached_read;
       sc_signal<bool>     r_read_to_cleanup_is_ll;
       sc_signal<addr_t>   r_read_to_cleanup_addr;
@@ -810,5 +810,5 @@
       sc_signal<data_t>   r_write_sc_key;             // sc command key
       sc_signal<bool>     r_write_bc_data_we;         // Write enable for data buffer
- 
+
       // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1)
       sc_signal<bool>     r_write_to_tgt_rsp_req;     // valid request
@@ -818,7 +818,7 @@
       sc_signal<bool>     r_write_to_tgt_rsp_sc_fail; // sc command failed
 
-      // Buffer between WRITE fsm and IXR_CMD fsm 
+      // Buffer between WRITE fsm and IXR_CMD fsm
       sc_signal<bool>     r_write_to_ixr_cmd_req;     // valid request
-      sc_signal<size_t>   r_write_to_ixr_cmd_index;   // TRT index 
+      sc_signal<size_t>   r_write_to_ixr_cmd_index;   // TRT index
 
       // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches)
@@ -908,5 +908,5 @@
       sc_signal<size_t>   r_cleanup_to_tgt_rsp_trdid; // transaction trdid
       sc_signal<size_t>   r_cleanup_to_tgt_rsp_pktid; // transaction pktid
-      sc_signal<addr_t>     r_cleanup_to_tgt_rsp_ll_key;
+      sc_signal<addr_t>   r_cleanup_to_tgt_rsp_ll_key;
 
       //RWT
@@ -948,5 +948,5 @@
       // Buffer between CAS fsm and IXR_CMD fsm (XRAM write)
       sc_signal<bool>     r_cas_to_ixr_cmd_req;   // valid request
-      sc_signal<size_t>   r_cas_to_ixr_cmd_index; // TRT index 
+      sc_signal<size_t>   r_cas_to_ixr_cmd_index; // TRT index
 
       // Buffer between CAS fsm and TGT_RSP fsm
@@ -978,5 +978,5 @@
 
       // Buffer between IXR_RSP fsm and CONFIG fsm  (response from the XRAM)
-      sc_signal<bool>     r_ixr_rsp_to_config_ack;      // one single bit   
+      sc_signal<bool>     r_ixr_rsp_to_config_ack;      // one single bit
 
       // Buffer between IXR_RSP fsm and XRAM_RSP fsm  (response from the XRAM)
@@ -1028,7 +1028,7 @@
       GenericFifo<size_t> m_xram_rsp_to_cc_send_srcid_fifo;    // fifo for srcids
 
-      // Buffer between XRAM_RSP fsm and IXR_CMD fsm 
+      // Buffer between XRAM_RSP fsm and IXR_CMD fsm
       sc_signal<bool>     r_xram_rsp_to_ixr_cmd_req;   // Valid request
-      sc_signal<size_t>   r_xram_rsp_to_ixr_cmd_index; // TRT index 
+      sc_signal<size_t>   r_xram_rsp_to_ixr_cmd_index; // TRT index
 
       //RWT
@@ -1041,5 +1041,5 @@
       sc_signal<int>      r_ixr_cmd_fsm;
       sc_signal<size_t>   r_ixr_cmd_word;              // word index for a put
-      sc_signal<size_t>   r_ixr_cmd_trdid;             // TRT index value     
+      sc_signal<size_t>   r_ixr_cmd_trdid;             // TRT index value
       sc_signal<addr_t>   r_ixr_cmd_address;           // address to XRAM
       sc_signal<data_t> * r_ixr_cmd_wdata;             // cache line buffer
@@ -1112,9 +1112,9 @@
       sc_signal<data_t>    *r_cleanup_old_data;
       sc_signal<bool>      r_cleanup_contains_data;
-      
+
       sc_signal<bool>      r_cleanup_ncc;
       sc_signal<bool>      r_cleanup_to_ixr_cmd_ncc_l1_dirty;
       sc_signal<bool>      r_xram_rsp_to_ixr_cmd_inval_ncc_pending;
-      
+
       sc_signal<bool>      r_cleanup_to_ixr_cmd_req;
       sc_signal<data_t>    *r_cleanup_to_ixr_cmd_data;
