Index: branches/RWT/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp
===================================================================
--- branches/RWT/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp	(revision 787)
+++ branches/RWT/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp	(revision 814)
@@ -135,5 +135,5 @@
         "MULTI_ACK_UPT_LOCK",
         "MULTI_ACK_UPT_CLEAR",
-        "MULTI_ACK_WRITE_RSP",
+        "MULTI_ACK_WRITE_RSP"
     };
     const char *config_fsm_str[] =
@@ -496,20 +496,20 @@
 #if MONITOR_MEMCACHE_FSM == 1
             ,
-        p_read_fsm("p_read_fsm"), 
-        p_write_fsm("p_write_fsm"), 
-        p_xram_rsp_fsm("p_xram_rsp_fsm"), 
-        p_cas_fsm("p_cas_fsm"), 
-        p_cleanup_fsm("p_cleanup_fsm"), 
-        p_config_fsm("p_config_fsm"), 
-        p_alloc_heap_fsm("p_alloc_heap_fsm"), 
-        p_alloc_dir_fsm("p_alloc_dir_fsm"), 
-        p_alloc_trt_fsm("p_alloc_trt_fsm"), 
-        p_alloc_upt_fsm("p_alloc_upt_fsm"), 
-        p_alloc_ivt_fsm("p_alloc_ivt_fsm"), 
-        p_tgt_cmd_fsm("p_tgt_cmd_fsm"), 
-        p_tgt_rsp_fsm("p_tgt_rsp_fsm"), 
-        p_ixr_cmd_fsm("p_ixr_cmd_fsm"), 
-        p_ixr_rsp_fsm("p_ixr_rsp_fsm"), 
-        p_cc_send_fsm("p_cc_send_fsm"), 
+        p_read_fsm("p_read_fsm"),
+        p_write_fsm("p_write_fsm"),
+        p_xram_rsp_fsm("p_xram_rsp_fsm"),
+        p_cas_fsm("p_cas_fsm"),
+        p_cleanup_fsm("p_cleanup_fsm"),
+        p_config_fsm("p_config_fsm"),
+        p_alloc_heap_fsm("p_alloc_heap_fsm"),
+        p_alloc_dir_fsm("p_alloc_dir_fsm"),
+        p_alloc_trt_fsm("p_alloc_trt_fsm"),
+        p_alloc_upt_fsm("p_alloc_upt_fsm"),
+        p_alloc_ivt_fsm("p_alloc_ivt_fsm"),
+        p_tgt_cmd_fsm("p_tgt_cmd_fsm"),
+        p_tgt_rsp_fsm("p_tgt_rsp_fsm"),
+        p_ixr_cmd_fsm("p_ixr_cmd_fsm"),
+        p_ixr_rsp_fsm("p_ixr_rsp_fsm"),
+        p_cc_send_fsm("p_cc_send_fsm"),
         p_cc_receive_fsm("p_cc_receive_fsm"),
         p_multi_ack_fsm("p_multi_ack_fsm")
@@ -629,5 +629,5 @@
             {
                 m_debug_data[word] = m_cache_data.read(way, set, word);
-                if ( m_debug_previous_valid and 
+                if ( m_debug_previous_valid and
                         (m_debug_data[word] != m_debug_previous_data[word]) )
                 {
@@ -647,7 +647,7 @@
                 << " / VAL = " << std::dec << entry.valid
                 << " / WAY = " << way
-                << " / COUNT = " << entry.count 
+                << " / COUNT = " << entry.count
                 << " / DIRTY = " << entry.dirty
-                << " / DATA_CHANGE = " << data_change 
+                << " / DATA_CHANGE = " << data_change
                 << std::endl;
             std::cout << std::hex << "     /0:" << m_debug_data[0]
@@ -672,5 +672,5 @@
         m_debug_previous_valid = entry.valid;
         m_debug_previous_dirty = entry.dirty;
-        for( size_t word=0 ; word<m_words ; word++ ) 
+        for( size_t word=0 ; word<m_words ; word++ )
             m_debug_previous_data[word] = m_debug_data[word];
     }
@@ -840,5 +840,5 @@
     }
 
-   
+
     /////////////////////////////////////////
     tmpl(void)::reset_counters()
@@ -874,5 +874,5 @@
         m_cpt_update_remote       = 0;
         m_cpt_update_cost         = 0;
-        
+
         m_cpt_minval              = 0;
         m_cpt_minval_local        = 0;
@@ -893,5 +893,5 @@
         m_cpt_write_miss          = 0;
         m_cpt_write_dirty         = 0;
-        
+
         m_cpt_trt_rb              = 0;
         m_cpt_trt_full            = 0;
@@ -1329,5 +1329,5 @@
         // The READ/WRITE commands accepted in the configuration segment are targeting
         // configuration or status registers. They must contain one single flit.
-        // - For almost all addressable registers, the response is returned immediately. 
+        // - For almost all addressable registers, the response is returned immediately.
         // - For MEMC_CMD_TYPE, the response is delayed until the operation is completed.
         ////////////////////////////////////////////////////////////////////////////////////
@@ -1366,5 +1366,5 @@
                         else                       r_tgt_cmd_fsm = TGT_CMD_CONFIG;
                     }
-                    else                            //////////// memory access 
+                    else                            //////////// memory access
                     {
                         if ( p_vci_tgt.cmd.read() == vci_param_int::CMD_READ )
@@ -1411,5 +1411,5 @@
 
                             if((p_vci_tgt.pktid.read() & 0x7) == TYPE_CAS) r_tgt_cmd_fsm = TGT_CMD_CAS;
-                            else                                           r_tgt_cmd_fsm = TGT_CMD_WRITE; 
+                            else                                           r_tgt_cmd_fsm = TGT_CMD_WRITE;
                         }
                         else
@@ -1509,6 +1509,6 @@
                                   m_config_func_idx_mask;
 
-                    bool     need_rsp; 
-                    int      error;  
+                    bool     need_rsp;
+                    int      error;
                     uint32_t rdata = 0;         // default value
                     uint32_t wdata = p_vci_tgt.wdata.read();
@@ -1617,5 +1617,5 @@
 
                                         break;
-                                        
+
                                     default:
                                         error = 1;
@@ -1719,8 +1719,8 @@
                     size_t   cell     = (address - seg_base)/vci_param_int::B;
 
-                    bool     need_rsp; 
-                    size_t   error;  
+                    bool     need_rsp;
+                    size_t   error;
                     uint32_t rdata = 0;         // default value
-                    uint32_t wdata = p_vci_tgt.wdata.read();     
+                    uint32_t wdata = p_vci_tgt.wdata.read();
 
                     if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_READ)         // get lock
@@ -1830,7 +1830,7 @@
                         << " read command packet must contain one single flit" << std::endl;
                     exit(0);
-                } 
+                }
                 // check plen for LL
-                if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) and 
+                if ( (p_vci_tgt.cmd.read() == vci_param_int::CMD_LOCKED_READ) and
                         (p_vci_tgt.plen.read() != 8) )
                 {
@@ -1867,5 +1867,5 @@
                     }
                     else {
-                        if (is_local_req(p_vci_tgt.srcid.read())) 
+                        if (is_local_req(p_vci_tgt.srcid.read()))
                         {
                             m_cpt_read_local++;
@@ -1910,5 +1910,5 @@
                             m_cpt_write_flits_local++;
                         }
-                        else 
+                        else
                         {
                             m_cpt_write_flits_remote++;
@@ -1926,5 +1926,5 @@
                                 m_cpt_sc_local++;
                             }
-                            else 
+                            else
                             {
                                 m_cpt_sc_remote++;
@@ -1932,5 +1932,5 @@
                         }
                         else {
-                            if (is_local_req(p_vci_tgt.srcid.read())) 
+                            if (is_local_req(p_vci_tgt.srcid.read()))
                             {
                                 m_cpt_write_local++;
@@ -1973,5 +1973,5 @@
                     if (p_vci_tgt.eop) {
                         // <Activity counters>
-                        if (is_local_req(p_vci_tgt.srcid.read())) 
+                        if (is_local_req(p_vci_tgt.srcid.read()))
                         {
                             m_cpt_cas_local++;
@@ -1993,5 +1993,5 @@
         //    MULTI_ACK FSM
         /////////////////////////////////////////////////////////////////////////
-        // This FSM controls the response to the multicast update requests sent 
+        // This FSM controls the response to the multicast update requests sent
         // by the memory cache to the L1 caches and update the UPT.
         //
@@ -2133,5 +2133,5 @@
                 /////////////////////////
             case MULTI_ACK_WRITE_RSP:     // Post a response request to TGT_RSP FSM
-                // Wait if pending request 
+                // Wait if pending request
                 {
                     if ( r_multi_ack_to_tgt_rsp_req.read() ) break;
@@ -2168,9 +2168,9 @@
 
         //
-        // For both INVAL and SYNC commands, the CONFIG FSM contains the loop handling 
+        // For both INVAL and SYNC commands, the CONFIG FSM contains the loop handling
         //
         // all cache lines covered by the buffer. The various lines of a given buffer
         // can be pipelined: the CONFIG FSM does not wait the response for line (n) to send
-        // the command for line (n+1). It decrements the r_config_cmd_lines counter until 
+        // the command for line (n+1). It decrements the r_config_cmd_lines counter until
         // the last request has been registered in TRT (for a SYNC), or in IVT (for an INVAL).
         // The r_config_rsp_lines counter contains the number of expected responses from
@@ -2180,8 +2180,8 @@
         // be concurently accessed by those three FSMs, it is implemented as an [incr/decr]
         // counter.
-        // 
+        //
         // - INVAL request:
-        //   For each line, it access to the DIR. 
-        //   In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. 
+        //   For each line, it access to the DIR.
+        //   In case of miss, it does nothing, and a response is requested to TGT_RSP FSM.
         //   In case of hit, with no copies in L1 caches, the line is invalidated and
         //   a response is requested to TGT_RSP FSM.
@@ -2195,8 +2195,8 @@
         //   This constraint can be released, but it requires to make 2 PUT transactions
         //   for the first and the last line...
-        // 
+        //
         // - SYNC request:
-        //   For each line, it access to the DIR. 
-        //   In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. 
+        //   For each line, it access to the DIR.
+        //   In case of miss, it does nothing, and a response is requested to TGT_RSP FSM.
         //   In case of hit, a PUT transaction is registered in TRT and a request is sent
         //   to IXR_CMD FSM. The IXR_RSP FSM decrements the r_config_rsp_lines counter
@@ -2205,5 +2205,5 @@
         //
         // From the software point of view, a configuration request is a sequence
-        // of 6 atomic accesses in an uncached segment. A dedicated lock is used 
+        // of 6 atomic accesses in an uncached segment. A dedicated lock is used
         // to handle only one configuration command at a given time:
         // - Read  MEMC_LOCK       : Get the lock
@@ -2218,7 +2218,7 @@
         {
             /////////////////
-            case CONFIG_IDLE:  // waiting a config request 
-                {
-                    if ( r_config_cmd.read() != MEMC_CMD_NOP )  
+            case CONFIG_IDLE:  // waiting a config request
+                {
+                    if ( r_config_cmd.read() != MEMC_CMD_NOP )
                     {
                         r_config_fsm    = CONFIG_LOOP;
@@ -2226,5 +2226,5 @@
 #if DEBUG_MEMC_CONFIG
                         if(m_debug)
-                            std::cout << "  <MEMC " << name() << " CONFIG_IDLE> Config Request received" 
+                            std::cout << "  <MEMC " << name() << " CONFIG_IDLE> Config Request received"
                                 << " address = " << std::hex << r_config_address.read()
                                 << " / nlines = " << std::dec << r_config_cmd_lines.read()
@@ -2235,5 +2235,5 @@
                 }
                 /////////////////
-            case CONFIG_LOOP:   // test last line to be handled 
+            case CONFIG_LOOP:   // test last line to be handled
                 {
                     if ( r_config_cmd_lines.read() == 0 )
@@ -2249,7 +2249,7 @@
 #if DEBUG_MEMC_CONFIG
                     if(m_debug)
-                        std::cout << "  <MEMC " << name() << " CONFIG_LOOP>" 
-                            << " address = " << std::hex << r_config_address.read()    
-                            << " / nlines = " << std::dec << r_config_cmd_lines.read() 
+                        std::cout << "  <MEMC " << name() << " CONFIG_LOOP>"
+                            << " address = " << std::hex << r_config_address.read()
+                            << " / nlines = " << std::dec << r_config_cmd_lines.read()
                             << " / command = " << r_config_cmd.read() << std::endl;
 #endif
@@ -2257,5 +2257,5 @@
                 }
                 /////////////////
-            case CONFIG_WAIT:   // wait completion (last response) 
+            case CONFIG_WAIT:   // wait completion (last response)
                 {
                     if ( r_config_rsp_lines.read() == 0 )  // last response received
@@ -2266,5 +2266,5 @@
 #if DEBUG_MEMC_CONFIG
                     if(m_debug)
-                        std::cout << "  <MEMC " << name() << " CONFIG_WAIT>" 
+                        std::cout << "  <MEMC " << name() << " CONFIG_WAIT>"
                             << " / lines to do = " << std::dec << r_config_rsp_lines.read() << std::endl;
 #endif
@@ -2272,5 +2272,5 @@
                 }
                 ////////////////
-            case CONFIG_RSP:  // request TGT_RSP FSM to return response 
+            case CONFIG_RSP:  // request TGT_RSP FSM to return response
                 {
                     if ( not r_config_to_tgt_rsp_req.read() )
@@ -2329,5 +2329,5 @@
 
                     if (entry.valid and                            // hit & inval command
-                            (r_config_cmd.read() == MEMC_CMD_INVAL)) 
+                            (r_config_cmd.read() == MEMC_CMD_INVAL))
                     {
                         r_config_fsm    = CONFIG_IVT_LOCK;
@@ -2336,8 +2336,8 @@
                             entry.dirty and
                             (r_config_cmd.read() == MEMC_CMD_SYNC) )
-                    { 
+                    {
                         r_config_fsm = CONFIG_TRT_LOCK;
                     }
-                    else                                            // return to LOOP 
+                    else                                            // return to LOOP
                     {
                         r_config_cmd_lines = r_config_cmd_lines.read() - 1;
@@ -2359,5 +2359,5 @@
                 /////////////////////
             case CONFIG_TRT_LOCK:      // enter this state in case of SYNC command
-                // to a dirty cache line 
+                // to a dirty cache line
                 // keep DIR lock, and try to get TRT lock
                 // return to LOOP state if TRT full
@@ -2423,5 +2423,5 @@
                     std::vector<data_t> data_vector;
                     data_vector.clear();
-                    for(size_t word=0; word<m_words; word++) 
+                    for(size_t word=0; word<m_words; word++)
                     {
                         uint32_t data = m_cache_data.read( way, set, word );
@@ -2439,5 +2439,5 @@
                             0,                                   // read_length: unused
                             0,                                   // word_index:  unused
-                            std::vector<be_t>(m_words,0xF),      // byte-enable:     unused 
+                            std::vector<be_t>(m_words,0xF),      // byte-enable:     unused
                             data_vector,                         // data to be written
                             0,                                   // ll_key:          unused
@@ -2470,5 +2470,5 @@
                         if(m_debug)
                             std::cout << "  <MEMC " << name() << " CONFIG_PUT_REQ> post PUT request to IXR_CMD_FSM"
-                                << " / address = " << std::hex << r_config_address.read() << std::endl; 
+                                << " / address = " << std::hex << r_config_address.read() << std::endl;
 #endif
                     }
@@ -2480,5 +2480,5 @@
                 // Return to LOOP state if IVT full.
                 // Register inval in IVT, and invalidate the
-                // directory if IVT not full. 
+                // directory if IVT not full.
                 {
                     assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and
@@ -2515,5 +2515,5 @@
 
                             wok = m_ivt.set(false,       // it's an inval transaction
-                                    broadcast,   
+                                    broadcast,
                                     false,       // no response required
                                     true,        // acknowledge required
@@ -2558,5 +2558,5 @@
             case CONFIG_BC_SEND:    // Post a broadcast inval request to CC_SEND FSM
                 {
-                    if( not r_config_to_cc_send_multi_req.read() and 
+                    if( not r_config_to_cc_send_multi_req.read() and
                             not r_config_to_cc_send_brdcast_req.read() )
                     {
@@ -2575,5 +2575,5 @@
                         if(m_debug)
                             std::cout << "  <MEMC " << name() << " CONFIG_BC_SEND>"
-                                << " Post a broadcast inval request to CC_SEND FSM" 
+                                << " Post a broadcast inval request to CC_SEND FSM"
                                 << " / address = " << r_config_address.read() <<std::endl;
 #endif
@@ -2584,5 +2584,5 @@
             case CONFIG_INVAL_SEND:    // Post a multi inval request to CC_SEND FSM
                 {
-                    if( not r_config_to_cc_send_multi_req.read() and 
+                    if( not r_config_to_cc_send_multi_req.read() and
                             not r_config_to_cc_send_brdcast_req.read() )
                     {
@@ -2612,7 +2612,7 @@
                         if(m_debug)
                             std::cout << "  <MEMC " << name() << " CONFIG_INVAL_SEND>"
-                                << " Post multi inval request to CC_SEND FSM" 
-                                << " / address = " << std::hex << r_config_address.read() 
-                                << " / copy = " << r_config_dir_copy_srcid.read() 
+                                << " Post multi inval request to CC_SEND FSM"
+                                << " / address = " << std::hex << r_config_address.read()
+                                << " / copy = " << r_config_dir_copy_srcid.read()
                                 << " / inst = " << std::dec << r_config_dir_copy_inst.read() << std::endl;
 #endif
@@ -2640,5 +2640,5 @@
                 {
                     HeapEntry entry = m_heap.read( r_config_heap_next.read() );
-                    bool last_copy  = (entry.next == r_config_heap_next.read()); 
+                    bool last_copy  = (entry.next == r_config_heap_next.read());
 
                     config_to_cc_send_fifo_srcid = entry.owner.srcid;
@@ -2660,7 +2660,7 @@
                     if(m_debug)
                         std::cout << "  <MEMC " << name() << " CONFIG_HEAP_SCAN>"
-                            << " Post multi inval request to CC_SEND FSM" 
-                            << " / address = " << std::hex << r_config_address.read() 
-                            << " / copy = " << entry.owner.srcid 
+                            << " Post multi inval request to CC_SEND FSM"
+                            << " / address = " << std::hex << r_config_address.read()
+                            << " / copy = " << entry.owner.srcid
                             << " / inst = " << std::dec << entry.owner.inst << std::endl;
 #endif
@@ -2681,5 +2681,5 @@
                     }
                     else
-                    { 
+                    {
                         last_entry.next = free_pointer;
                     }
@@ -2799,5 +2799,5 @@
 
                         // hit on a WT line or the owner has no more copy (if LL, the owner must be invalidated even if he made the request)
-                        if (entry.cache_coherent or (entry.count == 0))// or (entry.owner.srcid == m_cmd_read_srcid_fifo.read())) 
+                        if (entry.cache_coherent or (entry.count == 0))// or (entry.owner.srcid == m_cmd_read_srcid_fifo.read()))
                         {
                             // test if we need to register a new copy in the heap
@@ -2851,5 +2851,5 @@
                             {
                                 std::cout
-                                    << "  <MEMC " << name() << " READ_IVT_LOCK>" 
+                                    << "  <MEMC " << name() << " READ_IVT_LOCK>"
                                     << " Wait cleanup completion"
                                     << std::endl;
@@ -2862,9 +2862,9 @@
                             r_read_to_cc_send_dest = r_read_copy.read();
                             r_read_to_cc_send_nline = nline;
-                            r_read_to_cc_send_inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); 
+                            r_read_to_cc_send_inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0);
                             r_read_to_cleanup_req = true;
                             r_read_to_cleanup_nline = nline;
                             r_read_to_cleanup_srcid = m_cmd_read_srcid_fifo.read();
-                            r_read_to_cleanup_inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); 
+                            r_read_to_cleanup_inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0);
                             r_read_to_cleanup_length  = m_cmd_read_length_fifo.read();
                             r_read_to_cleanup_first_word = m_x[(addr_t) m_cmd_read_addr_fifo.read()];
@@ -2920,5 +2920,5 @@
                     break;
                 }
-                ///////////////////                      
+                ///////////////////
             case READ_DIR_HIT:    //  read data in cache & update the directory
                 //  we enter this state in 3 cases:
@@ -3024,9 +3024,5 @@
                         bool go_cnt = (r_read_count.read() >= m_max_copies) or m_heap.is_full();
 
-                        if (!r_read_coherent.read())
-                        {
-                            std::cout << "Address = " << std::hex << (m_cmd_read_addr_fifo.read()) << std::dec << " |count = " << r_read_count.read() << std::endl;
-                        }
-                        assert (r_read_coherent.read() && "accÃšs au heap sur ncc");
+                        assert (r_read_coherent.read() && "Heap access on line NCC");
                         // read data in the cache
                         size_t set = m_y[(addr_t)(m_cmd_read_addr_fifo.read())];
@@ -3135,5 +3131,5 @@
                             m_heap.set_full();
                         }
-                        
+
                         // <Activity counters>
                         m_cpt_heap_slot_available--;
@@ -3418,6 +3414,6 @@
                             << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read()
                             << " / address = " << std::hex << m_cmd_write_addr_fifo.read()
-                            << " / data = " << m_cmd_write_data_fifo.read() 
-                            << " / pktid = " << m_cmd_write_pktid_fifo.read() 
+                            << " / data = " << m_cmd_write_data_fifo.read()
+                            << " / pktid = " << m_cmd_write_pktid_fifo.read()
                             << std::endl;
 #endif
@@ -3431,5 +3427,5 @@
 
                     // check that the next word is in the same cache line
-                    assert((m_nline[(addr_t)(r_write_address.read())] == 
+                    assert((m_nline[(addr_t)(r_write_address.read())] ==
                                 m_nline[(addr_t)(m_cmd_write_addr_fifo.read())]) &&
                             "MEMC ERROR in WRITE_NEXT state: Illegal write burst");
@@ -3482,5 +3478,5 @@
                         // test address and key match of the SC command on the
                         // LL/SC table without removing reservation. The reservation
-                        // will be erased after in this FSM. 
+                        // will be erased after in this FSM.
                         bool sc_success = m_llsc_table.check(r_write_address.read(),
                                 r_write_sc_key.read());
@@ -3493,5 +3489,5 @@
                     else
                     {
-                        // write burst 
+                        // write burst
 #define L2 soclib::common::uint32_log2
                         addr_t min = r_write_address.read();
@@ -3594,5 +3590,5 @@
                         addr_t nline = m_nline[(addr_t)(r_write_address.read())];
 
-                        //if there is a matched updt req, we should wait until it is over. Because 
+                        //if there is a matched updt req, we should wait until it is over. Because
                         //we need the lastest updt data.
                         match_inval = m_ivt.search_inval(nline, index);
@@ -3600,5 +3596,5 @@
                         assert ((r_write_count.read() == 1) and "NCC to CC req without copy");
 
-                        if( not match_inval                          and 
+                        if( not match_inval                          and
                             not m_ivt.is_full()                      and
                             not r_write_to_cc_send_req.read()        and
@@ -3676,5 +3672,5 @@
                     // no_update is true when there is no need for coherence transaction
                     bool no_update = ( (r_write_count.read() == 0) or
-                            (owner and (r_write_count.read() == 1) and 
+                            (owner and (r_write_count.read() == 1) and
                              ((r_write_pktid.read() & 0x7) != TYPE_SC)));
 
@@ -3682,5 +3678,5 @@
                     if(no_update)
                     {
-                        // SC command but zero copies 
+                        // SC command but zero copies
                         if ((r_write_pktid.read() & 0x7) == TYPE_SC)
                         {
@@ -3726,5 +3722,5 @@
                         if(no_update)
                         {
-                            std::cout << "  <MEMC " << name() 
+                            std::cout << "  <MEMC " << name()
                                 << " WRITE_DIR_HIT> Write into cache / No coherence transaction"
                                 << std::endl;
@@ -3761,5 +3757,5 @@
                                 true,  // response required
                                 false, // no acknowledge required
-                                srcid,    
+                                srcid,
                                 trdid,
                                 pktid,
@@ -3792,5 +3788,5 @@
                             if(wok)
                             {
-                                std::cout << "  <MEMC " << name() 
+                                std::cout << "  <MEMC " << name()
                                     << " WRITE_UPT_LOCK> Register the multicast update in UPT / "
                                     << " nb_copies = " << r_write_count.read() << std::endl;
@@ -3814,5 +3810,5 @@
 #if DEBUG_MEMC_WRITE
                         if(m_debug)
-                            std::cout << "  <MEMC " << name() 
+                            std::cout << "  <MEMC " << name()
                                 << " WRITE_UPT_HEAP_LOCK> Get acces to the HEAP" << std::endl;
 #endif
@@ -3906,5 +3902,5 @@
 
                     // put the next srcid in the fifo
-                    if ((entry.owner.srcid != r_write_srcid.read()) or 
+                    if ((entry.owner.srcid != r_write_srcid.read()) or
                             ((r_write_pktid.read() & 0x7) == TYPE_SC)    or
                             entry.owner.inst)
@@ -4026,5 +4022,5 @@
 
                                 r_write_sc_key = m_cmd_write_data_fifo.read();
-                            } 
+                            }
 
                             // initialize the be field for all words
@@ -4049,6 +4045,6 @@
                         {
                             std::cout << "  <MEMC " << name() << " WRITE_RSP> Post a request to TGT_RSP FSM"
-                                << " : rsrcid = " << std::hex << r_write_srcid.read() 
-                                << " : rpktid = " << std::hex << r_write_pktid.read() 
+                                << " : rsrcid = " << std::hex << r_write_srcid.read()
+                                << " : rpktid = " << std::hex << r_write_pktid.read()
                                 << " : sc_fail= " << std::hex << r_write_sc_fail.read()
                                 << std::endl;
@@ -4058,6 +4054,6 @@
                                     << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read()
                                     << " / address = " << m_cmd_write_addr_fifo.read()
-                                    << " / data = " << m_cmd_write_data_fifo.read() 
-                                    << " / pktid = " << m_cmd_write_pktid_fifo.read() 
+                                    << " / data = " << m_cmd_write_data_fifo.read()
+                                    << " / pktid = " << m_cmd_write_pktid_fifo.read()
                                     << std::endl;
                             }
@@ -4068,5 +4064,5 @@
                 }
                 ///////////////////////// RWT
-            case WRITE_MISS_IVT_LOCK: 
+            case WRITE_MISS_IVT_LOCK:
                 {
                     if (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE)
@@ -4224,5 +4220,5 @@
 #if DEBUG_MEMC_WRITE
                         if(m_debug)
-                            std::cout << "  <MEMC " << name() 
+                            std::cout << "  <MEMC " << name()
                                 << " WRITE_MISS_XRAM_REQ> Post a GET request to the"
                                 << " IXR_CMD FSM" << std::endl;
@@ -4282,5 +4278,5 @@
 #if DEBUG_MEMC_WRITE
                         if(m_debug)
-                            std::cout 
+                            std::cout
                                 << "  <MEMC "  << name()
                                 << " WRITE_BC_TRT_LOCK> Complete data buffer" << std::endl;
@@ -4476,5 +4472,5 @@
         //
         // - It sends a single flit VCI read to the XRAM in case of
-        //   GET request posted by the READ, WRITE or CAS FSMs. 
+        //   GET request posted by the READ, WRITE or CAS FSMs.
         // - It sends a multi-flit VCI write in case of PUT request posted by
         //   the XRAM_RSP, WRITE, CAS, or CONFIG FSMs.
@@ -4535,5 +4531,5 @@
                 else if(r_config_to_ixr_cmd_req.read())     r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT;
                 else if(r_cleanup_to_ixr_cmd_req)           r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT;
-                break;      
+                break;
                 /////////////////////////
             case IXR_CMD_CONFIG_IDLE:
@@ -4597,5 +4593,5 @@
                 }
                 /////////////////////
-            case IXR_CMD_CAS_TRT:       // access TRT for a PUT or a GET 
+            case IXR_CMD_CAS_TRT:       // access TRT for a PUT or a GET
                 {
                     if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD )
@@ -4624,5 +4620,5 @@
                 }
                 //////////////////////
-            case IXR_CMD_XRAM_TRT:       // access TRT for a PUT 
+            case IXR_CMD_XRAM_TRT:       // access TRT for a PUT
                 {
                     if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD )
@@ -4646,5 +4642,5 @@
                 }
                 //////////////////////
-            case IXR_CMD_CLEANUP_TRT:       // access TRT for a PUT 
+            case IXR_CMD_CLEANUP_TRT:       // access TRT for a PUT
                 {
                     if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD )
@@ -4866,5 +4862,5 @@
         // The FSM takes the lock protecting the TRT, and the corresponding
         // entry is erased. If an acknowledge was required (in case of software SYNC)
-        // the r_config_rsp_lines counter is decremented.  
+        // the r_config_rsp_lines counter is decremented.
         //
         // - A response to a GET request is a multi-cell VCI packet.
@@ -4873,5 +4869,5 @@
         // The FSM takes the lock protecting the TRT to store the line in the TRT
         // (taking into account the write requests already stored in the TRT).
-        // When the line is completely written, the r_ixr_rsp_to_xram_rsp_rok[index]  
+        // When the line is completely written, the r_ixr_rsp_to_xram_rsp_rok[index]
         // signal is set to inform the XRAM_RSP FSM.
         ///////////////////////////////////////////////////////////////////////////////
@@ -4902,6 +4898,6 @@
                                     << " IXR_RSP_IDLE> Response from XRAM to a get transaction" << std::endl;
 #endif
-                        }     
-                    } 
+                        }
+                    }
                     break;
                 }
@@ -4919,5 +4915,5 @@
                     if(r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP)
                     {
-                        size_t  index = r_ixr_rsp_trt_index.read(); 
+                        size_t  index = r_ixr_rsp_trt_index.read();
                         if (m_trt.is_config(index))     // it's a config transaction
                         {
@@ -4977,5 +4973,5 @@
         // The cache line has been written in the TRT by the IXR_CMD_FSM.
         // As the IXR_RSP FSM and the XRAM_RSP FSM are running in parallel,
-        // there is as many flip-flops r_ixr_rsp_to_xram_rsp_rok[i] as the number 
+        // there is as many flip-flops r_ixr_rsp_to_xram_rsp_rok[i] as the number
         // of entries in the TRT, that are handled with a round-robin priority...
         //
@@ -5018,5 +5014,5 @@
                             break;
                         }
-                    } 
+                    }
                     break;
                 }
@@ -5074,9 +5070,9 @@
                     r_xram_rsp_victim_inval     = inval ;
                     // a NCC line is by default considered as dirty in the L1: we must take a reservation on a TRT entry
-                    r_xram_rsp_victim_dirty     = victim.dirty or (!victim.cache_coherent && (victim.count == 1)); 
+                    r_xram_rsp_victim_dirty     = victim.dirty or (!victim.cache_coherent && (victim.count == 1));
 
 
                     // A line that undergoes a change in its state (ncc to cc), should not be evicted from the memory cache.
-                    if((victim.tag * m_sets + set) == r_read_to_cleanup_nline.read() and r_read_to_cleanup_req.read()) 
+                    if((victim.tag * m_sets + set) == r_read_to_cleanup_nline.read() and r_read_to_cleanup_req.read())
                     {
                         r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
@@ -5090,9 +5086,9 @@
 #endif
                     }
-                    else if( not r_xram_rsp_trt_buf.rerror ) 
+                    else if( not r_xram_rsp_trt_buf.rerror )
                     {
                         r_xram_rsp_fsm = XRAM_RSP_IVT_LOCK;
                     }
-                    else 
+                    else
                     {
                         r_xram_rsp_fsm = XRAM_RSP_ERROR_ERASE;
@@ -5111,5 +5107,5 @@
                 }
                 ///////////////////////
-            case XRAM_RSP_IVT_LOCK:   // Keep DIR and TRT locks and take the IVT lock 
+            case XRAM_RSP_IVT_LOCK:   // Keep DIR and TRT locks and take the IVT lock
                 // to check a possible pending inval
                 {
@@ -5241,6 +5237,6 @@
                         bool   wok = m_ivt.set(false,      // it's an inval transaction
                                 broadcast,  // set broadcast bit
-                                false,      // no response required 
-                                false,      // no acknowledge required 
+                                false,      // no response required
+                                false,      // no acknowledge required
                                 0,          // srcid
                                 0,          // trdid
@@ -5252,5 +5248,5 @@
                         r_xram_rsp_ivt_index = index;
                         assert( wok and
-                                "MEMC ERROR in XRAM_RSP_DIR_UPDT state: IVT should not be full"); 
+                                "MEMC ERROR in XRAM_RSP_DIR_UPDT state: IVT should not be full");
 
                     }
@@ -5313,5 +5309,5 @@
                                 0,                                 // unused
                                 0,                                 // unused
-                                std::vector<be_t>(m_words,0xF),                         
+                                std::vector<be_t>(m_words,0xF),
                                 data_vector);
 #if DEBUG_MEMC_XRAM_RSP
@@ -5411,5 +5407,5 @@
                         m_cpt_write_dirty++;
 
-                        bool multi_req = not r_xram_rsp_victim_is_cnt.read() and 
+                        bool multi_req = not r_xram_rsp_victim_is_cnt.read() and
                             r_xram_rsp_victim_inval.read();
                         bool not_last_multi_req = multi_req and (r_xram_rsp_victim_count.read() != 1);
@@ -5540,5 +5536,5 @@
                         // acknowledged before signaling another one.
                         // Therefore, when there is an active error, and other
-                        // errors arrive, these are not considered 
+                        // errors arrive, these are not considered
 
                         if (!r_xram_rsp_rerror_irq.read() && r_xram_rsp_rerror_irq_enable.read()
@@ -5639,5 +5635,5 @@
                     r_cleanup_inst  = (type == DspinRwtParam::TYPE_CLEANUP_INST);
                     r_cleanup_srcid = srcid;
-                    r_cleanup_ncc = 
+                    r_cleanup_ncc =
                         DspinRwtParam::dspin_get(
                                 flit,
@@ -5738,5 +5734,5 @@
                         uint64_t flit = m_cc_receive_to_cleanup_fifo.read();
 
-                        uint32_t data = 
+                        uint32_t data =
                             DspinRwtParam::dspin_get (flit, DspinRwtParam::CLEANUP_DATA_UPDT);
 
@@ -5809,5 +5805,5 @@
                     //RWT
                     size_t set = m_y[(addr_t)(cleanup_address)];
-                    m_cache_data.read_line(way, set, r_cleanup_old_data); 
+                    m_cache_data.read_line(way, set, r_cleanup_old_data);
                     r_cleanup_coherent = entry.cache_coherent;
 
@@ -5911,5 +5907,5 @@
                     entry.lock           = r_cleanup_lock.read();
                     entry.ptr            = r_cleanup_ptr.read();
-                    if (r_read_to_cleanup_req.read() and (r_cleanup_nline.read() == r_read_to_cleanup_nline.read())) //pending READ 
+                    if (r_read_to_cleanup_req.read() and (r_cleanup_nline.read() == r_read_to_cleanup_nline.read())) //pending READ
                     {
                         if (r_read_to_cleanup_cached_read.read())
@@ -5937,5 +5933,5 @@
 
 #if REVERT_CC_MECANISM
-                        // Revert CC to NCC if : 
+                        // Revert CC to NCC if :
                         //  - no more copy in L1 caches
                         //  - this line is not in counter mode (broadcast)
@@ -5948,5 +5944,5 @@
 
 #if REVERT_BC_MECANISM
-                        if ((r_cleanup_count.read() - 1) == 0) 
+                        if ((r_cleanup_count.read() - 1) == 0)
                         {
                             entry.is_cnt = false;
@@ -6082,5 +6078,5 @@
                         {
                             r_cleanup_to_tgt_rsp_data[i] = r_cleanup_old_data[i].read();
-                        }        
+                        }
                     }
 
@@ -6354,5 +6350,5 @@
                 //////////////////////
             case CLEANUP_IVT_LOCK:   // get the lock protecting the IVT to search a pending
-                // invalidate transaction matching the cleanup 
+                // invalidate transaction matching the cleanup
                 {
                     if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) break;
@@ -6432,5 +6428,5 @@
                 }
                 ///////////////////////
-            case CLEANUP_IVT_CLEAR:    // Clear IVT entry 
+            case CLEANUP_IVT_CLEAR:    // Clear IVT entry
                 {
                     assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP) and
@@ -6473,5 +6469,5 @@
                     r_cleanup_to_tgt_rsp_trdid   = r_cleanup_write_trdid.read();
                     r_cleanup_to_tgt_rsp_pktid   = r_cleanup_write_pktid.read();
-                    r_cleanup_to_tgt_rsp_type    = true; 
+                    r_cleanup_to_tgt_rsp_type    = true;
 
                     if (r_cleanup_ncc.read() )
@@ -6503,5 +6499,5 @@
                         {
                             size_t index = 0;
-                            bool   hit   = m_trt.hit_write(r_cleanup_nline.read(), &index); 
+                            bool   hit   = m_trt.hit_write(r_cleanup_nline.read(), &index);
 
                             assert (hit and "CLEANUP_IXR_REQ found no matching entry in TRT");
@@ -6510,5 +6506,5 @@
 
                             if (r_cleanup_contains_data.read())
-                            {  
+                            {
                                 std::vector<data_t> data_vector;
                                 data_vector.clear();
@@ -6587,5 +6583,5 @@
                             << " nline = "   << std::hex << r_cleanup_nline.read()
                             << " / way = "   << std::dec << r_cleanup_way.read()
-                            << " / srcid = " << std::dec << r_cleanup_srcid.read() 
+                            << " / srcid = " << std::dec << r_cleanup_srcid.read()
                             << std::endl;
 #endif
@@ -6805,5 +6801,5 @@
                             if(m_debug)
                                 std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_WRITE>"
-                                    << " Broacast Inval required" 
+                                    << " Broacast Inval required"
                                     << " / copies = " << r_cas_count.read() << std::endl;
 #endif
@@ -6817,5 +6813,5 @@
                             if(m_debug)
                                 std::cout << "  <MEMC " << name() << " CAS_DIR_HIT_WRITE>"
-                                    << " Multi Inval required" 
+                                    << " Multi Inval required"
                                     << " / copies = " << r_cas_count.read() << std::endl;
 #endif
@@ -6874,5 +6870,5 @@
                         wok = m_upt.set(true,    // it's an update transaction
                                 false,   // it's not a broadcast
-                                true,    // response required  
+                                true,    // response required
                                 false,   // no acknowledge required
                                 srcid,
@@ -7137,5 +7133,5 @@
                     {
                         if(i == word)                                        // first modified word
-                            data_vector.push_back( r_cas_wdata.read() );     
+                            data_vector.push_back( r_cas_wdata.read() );
                         else if((i == word+1) and (r_cas_cpt.read() == 4))   // second modified word
                             data_vector.push_back( m_cmd_cas_wdata_fifo.read() );
@@ -7144,5 +7140,5 @@
                     }
                     m_trt.set( r_cas_trt_index.read(),
-                            false,    // PUT request 
+                            false,    // PUT request
                             m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())],
                             0,
@@ -7364,5 +7360,5 @@
         //
         // It implements a round-robin priority between the four possible client FSMs
-        //     XRAM_RSP > CAS > READ > WRITE > CONFIG 
+        //     XRAM_RSP > CAS > READ > WRITE > CONFIG
         //
         // Each FSM can request the next services:
@@ -7375,5 +7371,5 @@
         // - r_config_to_cc_send_multi_req : multi-inval
         //   r_config_to_cc_send_brdcast_req : broadcast-inval
-        //   
+        //
         // An inval request is a double DSPIN flit command containing:
         // 1. the index of the line to be invalidated.
@@ -7517,5 +7513,5 @@
                 }
                 ///////////////////////////
-            case CC_SEND_READ_IDLE: 
+            case CC_SEND_READ_IDLE:
                 {
                     // WRITE
@@ -8264,5 +8260,5 @@
                     }
                     else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK;
-                    else if(r_cleanup_to_tgt_rsp_req) 
+                    else if(r_cleanup_to_tgt_rsp_req)
                     {
                         r_tgt_rsp_fsm = TGT_RSP_CLEANUP;
@@ -8809,5 +8805,5 @@
         // - The XRAM_RSP FSM initiates broadcast/multicast invalidate transaction and sets
         //   a new entry in the IVT
-        // - The CONFIG FSM does the same thing as the XRAM_RSP FSM 
+        // - The CONFIG FSM does the same thing as the XRAM_RSP FSM
         // - The CLEANUP FSM complete those trasactions and erase the IVT entry.
         // The resource is always allocated.
@@ -8844,5 +8840,5 @@
                 //////////////////////////
             case ALLOC_IVT_READ:            // allocated to READ FSM
-                if (r_read_fsm.read() != READ_IVT_LOCK) 
+                if (r_read_fsm.read() != READ_IVT_LOCK)
                 {
                     if (r_xram_rsp_fsm.read() == XRAM_RSP_IVT_LOCK)
@@ -9231,5 +9227,5 @@
                         r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
 
-                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 
+                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK )
                         r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
 
@@ -9268,5 +9264,5 @@
                         r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
 
-                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 
+                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK )
                         r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
 
@@ -9304,5 +9300,5 @@
                         r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
 
-                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 
+                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK )
                         r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
 
@@ -9338,5 +9334,5 @@
                         r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
 
-                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 
+                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK )
                         r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
 
@@ -9369,5 +9365,5 @@
                         r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
 
-                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 
+                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK )
                         r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
 
@@ -9404,5 +9400,5 @@
                         (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ))
                 {
-                    if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 
+                    if( r_config_fsm.read() == CONFIG_TRT_LOCK )
                         r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
 
@@ -9506,5 +9502,5 @@
                         r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP;
 
-                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) 
+                    else if( r_config_fsm.read() == CONFIG_TRT_LOCK )
                         r_alloc_trt_fsm = ALLOC_TRT_CONFIG;
                 }
@@ -9698,13 +9694,13 @@
         /////////////////////////////////////////////////////////////////////
 
-        m_cmd_read_addr_fifo.update(   cmd_read_fifo_get, cmd_read_fifo_put, 
+        m_cmd_read_addr_fifo.update(   cmd_read_fifo_get, cmd_read_fifo_put,
                 p_vci_tgt.address.read() );
-        m_cmd_read_length_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, 
+        m_cmd_read_length_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put,
                 p_vci_tgt.plen.read()>>2 );
-        m_cmd_read_srcid_fifo.update(  cmd_read_fifo_get, cmd_read_fifo_put, 
+        m_cmd_read_srcid_fifo.update(  cmd_read_fifo_get, cmd_read_fifo_put,
                 p_vci_tgt.srcid.read() );
-        m_cmd_read_trdid_fifo.update(  cmd_read_fifo_get, cmd_read_fifo_put, 
+        m_cmd_read_trdid_fifo.update(  cmd_read_fifo_get, cmd_read_fifo_put,
                 p_vci_tgt.trdid.read() );
-        m_cmd_read_pktid_fifo.update(  cmd_read_fifo_get, cmd_read_fifo_put, 
+        m_cmd_read_pktid_fifo.update(  cmd_read_fifo_get, cmd_read_fifo_put,
                 p_vci_tgt.pktid.read() );
 
@@ -9773,5 +9769,5 @@
 
         m_cc_receive_to_multi_ack_fifo.update( cc_receive_to_multi_ack_fifo_get,
-                cc_receive_to_multi_ack_fifo_put, 
+                cc_receive_to_multi_ack_fifo_put,
                 p_dspin_p2m.data.read() );
 
@@ -9817,10 +9813,10 @@
         // The three sources of (increment / decrement) are CONFIG / CLEANUP / IXR_RSP FSMs
         ////////////////////////////////////////////////////////////////////////////////////
-        if ( config_rsp_lines_incr and not 
+        if ( config_rsp_lines_incr and not
              (config_rsp_lines_cleanup_decr or config_rsp_lines_ixr_rsp_decr) )
         {
             r_config_rsp_lines = r_config_rsp_lines.read() + 1;
         }
-        if ( not config_rsp_lines_incr and  
+        if ( not config_rsp_lines_incr and
              (config_rsp_lines_cleanup_decr or config_rsp_lines_ixr_rsp_decr) )
         {
@@ -9830,5 +9826,5 @@
         ////////////////////////////////////////////////////////////////////////////////////
         //            Update min m_cpt_heap_min_slot_available.
-        // The four sources of (increment / decrement) are READ / CLEANUP / XRAM_RSP / CONFIG FSMs 
+        // The four sources of (increment / decrement) are READ / CLEANUP / XRAM_RSP / CONFIG FSMs
         ////////////////////////////////////////////////////////////////////////////////////
         assert((m_cpt_heap_slot_available <= m_heap_size) and "m_cpt_heap_slot_available > m_heap_size");
@@ -9868,11 +9864,11 @@
         // DATA width is 8 bytes
         // The following values are not transmitted to XRAM
-        //   p_vci_ixr.be 
-        //   p_vci_ixr.pktid  
-        //   p_vci_ixr.cons 
-        //   p_vci_ixr.wrap 
-        //   p_vci_ixr.contig 
-        //   p_vci_ixr.clen 
-        //   p_vci_ixr.cfixed 
+        //   p_vci_ixr.be
+        //   p_vci_ixr.pktid
+        //   p_vci_ixr.cons
+        //   p_vci_ixr.wrap
+        //   p_vci_ixr.contig
+        //   p_vci_ixr.clen
+        //   p_vci_ixr.cfixed
 
         p_vci_ixr.plen    = 64;
@@ -9880,5 +9876,5 @@
         p_vci_ixr.trdid   = r_ixr_cmd_trdid.read();
         p_vci_ixr.address = (addr_t)r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2);
-        p_vci_ixr.be      = 0xFF; 
+        p_vci_ixr.be      = 0xFF;
         p_vci_ixr.pktid   = 0;
         p_vci_ixr.cons    = false;
@@ -9916,5 +9912,5 @@
             p_vci_ixr.cmdval  = true;
             p_vci_ixr.address = (addr_t)r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2);
-            p_vci_ixr.wdata   = ((wide_data_t)(r_ixr_cmd_wdata[r_ixr_cmd_word.read()].read()) | 
+            p_vci_ixr.wdata   = ((wide_data_t)(r_ixr_cmd_wdata[r_ixr_cmd_word.read()].read()) |
                     ((wide_data_t)(r_ixr_cmd_wdata[r_ixr_cmd_word.read() + 1].read()) << 32));
             p_vci_ixr.trdid   = r_cleanup_to_ixr_cmd_index.read();
@@ -9933,5 +9929,5 @@
         if( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ) or
                 (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) )
-        { 
+        {
             p_vci_ixr.rspack = (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP);
         }
@@ -10109,10 +10105,10 @@
                     p_vci_tgt.rspval  = true;
 
-                    if( is_ll and not r_tgt_rsp_key_sent.read() ) 
+                    if( is_ll and not r_tgt_rsp_key_sent.read() )
                     {
                         // LL response first flit
                         p_vci_tgt.rdata = r_xram_rsp_to_tgt_rsp_ll_key.read();
                     }
-                    else 
+                    else
                     {
                         // LL response second flit or READ response
@@ -10275,5 +10271,5 @@
                             m_broadcast_boundaries,
                             DspinRwtParam::BROADCAST_BOX);
-                    
+
                     DspinRwtParam::dspin_set( flit,
                             1,
