Index: branches/RWT/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h =================================================================== --- branches/RWT/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h (revision 787) +++ branches/RWT/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h (revision 814) @@ -1,4 +1,4 @@ #ifndef SOCLIB_CABA_MEM_CACHE_DIRECTORY_H -#define SOCLIB_CABA_MEM_CACHE_DIRECTORY_H +#define SOCLIB_CABA_MEM_CACHE_DIRECTORY_H #include @@ -14,5 +14,5 @@ //////////////////////////////////////////////////////////////////////// - // A LRU entry + // A LRU entry //////////////////////////////////////////////////////////////////////// class LruEntry { @@ -20,5 +20,5 @@ public: - bool recent; + bool recent; void init() @@ -33,5 +33,5 @@ //////////////////////////////////////////////////////////////////////// class Owner{ - + public: // Fields @@ -66,5 +66,5 @@ //////////////////////////////////////////////////////////////////////// - // A directory entry + // A directory entry //////////////////////////////////////////////////////////////////////// class DirectoryEntry { @@ -81,5 +81,5 @@ tag_t tag; // tag of the entry size_t count; // number of copies - Owner owner; // an owner of the line + Owner owner; // an owner of the line size_t ptr; // pointer to the next owner @@ -109,8 +109,8 @@ owner = source.owner; ptr = source.ptr; - } - - ///////////////////////////////////////////////////////////////////// - // The init() function initializes the entry + } + + ///////////////////////////////////////////////////////////////////// + // The init() function initializes the entry ///////////////////////////////////////////////////////////////////// void init() @@ -125,14 +125,14 @@ ///////////////////////////////////////////////////////////////////// - // The copy() function copies an existing source entry to a target + // The copy() function copies an existing source entry to a target ///////////////////////////////////////////////////////////////////// void copy(const DirectoryEntry &source) { - valid = source.valid; + valid = source.valid; cache_coherent = source.cache_coherent; is_cnt = source.is_cnt; - dirty = source.dirty; - lock = source.lock; - tag = source.tag; + dirty = source.dirty; + lock = source.lock; + tag = source.tag; count = source.count; owner = source.owner; @@ -141,17 +141,17 @@ //////////////////////////////////////////////////////////////////// - // The print() function prints the entry + // The print() function prints the entry //////////////////////////////////////////////////////////////////// void print() { - std::cout << "Valid = " << valid + std::cout << "Valid = " << valid << " ; COHERENCE = " << cache_coherent - << " ; IS COUNT = " << is_cnt - << " ; Dirty = " << dirty - << " ; Lock = " << lock - << " ; Tag = " << std::hex << tag << std::dec - << " ; Count = " << count - << " ; Owner = " << owner.srcid - << " " << owner.inst + << " ; IS COUNT = " << is_cnt + << " ; Dirty = " << dirty + << " ; Lock = " << lock + << " ; Tag = " << std::hex << tag << std::dec + << " ; Count = " << count + << " ; Owner = " << owner.srcid + << " " << owner.inst << " ; Pointer = " << ptr << std::endl; } @@ -160,5 +160,5 @@ //////////////////////////////////////////////////////////////////////// - // The directory + // The directory //////////////////////////////////////////////////////////////////////// class CacheDirectory { @@ -171,13 +171,13 @@ // Directory constants - size_t m_ways; - size_t m_sets; - size_t m_words; - size_t m_width; - uint32_t lfsr; + size_t m_ways; + size_t m_sets; + size_t m_words; + size_t m_width; + uint32_t lfsr; // the directory & lru tables - DirectoryEntry **m_dir_tab; - LruEntry **m_lru_tab; + DirectoryEntry **m_dir_tab; + LruEntry **m_lru_tab; public: @@ -186,7 +186,7 @@ // Constructor //////////////////////// - CacheDirectory( size_t ways, size_t sets, size_t words, size_t address_width) - { - m_ways = ways; + CacheDirectory( size_t ways, size_t sets, size_t words, size_t address_width) + { + m_ways = ways; m_sets = sets; m_words = words; @@ -223,7 +223,7 @@ // LRU is updated. // Arguments : - // - address : the address of the entry + // - address : the address of the entry // - way : (return argument) the way of the entry in case of hit - // The function returns a copy of a (valid or invalid) entry + // The function returns a copy of a (valid or invalid) entry ///////////////////////////////////////////////////////////////////// DirectoryEntry read(const addr_t &address, size_t &way) @@ -240,8 +240,8 @@ bool valid = m_dir_tab[set][i].valid; hit = equal && valid; - if ( hit ) { + if ( hit ) { way = i; break; - } + } } if ( hit ) { @@ -255,5 +255,5 @@ ///////////////////////////////////////////////////////////////////// // The inval function invalidate an entry defined by the set and - // way arguments. + // way arguments. ///////////////////////////////////////////////////////////////////// void inval( const size_t &way, const size_t &set ) @@ -266,8 +266,8 @@ // changing the LRU // Arguments : - // - address : the address of the entry - // The function returns a copy of a (valid or invalid) entry - ///////////////////////////////////////////////////////////////////// - DirectoryEntry read_neutral( const addr_t &address, + // - address : the address of the entry + // The function returns a copy of a (valid or invalid) entry + ///////////////////////////////////////////////////////////////////// + DirectoryEntry read_neutral( const addr_t &address, size_t* ret_way, size_t* ret_set ) @@ -279,5 +279,5 @@ #undef L2 - for ( size_t way = 0 ; way < m_ways ; way++ ) + for ( size_t way = 0 ; way < m_ways ; way++ ) { bool equal = ( m_dir_tab[set][way].tag == tag ); @@ -286,13 +286,13 @@ { *ret_set = set; - *ret_way = way; + *ret_way = way; return DirectoryEntry(m_dir_tab[set][way]); } - } + } return DirectoryEntry(); } // end read_neutral() ///////////////////////////////////////////////////////////////////// - // The write function writes a new entry, + // The write function writes a new entry, // and updates the LRU bits if necessary. // Arguments : @@ -301,11 +301,11 @@ // - entry : the entry value ///////////////////////////////////////////////////////////////////// - void write( const size_t &set, - const size_t &way, + void write( const size_t &set, + const size_t &way, const DirectoryEntry &entry) { - assert( (set p_read_fsm; - sc_out p_write_fsm; - sc_out p_xram_rsp_fsm; - sc_out p_cas_fsm; - sc_out p_cleanup_fsm; - sc_out p_config_fsm; - sc_out p_alloc_heap_fsm; - sc_out p_alloc_dir_fsm; - sc_out p_alloc_trt_fsm; - sc_out p_alloc_upt_fsm; - sc_out p_alloc_ivt_fsm; - sc_out p_tgt_cmd_fsm; - sc_out p_tgt_rsp_fsm; - sc_out p_ixr_cmd_fsm; - sc_out p_ixr_rsp_fsm; - sc_out p_cc_send_fsm; - sc_out p_cc_receive_fsm; - sc_out p_multi_ack_fsm; + sc_out p_read_fsm; + sc_out p_write_fsm; + sc_out p_xram_rsp_fsm; + sc_out p_cas_fsm; + sc_out p_cleanup_fsm; + sc_out p_config_fsm; + sc_out p_alloc_heap_fsm; + sc_out p_alloc_dir_fsm; + sc_out p_alloc_trt_fsm; + sc_out p_alloc_upt_fsm; + sc_out p_alloc_ivt_fsm; + sc_out p_tgt_cmd_fsm; + sc_out p_tgt_rsp_fsm; + sc_out p_ixr_cmd_fsm; + sc_out p_ixr_rsp_fsm; + sc_out p_cc_send_fsm; + sc_out p_cc_receive_fsm; + sc_out p_multi_ack_fsm; #endif @@ -558,7 +558,7 @@ const size_t max_copies, // max number of copies const size_t heap_size=HEAP_ENTRIES, - const size_t trt_lines=TRT_ENTRIES, - const size_t upt_lines=UPT_ENTRIES, - const size_t ivt_lines=IVT_ENTRIES, + const size_t trt_lines=TRT_ENTRIES, + const size_t upt_lines=UPT_ENTRIES, + const size_t ivt_lines=IVT_ENTRIES, const size_t debug_start_cycle=0, const bool debug_ok=false ); @@ -584,5 +584,5 @@ // Component attributes - std::list m_seglist; // segments allocated + std::list m_seglist; // segments allocated size_t m_nseg; // number of segments soclib::common::Segment **m_seg; // array of segments pointers @@ -657,5 +657,5 @@ // Fifo between CC_RECEIVE fsm and CLEANUP fsm GenericFifo m_cc_receive_to_cleanup_fifo; - + // Fifo between CC_RECEIVE fsm and MULTI_ACK fsm GenericFifo m_cc_receive_to_multi_ack_fifo; @@ -686,5 +686,5 @@ sc_signal r_config_fsm; // FSM state sc_signal r_config_lock; // lock protecting exclusive access - sc_signal r_config_cmd; // config request type + sc_signal r_config_cmd; // config request type sc_signal r_config_address; // target buffer physical address sc_signal r_config_srcid; // config request srcid @@ -702,5 +702,5 @@ sc_signal r_config_heap_next; // current pointer to scan HEAP sc_signal r_config_trt_index; // selected entry in TRT - sc_signal r_config_ivt_index; // selected entry in IVT + sc_signal r_config_ivt_index; // selected entry in IVT // Buffer between CONFIG fsm and IXR_CMD fsm @@ -744,5 +744,5 @@ sc_signal r_read_ll_key; // LL key from llsc_global_table - // Buffer between READ fsm and IXR_CMD fsm + // Buffer between READ fsm and IXR_CMD fsm sc_signal r_read_to_ixr_cmd_req; // valid request sc_signal r_read_to_ixr_cmd_index; // TRT index @@ -764,5 +764,5 @@ sc_signal r_read_to_cc_send_inst; - //RWT: Buffer between READ fsm and CLEANUP fsm (wait for the data coming from L1 cache) + //RWT: Buffer between READ fsm and CLEANUP fsm (wait for the data coming from L1 cache) sc_signal r_read_to_cleanup_req; // valid request sc_signal r_read_to_cleanup_nline; // cache line index @@ -771,5 +771,5 @@ sc_signal r_read_to_cleanup_length; sc_signal r_read_to_cleanup_first_word; - sc_signal r_read_to_cleanup_cached_read; + sc_signal r_read_to_cleanup_cached_read; sc_signal r_read_to_cleanup_is_ll; sc_signal r_read_to_cleanup_addr; @@ -810,5 +810,5 @@ sc_signal r_write_sc_key; // sc command key sc_signal r_write_bc_data_we; // Write enable for data buffer - + // Buffer between WRITE fsm and TGT_RSP fsm (acknowledge a write command from L1) sc_signal r_write_to_tgt_rsp_req; // valid request @@ -818,7 +818,7 @@ sc_signal r_write_to_tgt_rsp_sc_fail; // sc command failed - // Buffer between WRITE fsm and IXR_CMD fsm + // Buffer between WRITE fsm and IXR_CMD fsm sc_signal r_write_to_ixr_cmd_req; // valid request - sc_signal r_write_to_ixr_cmd_index; // TRT index + sc_signal r_write_to_ixr_cmd_index; // TRT index // Buffer between WRITE fsm and CC_SEND fsm (Update/Invalidate L1 caches) @@ -908,5 +908,5 @@ sc_signal r_cleanup_to_tgt_rsp_trdid; // transaction trdid sc_signal r_cleanup_to_tgt_rsp_pktid; // transaction pktid - sc_signal r_cleanup_to_tgt_rsp_ll_key; + sc_signal r_cleanup_to_tgt_rsp_ll_key; //RWT @@ -948,5 +948,5 @@ // Buffer between CAS fsm and IXR_CMD fsm (XRAM write) sc_signal r_cas_to_ixr_cmd_req; // valid request - sc_signal r_cas_to_ixr_cmd_index; // TRT index + sc_signal r_cas_to_ixr_cmd_index; // TRT index // Buffer between CAS fsm and TGT_RSP fsm @@ -978,5 +978,5 @@ // Buffer between IXR_RSP fsm and CONFIG fsm (response from the XRAM) - sc_signal r_ixr_rsp_to_config_ack; // one single bit + sc_signal r_ixr_rsp_to_config_ack; // one single bit // Buffer between IXR_RSP fsm and XRAM_RSP fsm (response from the XRAM) @@ -1028,7 +1028,7 @@ GenericFifo m_xram_rsp_to_cc_send_srcid_fifo; // fifo for srcids - // Buffer between XRAM_RSP fsm and IXR_CMD fsm + // Buffer between XRAM_RSP fsm and IXR_CMD fsm sc_signal r_xram_rsp_to_ixr_cmd_req; // Valid request - sc_signal r_xram_rsp_to_ixr_cmd_index; // TRT index + sc_signal r_xram_rsp_to_ixr_cmd_index; // TRT index //RWT @@ -1041,5 +1041,5 @@ sc_signal r_ixr_cmd_fsm; sc_signal r_ixr_cmd_word; // word index for a put - sc_signal r_ixr_cmd_trdid; // TRT index value + sc_signal r_ixr_cmd_trdid; // TRT index value sc_signal r_ixr_cmd_address; // address to XRAM sc_signal * r_ixr_cmd_wdata; // cache line buffer @@ -1112,9 +1112,9 @@ sc_signal *r_cleanup_old_data; sc_signal r_cleanup_contains_data; - + sc_signal r_cleanup_ncc; sc_signal r_cleanup_to_ixr_cmd_ncc_l1_dirty; sc_signal r_xram_rsp_to_ixr_cmd_inval_ncc_pending; - + sc_signal r_cleanup_to_ixr_cmd_req; sc_signal *r_cleanup_to_ixr_cmd_data; Index: branches/RWT/modules/vci_mem_cache/caba/source/include/xram_transaction.h =================================================================== --- branches/RWT/modules/vci_mem_cache/caba/source/include/xram_transaction.h (revision 787) +++ branches/RWT/modules/vci_mem_cache/caba/source/include/xram_transaction.h (revision 814) @@ -10,8 +10,8 @@ //////////////////////////////////////////////////////////////////////// -// A transaction tab entry +// A transaction tab entry //////////////////////////////////////////////////////////////////////// -class TransactionTabEntry +class TransactionTabEntry { typedef sc_dt::sc_uint<64> wide_data_t; @@ -21,27 +21,27 @@ public: - bool valid; // entry valid - bool xram_read; // read request to XRAM - addr_t nline; // index (zy) of the requested line - size_t srcid; // processor requesting the transaction - size_t trdid; // processor requesting the transaction - size_t pktid; // processor requesting the transaction - bool proc_read; // read request from processor - size_t read_length; // length of the read (for the response) - size_t word_index; // index of the first read word (for the response) - std::vector wdata; // write buffer (one cache line) - std::vector wdata_be; // be for each data in the write buffer - bool rerror; // error returned by xram - data_t ll_key; // LL key returned by the llsc_global_table - bool config; // transaction required by CONFIG FSM - - ///////////////////////////////////////////////////////////////////// - // The init() function initializes the entry + bool valid; // entry valid + bool xram_read; // read request to XRAM + addr_t nline; // index (zy) of the requested line + size_t srcid; // processor requesting the transaction + size_t trdid; // processor requesting the transaction + size_t pktid; // processor requesting the transaction + bool proc_read; // read request from processor + size_t read_length; // length of the read (for the response) + size_t word_index; // index of the first read word (for the response) + std::vector wdata; // write buffer (one cache line) + std::vector wdata_be; // be for each data in the write buffer + bool rerror; // error returned by xram + data_t ll_key; // LL key returned by the llsc_global_table + bool config; // transaction required by CONFIG FSM + + ///////////////////////////////////////////////////////////////////// + // The init() function initializes the entry ///////////////////////////////////////////////////////////////////// void init() { - valid = false; - rerror = false; - config = false; + valid = false; + rerror = false; + config = false; } @@ -69,13 +69,13 @@ void copy(const TransactionTabEntry &source) { - valid = source.valid; - xram_read = source.xram_read; - nline = source.nline; - srcid = source.srcid; - trdid = source.trdid; - pktid = source.pktid; - proc_read = source.proc_read; + valid = source.valid; + xram_read = source.xram_read; + nline = source.nline; + srcid = source.srcid; + trdid = source.trdid; + pktid = source.pktid; + proc_read = source.proc_read; read_length = source.read_length; - word_index = source.word_index; + word_index = source.word_index; wdata_be.assign(source.wdata_be.begin(),source.wdata_be.end()); wdata.assign(source.wdata.begin(),source.wdata.end()); @@ -86,5 +86,5 @@ //////////////////////////////////////////////////////////////////// - // The print() function prints the entry + // The print() function prints the entry //////////////////////////////////////////////////////////////////// void print() @@ -99,13 +99,13 @@ std::cout << "proc_read = " << proc_read << std::endl; std::cout << "read_length = " << read_length << std::endl; - std::cout << "word_index = " << word_index << std::endl; + std::cout << "word_index = " << word_index << std::endl; for(size_t i=0; i &be, - const std::vector &data) + void write_data_mask(const size_t index, + const std::vector &be, + const std::vector &data) { assert( (index < size_tab) and @@ -349,5 +349,5 @@ "MEMC ERROR: Bad data size in TRT write_data_mask()"); - for(size_t i=0; i &data_be, - const std::vector &data, + const std::vector &data, const data_t ll_key = 0, - const bool config = false) + const bool config = false) { assert( (index < size_tab) and "MEMC ERROR: The selected entry is out of range in TRT set()"); - assert( (data_be.size()==tab[index].wdata_be.size()) and + assert( (data_be.size()==tab[index].wdata_be.size()) and "MEMC ERROR: Bad data_be argument in TRT set()"); - assert( (data.size()==tab[index].wdata.size()) and + assert( (data.size()==tab[index].wdata.size()) and "MEMC ERROR: Bad data argument in TRT set()"); - tab[index].valid = true; - tab[index].xram_read = xram_read; - tab[index].nline = nline; - tab[index].srcid = srcid; - tab[index].trdid = trdid; - tab[index].pktid = pktid; - tab[index].proc_read = proc_read; - tab[index].read_length = read_length; - tab[index].word_index = word_index; - tab[index].ll_key = ll_key; - tab[index].config = config; - for(size_t i=0; i - if (is_local_req(p_vci_tgt.srcid.read())) + if (is_local_req(p_vci_tgt.srcid.read())) { m_cpt_cas_local++; @@ -1993,5 +1993,5 @@ // MULTI_ACK FSM ///////////////////////////////////////////////////////////////////////// - // This FSM controls the response to the multicast update requests sent + // This FSM controls the response to the multicast update requests sent // by the memory cache to the L1 caches and update the UPT. // @@ -2133,5 +2133,5 @@ ///////////////////////// case MULTI_ACK_WRITE_RSP: // Post a response request to TGT_RSP FSM - // Wait if pending request + // Wait if pending request { if ( r_multi_ack_to_tgt_rsp_req.read() ) break; @@ -2168,9 +2168,9 @@ // - // For both INVAL and SYNC commands, the CONFIG FSM contains the loop handling + // For both INVAL and SYNC commands, the CONFIG FSM contains the loop handling // // all cache lines covered by the buffer. The various lines of a given buffer // can be pipelined: the CONFIG FSM does not wait the response for line (n) to send - // the command for line (n+1). It decrements the r_config_cmd_lines counter until + // the command for line (n+1). It decrements the r_config_cmd_lines counter until // the last request has been registered in TRT (for a SYNC), or in IVT (for an INVAL). // The r_config_rsp_lines counter contains the number of expected responses from @@ -2180,8 +2180,8 @@ // be concurently accessed by those three FSMs, it is implemented as an [incr/decr] // counter. - // + // // - INVAL request: - // For each line, it access to the DIR. - // In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. + // For each line, it access to the DIR. + // In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. // In case of hit, with no copies in L1 caches, the line is invalidated and // a response is requested to TGT_RSP FSM. @@ -2195,8 +2195,8 @@ // This constraint can be released, but it requires to make 2 PUT transactions // for the first and the last line... - // + // // - SYNC request: - // For each line, it access to the DIR. - // In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. + // For each line, it access to the DIR. + // In case of miss, it does nothing, and a response is requested to TGT_RSP FSM. // In case of hit, a PUT transaction is registered in TRT and a request is sent // to IXR_CMD FSM. The IXR_RSP FSM decrements the r_config_rsp_lines counter @@ -2205,5 +2205,5 @@ // // From the software point of view, a configuration request is a sequence - // of 6 atomic accesses in an uncached segment. A dedicated lock is used + // of 6 atomic accesses in an uncached segment. A dedicated lock is used // to handle only one configuration command at a given time: // - Read MEMC_LOCK : Get the lock @@ -2218,7 +2218,7 @@ { ///////////////// - case CONFIG_IDLE: // waiting a config request - { - if ( r_config_cmd.read() != MEMC_CMD_NOP ) + case CONFIG_IDLE: // waiting a config request + { + if ( r_config_cmd.read() != MEMC_CMD_NOP ) { r_config_fsm = CONFIG_LOOP; @@ -2226,5 +2226,5 @@ #if DEBUG_MEMC_CONFIG if(m_debug) - std::cout << " Config Request received" + std::cout << " Config Request received" << " address = " << std::hex << r_config_address.read() << " / nlines = " << std::dec << r_config_cmd_lines.read() @@ -2235,5 +2235,5 @@ } ///////////////// - case CONFIG_LOOP: // test last line to be handled + case CONFIG_LOOP: // test last line to be handled { if ( r_config_cmd_lines.read() == 0 ) @@ -2249,7 +2249,7 @@ #if DEBUG_MEMC_CONFIG if(m_debug) - std::cout << " " - << " address = " << std::hex << r_config_address.read() - << " / nlines = " << std::dec << r_config_cmd_lines.read() + std::cout << " " + << " address = " << std::hex << r_config_address.read() + << " / nlines = " << std::dec << r_config_cmd_lines.read() << " / command = " << r_config_cmd.read() << std::endl; #endif @@ -2257,5 +2257,5 @@ } ///////////////// - case CONFIG_WAIT: // wait completion (last response) + case CONFIG_WAIT: // wait completion (last response) { if ( r_config_rsp_lines.read() == 0 ) // last response received @@ -2266,5 +2266,5 @@ #if DEBUG_MEMC_CONFIG if(m_debug) - std::cout << " " + std::cout << " " << " / lines to do = " << std::dec << r_config_rsp_lines.read() << std::endl; #endif @@ -2272,5 +2272,5 @@ } //////////////// - case CONFIG_RSP: // request TGT_RSP FSM to return response + case CONFIG_RSP: // request TGT_RSP FSM to return response { if ( not r_config_to_tgt_rsp_req.read() ) @@ -2329,5 +2329,5 @@ if (entry.valid and // hit & inval command - (r_config_cmd.read() == MEMC_CMD_INVAL)) + (r_config_cmd.read() == MEMC_CMD_INVAL)) { r_config_fsm = CONFIG_IVT_LOCK; @@ -2336,8 +2336,8 @@ entry.dirty and (r_config_cmd.read() == MEMC_CMD_SYNC) ) - { + { r_config_fsm = CONFIG_TRT_LOCK; } - else // return to LOOP + else // return to LOOP { r_config_cmd_lines = r_config_cmd_lines.read() - 1; @@ -2359,5 +2359,5 @@ ///////////////////// case CONFIG_TRT_LOCK: // enter this state in case of SYNC command - // to a dirty cache line + // to a dirty cache line // keep DIR lock, and try to get TRT lock // return to LOOP state if TRT full @@ -2423,5 +2423,5 @@ std::vector data_vector; data_vector.clear(); - for(size_t word=0; word(m_words,0xF), // byte-enable: unused + std::vector(m_words,0xF), // byte-enable: unused data_vector, // data to be written 0, // ll_key: unused @@ -2470,5 +2470,5 @@ if(m_debug) std::cout << " post PUT request to IXR_CMD_FSM" - << " / address = " << std::hex << r_config_address.read() << std::endl; + << " / address = " << std::hex << r_config_address.read() << std::endl; #endif } @@ -2480,5 +2480,5 @@ // Return to LOOP state if IVT full. // Register inval in IVT, and invalidate the - // directory if IVT not full. + // directory if IVT not full. { assert( (r_alloc_dir_fsm.read() == ALLOC_DIR_CONFIG) and @@ -2515,5 +2515,5 @@ wok = m_ivt.set(false, // it's an inval transaction - broadcast, + broadcast, false, // no response required true, // acknowledge required @@ -2558,5 +2558,5 @@ case CONFIG_BC_SEND: // Post a broadcast inval request to CC_SEND FSM { - if( not r_config_to_cc_send_multi_req.read() and + if( not r_config_to_cc_send_multi_req.read() and not r_config_to_cc_send_brdcast_req.read() ) { @@ -2575,5 +2575,5 @@ if(m_debug) std::cout << " " - << " Post a broadcast inval request to CC_SEND FSM" + << " Post a broadcast inval request to CC_SEND FSM" << " / address = " << r_config_address.read() <" - << " Post multi inval request to CC_SEND FSM" - << " / address = " << std::hex << r_config_address.read() - << " / copy = " << r_config_dir_copy_srcid.read() + << " Post multi inval request to CC_SEND FSM" + << " / address = " << std::hex << r_config_address.read() + << " / copy = " << r_config_dir_copy_srcid.read() << " / inst = " << std::dec << r_config_dir_copy_inst.read() << std::endl; #endif @@ -2640,5 +2640,5 @@ { HeapEntry entry = m_heap.read( r_config_heap_next.read() ); - bool last_copy = (entry.next == r_config_heap_next.read()); + bool last_copy = (entry.next == r_config_heap_next.read()); config_to_cc_send_fifo_srcid = entry.owner.srcid; @@ -2660,7 +2660,7 @@ if(m_debug) std::cout << " " - << " Post multi inval request to CC_SEND FSM" - << " / address = " << std::hex << r_config_address.read() - << " / copy = " << entry.owner.srcid + << " Post multi inval request to CC_SEND FSM" + << " / address = " << std::hex << r_config_address.read() + << " / copy = " << entry.owner.srcid << " / inst = " << std::dec << entry.owner.inst << std::endl; #endif @@ -2681,5 +2681,5 @@ } else - { + { last_entry.next = free_pointer; } @@ -2799,5 +2799,5 @@ // hit on a WT line or the owner has no more copy (if LL, the owner must be invalidated even if he made the request) - if (entry.cache_coherent or (entry.count == 0))// or (entry.owner.srcid == m_cmd_read_srcid_fifo.read())) + if (entry.cache_coherent or (entry.count == 0))// or (entry.owner.srcid == m_cmd_read_srcid_fifo.read())) { // test if we need to register a new copy in the heap @@ -2851,5 +2851,5 @@ { std::cout - << " " + << " " << " Wait cleanup completion" << std::endl; @@ -2862,9 +2862,9 @@ r_read_to_cc_send_dest = r_read_copy.read(); r_read_to_cc_send_nline = nline; - r_read_to_cc_send_inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); + r_read_to_cc_send_inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); r_read_to_cleanup_req = true; r_read_to_cleanup_nline = nline; r_read_to_cleanup_srcid = m_cmd_read_srcid_fifo.read(); - r_read_to_cleanup_inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); + r_read_to_cleanup_inst = ((m_cmd_read_pktid_fifo.read() & 0x2) != 0); r_read_to_cleanup_length = m_cmd_read_length_fifo.read(); r_read_to_cleanup_first_word = m_x[(addr_t) m_cmd_read_addr_fifo.read()]; @@ -2920,5 +2920,5 @@ break; } - /////////////////// + /////////////////// case READ_DIR_HIT: // read data in cache & update the directory // we enter this state in 3 cases: @@ -3024,9 +3024,5 @@ bool go_cnt = (r_read_count.read() >= m_max_copies) or m_heap.is_full(); - if (!r_read_coherent.read()) - { - std::cout << "Address = " << std::hex << (m_cmd_read_addr_fifo.read()) << std::dec << " |count = " << r_read_count.read() << std::endl; - } - assert (r_read_coherent.read() && "accÚs au heap sur ncc"); + assert (r_read_coherent.read() && "Heap access on line NCC"); // read data in the cache size_t set = m_y[(addr_t)(m_cmd_read_addr_fifo.read())]; @@ -3135,5 +3131,5 @@ m_heap.set_full(); } - + // m_cpt_heap_slot_available--; @@ -3418,6 +3414,6 @@ << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read() << " / address = " << std::hex << m_cmd_write_addr_fifo.read() - << " / data = " << m_cmd_write_data_fifo.read() - << " / pktid = " << m_cmd_write_pktid_fifo.read() + << " / data = " << m_cmd_write_data_fifo.read() + << " / pktid = " << m_cmd_write_pktid_fifo.read() << std::endl; #endif @@ -3431,5 +3427,5 @@ // check that the next word is in the same cache line - assert((m_nline[(addr_t)(r_write_address.read())] == + assert((m_nline[(addr_t)(r_write_address.read())] == m_nline[(addr_t)(m_cmd_write_addr_fifo.read())]) && "MEMC ERROR in WRITE_NEXT state: Illegal write burst"); @@ -3482,5 +3478,5 @@ // test address and key match of the SC command on the // LL/SC table without removing reservation. The reservation - // will be erased after in this FSM. + // will be erased after in this FSM. bool sc_success = m_llsc_table.check(r_write_address.read(), r_write_sc_key.read()); @@ -3493,5 +3489,5 @@ else { - // write burst + // write burst #define L2 soclib::common::uint32_log2 addr_t min = r_write_address.read(); @@ -3594,5 +3590,5 @@ addr_t nline = m_nline[(addr_t)(r_write_address.read())]; - //if there is a matched updt req, we should wait until it is over. Because + //if there is a matched updt req, we should wait until it is over. Because //we need the lastest updt data. match_inval = m_ivt.search_inval(nline, index); @@ -3600,5 +3596,5 @@ assert ((r_write_count.read() == 1) and "NCC to CC req without copy"); - if( not match_inval and + if( not match_inval and not m_ivt.is_full() and not r_write_to_cc_send_req.read() and @@ -3676,5 +3672,5 @@ // no_update is true when there is no need for coherence transaction bool no_update = ( (r_write_count.read() == 0) or - (owner and (r_write_count.read() == 1) and + (owner and (r_write_count.read() == 1) and ((r_write_pktid.read() & 0x7) != TYPE_SC))); @@ -3682,5 +3678,5 @@ if(no_update) { - // SC command but zero copies + // SC command but zero copies if ((r_write_pktid.read() & 0x7) == TYPE_SC) { @@ -3726,5 +3722,5 @@ if(no_update) { - std::cout << " Write into cache / No coherence transaction" << std::endl; @@ -3761,5 +3757,5 @@ true, // response required false, // no acknowledge required - srcid, + srcid, trdid, pktid, @@ -3792,5 +3788,5 @@ if(wok) { - std::cout << " Register the multicast update in UPT / " << " nb_copies = " << r_write_count.read() << std::endl; @@ -3814,5 +3810,5 @@ #if DEBUG_MEMC_WRITE if(m_debug) - std::cout << " Get acces to the HEAP" << std::endl; #endif @@ -3906,5 +3902,5 @@ // put the next srcid in the fifo - if ((entry.owner.srcid != r_write_srcid.read()) or + if ((entry.owner.srcid != r_write_srcid.read()) or ((r_write_pktid.read() & 0x7) == TYPE_SC) or entry.owner.inst) @@ -4026,5 +4022,5 @@ r_write_sc_key = m_cmd_write_data_fifo.read(); - } + } // initialize the be field for all words @@ -4049,6 +4045,6 @@ { std::cout << " Post a request to TGT_RSP FSM" - << " : rsrcid = " << std::hex << r_write_srcid.read() - << " : rpktid = " << std::hex << r_write_pktid.read() + << " : rsrcid = " << std::hex << r_write_srcid.read() + << " : rpktid = " << std::hex << r_write_pktid.read() << " : sc_fail= " << std::hex << r_write_sc_fail.read() << std::endl; @@ -4058,6 +4054,6 @@ << " srcid = " << std::hex << m_cmd_write_srcid_fifo.read() << " / address = " << m_cmd_write_addr_fifo.read() - << " / data = " << m_cmd_write_data_fifo.read() - << " / pktid = " << m_cmd_write_pktid_fifo.read() + << " / data = " << m_cmd_write_data_fifo.read() + << " / pktid = " << m_cmd_write_pktid_fifo.read() << std::endl; } @@ -4068,5 +4064,5 @@ } ///////////////////////// RWT - case WRITE_MISS_IVT_LOCK: + case WRITE_MISS_IVT_LOCK: { if (r_alloc_ivt_fsm.read() == ALLOC_IVT_WRITE) @@ -4224,5 +4220,5 @@ #if DEBUG_MEMC_WRITE if(m_debug) - std::cout << " Post a GET request to the" << " IXR_CMD FSM" << std::endl; @@ -4282,5 +4278,5 @@ #if DEBUG_MEMC_WRITE if(m_debug) - std::cout + std::cout << " Complete data buffer" << std::endl; @@ -4476,5 +4472,5 @@ // // - It sends a single flit VCI read to the XRAM in case of - // GET request posted by the READ, WRITE or CAS FSMs. + // GET request posted by the READ, WRITE or CAS FSMs. // - It sends a multi-flit VCI write in case of PUT request posted by // the XRAM_RSP, WRITE, CAS, or CONFIG FSMs. @@ -4535,5 +4531,5 @@ else if(r_config_to_ixr_cmd_req.read()) r_ixr_cmd_fsm = IXR_CMD_CONFIG_TRT; else if(r_cleanup_to_ixr_cmd_req) r_ixr_cmd_fsm = IXR_CMD_CLEANUP_TRT; - break; + break; ///////////////////////// case IXR_CMD_CONFIG_IDLE: @@ -4597,5 +4593,5 @@ } ///////////////////// - case IXR_CMD_CAS_TRT: // access TRT for a PUT or a GET + case IXR_CMD_CAS_TRT: // access TRT for a PUT or a GET { if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) @@ -4624,5 +4620,5 @@ } ////////////////////// - case IXR_CMD_XRAM_TRT: // access TRT for a PUT + case IXR_CMD_XRAM_TRT: // access TRT for a PUT { if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) @@ -4646,5 +4642,5 @@ } ////////////////////// - case IXR_CMD_CLEANUP_TRT: // access TRT for a PUT + case IXR_CMD_CLEANUP_TRT: // access TRT for a PUT { if ( r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_CMD ) @@ -4866,5 +4862,5 @@ // The FSM takes the lock protecting the TRT, and the corresponding // entry is erased. If an acknowledge was required (in case of software SYNC) - // the r_config_rsp_lines counter is decremented. + // the r_config_rsp_lines counter is decremented. // // - A response to a GET request is a multi-cell VCI packet. @@ -4873,5 +4869,5 @@ // The FSM takes the lock protecting the TRT to store the line in the TRT // (taking into account the write requests already stored in the TRT). - // When the line is completely written, the r_ixr_rsp_to_xram_rsp_rok[index] + // When the line is completely written, the r_ixr_rsp_to_xram_rsp_rok[index] // signal is set to inform the XRAM_RSP FSM. /////////////////////////////////////////////////////////////////////////////// @@ -4902,6 +4898,6 @@ << " IXR_RSP_IDLE> Response from XRAM to a get transaction" << std::endl; #endif - } - } + } + } break; } @@ -4919,5 +4915,5 @@ if(r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP) { - size_t index = r_ixr_rsp_trt_index.read(); + size_t index = r_ixr_rsp_trt_index.read(); if (m_trt.is_config(index)) // it's a config transaction { @@ -4977,5 +4973,5 @@ // The cache line has been written in the TRT by the IXR_CMD_FSM. // As the IXR_RSP FSM and the XRAM_RSP FSM are running in parallel, - // there is as many flip-flops r_ixr_rsp_to_xram_rsp_rok[i] as the number + // there is as many flip-flops r_ixr_rsp_to_xram_rsp_rok[i] as the number // of entries in the TRT, that are handled with a round-robin priority... // @@ -5018,5 +5014,5 @@ break; } - } + } break; } @@ -5074,9 +5070,9 @@ r_xram_rsp_victim_inval = inval ; // a NCC line is by default considered as dirty in the L1: we must take a reservation on a TRT entry - r_xram_rsp_victim_dirty = victim.dirty or (!victim.cache_coherent && (victim.count == 1)); + r_xram_rsp_victim_dirty = victim.dirty or (!victim.cache_coherent && (victim.count == 1)); // A line that undergoes a change in its state (ncc to cc), should not be evicted from the memory cache. - if((victim.tag * m_sets + set) == r_read_to_cleanup_nline.read() and r_read_to_cleanup_req.read()) + if((victim.tag * m_sets + set) == r_read_to_cleanup_nline.read() and r_read_to_cleanup_req.read()) { r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT; @@ -5090,9 +5086,9 @@ #endif } - else if( not r_xram_rsp_trt_buf.rerror ) + else if( not r_xram_rsp_trt_buf.rerror ) { r_xram_rsp_fsm = XRAM_RSP_IVT_LOCK; } - else + else { r_xram_rsp_fsm = XRAM_RSP_ERROR_ERASE; @@ -5111,5 +5107,5 @@ } /////////////////////// - case XRAM_RSP_IVT_LOCK: // Keep DIR and TRT locks and take the IVT lock + case XRAM_RSP_IVT_LOCK: // Keep DIR and TRT locks and take the IVT lock // to check a possible pending inval { @@ -5241,6 +5237,6 @@ bool wok = m_ivt.set(false, // it's an inval transaction broadcast, // set broadcast bit - false, // no response required - false, // no acknowledge required + false, // no response required + false, // no acknowledge required 0, // srcid 0, // trdid @@ -5252,5 +5248,5 @@ r_xram_rsp_ivt_index = index; assert( wok and - "MEMC ERROR in XRAM_RSP_DIR_UPDT state: IVT should not be full"); + "MEMC ERROR in XRAM_RSP_DIR_UPDT state: IVT should not be full"); } @@ -5313,5 +5309,5 @@ 0, // unused 0, // unused - std::vector(m_words,0xF), + std::vector(m_words,0xF), data_vector); #if DEBUG_MEMC_XRAM_RSP @@ -5411,5 +5407,5 @@ m_cpt_write_dirty++; - bool multi_req = not r_xram_rsp_victim_is_cnt.read() and + bool multi_req = not r_xram_rsp_victim_is_cnt.read() and r_xram_rsp_victim_inval.read(); bool not_last_multi_req = multi_req and (r_xram_rsp_victim_count.read() != 1); @@ -5540,5 +5536,5 @@ // acknowledged before signaling another one. // Therefore, when there is an active error, and other - // errors arrive, these are not considered + // errors arrive, these are not considered if (!r_xram_rsp_rerror_irq.read() && r_xram_rsp_rerror_irq_enable.read() @@ -5639,5 +5635,5 @@ r_cleanup_inst = (type == DspinRwtParam::TYPE_CLEANUP_INST); r_cleanup_srcid = srcid; - r_cleanup_ncc = + r_cleanup_ncc = DspinRwtParam::dspin_get( flit, @@ -5738,5 +5734,5 @@ uint64_t flit = m_cc_receive_to_cleanup_fifo.read(); - uint32_t data = + uint32_t data = DspinRwtParam::dspin_get (flit, DspinRwtParam::CLEANUP_DATA_UPDT); @@ -5809,5 +5805,5 @@ //RWT size_t set = m_y[(addr_t)(cleanup_address)]; - m_cache_data.read_line(way, set, r_cleanup_old_data); + m_cache_data.read_line(way, set, r_cleanup_old_data); r_cleanup_coherent = entry.cache_coherent; @@ -5911,5 +5907,5 @@ entry.lock = r_cleanup_lock.read(); entry.ptr = r_cleanup_ptr.read(); - if (r_read_to_cleanup_req.read() and (r_cleanup_nline.read() == r_read_to_cleanup_nline.read())) //pending READ + if (r_read_to_cleanup_req.read() and (r_cleanup_nline.read() == r_read_to_cleanup_nline.read())) //pending READ { if (r_read_to_cleanup_cached_read.read()) @@ -5937,5 +5933,5 @@ #if REVERT_CC_MECANISM - // Revert CC to NCC if : + // Revert CC to NCC if : // - no more copy in L1 caches // - this line is not in counter mode (broadcast) @@ -5948,5 +5944,5 @@ #if REVERT_BC_MECANISM - if ((r_cleanup_count.read() - 1) == 0) + if ((r_cleanup_count.read() - 1) == 0) { entry.is_cnt = false; @@ -6082,5 +6078,5 @@ { r_cleanup_to_tgt_rsp_data[i] = r_cleanup_old_data[i].read(); - } + } } @@ -6354,5 +6350,5 @@ ////////////////////// case CLEANUP_IVT_LOCK: // get the lock protecting the IVT to search a pending - // invalidate transaction matching the cleanup + // invalidate transaction matching the cleanup { if(r_alloc_ivt_fsm.read() != ALLOC_IVT_CLEANUP) break; @@ -6432,5 +6428,5 @@ } /////////////////////// - case CLEANUP_IVT_CLEAR: // Clear IVT entry + case CLEANUP_IVT_CLEAR: // Clear IVT entry { assert( (r_alloc_ivt_fsm.read() == ALLOC_IVT_CLEANUP) and @@ -6473,5 +6469,5 @@ r_cleanup_to_tgt_rsp_trdid = r_cleanup_write_trdid.read(); r_cleanup_to_tgt_rsp_pktid = r_cleanup_write_pktid.read(); - r_cleanup_to_tgt_rsp_type = true; + r_cleanup_to_tgt_rsp_type = true; if (r_cleanup_ncc.read() ) @@ -6503,5 +6499,5 @@ { size_t index = 0; - bool hit = m_trt.hit_write(r_cleanup_nline.read(), &index); + bool hit = m_trt.hit_write(r_cleanup_nline.read(), &index); assert (hit and "CLEANUP_IXR_REQ found no matching entry in TRT"); @@ -6510,5 +6506,5 @@ if (r_cleanup_contains_data.read()) - { + { std::vector data_vector; data_vector.clear(); @@ -6587,5 +6583,5 @@ << " nline = " << std::hex << r_cleanup_nline.read() << " / way = " << std::dec << r_cleanup_way.read() - << " / srcid = " << std::dec << r_cleanup_srcid.read() + << " / srcid = " << std::dec << r_cleanup_srcid.read() << std::endl; #endif @@ -6805,5 +6801,5 @@ if(m_debug) std::cout << " " - << " Broacast Inval required" + << " Broacast Inval required" << " / copies = " << r_cas_count.read() << std::endl; #endif @@ -6817,5 +6813,5 @@ if(m_debug) std::cout << " " - << " Multi Inval required" + << " Multi Inval required" << " / copies = " << r_cas_count.read() << std::endl; #endif @@ -6874,5 +6870,5 @@ wok = m_upt.set(true, // it's an update transaction false, // it's not a broadcast - true, // response required + true, // response required false, // no acknowledge required srcid, @@ -7137,5 +7133,5 @@ { if(i == word) // first modified word - data_vector.push_back( r_cas_wdata.read() ); + data_vector.push_back( r_cas_wdata.read() ); else if((i == word+1) and (r_cas_cpt.read() == 4)) // second modified word data_vector.push_back( m_cmd_cas_wdata_fifo.read() ); @@ -7144,5 +7140,5 @@ } m_trt.set( r_cas_trt_index.read(), - false, // PUT request + false, // PUT request m_nline[(addr_t)(m_cmd_cas_addr_fifo.read())], 0, @@ -7364,5 +7360,5 @@ // // It implements a round-robin priority between the four possible client FSMs - // XRAM_RSP > CAS > READ > WRITE > CONFIG + // XRAM_RSP > CAS > READ > WRITE > CONFIG // // Each FSM can request the next services: @@ -7375,5 +7371,5 @@ // - r_config_to_cc_send_multi_req : multi-inval // r_config_to_cc_send_brdcast_req : broadcast-inval - // + // // An inval request is a double DSPIN flit command containing: // 1. the index of the line to be invalidated. @@ -7517,5 +7513,5 @@ } /////////////////////////// - case CC_SEND_READ_IDLE: + case CC_SEND_READ_IDLE: { // WRITE @@ -8264,5 +8260,5 @@ } else if(r_multi_ack_to_tgt_rsp_req) r_tgt_rsp_fsm = TGT_RSP_MULTI_ACK; - else if(r_cleanup_to_tgt_rsp_req) + else if(r_cleanup_to_tgt_rsp_req) { r_tgt_rsp_fsm = TGT_RSP_CLEANUP; @@ -8809,5 +8805,5 @@ // - The XRAM_RSP FSM initiates broadcast/multicast invalidate transaction and sets // a new entry in the IVT - // - The CONFIG FSM does the same thing as the XRAM_RSP FSM + // - The CONFIG FSM does the same thing as the XRAM_RSP FSM // - The CLEANUP FSM complete those trasactions and erase the IVT entry. // The resource is always allocated. @@ -8844,5 +8840,5 @@ ////////////////////////// case ALLOC_IVT_READ: // allocated to READ FSM - if (r_read_fsm.read() != READ_IVT_LOCK) + if (r_read_fsm.read() != READ_IVT_LOCK) { if (r_xram_rsp_fsm.read() == XRAM_RSP_IVT_LOCK) @@ -9231,5 +9227,5 @@ r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; - else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) + else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) r_alloc_trt_fsm = ALLOC_TRT_CONFIG; @@ -9268,5 +9264,5 @@ r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; - else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) + else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) r_alloc_trt_fsm = ALLOC_TRT_CONFIG; @@ -9304,5 +9300,5 @@ r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; - else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) + else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) r_alloc_trt_fsm = ALLOC_TRT_CONFIG; @@ -9338,5 +9334,5 @@ r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; - else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) + else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) r_alloc_trt_fsm = ALLOC_TRT_CONFIG; @@ -9369,5 +9365,5 @@ r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; - else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) + else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) r_alloc_trt_fsm = ALLOC_TRT_CONFIG; @@ -9404,5 +9400,5 @@ (r_ixr_rsp_fsm.read() != IXR_RSP_TRT_READ)) { - if( r_config_fsm.read() == CONFIG_TRT_LOCK ) + if( r_config_fsm.read() == CONFIG_TRT_LOCK ) r_alloc_trt_fsm = ALLOC_TRT_CONFIG; @@ -9506,5 +9502,5 @@ r_alloc_trt_fsm = ALLOC_TRT_IXR_RSP; - else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) + else if( r_config_fsm.read() == CONFIG_TRT_LOCK ) r_alloc_trt_fsm = ALLOC_TRT_CONFIG; } @@ -9698,13 +9694,13 @@ ///////////////////////////////////////////////////////////////////// - m_cmd_read_addr_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, + m_cmd_read_addr_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, p_vci_tgt.address.read() ); - m_cmd_read_length_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, + m_cmd_read_length_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, p_vci_tgt.plen.read()>>2 ); - m_cmd_read_srcid_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, + m_cmd_read_srcid_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, p_vci_tgt.srcid.read() ); - m_cmd_read_trdid_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, + m_cmd_read_trdid_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, p_vci_tgt.trdid.read() ); - m_cmd_read_pktid_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, + m_cmd_read_pktid_fifo.update( cmd_read_fifo_get, cmd_read_fifo_put, p_vci_tgt.pktid.read() ); @@ -9773,5 +9769,5 @@ m_cc_receive_to_multi_ack_fifo.update( cc_receive_to_multi_ack_fifo_get, - cc_receive_to_multi_ack_fifo_put, + cc_receive_to_multi_ack_fifo_put, p_dspin_p2m.data.read() ); @@ -9817,10 +9813,10 @@ // The three sources of (increment / decrement) are CONFIG / CLEANUP / IXR_RSP FSMs //////////////////////////////////////////////////////////////////////////////////// - if ( config_rsp_lines_incr and not + if ( config_rsp_lines_incr and not (config_rsp_lines_cleanup_decr or config_rsp_lines_ixr_rsp_decr) ) { r_config_rsp_lines = r_config_rsp_lines.read() + 1; } - if ( not config_rsp_lines_incr and + if ( not config_rsp_lines_incr and (config_rsp_lines_cleanup_decr or config_rsp_lines_ixr_rsp_decr) ) { @@ -9830,5 +9826,5 @@ //////////////////////////////////////////////////////////////////////////////////// // Update min m_cpt_heap_min_slot_available. - // The four sources of (increment / decrement) are READ / CLEANUP / XRAM_RSP / CONFIG FSMs + // The four sources of (increment / decrement) are READ / CLEANUP / XRAM_RSP / CONFIG FSMs //////////////////////////////////////////////////////////////////////////////////// assert((m_cpt_heap_slot_available <= m_heap_size) and "m_cpt_heap_slot_available > m_heap_size"); @@ -9868,11 +9864,11 @@ // DATA width is 8 bytes // The following values are not transmitted to XRAM - // p_vci_ixr.be - // p_vci_ixr.pktid - // p_vci_ixr.cons - // p_vci_ixr.wrap - // p_vci_ixr.contig - // p_vci_ixr.clen - // p_vci_ixr.cfixed + // p_vci_ixr.be + // p_vci_ixr.pktid + // p_vci_ixr.cons + // p_vci_ixr.wrap + // p_vci_ixr.contig + // p_vci_ixr.clen + // p_vci_ixr.cfixed p_vci_ixr.plen = 64; @@ -9880,5 +9876,5 @@ p_vci_ixr.trdid = r_ixr_cmd_trdid.read(); p_vci_ixr.address = (addr_t)r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2); - p_vci_ixr.be = 0xFF; + p_vci_ixr.be = 0xFF; p_vci_ixr.pktid = 0; p_vci_ixr.cons = false; @@ -9916,5 +9912,5 @@ p_vci_ixr.cmdval = true; p_vci_ixr.address = (addr_t)r_ixr_cmd_address.read() + (r_ixr_cmd_word.read()<<2); - p_vci_ixr.wdata = ((wide_data_t)(r_ixr_cmd_wdata[r_ixr_cmd_word.read()].read()) | + p_vci_ixr.wdata = ((wide_data_t)(r_ixr_cmd_wdata[r_ixr_cmd_word.read()].read()) | ((wide_data_t)(r_ixr_cmd_wdata[r_ixr_cmd_word.read() + 1].read()) << 32)); p_vci_ixr.trdid = r_cleanup_to_ixr_cmd_index.read(); @@ -9933,5 +9929,5 @@ if( (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_READ) or (r_ixr_rsp_fsm.read() == IXR_RSP_TRT_ERASE) ) - { + { p_vci_ixr.rspack = (r_alloc_trt_fsm.read() == ALLOC_TRT_IXR_RSP); } @@ -10109,10 +10105,10 @@ p_vci_tgt.rspval = true; - if( is_ll and not r_tgt_rsp_key_sent.read() ) + if( is_ll and not r_tgt_rsp_key_sent.read() ) { // LL response first flit p_vci_tgt.rdata = r_xram_rsp_to_tgt_rsp_ll_key.read(); } - else + else { // LL response second flit or READ response @@ -10275,5 +10271,5 @@ m_broadcast_boundaries, DspinRwtParam::BROADCAST_BOX); - + DspinRwtParam::dspin_set( flit, 1,