Changeset 816 for trunk/modules
- Timestamp:
- Sep 26, 2014, 2:47:09 PM (10 years ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
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trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r809 r816 132 132 const char * vci_pktid_type_str[] = { 133 133 "TYPE_DATA_UNC", 134 "TYPE_READ_DATA_MISS", 135 "TYPE_READ_INS_UNC", 134 "TYPE_READ_DATA_MISS", 135 "TYPE_READ_INS_UNC", 136 136 "TYPE_READ_INS_MISS", 137 137 "TYPE_WRITE", … … 359 359 r_dcache_cleanup_victim_req("r_dcache_cleanup_victim_req"), 360 360 r_dcache_cleanup_victim_nline("r_dcache_cleanup_victim_nline"), 361 361 362 362 r_dcache_cc_send_req("r_dcache_cc_send_req"), 363 363 r_dcache_cc_send_type("r_dcache_cc_send_type"), … … 567 567 std::cout << "Monitor PROC " << name() 568 568 << " DCACHE at cycle " << std::dec << m_cpt_total_cycles 569 << " / HIT = " << cache_hit 569 << " / HIT = " << cache_hit 570 570 << " / PADDR = " << std::hex << addr 571 << " / DATA = " << cache_rdata 571 << " / DATA = " << cache_rdata 572 572 << " / WAY = " << cache_way << std::endl; 573 573 m_debug_previous_d_hit = cache_hit; … … 584 584 std::cout << "Monitor PROC " << name() 585 585 << " ICACHE at cycle " << std::dec << m_cpt_total_cycles 586 << " / HIT = " << cache_hit 586 << " / HIT = " << cache_hit 587 587 << " / PADDR = " << std::hex << addr 588 << " / DATA = " << cache_rdata 588 << " / DATA = " << cache_rdata 589 589 << " / WAY = " << cache_way << std::endl; 590 590 m_debug_previous_i_hit = cache_hit; … … 1115 1115 else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_INST_PADDR_EXT) 1116 1116 { 1117 r_icache_paddr_ext = r_dcache_save_wdata.read(); 1117 r_icache_paddr_ext = r_dcache_save_wdata.read(); 1118 1118 r_dcache_xtn_req = false; 1119 1119 } … … 1208 1208 #if DEBUG_ICACHE 1209 1209 if ( m_debug_icache_fsm ) 1210 std::cout << " <PROC " << name() << " ICACHE_IDLE> MMU Privilege Violation" 1210 std::cout << " <PROC " << name() << " ICACHE_IDLE> MMU Privilege Violation" 1211 1211 << " : PADDR = " << std::hex << paddr << std::endl; 1212 1212 #endif … … 1223 1223 #if DEBUG_ICACHE 1224 1224 if ( m_debug_icache_fsm ) 1225 std::cout << " <PROC " << name() << " ICACHE_IDLE> MMU Executable Violation" 1225 std::cout << " <PROC " << name() << " ICACHE_IDLE> MMU Executable Violation" 1226 1226 << " : PADDR = " << std::hex << paddr << std::endl; 1227 1227 #endif … … 1262 1262 #if DEBUG_ICACHE 1263 1263 if (m_debug_icache_fsm) 1264 std::cout << " <PROC " << name() << " ICACHE_IDLE> READ MISS in icache" 1264 std::cout << " <PROC " << name() << " ICACHE_IDLE> READ MISS in icache" 1265 1265 << " : PADDR = " << std::hex << paddr << std::endl; 1266 1266 #endif … … 1284 1284 #if DEBUG_ICACHE 1285 1285 if (m_debug_icache_fsm) 1286 std::cout << " <PROC " << name() << " ICACHE_IDLE> READ HIT in icache" 1286 std::cout << " <PROC " << name() << " ICACHE_IDLE> READ HIT in icache" 1287 1287 << " : PADDR = " << std::hex << paddr 1288 1288 << " / INST = " << cache_inst << std::endl; … … 1299 1299 { 1300 1300 std::cout << " <PROC " << name() 1301 << " ICACHE_IDLE> READ UNCACHEABLE in icache" 1301 << " ICACHE_IDLE> READ UNCACHEABLE in icache" 1302 1302 << " : PADDR = " << std::hex << paddr << std::endl; 1303 1303 } … … 1566 1566 case ICACHE_MISS_SELECT: // Try to select a slot in associative set, 1567 1567 // Waiting in this state if no slot available. 1568 // If a victim slot has been choosen and the r_icache_cc_send_req is false, 1569 // we send the cleanup request in this state. 1568 // If a victim slot has been choosen and the r_icache_cc_send_req is false, 1569 // we send the cleanup request in this state. 1570 1570 // If not, a r_icache_cleanup_victim_req flip-flop is 1571 1571 // utilized for saving this cleanup request, and it will be sent later 1572 // in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR. 1572 // in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR. 1573 1573 // The r_icache_miss_clack flip-flop is set 1574 1574 // when a cleanup is required … … 1624 1624 r_icache_cc_send_nline = victim; 1625 1625 r_icache_cc_send_way = way; 1626 r_icache_cc_send_type = CC_TYPE_CLEANUP; 1626 r_icache_cc_send_type = CC_TYPE_CLEANUP; 1627 1627 } 1628 1628 else … … 1689 1689 r_icache_cc_send_nline = r_icache_cleanup_victim_nline; 1690 1690 r_icache_cc_send_way = r_icache_miss_way; 1691 r_icache_cc_send_type = CC_TYPE_CLEANUP; 1691 r_icache_cc_send_type = CC_TYPE_CLEANUP; 1692 1692 r_icache_cleanup_victim_req = false; 1693 } 1693 } 1694 1694 1695 1695 // coherence clack interrupt … … 1700 1700 break; 1701 1701 } 1702 1702 1703 1703 // coherence interrupt 1704 1704 if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read()) … … 1778 1778 r_icache_cc_send_nline = r_icache_cleanup_victim_nline; 1779 1779 r_icache_cc_send_way = r_icache_miss_way; 1780 r_icache_cc_send_type = CC_TYPE_CLEANUP; 1780 r_icache_cc_send_type = CC_TYPE_CLEANUP; 1781 1781 r_icache_cleanup_victim_req = false; 1782 } 1782 } 1783 1783 1784 1784 // coherence clack interrupt … … 2051 2051 #endif 2052 2052 2053 // Switch slot state to ZOMBI and send CLEANUP command 2053 // Switch slot state to ZOMBI and send CLEANUP command 2054 2054 r_icache.write_dir(r_icache_cc_way.read(), 2055 2055 r_icache_cc_set.read(), … … 2200 2200 // 6/ Error handling: 2201 2201 // When the MMU is not activated, Read Bus Errors are synchronous events, 2202 // Some Write Bus Errors are synchronous events when the request is a non cacheable access 2203 // but some Write Bus Errors are asynchronous events when the request is cacheable access 2202 // Some Write Bus Errors are synchronous events when the request is a non cacheable access 2203 // but some Write Bus Errors are asynchronous events when the request is cacheable access 2204 2204 // (processor is not frozen). 2205 2205 // - If a Read Bus Error or a Non Cacheable Write Bus Error is detected, the VCI_RSP FSM sets the … … 2207 2207 // r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled 2208 2208 // by the DCACHE FSM. 2209 // - If a Cacheable Write Bus Error is detected, the VCI_RSP_FSM signals 2209 // - If a Cacheable Write Bus Error is detected, the VCI_RSP_FSM signals 2210 2210 // the asynchronous error using the setWriteBerr() method. 2211 2211 // When the MMU is activated bus error are rare events, as the MMU … … 2228 2228 // 6) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE 2229 2229 // 7) Cacheable read miss (processor) => DCACHE_MISS_SELECT 2230 // 8) Uncacheable read (processor)=> DCACHE_UNC_WAIT2230 // 8) Uncacheable read/write (processor)=> DCACHE_UNC_WAIT 2231 2231 // 9) LL access (processor) => DCACHE_LL_WAIT 2232 2232 // 10) SC access (processor) => DCACHE_SC_WAIT … … 2291 2291 { 2292 2292 // we take into account the paddr extension 2293 if (vci_param::N > 32) 2293 if (vci_param::N > 32) 2294 2294 paddr = paddr | ((paddr_t) (r_dcache_paddr_ext.read()) << 32); 2295 2295 } … … 2789 2789 if (m_debug_dcache_fsm) 2790 2790 std::cout << " <PROC " << name() << " DCACHE_IDLE>" 2791 << " READ MISS in dcache" 2791 << " READ MISS in dcache" 2792 2792 << " / PADDR = " << std::hex << paddr << std::endl; 2793 2793 #endif … … 2816 2816 if (m_debug_dcache_fsm) 2817 2817 std::cout << " <PROC " << name() << " DCACHE_IDLE>" 2818 << " READ HIT in dcache" 2819 << " : PADDR = " << std::hex << paddr 2818 << " READ HIT in dcache" 2819 << " : PADDR = " << std::hex << paddr 2820 2820 << " / DATA = " << std::hex << cache_rdata << std::endl; 2821 2821 #endif … … 2832 2832 if (m_debug_dcache_fsm) 2833 2833 std::cout << " <PROC " << name() << " DCACHE_IDLE>" 2834 << " READ UNCACHEABLE in dcache" 2834 << " READ UNCACHEABLE in dcache" 2835 2835 << " / PADDR = " << std::hex << paddr << std::endl; 2836 2836 #endif … … 2892 2892 r_dcache_llsc_valid = false; 2893 2893 2894 if (not cacheable) 2895 { 2894 if (not cacheable) // uncacheable write 2895 { 2896 2896 r_dcache_vci_paddr = paddr; 2897 2897 r_dcache_vci_wdata = m_dreq.wdata; … … 3100 3100 if (m_debug_dcache_fsm) 3101 3101 { 3102 std::cout << " <PROC " << name() 3102 std::cout << " <PROC " << name() 3103 3103 << " DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped" 3104 3104 << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() … … 3137 3137 if (m_debug_dcache_fsm) 3138 3138 { 3139 std::cout << " <PROC " << name() 3139 std::cout << " <PROC " << name() 3140 3140 << " DCACHE_TLB_PTE1_GET> HIT in dcache" 3141 3141 << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() … … 3159 3159 if (m_debug_dcache_fsm) 3160 3160 { 3161 std::cout << " <PROC " << name() 3161 std::cout << " <PROC " << name() 3162 3162 << " DCACHE_TLB_PTE1_GET> HIT in dcache" 3163 3163 << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() … … 3186 3186 if (m_debug_dcache_fsm) 3187 3187 { 3188 std::cout << " <PROC " << name() 3188 std::cout << " <PROC " << name() 3189 3189 << " DCACHE_TLB_PTE1_GET> MISS in dcache:" 3190 3190 << " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl; … … 3228 3228 { 3229 3229 if (r_dcache_tlb_ins.read()) 3230 std::cout << " <PROC " << name() 3230 std::cout << " <PROC " << name() 3231 3231 << " DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:"; 3232 3232 else 3233 std::cout << " <PROC " << name() 3233 std::cout << " <PROC " << name() 3234 3234 << ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:"; 3235 3235 std::cout << " way = " << std::dec << way … … 3299 3299 if (m_debug_dcache_fsm) 3300 3300 { 3301 std::cout << " <PROC " << name() 3301 std::cout << " <PROC " << name() 3302 3302 << " DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB" 3303 3303 << " / set = " << std::dec << r_dcache_tlb_set.read() … … 3323 3323 if (m_debug_dcache_fsm) 3324 3324 { 3325 std::cout << " <PROC " << name() 3325 std::cout << " <PROC " << name() 3326 3326 << " DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB" 3327 3327 << " / set = " << std::dec << r_dcache_tlb_set.read() … … 3340 3340 if (m_debug_dcache_fsm) 3341 3341 { 3342 std::cout << " <PROC " << name() 3342 std::cout << " <PROC " << name() 3343 3343 << " DCACHE_TLB_PTE1_UPDT> L/R bit update required" 3344 3344 << std::endl; … … 3428 3428 if (m_debug_dcache_fsm) 3429 3429 { 3430 std::cout << " <PROC " << name() 3430 std::cout << " <PROC " << name() 3431 3431 << " DCACHE_TLB_PTE2_GET> HIT in dcache:" 3432 3432 << " PTE_FLAGS = " << std::hex << pte_flags … … 3444 3444 if (m_debug_dcache_fsm) 3445 3445 { 3446 std::cout << " <PROC " << name() 3446 std::cout << " <PROC " << name() 3447 3447 << " DCACHE_TLB_PTE2_GET> ZOMBI in dcache: waiting cleanup ack" 3448 3448 << std::endl; … … 3946 3946 { 3947 3947 paddr = (paddr_t)r_dcache_save_wdata.read(); 3948 if (vci_param::N > 32) 3948 if (vci_param::N > 32) 3949 3949 paddr = paddr | ((paddr_t)(r_dcache_paddr_ext.read()) << 32); 3950 3950 hit = true; … … 4091 4091 case DCACHE_MISS_SELECT: // Try to select a slot in associative set, 4092 4092 // Waiting in this state if no slot available. 4093 // If a victim slot has been choosen and the r_icache_cc_send_req is false, 4094 // we send the cleanup request in this state. 4093 // If a victim slot has been choosen and the r_icache_cc_send_req is false, 4094 // we send the cleanup request in this state. 4095 4095 // If not, a r_icache_cleanup_victim_req flip-flop is 4096 4096 // utilized for saving this cleanup request, and it will be sent later 4097 // in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR. 4097 // in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR. 4098 4098 // The r_icache_miss_clack flip-flop is set 4099 4099 // when a cleanup is required … … 4149 4149 r_dcache_cc_send_nline = victim; 4150 4150 r_dcache_cc_send_way = way; 4151 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 4151 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 4152 4152 4153 4153 } … … 4246 4246 r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline; 4247 4247 r_dcache_cc_send_way = r_dcache_miss_way; 4248 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 4248 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 4249 4249 r_dcache_cleanup_victim_req = false; 4250 } 4250 } 4251 4251 4252 4252 // coherence clack request (from DSPIN CLACK) … … 4259 4259 4260 4260 // coherence request (from CC_RECEIVE FSM) 4261 if (r_cc_receive_dcache_req.read() and 4262 not r_dcache_cc_send_req.read() and 4261 if (r_cc_receive_dcache_req.read() and 4262 not r_dcache_cc_send_req.read() and 4263 4263 not r_dcache_cleanup_victim_req.read()) 4264 4264 { … … 4381 4381 r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline; 4382 4382 r_dcache_cc_send_way = r_dcache_miss_way; 4383 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 4383 r_dcache_cc_send_type = CC_TYPE_CLEANUP; 4384 4384 r_dcache_cleanup_victim_req = false; 4385 } 4385 } 4386 4386 4387 4387 // coherence clack request (from DSPIN CLACK) … … 4394 4394 4395 4395 // coherence request (from CC_RECEIVE FSM) 4396 if (r_cc_receive_dcache_req.read() and 4397 not r_dcache_cc_send_req.read() and 4396 if (r_cc_receive_dcache_req.read() and 4397 not r_dcache_cc_send_req.read() and 4398 4398 not r_dcache_cleanup_victim_req.read()) 4399 4399 { … … 4467 4467 } 4468 4468 ///////////////////// 4469 case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read 4469 case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read/write 4470 4470 { 4471 4471 // coherence clack request (from DSPIN CLACK) … … 4491 4491 else 4492 4492 r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; 4493 4493 4494 4494 r_mmu_dbvar = m_dreq.addr; 4495 4495 r_vci_rsp_data_error = false; … … 4760 4760 } 4761 4761 4762 assert ( not r_dcache_cc_send_req.read() and 4762 assert ( not r_dcache_cc_send_req.read() and 4763 4763 "CC_SEND must be available in DCACHE_CC_CHECK" ); 4764 4764 4765 4765 // Match between MISS address and CC address 4766 if (r_cc_receive_dcache_req.read() and 4766 if (r_cc_receive_dcache_req.read() and 4767 4767 ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT) or 4768 4768 (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or … … 4801 4801 4802 4802 // CC request handler 4803 4803 4804 4804 int state = 0; 4805 4805 size_t way = 0; … … 4901 4901 "must not be set"); 4902 4902 4903 // Switch slot state to ZOMBI and send CLEANUP command 4903 // Switch slot state to ZOMBI and send CLEANUP command 4904 4904 r_dcache.write_dir(way, 4905 4905 set, … … 4962 4962 "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req " 4963 4963 "must not be set"); 4964 4964 4965 4965 if (not r_cc_receive_updt_fifo_be.rok()) break; 4966 4966 4967 4967 if (r_dcache_cc_need_write.read()) 4968 4968 { 4969 4969 4970 4970 #ifdef INSTRUMENTATION 4971 4971 m_cpt_dcache_data_write++; … … 5408 5408 { 5409 5409 std::cout << "ERROR in VCI_CC_VCACHE " << name() 5410 << " VCI response packet too short" 5410 << " VCI response packet too short" 5411 5411 << " for instruction miss" << std::endl; 5412 5412 exit(0); … … 5591 5591 { 5592 5592 // the new client is dcache and has a cleanup request 5593 if ((update_last_client == 0) and 5593 if ((update_last_client == 0) and 5594 5594 (r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP)) 5595 5595 r_cc_send_fsm = CC_SEND_CLEANUP_1; 5596 5596 // the new client is dcache and has a multi acknowledgement request 5597 else if ((update_last_client == 0) and 5597 else if ((update_last_client == 0) and 5598 5598 (r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK)) 5599 5599 r_cc_send_fsm = CC_SEND_MULTI_ACK; 5600 5600 // the new client is icache and has a cleanup request 5601 else if ((update_last_client == 1) and 5601 else if ((update_last_client == 1) and 5602 5602 (r_icache_cc_send_type.read() == CC_TYPE_CLEANUP)) 5603 5603 r_cc_send_fsm = CC_SEND_CLEANUP_1; … … 5680 5680 } 5681 5681 // test for a multi updt 5682 else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA) 5682 else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA) 5683 5683 { 5684 5684 r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_HEADER; … … 5716 5716 // not to actually post a request to an available cache => need a 5717 5717 // flip_flop to check that ? 5718 if (not (r_cc_receive_icache_req.read()) and 5718 if (not (r_cc_receive_icache_req.read()) and 5719 5719 not (r_cc_receive_dcache_req.read()) and 5720 5720 (p_dspin_m2p.write.read())) … … 5757 5757 uint64_t receive_data = p_dspin_m2p.data.read(); 5758 5758 // for data INVAL, wait for dcache to take the request 5759 if (p_dspin_m2p.write.read() and 5759 if (p_dspin_m2p.write.read() and 5760 5760 not r_cc_receive_dcache_req.read()) 5761 5761 { … … 5776 5776 uint64_t receive_data = p_dspin_m2p.data.read(); 5777 5777 // for ins INVAL, wait for icache to take the request 5778 if (p_dspin_m2p.write.read() and 5778 if (p_dspin_m2p.write.read() and 5779 5779 not r_cc_receive_icache_req.read()) 5780 5780 { … … 5896 5896 5897 5897 ///////////////// DSPIN CLACK interface /////////////// 5898 5898 5899 5899 uint64_t clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), 5900 5900 DspinDhccpParam::CLACK_TYPE); … … 5977 5977 p_vci.pktid = 0; 5978 5978 p_vci.srcid = m_srcid; 5979 p_vci.cons = is_sc_or_cas; 5980 p_vci.contig = not is_sc_or_cas; 5979 p_vci.cons = is_sc_or_cas; 5980 p_vci.contig = not is_sc_or_cas; 5981 5981 p_vci.wrap = false; 5982 5982 p_vci.clen = 0; … … 5985 5985 if (m_monitor_ok) { 5986 5986 if (p_vci.cmdack.read() == true and p_vci.cmdval == true) { 5987 if (((p_vci.address.read()) >= m_monitor_base) and 5987 if (((p_vci.address.read()) >= m_monitor_base) and 5988 5988 ((p_vci.address.read()) < m_monitor_base + m_monitor_length)) { 5989 5989 std::cout << "CC_VCACHE Monitor " << name() << std::hex 5990 << " Access type = " << vci_cmd_type_str[p_vci.cmd.read()] 5990 << " Access type = " << vci_cmd_type_str[p_vci.cmd.read()] 5991 5991 << " Pktid type = " << vci_pktid_type_str[p_vci.pktid.read()] 5992 5992 << " : address = " << p_vci.address.read() 5993 << " / be = " << p_vci.be.read(); 5993 << " / be = " << p_vci.be.read(); 5994 5994 if (p_vci.cmd.read() == vci_param::CMD_WRITE ) { 5995 5995 std::cout << " / data = " << p_vci.wdata.read(); … … 6139 6139 } // end switch r_vci_rsp_fsm 6140 6140 6141 6142 // Send coherence packets on DSPIN P2M 6143 // it depends on the CC_SEND FSM 6141 6142 // Send coherence packets on DSPIN P2M 6143 // it depends on the CC_SEND FSM 6144 6144 6145 6145 uint64_t dspin_send_data = 0; … … 6165 6165 if (r_cc_send_last_client.read() == 0) // dcache active request 6166 6166 { 6167 uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read() 6168 >> (m_nline_width - m_x_width - m_y_width) 6167 uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read() 6168 >> (m_nline_width - m_x_width - m_y_width) 6169 6169 << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); 6170 6170 6171 6171 DspinDhccpParam::dspin_set(dspin_send_data, 6172 6172 dest, … … 6187 6187 else // icache active request 6188 6188 { 6189 uint64_t dest = (uint64_t) r_icache_cc_send_nline.read() 6190 >> (m_nline_width - m_x_width - m_y_width) 6189 uint64_t dest = (uint64_t) r_icache_cc_send_nline.read() 6190 >> (m_nline_width - m_x_width - m_y_width) 6191 6191 << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); 6192 6192 … … 6249 6249 if (r_cc_send_last_client.read() == 0) // dcache active request 6250 6250 { 6251 uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read() 6252 >> (m_nline_width - m_x_width - m_y_width) 6251 uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read() 6252 >> (m_nline_width - m_x_width - m_y_width) 6253 6253 << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); 6254 6254 6255 6255 DspinDhccpParam::dspin_set(dspin_send_data, 6256 6256 dest, … … 6263 6263 else // icache active request 6264 6264 { 6265 uint64_t dest = (uint64_t) r_icache_cc_send_nline.read() 6266 >> (m_nline_width - m_x_width - m_y_width) 6265 uint64_t dest = (uint64_t) r_icache_cc_send_nline.read() 6266 >> (m_nline_width - m_x_width - m_y_width) 6267 6267 << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); 6268 6268 6269 6269 6270 6270 DspinDhccpParam::dspin_set(dspin_send_data, … … 6286 6286 6287 6287 // Receive coherence packets 6288 // It depends on the CC_RECEIVE FSM 6288 // It depends on the CC_RECEIVE FSM 6289 6289 switch (r_cc_receive_fsm.read()) 6290 6290 { … … 6343 6343 case CC_RECEIVE_INS_UPDT_HEADER: 6344 6344 { 6345 if (not r_cc_receive_icache_req.read()) 6345 if (not r_cc_receive_icache_req.read()) 6346 6346 p_dspin_m2p.read = true; 6347 6347 else … … 6398 6398 } 6399 6399 6400 p_dspin_clack.read = dspin_clack_get; 6400 p_dspin_clack.read = dspin_clack_get; 6401 6401 } // end genMoore 6402 6402
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