Index: trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp =================================================================== --- trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 815) +++ trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 816) @@ -132,6 +132,6 @@ const char * vci_pktid_type_str[] = { "TYPE_DATA_UNC", - "TYPE_READ_DATA_MISS", - "TYPE_READ_INS_UNC", + "TYPE_READ_DATA_MISS", + "TYPE_READ_INS_UNC", "TYPE_READ_INS_MISS", "TYPE_WRITE", @@ -359,5 +359,5 @@ r_dcache_cleanup_victim_req("r_dcache_cleanup_victim_req"), r_dcache_cleanup_victim_nline("r_dcache_cleanup_victim_nline"), - + r_dcache_cc_send_req("r_dcache_cc_send_req"), r_dcache_cc_send_type("r_dcache_cc_send_type"), @@ -567,7 +567,7 @@ std::cout << "Monitor PROC " << name() << " DCACHE at cycle " << std::dec << m_cpt_total_cycles - << " / HIT = " << cache_hit + << " / HIT = " << cache_hit << " / PADDR = " << std::hex << addr - << " / DATA = " << cache_rdata + << " / DATA = " << cache_rdata << " / WAY = " << cache_way << std::endl; m_debug_previous_d_hit = cache_hit; @@ -584,7 +584,7 @@ std::cout << "Monitor PROC " << name() << " ICACHE at cycle " << std::dec << m_cpt_total_cycles - << " / HIT = " << cache_hit + << " / HIT = " << cache_hit << " / PADDR = " << std::hex << addr - << " / DATA = " << cache_rdata + << " / DATA = " << cache_rdata << " / WAY = " << cache_way << std::endl; m_debug_previous_i_hit = cache_hit; @@ -1115,5 +1115,5 @@ else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_INST_PADDR_EXT) { - r_icache_paddr_ext = r_dcache_save_wdata.read(); + r_icache_paddr_ext = r_dcache_save_wdata.read(); r_dcache_xtn_req = false; } @@ -1208,5 +1208,5 @@ #if DEBUG_ICACHE if ( m_debug_icache_fsm ) -std::cout << " MMU Privilege Violation" +std::cout << " MMU Privilege Violation" << " : PADDR = " << std::hex << paddr << std::endl; #endif @@ -1223,5 +1223,5 @@ #if DEBUG_ICACHE if ( m_debug_icache_fsm ) -std::cout << " MMU Executable Violation" +std::cout << " MMU Executable Violation" << " : PADDR = " << std::hex << paddr << std::endl; #endif @@ -1262,5 +1262,5 @@ #if DEBUG_ICACHE if (m_debug_icache_fsm) - std::cout << " READ MISS in icache" + std::cout << " READ MISS in icache" << " : PADDR = " << std::hex << paddr << std::endl; #endif @@ -1284,5 +1284,5 @@ #if DEBUG_ICACHE if (m_debug_icache_fsm) - std::cout << " READ HIT in icache" + std::cout << " READ HIT in icache" << " : PADDR = " << std::hex << paddr << " / INST = " << cache_inst << std::endl; @@ -1299,5 +1299,5 @@ { std::cout << " READ UNCACHEABLE in icache" + << " ICACHE_IDLE> READ UNCACHEABLE in icache" << " : PADDR = " << std::hex << paddr << std::endl; } @@ -1566,9 +1566,9 @@ case ICACHE_MISS_SELECT: // Try to select a slot in associative set, // Waiting in this state if no slot available. - // If a victim slot has been choosen and the r_icache_cc_send_req is false, - // we send the cleanup request in this state. + // If a victim slot has been choosen and the r_icache_cc_send_req is false, + // we send the cleanup request in this state. // If not, a r_icache_cleanup_victim_req flip-flop is // utilized for saving this cleanup request, and it will be sent later - // in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR. + // in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR. // The r_icache_miss_clack flip-flop is set // when a cleanup is required @@ -1624,5 +1624,5 @@ r_icache_cc_send_nline = victim; r_icache_cc_send_way = way; - r_icache_cc_send_type = CC_TYPE_CLEANUP; + r_icache_cc_send_type = CC_TYPE_CLEANUP; } else @@ -1689,7 +1689,7 @@ r_icache_cc_send_nline = r_icache_cleanup_victim_nline; r_icache_cc_send_way = r_icache_miss_way; - r_icache_cc_send_type = CC_TYPE_CLEANUP; + r_icache_cc_send_type = CC_TYPE_CLEANUP; r_icache_cleanup_victim_req = false; - } + } // coherence clack interrupt @@ -1700,5 +1700,5 @@ break; } - + // coherence interrupt if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read()) @@ -1778,7 +1778,7 @@ r_icache_cc_send_nline = r_icache_cleanup_victim_nline; r_icache_cc_send_way = r_icache_miss_way; - r_icache_cc_send_type = CC_TYPE_CLEANUP; + r_icache_cc_send_type = CC_TYPE_CLEANUP; r_icache_cleanup_victim_req = false; - } + } // coherence clack interrupt @@ -2051,5 +2051,5 @@ #endif - // Switch slot state to ZOMBI and send CLEANUP command + // Switch slot state to ZOMBI and send CLEANUP command r_icache.write_dir(r_icache_cc_way.read(), r_icache_cc_set.read(), @@ -2200,6 +2200,6 @@ // 6/ Error handling: // When the MMU is not activated, Read Bus Errors are synchronous events, - // Some Write Bus Errors are synchronous events when the request is a non cacheable access - // but some Write Bus Errors are asynchronous events when the request is cacheable access + // Some Write Bus Errors are synchronous events when the request is a non cacheable access + // but some Write Bus Errors are asynchronous events when the request is cacheable access // (processor is not frozen). // - If a Read Bus Error or a Non Cacheable Write Bus Error is detected, the VCI_RSP FSM sets the @@ -2207,5 +2207,5 @@ // r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled // by the DCACHE FSM. - // - If a Cacheable Write Bus Error is detected, the VCI_RSP_FSM signals + // - If a Cacheable Write Bus Error is detected, the VCI_RSP_FSM signals // the asynchronous error using the setWriteBerr() method. // When the MMU is activated bus error are rare events, as the MMU @@ -2228,5 +2228,5 @@ // 6) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE // 7) Cacheable read miss (processor) => DCACHE_MISS_SELECT - // 8) Uncacheable read (processor) => DCACHE_UNC_WAIT + // 8) Uncacheable read/write (processor)=> DCACHE_UNC_WAIT // 9) LL access (processor) => DCACHE_LL_WAIT // 10) SC access (processor) => DCACHE_SC_WAIT @@ -2291,5 +2291,5 @@ { // we take into account the paddr extension - if (vci_param::N > 32) + if (vci_param::N > 32) paddr = paddr | ((paddr_t) (r_dcache_paddr_ext.read()) << 32); } @@ -2789,5 +2789,5 @@ if (m_debug_dcache_fsm) std::cout << " " - << " READ MISS in dcache" + << " READ MISS in dcache" << " / PADDR = " << std::hex << paddr << std::endl; #endif @@ -2816,6 +2816,6 @@ if (m_debug_dcache_fsm) std::cout << " " - << " READ HIT in dcache" - << " : PADDR = " << std::hex << paddr + << " READ HIT in dcache" + << " : PADDR = " << std::hex << paddr << " / DATA = " << std::hex << cache_rdata << std::endl; #endif @@ -2832,5 +2832,5 @@ if (m_debug_dcache_fsm) std::cout << " " - << " READ UNCACHEABLE in dcache" + << " READ UNCACHEABLE in dcache" << " / PADDR = " << std::hex << paddr << std::endl; #endif @@ -2892,6 +2892,6 @@ r_dcache_llsc_valid = false; - if (not cacheable) - { + if (not cacheable) // uncacheable write + { r_dcache_vci_paddr = paddr; r_dcache_vci_wdata = m_dreq.wdata; @@ -3100,5 +3100,5 @@ if (m_debug_dcache_fsm) { - std::cout << " HIT in dcache, but unmapped" << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() @@ -3137,5 +3137,5 @@ if (m_debug_dcache_fsm) { - std::cout << " HIT in dcache" << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() @@ -3159,5 +3159,5 @@ if (m_debug_dcache_fsm) { - std::cout << " HIT in dcache" << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() @@ -3186,5 +3186,5 @@ if (m_debug_dcache_fsm) { - std::cout << " MISS in dcache:" << " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl; @@ -3228,8 +3228,8 @@ { if (r_dcache_tlb_ins.read()) - std::cout << " Select a slot in ITLB:"; else - std::cout << " Select a slot in DTLB:"; std::cout << " way = " << std::dec << way @@ -3299,5 +3299,5 @@ if (m_debug_dcache_fsm) { - std::cout << " write PTE1 in ITLB" << " / set = " << std::dec << r_dcache_tlb_set.read() @@ -3323,5 +3323,5 @@ if (m_debug_dcache_fsm) { - std::cout << " write PTE1 in DTLB" << " / set = " << std::dec << r_dcache_tlb_set.read() @@ -3340,5 +3340,5 @@ if (m_debug_dcache_fsm) { - std::cout << " L/R bit update required" << std::endl; @@ -3428,5 +3428,5 @@ if (m_debug_dcache_fsm) { - std::cout << " HIT in dcache:" << " PTE_FLAGS = " << std::hex << pte_flags @@ -3444,5 +3444,5 @@ if (m_debug_dcache_fsm) { - std::cout << " ZOMBI in dcache: waiting cleanup ack" << std::endl; @@ -3946,5 +3946,5 @@ { paddr = (paddr_t)r_dcache_save_wdata.read(); - if (vci_param::N > 32) + if (vci_param::N > 32) paddr = paddr | ((paddr_t)(r_dcache_paddr_ext.read()) << 32); hit = true; @@ -4091,9 +4091,9 @@ case DCACHE_MISS_SELECT: // Try to select a slot in associative set, // Waiting in this state if no slot available. - // If a victim slot has been choosen and the r_icache_cc_send_req is false, - // we send the cleanup request in this state. + // If a victim slot has been choosen and the r_icache_cc_send_req is false, + // we send the cleanup request in this state. // If not, a r_icache_cleanup_victim_req flip-flop is // utilized for saving this cleanup request, and it will be sent later - // in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR. + // in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR. // The r_icache_miss_clack flip-flop is set // when a cleanup is required @@ -4149,5 +4149,5 @@ r_dcache_cc_send_nline = victim; r_dcache_cc_send_way = way; - r_dcache_cc_send_type = CC_TYPE_CLEANUP; + r_dcache_cc_send_type = CC_TYPE_CLEANUP; } @@ -4246,7 +4246,7 @@ r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline; r_dcache_cc_send_way = r_dcache_miss_way; - r_dcache_cc_send_type = CC_TYPE_CLEANUP; + r_dcache_cc_send_type = CC_TYPE_CLEANUP; r_dcache_cleanup_victim_req = false; - } + } // coherence clack request (from DSPIN CLACK) @@ -4259,6 +4259,6 @@ // coherence request (from CC_RECEIVE FSM) - if (r_cc_receive_dcache_req.read() and - not r_dcache_cc_send_req.read() and + if (r_cc_receive_dcache_req.read() and + not r_dcache_cc_send_req.read() and not r_dcache_cleanup_victim_req.read()) { @@ -4381,7 +4381,7 @@ r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline; r_dcache_cc_send_way = r_dcache_miss_way; - r_dcache_cc_send_type = CC_TYPE_CLEANUP; + r_dcache_cc_send_type = CC_TYPE_CLEANUP; r_dcache_cleanup_victim_req = false; - } + } // coherence clack request (from DSPIN CLACK) @@ -4394,6 +4394,6 @@ // coherence request (from CC_RECEIVE FSM) - if (r_cc_receive_dcache_req.read() and - not r_dcache_cc_send_req.read() and + if (r_cc_receive_dcache_req.read() and + not r_dcache_cc_send_req.read() and not r_dcache_cleanup_victim_req.read()) { @@ -4467,5 +4467,5 @@ } ///////////////////// - case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read + case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read/write { // coherence clack request (from DSPIN CLACK) @@ -4491,5 +4491,5 @@ else r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; - + r_mmu_dbvar = m_dreq.addr; r_vci_rsp_data_error = false; @@ -4760,9 +4760,9 @@ } - assert ( not r_dcache_cc_send_req.read() and + assert ( not r_dcache_cc_send_req.read() and "CC_SEND must be available in DCACHE_CC_CHECK" ); // Match between MISS address and CC address - if (r_cc_receive_dcache_req.read() and + if (r_cc_receive_dcache_req.read() and ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT) or (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or @@ -4801,5 +4801,5 @@ // CC request handler - + int state = 0; size_t way = 0; @@ -4901,5 +4901,5 @@ "must not be set"); - // Switch slot state to ZOMBI and send CLEANUP command + // Switch slot state to ZOMBI and send CLEANUP command r_dcache.write_dir(way, set, @@ -4962,10 +4962,10 @@ "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req " "must not be set"); - + if (not r_cc_receive_updt_fifo_be.rok()) break; if (r_dcache_cc_need_write.read()) { - + #ifdef INSTRUMENTATION m_cpt_dcache_data_write++; @@ -5408,5 +5408,5 @@ { std::cout << "ERROR in VCI_CC_VCACHE " << name() - << " VCI response packet too short" + << " VCI response packet too short" << " for instruction miss" << std::endl; exit(0); @@ -5591,13 +5591,13 @@ { // the new client is dcache and has a cleanup request - if ((update_last_client == 0) and + if ((update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP)) r_cc_send_fsm = CC_SEND_CLEANUP_1; // the new client is dcache and has a multi acknowledgement request - else if ((update_last_client == 0) and + else if ((update_last_client == 0) and (r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK)) r_cc_send_fsm = CC_SEND_MULTI_ACK; // the new client is icache and has a cleanup request - else if ((update_last_client == 1) and + else if ((update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_CLEANUP)) r_cc_send_fsm = CC_SEND_CLEANUP_1; @@ -5680,5 +5680,5 @@ } // test for a multi updt - else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA) + else if (receive_type == DspinDhccpParam::TYPE_MULTI_UPDT_DATA) { r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_HEADER; @@ -5716,5 +5716,5 @@ // not to actually post a request to an available cache => need a // flip_flop to check that ? - if (not (r_cc_receive_icache_req.read()) and + if (not (r_cc_receive_icache_req.read()) and not (r_cc_receive_dcache_req.read()) and (p_dspin_m2p.write.read())) @@ -5757,5 +5757,5 @@ uint64_t receive_data = p_dspin_m2p.data.read(); // for data INVAL, wait for dcache to take the request - if (p_dspin_m2p.write.read() and + if (p_dspin_m2p.write.read() and not r_cc_receive_dcache_req.read()) { @@ -5776,5 +5776,5 @@ uint64_t receive_data = p_dspin_m2p.data.read(); // for ins INVAL, wait for icache to take the request - if (p_dspin_m2p.write.read() and + if (p_dspin_m2p.write.read() and not r_cc_receive_icache_req.read()) { @@ -5896,5 +5896,5 @@ ///////////////// DSPIN CLACK interface /////////////// - + uint64_t clack_type = DspinDhccpParam::dspin_get(r_dspin_clack_flit.read(), DspinDhccpParam::CLACK_TYPE); @@ -5977,6 +5977,6 @@ p_vci.pktid = 0; p_vci.srcid = m_srcid; - p_vci.cons = is_sc_or_cas; - p_vci.contig = not is_sc_or_cas; + p_vci.cons = is_sc_or_cas; + p_vci.contig = not is_sc_or_cas; p_vci.wrap = false; p_vci.clen = 0; @@ -5985,11 +5985,11 @@ if (m_monitor_ok) { if (p_vci.cmdack.read() == true and p_vci.cmdval == true) { - if (((p_vci.address.read()) >= m_monitor_base) and + if (((p_vci.address.read()) >= m_monitor_base) and ((p_vci.address.read()) < m_monitor_base + m_monitor_length)) { std::cout << "CC_VCACHE Monitor " << name() << std::hex - << " Access type = " << vci_cmd_type_str[p_vci.cmd.read()] + << " Access type = " << vci_cmd_type_str[p_vci.cmd.read()] << " Pktid type = " << vci_pktid_type_str[p_vci.pktid.read()] << " : address = " << p_vci.address.read() - << " / be = " << p_vci.be.read(); + << " / be = " << p_vci.be.read(); if (p_vci.cmd.read() == vci_param::CMD_WRITE ) { std::cout << " / data = " << p_vci.wdata.read(); @@ -6139,7 +6139,7 @@ } // end switch r_vci_rsp_fsm - - // Send coherence packets on DSPIN P2M - // it depends on the CC_SEND FSM + + // Send coherence packets on DSPIN P2M + // it depends on the CC_SEND FSM uint64_t dspin_send_data = 0; @@ -6165,8 +6165,8 @@ if (r_cc_send_last_client.read() == 0) // dcache active request { - uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read() - >> (m_nline_width - m_x_width - m_y_width) + uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read() + >> (m_nline_width - m_x_width - m_y_width) << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); - + DspinDhccpParam::dspin_set(dspin_send_data, dest, @@ -6187,6 +6187,6 @@ else // icache active request { - uint64_t dest = (uint64_t) r_icache_cc_send_nline.read() - >> (m_nline_width - m_x_width - m_y_width) + uint64_t dest = (uint64_t) r_icache_cc_send_nline.read() + >> (m_nline_width - m_x_width - m_y_width) << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); @@ -6249,8 +6249,8 @@ if (r_cc_send_last_client.read() == 0) // dcache active request { - uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read() - >> (m_nline_width - m_x_width - m_y_width) + uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read() + >> (m_nline_width - m_x_width - m_y_width) << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); - + DspinDhccpParam::dspin_set(dspin_send_data, dest, @@ -6263,8 +6263,8 @@ else // icache active request { - uint64_t dest = (uint64_t) r_icache_cc_send_nline.read() - >> (m_nline_width - m_x_width - m_y_width) + uint64_t dest = (uint64_t) r_icache_cc_send_nline.read() + >> (m_nline_width - m_x_width - m_y_width) << (DspinDhccpParam::GLOBALID_WIDTH - m_x_width - m_y_width); - + DspinDhccpParam::dspin_set(dspin_send_data, @@ -6286,5 +6286,5 @@ // Receive coherence packets - // It depends on the CC_RECEIVE FSM + // It depends on the CC_RECEIVE FSM switch (r_cc_receive_fsm.read()) { @@ -6343,5 +6343,5 @@ case CC_RECEIVE_INS_UPDT_HEADER: { - if (not r_cc_receive_icache_req.read()) + if (not r_cc_receive_icache_req.read()) p_dspin_m2p.read = true; else @@ -6398,5 +6398,5 @@ } - p_dspin_clack.read = dspin_clack_get; + p_dspin_clack.read = dspin_clack_get; } // end genMoore