Changeset 82

Timestamp:

Sep 2, 2010, 2:22:12 PM (14 years ago)

Author:

guthmull

Message:

Add broadcast limitation compatibility, indicate the type of response when possible

Location:

trunk/modules

Files:

• vci_cc_xcache_wrapper_v1/caba/source/src/vci_cc_xcache_wrapper_v1.cpp (modified) (11 diffs)
• vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp (modified) (12 diffs)
• vci_mem_cache_v2/caba/source/include/vci_mem_cache_v2.h (modified) (2 diffs)
• vci_mem_cache_v2/caba/source/src/vci_mem_cache_v2.cpp (modified) (51 diffs)
• vci_mem_cache_v3/caba/source/include/vci_mem_cache_v3.h (modified) (2 diffs)
• vci_mem_cache_v3/caba/source/src/vci_mem_cache_v3.cpp (modified) (7 diffs)
• vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h (modified) (1 diff)
• vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp (modified) (9 diffs)

trunk/modules/vci_cc_xcache_wrapper_v1/caba/source/src/vci_cc_xcache_wrapper_v1.cpp

@@ -434 +434 @@
 
                     // multi-update or multi-invalidate for data type
-                    if ( (address != 0x3) && (! m_segment.contains(address)) ) 
+                    if ( ((address&0x3) != 0x3) && (! m_segment.contains(address)) ) 
                     {
                         std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
@@ -448 +448 @@
                     r_tgt_plen  = p_vci_tgt.plen.read();
                     
-                    if ( address == 0x3 )   // broadcast invalidate for data or instruction type
+                    if ( (address&0x3) == 0x3 )   // broadcast invalidate for data or instruction type
                     {
                         if ( ! p_vci_tgt.eop.read() ) 
@@ -1487 +1487 @@
                     r_vci_rsp_fsm = RSP_IDLE;
                 }
-                if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error = true;
+                if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error = true;
                 break;
 
@@ -1499 +1499 @@
                 r_vci_rsp_fsm = RSP_IDLE;
                 r_icache_unc_req = false;
-                if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error = true;
+                if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error = true;
                 break;
 
@@ -1516 +1516 @@
                     r_vci_rsp_fsm = RSP_IDLE;
                 }
-                if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true;
+                if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true;
                 break;
 
@@ -1527 +1527 @@
                     r_dcache_write_req = false;
                 }
-                if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) m_iss.setWriteBerr();
+                if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) m_iss.setWriteBerr();
                 break;
 
@@ -1539 +1539 @@
                 r_vci_rsp_fsm = RSP_IDLE;
                 r_dcache_unc_req = false;
-                if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true;
+                if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true;
                 break;
 
@@ -1548 +1548 @@
                 assert( p_vci_ini_c.reop.read() &&
                         "illegal VCI response packet for icache cleanup");
-                assert( (p_vci_ini_c.rerror.read() == vci_param::ERR_NORMAL) &&
+                assert( ((p_vci_ini_c.rerror.read()&0x1) == vci_param::ERR_NORMAL) &&
                         "error in response packet for icache cleanup");
                 if ( r_vci_rsp_fsm == RSP_INS_CLEANUP ) r_icache_cleanup_req = false;
@@ -1887 +1887 @@
                 p_vci_tgt.rtrdid  = r_tgt_trdid.read();
                 p_vci_tgt.rdata   = 0;
-                p_vci_tgt.rerror  = 0;
+                p_vci_tgt.rerror  = 0x2 & ( (1 << (vci_param::E + 1)) - 1); // Write OK
                 p_vci_tgt.reop    = true;
                 break;
@@ -1898 +1898 @@
                 p_vci_tgt.rtrdid  = r_tgt_trdid.read();
                 p_vci_tgt.rdata   = 0;
-                p_vci_tgt.rerror  = 0;
+                p_vci_tgt.rerror  = 0x2 & ( (1 << (vci_param::E + 1)) - 1); // Write OK
                 p_vci_tgt.reop    = true;
                 break;
@@ -1909 +1909 @@
                 p_vci_tgt.rtrdid  = r_tgt_trdid.read();
                 p_vci_tgt.rdata   = 0;
-                p_vci_tgt.rerror  = 0;
+                p_vci_tgt.rerror  = 0x2 & ( (1 << (vci_param::E + 1)) - 1); // Write OK
                 p_vci_tgt.reop    = true;
                 break;

trunk/modules/vci_cc_xcache_wrapper_v4/caba/source/src/vci_cc_xcache_wrapper_v4.cpp

@@ -432 +432 @@
 
                     // multi-update or multi-invalidate for data type
-                    if ( (address != 0x3) && (! m_segment.contains(address)) ) 
+                    if ( ((address&0x3) != 0x3) && (! m_segment.contains(address)) ) 
                     {
                         std::cout << "error in component VCI_CC_XCACHE_WRAPPER " << name() << std::endl;
@@ -446 +446 @@
                     r_tgt_plen  = p_vci_tgt.plen.read();
                     
-                    if ( address == 0x3 )   // broadcast invalidate for data or instruction type
+                    if ( (address&0x3) == 0x3 )   // broadcast invalidate for data or instruction type
                     {
                         if ( ! p_vci_tgt.eop.read() ) 
@@ -1558 +1558 @@
                     r_vci_rsp_fsm = RSP_IDLE;
                 }
-                if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error = true;
+                if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error = true;
                 break;
 
@@ -1570 +1570 @@
                 r_vci_rsp_fsm = RSP_IDLE;
                 r_icache_unc_req = false;
-                if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error = true;
+                if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_ins_error = true;
                 break;
 
@@ -1587 +1587 @@
                     r_vci_rsp_fsm = RSP_IDLE;
                 }
-                if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true;
+                if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true;
                 break;
 
@@ -1598 +1598 @@
                     r_dcache_write_req = false;
                 }
-                if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) m_iss.setWriteBerr();
+                if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) m_iss.setWriteBerr();
                 break;
 
@@ -1610 +1610 @@
                 r_vci_rsp_fsm = RSP_IDLE;
                 r_dcache_unc_req = false;
-                if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true;
+                if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true;
                 break;
 
@@ -1622 +1622 @@
                 r_vci_rsp_fsm = RSP_IDLE;
                 r_dcache_sc_req = false;
-                if ( p_vci_ini_rw.rerror.read() != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true;
+                if ( (p_vci_ini_rw.rerror.read()&0x1) != vci_param::ERR_NORMAL ) r_vci_rsp_data_error = true;
                 break;
 
@@ -1631 +1631 @@
                 assert( p_vci_ini_c.reop.read() &&
                         "illegal VCI response packet for icache cleanup");
-                assert( (p_vci_ini_c.rerror.read() == vci_param::ERR_NORMAL) &&
+                assert( ((p_vci_ini_c.rerror.read()&0x1) == vci_param::ERR_NORMAL) &&
                         "error in response packet for icache cleanup");
                 if ( r_vci_rsp_fsm == RSP_INS_CLEANUP ) r_icache_cleanup_req = false;
@@ -2011 +2011 @@
                 p_vci_tgt.rtrdid  = r_tgt_trdid.read();
                 p_vci_tgt.rdata   = 0;
-                p_vci_tgt.rerror  = 0;
+                p_vci_tgt.rerror  = 0x2 & ( (1 << (vci_param::E + 1)) - 1); // Write OK
                 p_vci_tgt.reop    = true;
                 break;
@@ -2022 +2022 @@
                 p_vci_tgt.rtrdid  = r_tgt_trdid.read();
                 p_vci_tgt.rdata   = 0;
-                p_vci_tgt.rerror  = 0;
+                p_vci_tgt.rerror  = 0x2 & ( (1 << (vci_param::E + 1)) - 1); // Write OK
                 p_vci_tgt.reop    = true;
                 break;
@@ -2033 +2033 @@
                 p_vci_tgt.rtrdid  = r_tgt_trdid.read();
                 p_vci_tgt.rdata   = 0;
-                p_vci_tgt.rerror  = 0;
+                p_vci_tgt.rerror  = 0x2 & ( (1 << (vci_param::E + 1)) - 1); // Write OK
                 p_vci_tgt.reop    = true;
                 break;

trunk/modules/vci_mem_cache_v2/caba/source/include/vci_mem_cache_v2.h

@@ -334 +334 @@
       const soclib::common::AddressMaskingTable<vci_addr_t>   m_nline; 
 
+      // broadcast address
+      vci_addr_t broadcast_addr;
+
       //////////////////////////////////////////////////
       // Others registers
@@ -448 +451 @@
       sc_signal<copy_t>    r_write_to_init_cmd_d_copies;    // bit_vector of L1 to update
       sc_signal<data_t>   *r_write_to_init_cmd_data;        // data (one cache line)
-      sc_signal<bool>     *r_write_to_init_cmd_we;              // word enable
+      sc_signal<be_t>     *r_write_to_init_cmd_be;              // word enable
       sc_signal<size_t>    r_write_to_init_cmd_count;       // number of words in line
       sc_signal<size_t>    r_write_to_init_cmd_index;       // index of first word in line

trunk/modules/vci_mem_cache_v2/caba/source/src/vci_mem_cache_v2.cpp

@@ -34 +34 @@
 //#define DEBUG_VCI_MEM_CACHE 1
 #define RANDOMIZE_SC
+#define DEBUG_START_CYCLE 33069000
 
 namespace soclib { namespace caba {
@@ -295 +296 @@
 
 
+      // Set the broadcast address with Xmin,Xmax,Ymin,Ymax set to maximum
+      broadcast_addr = 0x3 | (0x7C1F << (vci_param::N-20));
+
       // Get the segments associated to the MemCache 
       std::list<soclib::common::Segment>::iterator seg;
@@ -348 +352 @@
       r_write_be                                = new sc_signal<be_t>[nwords];
       r_write_to_init_cmd_data          = new sc_signal<data_t>[nwords];
-      r_write_to_init_cmd_we            = new sc_signal<bool>[nwords];
+      r_write_to_init_cmd_be            = new sc_signal<be_t>[nwords];
       r_write_to_ixr_cmd_data       = new sc_signal<data_t>[nwords];
 
@@ -530 +534 @@
 
 #if DEBUG_VCI_MEM_CACHE 
+if(m_cpt_cycles > DEBUG_START_CYCLE){
     std::cout << "---------------------------------------------" << std::dec << std::endl;
     std::cout << "MEM_CACHE " << m_srcid_ini << " ; Time = " << m_cpt_cycles << std::endl
@@ -546 +551 @@
       << " - ALLOC_TRT FSM = " << alloc_trt_fsm_str[r_alloc_trt_fsm] << std::endl
       << " - ALLOC_UPT FSM = " << alloc_upt_fsm_str[r_alloc_upt_fsm] << std::endl;
+}
 #endif
 
@@ -700 +706 @@
             bool valid  = m_update_tab.decrement(r_init_rsp_upt_index.read(), count);
 #ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
         std::cout << sc_time_stamp() << " " << name() << " INIT_RSP_UPT_LOCK update table : " << std::endl;
         m_update_tab.print();
+}
 #endif
             assert ( valid 
@@ -724 +732 @@
             m_update_tab.clear(r_init_rsp_upt_index.read());
 #ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
         std::cout << sc_time_stamp() << " " << name() << " INIT_RSP_UPT_CLEAR update table : " << std::endl;
         m_update_tab.print();
+}
 #endif
           }
@@ -777 +787 @@
             DirectoryEntry entry = m_cache_directory.read(m_cmd_read_addr_fifo.read(), way);
 #ifdef DDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
            std::cout << "In READ_DIR_LOCK printing the entry of address is : " << std::hex << m_cmd_read_addr_fifo.read() << std::endl;
            entry.print();
            std::cout << "done" << std::endl;
+}
 #endif
 
@@ -832 +844 @@
               }
               if(!inst_read && !is_cnt){ // Data read, vector mode
-                assert(!(r_read_d_copies.read() & (0x1 << m_cmd_read_srcid_fifo.read())) && "MemCache Error : processor read on an already owned cache line");
+                if(r_read_d_copies.read() & (0x1 << m_cmd_read_srcid_fifo.read())) {
+                    std::cout << "MemCache Error : processor read on an already owned cache line, Time : " << m_cpt_cycles << std::endl;
+                    exit(0);
+                }
                 entry.d_copies  = r_read_d_copies.read() | (0x1 << m_cmd_read_srcid_fifo.read()); 
                 entry.i_copies  = r_read_i_copies.read();
@@ -848 +863 @@
             }
 #ifdef DDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
            std::cout << "In READ_DIR_HIT printing the entry of address is : " << std::endl;
            entry.print();
            std::cout << "done" << std::endl;
+}
 #endif
 
@@ -881 +898 @@
           if ( r_alloc_trt_fsm.read() == ALLOC_TRT_READ ) {
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
         std::cout << sc_time_stamp() << " " << name() << " READ_TRT_LOCK " << std::endl;
+}
 #endif
             size_t index = 0;
@@ -912 +931 @@
                 std::vector<data_t>(m_words,0));
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
         std::cout << sc_time_stamp() << " " << name() << " READ_TRT_SET transaction table : " << std::endl;
         for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
           m_transaction_tab.print(i);
+}
 #endif
 
@@ -1178 +1199 @@
                 index);
 #ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
             if(wok){
         std::cout << sc_time_stamp() << " " << name() << " WRITE_UPT_LOCK update table : " << std::endl;
         m_update_tab.print();
             }
+}
 #endif
             r_write_upt_index = index;
@@ -1210 +1233 @@
 
             for(size_t i=0; i<m_words ; i++){
-              if(r_write_be[i].read())  r_write_to_init_cmd_we[i]=true;
-              else                      r_write_to_init_cmd_we[i]=false;
+              r_write_to_init_cmd_be[i]=r_write_be[i].read();
             }
 
@@ -1241 +1263 @@
           if ( r_alloc_trt_fsm.read() == ALLOC_TRT_WRITE ) {
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
         std::cout << sc_time_stamp() << " " << name() << " READ_TRT_LOCK " << std::endl;
+}
 #endif
             size_t hit_index = 0;
@@ -1292 +1316 @@
                 data_vector);
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
         std::cout << sc_time_stamp() << " " << name() << " WRITE_TRT_SET transaction table : " << std::endl;
         for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
           m_transaction_tab.print(i);
+}
 #endif
 
@@ -1318 +1344 @@
             r_write_fsm = WRITE_RSP;
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
         std::cout << sc_time_stamp() << " " << name() << " WRITE_TRT_DATA transaction table : " << std::endl;
         for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
           m_transaction_tab.print(i);
+}
 #endif
 
@@ -1377 +1405 @@
                 index);
 #ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
             if(wok){
         std::cout << sc_time_stamp() << " " << name() << " WRITE_INVAL_LOCK update table : " << std::endl;
         m_update_tab.print();
             }
+}
 #endif
             r_write_upt_index = index;
@@ -1408 +1438 @@
                 std::vector<data_t>(m_words,0));
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
         std::cout << sc_time_stamp() << " " << name() << " WRITE_DIR_INVAL transaction table : " << std::endl;
         for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
           m_transaction_tab.print(i);
+}
 #endif
 
@@ -1447 +1479 @@
 
             for(size_t i=0; i<m_words ; i++){
-              r_write_to_init_cmd_we[i]=false;
+              r_write_to_init_cmd_be[i]=0;
               r_write_to_init_cmd_data[i] = 0;
             }
@@ -1617 +1649 @@
             r_ixr_rsp_fsm = IXR_RSP_IDLE;
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
         std::cout << sc_time_stamp() << " " << name() << " IXR_RSP_TRT_ERASE transaction table : " << std::endl;
         for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
           m_transaction_tab.print(i);
+}
 #endif
 
@@ -1638 +1672 @@
             if ( eop ) {
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
         std::cout << sc_time_stamp() << " " << name() << " IXR_RSP_TRT_READ transaction table : " << std::endl;
         for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
           m_transaction_tab.print(i);
+}
 #endif
 
@@ -1687 +1723 @@
               break;
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
         std::cout << "XRAM_RSP FSM in XRAM_RSP_IDLE state" << std::endl;
+}
 #endif
             }
@@ -1699 +1737 @@
             r_xram_rsp_fsm           = XRAM_RSP_TRT_COPY;
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
         std::cout << "XRAM_RSP FSM in XRAM_RSP_DIR_LOCK state" << std::endl;
+}
 #endif
           }
@@ -1734 +1774 @@
             r_xram_rsp_fsm = XRAM_RSP_INVAL_LOCK;
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
         std::cout << "XRAM_RSP FSM in XRAM_RSP_TRT_COPY state" << std::endl;
         std::cout << "Victim way : " << std::hex << way << " set " << std::hex << set << std::endl;
         victim.print();
+}
 #endif
           }
@@ -1746 +1788 @@
           if ( r_alloc_upt_fsm == ALLOC_UPT_XRAM_RSP ) {
 #ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
         std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state" << std::endl;
+}
 #endif
             size_t index;
@@ -1752 +1796 @@
               r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
 #ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
         std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state to XRAM_RSP_INVAL_WAIT state" << std::endl;
+}
 #endif
 
@@ -1759 +1805 @@
               r_xram_rsp_fsm = XRAM_RSP_INVAL_WAIT;
 #ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
         std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state to XRAM_RSP_INVAL_WAIT state" << std::endl;
+}
 #endif
             }
@@ -1765 +1813 @@
               r_xram_rsp_fsm = XRAM_RSP_DIR_UPDT;
 #ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
         std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_LOCK state to XRAM_RSP_DIR_UPDT state" << std::endl;
+}
 #endif
             }
@@ -1777 +1827 @@
           break;
 #ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
         std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL_WAIT state" << std::endl;
+}
 #endif
         }
@@ -1822 +1874 @@
           m_cache_directory.write(set, way, entry);
 #ifdef DDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
            std::cout << "printing the entry : " << std::endl;
            entry.print();
            std::cout << "done" << std::endl;
+}
 #endif
 
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
         std::cout << sc_time_stamp() << " " << name() << " XRAM_RSP_DIR_UPDT transaction table : " << std::endl;
         for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
           m_transaction_tab.print(i);
+}
 #endif
 
@@ -1849 +1905 @@
 
 #ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
             std::cout << "xram_rsp : record invalidation, time = " << std::dec << m_cpt_cycles << std::endl;
             m_update_tab.print();
+}
 #endif
             r_xram_rsp_upt_index = index;
@@ -1885 +1943 @@
                 std::vector<data_t>(m_words,0) );
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
         std::cout << sc_time_stamp() << " " << name() << " XRAM_RSP_TRT_DIRTY transaction table : " << std::endl;
         for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
           m_transaction_tab.print(i);
+}
 #endif
 
@@ -1915 +1975 @@
 
 #ifdef DDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
         std::cout << "XRAM_RSP FSM in XRAM_RSP_DIR_RSP state" << std::endl;
+}
 #endif
           }
@@ -1933 +1995 @@
             else                                    r_xram_rsp_fsm = XRAM_RSP_IDLE;
 #ifdef DDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
         std::cout << "XRAM_RSP FSM in XRAM_RSP_INVAL state" << std::endl;
+}
 #endif
           }
@@ -1951 +2015 @@
             r_xram_rsp_fsm = XRAM_RSP_IDLE;
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
         std::cout << "XRAM_RSP FSM in XRAM_RSP_WRITE_DIRTY state" << std::endl;
+}
 #endif
           }
@@ -1981 +2047 @@
             }
             if ( (p_vci_tgt_cleanup.cmd.read() == vci_param::CMD_WRITE) &&
-                (((addr_t)(p_vci_tgt_cleanup.address.read())) != BROADCAST_ADDR) &&
+                (((addr_t)(p_vci_tgt_cleanup.address.read())&0x3) != 0x3) &&
                 reached) {
 
@@ -2006 +2072 @@
            DirectoryEntry entry = m_cache_directory.read(cleanup_address , way);
 #ifdef DDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
            std::cout << "In CLEANUP_DIR_LOCK printing the entry of address is : " << std::hex << cleanup_address << std::endl;
            entry.print();
            std::cout << "done" << std::endl;
+}
 #endif
             r_cleanup_is_cnt    = entry.is_cnt;
@@ -2089 +2157 @@
             if(!hit_inval) {
 #ifdef DEBUG_VCI_MEM_CACHE
+if(m_cpt_cycles > DEBUG_START_CYCLE){
               std::cout << "MEM_CACHE WARNING: cleanup with no corresponding entry at address : " << std::hex << (r_cleanup_nline.read()*4*m_words) << std::dec << std::endl;
+}
 #endif
               r_cleanup_fsm = CLEANUP_RSP;
@@ -2111 +2181 @@
             m_update_tab.clear(r_cleanup_index.read());
 #ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
         std::cout << sc_time_stamp() << " " << name() << " CLEANUP_UPT_WRITE update table : " << std::endl;
         m_update_tab.print();
+}
 #endif
 
@@ -2206 +2278 @@
             // set Atomic Table
             m_atomic_tab.set(m_cmd_llsc_srcid_fifo.read(), m_cmd_llsc_addr_fifo.read());
+
+#ifdef DDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
+           std::cout << "In LLSC_DIR_LOCK printing the entry of address is : " << std::hex << m_cmd_llsc_addr_fifo.read() << std::endl;
+           entry.print();
+           std::cout << "done" << std::endl;
+}
+#endif
+
 
             if ( entry.valid )  r_llsc_fsm = LL_DIR_HIT;
@@ -2347 +2428 @@
                 index);
 #ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
             if(wok){
         std::cout << sc_time_stamp() << " " << name() << " SC_UPT_LOCK update table : " << std::endl;
         m_update_tab.print();
             }
+}
 #endif
             r_llsc_upt_index = index;
@@ -2436 +2519 @@
                 index);
 #ifdef IDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
             if(wok){
         std::cout << sc_time_stamp() << " " << name() << " LLSC_INVAL_LOCK update table : " << std::endl;
         m_update_tab.print();
             }
+}
 #endif
             r_llsc_upt_index = index;
@@ -2466 +2551 @@
                 std::vector<data_t>(m_words,0));
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
         std::cout << sc_time_stamp() << " " << name() << " SC_DIR_INVAL transaction table : " << std::endl;
         for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
           m_transaction_tab.print(i);
+}
 #endif
             // reset Atomic Table
@@ -2624 +2711 @@
             }
 #ifdef TDEBUG
+if(m_cpt_cycles > DEBUG_START_CYCLE){
         std::cout << sc_time_stamp() << " " << name() << " LLSC_TRT_SET transaction table : " << std::endl;
         for(size_t i = 0 ; i < m_transaction_tab.size() ; i++)
           m_transaction_tab.print(i);
+}
 #endif
 
@@ -3611 +3700 @@
         p_vci_tgt.rtrdid   = r_write_to_tgt_rsp_trdid.read();
         p_vci_tgt.rpktid   = r_write_to_tgt_rsp_pktid.read();
-        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.rerror   = 0x2 & ( (1 << (vci_param::E + 1)) - 1); // Write OK
         p_vci_tgt.reop     = true;
         break;
@@ -3684 +3773 @@
         p_vci_ini.cmdval  = true;
         if(r_xram_rsp_to_init_cmd_brdcast.read())
-          p_vci_ini.address = BROADCAST_ADDR;
+          p_vci_ini.address = broadcast_addr;
         else {
           if(r_init_cmd_inst.read()) {
@@ -3700 +3789 @@
       case INIT_CMD_BRDCAST:
         p_vci_ini.cmdval  = true;
-        p_vci_ini.address = BROADCAST_ADDR;
+        p_vci_ini.address = broadcast_addr;
         p_vci_ini.wdata   = (addr_t)r_write_to_init_cmd_nline.read();
         p_vci_ini.be      = ((r_write_to_init_cmd_nline.read() >> 32) & 0x3);
@@ -3730 +3819 @@
         p_vci_ini.wdata   = r_write_to_init_cmd_data[r_init_cmd_cpt.read() +
           r_write_to_init_cmd_index.read()].read();
-        if(r_write_to_init_cmd_we[r_init_cmd_cpt.read() +
-            r_write_to_init_cmd_index.read()].read())  
-          p_vci_ini.be      = 0xF;
-        else                    p_vci_ini.be      = 0x0;
+        p_vci_ini.be      = r_write_to_init_cmd_be[r_init_cmd_cpt.read() +r_write_to_init_cmd_index.read()].read() ;  
         p_vci_ini.plen    = 4 * (r_write_to_init_cmd_count.read() + 2);
         p_vci_ini.trdid   = r_write_to_init_cmd_trdid.read();
@@ -3741 +3827 @@
       case INIT_CMD_SC_BRDCAST:
         p_vci_ini.cmdval  = true;
-        p_vci_ini.address = BROADCAST_ADDR;
+        p_vci_ini.address = broadcast_addr;
         p_vci_ini.wdata   = (addr_t)r_llsc_to_init_cmd_nline.read();
         p_vci_ini.be      = ((r_llsc_to_init_cmd_nline.read() >> 32) & 0x3);
@@ -3810 +3896 @@
           p_vci_tgt_cleanup.rpktid = r_cleanup_pktid.read();
           p_vci_tgt_cleanup.rtrdid = r_cleanup_trdid.read();
-          p_vci_tgt_cleanup.rerror = 0;
+          p_vci_tgt_cleanup.rerror = 0x2 & ( (1 << (vci_param::E + 1)) - 1);
           p_vci_tgt_cleanup.reop   = 1;
           break;

trunk/modules/vci_mem_cache_v3/caba/source/include/vci_mem_cache_v3.h

@@ -61 +61 @@
 #define TRANSACTION_TAB_LINES 4     // Number of lines in the transaction tab
 #define UPDATE_TAB_LINES 4          // Number of lines in the update tab
-#define BROADCAST_ADDR 0x0000000003 // Address to send the broadcast invalidate
 
 namespace soclib {  namespace caba {
@@ -362 +361 @@
       const soclib::common::AddressMaskingTable<vci_addr_t>   m_nline; 
 
+      // broadcast address
+      vci_addr_t broadcast_addr;
+
       //////////////////////////////////////////////////
       // Others registers

trunk/modules/vci_mem_cache_v3/caba/source/src/vci_mem_cache_v3.cpp

@@ -325 +325 @@
       assert(nways <= 32);
 
+      // Set the broadcast address with Xmin,Xmax,Ymin,Ymax set to maximum
+      broadcast_addr = 0x3 | (0x7C1F << (vci_param::N-20));
 
       // Get the segments associated to the MemCache 
@@ -2358 +2360 @@
             }
             if ( (p_vci_tgt_cleanup.cmd.read() == vci_param::CMD_WRITE) &&
-                (((addr_t)(p_vci_tgt_cleanup.address.read())) != BROADCAST_ADDR) &&
+                (((addr_t)(p_vci_tgt_cleanup.address.read())&0x3) != 0x3) &&
                 reached) {
 
@@ -4337 +4339 @@
         p_vci_tgt.rtrdid   = r_write_to_tgt_rsp_trdid.read();
         p_vci_tgt.rpktid   = r_write_to_tgt_rsp_pktid.read();
-        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.rerror   = 0x2 & ( (1 << (vci_param::E + 1)) - 1); // Write OK
         p_vci_tgt.reop     = true;
         break;
@@ -4421 +4423 @@
       case INIT_CMD_XRAM_BRDCAST:
         p_vci_ini.cmdval  = true;
-        p_vci_ini.address = BROADCAST_ADDR;
+        p_vci_ini.address = broadcast_addr;
         p_vci_ini.wdata   = (uint32_t)r_xram_rsp_to_init_cmd_nline.read();
         p_vci_ini.be      = ((r_xram_rsp_to_init_cmd_nline.read() >> 32) & 0x3);
@@ -4431 +4433 @@
       case INIT_CMD_WRITE_BRDCAST:
         p_vci_ini.cmdval  = true;
-        p_vci_ini.address = BROADCAST_ADDR;
+        p_vci_ini.address = broadcast_addr;
         p_vci_ini.wdata   = (addr_t)r_write_to_init_cmd_nline.read();
         p_vci_ini.be      = ((r_write_to_init_cmd_nline.read() >> 32) & 0x3);
@@ -4476 +4478 @@
       case INIT_CMD_SC_BRDCAST:
         p_vci_ini.cmdval  = true;
-        p_vci_ini.address = BROADCAST_ADDR;
+        p_vci_ini.address = broadcast_addr;
         p_vci_ini.wdata   = (addr_t)r_llsc_to_init_cmd_nline.read();
         p_vci_ini.be      = ((r_llsc_to_init_cmd_nline.read() >> 32) & 0x3);
@@ -4549 +4551 @@
           p_vci_tgt_cleanup.rpktid = r_cleanup_pktid.read();
           p_vci_tgt_cleanup.rtrdid = r_cleanup_trdid.read();
-          p_vci_tgt_cleanup.rerror = 0;
+          p_vci_tgt_cleanup.rerror = 0x2 & ( (1 << (vci_param::E + 1)) - 1);
           p_vci_tgt_cleanup.reop   = 1;
           break;

trunk/modules/vci_mem_cache_v4/caba/source/include/vci_mem_cache_v4.h

@@ -354 +354 @@
       const soclib::common::AddressMaskingTable<vci_addr_t>   m_nline; 
 
+      // broadcast address
+      vci_addr_t broadcast_addr;
+
       //////////////////////////////////////////////////
       // Others registers

trunk/modules/vci_mem_cache_v4/caba/source/src/vci_mem_cache_v4.cpp

@@ -321 +321 @@
       assert(nways <= 32);
 
+      // Set the broadcast address with Xmin,Xmax,Ymin,Ymax set to maximum
+      broadcast_addr = 0x3 | (0x7C1F << (vci_param::N-20));
 
       // Get the segments associated to the MemCache 
@@ -2324 +2326 @@
             }
             if ( (p_vci_tgt_cleanup.cmd.read() == vci_param::CMD_WRITE) &&
-                (((addr_t)(p_vci_tgt_cleanup.address.read())) != BROADCAST_ADDR) &&
+                (((addr_t)(p_vci_tgt_cleanup.address.read())&0x3) != 0x3) &&
                 reached) {
 
@@ -4247 +4249 @@
         p_vci_tgt.rtrdid   = r_write_to_tgt_rsp_trdid.read();
         p_vci_tgt.rpktid   = r_write_to_tgt_rsp_pktid.read();
-        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.rerror   = 0x2 & ( (1 << (vci_param::E + 1)) - 1); // Write OK
         p_vci_tgt.reop     = true;
         break;
@@ -4256 +4258 @@
         p_vci_tgt.rtrdid   = r_cleanup_to_tgt_rsp_trdid.read();
         p_vci_tgt.rpktid   = r_cleanup_to_tgt_rsp_pktid.read();
-        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.rerror   = 0; // Can be a SC rsp
         p_vci_tgt.reop     = true;
         break;
@@ -4283 +4285 @@
         p_vci_tgt.rtrdid   = r_init_rsp_to_tgt_rsp_trdid.read();
         p_vci_tgt.rpktid   = r_init_rsp_to_tgt_rsp_pktid.read();
-        p_vci_tgt.rerror   = 0;
+        p_vci_tgt.rerror   = 0; // Can be a SC rsp
         p_vci_tgt.reop     = true;      
         break;
@@ -4331 +4333 @@
       case INIT_CMD_XRAM_BRDCAST:
         p_vci_ini.cmdval  = true;
-        p_vci_ini.address = BROADCAST_ADDR;
+        p_vci_ini.address = broadcast_addr;
         p_vci_ini.wdata   = (uint32_t)r_xram_rsp_to_init_cmd_nline.read();
         p_vci_ini.be      = ((r_xram_rsp_to_init_cmd_nline.read() >> 32) & 0x3);
@@ -4341 +4343 @@
       case INIT_CMD_WRITE_BRDCAST:
         p_vci_ini.cmdval  = true;
-        p_vci_ini.address = BROADCAST_ADDR;
+        p_vci_ini.address = broadcast_addr;
         p_vci_ini.wdata   = (addr_t)r_write_to_init_cmd_nline.read();
         p_vci_ini.be      = ((r_write_to_init_cmd_nline.read() >> 32) & 0x3);
@@ -4396 +4398 @@
       case INIT_CMD_SC_BRDCAST:
         p_vci_ini.cmdval  = true;
-        p_vci_ini.address = BROADCAST_ADDR;
+        p_vci_ini.address = broadcast_addr;
         p_vci_ini.wdata   = (addr_t)r_llsc_to_init_cmd_nline.read();
         p_vci_ini.be      = ((r_llsc_to_init_cmd_nline.read() >> 32) & 0x3);
@@ -4507 +4509 @@
           p_vci_tgt_cleanup.rpktid = r_cleanup_pktid.read();
           p_vci_tgt_cleanup.rtrdid = r_cleanup_trdid.read();
-          p_vci_tgt_cleanup.rerror = 0;
+          p_vci_tgt_cleanup.rerror = 0x2 & ( (1 << (vci_param::E + 1)) - 1);
           p_vci_tgt_cleanup.reop   = 1;
           break;