Index: branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h
===================================================================
--- branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	(revision 814)
+++ branches/RWT/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h	(revision 823)
@@ -69,10 +69,10 @@
     : public soclib::caba::BaseModule
     {
-      typedef typename vci_param_int::fast_addr_t  addr_t;
-      typedef typename sc_dt::sc_uint<64>          wide_data_t;
-      typedef uint32_t                             data_t;
-      typedef uint32_t                             tag_t;
-      typedef uint32_t                             be_t;
-      typedef uint32_t                             copy_t;
+      typedef typename vci_param_int::fast_addr_t addr_t;
+      typedef typename sc_dt::sc_uint<64>         wide_data_t;
+      typedef uint32_t                            data_t;
+      typedef uint32_t                            tag_t;
+      typedef uint32_t                            be_t;
+      typedef uint32_t                            copy_t;
 
       /* States of the TGT_CMD fsm */
@@ -113,5 +113,4 @@
         CC_RECEIVE_IDLE,
         CC_RECEIVE_CLEANUP,
-        CC_RECEIVE_CLEANUP_EOP,
         CC_RECEIVE_MULTI_ACK
       };
@@ -232,5 +231,4 @@
       {
         IXR_RSP_IDLE,
-        IXR_RSP_ACK,
         IXR_RSP_TRT_ERASE,
         IXR_RSP_TRT_READ
@@ -399,12 +397,12 @@
           //  b1 accÃšs table llsc type SW / other
           //  b2 WRITE/CAS/LL/SC
-          TYPE_READ_DATA_UNC   = 0x0,
-          TYPE_READ_DATA_MISS  = 0x1,
-          TYPE_READ_INS_UNC    = 0x2,
-          TYPE_READ_INS_MISS   = 0x3,
-          TYPE_WRITE           = 0x4,
-          TYPE_CAS             = 0x5,
-          TYPE_LL              = 0x6,
-          TYPE_SC              = 0x7
+          TYPE_READ_DATA_UNC  = 0x0,
+          TYPE_READ_DATA_MISS = 0x1,
+          TYPE_READ_INS_UNC   = 0x2,
+          TYPE_READ_INS_MISS  = 0x3,
+          TYPE_WRITE          = 0x4,
+          TYPE_CAS            = 0x5,
+          TYPE_LL             = 0x6,
+          TYPE_SC             = 0x7
       };
 
@@ -425,55 +423,55 @@
 
       // instrumentation counters
-      uint32_t m_cpt_cycles;        // Counter of cycles
+      uint32_t m_cpt_cycles;                  // Counter of cycles
 
       // Counters accessible in software (not yet but eventually) and tagged
-      uint32_t m_cpt_reset_count;    // Last cycle at which counters have been reset
-      uint32_t m_cpt_read_local;     // Number of local READ transactions
-      uint32_t m_cpt_read_remote;    // number of remote READ transactions
-      uint32_t m_cpt_read_cost;      // Number of (flits * distance) for READs
-
-      uint32_t m_cpt_write_local;    // Number of local WRITE transactions
-      uint32_t m_cpt_write_remote;   // number of remote WRITE transactions
-      uint32_t m_cpt_write_flits_local;  // number of flits for local WRITEs
-      uint32_t m_cpt_write_flits_remote; // number of flits for remote WRITEs
-      uint32_t m_cpt_write_cost;     // Number of (flits * distance) for WRITEs
-      uint32_t m_cpt_write_ncc_miss;   // Number of write on ncc line
-
-      uint32_t m_cpt_ll_local;       // Number of local LL transactions
-      uint32_t m_cpt_ll_remote;      // number of remote LL transactions
-      uint32_t m_cpt_ll_cost;        // Number of (flits * distance) for LLs
-
-      uint32_t m_cpt_sc_local;       // Number of local SC transactions
-      uint32_t m_cpt_sc_remote;      // number of remote SC transactions
-      uint32_t m_cpt_sc_cost;        // Number of (flits * distance) for SCs
-
-      uint32_t m_cpt_cas_local;      // Number of local SC transactions
-      uint32_t m_cpt_cas_remote;     // number of remote SC transactions
-      uint32_t m_cpt_cas_cost;       // Number of (flits * distance) for SCs
-
-      uint32_t m_cpt_update;         // Number of requests causing an UPDATE
-      uint32_t m_cpt_update_local;   // Number of local UPDATE transactions
-      uint32_t m_cpt_update_remote;  // Number of remote UPDATE transactions
-      uint32_t m_cpt_update_cost;    // Number of (flits * distance) for UPDT
-
-      uint32_t m_cpt_minval;         // Number of requests causing M_INV
-      uint32_t m_cpt_minval_local;   // Number of local M_INV transactions
-      uint32_t m_cpt_minval_remote;  // Number of remote M_INV transactions
-      uint32_t m_cpt_minval_cost;    // Number of (flits * distance) for M_INV
-
-      uint32_t m_cpt_binval;         // Number of BROADCAST INVAL
-
-      uint32_t m_cpt_cleanup_local;  // Number of local CLEANUP transactions (all cleanup types)
-      uint32_t m_cpt_cleanup_remote; // Number of remote CLEANUP transactions (all cleanup types)
-      uint32_t m_cpt_cleanup_cost;   // Number of (flits * distance) for CLEANUPs (all types)
+      uint32_t m_cpt_reset_count;             // Last cycle at which counters have been reset
+      uint32_t m_cpt_read_local;              // Number of local READ transactions
+      uint32_t m_cpt_read_remote;             // number of remote READ transactions
+      uint32_t m_cpt_read_cost;               // Number of (flits * distance) for READs
+
+      uint32_t m_cpt_write_local;             // Number of local WRITE transactions
+      uint32_t m_cpt_write_remote;            // number of remote WRITE transactions
+      uint32_t m_cpt_write_flits_local;       // number of flits for local WRITEs
+      uint32_t m_cpt_write_flits_remote;      // number of flits for remote WRITEs
+      uint32_t m_cpt_write_cost;              // Number of (flits * distance) for WRITEs
+      uint32_t m_cpt_write_ncc_miss;          // Number of write on ncc line
+
+      uint32_t m_cpt_ll_local;                // Number of local LL transactions
+      uint32_t m_cpt_ll_remote;               // number of remote LL transactions
+      uint32_t m_cpt_ll_cost;                 // Number of (flits * distance) for LLs
+
+      uint32_t m_cpt_sc_local;                // Number of local SC transactions
+      uint32_t m_cpt_sc_remote;               // number of remote SC transactions
+      uint32_t m_cpt_sc_cost;                 // Number of (flits * distance) for SCs
+
+      uint32_t m_cpt_cas_local;               // Number of local SC transactions
+      uint32_t m_cpt_cas_remote;              // number of remote SC transactions
+      uint32_t m_cpt_cas_cost;                // Number of (flits * distance) for SCs
+
+      uint32_t m_cpt_update;                  // Number of requests causing an UPDATE
+      uint32_t m_cpt_update_local;            // Number of local UPDATE transactions
+      uint32_t m_cpt_update_remote;           // Number of remote UPDATE transactions
+      uint32_t m_cpt_update_cost;             // Number of (flits * distance) for UPDT
+
+      uint32_t m_cpt_minval;                  // Number of requests causing M_INV
+      uint32_t m_cpt_minval_local;            // Number of local M_INV transactions
+      uint32_t m_cpt_minval_remote;           // Number of remote M_INV transactions
+      uint32_t m_cpt_minval_cost;             // Number of (flits * distance) for M_INV
+
+      uint32_t m_cpt_binval;                  // Number of BROADCAST INVAL
+
+      uint32_t m_cpt_cleanup_local;           // Number of local CLEANUP transactions (all cleanup types)
+      uint32_t m_cpt_cleanup_remote;          // Number of remote CLEANUP transactions (all cleanup types)
+      uint32_t m_cpt_cleanup_cost;            // Number of (flits * distance) for CLEANUPs (all types)
 
       // Counters not accessible by software, but tagged
-      uint32_t m_cpt_read_miss;       // Number of MISS READ
-      uint32_t m_cpt_write_miss;      // Number of MISS WRITE
-      uint32_t m_cpt_write_dirty;     // Cumulated length for WRITE transactions
-      uint32_t m_cpt_write_broadcast; // Number of BROADCAST INVAL because write
-
-      uint32_t m_cpt_trt_rb;          // Read blocked by a hit in trt
-      uint32_t m_cpt_trt_full;        // Transaction blocked due to a full trt
+      uint32_t m_cpt_read_miss;               // Number of MISS READ
+      uint32_t m_cpt_write_miss;              // Number of MISS WRITE
+      uint32_t m_cpt_write_dirty;             // Cumulated length for WRITE transactions
+      uint32_t m_cpt_write_broadcast;         // Number of BROADCAST INVAL because write
+
+      uint32_t m_cpt_trt_rb;                  // Read blocked by a hit in trt
+      uint32_t m_cpt_trt_full;                // Transaction blocked due to a full trt
 
       uint32_t m_cpt_heap_unused;             // NB cycles HEAP LOCK unused
@@ -481,13 +479,13 @@
       uint32_t m_cpt_heap_min_slot_available; // NB HEAP : Min of slot available
 
-      uint32_t m_cpt_ncc_to_cc_read;         // NB change from NCC to CC caused by a READ
-      uint32_t m_cpt_ncc_to_cc_write;        // NB change from NCC to CC caused by a WRITE
-
-      uint32_t m_cpt_cleanup_data_local;  // Number of local cleanups with data
-      uint32_t m_cpt_cleanup_data_remote; // Number of remote cleanups with data
-      uint32_t m_cpt_cleanup_data_cost;   // Cost for cleanups with data
-
-      uint32_t m_cpt_update_flits;  // Number of flits for UPDATEs
-      uint32_t m_cpt_inval_cost;    // Number of (flits * distance) for INVALs
+      uint32_t m_cpt_ncc_to_cc_read;          // NB change from NCC to CC caused by a READ
+      uint32_t m_cpt_ncc_to_cc_write;         // NB change from NCC to CC caused by a WRITE
+
+      uint32_t m_cpt_cleanup_data_local;      // Number of local cleanups with data
+      uint32_t m_cpt_cleanup_data_remote;     // Number of remote cleanups with data
+      uint32_t m_cpt_cleanup_data_cost;       // Cost for cleanups with data
+
+      uint32_t m_cpt_update_flits;            // Number of flits for UPDATEs
+      uint32_t m_cpt_inval_cost;              // Number of (flits * distance) for INVALs
 
       uint32_t m_cpt_get;
@@ -499,13 +497,4 @@
       uint32_t m_cpt_upt_unused; // NB cycles UPT LOCK unused
 
-      // Unused
-      uint32_t m_cpt_read_data_unc;
-      uint32_t m_cpt_read_data_miss_CC;
-      uint32_t m_cpt_read_ins_unc;
-      uint32_t m_cpt_read_ins_miss;
-      uint32_t m_cpt_read_ll_CC;
-      uint32_t m_cpt_read_data_miss_NCC;
-      uint32_t m_cpt_read_ll_NCC;
-
       size_t   m_prev_count;
 
@@ -515,12 +504,12 @@
 
       public:
-      sc_in<bool>                                 p_clk;
-      sc_in<bool>                                 p_resetn;
-      sc_out<bool>                                p_irq;
-      soclib::caba::VciTarget<vci_param_int>      p_vci_tgt;
-      soclib::caba::VciInitiator<vci_param_ext>   p_vci_ixr;
-      soclib::caba::DspinInput<dspin_in_width>    p_dspin_p2m;
-      soclib::caba::DspinOutput<dspin_out_width>  p_dspin_m2p;
-      soclib::caba::DspinOutput<dspin_out_width>  p_dspin_clack;
+      sc_in<bool>                                p_clk;
+      sc_in<bool>                                p_resetn;
+      sc_out<bool>                               p_irq;
+      soclib::caba::VciTarget<vci_param_int>     p_vci_tgt;
+      soclib::caba::VciInitiator<vci_param_ext>  p_vci_ixr;
+      soclib::caba::DspinInput<dspin_in_width>   p_dspin_p2m;
+      soclib::caba::DspinOutput<dspin_out_width> p_dspin_m2p;
+      soclib::caba::DspinOutput<dspin_out_width> p_dspin_clack;
 
 #if MONITOR_MEMCACHE_FSM == 1
@@ -557,10 +546,10 @@
           const size_t                       nwords,          // Number of words per line
           const size_t                       max_copies,      // max number of copies
-          const size_t                       heap_size=HEAP_ENTRIES,
-          const size_t                       trt_lines=TRT_ENTRIES,
-          const size_t                       upt_lines=UPT_ENTRIES,
-          const size_t                       ivt_lines=IVT_ENTRIES,
-          const size_t                       debug_start_cycle=0,
-          const bool                         debug_ok=false );
+          const size_t                       heap_size = HEAP_ENTRIES,
+          const size_t                       trt_lines = TRT_ENTRIES,
+          const size_t                       upt_lines = UPT_ENTRIES,
+          const size_t                       ivt_lines = IVT_ENTRIES,
+          const size_t                       debug_start_cycle = 0,
+          const bool                         debug_ok = false );
 
       ~VciMemCache();
@@ -568,5 +557,5 @@
       void reset_counters();
       void print_stats(bool activity_counters = true, bool stats = false);
-      void print_trace( size_t detailled = 0 );
+      void print_trace(size_t detailled = 0);
       void cache_monitor(addr_t addr);
       void start_monitor(addr_t addr, addr_t length);
@@ -581,5 +570,5 @@
       uint32_t min_value(uint32_t old_value, uint32_t new_value);
       bool is_local_req(uint32_t req_srcid);
-      int  read_instrumentation(uint32_t regr, uint32_t & rdata);
+      int read_instrumentation(uint32_t regr, uint32_t & rdata);
 
       // Component attributes
@@ -616,11 +605,11 @@
 
       // adress masks
-      const soclib::common::AddressMaskingTable<addr_t>   m_x;
-      const soclib::common::AddressMaskingTable<addr_t>   m_y;
-      const soclib::common::AddressMaskingTable<addr_t>   m_z;
-      const soclib::common::AddressMaskingTable<addr_t>   m_nline;
+      const soclib::common::AddressMaskingTable<addr_t> m_x;
+      const soclib::common::AddressMaskingTable<addr_t> m_y;
+      const soclib::common::AddressMaskingTable<addr_t> m_z;
+      const soclib::common::AddressMaskingTable<addr_t> m_nline;
 
       // broadcast address
-      uint32_t                           m_broadcast_boundaries;
+      uint32_t m_broadcast_boundaries;
 
       // configuration interface constants
@@ -632,32 +621,32 @@
 
       // Fifo between TGT_CMD fsm and READ fsm
-      GenericFifo<addr_t>    m_cmd_read_addr_fifo;
-      GenericFifo<size_t>    m_cmd_read_length_fifo;
-      GenericFifo<size_t>    m_cmd_read_srcid_fifo;
-      GenericFifo<size_t>    m_cmd_read_trdid_fifo;
-      GenericFifo<size_t>    m_cmd_read_pktid_fifo;
+      GenericFifo<addr_t> m_cmd_read_addr_fifo;
+      GenericFifo<size_t> m_cmd_read_length_fifo;
+      GenericFifo<size_t> m_cmd_read_srcid_fifo;
+      GenericFifo<size_t> m_cmd_read_trdid_fifo;
+      GenericFifo<size_t> m_cmd_read_pktid_fifo;
 
       // Fifo between TGT_CMD fsm and WRITE fsm
-      GenericFifo<addr_t>    m_cmd_write_addr_fifo;
-      GenericFifo<bool>      m_cmd_write_eop_fifo;
-      GenericFifo<size_t>    m_cmd_write_srcid_fifo;
-      GenericFifo<size_t>    m_cmd_write_trdid_fifo;
-      GenericFifo<size_t>    m_cmd_write_pktid_fifo;
-      GenericFifo<data_t>    m_cmd_write_data_fifo;
-      GenericFifo<be_t>      m_cmd_write_be_fifo;
+      GenericFifo<addr_t> m_cmd_write_addr_fifo;
+      GenericFifo<bool>   m_cmd_write_eop_fifo;
+      GenericFifo<size_t> m_cmd_write_srcid_fifo;
+      GenericFifo<size_t> m_cmd_write_trdid_fifo;
+      GenericFifo<size_t> m_cmd_write_pktid_fifo;
+      GenericFifo<data_t> m_cmd_write_data_fifo;
+      GenericFifo<be_t>   m_cmd_write_be_fifo;
 
       // Fifo between TGT_CMD fsm and CAS fsm
-      GenericFifo<addr_t>    m_cmd_cas_addr_fifo;
-      GenericFifo<bool>      m_cmd_cas_eop_fifo;
-      GenericFifo<size_t>    m_cmd_cas_srcid_fifo;
-      GenericFifo<size_t>    m_cmd_cas_trdid_fifo;
-      GenericFifo<size_t>    m_cmd_cas_pktid_fifo;
-      GenericFifo<data_t>    m_cmd_cas_wdata_fifo;
+      GenericFifo<addr_t> m_cmd_cas_addr_fifo;
+      GenericFifo<bool>   m_cmd_cas_eop_fifo;
+      GenericFifo<size_t> m_cmd_cas_srcid_fifo;
+      GenericFifo<size_t> m_cmd_cas_trdid_fifo;
+      GenericFifo<size_t> m_cmd_cas_pktid_fifo;
+      GenericFifo<data_t> m_cmd_cas_wdata_fifo;
 
       // Fifo between CC_RECEIVE fsm and CLEANUP fsm
-      GenericFifo<uint64_t>  m_cc_receive_to_cleanup_fifo;
+      GenericFifo<uint64_t> m_cc_receive_to_cleanup_fifo;
 
       // Fifo between CC_RECEIVE fsm and MULTI_ACK fsm
-      GenericFifo<uint64_t>  m_cc_receive_to_multi_ack_fifo;
+      GenericFifo<uint64_t> m_cc_receive_to_multi_ack_fifo;
 
       // Buffer between TGT_CMD fsm and TGT_RSP fsm
@@ -678,5 +667,5 @@
       //////////////////////////////////////////////////
 
-      sc_signal<int>         r_tgt_cmd_fsm;
+      sc_signal<int> r_tgt_cmd_fsm;
 
       ///////////////////////////////////////////////////////
@@ -684,42 +673,42 @@
       ///////////////////////////////////////////////////////
 
-      sc_signal<int>      r_config_fsm;               // FSM state
-      sc_signal<bool>     r_config_lock;              // lock protecting exclusive access
-      sc_signal<int>      r_config_cmd;               // config request type
-      sc_signal<addr_t>   r_config_address;           // target buffer physical address
-      sc_signal<size_t>   r_config_srcid;             // config request srcid
-      sc_signal<size_t>   r_config_trdid;             // config request trdid
-      sc_signal<size_t>   r_config_pktid;             // config request pktid
-      sc_signal<size_t>   r_config_cmd_lines;         // number of lines to be handled
-      sc_signal<size_t>   r_config_rsp_lines;         // number of lines not completed
-      sc_signal<size_t>   r_config_dir_way;           // DIR: selected way
-      sc_signal<bool>     r_config_dir_lock;          // DIR: locked entry
-      sc_signal<size_t>   r_config_dir_count;         // DIR: number of copies
-      sc_signal<bool>     r_config_dir_is_cnt;        // DIR: counter mode (broadcast)
-      sc_signal<size_t>   r_config_dir_copy_srcid;    // DIR: first copy SRCID
-      sc_signal<bool>     r_config_dir_copy_inst;     // DIR: first copy L1 type
-      sc_signal<size_t>   r_config_dir_ptr;           // DIR: index of next copy in HEAP
-      sc_signal<size_t>   r_config_heap_next;         // current pointer to scan HEAP
-      sc_signal<size_t>   r_config_trt_index;         // selected entry in TRT
-      sc_signal<size_t>   r_config_ivt_index;         // selected entry in IVT
+      sc_signal<int>    r_config_fsm;            // FSM state
+      sc_signal<bool>   r_config_lock;           // lock protecting exclusive access
+      sc_signal<int>    r_config_cmd;            // config request type
+      sc_signal<addr_t> r_config_address;        // target buffer physical address
+      sc_signal<size_t> r_config_srcid;          // config request srcid
+      sc_signal<size_t> r_config_trdid;          // config request trdid
+      sc_signal<size_t> r_config_pktid;          // config request pktid
+      sc_signal<size_t> r_config_cmd_lines;      // number of lines to be handled
+      sc_signal<size_t> r_config_rsp_lines;      // number of lines not completed
+      sc_signal<size_t> r_config_dir_way;        // DIR: selected way
+      sc_signal<bool>   r_config_dir_lock;       // DIR: locked entry
+      sc_signal<size_t> r_config_dir_count;      // DIR: number of copies
+      sc_signal<bool>   r_config_dir_is_cnt;     // DIR: counter mode (broadcast)
+      sc_signal<size_t> r_config_dir_copy_srcid; // DIR: first copy SRCID
+      sc_signal<bool>   r_config_dir_copy_inst;  // DIR: first copy L1 type
+      sc_signal<size_t> r_config_dir_ptr;        // DIR: index of next copy in HEAP
+      sc_signal<size_t> r_config_heap_next;      // current pointer to scan HEAP
+      sc_signal<size_t> r_config_trt_index;      // selected entry in TRT
+      sc_signal<size_t> r_config_ivt_index;      // selected entry in IVT
 
       // Buffer between CONFIG fsm and IXR_CMD fsm
-      sc_signal<bool>     r_config_to_ixr_cmd_req;    // valid request
-      sc_signal<size_t>   r_config_to_ixr_cmd_index;  // TRT index
+      sc_signal<bool>   r_config_to_ixr_cmd_req;   // valid request
+      sc_signal<size_t> r_config_to_ixr_cmd_index; // TRT index
 
       // Buffer between CONFIG fsm and TGT_RSP fsm (send a done response to L1 cache)
-      sc_signal<bool>     r_config_to_tgt_rsp_req;    // valid request
-      sc_signal<bool>     r_config_to_tgt_rsp_error;  // error response
-      sc_signal<size_t>   r_config_to_tgt_rsp_srcid;  // Transaction srcid
-      sc_signal<size_t>   r_config_to_tgt_rsp_trdid;  // Transaction trdid
-      sc_signal<size_t>   r_config_to_tgt_rsp_pktid;  // Transaction pktid
+      sc_signal<bool>   r_config_to_tgt_rsp_req;   // valid request
+      sc_signal<bool>   r_config_to_tgt_rsp_error; // error response
+      sc_signal<size_t> r_config_to_tgt_rsp_srcid; // Transaction srcid
+      sc_signal<size_t> r_config_to_tgt_rsp_trdid; // Transaction trdid
+      sc_signal<size_t> r_config_to_tgt_rsp_pktid; // Transaction pktid
 
       // Buffer between CONFIG fsm and CC_SEND fsm (multi-inval / broadcast-inval)
-      sc_signal<bool>     r_config_to_cc_send_multi_req;    // multi-inval request
-      sc_signal<bool>     r_config_to_cc_send_brdcast_req;  // broadcast-inval request
-      sc_signal<addr_t>   r_config_to_cc_send_nline;        // line index
-      sc_signal<size_t>   r_config_to_cc_send_trdid;        // UPT index
-      GenericFifo<bool>   m_config_to_cc_send_inst_fifo;    // fifo for the L1 type
-      GenericFifo<size_t> m_config_to_cc_send_srcid_fifo;   // fifo for owners srcid
+      sc_signal<bool>     r_config_to_cc_send_multi_req;   // multi-inval request
+      sc_signal<bool>     r_config_to_cc_send_brdcast_req; // broadcast-inval request
+      sc_signal<addr_t>   r_config_to_cc_send_nline;       // line index
+      sc_signal<size_t>   r_config_to_cc_send_trdid;       // UPT index
+      GenericFifo<bool>   m_config_to_cc_send_inst_fifo;   // fifo for the L1 type
+      GenericFifo<size_t> m_config_to_cc_send_srcid_fifo;  // fifo for owners srcid
 
       ///////////////////////////////////////////////////////
@@ -727,34 +716,34 @@
       ///////////////////////////////////////////////////////
 
-      sc_signal<int>      r_read_fsm;                 // FSM state
-      sc_signal<size_t>   r_read_copy;                // Srcid of the first copy
-      sc_signal<size_t>   r_read_copy_cache;          // Srcid of the first copy
-      sc_signal<bool>     r_read_copy_inst;           // Type of the first copy
-      sc_signal<tag_t>    r_read_tag;                 // cache line tag (in directory)
-      sc_signal<bool>     r_read_is_cnt;              // is_cnt bit (in directory)
-      sc_signal<bool>     r_read_lock;                // lock bit (in directory)
-      sc_signal<bool>     r_read_dirty;               // dirty bit (in directory)
-      sc_signal<size_t>   r_read_count;               // number of copies
-      sc_signal<size_t>   r_read_ptr;                 // pointer to the heap
-      sc_signal<data_t> * r_read_data;                // data (one cache line)
-      sc_signal<size_t>   r_read_way;                 // associative way (in cache)
-      sc_signal<size_t>   r_read_trt_index;           // Transaction Table index
-      sc_signal<size_t>   r_read_next_ptr;            // Next entry to point to
-      sc_signal<bool>     r_read_last_free;           // Last free entry
-      sc_signal<addr_t>   r_read_ll_key;              // LL key from llsc_global_table
+      sc_signal<int>      r_read_fsm;        // FSM state
+      sc_signal<size_t>   r_read_copy;       // Srcid of the first copy
+      sc_signal<size_t>   r_read_copy_cache; // Srcid of the first copy
+      sc_signal<bool>     r_read_copy_inst;  // Type of the first copy
+      sc_signal<tag_t>    r_read_tag;        // cache line tag (in directory)
+      sc_signal<bool>     r_read_is_cnt;     // is_cnt bit (in directory)
+      sc_signal<bool>     r_read_lock;       // lock bit (in directory)
+      sc_signal<bool>     r_read_dirty;      // dirty bit (in directory)
+      sc_signal<size_t>   r_read_count;      // number of copies
+      sc_signal<size_t>   r_read_ptr;        // pointer to the heap
+      sc_signal<data_t> * r_read_data;       // data (one cache line)
+      sc_signal<size_t>   r_read_way;        // associative way (in cache)
+      sc_signal<size_t>   r_read_trt_index;  // Transaction Table index
+      sc_signal<size_t>   r_read_next_ptr;   // Next entry to point to
+      sc_signal<bool>     r_read_last_free;  // Last free entry
+      sc_signal<addr_t>   r_read_ll_key;     // LL key from llsc_global_table
 
       // Buffer between READ fsm and IXR_CMD fsm
-      sc_signal<bool>     r_read_to_ixr_cmd_req;      // valid request
-      sc_signal<size_t>   r_read_to_ixr_cmd_index;    // TRT index
+      sc_signal<bool>     r_read_to_ixr_cmd_req;   // valid request
+      sc_signal<size_t>   r_read_to_ixr_cmd_index; // TRT index
 
       // Buffer between READ fsm and TGT_RSP fsm (send a hit read response to L1 cache)
-      sc_signal<bool>     r_read_to_tgt_rsp_req;      // valid request
-      sc_signal<size_t>   r_read_to_tgt_rsp_srcid;    // Transaction srcid
-      sc_signal<size_t>   r_read_to_tgt_rsp_trdid;    // Transaction trdid
-      sc_signal<size_t>   r_read_to_tgt_rsp_pktid;    // Transaction pktid
-      sc_signal<data_t> * r_read_to_tgt_rsp_data;     // data (one cache line)
-      sc_signal<size_t>   r_read_to_tgt_rsp_word;     // first word of the response
-      sc_signal<size_t>   r_read_to_tgt_rsp_length;   // length of the response
-      sc_signal<addr_t>   r_read_to_tgt_rsp_ll_key;   // LL key from llsc_global_table
+      sc_signal<bool>     r_read_to_tgt_rsp_req;    // valid request
+      sc_signal<size_t>   r_read_to_tgt_rsp_srcid;  // Transaction srcid
+      sc_signal<size_t>   r_read_to_tgt_rsp_trdid;  // Transaction trdid
+      sc_signal<size_t>   r_read_to_tgt_rsp_pktid;  // Transaction pktid
+      sc_signal<data_t> * r_read_to_tgt_rsp_data;   // data (one cache line)
+      sc_signal<size_t>   r_read_to_tgt_rsp_word;   // first word of the response
+      sc_signal<size_t>   r_read_to_tgt_rsp_length; // length of the response
+      sc_signal<addr_t>   r_read_to_tgt_rsp_ll_key; // LL key from llsc_global_table
 
       //RWT: Buffer between READ fsm and CC_SEND fsm (send inval)
@@ -777,5 +766,5 @@
 
       //RWT:
-      sc_signal<bool>     r_read_coherent;          // State of the cache slot after transaction
+      sc_signal<bool>     r_read_coherent; // State of the cache slot after transaction
       sc_signal<bool>     r_read_ll_done;
 
@@ -839,9 +828,9 @@
 
       // RWT: Buffer between WRITE fsm and CLEANUP fsm (change slot state)
-      sc_signal<bool>     r_write_to_cleanup_req;         // valid request
-      sc_signal<addr_t>   r_write_to_cleanup_nline;       // cache line index
+      sc_signal<bool>     r_write_to_cleanup_req;    // valid request
+      sc_signal<addr_t>   r_write_to_cleanup_nline;  // cache line index
 
       // RWT
-      sc_signal<bool>     r_write_coherent;               // cache slot state after transaction
+      sc_signal<bool>     r_write_coherent;          // cache slot state after transaction
 
       //Buffer between WRITE fsm and CC_SEND fsm (INVAL for RWT)
@@ -1114,6 +1103,4 @@
 
       sc_signal<bool>      r_cleanup_ncc;
-      sc_signal<bool>      r_cleanup_to_ixr_cmd_ncc_l1_dirty;
-      sc_signal<bool>      r_xram_rsp_to_ixr_cmd_inval_ncc_pending;
 
       sc_signal<bool>      r_cleanup_to_ixr_cmd_req;
