Index: branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
===================================================================
--- branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 805)
+++ branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 824)
@@ -56,5 +56,5 @@
 
 ////////////////////////////////////////////
-template<typename vci_param, 
+template<typename vci_param,
          size_t   dspin_in_width,
          size_t   dspin_out_width,
@@ -67,5 +67,5 @@
     typedef typename vci_param::fast_addr_t  paddr_t;
 
-    enum icache_fsm_state_e 
+    enum icache_fsm_state_e
     {
         ICACHE_IDLE,
@@ -94,5 +94,5 @@
     };
 
-    enum dcache_fsm_state_e 
+    enum dcache_fsm_state_e
     {
         DCACHE_IDLE,
@@ -108,5 +108,5 @@
         DCACHE_TLB_LR_WAIT,
         DCACHE_TLB_RETURN,
-	    // handling processor XTN requests
+        // handling processor XTN requests
         DCACHE_XTN_SWITCH,
         DCACHE_XTN_SYNC,
@@ -128,5 +128,5 @@
         DCACHE_DIRTY_GET_PTE,
         DCACHE_DIRTY_WAIT,
-	    // handling processor miss requests
+        // handling processor miss requests
         DCACHE_MISS_SELECT,
         DCACHE_MISS_CLEAN,
@@ -148,5 +148,5 @@
     };
 
-    enum cmd_fsm_state_e 
+    enum cmd_fsm_state_e
     {
         CMD_IDLE,
@@ -162,5 +162,5 @@
     };
 
-    enum rsp_fsm_state_e 
+    enum rsp_fsm_state_e
     {
         RSP_IDLE,
@@ -173,5 +173,5 @@
     };
 
-    enum cc_receive_fsm_state_e 
+    enum cc_receive_fsm_state_e
     {
         CC_RECEIVE_IDLE,
@@ -190,5 +190,5 @@
     };
 
-    enum cc_send_fsm_state_e 
+    enum cc_send_fsm_state_e
     {
         CC_SEND_IDLE,
@@ -228,5 +228,5 @@
 
     // cc_send_type
-    typedef enum 
+    typedef enum
     {
         CC_TYPE_CLEANUP,
@@ -235,5 +235,5 @@
 
     // cc_receive_type
-    typedef enum 
+    typedef enum
     {
         CC_TYPE_CLACK,
@@ -244,5 +244,5 @@
 
     // TLB Mode : ITLB / DTLB / ICACHE / DCACHE
-    enum 
+    enum
     {
         INS_TLB_MASK    = 0x8,
@@ -256,6 +256,6 @@
     {
         MMU_NONE                      = 0x0000, // None
-        MMU_WRITE_PT1_UNMAPPED 	      = 0x0001, // Write & Page fault on PT1
-        MMU_WRITE_PT2_UNMAPPED 	      = 0x0002, // Write & Page fault on PT2
+        MMU_WRITE_PT1_UNMAPPED        = 0x0001, // Write & Page fault on PT1
+        MMU_WRITE_PT2_UNMAPPED        = 0x0002, // Write & Page fault on PT2
         MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write & Protected access in user mode
         MMU_WRITE_ACCES_VIOLATION     = 0x0008, // Write to non writable page
@@ -264,9 +264,9 @@
         MMU_WRITE_PT2_ILLEGAL_ACCESS  = 0x0080, // Write & Bus Error accessing PT2
         MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write & Bus Error in cache access
-        MMU_READ_PT1_UNMAPPED 	      = 0x1001, // Read & Page fault on PT1
-        MMU_READ_PT2_UNMAPPED 	      = 0x1002, // Read & Page fault on PT2
+        MMU_READ_PT1_UNMAPPED         = 0x1001, // Read & Page fault on PT1
+        MMU_READ_PT2_UNMAPPED         = 0x1002, // Read & Page fault on PT2
         MMU_READ_PRIVILEGE_VIOLATION  = 0x1004, // Read & Protected access in user mode
         MMU_READ_EXEC_VIOLATION       = 0x1010, // Read & Exec access to a non exec page
-        MMU_READ_UNDEFINED_XTN 	      = 0x1020, // Read & Undefined external access
+        MMU_READ_UNDEFINED_XTN        = 0x1020, // Read & Undefined external access
         MMU_READ_PT1_ILLEGAL_ACCESS   = 0x1040, // Read & Bus Error accessing PT1
         MMU_READ_PT2_ILLEGAL_ACCESS   = 0x1080, // Read & Bus Error accessing PT2
@@ -310,21 +310,21 @@
     const size_t                        m_cc_global_id;
     const size_t                        m_nline_width;
-    const size_t  						m_itlb_ways;
-    const size_t  						m_itlb_sets;
-    const size_t  						m_dtlb_ways;
-    const size_t  						m_dtlb_sets;
-    const size_t  						m_icache_ways;
-    const size_t  						m_icache_sets;
-    const paddr_t 						m_icache_yzmask;
-    const size_t  						m_icache_words;
-    const size_t  						m_dcache_ways;
-    const size_t  						m_dcache_sets;
-    const paddr_t 						m_dcache_yzmask;
-    const size_t  						m_dcache_words;
+    const size_t                        m_itlb_ways;
+    const size_t                        m_itlb_sets;
+    const size_t                        m_dtlb_ways;
+    const size_t                        m_dtlb_sets;
+    const size_t                        m_icache_ways;
+    const size_t                        m_icache_sets;
+    const paddr_t                       m_icache_yzmask;
+    const size_t                        m_icache_words;
+    const size_t                        m_dcache_ways;
+    const size_t                        m_dcache_sets;
+    const paddr_t                       m_dcache_yzmask;
+    const size_t                        m_dcache_words;
     const size_t                        m_x_width;
     const size_t                        m_y_width;
     const size_t                        m_proc_id;
-    const uint32_t						m_max_frozen_cycles;
-    const size_t  						m_paddr_nbits;
+    const uint32_t                      m_max_frozen_cycles;
+    const size_t                        m_paddr_nbits;
     uint32_t                            m_debug_start_cycle;
     bool                                m_debug_ok;
@@ -342,5 +342,5 @@
 
     /////////////////////////////////////////////
-    // debug variables 
+    // debug variables
     /////////////////////////////////////////////
     bool                                m_debug_previous_i_hit;
@@ -351,14 +351,14 @@
     // Software visible REGISTERS
     ///////////////////////////////
-    sc_signal<uint32_t>     r_mmu_ptpr;             	// page table pointer register
-    sc_signal<uint32_t>     r_mmu_mode;             	// mmu mode register
-    sc_signal<uint32_t>     r_mmu_word_lo;          	// mmu misc data low
-    sc_signal<uint32_t>     r_mmu_word_hi;          	// mmu misc data hight
-    sc_signal<uint32_t>     r_mmu_ibvar;      	    	// mmu bad instruction address
-    sc_signal<uint32_t>     r_mmu_dbvar;              	// mmu bad data address
-    sc_signal<uint32_t>     r_mmu_ietr;                 // mmu instruction error type
-    sc_signal<uint32_t>     r_mmu_detr;                 // mmu data error type
-    uint32_t	            r_mmu_params;		        // read-only
-    uint32_t	            r_mmu_release;		        // read_only
+    sc_signal<uint32_t>     r_mmu_ptpr;      // page table pointer register
+    sc_signal<uint32_t>     r_mmu_mode;      // mmu mode register
+    sc_signal<uint32_t>     r_mmu_word_lo;   // mmu misc data low
+    sc_signal<uint32_t>     r_mmu_word_hi;   // mmu misc data hight
+    sc_signal<uint32_t>     r_mmu_ibvar;     // mmu bad instruction address
+    sc_signal<uint32_t>     r_mmu_dbvar;     // mmu bad data address
+    sc_signal<uint32_t>     r_mmu_ietr;      // mmu instruction error type
+    sc_signal<uint32_t>     r_mmu_detr;      // mmu data error type
+    uint32_t                r_mmu_params;    // read-only
+    uint32_t                r_mmu_release;   // read_only
 
 
@@ -368,27 +368,27 @@
     sc_signal<int>          r_icache_fsm;               // state register
     sc_signal<int>          r_icache_fsm_save;          // return state for coherence op
-    sc_signal<paddr_t>      r_icache_vci_paddr;      	// physical address
+    sc_signal<paddr_t>      r_icache_vci_paddr;         // physical address
     sc_signal<uint32_t>     r_icache_vaddr_save;        // virtual address from processor
 
     // icache miss handling
-    sc_signal<size_t>       r_icache_miss_way;		    // selected way for cache update
-    sc_signal<size_t>       r_icache_miss_set;		    // selected set for cache update
-    sc_signal<size_t>       r_icache_miss_word;		    // word index ( cache update)
+    sc_signal<size_t>       r_icache_miss_way;          // selected way for cache update
+    sc_signal<size_t>       r_icache_miss_set;          // selected set for cache update
+    sc_signal<size_t>       r_icache_miss_word;         // word index ( cache update)
     sc_signal<bool>         r_icache_miss_inval;        // coherence request matching a miss
     sc_signal<bool>         r_icache_miss_clack;        // waiting for a cleanup acknowledge
 
     // coherence request handling
-    sc_signal<size_t>       r_icache_cc_way;		    // selected way for cc update/inval
-    sc_signal<size_t>       r_icache_cc_set;		    // selected set for cc update/inval
-    sc_signal<size_t>       r_icache_cc_word;		    // word counter for cc update
+    sc_signal<size_t>       r_icache_cc_way;            // selected way for cc update/inval
+    sc_signal<size_t>       r_icache_cc_set;            // selected set for cc update/inval
+    sc_signal<size_t>       r_icache_cc_word;           // word counter for cc update
     sc_signal<bool>         r_icache_cc_need_write;     // activate the cache for writing
 
     // coherence clack handling
     sc_signal<bool>         r_icache_clack_req;         // clack request
-    sc_signal<size_t>       r_icache_clack_way;		    // clack way
-    sc_signal<size_t>       r_icache_clack_set;		    // clack set
+    sc_signal<size_t>       r_icache_clack_way;         // clack way
+    sc_signal<size_t>       r_icache_clack_set;         // clack set
 
     // icache flush handling
-    sc_signal<size_t>       r_icache_flush_count;	    // slot counter used for cache flush
+    sc_signal<size_t>       r_icache_flush_count;       // slot counter used for cache flush
 
     // communication between ICACHE FSM and VCI_CMD FSM
@@ -397,9 +397,9 @@
 
     // communication between ICACHE FSM and DCACHE FSM
-    sc_signal<bool>	        r_icache_tlb_miss_req;       // (set icache/reset dcache)
+    sc_signal<bool>         r_icache_tlb_miss_req;       // (set icache/reset dcache)
     sc_signal<bool>         r_icache_tlb_rsp_error;      // tlb miss response error
 
     // Flip-Flop in ICACHE FSM for saving the cleanup victim request
-    sc_signal<bool>         r_icache_cleanup_victim_req; 
+    sc_signal<bool>         r_icache_cleanup_victim_req;
     sc_signal<paddr_t>      r_icache_cleanup_victim_nline;
 
@@ -427,15 +427,15 @@
     sc_signal<uint32_t>     r_dcache_save_be;           // byte enable (from proc)
     sc_signal<paddr_t>      r_dcache_save_paddr;        // physical address
-    sc_signal<size_t>       r_dcache_save_cache_way;	// selected way (from dcache)
-    sc_signal<size_t>       r_dcache_save_cache_set;	// selected set (from dcache)
-    sc_signal<size_t>       r_dcache_save_cache_word;	// selected word (from dcache)
+    sc_signal<size_t>       r_dcache_save_cache_way;    // selected way (from dcache)
+    sc_signal<size_t>       r_dcache_save_cache_set;    // selected set (from dcache)
+    sc_signal<size_t>       r_dcache_save_cache_word;   // selected word (from dcache)
     // registers used by the Dirty bit sub-fsm
     sc_signal<paddr_t>      r_dcache_dirty_paddr;       // PTE physical address
-    sc_signal<size_t>       r_dcache_dirty_way;	        // way to invalidate in dcache
-    sc_signal<size_t>       r_dcache_dirty_set;	        // set to invalidate in dcache
+    sc_signal<size_t>       r_dcache_dirty_way;         // way to invalidate in dcache
+    sc_signal<size_t>       r_dcache_dirty_set;         // set to invalidate in dcache
 
     // communication between DCACHE FSM and VCI_CMD FSM
-    sc_signal<paddr_t>      r_dcache_vci_paddr;		    // physical address for VCI command
-    sc_signal<uint32_t>     r_dcache_vci_wdata;		    // write unc data for VCI command
+    sc_signal<paddr_t>      r_dcache_vci_paddr;         // physical address for VCI command
+    sc_signal<uint32_t>     r_dcache_vci_wdata;         // write unc data for VCI command
     sc_signal<bool>         r_dcache_vci_miss_req;      // read miss request
     sc_signal<bool>         r_dcache_vci_unc_req;       // uncacheable request (read/write)
@@ -456,20 +456,20 @@
 
     // register used for XTN inval
-    sc_signal<size_t>       r_dcache_xtn_way;		    // selected way (from dcache)
-    sc_signal<size_t>       r_dcache_xtn_set;		    // selected set (from dcache)
+    sc_signal<size_t>       r_dcache_xtn_way;           // selected way (from dcache)
+    sc_signal<size_t>       r_dcache_xtn_set;           // selected set (from dcache)
 
     // handling dcache miss
-    sc_signal<int>	        r_dcache_miss_type;		    // depending on the requester
-    sc_signal<size_t>       r_dcache_miss_word;		    // word index for cache update
-    sc_signal<size_t>       r_dcache_miss_way;		    // selected way for cache update
-    sc_signal<size_t>       r_dcache_miss_set;		    // selected set for cache update
+    sc_signal<int>          r_dcache_miss_type;         // depending on the requester
+    sc_signal<size_t>       r_dcache_miss_word;         // word index for cache update
+    sc_signal<size_t>       r_dcache_miss_way;          // selected way for cache update
+    sc_signal<size_t>       r_dcache_miss_set;          // selected set for cache update
     sc_signal<bool>         r_dcache_miss_inval;        // coherence request matching a miss
     sc_signal<bool>         r_dcache_miss_clack;        // waiting for a cleanup acknowledge
 
     // handling coherence requests
-    sc_signal<size_t>       r_dcache_cc_way;		    // selected way for cc update/inval
-    sc_signal<size_t>       r_dcache_cc_set;		    // selected set for cc update/inval
+    sc_signal<size_t>       r_dcache_cc_way;            // selected way for cc update/inval
+    sc_signal<size_t>       r_dcache_cc_set;            // selected set for cc update/inval
     sc_signal<int>          r_dcache_cc_state;          // state of selected cache slot
-    sc_signal<size_t>       r_dcache_cc_word;		    // word counter for cc update
+    sc_signal<size_t>       r_dcache_cc_word;           // word counter for cc update
     sc_signal<bool>         r_dcache_cc_need_write;     // activate the cache for writing
     sc_signal<paddr_t>      r_dcache_cc_inval_addr;     // address for a cleanup transaction
@@ -478,27 +478,27 @@
     // coherence clack handling
     sc_signal<bool>         r_dcache_clack_req;         // clack request
-    sc_signal<size_t>       r_dcache_clack_way;		    // clack way
-    sc_signal<size_t>       r_dcache_clack_set;		    // clack set
+    sc_signal<size_t>       r_dcache_clack_way;         // clack way
+    sc_signal<size_t>       r_dcache_clack_set;         // clack set
 
     // dcache flush handling
-    sc_signal<size_t>       r_dcache_flush_count;	    // slot counter used for cache flush
+    sc_signal<size_t>       r_dcache_flush_count;       // slot counter used for cache flush
 
     // ll response handling
-    sc_signal<size_t>       r_dcache_ll_rsp_count;	    // flit counter used for ll rsp
+    sc_signal<size_t>       r_dcache_ll_rsp_count;      // flit counter used for ll rsp
 
     // used by the TLB miss sub-fsm
-    sc_signal<uint32_t>     r_dcache_tlb_vaddr;		    // virtual address for a tlb miss
-    sc_signal<bool>         r_dcache_tlb_ins;		    // target tlb (itlb if true)
-    sc_signal<paddr_t>      r_dcache_tlb_paddr;		    // physical address of pte
-    sc_signal<uint32_t>     r_dcache_tlb_pte_flags;	    // pte1 or first word of pte2
-    sc_signal<uint32_t>     r_dcache_tlb_pte_ppn;	    // second word of pte2
-    sc_signal<size_t>       r_dcache_tlb_cache_way;	    // selected way in dcache
-    sc_signal<size_t>       r_dcache_tlb_cache_set;	    // selected set in dcache
-    sc_signal<size_t>       r_dcache_tlb_cache_word;	// selected word in dcache
-    sc_signal<size_t>       r_dcache_tlb_way;		    // selected way in tlb
-    sc_signal<size_t>       r_dcache_tlb_set;		    // selected set in tlb
+    sc_signal<uint32_t>     r_dcache_tlb_vaddr;         // virtual address for a tlb miss
+    sc_signal<bool>         r_dcache_tlb_ins;           // target tlb (itlb if true)
+    sc_signal<paddr_t>      r_dcache_tlb_paddr;         // physical address of pte
+    sc_signal<uint32_t>     r_dcache_tlb_pte_flags;     // pte1 or first word of pte2
+    sc_signal<uint32_t>     r_dcache_tlb_pte_ppn;       // second word of pte2
+    sc_signal<size_t>       r_dcache_tlb_cache_way;     // selected way in dcache
+    sc_signal<size_t>       r_dcache_tlb_cache_set;     // selected set in dcache
+    sc_signal<size_t>       r_dcache_tlb_cache_word;    // selected word in dcache
+    sc_signal<size_t>       r_dcache_tlb_way;           // selected way in tlb
+    sc_signal<size_t>       r_dcache_tlb_set;           // selected set in tlb
 
     // ITLB and DTLB invalidation
-    sc_signal<paddr_t>      r_dcache_tlb_inval_line;	// line index
+    sc_signal<paddr_t>      r_dcache_tlb_inval_line;    // line index
     sc_signal<size_t>       r_dcache_tlb_inval_set;     // tlb set counter
 
@@ -508,5 +508,5 @@
 
     // Filp-Flop in DCACHE FSM for saving the cleanup victim request
-    sc_signal<bool>         r_dcache_cleanup_victim_req; 
+    sc_signal<bool>         r_dcache_cleanup_victim_req;
     sc_signal<bool>         r_dcache_cleanup_victim_line_ncc;
     sc_signal<bool>         r_dcache_cleanup_victim_updt_data;
@@ -551,8 +551,8 @@
     ///////////////////////////////////
     sc_signal<int>          r_vci_cmd_fsm;
-    sc_signal<size_t>       r_vci_cmd_min;      	        // used for write bursts
-    sc_signal<size_t>       r_vci_cmd_max;      	        // used for write bursts
-    sc_signal<size_t>       r_vci_cmd_cpt;    		        // used for write bursts
-    sc_signal<bool>         r_vci_cmd_imiss_prio;	        // round-robin between imiss & dmiss
+    sc_signal<size_t>       r_vci_cmd_min;                  // used for write bursts
+    sc_signal<size_t>       r_vci_cmd_max;                  // used for write bursts
+    sc_signal<size_t>       r_vci_cmd_cpt;                  // used for write bursts
+    sc_signal<bool>         r_vci_cmd_imiss_prio;           // round-robin between imiss & dmiss
 
     ///////////////////////////////////
@@ -563,6 +563,6 @@
     sc_signal<bool>         r_vci_rsp_ins_error;
     sc_signal<bool>         r_vci_rsp_data_error;
-    GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;	        // response FIFO to ICACHE FSM
-    GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;	        // response FIFO to DCACHE FSM
+    GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;          // response FIFO to ICACHE FSM
+    GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;          // response FIFO to DCACHE FSM
 
 
@@ -595,5 +595,5 @@
     sc_signal<size_t>       r_cc_receive_icache_set;        // cc_receive to icache set
     sc_signal<size_t>       r_cc_receive_icache_updt_tab_idx;  // cc_receive update table index
-    sc_signal<paddr_t>      r_cc_receive_icache_nline;	    // cache line physical address
+    sc_signal<paddr_t>      r_cc_receive_icache_nline;      // cache line physical address
 
     // communication between CC_RECEIVE FSM and DCACHE FSM
@@ -603,5 +603,5 @@
     sc_signal<size_t>       r_cc_receive_dcache_set;              // cc_receive to dcache set
     sc_signal<size_t>       r_cc_receive_dcache_updt_tab_idx;     // cc_receive update table index
-    sc_signal<paddr_t>      r_cc_receive_dcache_nline;	          // cache line physical address
+    sc_signal<paddr_t>      r_cc_receive_dcache_nline;            // cache line physical address
     sc_signal<bool>         r_cc_receive_dcache_inval_is_config;  // inval from memcache is config
 
@@ -611,5 +611,5 @@
     sc_signal<bool>         r_dspin_clack_req;
     sc_signal<uint64_t>     r_dspin_clack_flit;
-    
+
     //////////////////////////////////////////////////////////////////
     // processor, write buffer, caches , TLBs
@@ -617,9 +617,9 @@
 
     iss_t                       r_iss;
-    MultiWriteBuffer<paddr_t>	r_wbuf;
-    GenericCache<paddr_t>   	r_icache;
-    GenericCache<paddr_t>    	r_dcache;
-    GenericTlb<paddr_t>       	r_itlb;
-    GenericTlb<paddr_t>     	r_dtlb;
+    MultiWriteBuffer<paddr_t>   r_wbuf;
+    GenericCache<paddr_t>       r_icache;
+    GenericCache<paddr_t>       r_dcache;
+    GenericTlb<paddr_t>         r_itlb;
+    GenericTlb<paddr_t>         r_dtlb;
 
     //////////////////////////////////////////////////////////////////
@@ -648,6 +648,6 @@
     uint32_t m_cpt_icache_dir_write;           // ICACHE DIR WRITE
 
-    uint32_t m_cpt_frz_cycles;	               // number of cycles where the cpu is frozen
-    uint32_t m_cpt_total_cycles;	           // total number of cycles
+    uint32_t m_cpt_frz_cycles;                 // number of cycles where the cpu is frozen
+    uint32_t m_cpt_total_cycles;               // total number of cycles
 
     // Cache activity counters
@@ -764,8 +764,8 @@
     uint32_t m_cpt_fsm_cc_send    [64];
 
-    uint32_t m_cpt_stop_simulation;		// used to stop simulation if frozen
-    bool     m_monitor_ok;		        // used to debug cache output  
-    uint32_t m_monitor_base;		    
-    uint32_t m_monitor_length;		    
+    uint32_t m_cpt_stop_simulation;     // used to stop simulation if frozen
+    bool     m_monitor_ok;              // used to debug cache output
+    uint32_t m_monitor_base;
+    uint32_t m_monitor_length;
 
 protected:
@@ -807,7 +807,7 @@
     void start_monitor(paddr_t,paddr_t);
     void stop_monitor();
-    inline void iss_set_debug_mask(uint v) 
-    {
-	    r_iss.set_debug_mask(v);
+    inline void iss_set_debug_mask(uint v)
+    {
+        r_iss.set_debug_mask(v);
     }
 
