Index: branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
===================================================================
--- branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 805)
+++ branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 824)
@@ -56,5 +56,5 @@
 
 ////////////////////////////////////////////
-template<typename vci_param, 
+template<typename vci_param,
          size_t   dspin_in_width,
          size_t   dspin_out_width,
@@ -67,5 +67,5 @@
     typedef typename vci_param::fast_addr_t  paddr_t;
 
-    enum icache_fsm_state_e 
+    enum icache_fsm_state_e
     {
         ICACHE_IDLE,
@@ -94,5 +94,5 @@
     };
 
-    enum dcache_fsm_state_e 
+    enum dcache_fsm_state_e
     {
         DCACHE_IDLE,
@@ -108,5 +108,5 @@
         DCACHE_TLB_LR_WAIT,
         DCACHE_TLB_RETURN,
-	    // handling processor XTN requests
+        // handling processor XTN requests
         DCACHE_XTN_SWITCH,
         DCACHE_XTN_SYNC,
@@ -128,5 +128,5 @@
         DCACHE_DIRTY_GET_PTE,
         DCACHE_DIRTY_WAIT,
-	    // handling processor miss requests
+        // handling processor miss requests
         DCACHE_MISS_SELECT,
         DCACHE_MISS_CLEAN,
@@ -148,5 +148,5 @@
     };
 
-    enum cmd_fsm_state_e 
+    enum cmd_fsm_state_e
     {
         CMD_IDLE,
@@ -162,5 +162,5 @@
     };
 
-    enum rsp_fsm_state_e 
+    enum rsp_fsm_state_e
     {
         RSP_IDLE,
@@ -173,5 +173,5 @@
     };
 
-    enum cc_receive_fsm_state_e 
+    enum cc_receive_fsm_state_e
     {
         CC_RECEIVE_IDLE,
@@ -190,5 +190,5 @@
     };
 
-    enum cc_send_fsm_state_e 
+    enum cc_send_fsm_state_e
     {
         CC_SEND_IDLE,
@@ -228,5 +228,5 @@
 
     // cc_send_type
-    typedef enum 
+    typedef enum
     {
         CC_TYPE_CLEANUP,
@@ -235,5 +235,5 @@
 
     // cc_receive_type
-    typedef enum 
+    typedef enum
     {
         CC_TYPE_CLACK,
@@ -244,5 +244,5 @@
 
     // TLB Mode : ITLB / DTLB / ICACHE / DCACHE
-    enum 
+    enum
     {
         INS_TLB_MASK    = 0x8,
@@ -256,6 +256,6 @@
     {
         MMU_NONE                      = 0x0000, // None
-        MMU_WRITE_PT1_UNMAPPED 	      = 0x0001, // Write & Page fault on PT1
-        MMU_WRITE_PT2_UNMAPPED 	      = 0x0002, // Write & Page fault on PT2
+        MMU_WRITE_PT1_UNMAPPED        = 0x0001, // Write & Page fault on PT1
+        MMU_WRITE_PT2_UNMAPPED        = 0x0002, // Write & Page fault on PT2
         MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write & Protected access in user mode
         MMU_WRITE_ACCES_VIOLATION     = 0x0008, // Write to non writable page
@@ -264,9 +264,9 @@
         MMU_WRITE_PT2_ILLEGAL_ACCESS  = 0x0080, // Write & Bus Error accessing PT2
         MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write & Bus Error in cache access
-        MMU_READ_PT1_UNMAPPED 	      = 0x1001, // Read & Page fault on PT1
-        MMU_READ_PT2_UNMAPPED 	      = 0x1002, // Read & Page fault on PT2
+        MMU_READ_PT1_UNMAPPED         = 0x1001, // Read & Page fault on PT1
+        MMU_READ_PT2_UNMAPPED         = 0x1002, // Read & Page fault on PT2
         MMU_READ_PRIVILEGE_VIOLATION  = 0x1004, // Read & Protected access in user mode
         MMU_READ_EXEC_VIOLATION       = 0x1010, // Read & Exec access to a non exec page
-        MMU_READ_UNDEFINED_XTN 	      = 0x1020, // Read & Undefined external access
+        MMU_READ_UNDEFINED_XTN        = 0x1020, // Read & Undefined external access
         MMU_READ_PT1_ILLEGAL_ACCESS   = 0x1040, // Read & Bus Error accessing PT1
         MMU_READ_PT2_ILLEGAL_ACCESS   = 0x1080, // Read & Bus Error accessing PT2
@@ -310,21 +310,21 @@
     const size_t                        m_cc_global_id;
     const size_t                        m_nline_width;
-    const size_t  						m_itlb_ways;
-    const size_t  						m_itlb_sets;
-    const size_t  						m_dtlb_ways;
-    const size_t  						m_dtlb_sets;
-    const size_t  						m_icache_ways;
-    const size_t  						m_icache_sets;
-    const paddr_t 						m_icache_yzmask;
-    const size_t  						m_icache_words;
-    const size_t  						m_dcache_ways;
-    const size_t  						m_dcache_sets;
-    const paddr_t 						m_dcache_yzmask;
-    const size_t  						m_dcache_words;
+    const size_t                        m_itlb_ways;
+    const size_t                        m_itlb_sets;
+    const size_t                        m_dtlb_ways;
+    const size_t                        m_dtlb_sets;
+    const size_t                        m_icache_ways;
+    const size_t                        m_icache_sets;
+    const paddr_t                       m_icache_yzmask;
+    const size_t                        m_icache_words;
+    const size_t                        m_dcache_ways;
+    const size_t                        m_dcache_sets;
+    const paddr_t                       m_dcache_yzmask;
+    const size_t                        m_dcache_words;
     const size_t                        m_x_width;
     const size_t                        m_y_width;
     const size_t                        m_proc_id;
-    const uint32_t						m_max_frozen_cycles;
-    const size_t  						m_paddr_nbits;
+    const uint32_t                      m_max_frozen_cycles;
+    const size_t                        m_paddr_nbits;
     uint32_t                            m_debug_start_cycle;
     bool                                m_debug_ok;
@@ -342,5 +342,5 @@
 
     /////////////////////////////////////////////
-    // debug variables 
+    // debug variables
     /////////////////////////////////////////////
     bool                                m_debug_previous_i_hit;
@@ -351,14 +351,14 @@
     // Software visible REGISTERS
     ///////////////////////////////
-    sc_signal<uint32_t>     r_mmu_ptpr;             	// page table pointer register
-    sc_signal<uint32_t>     r_mmu_mode;             	// mmu mode register
-    sc_signal<uint32_t>     r_mmu_word_lo;          	// mmu misc data low
-    sc_signal<uint32_t>     r_mmu_word_hi;          	// mmu misc data hight
-    sc_signal<uint32_t>     r_mmu_ibvar;      	    	// mmu bad instruction address
-    sc_signal<uint32_t>     r_mmu_dbvar;              	// mmu bad data address
-    sc_signal<uint32_t>     r_mmu_ietr;                 // mmu instruction error type
-    sc_signal<uint32_t>     r_mmu_detr;                 // mmu data error type
-    uint32_t	            r_mmu_params;		        // read-only
-    uint32_t	            r_mmu_release;		        // read_only
+    sc_signal<uint32_t>     r_mmu_ptpr;      // page table pointer register
+    sc_signal<uint32_t>     r_mmu_mode;      // mmu mode register
+    sc_signal<uint32_t>     r_mmu_word_lo;   // mmu misc data low
+    sc_signal<uint32_t>     r_mmu_word_hi;   // mmu misc data hight
+    sc_signal<uint32_t>     r_mmu_ibvar;     // mmu bad instruction address
+    sc_signal<uint32_t>     r_mmu_dbvar;     // mmu bad data address
+    sc_signal<uint32_t>     r_mmu_ietr;      // mmu instruction error type
+    sc_signal<uint32_t>     r_mmu_detr;      // mmu data error type
+    uint32_t                r_mmu_params;    // read-only
+    uint32_t                r_mmu_release;   // read_only
 
 
@@ -368,27 +368,27 @@
     sc_signal<int>          r_icache_fsm;               // state register
     sc_signal<int>          r_icache_fsm_save;          // return state for coherence op
-    sc_signal<paddr_t>      r_icache_vci_paddr;      	// physical address
+    sc_signal<paddr_t>      r_icache_vci_paddr;         // physical address
     sc_signal<uint32_t>     r_icache_vaddr_save;        // virtual address from processor
 
     // icache miss handling
-    sc_signal<size_t>       r_icache_miss_way;		    // selected way for cache update
-    sc_signal<size_t>       r_icache_miss_set;		    // selected set for cache update
-    sc_signal<size_t>       r_icache_miss_word;		    // word index ( cache update)
+    sc_signal<size_t>       r_icache_miss_way;          // selected way for cache update
+    sc_signal<size_t>       r_icache_miss_set;          // selected set for cache update
+    sc_signal<size_t>       r_icache_miss_word;         // word index ( cache update)
     sc_signal<bool>         r_icache_miss_inval;        // coherence request matching a miss
     sc_signal<bool>         r_icache_miss_clack;        // waiting for a cleanup acknowledge
 
     // coherence request handling
-    sc_signal<size_t>       r_icache_cc_way;		    // selected way for cc update/inval
-    sc_signal<size_t>       r_icache_cc_set;		    // selected set for cc update/inval
-    sc_signal<size_t>       r_icache_cc_word;		    // word counter for cc update
+    sc_signal<size_t>       r_icache_cc_way;            // selected way for cc update/inval
+    sc_signal<size_t>       r_icache_cc_set;            // selected set for cc update/inval
+    sc_signal<size_t>       r_icache_cc_word;           // word counter for cc update
     sc_signal<bool>         r_icache_cc_need_write;     // activate the cache for writing
 
     // coherence clack handling
     sc_signal<bool>         r_icache_clack_req;         // clack request
-    sc_signal<size_t>       r_icache_clack_way;		    // clack way
-    sc_signal<size_t>       r_icache_clack_set;		    // clack set
+    sc_signal<size_t>       r_icache_clack_way;         // clack way
+    sc_signal<size_t>       r_icache_clack_set;         // clack set
 
     // icache flush handling
-    sc_signal<size_t>       r_icache_flush_count;	    // slot counter used for cache flush
+    sc_signal<size_t>       r_icache_flush_count;       // slot counter used for cache flush
 
     // communication between ICACHE FSM and VCI_CMD FSM
@@ -397,9 +397,9 @@
 
     // communication between ICACHE FSM and DCACHE FSM
-    sc_signal<bool>	        r_icache_tlb_miss_req;       // (set icache/reset dcache)
+    sc_signal<bool>         r_icache_tlb_miss_req;       // (set icache/reset dcache)
     sc_signal<bool>         r_icache_tlb_rsp_error;      // tlb miss response error
 
     // Flip-Flop in ICACHE FSM for saving the cleanup victim request
-    sc_signal<bool>         r_icache_cleanup_victim_req; 
+    sc_signal<bool>         r_icache_cleanup_victim_req;
     sc_signal<paddr_t>      r_icache_cleanup_victim_nline;
 
@@ -427,15 +427,15 @@
     sc_signal<uint32_t>     r_dcache_save_be;           // byte enable (from proc)
     sc_signal<paddr_t>      r_dcache_save_paddr;        // physical address
-    sc_signal<size_t>       r_dcache_save_cache_way;	// selected way (from dcache)
-    sc_signal<size_t>       r_dcache_save_cache_set;	// selected set (from dcache)
-    sc_signal<size_t>       r_dcache_save_cache_word;	// selected word (from dcache)
+    sc_signal<size_t>       r_dcache_save_cache_way;    // selected way (from dcache)
+    sc_signal<size_t>       r_dcache_save_cache_set;    // selected set (from dcache)
+    sc_signal<size_t>       r_dcache_save_cache_word;   // selected word (from dcache)
     // registers used by the Dirty bit sub-fsm
     sc_signal<paddr_t>      r_dcache_dirty_paddr;       // PTE physical address
-    sc_signal<size_t>       r_dcache_dirty_way;	        // way to invalidate in dcache
-    sc_signal<size_t>       r_dcache_dirty_set;	        // set to invalidate in dcache
+    sc_signal<size_t>       r_dcache_dirty_way;         // way to invalidate in dcache
+    sc_signal<size_t>       r_dcache_dirty_set;         // set to invalidate in dcache
 
     // communication between DCACHE FSM and VCI_CMD FSM
-    sc_signal<paddr_t>      r_dcache_vci_paddr;		    // physical address for VCI command
-    sc_signal<uint32_t>     r_dcache_vci_wdata;		    // write unc data for VCI command
+    sc_signal<paddr_t>      r_dcache_vci_paddr;         // physical address for VCI command
+    sc_signal<uint32_t>     r_dcache_vci_wdata;         // write unc data for VCI command
     sc_signal<bool>         r_dcache_vci_miss_req;      // read miss request
     sc_signal<bool>         r_dcache_vci_unc_req;       // uncacheable request (read/write)
@@ -456,20 +456,20 @@
 
     // register used for XTN inval
-    sc_signal<size_t>       r_dcache_xtn_way;		    // selected way (from dcache)
-    sc_signal<size_t>       r_dcache_xtn_set;		    // selected set (from dcache)
+    sc_signal<size_t>       r_dcache_xtn_way;           // selected way (from dcache)
+    sc_signal<size_t>       r_dcache_xtn_set;           // selected set (from dcache)
 
     // handling dcache miss
-    sc_signal<int>	        r_dcache_miss_type;		    // depending on the requester
-    sc_signal<size_t>       r_dcache_miss_word;		    // word index for cache update
-    sc_signal<size_t>       r_dcache_miss_way;		    // selected way for cache update
-    sc_signal<size_t>       r_dcache_miss_set;		    // selected set for cache update
+    sc_signal<int>          r_dcache_miss_type;         // depending on the requester
+    sc_signal<size_t>       r_dcache_miss_word;         // word index for cache update
+    sc_signal<size_t>       r_dcache_miss_way;          // selected way for cache update
+    sc_signal<size_t>       r_dcache_miss_set;          // selected set for cache update
     sc_signal<bool>         r_dcache_miss_inval;        // coherence request matching a miss
     sc_signal<bool>         r_dcache_miss_clack;        // waiting for a cleanup acknowledge
 
     // handling coherence requests
-    sc_signal<size_t>       r_dcache_cc_way;		    // selected way for cc update/inval
-    sc_signal<size_t>       r_dcache_cc_set;		    // selected set for cc update/inval
+    sc_signal<size_t>       r_dcache_cc_way;            // selected way for cc update/inval
+    sc_signal<size_t>       r_dcache_cc_set;            // selected set for cc update/inval
     sc_signal<int>          r_dcache_cc_state;          // state of selected cache slot
-    sc_signal<size_t>       r_dcache_cc_word;		    // word counter for cc update
+    sc_signal<size_t>       r_dcache_cc_word;           // word counter for cc update
     sc_signal<bool>         r_dcache_cc_need_write;     // activate the cache for writing
     sc_signal<paddr_t>      r_dcache_cc_inval_addr;     // address for a cleanup transaction
@@ -478,27 +478,27 @@
     // coherence clack handling
     sc_signal<bool>         r_dcache_clack_req;         // clack request
-    sc_signal<size_t>       r_dcache_clack_way;		    // clack way
-    sc_signal<size_t>       r_dcache_clack_set;		    // clack set
+    sc_signal<size_t>       r_dcache_clack_way;         // clack way
+    sc_signal<size_t>       r_dcache_clack_set;         // clack set
 
     // dcache flush handling
-    sc_signal<size_t>       r_dcache_flush_count;	    // slot counter used for cache flush
+    sc_signal<size_t>       r_dcache_flush_count;       // slot counter used for cache flush
 
     // ll response handling
-    sc_signal<size_t>       r_dcache_ll_rsp_count;	    // flit counter used for ll rsp
+    sc_signal<size_t>       r_dcache_ll_rsp_count;      // flit counter used for ll rsp
 
     // used by the TLB miss sub-fsm
-    sc_signal<uint32_t>     r_dcache_tlb_vaddr;		    // virtual address for a tlb miss
-    sc_signal<bool>         r_dcache_tlb_ins;		    // target tlb (itlb if true)
-    sc_signal<paddr_t>      r_dcache_tlb_paddr;		    // physical address of pte
-    sc_signal<uint32_t>     r_dcache_tlb_pte_flags;	    // pte1 or first word of pte2
-    sc_signal<uint32_t>     r_dcache_tlb_pte_ppn;	    // second word of pte2
-    sc_signal<size_t>       r_dcache_tlb_cache_way;	    // selected way in dcache
-    sc_signal<size_t>       r_dcache_tlb_cache_set;	    // selected set in dcache
-    sc_signal<size_t>       r_dcache_tlb_cache_word;	// selected word in dcache
-    sc_signal<size_t>       r_dcache_tlb_way;		    // selected way in tlb
-    sc_signal<size_t>       r_dcache_tlb_set;		    // selected set in tlb
+    sc_signal<uint32_t>     r_dcache_tlb_vaddr;         // virtual address for a tlb miss
+    sc_signal<bool>         r_dcache_tlb_ins;           // target tlb (itlb if true)
+    sc_signal<paddr_t>      r_dcache_tlb_paddr;         // physical address of pte
+    sc_signal<uint32_t>     r_dcache_tlb_pte_flags;     // pte1 or first word of pte2
+    sc_signal<uint32_t>     r_dcache_tlb_pte_ppn;       // second word of pte2
+    sc_signal<size_t>       r_dcache_tlb_cache_way;     // selected way in dcache
+    sc_signal<size_t>       r_dcache_tlb_cache_set;     // selected set in dcache
+    sc_signal<size_t>       r_dcache_tlb_cache_word;    // selected word in dcache
+    sc_signal<size_t>       r_dcache_tlb_way;           // selected way in tlb
+    sc_signal<size_t>       r_dcache_tlb_set;           // selected set in tlb
 
     // ITLB and DTLB invalidation
-    sc_signal<paddr_t>      r_dcache_tlb_inval_line;	// line index
+    sc_signal<paddr_t>      r_dcache_tlb_inval_line;    // line index
     sc_signal<size_t>       r_dcache_tlb_inval_set;     // tlb set counter
 
@@ -508,5 +508,5 @@
 
     // Filp-Flop in DCACHE FSM for saving the cleanup victim request
-    sc_signal<bool>         r_dcache_cleanup_victim_req; 
+    sc_signal<bool>         r_dcache_cleanup_victim_req;
     sc_signal<bool>         r_dcache_cleanup_victim_line_ncc;
     sc_signal<bool>         r_dcache_cleanup_victim_updt_data;
@@ -551,8 +551,8 @@
     ///////////////////////////////////
     sc_signal<int>          r_vci_cmd_fsm;
-    sc_signal<size_t>       r_vci_cmd_min;      	        // used for write bursts
-    sc_signal<size_t>       r_vci_cmd_max;      	        // used for write bursts
-    sc_signal<size_t>       r_vci_cmd_cpt;    		        // used for write bursts
-    sc_signal<bool>         r_vci_cmd_imiss_prio;	        // round-robin between imiss & dmiss
+    sc_signal<size_t>       r_vci_cmd_min;                  // used for write bursts
+    sc_signal<size_t>       r_vci_cmd_max;                  // used for write bursts
+    sc_signal<size_t>       r_vci_cmd_cpt;                  // used for write bursts
+    sc_signal<bool>         r_vci_cmd_imiss_prio;           // round-robin between imiss & dmiss
 
     ///////////////////////////////////
@@ -563,6 +563,6 @@
     sc_signal<bool>         r_vci_rsp_ins_error;
     sc_signal<bool>         r_vci_rsp_data_error;
-    GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;	        // response FIFO to ICACHE FSM
-    GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;	        // response FIFO to DCACHE FSM
+    GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;          // response FIFO to ICACHE FSM
+    GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;          // response FIFO to DCACHE FSM
 
 
@@ -595,5 +595,5 @@
     sc_signal<size_t>       r_cc_receive_icache_set;        // cc_receive to icache set
     sc_signal<size_t>       r_cc_receive_icache_updt_tab_idx;  // cc_receive update table index
-    sc_signal<paddr_t>      r_cc_receive_icache_nline;	    // cache line physical address
+    sc_signal<paddr_t>      r_cc_receive_icache_nline;      // cache line physical address
 
     // communication between CC_RECEIVE FSM and DCACHE FSM
@@ -603,5 +603,5 @@
     sc_signal<size_t>       r_cc_receive_dcache_set;              // cc_receive to dcache set
     sc_signal<size_t>       r_cc_receive_dcache_updt_tab_idx;     // cc_receive update table index
-    sc_signal<paddr_t>      r_cc_receive_dcache_nline;	          // cache line physical address
+    sc_signal<paddr_t>      r_cc_receive_dcache_nline;            // cache line physical address
     sc_signal<bool>         r_cc_receive_dcache_inval_is_config;  // inval from memcache is config
 
@@ -611,5 +611,5 @@
     sc_signal<bool>         r_dspin_clack_req;
     sc_signal<uint64_t>     r_dspin_clack_flit;
-    
+
     //////////////////////////////////////////////////////////////////
     // processor, write buffer, caches , TLBs
@@ -617,9 +617,9 @@
 
     iss_t                       r_iss;
-    MultiWriteBuffer<paddr_t>	r_wbuf;
-    GenericCache<paddr_t>   	r_icache;
-    GenericCache<paddr_t>    	r_dcache;
-    GenericTlb<paddr_t>       	r_itlb;
-    GenericTlb<paddr_t>     	r_dtlb;
+    MultiWriteBuffer<paddr_t>   r_wbuf;
+    GenericCache<paddr_t>       r_icache;
+    GenericCache<paddr_t>       r_dcache;
+    GenericTlb<paddr_t>         r_itlb;
+    GenericTlb<paddr_t>         r_dtlb;
 
     //////////////////////////////////////////////////////////////////
@@ -648,6 +648,6 @@
     uint32_t m_cpt_icache_dir_write;           // ICACHE DIR WRITE
 
-    uint32_t m_cpt_frz_cycles;	               // number of cycles where the cpu is frozen
-    uint32_t m_cpt_total_cycles;	           // total number of cycles
+    uint32_t m_cpt_frz_cycles;                 // number of cycles where the cpu is frozen
+    uint32_t m_cpt_total_cycles;               // total number of cycles
 
     // Cache activity counters
@@ -764,8 +764,8 @@
     uint32_t m_cpt_fsm_cc_send    [64];
 
-    uint32_t m_cpt_stop_simulation;		// used to stop simulation if frozen
-    bool     m_monitor_ok;		        // used to debug cache output  
-    uint32_t m_monitor_base;		    
-    uint32_t m_monitor_length;		    
+    uint32_t m_cpt_stop_simulation;     // used to stop simulation if frozen
+    bool     m_monitor_ok;              // used to debug cache output
+    uint32_t m_monitor_base;
+    uint32_t m_monitor_length;
 
 protected:
@@ -807,7 +807,7 @@
     void start_monitor(paddr_t,paddr_t);
     void stop_monitor();
-    inline void iss_set_debug_mask(uint v) 
-    {
-	    r_iss.set_debug_mask(v);
+    inline void iss_set_debug_mask(uint v)
+    {
+        r_iss.set_debug_mask(v);
     }
 
Index: branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
===================================================================
--- branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 805)
+++ branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 824)
@@ -34,7 +34,7 @@
 #include "../include/vci_cc_vcache_wrapper.h"
 
-#define DEBUG_DCACHE		1
-#define DEBUG_ICACHE		1
-#define DEBUG_CMD   		0
+#define DEBUG_DCACHE        1
+#define DEBUG_ICACHE        1
+#define DEBUG_CMD           0
 #define INSTRUMENTATION     1
 
@@ -137,6 +137,6 @@
 const char *vci_pktid_type_str[] = {
         "TYPE_DATA_UNC",
-        "TYPE_READ_DATA_MISS",            
-        "TYPE_READ_INS_UNC",          
+        "TYPE_READ_DATA_MISS",
+        "TYPE_READ_INS_UNC",
         "TYPE_READ_INS_MISS",
         "TYPE_WRITE",
@@ -199,26 +199,26 @@
 /////////////////////////////////
 tmpl(/**/)::VciCcVCacheWrapper(
-    sc_module_name 			name,
-    const int 				proc_id,
-    const MappingTable 	    &mtd,
-    const IntTab 	        &srcid,
-    const size_t 	        cc_global_id,
-    const size_t 			itlb_ways,
-    const size_t 			itlb_sets,
-    const size_t 			dtlb_ways,
-    const size_t 			dtlb_sets,
-    const size_t 			icache_ways,
-    const size_t 			icache_sets,
-    const size_t 			icache_words,
-    const size_t 			dcache_ways,
-    const size_t 			dcache_sets,
-    const size_t 			dcache_words,
-    const size_t 			wbuf_nlines,
-    const size_t 			wbuf_nwords,
-    const size_t			x_width,
-    const size_t			y_width,
-    const uint32_t			max_frozen_cycles,
-    const uint32_t			debug_start_cycle,
-    const bool				debug_ok )
+    sc_module_name          name,
+    const int               proc_id,
+    const MappingTable      &mtd,
+    const IntTab            &srcid,
+    const size_t            cc_global_id,
+    const size_t            itlb_ways,
+    const size_t            itlb_sets,
+    const size_t            dtlb_ways,
+    const size_t            dtlb_sets,
+    const size_t            icache_ways,
+    const size_t            icache_sets,
+    const size_t            icache_words,
+    const size_t            dcache_ways,
+    const size_t            dcache_sets,
+    const size_t            dcache_words,
+    const size_t            wbuf_nlines,
+    const size_t            wbuf_nwords,
+    const size_t            x_width,
+    const size_t            y_width,
+    const uint32_t          max_frozen_cycles,
+    const uint32_t          debug_start_cycle,
+    const bool              debug_ok )
     : soclib::caba::BaseModule(name),
 
@@ -379,6 +379,6 @@
       r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
       r_vci_rsp_data_error("r_vci_rsp_data_error"),
-      r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2),	// 2 words depth
-      r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2),	// 2 words depth
+      r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2),    // 2 words depth
+      r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2),    // 2 words depth
       r_vci_rsp_fifo_rpktid("r_vci_rsp_fifo_rpktid", 2),    // 2 words depth
       r_cc_send_data_fifo("r_cc_send_data_fifo", 16),
@@ -390,7 +390,7 @@
       r_cc_receive_data_ins("r_cc_receive_data_ins"),
       r_cc_receive_word_idx("r_cc_receive_word_idx"),
-      r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2),	// 2 words depth
-      r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2),	// 2 words depth
-      r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2),	// 2 words depth
+      r_cc_receive_updt_fifo_be("r_cc_receive_updt_fifo_be", 2),     // 2 words depth
+      r_cc_receive_updt_fifo_data("r_cc_receive_updt_fifo_data", 2), // 2 words depth
+      r_cc_receive_updt_fifo_eop("r_cc_receive_updt_fifo_eop", 2),   // 2 words depth
 
       r_cc_receive_icache_req("r_cc_receive_icache_req"),
@@ -559,8 +559,8 @@
 {
     bool        cache_hit;
-    size_t	    cache_way = 0;
-    size_t	    cache_set = 0;
-    size_t	    cache_word = 0;
-    uint32_t	cache_rdata = 0;
+    size_t      cache_way = 0;
+    size_t      cache_set = 0;
+    size_t      cache_word = 0;
+    uint32_t    cache_rdata = 0;
 
     cache_hit = r_dcache.read_neutral( addr,
@@ -574,9 +574,9 @@
         std::cout << "Monitor PROC " << name()
                   << " DCACHE at cycle " << std::dec << m_cpt_total_cycles
-                  << " / HIT = " << cache_hit 
+                  << " / HIT = " << cache_hit
                   << " / PADDR = " << std::hex << addr
-                  << " / DATA = " << cache_rdata 
+                  << " / DATA = " << cache_rdata
                   << " / WAY = " << cache_way << std::endl;
-	    m_debug_previous_d_hit = cache_hit;
+        m_debug_previous_d_hit = cache_hit;
     }
 
@@ -591,9 +591,9 @@
         std::cout << "Monitor PROC " << name()
                   << " ICACHE at cycle " << std::dec << m_cpt_total_cycles
-                  << " / HIT = " << cache_hit 
+                  << " / HIT = " << cache_hit
                   << " / PADDR = " << std::hex << addr
-                  << " / DATA = " << cache_rdata 
+                  << " / DATA = " << cache_rdata
                   << " / WAY = " << cache_way << std::endl;
-	    m_debug_previous_i_hit = cache_hit;
+        m_debug_previous_i_hit = cache_hit;
     }
 }
@@ -810,5 +810,5 @@
         r_mmu_mode = 0x3;
 
-	    // No request from ICACHE FSM to CMD FSM
+        // No request from ICACHE FSM to CMD FSM
         r_icache_miss_req          = false;
         r_icache_unc_req           = false;
@@ -865,5 +865,5 @@
         m_debug_previous_i_hit     = false;
         m_debug_previous_d_hit     = false;
-        m_debug_activated	       = false;
+        m_debug_activated          = false;
 
         // SPECIAL REGISTERS ODCCP
@@ -944,18 +944,18 @@
         m_cost_data_tlb_occup_cache_frz  = 0;
 
-    	m_cpt_ins_tlb_inval       = 0;
-    	m_cpt_data_tlb_inval      = 0;
-    	m_cost_ins_tlb_inval_frz  = 0;
-    	m_cost_data_tlb_inval_frz = 0;
+        m_cpt_ins_tlb_inval       = 0;
+        m_cpt_data_tlb_inval      = 0;
+        m_cost_ins_tlb_inval_frz  = 0;
+        m_cost_data_tlb_inval_frz = 0;
 
         m_cpt_cc_broadcast   = 0;
 
-   	    m_cost_updt_data_frz  = 0;
-   	    m_cost_inval_ins_frz  = 0;
-   	    m_cost_inval_data_frz = 0;
-   	    m_cost_broadcast_frz  = 0;
-
-   	    m_cpt_cc_cleanup_data = 0;
-   	    m_cpt_cc_cleanup_ins  = 0;
+        m_cost_updt_data_frz  = 0;
+        m_cost_inval_ins_frz  = 0;
+        m_cost_inval_data_frz = 0;
+        m_cost_broadcast_frz  = 0;
+
+        m_cpt_cc_cleanup_data = 0;
+        m_cpt_cc_cleanup_ins  = 0;
 
         m_cpt_cleanup_data_not_dirty  = 0;
@@ -986,7 +986,7 @@
         m_cpt_read              = 0;
         m_cpt_write             = 0;
-   	    m_cpt_cc_update_data = 0;
-   	    m_cpt_cc_inval_ins   = 0;
-   	    m_cpt_cc_inval_data  = 0;
+        m_cpt_cc_update_data = 0;
+        m_cpt_cc_inval_ins   = 0;
+        m_cpt_cc_inval_data  = 0;
 */
 
@@ -1106,5 +1106,5 @@
     {
     /////////////////
-    case ICACHE_IDLE:	// In this state, we handle processor requests, XTN requests,
+    case ICACHE_IDLE:   // In this state, we handle processor requests, XTN requests,
                         // and coherence requests with a fixed priority:
                         // 1/ Coherence requests                        => ICACHE_CC_CHECK
@@ -1183,6 +1183,6 @@
         if ( m_ireq.valid )
         {
-            bool	    cacheable;
-            paddr_t	    paddr;
+            bool        cacheable;
+            paddr_t     paddr;
             bool        tlb_hit = false;
             pte_info_t  tlb_flags;
@@ -1242,5 +1242,5 @@
             //   and there is no access rights checking
 
-            if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) 	// tlb not activated:
+            if ( not (r_mmu_mode.read() & INS_TLB_MASK) )   // tlb not activated:
             {
                 // cacheability
@@ -1248,7 +1248,7 @@
                 else     cacheable = m_cacheability_table[(uint64_t)m_ireq.addr];
             }
-            else						        // itlb activated
-            {
-                if ( tlb_hit )	// ITLB hit
+            else                          // itlb activated
+            {
+                if ( tlb_hit )  // ITLB hit
                 {
                     // cacheability
@@ -1295,5 +1295,5 @@
             {
 
-                if (cache_state == CACHE_SLOT_STATE_EMPTY)	    // cache miss
+                if (cache_state == CACHE_SLOT_STATE_EMPTY)      // cache miss
                 {
 
@@ -1305,15 +1305,15 @@
 #if DEBUG_ICACHE
 if ( m_debug_activated )
-std::cout << "  <PROC " << name() << " ICACHE_IDLE> READ MISS in icache" 
+std::cout << "  <PROC " << name() << " ICACHE_IDLE> READ MISS in icache"
           << " : PADDR = " << std::hex << paddr << std::endl;
 #endif
                    r_icache_miss_req = true;
                 }
-                else if (cache_state == CACHE_SLOT_STATE_ZOMBI )	// pending cleanup
+                else if (cache_state == CACHE_SLOT_STATE_ZOMBI )    // pending cleanup
                 {
                     // stalled until cleanup is acknowledged
                     r_icache_fsm       = ICACHE_IDLE;
                 }
-                else			                            // cache hit
+                else                                       // cache hit
                 {
 
@@ -1327,5 +1327,5 @@
 #if DEBUG_ICACHE
 if ( m_debug_activated )
-std::cout << "  <PROC " << name() << " ICACHE_IDLE> READ HIT in icache" 
+std::cout << "  <PROC " << name() << " ICACHE_IDLE> READ HIT in icache"
           << " : PADDR = " << std::hex << paddr
           << " / INST  = " << cache_inst << std::dec << std::endl;
@@ -1333,5 +1333,5 @@
                 }
             }
-            else             	// non cacheable read
+            else               // non cacheable read
             {
                 r_icache_unc_req  = true;
@@ -1342,5 +1342,5 @@
 {
     std::cout << "  <PROC " << name()
-              << " ICACHE_IDLE> READ UNCACHEABLE in icache" 
+              << " ICACHE_IDLE> READ UNCACHEABLE in icache"
               << " : PADDR = " << std::hex << paddr << std::endl;
 }
@@ -1351,5 +1351,5 @@
     }
     /////////////////////
-    case ICACHE_TLB_WAIT:	// Waiting the itlb update by the DCACHE FSM after a tlb miss
+    case ICACHE_TLB_WAIT:   // Waiting the itlb update by the DCACHE FSM after a tlb miss
                             // the itlb is udated by the DCACHE FSM, as well as the
                             // r_mmu_ietr and r_mmu_ibvar registers in case of error.
@@ -1386,5 +1386,5 @@
                 r_icache_fsm             = ICACHE_IDLE;
             }
-            else				// tlb updated : return to IDLE state
+            else                // tlb updated : return to IDLE state
             {
                 r_icache_fsm  = ICACHE_IDLE;
@@ -1394,5 +1394,5 @@
     }
     //////////////////////////
-    case ICACHE_XTN_TLB_FLUSH:   	// invalidate in one cycle all non global TLB entries
+    case ICACHE_XTN_TLB_FLUSH:      // invalidate in one cycle all non global TLB entries
     {
         r_itlb.flush();
@@ -1402,11 +1402,11 @@
     }
     ////////////////////////////
-    case ICACHE_XTN_CACHE_FLUSH:	// Invalidate sequencially all cache lines, using
+    case ICACHE_XTN_CACHE_FLUSH:    // Invalidate sequencially all cache lines, using
                                     // r_icache_flush_count as a slot counter,
-                                	// looping in this state until all slots are visited.
+                                    // looping in this state until all slots are visited.
                                     // It can require two cycles per slot:
                                     // We test here the slot state, and make the actual inval
                                     // (if line is valid) in ICACHE_XTN_CACHE_FLUSH_GO state.
-                       		        // A cleanup request is generated for each valid line
+                                    // A cleanup request is generated for each valid line
     {
         // coherence clack interrupt
@@ -1430,6 +1430,6 @@
             int       state;
             paddr_t   tag;
-            size_t	  way = r_icache_flush_count.read()/m_icache_sets;
-            size_t	  set = r_icache_flush_count.read()%m_icache_sets;
+            size_t    way = r_icache_flush_count.read()/m_icache_sets;
+            size_t    set = r_icache_flush_count.read()%m_icache_sets;
 
 #ifdef INSTRUMENTATION
@@ -1457,7 +1457,7 @@
                       (m_icache_sets*m_icache_ways - 1) )  // last slot
             {
-            	r_dcache_xtn_req = false;
+                r_dcache_xtn_req = false;
                 m_drsp.valid     = true;
-            	r_icache_fsm 	 = ICACHE_IDLE;
+                r_icache_fsm     = ICACHE_IDLE;
             }
 
@@ -1472,8 +1472,8 @@
     }
     ///////////////////////////////
-    case ICACHE_XTN_CACHE_FLUSH_GO:	    // Switch slot state to ZOMBI for an XTN flush
-    {
-        size_t	  way = r_icache_miss_way.read();
-        size_t	  set = r_icache_miss_set.read();
+    case ICACHE_XTN_CACHE_FLUSH_GO:     // Switch slot state to ZOMBI for an XTN flush
+    {
+        size_t  way = r_icache_miss_way.read();
+        size_t  set = r_icache_miss_set.read();
 
 #ifdef INSTRUMENTATION
@@ -1488,7 +1488,7 @@
                       (m_icache_sets*m_icache_ways - 1) )  // last slot
         {
-         	r_dcache_xtn_req = false;
+            r_dcache_xtn_req = false;
             m_drsp.valid     = true;
-         	r_icache_fsm 	 = ICACHE_IDLE;
+            r_icache_fsm     = ICACHE_IDLE;
         }
         else
@@ -1500,6 +1500,6 @@
 
     //////////////////////////
-    case ICACHE_XTN_TLB_INVAL: 		// invalidate one TLB entry selected by the virtual address
-        				            // stored in the r_dcache_save_wdata register
+    case ICACHE_XTN_TLB_INVAL:      // invalidate one TLB entry selected by the virtual address
+                                    // stored in the r_dcache_save_wdata register
     {
         r_itlb.inval(r_dcache_save_wdata.read());
@@ -1509,14 +1509,14 @@
     }
     ///////////////////////////////
-    case ICACHE_XTN_CACHE_INVAL_VA:	// Selective cache line invalidate with virtual address
+    case ICACHE_XTN_CACHE_INVAL_VA: // Selective cache line invalidate with virtual address
                                     // requires 3 cycles (in case of hit on itlb and icache).
-					                // In this state, access TLB to translate virtual address
-        				            // stored in the r_dcache_save_wdata register.
-    {
-        paddr_t 	paddr;
-        bool    	hit;
+                                    // In this state, access TLB to translate virtual address
+                                    // stored in the r_dcache_save_wdata register.
+    {
+        paddr_t paddr;
+        bool    hit;
 
         // read physical address in TLB when MMU activated
-        if ( r_mmu_mode.read() & INS_TLB_MASK ) 	// itlb activated
+        if ( r_mmu_mode.read() & INS_TLB_MASK )     // itlb activated
         {
 
@@ -1527,16 +1527,16 @@
                                    &paddr);
         }
-        else 						// itlb not activated
-        {
-            paddr 	= (paddr_t)r_dcache_save_wdata.read();
-            hit 	= true;
-        }
-
-        if ( hit )		// continue the selective inval process
+        else                        // itlb not activated
+        {
+            paddr   = (paddr_t)r_dcache_save_wdata.read();
+            hit     = true;
+        }
+
+        if ( hit )      // continue the selective inval process
         {
             r_icache_vci_paddr    = paddr;
             r_icache_fsm          = ICACHE_XTN_CACHE_INVAL_PA;
         }
-        else			// miss : send a request to DCACHE FSM
+        else            // miss : send a request to DCACHE FSM
         {
 
@@ -1545,5 +1545,5 @@
 #endif
             r_icache_tlb_miss_req = true;
-	        r_icache_vaddr_save   = r_dcache_save_wdata.read();
+            r_icache_vaddr_save   = r_dcache_save_wdata.read();
             r_icache_fsm          = ICACHE_TLB_WAIT;
         }
@@ -1551,12 +1551,12 @@
     }
     ///////////////////////////////
-    case ICACHE_XTN_CACHE_INVAL_PA:	// selective invalidate cache line with physical address
+    case ICACHE_XTN_CACHE_INVAL_PA: // selective invalidate cache line with physical address
                                     // require 2 cycles. In this state, we read directory
                                     // with address stored in r_icache_vci_paddr register.
     {
         int         state;
-        size_t		way;
-        size_t		set;
-        size_t		word;
+        size_t      way;
+        size_t      set;
+        size_t      word;
 
 #ifdef INSTRUMENTATION
@@ -1569,5 +1569,5 @@
                           &word);
 
-        if ( state == CACHE_SLOT_STATE_VALID_CC )	// inval to be done
+        if ( state == CACHE_SLOT_STATE_VALID_CC )   // inval to be done
         {
             r_icache_miss_way = way;
@@ -1575,5 +1575,5 @@
             r_icache_fsm      = ICACHE_XTN_CACHE_INVAL_GO;
         }
-        else		// miss : acknowlege the XTN request and return
+        else        // miss : acknowlege the XTN request and return
         {
             r_dcache_xtn_req = false;
@@ -1636,7 +1636,7 @@
         bool        found;
         bool        cleanup;
-        size_t  	way;
-        size_t  	set;
-        paddr_t 	victim;
+        size_t      way;
+        size_t      set;
+        paddr_t     victim;
 
 #ifdef INSTRUMENTATION
@@ -1661,5 +1661,5 @@
                     r_icache_cc_send_nline  = victim;
                     r_icache_cc_send_way    = way;
-                    r_icache_cc_send_type   = CC_TYPE_CLEANUP;    
+                    r_icache_cc_send_type   = CC_TYPE_CLEANUP;
                 }
                 else
@@ -1692,5 +1692,5 @@
     }
     ///////////////////////
-    case ICACHE_MISS_CLEAN:	         // switch the slot to zombi state
+    case ICACHE_MISS_CLEAN:          // switch the slot to zombi state
     {
         if (m_ireq.valid) m_cost_ins_miss_frz++;
@@ -1716,5 +1716,5 @@
     }
     //////////////////////
-    case ICACHE_MISS_WAIT:	  // waiting response from VCI_RSP FSM
+    case ICACHE_MISS_WAIT:    // waiting response from VCI_RSP FSM
     {
         if (m_ireq.valid) m_cost_ins_miss_frz++;
@@ -1725,7 +1725,7 @@
             r_icache_cc_send_nline      = r_icache_cleanup_victim_nline;
             r_icache_cc_send_way        = r_icache_miss_way;
-            r_icache_cc_send_type       = CC_TYPE_CLEANUP; 
+            r_icache_cc_send_type       = CC_TYPE_CLEANUP;
             r_icache_cleanup_victim_req = false;
-        }   
+        }
 
         // coherence clack interrupt
@@ -1736,5 +1736,5 @@
             break;
         }
-        
+
         // coherence interrupt
         if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read() )
@@ -1762,9 +1762,9 @@
     }
     ///////////////////////////
-    case ICACHE_MISS_DATA_UPDT:	  // update the cache (one word per cycle)
+    case ICACHE_MISS_DATA_UPDT:   // update the cache (one word per cycle)
     {
         if ( m_ireq.valid ) m_cost_ins_miss_frz++;
 
-        if ( r_vci_rsp_fifo_icache.rok() )	// response available
+        if ( r_vci_rsp_fifo_icache.rok() )  // response available
         {
 
@@ -1790,5 +1790,5 @@
             r_icache_miss_word = r_icache_miss_word.read() + 1;
 
-            if ( r_icache_miss_word.read() == m_icache_words-1 ) 	// last word
+            if ( r_icache_miss_word.read() == m_icache_words-1 )   // last word
             {
                 r_icache_fsm = ICACHE_MISS_DIR_UPDT;
@@ -1798,5 +1798,5 @@
     }
     //////////////////////////
-    case ICACHE_MISS_DIR_UPDT:	// Stalled if a victim line has been evicted,
+    case ICACHE_MISS_DIR_UPDT:  // Stalled if a victim line has been evicted,
                                 // and the cleanup ack has not been received,
                                 // as indicated by r_icache_miss_clack.
@@ -1814,7 +1814,7 @@
             r_icache_cc_send_nline      = r_icache_cleanup_victim_nline;
             r_icache_cc_send_way        = r_icache_miss_way;
-            r_icache_cc_send_type       = CC_TYPE_CLEANUP; 
+            r_icache_cc_send_type       = CC_TYPE_CLEANUP;
             r_icache_cleanup_victim_req = false;
-        }   
+        }
 
         // coherence clack interrupt
@@ -1895,5 +1895,5 @@
     }
     ////////////////////
-    case ICACHE_UNC_WAIT:	// waiting a response to an uncacheable read from VCI_RSP FSM
+    case ICACHE_UNC_WAIT:  // waiting a response to an uncacheable read from VCI_RSP FSM
     {
         // coherence clack interrupt
@@ -1936,5 +1936,5 @@
     }
     /////////////////////
-    case ICACHE_CC_CHECK:   	// This state is the entry point of a sub-fsm
+    case ICACHE_CC_CHECK:       // This state is the entry point of a sub-fsm
                                 // handling coherence requests.
                                 // if there is a matching pending miss, it is
@@ -2028,8 +2028,8 @@
         // CC request handler
 
-        int	        state = 0;
-        size_t 	    way = 0;
-        size_t 	    set = 0;
-        size_t 	    word = 0;
+        int         state = 0;
+        size_t      way = 0;
+        size_t      set = 0;
+        size_t      word = 0;
 
 #ifdef INSTRUMENTATION
@@ -2090,5 +2090,5 @@
     }
     /////////////////////
-    case ICACHE_CC_INVAL:  	// hit inval : switch slot to ZOMBI state
+    case ICACHE_CC_INVAL:   // hit inval : switch slot to ZOMBI state
     {
         assert (not r_icache_cc_send_req.read() &&
@@ -2100,5 +2100,5 @@
 #endif
 
-        // Switch slot state to ZOMBI and send CLEANUP command 
+        // Switch slot state to ZOMBI and send CLEANUP command
         r_icache.write_dir( r_icache_cc_way.read(),
                             r_icache_cc_set.read(),
@@ -2126,5 +2126,5 @@
     }
     ////////////////////
-    case ICACHE_CC_UPDT:	// hit update : write one word per cycle
+    case ICACHE_CC_UPDT:    // hit update : write one word per cycle
     {
         assert (not r_icache_cc_send_req.read() &&
@@ -2165,5 +2165,5 @@
         }
 
-        if ( r_cc_receive_updt_fifo_eop.read() )	// last word
+        if ( r_cc_receive_updt_fifo_eop.read() )   // last word
         {
             // no need to write in the cache anymore
@@ -2306,14 +2306,14 @@
     {
         paddr_t     paddr;                          // physical address
-        pte_info_t 	tlb_flags;
-        size_t     	tlb_way;
-        size_t     	tlb_set;
-        paddr_t    	tlb_nline = 0;
-        size_t		cache_way;
-        size_t		cache_set;
-        size_t		cache_word;
-        uint32_t	cache_rdata = 0;
-        bool	    tlb_hit = false;
-        int	        cache_state = CACHE_SLOT_STATE_EMPTY;
+        pte_info_t  tlb_flags;
+        size_t      tlb_way;
+        size_t      tlb_set;
+        paddr_t     tlb_nline = 0;
+        size_t      cache_way;
+        size_t      cache_set;
+        size_t      cache_word;
+        uint32_t    cache_rdata = 0;
+        bool        tlb_hit = false;
+        int         cache_state = CACHE_SLOT_STATE_EMPTY;
 
         bool        tlb_inval_required = false;     // request TLB inval after cache update
@@ -2341,5 +2341,5 @@
             {
                 // we take into account the paddr extension
-                if (vci_param::N > 32) 
+                if (vci_param::N > 32)
                     paddr = paddr | ((paddr_t)(r_dcache_paddr_ext.read()) << 32);
             }
@@ -2404,6 +2404,6 @@
             {
                 tlb_inval_required       = true;
-	            r_dcache_tlb_inval_set   = 0;
-	            r_dcache_tlb_inval_line  = r_dcache_save_paddr.read()>>
+                r_dcache_tlb_inval_set   = 0;
+                r_dcache_tlb_inval_line  = r_dcache_save_paddr.read()>>
                                            (uint32_log2(m_dcache_words<<2));
 
@@ -2620,10 +2620,10 @@
                     switch( xtn_opcode )
                     {
-                    case iss_t::XTN_PTPR:   			// itlb & dtlb must be flushed
+                    case iss_t::XTN_PTPR:               // itlb & dtlb must be flushed
                         r_dcache_xtn_req = true;
                         r_dcache_fsm     = DCACHE_XTN_SWITCH;
                         break;
 
-                    case iss_t::XTN_TLB_MODE:			// no cache or tlb access
+                    case iss_t::XTN_TLB_MODE:           // no cache or tlb access
                         r_mmu_mode       = m_dreq.wdata;
                         m_drsp.valid     = true;
@@ -2631,18 +2631,18 @@
                         break;
 
-                    case iss_t::XTN_DTLB_INVAL:     		// dtlb access
+                    case iss_t::XTN_DTLB_INVAL:             // dtlb access
                         r_dcache_fsm     = DCACHE_XTN_DT_INVAL;
                         break;
 
-                    case iss_t::XTN_ITLB_INVAL:     		// itlb access
+                    case iss_t::XTN_ITLB_INVAL:             // itlb access
                         r_dcache_xtn_req = true;
                         r_dcache_fsm     = DCACHE_XTN_IT_INVAL;
                         break;
 
-                    case iss_t::XTN_DCACHE_INVAL:   		// dcache, dtlb & itlb access
+                    case iss_t::XTN_DCACHE_INVAL:           // dcache, dtlb & itlb access
                         r_dcache_fsm     = DCACHE_XTN_DC_INVAL_VA;
                         break;
 
-                    case iss_t::XTN_MMU_DCACHE_PA_INV:  	// dcache, dtlb & itlb access
+                    case iss_t::XTN_MMU_DCACHE_PA_INV:      // dcache, dtlb & itlb access
                         r_dcache_fsm     = DCACHE_XTN_DC_INVAL_PA;
                         if (sizeof(paddr_t) <= 32)
@@ -2659,29 +2659,29 @@
                         break;
 
-                    case iss_t::XTN_DCACHE_FLUSH:   	       // itlb and dtlb must be reset
+                    case iss_t::XTN_DCACHE_FLUSH:           // itlb and dtlb must be reset
                         r_dcache_flush_count = 0;
                         r_dcache_fsm     = DCACHE_XTN_DC_FLUSH;
                         break;
 
-                    case iss_t::XTN_ICACHE_INVAL:   		// icache and itlb access
+                    case iss_t::XTN_ICACHE_INVAL:           // icache and itlb access
                         r_dcache_xtn_req = true;
                         r_dcache_fsm     = DCACHE_XTN_IC_INVAL_VA;
                         break;
 
-                    case iss_t::XTN_MMU_ICACHE_PA_INV:		// icache access
+                    case iss_t::XTN_MMU_ICACHE_PA_INV:      // icache access
                         r_dcache_xtn_req = true;
                         r_dcache_fsm     = DCACHE_XTN_IC_INVAL_PA;
                         break;
 
-                    case iss_t::XTN_ICACHE_FLUSH:   		// icache access
+                    case iss_t::XTN_ICACHE_FLUSH:           // icache access
                         r_dcache_xtn_req = true;
                         r_dcache_fsm     = DCACHE_XTN_IC_FLUSH;
                         break;
 
-                    case iss_t::XTN_SYNC:           		// wait until write buffer empty
+                    case iss_t::XTN_SYNC:                   // wait until write buffer empty
                         r_dcache_fsm     = DCACHE_XTN_SYNC;
                         break;
 
-                    case iss_t::XTN_MMU_WORD_LO: 		// no cache or tlb access
+                    case iss_t::XTN_MMU_WORD_LO:        // no cache or tlb access
                         r_mmu_word_lo    = m_dreq.wdata;
                         m_drsp.valid     = true;
@@ -2689,5 +2689,5 @@
                         break;
 
-                    case iss_t::XTN_MMU_WORD_HI: 		// no cache or tlb access
+                    case iss_t::XTN_MMU_WORD_HI:        // no cache or tlb access
                         r_mmu_word_hi    = m_dreq.wdata;
                         m_drsp.valid     = true;
@@ -2712,9 +2712,9 @@
                     break;
 
-	                case iss_t::XTN_ICACHE_PREFETCH:		// not implemented : no action
-	                case iss_t::XTN_DCACHE_PREFETCH:		// not implemented : no action
+                    case iss_t::XTN_ICACHE_PREFETCH:        // not implemented : no action
+                    case iss_t::XTN_DCACHE_PREFETCH:        // not implemented : no action
                         m_drsp.valid     = true;
                         r_dcache_fsm     = DCACHE_IDLE;
-		            break;
+                    break;
 
                     default:
@@ -2739,8 +2739,8 @@
             else
             {
-                bool	    valid_req;
-                bool	    cacheable;
-
-                if ( not (r_mmu_mode.read() & DATA_TLB_MASK) )		// dtlb not activated
+                bool        valid_req;
+                bool        cacheable;
+
+                if ( not (r_mmu_mode.read() & DATA_TLB_MASK) )     // dtlb not activated
                 {
                     valid_req     = true;
@@ -2749,7 +2749,7 @@
                     else cacheable = m_cacheability_table[(uint64_t)m_dreq.addr];
                 }
-                else 							                   // dtlb activated
+                else                                               // dtlb activated
                 {
-                    if ( tlb_hit )					// tlb hit
+                    if ( tlb_hit )                  // tlb hit
                     {
                         // cacheability
@@ -2800,5 +2800,5 @@
                         }
                     }
-                    else						// tlb miss
+                    else                     // tlb miss
                     {
                         valid_req            = false;
@@ -2809,5 +2809,5 @@
                 }    // end DTLB activated
 
-                if ( valid_req ) 	// processor request is valid (after MMU check)
+                if ( valid_req )    // processor request is valid (after MMU check)
                 {
                     // READ request
@@ -2818,5 +2818,5 @@
                           and not r_dcache_updt_req.read() )
                     {
-                        if ( cacheable )           	// cacheable read
+                        if ( cacheable )            // cacheable read
                         {
                             if ( cache_state == CACHE_SLOT_STATE_EMPTY )   // cache miss
@@ -2833,5 +2833,5 @@
 if ( m_debug_activated )
 std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
-          << " READ MISS in dcache" 
+          << " READ MISS in dcache"
           << " / PADDR = " << std::hex << paddr << std::endl;
 #endif
@@ -2860,11 +2860,11 @@
 if ( m_debug_activated )
 std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
-          << " READ HIT in dcache" 
-          << " : PADDR = " << std::hex << paddr 
+          << " READ HIT in dcache"
+          << " : PADDR = " << std::hex << paddr
           << " / DATA  = " << std::hex << cache_rdata << std::dec << std::endl;
 #endif
                             }
                         }
-                        else					// uncacheable read
+                        else                    // uncacheable read
                         {
                             r_dcache_vci_paddr      = paddr;
@@ -2876,5 +2876,5 @@
 if ( m_debug_activated )
 std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
-          << " READ UNCACHEABLE in dcache" 
+          << " READ UNCACHEABLE in dcache"
           << " / PADDR = " << std::hex << paddr << std::endl;
 #endif
@@ -2911,14 +2911,14 @@
                     {
                         if ( (r_mmu_mode.read() & DATA_TLB_MASK )
-                              and not tlb_flags.d )		// Dirty bit must be set
+                              and not tlb_flags.d )     // Dirty bit must be set
                         {
                             // The PTE physical address is obtained from the nline value (dtlb),
                             // and from the virtual address (word index)
-                            if ( tlb_flags.b )	// PTE1
+                            if ( tlb_flags.b )  // PTE1
                             {
                                 r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) |
                                                        (paddr_t)((m_dreq.addr>>19) & 0x3c);
                             }
-                            else		// PTE2
+                            else        // PTE2
                             {
                                 r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) |
@@ -2927,5 +2927,5 @@
                             r_dcache_fsm      = DCACHE_DIRTY_GET_PTE;
                         }
-                        else					// Write request accepted
+                        else                    // Write request accepted
                         {
 #ifdef INSTRUMENTATION
@@ -2936,6 +2936,6 @@
                                 r_dcache_llsc_valid = false;
 
-                            if (not cacheable) 
-                            {                            
+                            if (not cacheable)
+                            {
                                 r_dcache_vci_paddr      = paddr;
                                 r_dcache_vci_wdata      = m_dreq.wdata;
@@ -2951,5 +2951,5 @@
                                 updt_request = true;
                                 m_drsp.valid = true;
-                                if ( cache_state == CACHE_SLOT_STATE_VALID_NCC ) 
+                                if ( cache_state == CACHE_SLOT_STATE_VALID_NCC )
                                 {
                                     if ( r_dcache_content_state[cache_way*m_dcache_sets+cache_set] == LINE_CACHE_DATA_NOT_DIRTY )
@@ -2996,5 +2996,5 @@
 if ( m_debug_activated )
 std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
-          << " WRITE REQ " 
+          << " WRITE REQ "
           << " / wbuf_request = " << wbuf_request
           << " / updt_request = " << updt_request
@@ -3018,14 +3018,14 @@
                     {
                         if ( (r_mmu_mode.read() & DATA_TLB_MASK )
-                              and not tlb_flags.d )			// Dirty bit must be set
+                              and not tlb_flags.d )         // Dirty bit must be set
                         {
                             // The PTE physical address is obtained from the nline value (dtlb),
                             // and the word index (virtual address)
-                            if ( tlb_flags.b )	// PTE1
+                            if ( tlb_flags.b )  // PTE1
                             {
                                 r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) |
                                                        (paddr_t)((m_dreq.addr>>19) & 0x3c);
                             }
-                            else			// PTE2
+                            else            // PTE2
                             {
                                 r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) |
@@ -3037,5 +3037,5 @@
                             m_drsp.rdata = 0;
                         }
-                        else					// SC request accepted
+                        else                    // SC request accepted
                         {
 #ifdef INSTRUMENTATION
@@ -3054,7 +3054,7 @@
                             else                                          // local fail
                             {
-	                            m_drsp.valid = true;
-	                            m_drsp.error = false;
-	                            m_drsp.rdata = 0x1;
+                                m_drsp.valid = true;
+                                m_drsp.error = false;
+                                m_drsp.rdata = 0x1;
                             }
                         }
@@ -3065,5 +3065,5 @@
 
         // itlb miss request
-    	else if ( r_icache_tlb_miss_req.read() and not wbuf_write_miss )
+        else if ( r_icache_tlb_miss_req.read() and not wbuf_write_miss )
         {
             r_dcache_tlb_ins    = true;
@@ -3091,14 +3091,14 @@
                           // r_mmu_ins_* or r_mmu_data* error reporting registers.
     {
-        uint32_t	ptba = 0;
-        bool		bypass;
-        paddr_t		pte_paddr;
+        uint32_t    ptba = 0;
+        bool        bypass;
+        paddr_t     pte_paddr;
 
         // evaluate bypass in order to skip first level page table access
-        if ( r_dcache_tlb_ins.read() )				// itlb miss
+        if ( r_dcache_tlb_ins.read() )  // itlb miss
         {
             bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
         }
-        else							// dtlb miss
+        else                            // dtlb miss
         {
             bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
@@ -3137,5 +3137,5 @@
     }
     /////////////////////////
-    case DCACHE_TLB_PTE1_GET:	// try to read a PT1 entry in dcache
+    case DCACHE_TLB_PTE1_GET:   // try to read a PT1 entry in dcache
     {
         // coherence clack request (from DSPIN CLACK)
@@ -3155,8 +3155,8 @@
         }
 
-        uint32_t 	entry;
-        size_t		way;
-        size_t		set;
-        size_t		word;
+        uint32_t    entry;
+        size_t      way;
+        size_t      set;
+        size_t      word;
         int         cache_state;
         r_dcache.read( r_dcache_tlb_paddr.read(),
@@ -3174,5 +3174,5 @@
         if (( cache_state == CACHE_SLOT_STATE_VALID_NCC ) or ( cache_state == CACHE_SLOT_STATE_VALID_CC ))
         {
-            if ( not (entry & PTE_V_MASK) )	// unmapped
+            if ( not (entry & PTE_V_MASK) ) // unmapped
             {
                 if ( r_dcache_tlb_ins.read() )
@@ -3195,5 +3195,5 @@
 if ( m_debug_activated )
 {
-    std::cout << "  <PROC " << name() 
+    std::cout << "  <PROC " << name()
               << " DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
               << std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
@@ -3206,5 +3206,5 @@
 
             }
-            else if( entry & PTE_T_MASK ) 	//  PTD : me must access PT2
+            else if( entry & PTE_T_MASK )   //  PTD : me must access PT2
             {
                 // mark the cache line ac containing a PTD
@@ -3212,5 +3212,5 @@
 
                 // register bypass
-                if ( r_dcache_tlb_ins.read() )		// itlb
+                if ( r_dcache_tlb_ins.read() )      // itlb
                 {
                     r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
@@ -3218,5 +3218,5 @@
                                       r_dcache_tlb_paddr.read() / (m_icache_words<<2) );
                 }
-                else					// dtlb
+                else                    // dtlb
                 {
                     r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
@@ -3232,5 +3232,5 @@
 if ( m_debug_activated )
 {
-    std::cout << "  <PROC " << name() 
+    std::cout << "  <PROC " << name()
               << " DCACHE_TLB_PTE1_GET> HIT in dcache"
               << std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
@@ -3242,5 +3242,5 @@
 #endif
             }
-            else			//  PTE1 :  we must update the TLB
+            else            //  PTE1 :  we must update the TLB
             {
                 r_dcache_content_state[m_icache_sets*way+set] = LINE_CACHE_IN_TLB;
@@ -3256,5 +3256,5 @@
 if ( m_debug_activated )
 {
-    std::cout << "  <PROC " << name() 
+    std::cout << "  <PROC " << name()
               << " DCACHE_TLB_PTE1_GET> HIT in dcache"
               << std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
@@ -3272,5 +3272,5 @@
             r_dcache_fsm   = DCACHE_TLB_PTE1_GET;
         }
-        else		// we must load the missing cache line in dcache
+        else        // we must load the missing cache line in dcache
         {
             r_dcache_vci_miss_req  = true;
@@ -3283,5 +3283,5 @@
 if ( m_debug_activated )
 {
-    std::cout << "  <PROC " << name() 
+    std::cout << "  <PROC " << name()
               << " DCACHE_TLB_PTE1_GET> MISS in dcache:"
               << " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
@@ -3292,8 +3292,8 @@
     }
     ////////////////////////////
-    case DCACHE_TLB_PTE1_SELECT:	// select a slot for PTE1
-    {
-        size_t 	way;
-        size_t 	set;
+    case DCACHE_TLB_PTE1_SELECT:   // select a slot for PTE1
+    {
+        size_t way;
+        size_t set;
 
         if ( r_dcache_tlb_ins.read() )
@@ -3325,8 +3325,8 @@
 {
     if ( r_dcache_tlb_ins.read() )
-        std::cout << "  <PROC " << name() 
+        std::cout << "  <PROC " << name()
                   << " DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
     else
-        std::cout << "  <PROC " << name() 
+        std::cout << "  <PROC " << name()
                   << ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
         std::cout << " way = " << std::dec << way
@@ -3337,5 +3337,5 @@
     }
     //////////////////////////
-    case DCACHE_TLB_PTE1_UPDT:	// write a new PTE1 in tlb after testing the L/R bit
+    case DCACHE_TLB_PTE1_UPDT:  // write a new PTE1 in tlb after testing the L/R bit
                                 // - if L/R bit already set, exit the sub-fsm.
                                 // - if not, we update the page table but we dont write
@@ -3343,8 +3343,8 @@
                                 //   the coherence mechanism.
     {
-        paddr_t	  nline    = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
+        paddr_t   nline    = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
         uint32_t  pte      = r_dcache_tlb_pte_flags.read();
-        bool	  pt_updt  = false;
-        bool	  local    = true;
+        bool      pt_updt  = false;
+        bool      local    = true;
 
         // We should compute the access locality:
@@ -3355,5 +3355,5 @@
         // As long as this computation is not done, all access are local.
 
-        if ( local )						// local access
+        if ( local )                        // local access
         {
             if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
@@ -3366,5 +3366,5 @@
             }
         }
-        else 							// remote access
+        else                                // remote access
         {
             if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
@@ -3378,11 +3378,11 @@
         }
 
-        if ( not pt_updt )					// update TLB and return
+        if ( not pt_updt )                  // update TLB and return
         {
             if ( r_dcache_tlb_ins.read() )
             {
-                r_itlb.write( true,		// 2M page
+                r_itlb.write( true,     // 2M page
                               pte,
-                              0,		// argument unused for a PTE1
+                              0,        // argument unused for a PTE1
                               r_dcache_tlb_vaddr.read(),
                               r_dcache_tlb_way.read(),
@@ -3396,5 +3396,5 @@
 if ( m_debug_activated )
 {
-    std::cout << "  <PROC " << name() 
+    std::cout << "  <PROC " << name()
               << " DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB"
               << " / set = " << std::dec << r_dcache_tlb_set.read()
@@ -3406,7 +3406,7 @@
             else
             {
-                r_dtlb.write( true,		// 2M page
+                r_dtlb.write( true,     // 2M page
                               pte,
-                              0,		// argument unused for a PTE1
+                              0,        // argument unused for a PTE1
                               r_dcache_tlb_vaddr.read(),
                               r_dcache_tlb_way.read(),
@@ -3420,5 +3420,5 @@
 if ( m_debug_activated )
 {
-    std::cout << "  <PROC " << name() 
+    std::cout << "  <PROC " << name()
               << " DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB"
               << " / set = " << std::dec << r_dcache_tlb_set.read()
@@ -3437,5 +3437,5 @@
 if ( m_debug_activated )
 {
-    std::cout << "  <PROC " << name() 
+    std::cout << "  <PROC " << name()
               << " DCACHE_TLB_PTE1_UPDT> L/R bit update required"
               << std::endl;
@@ -3446,5 +3446,5 @@
     }
     /////////////////////////
-    case DCACHE_TLB_PTE2_GET:	// Try to get a PTE2 (64 bits) in the dcache
+    case DCACHE_TLB_PTE2_GET:   // Try to get a PTE2 (64 bits) in the dcache
     {
         // coherence clack request (from DSPIN CLACK)
@@ -3464,9 +3464,9 @@
         }
 
-        uint32_t 	pte_flags     = 0;
-        uint32_t 	pte_ppn       = 0;
-        size_t   	way           = 0;
-        size_t   	set           = 0;
-        size_t		word          = 0;
+        uint32_t    pte_flags     = 0;
+        uint32_t    pte_ppn       = 0;
+        size_t      way           = 0;
+        size_t      set           = 0;
+        size_t      word          = 0;
         int         cache_state   = 0;
 
@@ -3484,5 +3484,5 @@
         if ((cache_state == CACHE_SLOT_STATE_VALID_CC) or (cache_state == CACHE_SLOT_STATE_VALID_NCC))
         {
-            if ( not (pte_flags & PTE_V_MASK) )	// unmapped
+            if ( not (pte_flags & PTE_V_MASK) ) // unmapped
             {
                 if ( r_dcache_tlb_ins.read() )
@@ -3512,5 +3512,5 @@
 #endif
             }
-            else				// mapped : we must update the TLB
+            else                // mapped : we must update the TLB
             {
                 r_dcache_content_state[m_dcache_sets*way+set] = LINE_CACHE_IN_TLB;
@@ -3527,5 +3527,5 @@
 if ( m_debug_activated )
 {
-    std::cout << "  <PROC " << name() 
+    std::cout << "  <PROC " << name()
               << " DCACHE_TLB_PTE2_GET> HIT in dcache:"
               << " PTE_FLAGS = " << std::hex << pte_flags
@@ -3543,5 +3543,5 @@
 if ( m_debug_activated )
 {
-    std::cout << "  <PROC " << name() 
+    std::cout << "  <PROC " << name()
               << " DCACHE_TLB_PTE2_GET> ZOMBI in dcache: waiting cleanup ack"
               << std::endl;
@@ -3577,5 +3577,5 @@
         {
             r_itlb.select( r_dcache_tlb_vaddr.read(),
-                           false,	// PTE2
+                           false,   // PTE2
                            &way,
                            &set );
@@ -3587,5 +3587,5 @@
         {
             r_dtlb.select( r_dcache_tlb_vaddr.read(),
-                           false,	// PTE2
+                           false,   // PTE2
                            &way,
                            &set );
@@ -3614,5 +3614,5 @@
     }
     //////////////////////////
-    case DCACHE_TLB_PTE2_UPDT:	// write a new PTE2 in tlb after testing the L/R bit
+    case DCACHE_TLB_PTE2_UPDT:  // write a new PTE2 in tlb after testing the L/R bit
                                 // - if L/R bit already set, exit the sub-fsm.
                                 // - if not, we update the page table but we dont write
@@ -3620,5 +3620,5 @@
                                 //   the coherence mechanism.
     {
-        paddr_t	        nline     = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
+        paddr_t         nline     = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
         uint32_t        pte_flags = r_dcache_tlb_pte_flags.read();
         uint32_t        pte_ppn   = r_dcache_tlb_pte_ppn.read();
@@ -3633,5 +3633,5 @@
         // As long as this computation is not done, all access are local.
 
-        if ( local )						// local access
+        if ( local )                        // local access
         {
             if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
@@ -3641,5 +3641,5 @@
                 r_dcache_vci_cas_new   = pte_flags | PTE_L_MASK;
                 pte_flags              = pte_flags | PTE_L_MASK;
-		        r_dcache_tlb_pte_flags = pte_flags;
+                r_dcache_tlb_pte_flags = pte_flags;
             }
         }
@@ -3652,5 +3652,5 @@
                 r_dcache_vci_cas_new   = pte_flags | PTE_R_MASK;
                 pte_flags              = pte_flags | PTE_R_MASK;
-		        r_dcache_tlb_pte_flags = pte_flags;
+                r_dcache_tlb_pte_flags = pte_flags;
             }
         }
@@ -3660,5 +3660,5 @@
             if ( r_dcache_tlb_ins.read() )
             {
-                r_itlb.write( false,	// 4K page
+                r_itlb.write( false,    // 4K page
                               pte_flags,
                               pte_ppn,
@@ -3684,5 +3684,5 @@
             else
             {
-                r_dtlb.write( false,	// 4K page
+                r_dtlb.write( false,    // 4K page
                               pte_flags,
                               pte_ppn,
@@ -3711,5 +3711,5 @@
         else                                   // update page table but not TLB
         {
-            r_dcache_fsm = DCACHE_TLB_LR_UPDT; 	// dcache and page table update
+            r_dcache_fsm = DCACHE_TLB_LR_UPDT; // dcache and page table update
 
 #if DEBUG_DCACHE
@@ -3772,5 +3772,5 @@
             }
 
-            r_dcache_fsm = DCACHE_TLB_RETURN; 
+            r_dcache_fsm = DCACHE_TLB_RETURN;
         }
         else
@@ -3790,5 +3790,5 @@
     }
     ////////////////////////
-    case DCACHE_TLB_LR_WAIT:		// Waiting the response to SC transaction for DIRTY bit.
+    case DCACHE_TLB_LR_WAIT:        // Waiting the response to SC transaction for DIRTY bit.
                                     // We consume the response in rsp FIFO,
                                     // and exit the sub-fsm, but we don't
@@ -3815,5 +3815,5 @@
         }
 
-        if ( r_vci_rsp_data_error.read() ) 	// bus error
+        if ( r_vci_rsp_data_error.read() )  // bus error
         {
             std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
@@ -3821,6 +3821,6 @@
             exit(0);
         }
-	else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
-	{
+       else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
+       {
 #if DEBUG_DCACHE
 if ( m_debug_activated )
@@ -3836,5 +3836,5 @@
     }
     ///////////////////////
-    case DCACHE_TLB_RETURN:		// return to caller depending on tlb miss type
+    case DCACHE_TLB_RETURN:    // return to caller depending on tlb miss type
     {
 #if DEBUG_DCACHE
@@ -3850,5 +3850,5 @@
     }
     ///////////////////////
-    case DCACHE_XTN_SWITCH:		// The r_ptpr registers must be written,
+    case DCACHE_XTN_SWITCH:     // The r_ptpr registers must be written,
                                 // and both itlb and dtlb must be flushed.
                                 // Caution : the itlb miss requests must be taken
@@ -3890,5 +3890,5 @@
     }
     /////////////////////
-    case DCACHE_XTN_SYNC:		// waiting until write buffer empty
+    case DCACHE_XTN_SYNC:       // waiting until write buffer empty
                                 // The coherence request must be taken
                                 // as there is a risk of dead-lock
@@ -3959,5 +3959,5 @@
     }
     /////////////////////////
-    case DCACHE_XTN_DC_FLUSH:	// Invalidate sequencially all cache lines, using
+    case DCACHE_XTN_DC_FLUSH:   // Invalidate sequencially all cache lines, using
                                 // r_dcache_flush_count as a slot counter,
                                 // looping in this state until all slots have been visited.
@@ -4125,5 +4125,5 @@
     }
     /////////////////////////
-    case DCACHE_XTN_DT_INVAL: 	// handling processor XTN_DTLB_INVAL request
+    case DCACHE_XTN_DT_INVAL:   // handling processor XTN_DTLB_INVAL request
     {
         r_dtlb.inval(r_dcache_save_wdata.read());
@@ -4135,10 +4135,10 @@
     case DCACHE_XTN_DC_INVAL_VA:  // selective cache line invalidate with virtual address
                                   // requires 3 cycles: access tlb, read cache, inval cache
-                               	  // we compute the physical address in this state
+                                  // we compute the physical address in this state
     {
         paddr_t paddr;
         bool    hit;
 
-        if ( r_mmu_mode.read() & DATA_TLB_MASK ) 	// dtlb activated
+        if ( r_mmu_mode.read() & DATA_TLB_MASK )    // dtlb activated
         {
 
@@ -4149,24 +4149,24 @@
                                     &paddr );
         }
-        else 						// dtlb not activated
+        else                        // dtlb not activated
         {
             paddr = (paddr_t)r_dcache_save_wdata.read();
-            if (vci_param::N > 32) 
+            if (vci_param::N > 32)
                 paddr = paddr | ((paddr_t)(r_dcache_paddr_ext.read()) << 32);
             hit   = true;
         }
 
-        if ( hit )		// tlb hit
+        if ( hit )      // tlb hit
         {
             r_dcache_save_paddr = paddr;
             r_dcache_fsm      = DCACHE_XTN_DC_INVAL_PA;
         }
-        else			// tlb miss
-       	{
+        else            // tlb miss
+        {
 
 #ifdef INSTRUMENTATION
 m_cpt_data_tlb_miss++;
 #endif
-            r_dcache_tlb_ins    = false;		// dtlb
+            r_dcache_tlb_ins    = false;        // dtlb
             r_dcache_tlb_vaddr  = r_dcache_save_wdata.read();
             r_dcache_fsm        = DCACHE_TLB_MISS;
@@ -4190,7 +4190,7 @@
                                   // In this state we read dcache.
     {
-        size_t		way;
-        size_t		set;
-        size_t		word;
+        size_t      way;
+        size_t      set;
+        size_t      word;
         int         state;
 
@@ -4204,5 +4204,5 @@
                            &word );
 
-        if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC))	// inval to be done
+        if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC))  // inval to be done
         {
             r_dcache_xtn_way       = way;
@@ -4210,5 +4210,5 @@
             r_dcache_xtn_state     = state;
             r_dcache_xtn_data_addr = r_dcache_save_paddr.read()&~0x3F;
-            
+
             if( (state == CACHE_SLOT_STATE_VALID_NCC) and (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_NOT_DIRTY) )
             {
@@ -4216,7 +4216,7 @@
             }
             r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
-            
-        }
-        else		// miss : nothing to do
+
+        }
+        else        // miss : nothing to do
         {
             r_dcache_fsm      = DCACHE_IDLE;
@@ -4240,5 +4240,5 @@
     ////////////////////////////
     case DCACHE_XTN_DC_INVAL_GO:  // In this state, we invalidate the cache line
-        			              // Blocked if previous cleanup not completed
+                                  // Blocked if previous cleanup not completed
                                   // Test if itlb or dtlb inval is required
     {
@@ -4246,6 +4246,6 @@
         {
             int     state      = r_dcache_xtn_state.read();
-            size_t	way        = r_dcache_xtn_way.read();
-            size_t	set        = r_dcache_xtn_set.read();
+            size_t  way        = r_dcache_xtn_way.read();
+            size_t  set        = r_dcache_xtn_set.read();
             paddr_t nline      = r_dcache_save_paddr.read() / (m_dcache_words<<2);
 
@@ -4323,5 +4323,5 @@
 }
 #endif
-	    }
+        }
         break;
     }
@@ -4363,5 +4363,5 @@
 
     //////////////////////////////
-    case DCACHE_XTN_DC_INVAL_END:  	// send response to processor XTN request
+    case DCACHE_XTN_DC_INVAL_END:   // send response to processor XTN request
     {
         r_dcache_fsm = DCACHE_IDLE;
@@ -4531,5 +4531,5 @@
     }
     ///////////////////////
-    case DCACHE_MISS_CLEAN:		// switch the slot to ZOMBI state
+    case DCACHE_MISS_CLEAN:     // switch the slot to ZOMBI state
                                 // and possibly request itlb or dtlb invalidate
     {
@@ -4585,5 +4585,5 @@
     }
     //////////////////////
-    case DCACHE_MISS_WAIT:	// waiting the response to a miss request from VCI_RSP FSM
+    case DCACHE_MISS_WAIT:  // waiting the response to a miss request from VCI_RSP FSM
                             // This state is in charge of error signaling
                             // There is 5 types of error depending on the requester
@@ -4618,5 +4618,5 @@
         }
 
-        if ( r_vci_rsp_data_error.read() ) 			// bus error
+        if ( r_vci_rsp_data_error.read() )  // bus error
         {
             switch ( r_dcache_miss_type.read() )
@@ -4672,17 +4672,17 @@
             r_vci_rsp_data_error = false;
         }
-        else if ( r_vci_rsp_fifo_dcache.rok() )		// valid response available
+        else if ( r_vci_rsp_fifo_dcache.rok() )    // valid response available
         {
             r_dcache_miss_word = 0;
-	        r_dcache_fsm       = DCACHE_MISS_DATA_UPDT;
+            r_dcache_fsm       = DCACHE_MISS_DATA_UPDT;
         }
         break;
     }
     //////////////////////////
-    case DCACHE_MISS_DATA_UPDT:	  // update the dcache (one word per cycle)
+    case DCACHE_MISS_DATA_UPDT:   // update the dcache (one word per cycle)
     {
         if ( m_dreq.valid) m_cost_data_miss_frz++;
 
-        if ( r_vci_rsp_fifo_dcache.rok() && r_vci_rsp_fifo_rpktid.rok())	// one word available
+        if ( r_vci_rsp_fifo_dcache.rok() && r_vci_rsp_fifo_rpktid.rok())   // one word available
         {
 #ifdef INSTRUMENTATION
@@ -4860,5 +4860,5 @@
         }
 
-        if ( r_vci_rsp_data_error.read() ) 	// bus error
+        if ( r_vci_rsp_data_error.read() )  // bus error
         {
             if(r_dcache_vci_unc_write.read())
@@ -4873,6 +4873,6 @@
             break;
         }
-	    else if ( r_vci_rsp_fifo_dcache.rok() )     // data available
-	    {
+        else if ( r_vci_rsp_fifo_dcache.rok() )     // data available
+        {
             // consume data
             vci_rsp_fifo_dcache_get = true;
@@ -4882,9 +4882,9 @@
             if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
             {
-	            m_drsp.valid        = true;
+                m_drsp.valid        = true;
                 m_drsp.error        = false;
-	            m_drsp.rdata        = r_vci_rsp_fifo_dcache.read();
-            }
-	    }
+                m_drsp.rdata        = r_vci_rsp_fifo_dcache.read();
+            }
+        }
         break;
     }
@@ -4908,5 +4908,5 @@
         }
 
-        if ( r_vci_rsp_data_error.read() ) 	// bus error
+        if ( r_vci_rsp_data_error.read() )  // bus error
         {
             r_mmu_detr           = MMU_READ_DATA_ILLEGAL_ACCESS;
@@ -4918,6 +4918,6 @@
             break;
         }
-	    else if ( r_vci_rsp_fifo_dcache.rok() )     // data available
-	    {
+        else if ( r_vci_rsp_fifo_dcache.rok() )     // data available
+        {
             // consume data
             vci_rsp_fifo_dcache_get = true;
@@ -4940,9 +4940,9 @@
                 r_dcache_fsm = DCACHE_IDLE;
             }
-	    }
+        }
         break;
     }
     ////////////////////
-    case DCACHE_SC_WAIT:	// waiting VCI response to a SC transaction
+    case DCACHE_SC_WAIT:   // waiting VCI response to a SC transaction
     {
         // coherence clack request (from DSPIN CLACK)
@@ -4962,5 +4962,5 @@
         }
 
-        if ( r_vci_rsp_data_error.read() ) 		// bus error
+        if ( r_vci_rsp_data_error.read() )     // bus error
         {
             r_mmu_detr           = MMU_READ_DATA_ILLEGAL_ACCESS;
@@ -4972,6 +4972,6 @@
             break;
         }
-	    else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
-	    {
+        else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
+        {
             // consume response
             vci_rsp_fifo_dcache_get = true;
@@ -4979,9 +4979,9 @@
             m_drsp.rdata            = r_vci_rsp_fifo_dcache.read();
             r_dcache_fsm            = DCACHE_IDLE;
-	    }
+        }
         break;
     }
     //////////////////////////
-    case DCACHE_DIRTY_GET_PTE:		// This sub_fsm set the PTE Dirty bit in memory
+    case DCACHE_DIRTY_GET_PTE:      // This sub_fsm set the PTE Dirty bit in memory
                                     // before handling a processor WRITE or SC request
                                     // Input argument is r_dcache_dirty_paddr
@@ -5083,5 +5083,5 @@
         if (!r_cas_islocal.read())
         {
-            if ( r_vci_rsp_data_error.read() )	// bus error
+            if ( r_vci_rsp_data_error.read() )  // bus error
             {
                 std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl;
@@ -5089,5 +5089,5 @@
                 exit(0);
             }
-            else if ( r_vci_rsp_fifo_dcache.rok() )	// response available
+            else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
             {
                 vci_rsp_fifo_dcache_get = true;
@@ -5155,10 +5155,10 @@
 //              << " DCACHE_CC_CHECK> paddr = " << paddr
 //              << " r_dcache_vci_paddr = " << r_dcache_vci_paddr.read()
-//              << " mask = " << mask 
-//              << " (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = " 
+//              << " mask = " << mask
+//              << " (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = "
 //              << (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT)
-//              << " (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = " 
+//              << " (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = "
 //              << (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)
-//              << " ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = " 
+//              << " ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = "
 //              << ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))
 //              << std::dec <<std::endl;
@@ -5206,9 +5206,9 @@
         }
 
-        
+
         // Match between MISS address and CC address
         // note: In the same cycle we can handle a CLACK and a MISS match
         // because the CLACK access the directory but the MISS match dont.
-        if (r_cc_receive_dcache_req.read() and 
+        if (r_cc_receive_dcache_req.read() and
           ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT  )  or
            (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT    )  or
@@ -5250,5 +5250,5 @@
 
         // CC request handler
-       
+
         int    state = 0;
         size_t way   = 0;
@@ -5365,5 +5365,5 @@
                 // If the type of inval request from Memcache is configuration
                 // (software), we send a classic CLEANUP
-                if (cache_state == CACHE_SLOT_STATE_VALID_CC or r_cc_receive_dcache_inval_is_config.read()) 
+                if (cache_state == CACHE_SLOT_STATE_VALID_CC or r_cc_receive_dcache_inval_is_config.read())
                 {
                     r_dcache.write_dir( way,
@@ -5388,5 +5388,5 @@
         if (cache_state == CACHE_SLOT_STATE_VALID_NCC and not r_cc_receive_dcache_inval_is_config.read())
         {
-            r_dcache_cc_cleanup_line_ncc = true; 
+            r_dcache_cc_cleanup_line_ncc = true;
             if ((r_dcache_content_state[way*m_dcache_sets+set] != LINE_CACHE_DATA_NOT_DIRTY) or r_dcache_dirty_save.read() or dirty_save) //must send data
             {
@@ -5404,5 +5404,5 @@
                                     set,
                                     CACHE_SLOT_STATE_ZOMBI );
- 
+
                 r_dcache_cc_cleanup_updt_data = false;
                 r_dcache_fsm = r_dcache_fsm_cc_save.read();
@@ -5417,5 +5417,5 @@
         break;
     }
-    
+
     /////////////////////
     case DCACHE_CC_INVAL_DATA:
@@ -5487,5 +5487,5 @@
                         "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "
                         "must not be set");
-        
+
                 if ( not r_cc_receive_updt_fifo_be.rok() ) break;
 
@@ -5538,5 +5538,5 @@
     }
     ///////////////////////////
-    case DCACHE_INVAL_TLB_SCAN:     	// Scan sequencially all sets for both ITLB & DTLB
+    case DCACHE_INVAL_TLB_SCAN:         // Scan sequencially all sets for both ITLB & DTLB
                                         // It makes assumption: m_itlb_sets == m_dtlb_sets
                                         // All ways are handled in parallel.
@@ -5554,5 +5554,5 @@
                                         // - r_dcache_fsm_scan_save
     {
-        paddr_t	line = r_dcache_tlb_inval_line.read();
+        paddr_t line = r_dcache_tlb_inval_line.read();
         size_t  set  = r_dcache_tlb_inval_set.read();
         size_t  way;
@@ -5611,6 +5611,6 @@
     if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) )
     {
-        m_cpt_frz_cycles++; 		// used for instrumentation
-        m_cpt_stop_simulation++;	// used for debug
+        m_cpt_frz_cycles++;         // used for instrumentation
+        m_cpt_stop_simulation++;    // used for debug
         if ( m_cpt_stop_simulation > m_max_frozen_cycles )
         {
@@ -5942,5 +5942,5 @@
                             {
                                 std::cout << "ERROR in VCI_CC_VCACHE " << name()
-                                          << " VCI response packet too short" 
+                                          << " VCI response packet too short"
                                           << " for instruction miss" << std::endl;
                                 exit(0);
@@ -6131,13 +6131,13 @@
             {
                 // the new client is dcache and has a cleanup request
-                if      ( (update_last_client == 0) and 
+                if      ( (update_last_client == 0) and
                           (r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
                     r_cc_send_fsm = CC_SEND_CLEANUP_1;
                 // the new client is dcache and has a multi acknowledgement request
-                else if ( (update_last_client == 0) and 
+                else if ( (update_last_client == 0) and
                           (r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
                     r_cc_send_fsm = CC_SEND_MULTI_ACK;
                 // the new client is icache and has a cleanup request
-                else if ( (update_last_client == 1) and 
+                else if ( (update_last_client == 1) and
                           (r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
                     r_cc_send_fsm = CC_SEND_CLEANUP_1;
@@ -6252,5 +6252,5 @@
                 }
                 // test for a multi updt
-                else if (receive_type == DspinRwtParam::TYPE_MULTI_UPDT_DATA) 
+                else if (receive_type == DspinRwtParam::TYPE_MULTI_UPDT_DATA)
                 {
                     r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_HEADER;
@@ -6288,5 +6288,5 @@
             // not to actually post a request to an available cache => need a
             // flip_flop to check that ?
-            if (not (r_cc_receive_icache_req.read()) and 
+            if (not (r_cc_receive_icache_req.read()) and
                 not (r_cc_receive_dcache_req.read()) and
                 (p_dspin_m2p.write.read()))
@@ -6333,5 +6333,5 @@
             uint64_t receive_data = p_dspin_m2p.data.read();
             // for data INVAL, wait for dcache to take the request
-            if (p_dspin_m2p.write.read()           and 
+            if (p_dspin_m2p.write.read()           and
                 not r_cc_receive_dcache_req.read() )
             {
@@ -6352,5 +6352,5 @@
             uint64_t receive_data = p_dspin_m2p.data.read();
             // for ins INVAL, wait for icache to take the request
-            if (p_dspin_m2p.write.read()           and 
+            if (p_dspin_m2p.write.read()           and
                 not r_cc_receive_icache_req.read() )
             {
@@ -6472,5 +6472,5 @@
 
     ///////////////// DSPIN CLACK interface ///////////////
-    
+
     uint64_t clack_type = DspinRwtParam::dspin_get(r_dspin_clack_flit.read(),
                                                      DspinRwtParam::CLACK_TYPE);
@@ -6559,6 +6559,6 @@
     p_vci.pktid  = 0;
     p_vci.srcid  = m_srcid;
-    p_vci.cons   = is_sc_or_cas; 
-    p_vci.contig = not is_sc_or_cas; 
+    p_vci.cons   = is_sc_or_cas;
+    p_vci.contig = not is_sc_or_cas;
     p_vci.wrap   = false;
     p_vci.clen   = 0;
@@ -6567,11 +6567,11 @@
     if ( m_monitor_ok ) {
         if ( p_vci.cmdack.read() == true and p_vci.cmdval == true) {
-            if (((p_vci.address.read()) >= m_monitor_base) and 
+            if (((p_vci.address.read()) >= m_monitor_base) and
                 ((p_vci.address.read()) < m_monitor_base + m_monitor_length) ) {
                 std::cout << "CC_VCACHE Monitor " << name() << std::hex
-                          << " Access type = " << vci_cmd_type_str[p_vci.cmd.read()] 
+                          << " Access type = " << vci_cmd_type_str[p_vci.cmd.read()]
                           << " Pktid type = " << vci_pktid_type_str[p_vci.pktid.read()]
                           << " : address = " << p_vci.address.read()
-                          << " / be = " << p_vci.be.read(); 
+                          << " / be = " << p_vci.be.read();
                 if ( p_vci.cmd.read() == vci_param::CMD_WRITE ) {
                     std::cout << " / data = " << p_vci.wdata.read();
@@ -6721,7 +6721,7 @@
     } // end switch r_vci_rsp_fsm
 
-    
-    // Send coherence packets on DSPIN P2M 
-    // it depends on the CC_SEND FSM 
+
+    // Send coherence packets on DSPIN P2M
+    // it depends on the CC_SEND FSM
 
     uint64_t dspin_send_data = 0;
@@ -6747,6 +6747,6 @@
             if(r_cc_send_last_client.read() == 0) // dcache active request
             {
-                uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read() 
-                                >> (m_nline_width - m_x_width - m_y_width) 
+                uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
+                                >> (m_nline_width - m_x_width - m_y_width)
                                 << (DspinRwtParam::GLOBALID_WIDTH - m_x_width - m_y_width);
                 DspinRwtParam::dspin_set(dspin_send_data,
@@ -6772,6 +6772,6 @@
             else                                // icache active request
             {
-                uint64_t dest = (uint64_t) r_icache_cc_send_nline.read() 
-                                >> (m_nline_width - m_x_width - m_y_width) 
+                uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
+                                >> (m_nline_width - m_x_width - m_y_width)
                                 << (DspinRwtParam::GLOBALID_WIDTH - m_x_width - m_y_width);
 
@@ -6833,5 +6833,5 @@
                                        r_cc_send_data_fifo.read(),
                                        DspinRwtParam::CLEANUP_DATA_UPDT);
-            
+
             p_dspin_p2m.data = dspin_send_data;
             p_dspin_p2m.write = true;
@@ -6852,8 +6852,8 @@
             if(r_cc_send_last_client.read() == 0) // dcache active request
             {
-                uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read() 
-                                >> (m_nline_width - m_x_width - m_y_width) 
+                uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
+                                >> (m_nline_width - m_x_width - m_y_width)
                                 << (DspinRwtParam::GLOBALID_WIDTH - m_x_width - m_y_width);
- 
+
                 DspinRwtParam::dspin_set(dspin_send_data,
                                            dest,
@@ -6866,8 +6866,8 @@
             else                                    // icache active request
             {
-                uint64_t dest = (uint64_t) r_icache_cc_send_nline.read() 
-                                >> (m_nline_width - m_x_width - m_y_width) 
+                uint64_t dest = (uint64_t) r_icache_cc_send_nline.read()
+                                >> (m_nline_width - m_x_width - m_y_width)
                                 << (DspinRwtParam::GLOBALID_WIDTH - m_x_width - m_y_width);
- 
+
 
                 DspinRwtParam::dspin_set(dspin_send_data,
@@ -6889,5 +6889,5 @@
 
     // Receive coherence packets
-    // It depends on the CC_RECEIVE FSM 
+    // It depends on the CC_RECEIVE FSM
     switch( r_cc_receive_fsm.read() )
     {
@@ -6946,5 +6946,5 @@
         case CC_RECEIVE_INS_UPDT_HEADER:
         {
-            if ( not r_cc_receive_icache_req.read()) 
+            if ( not r_cc_receive_icache_req.read())
                 p_dspin_m2p.read = true;
             else
@@ -7001,5 +7001,5 @@
     }
 
-    p_dspin_clack.read = dspin_clack_get; 
+    p_dspin_clack.read = dspin_clack_get;
 } // end genMoore
 
