Changeset 827 for branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src

Timestamp:

Oct 1, 2014, 5:44:55 PM (10 years ago)

Author:

devigne

Message:

RWT Commit : vci_cc_vcache_wrapper cosmetic

File:

• branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (modified) (310 diffs)

branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

@@ -37 +37 @@
 #define DEBUG_ICACHE        1
 #define DEBUG_CMD           0
-#define INSTRUMENTATION     1
 
 namespace soclib {
@@ -43 +42 @@
 
 namespace {
-const char *icache_fsm_state_str[] = {
+const char * icache_fsm_state_str[] = {
         "ICACHE_IDLE",
 
@@ -69 +68 @@
     };
 
-const char *dcache_fsm_state_str[] = {
+const char * dcache_fsm_state_str[] = {
         "DCACHE_IDLE",
 
@@ -122 +121 @@
     };
 
-const char *cmd_fsm_state_str[] = {
+const char * cmd_fsm_state_str[] = {
         "CMD_IDLE",
         "CMD_INS_MISS",
@@ -135 +134 @@
     };
 
-const char *vci_pktid_type_str[] = {
+const char * vci_pktid_type_str[] = {
         "TYPE_DATA_UNC",
         "TYPE_READ_DATA_MISS",
@@ -146 +145 @@
     };
 
-const char *vci_cmd_type_str[] = {
+const char * vci_cmd_type_str[] = {
         "NOP or STORE_COND",
         "READ",
@@ -153 +152 @@
     };
 
-const char *rsp_fsm_state_str[] = {
+const char * rsp_fsm_state_str[] = {
         "RSP_IDLE",
         "RSP_INS_MISS",
@@ -163 +162 @@
     };
 
-const char *cc_receive_fsm_state_str[] = {
+const char * cc_receive_fsm_state_str[] = {
         "CC_RECEIVE_IDLE",
         "CC_RECEIVE_BRDCAST_HEADER",
@@ -179 +178 @@
     };
 
-const char *cc_send_fsm_state_str[] = {
+const char * cc_send_fsm_state_str[] = {
         "CC_SEND_IDLE",
         "CC_SEND_CLEANUP_1",
@@ -199 +198 @@
 /////////////////////////////////
 tmpl(/**/)::VciCcVCacheWrapper(
-    sc_module_name          name,
-    const int               proc_id,
-    const MappingTable      &mtd,
-    const IntTab            &srcid,
-    const size_t            cc_global_id,
-    const size_t            itlb_ways,
-    const size_t            itlb_sets,
-    const size_t            dtlb_ways,
-    const size_t            dtlb_sets,
-    const size_t            icache_ways,
-    const size_t            icache_sets,
-    const size_t            icache_words,
-    const size_t            dcache_ways,
-    const size_t            dcache_sets,
-    const size_t            dcache_words,
-    const size_t            wbuf_nlines,
-    const size_t            wbuf_nwords,
-    const size_t            x_width,
-    const size_t            y_width,
-    const uint32_t          max_frozen_cycles,
-    const uint32_t          debug_start_cycle,
-    const bool              debug_ok )
+    sc_module_name     name,
+    const int          proc_id,
+    const MappingTable &mtd,
+    const IntTab       &srcid,
+    const size_t       cc_global_id,
+    const size_t       itlb_ways,
+    const size_t       itlb_sets,
+    const size_t       dtlb_ways,
+    const size_t       dtlb_sets,
+    const size_t       icache_ways,
+    const size_t       icache_sets,
+    const size_t       icache_words,
+    const size_t       dcache_ways,
+    const size_t       dcache_sets,
+    const size_t       dcache_words,
+    const size_t       wbuf_nlines,
+    const size_t       wbuf_nwords,
+    const size_t       x_width,
+    const size_t       y_width,
+    const uint32_t     max_frozen_cycles,
+    const uint32_t     debug_start_cycle,
+    const bool         debug_ok)
     : soclib::caba::BaseModule(name),
 
@@ -230 +229 @@
       p_dspin_clack("p_dspin_clack"),
 
-      m_cacheability_table( mtd.getCacheabilityTable() ),
-      m_srcid( mtd.indexForId(srcid) ),
-      m_cc_global_id( cc_global_id ),
-      m_nline_width( vci_param::N - (uint32_log2(dcache_words)) - 2 ),
-      m_itlb_ways( itlb_ways ),
-      m_itlb_sets( itlb_sets ),
-      m_dtlb_ways( dtlb_ways ),
-      m_dtlb_sets( dtlb_sets ),
-      m_icache_ways( icache_ways ),
-      m_icache_sets( icache_sets ),
-      m_icache_yzmask( (~0)<<(uint32_log2(icache_words) + 2) ),
-      m_icache_words( icache_words ),
-      m_dcache_ways( dcache_ways ),
-      m_dcache_sets( dcache_sets ),
-      m_dcache_yzmask( (~0)<<(uint32_log2(dcache_words) + 2) ),
-      m_dcache_words( dcache_words ),
-      m_x_width( x_width ),
-      m_y_width( y_width ),
-      m_proc_id( proc_id ),
-      m_max_frozen_cycles( max_frozen_cycles ),
-      m_paddr_nbits( vci_param::N ),
-      m_debug_start_cycle( debug_start_cycle ),
-      m_debug_ok( debug_ok ),
+      m_cacheability_table(mtd.getCacheabilityTable()),
+      m_srcid(mtd.indexForId(srcid)),
+      m_cc_global_id(cc_global_id),
+      m_nline_width(vci_param::N - (uint32_log2(dcache_words)) - 2),
+      m_itlb_ways(itlb_ways),
+      m_itlb_sets(itlb_sets),
+      m_dtlb_ways(dtlb_ways),
+      m_dtlb_sets(dtlb_sets),
+      m_icache_ways(icache_ways),
+      m_icache_sets(icache_sets),
+      m_icache_yzmask((~0) << (uint32_log2(icache_words) + 2)),
+      m_icache_words(icache_words),
+      m_dcache_ways(dcache_ways),
+      m_dcache_sets(dcache_sets),
+      m_dcache_yzmask((~0) << (uint32_log2(dcache_words) + 2)),
+      m_dcache_words(dcache_words),
+      m_x_width(x_width),
+      m_y_width(y_width),
+      m_proc_id(proc_id),
+      m_max_frozen_cycles(max_frozen_cycles),
+      m_paddr_nbits(vci_param::N),
+      m_debug_start_cycle(debug_start_cycle),
+      m_debug_ok(debug_ok),
       m_dcache_paddr_ext_reset(0),
       m_icache_paddr_ext_reset(0),
@@ -281 +280 @@
       r_icache_cc_need_write("r_icache_cc_need_write"),
 
+      r_icache_clack_req("r_icache_clack_req"),
+      r_icache_clack_way("r_icache_clack_way"),
+      r_icache_clack_set("r_icache_clack_set"),
+
       r_icache_flush_count("r_icache_flush_count"),
 
@@ -286 +289 @@
       r_icache_unc_req("r_icache_unc_req"),
 
-      r_icache_tlb_miss_req("r_icache_tlb_read_req"),
+      r_icache_tlb_miss_req("r_icache_tlb_miss_req"),
       r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"),
 
@@ -297 +300 @@
       r_icache_cc_send_way("r_icache_cc_send_way"),
       r_icache_cc_send_updt_tab_idx("r_icache_cc_send_updt_tab_idx"),
+
+      r_icache_paddr_ext("r_icache_paddr_ext"),
 
       r_dcache_fsm("r_dcache_fsm"),
@@ -329 +334 @@
       r_dcache_vci_sc_data("r_dcache_vci_sc_data"),
 
+      r_cas_islocal("r_cas_islocal"),
+      r_cas_local_way("r_cas_local_way"),
+      r_cas_local_set("r_cas_local_set"),
+      r_cas_local_word("r_cas_local_word"),
+
       r_dcache_xtn_way("r_dcache_xtn_way"),
       r_dcache_xtn_set("r_dcache_xtn_set"),
@@ -337 +347 @@
       r_dcache_miss_set("r_dcache_miss_set"),
       r_dcache_miss_inval("r_dcache_miss_inval"),
+      r_dcache_miss_clack("r_dcache_miss_clack"),
 
       r_dcache_cc_way("r_dcache_cc_way"),
       r_dcache_cc_set("r_dcache_cc_set"),
+      r_dcache_cc_state("r_dcache_cc_state"),
       r_dcache_cc_word("r_dcache_cc_word"),
       r_dcache_cc_need_write("r_dcache_cc_need_write"),
+      r_dcache_cc_inval_addr("r_dcache_cc_inval_addr"),
+      r_dcache_cc_inval_data_cpt("r_dcache_cc_inval_data_cpt"),
+
+      r_dcache_clack_req("r_dcache_clack_req"),
+      r_dcache_clack_way("r_dcache_clack_way"),
+      r_dcache_clack_set("r_dcache_clack_set"),
 
       r_dcache_flush_count("r_dcache_flush_count"),
@@ -349 +367 @@
       r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"),
       r_dcache_tlb_ins("r_dcache_tlb_ins"),
+      r_dcache_tlb_paddr("r_dcache_tlb_paddr"),
       r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"),
       r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"),
+      r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"),
+      r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"),
+      r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"),
       r_dcache_tlb_way("r_dcache_tlb_way"),
       r_dcache_tlb_set("r_dcache_tlb_set"),
@@ -361 +383 @@
 
       r_dcache_cleanup_victim_req("r_dcache_cleanup_victim_req"),
+      r_dcache_cleanup_victim_line_ncc("r_dcache_cleanup_victim_line_ncc"),
+      r_dcache_cleanup_victim_updt_data("r_dcache_cleanup_victim_updt_data"),
       r_dcache_cleanup_victim_nline("r_dcache_cleanup_victim_nline"),
 
@@ -369 +393 @@
       r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"),
 
+      r_dcache_cc_cleanup_updt_data("r_dcache_cc_cleanup_updt_data"),
+      r_dcache_cc_cleanup_line_ncc("r_dcache_cc_cleanup_line_ncc"),
+      r_dcache_dirty_save("r_dcache_dirty_save"),
+      r_cc_send_cpt_word("r_cc_send_cpt_word"),
+      r_dcache_miss_data_cpt("r_dcache_miss_data_cpt"),
+      r_dcache_miss_data_addr("r_dcache_miss_data_addr"),
+      r_dcache_xtn_flush_data_cpt("r_dcache_xtn_flush_data_cpt"),
+      r_dcache_xtn_flush_addr_data("r_dcache_xtn_flush_addr_data"),
+      r_dcache_xtn_state("r_dcache_xtn_state"),
+      r_dcache_xtn_data_addr("r_dcache_xtn_data_addr"),
+      r_dcache_xtn_data_cpt("r_dcache_xtn_data_cpt"),
+      r_dcache_read_state("r_dcache_read_state"),
+
+      r_dcache_paddr_ext("r_dcache_paddr_ext"),
+
       r_vci_cmd_fsm("r_vci_cmd_fsm"),
       r_vci_cmd_min("r_vci_cmd_min"),
@@ -379 +418 @@
       r_vci_rsp_ins_error("r_vci_rsp_ins_error"),
       r_vci_rsp_data_error("r_vci_rsp_data_error"),
-      r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2),    // 2 words depth
-      r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2),    // 2 words depth
-      r_vci_rsp_fifo_rpktid("r_vci_rsp_fifo_rpktid", 2),    // 2 words depth
+      r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth
+      r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth
+      r_vci_rsp_fifo_rpktid("r_vci_rsp_fifo_rpktid", 2), // 2 words depth
       r_cc_send_data_fifo("r_cc_send_data_fifo", 16),
 
@@ -407 +446 @@
       r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"),
       r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"),
+      r_cc_receive_dcache_inval_is_config("r_cc_receive_dcache_inval_is_config"),
+
+      r_dspin_clack_req("r_dspin_clack_req"),
+      r_dspin_clack_flit("r_dspin_clack_flit"),
 
       r_iss(this->name(), proc_id),
@@ -412 +455 @@
       r_icache("icache", icache_ways, icache_sets, icache_words),
       r_dcache("dcache", dcache_ways, dcache_sets, dcache_words),
-      r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N),
-      r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N)
+      r_itlb("itlb", proc_id, itlb_ways, itlb_sets, vci_param::N),
+      r_dtlb("dtlb", proc_id, dtlb_ways, dtlb_sets, vci_param::N),
+
+      r_dcache_llsc_paddr("r_dcache_llsc_paddr"),
+      r_dcache_llsc_key("r_dcache_llsc_key"),
+      r_dcache_llsc_count("r_dcache_llsc_count"),
+      r_dcache_llsc_valid("r_dcache_llsc_valid")
 {
     std::cout << "  - Building VciCcVcacheWrapper : " << name << std::endl;
 
-    assert( ((icache_words*vci_param::B) < (1<<vci_param::K)) and
+    assert(((icache_words*vci_param::B) < (1 << vci_param::K)) and
              "Need more PLEN bits.");
 
-    assert( (vci_param::T > 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and
+    assert((vci_param::T > 2) and ((1 << (vci_param::T - 1)) >= (wbuf_nlines)) and
              "Need more TRDID bits.");
 
-    assert( (icache_words == dcache_words) and
+    assert((icache_words == dcache_words) and
              "icache_words and dcache_words parameters must be equal");
 
-    assert( (itlb_sets == dtlb_sets) and
+    assert((itlb_sets == dtlb_sets) and
              "itlb_sets and dtlb_sets parameters must be equal");
 
-    assert( (itlb_ways == dtlb_ways) and
+    assert((itlb_ways == dtlb_ways) and
              "itlb_ways and dtlb_ways parameters must be equal");
 
@@ -436 +484 @@
                    (uint32_log2(m_itlb_ways)   << 15)   | (uint32_log2(m_itlb_sets)   << 11) |
                    (uint32_log2(m_icache_ways) << 8)    | (uint32_log2(m_icache_sets) << 4)  |
-                   (uint32_log2(m_icache_words<<2));
-
-    r_mmu_release = (uint32_t)(1 << 16) | 0x1;
-
-    ////////////////////MODIFIED///////////////////////////////
-    //r_dcache_in_tlb        = new bool[dcache_ways*dcache_sets];
-    //r_dcache_contains_ptd  = new bool[dcache_ways*dcache_sets];
-    r_dcache_content_state = new int  [dcache_ways*dcache_sets];
-    r_dcache_dirty_word    = new int  [dcache_ways*dcache_sets*dcache_words];
-    r_dcache_zombi_ncc     = new bool [dcache_ways*dcache_sets];
-    ///////////////////////////////////////////////////////////
+                   (uint32_log2(m_icache_words << 2));
+
+    r_mmu_release = (uint32_t) (1 << 16) | 0x1;
+
+    r_dcache_content_state = new int[dcache_ways * dcache_sets];
+    r_dcache_dirty_word    = new int[dcache_ways * dcache_sets * dcache_words];
+    r_dcache_zombi_ncc     = new bool[dcache_ways * dcache_sets];
 
 
@@ -459 +503 @@
     typename iss_t::CacheInfo cache_info;
     cache_info.has_mmu = true;
-    cache_info.icache_line_size = icache_words*sizeof(uint32_t);
+    cache_info.icache_line_size = icache_words * sizeof(uint32_t);
     cache_info.icache_assoc = icache_ways;
     cache_info.icache_n_lines = icache_sets;
-    cache_info.dcache_line_size = dcache_words*sizeof(uint32_t);
+    cache_info.dcache_line_size = dcache_words * sizeof(uint32_t);
     cache_info.dcache_assoc = dcache_ways;
     cache_info.dcache_n_lines = dcache_sets;
@@ -475 +519 @@
     delete [] r_dcache_dirty_word;
     delete [] r_dcache_zombi_ncc;
-    /////////////////////////////////
-    //print_stats();
 }
 
@@ -515 +557 @@
               << " | MMU = " << r_mmu_mode.read();
 
-    if (r_dcache_updt_req.read() ) std::cout << " | P1_UPDT";
-    if (r_dcache_wbuf_req.read() ) std::cout << " | P1_WBUF";
+    if (r_dcache_updt_req.read()) std::cout << " | P1_UPDT";
+    if (r_dcache_wbuf_req.read()) std::cout << " | P1_WBUF";
     std::cout << std::endl;
 
-    if(mode & 0x01)
-    {
-        if ( r_icache_miss_req.read()     ) std::cout << "  IMISS_REQ" << std::endl;
-        if ( r_icache_unc_req.read()      ) std::cout << "  IUNC_REQ" << std::endl;
-        if ( r_dcache_vci_miss_req.read() ) std::cout << "  DMISS_REQ" << std::endl;
-        if ( r_dcache_vci_unc_req.read()  ) std::cout << "  DUNC_REQ" << std::endl;
-
-        r_wbuf.printTrace((mode>>1)&1);
-    }
-    if(mode & 0x02)
+    if (mode & 0x01)
+    {
+        if (r_icache_miss_req.read())     std::cout << "  IMISS_REQ" << std::endl;
+        if (r_icache_unc_req.read())      std::cout << "  IUNC_REQ" << std::endl;
+        if (r_dcache_vci_miss_req.read()) std::cout << "  DMISS_REQ" << std::endl;
+        if (r_dcache_vci_unc_req.read())  std::cout << "  DUNC_REQ" << std::endl;
+
+        r_wbuf.printTrace((mode >> 1) & 1);
+    }
+    if (mode & 0x02)
     {
         r_iss.dump();
     }
-    if(mode & 0x04)
+    if (mode & 0x04)
     {
         std::cout << "  Data Cache" << std::endl;
         r_dcache.printTrace();
     }
-    if(mode & 0x08)
+    if (mode & 0x08)
     {
         std::cout << "  Instruction Cache" << std::endl;
         r_icache.printTrace();
     }
-    if(mode & 0x10)
+    if (mode & 0x10)
     {
         std::cout << "  Data TLB" << std::endl;
         r_dtlb.printTrace();
     }
-    if(mode & 0x20)
+    if (mode & 0x20)
     {
         std::cout << "  Instruction TLB" << std::endl;
@@ -555 +597 @@
 
 //////////////////////////////////////////
-tmpl(void)::cache_monitor( paddr_t addr )
+tmpl(void)::cache_monitor(paddr_t addr)
 //////////////////////////////////////////
 {
-    bool        cache_hit;
-    size_t      cache_way = 0;
-    size_t      cache_set = 0;
-    size_t      cache_word = 0;
-    uint32_t    cache_rdata = 0;
-
-    cache_hit = r_dcache.read_neutral( addr,
-                                       &cache_rdata,
-                                       &cache_way,
-                                       &cache_set,
-                                       &cache_word );
-
-    if ( cache_hit != m_debug_previous_d_hit )
+    bool cache_hit;
+    size_t cache_way = 0;
+    size_t cache_set = 0;
+    size_t cache_word = 0;
+    uint32_t cache_rdata = 0;
+
+    cache_hit = r_dcache.read_neutral(addr,
+                                      &cache_rdata,
+                                      &cache_way,
+                                      &cache_set,
+                                      &cache_word);
+
+    if (cache_hit != m_debug_previous_d_hit)
     {
         std::cout << "Monitor PROC " << name()
@@ -581 +623 @@
     }
 
-    cache_hit = r_icache.read_neutral( addr,
-                                       &cache_rdata,
-                                       &cache_way,
-                                       &cache_set,
-                                       &cache_word );
-
-    if ( cache_hit != m_debug_previous_i_hit )
+    cache_hit = r_icache.read_neutral(addr,
+                                      &cache_rdata,
+                                      &cache_way,
+                                      &cache_set,
+                                      &cache_word);
+
+    if (cache_hit != m_debug_previous_i_hit)
     {
         std::cout << "Monitor PROC " << name()
@@ -609 +651 @@
         << "- READ RATE               = " << (float)m_cpt_data_read/run_cycles << std::endl
         << "- WRITE RATE              = " << (float)m_cpt_data_write/run_cycles << std::endl
-        << "- IMISS_RATE              = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl
-        << "- DMISS RATE              = " << (float)m_cpt_data_miss/(m_cpt_data_read-m_cpt_unc_read) << std::endl
-        << "- INS MISS COST           = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl
-        << "- DATA MISS COST          = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl
+        << "- IMISS_RATE              = " << (float)m_cpt_icache_miss/m_cpt_ins_read << std::endl
+        << "- DMISS RATE              = " << (float)m_cpt_dcache_miss/(m_cpt_data_read-m_cpt_unc_read) << std::endl
+        << "- INS MISS COST           = " << (float)m_cost_ins_miss_frz/m_cpt_icache_miss << std::endl
+        << "- DATA MISS COST          = " << (float)m_cost_data_miss_frz/m_cpt_dcache_miss << std::endl
         << "- WRITE COST              = " << (float)m_cost_write_frz/m_cpt_data_write << std::endl
         << "- UNC COST                = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl
         << "- UNCACHED READ RATE      = " << (float)m_cpt_unc_read/m_cpt_data_read << std::endl
         << "- CACHED WRITE RATE       = " << (float)m_cpt_write_cached/m_cpt_data_write << std::endl
-        << "- INS TLB MISS RATE       = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl
-        << "- DATA TLB MISS RATE      = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl
-        << "- ITLB MISS COST          = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl
-        << "- DTLB MISS COST          = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl
-        << "- ITLB UPDATE ACC COST    = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl
-        << "- DTLB UPDATE ACC COST    = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl
+        << "- INS TLB MISS RATE       = " << (float)m_cpt_itlb_miss/m_cpt_itlb_read << std::endl
+        << "- DATA TLB MISS RATE      = " << (float)m_cpt_dtlb_miss/m_cpt_dtlb_read << std::endl
+        << "- ITLB MISS COST          = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_itlb_miss << std::endl
+        << "- DTLB MISS COST          = " << (float)m_cost_data_tlb_miss_frz/m_cpt_dtlb_miss << std::endl
+        << "- ITLB UPDATE ACC COST    = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_itlb_write << std::endl
+        << "- DTLB UPDATE ACC COST    = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_dtlb_write << std::endl
         << "- DTLB UPDATE DIRTY COST  = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl
-        << "- ITLB HIT IN DCACHE RATE = " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl
-        << "- DTLB HIT IN DCACHE RATE = " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl
-        //<< "- DCACHE FROZEN BY ITLB   = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl
+        << "- ITLB HIT IN DCACHE RATE = " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_itlb_miss << std::endl
+        << "- DTLB HIT IN DCACHE RATE = " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_dtlb_miss << std::endl
         << "- DCACHE FOR TLB %        = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl
         << "- NB CC BROADCAST         = " << m_cpt_cc_broadcast << std::endl
@@ -666 +707 @@
 ////////////////////////
 {
-    m_cpt_dcache_data_read  = 0;
+    m_cpt_dcache_data_read = 0;
     m_cpt_dcache_data_write = 0;
-    m_cpt_dcache_dir_read   = 0;
-    m_cpt_dcache_dir_write  = 0;
-    m_cpt_icache_data_read  = 0;
+    m_cpt_dcache_dir_read = 0;
+    m_cpt_dcache_dir_write = 0;
+    m_cpt_icache_data_read = 0;
     m_cpt_icache_data_write = 0;
-    m_cpt_icache_dir_read   = 0;
-    m_cpt_icache_dir_write  = 0;
-
-    m_cpt_frz_cycles        = 0;
-//    m_cpt_dcache_frz_cycles = 0;
-    m_cpt_total_cycles      = 0;
-
-//    m_cpt_read         = 0;
-//    m_cpt_write        = 0;
-    m_cpt_data_miss    = 0;
-    m_cpt_ins_miss     = 0;
-    m_cpt_unc_read     = 0;
-    m_cpt_write_cached = 0;
-    m_cpt_ins_read     = 0;
-
-    m_cost_write_frz     = 0;
+    m_cpt_icache_dir_read = 0;
+    m_cpt_icache_dir_write = 0;
+
+    m_cpt_frz_cycles = 0;
+    m_cpt_total_cycles = 0;
+
+    m_cpt_data_read = 0;
+    m_cpt_data_write = 0;
+    m_cpt_data_write_back = 0;
+    m_cpt_data_cleanup = 0;
+    m_cpt_data_sc = 0;
+
+    m_cpt_dcache_miss = 0;
+    m_cpt_icache_miss = 0;
+    m_cpt_ins_read = 0;
+
     m_cost_data_miss_frz = 0;
-    m_cost_unc_read_frz  = 0;
-    m_cost_ins_miss_frz  = 0;
-
-    m_cpt_imiss_transaction      = 0;
-    m_cpt_dmiss_transaction      = 0;
-    m_cpt_unc_transaction        = 0;
-    m_cpt_write_transaction      = 0;
-    m_cpt_icache_unc_transaction = 0;
-
-    m_cost_imiss_transaction      = 0;
-    m_cost_dmiss_transaction      = 0;
-    m_cost_unc_transaction        = 0;
-    m_cost_write_transaction      = 0;
-    m_cost_icache_unc_transaction = 0;
-    m_length_write_transaction    = 0;
-
-    m_cpt_ins_tlb_read       = 0;
-    m_cpt_ins_tlb_miss       = 0;
-    m_cpt_ins_tlb_update_acc = 0;
-
-    m_cpt_data_tlb_read         = 0;
-    m_cpt_data_tlb_miss         = 0;
-    m_cpt_data_tlb_update_acc   = 0;
-    m_cpt_data_tlb_update_dirty = 0;
-    m_cpt_ins_tlb_hit_dcache    = 0;
-    m_cpt_data_tlb_hit_dcache   = 0;
-    m_cpt_ins_tlb_occup_cache   = 0;
-    m_cpt_data_tlb_occup_cache  = 0;
-
-    m_cost_ins_tlb_miss_frz          = 0;
-    m_cost_data_tlb_miss_frz         = 0;
-    m_cost_ins_tlb_update_acc_frz    = 0;
-    m_cost_data_tlb_update_acc_frz   = 0;
-    m_cost_data_tlb_update_dirty_frz = 0;
-    m_cost_ins_tlb_occup_cache_frz   = 0;
-    m_cost_data_tlb_occup_cache_frz  = 0;
-
-    m_cpt_itlbmiss_transaction      = 0;
-    m_cpt_itlb_ll_transaction       = 0;
-    m_cpt_itlb_sc_transaction       = 0;
-    m_cpt_dtlbmiss_transaction      = 0;
-    m_cpt_dtlb_ll_transaction       = 0;
-    m_cpt_dtlb_sc_transaction       = 0;
-    m_cpt_dtlb_ll_dirty_transaction = 0;
-    m_cpt_dtlb_sc_dirty_transaction = 0;
-
-    m_cost_itlbmiss_transaction      = 0;
-    m_cost_itlb_ll_transaction       = 0;
-    m_cost_itlb_sc_transaction       = 0;
-    m_cost_dtlbmiss_transaction      = 0;
-    m_cost_dtlb_ll_transaction       = 0;
-    m_cost_dtlb_sc_transaction       = 0;
-    m_cost_dtlb_ll_dirty_transaction = 0;
-    m_cost_dtlb_sc_dirty_transaction = 0;
-
-//    m_cpt_cc_update_data = 0;
-//    m_cpt_cc_inval_ins   = 0;
-//    m_cpt_cc_inval_data  = 0;
-    m_cpt_cc_broadcast   = 0;
-
-    m_cost_updt_data_frz  = 0;
-    m_cost_inval_ins_frz  = 0;
-    m_cost_inval_data_frz = 0;
-    m_cost_broadcast_frz  = 0;
-
-    m_cpt_cc_cleanup_data = 0;
-    m_cpt_cc_cleanup_ins  = 0;
-
-    m_cpt_cleanup_data_not_dirty  = 0;
+    m_cost_ins_miss_frz = 0;
+
+    m_cpt_write_transaction = 0;
+    m_length_write_transaction = 0;
+
+    m_cpt_itlb_read = 0;
+    m_cpt_itlb_miss = 0;
+    m_cpt_itlb_write = 0;
+    m_cost_ins_tlb_miss_frz = 0;
+
+    m_cpt_dtlb_read = 0;
+    m_cpt_dtlb_miss = 0;
+    m_cpt_dtlb_write = 0;
+
+    m_cpt_cleanup_data_not_dirty = 0;
     m_cpt_cleanup_data_dirty_word = 0;
     m_cpt_data_write_miss = 0;
     m_cpt_data_write_on_zombi = 0;
     m_cpt_data_write_on_zombi_ncc = 0;
-
 }
-
-
 
 /////////////////////////
@@ -771 +755 @@
 /////////////////////////
 {
-    if ( not p_resetn.read() )
+    if (not p_resetn.read())
     {
         r_iss.reset();
@@ -780 +764 @@
         r_dtlb.reset();
 
-        r_dcache_fsm      = DCACHE_IDLE;
-        r_icache_fsm      = ICACHE_IDLE;
-        r_vci_cmd_fsm     = CMD_IDLE;
-        r_vci_rsp_fsm     = RSP_IDLE;
-        r_cc_receive_fsm  = CC_RECEIVE_IDLE;
-        r_cc_send_fsm     = CC_SEND_IDLE;
+        r_dcache_fsm     = DCACHE_IDLE;
+        r_icache_fsm     = ICACHE_IDLE;
+        r_vci_cmd_fsm    = CMD_IDLE;
+        r_vci_rsp_fsm    = RSP_IDLE;
+        r_cc_receive_fsm = CC_RECEIVE_IDLE;
+        r_cc_send_fsm    = CC_SEND_IDLE;
 
         // reset data physical address extension
@@ -794 +778 @@
 
         // reset dcache directory extension
-        for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++)
+        for (size_t i = 0; i < m_dcache_ways * m_dcache_sets; i++)
         {
             r_dcache_content_state[i] = LINE_CACHE_DATA_NOT_DIRTY;
-            r_dcache_dirty_word[i]    = 0;
-            r_dcache_zombi_ncc[i]     = false;
+            r_dcache_dirty_word[i] = 0;
+            r_dcache_zombi_ncc[i] = false;
         }
 
@@ -838 +822 @@
 
         // No request from DCACHE FSM to CC_SEND FSM
-        r_dcache_cc_send_req       = false;
+        r_dcache_cc_send_req        = false;
+        r_dcache_cleanup_victim_req = false;
+
         r_dcache_clack_req         = false;
 
@@ -867 +853 @@
         m_debug_activated          = false;
 
-        // SPECIAL REGISTERS ODCCP
+        // RWT
         r_dcache_cc_cleanup_updt_data = false;
         r_dcache_cc_cleanup_line_ncc  = false;
-        r_dcache_miss_victim_no_coherence = false;
-        r_dcache_line_no_coherence = false;
         r_cc_send_cpt_word = 0;
         r_dcache_miss_data_cpt = 0;
         r_dcache_miss_data_addr = 0;
 
-        r_dcache_cleanup_victim_req = false;
         r_dcache_cleanup_victim_line_ncc = false;
         r_dcache_cleanup_victim_updt_data = false;
@@ -894 +877 @@
         m_cpt_stop_simulation   = 0;
 
-        m_cpt_data_miss         = 0;
+        m_cpt_data_read         = 0;
+
+        m_cpt_dcache_miss       = 0;
         m_cpt_data_write        = 0;
         m_cpt_data_sc           = 0;
@@ -900 +885 @@
         m_cpt_data_cleanup      = 0;
         m_cpt_cleanup_data_not_dirty = 0;
-        m_cpt_ins_miss          = 0;
+        m_cpt_icache_miss       = 0;
         m_cpt_unc_read          = 0;
         m_cpt_write_cached      = 0;
@@ -910 +895 @@
         m_cost_ins_miss_frz     = 0;
 
+        m_cpt_dunc_transaction  = 0;
+        m_cpt_ll_transaction    = 0;
+
         m_cpt_imiss_transaction = 0;
         m_cpt_dmiss_transaction = 0;
         m_cpt_unc_transaction   = 0;
         m_cpt_write_transaction = 0;
-        m_cpt_icache_unc_transaction = 0;
 
         m_cost_imiss_transaction      = 0;
@@ -920 +907 @@
         m_cost_unc_transaction        = 0;
         m_cost_write_transaction      = 0;
-        m_cost_icache_unc_transaction = 0;
         m_length_write_transaction    = 0;
 
-        m_cpt_ins_tlb_read       = 0;
-        m_cpt_ins_tlb_miss       = 0;
-        m_cpt_ins_tlb_update_acc = 0;
-
-        m_cpt_data_tlb_read         = 0;
-        m_cpt_data_tlb_miss         = 0;
-        m_cpt_data_tlb_update_acc   = 0;
+        m_cpt_itlb_read  = 0;
+        m_cpt_itlb_miss  = 0;
+        m_cpt_itlb_write = 0;
+
+        m_cpt_dtlb_read  = 0;
+        m_cpt_dtlb_miss  = 0;
+        m_cpt_dtlb_write = 0;
+
+        m_cpt_tlb_occup_dcache      = 0;
         m_cpt_data_tlb_update_dirty = 0;
         m_cpt_ins_tlb_hit_dcache    = 0;
         m_cpt_data_tlb_hit_dcache   = 0;
-        m_cpt_ins_tlb_occup_cache   = 0;
-        m_cpt_data_tlb_occup_cache  = 0;
 
         m_cost_ins_tlb_miss_frz          = 0;
@@ -941 +927 @@
         m_cost_data_tlb_update_acc_frz   = 0;
         m_cost_data_tlb_update_dirty_frz = 0;
-        m_cost_ins_tlb_occup_cache_frz   = 0;
-        m_cost_data_tlb_occup_cache_frz  = 0;
-
-        m_cpt_ins_tlb_inval       = 0;
-        m_cpt_data_tlb_inval      = 0;
-        m_cost_ins_tlb_inval_frz  = 0;
-        m_cost_data_tlb_inval_frz = 0;
+
+        m_cpt_cc_update_dcache = 0;
+        m_cpt_cc_inval_icache  = 0;
+        m_cpt_cc_inval_dcache  = 0;
 
         m_cpt_cc_broadcast   = 0;
@@ -966 +949 @@
 
         m_cpt_itlbmiss_transaction      = 0;
-        m_cpt_itlb_ll_transaction       = 0;
-        m_cpt_itlb_sc_transaction       = 0;
         m_cpt_dtlbmiss_transaction      = 0;
-        m_cpt_dtlb_ll_transaction       = 0;
-        m_cpt_dtlb_sc_transaction       = 0;
-        m_cpt_dtlb_ll_dirty_transaction = 0;
-        m_cpt_dtlb_sc_dirty_transaction = 0;
 
         m_cost_itlbmiss_transaction      = 0;
-        m_cost_itlb_ll_transaction       = 0;
-        m_cost_itlb_sc_transaction       = 0;
         m_cost_dtlbmiss_transaction      = 0;
-        m_cost_dtlb_ll_transaction       = 0;
-        m_cost_dtlb_sc_transaction       = 0;
-        m_cost_dtlb_ll_dirty_transaction = 0;
-        m_cost_dtlb_sc_dirty_transaction = 0;
-/*
-        m_cpt_dcache_frz_cycles = 0;
-        m_cpt_read              = 0;
-        m_cpt_write             = 0;
-        m_cpt_cc_update_data = 0;
-        m_cpt_cc_inval_ins   = 0;
-        m_cpt_cc_inval_data  = 0;
-*/
-
-        for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache      [i]   = 0;
-        for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache      [i]   = 0;
-        for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd         [i]   = 0;
-        for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp         [i]   = 0;
+
+        for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_icache[i] = 0;
+        for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_dcache[i] = 0;
+        for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_cmd[i] = 0;
+        for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_rsp[i] = 0;
 
         // init the llsc reservation buffer
@@ -1004 +967 @@
 
     // Response FIFOs default values
-    bool       vci_rsp_fifo_icache_get   = false;
-    bool       vci_rsp_fifo_icache_put   = false;
-    uint32_t   vci_rsp_fifo_icache_data  = 0;
-
-    bool       vci_rsp_fifo_dcache_get   = false;
-    bool       vci_rsp_fifo_dcache_put   = false;
-    uint32_t   vci_rsp_fifo_dcache_data  = 0;
-    bool       vci_rsp_fifo_rpktid_get   = false;
-    bool       vci_rsp_fifo_rpktid_put   = false;
-    bool       vci_rsp_fifo_rpktid       = false;
+    bool     vci_rsp_fifo_icache_get  = false;
+    bool     vci_rsp_fifo_icache_put  = false;
+    uint32_t vci_rsp_fifo_icache_data = 0;
+
+    bool     vci_rsp_fifo_dcache_get  = false;
+    bool     vci_rsp_fifo_dcache_put  = false;
+    uint32_t vci_rsp_fifo_dcache_data = 0;
+
+    bool     vci_rsp_fifo_rpktid_get  = false;
+    bool     vci_rsp_fifo_rpktid_put  = false;
+    bool     vci_rsp_fifo_rpktid      = false;
 
     // FIFO for cleanup data updt
-    bool       cleanup_data_updt_fifo_dcache_get   = false;
-    bool       cleanup_data_updt_fifo_dcache_put   = false;
-    uint32_t   cleanup_data_updt_fifo_dcache_data  = 0;
+    bool     cleanup_data_updt_fifo_dcache_get  = false;
+    bool     cleanup_data_updt_fifo_dcache_put  = false;
+    uint32_t cleanup_data_updt_fifo_dcache_data = 0;
 
     // updt fifo
-    bool       cc_receive_updt_fifo_get  = false;
-    bool       cc_receive_updt_fifo_put  = false;
-    uint32_t   cc_receive_updt_fifo_be   = 0;
-    uint32_t   cc_receive_updt_fifo_data = 0;
-    bool       cc_receive_updt_fifo_eop  = false;
+    bool     cc_receive_updt_fifo_get  = false;
+    bool     cc_receive_updt_fifo_put  = false;
+    uint32_t cc_receive_updt_fifo_be   = 0;
+    uint32_t cc_receive_updt_fifo_data = 0;
+    bool     cc_receive_updt_fifo_eop  = false;
 
 #ifdef INSTRUMENTATION
@@ -1099 +1063 @@
 
     // default value for m_irsp
-    m_irsp.valid       = false;
-    m_irsp.error       = false;
+    m_irsp.valid = false;
+    m_irsp.error = false;
     m_irsp.instruction = 0;
 
-    switch( r_icache_fsm.read() )
+    switch (r_icache_fsm.read())
     {
     /////////////////
@@ -1115 +1079 @@
     {
         // coherence clack interrupt
-        if ( r_icache_clack_req.read() )
+        if (r_icache_clack_req.read())
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1123 +1087 @@
 
         // coherence interrupt
-        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
+        if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1133 +1097 @@
         // These request are not executed in this IDLE state (except XTN_INST_PADDR_EXT),
         // because they require access to icache or itlb, that are already accessed
-        if ( r_dcache_xtn_req.read() )
-        {
-            if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR )
-            {
-                r_icache_fsm         = ICACHE_XTN_TLB_FLUSH;
-            }
-            else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH)
+        if (r_dcache_xtn_req.read())
+        {
+            if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_PTPR)
+            {
+                r_icache_fsm = ICACHE_XTN_TLB_FLUSH;
+            }
+            else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ICACHE_FLUSH)
             {
                 r_icache_flush_count = 0;
-                r_icache_fsm         = ICACHE_XTN_CACHE_FLUSH;
-            }
-            else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL)
-            {
-                r_icache_fsm         = ICACHE_XTN_TLB_INVAL;
-            }
-            else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL)
-            {
-                r_icache_fsm         = ICACHE_XTN_CACHE_INVAL_VA;
-            }
-            else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV)
+                r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
+            }
+            else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ITLB_INVAL)
+            {
+                r_icache_fsm = ICACHE_XTN_TLB_INVAL;
+            }
+            else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ICACHE_INVAL)
+            {
+                r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA;
+            }
+            else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_MMU_ICACHE_PA_INV)
             {
                 if (sizeof(paddr_t) <= 32)
@@ -1158 +1122 @@
                     assert(r_mmu_word_hi.read() == 0 &&
                     "illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr");
-                    r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read();
+                    r_icache_vci_paddr = (paddr_t) r_mmu_word_lo.read();
                 }
                 else
                 {
-                    r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 |
-                                         (paddr_t)r_mmu_word_lo.read();
+                    r_icache_vci_paddr = (paddr_t) r_mmu_word_hi.read() << 32 |
+                                         (paddr_t) r_mmu_word_lo.read();
                 }
                 r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA;
             }
-            else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_INST_PADDR_EXT)
+            else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_INST_PADDR_EXT)
             {
                 r_icache_paddr_ext = r_dcache_save_wdata.read();
@@ -1174 +1138 @@
             else
             {
-               assert( false and
+               assert(false and
                "undefined XTN request received by ICACHE FSM");
             }
@@ -1181 +1145 @@
 
         // processor request
-        if ( m_ireq.valid )
-        {
-            bool        cacheable;
-            paddr_t     paddr;
-            bool        tlb_hit = false;
-            pte_info_t  tlb_flags;
-            size_t      tlb_way;
-            size_t      tlb_set;
-            paddr_t     tlb_nline;
-            uint32_t    cache_inst = 0;
-            size_t      cache_way;
-            size_t      cache_set;
-            size_t      cache_word;
-            int         cache_state = CACHE_SLOT_STATE_EMPTY;
+        if (m_ireq.valid)
+        {
+            bool       cacheable;
+            paddr_t    paddr;
+            bool       tlb_hit = false;
+            pte_info_t tlb_flags;
+            size_t     tlb_way;
+            size_t     tlb_set;
+            paddr_t    tlb_nline;
+            uint32_t   cache_inst = 0;
+            size_t     cache_way;
+            size_t     cache_set;
+            size_t     cache_word;
+            int        cache_state = CACHE_SLOT_STATE_EMPTY;
 
             // We register processor request
@@ -1201 +1165 @@
 
             // sytematic itlb access (if activated)
-            if ( r_mmu_mode.read() & INS_TLB_MASK )
+            if (r_mmu_mode.read() & INS_TLB_MASK)
             {
 
 #ifdef INSTRUMENTATION
-m_cpt_ins_tlb_read++;
-#endif
-                tlb_hit = r_itlb.translate( m_ireq.addr,
-                                            &paddr,
-                                            &tlb_flags,
-                                            &tlb_nline, // unused
-                                            &tlb_way,   // unused
-                                            &tlb_set ); // unused
+                m_cpt_itlb_read++;
+#endif
+                tlb_hit = r_itlb.translate(m_ireq.addr,
+                                           &paddr,
+                                           &tlb_flags,
+                                           &tlb_nline, // unused
+                                           &tlb_way,   // unused
+                                           &tlb_set);  // unused
             }
             else if (vci_param::N > 32)
@@ -1220 +1184 @@
 
             // systematic icache access (if activated)
-            if ( r_mmu_mode.read() & INS_CACHE_MASK )
+            if (r_mmu_mode.read() & INS_CACHE_MASK)
             {
 
 
 #ifdef INSTRUMENTATION
-m_cpt_icache_data_read++;
-m_cpt_icache_dir_read++;
-#endif
-                r_icache.read( paddr,
-                               &cache_inst,
-                               &cache_way,
-                               &cache_set,
-                               &cache_word,
-                               &cache_state );
+                m_cpt_icache_data_read++;
+                m_cpt_icache_dir_read++;
+#endif
+                r_icache.read(paddr,
+                              &cache_inst,
+                              &cache_way,
+                              &cache_set,
+                              &cache_word,
+                              &cache_state);
             }
 
@@ -1242 +1206 @@
             //   and there is no access rights checking
 
-            if ( not (r_mmu_mode.read() & INS_TLB_MASK) )   // tlb not activated:
+            if (not (r_mmu_mode.read() & INS_TLB_MASK)) // tlb not activated:
             {
                 // cacheability
-                if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
-                else     cacheable = m_cacheability_table[(uint64_t)m_ireq.addr];
-            }
-            else                          // itlb activated
-            {
-                if ( tlb_hit )  // ITLB hit
+                if   (not (r_mmu_mode.read() & INS_CACHE_MASK)) cacheable = false;
+                else cacheable = m_cacheability_table[(uint64_t) m_ireq.addr];
+            }
+            else // itlb activated
+            {
+                if (tlb_hit) // ITLB hit
                 {
                     // cacheability
-                    if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false;
-                    else  cacheable = tlb_flags.c;
+                    if   (not (r_mmu_mode.read() & INS_CACHE_MASK)) cacheable = false;
+                    else cacheable = tlb_flags.c;
 
                     // access rights checking
-                    if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) )
+                    if (not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER))
                     {
-                        r_mmu_ietr          = MMU_READ_PRIVILEGE_VIOLATION;
-                        r_mmu_ibvar         = m_ireq.addr;
-                        m_irsp.valid        = true;
-                        m_irsp.error        = true;
-                        m_irsp.instruction  = 0;
+
+#if DEBUG_ICACHE
+                        if (m_debug_activated)
+                            std::cout << "  <PROC " << name() << " ICACHE_IDLE> MMU Privilege Violation"
+                                << " : PADDR = " << std::hex << paddr << std::endl;
+#endif
+                        r_mmu_ietr         = MMU_READ_PRIVILEGE_VIOLATION;
+                        r_mmu_ibvar        = m_ireq.addr;
+                        m_irsp.valid       = true;
+                        m_irsp.error       = true;
+                        m_irsp.instruction = 0;
                         break;
                     }
-                    else if ( not tlb_flags.x )
+                    else if (not tlb_flags.x)
                     {
-                        r_mmu_ietr          = MMU_READ_EXEC_VIOLATION;
-                        r_mmu_ibvar         = m_ireq.addr;
-                        m_irsp.valid        = true;
-                        m_irsp.error        = true;
-                        m_irsp.instruction  = 0;
+
+#if DEBUG_ICACHE
+                        if (m_debug_activated)
+                        {
+                            std::cout << "  <PROC " << name() << " ICACHE_IDLE> MMU Executable Violation"
+                                << " : PADDR = " << std::hex << paddr << std::endl;
+                        }
+#endif
+                        r_mmu_ietr         = MMU_READ_EXEC_VIOLATION;
+                        r_mmu_ibvar        = m_ireq.addr;
+                        m_irsp.valid       = true;
+                        m_irsp.error       = true;
+                        m_irsp.instruction = 0;
                         break;
                     }
                 }
-                else           // ITLB miss
+                else // ITLB miss
                 {
 
 #ifdef INSTRUMENTATION
-m_cpt_ins_tlb_miss++;
+                    m_cpt_itlb_miss++;
 #endif
                     r_icache_fsm          = ICACHE_TLB_WAIT;
@@ -1289 +1267 @@
 
             // physical address registration
-            r_icache_vci_paddr   = paddr;
+            r_icache_vci_paddr = paddr;
 
             // Finally, we send the response to processor, and compute next state
-            if ( cacheable )
-            {
-
-                if (cache_state == CACHE_SLOT_STATE_EMPTY)      // cache miss
+            if (cacheable)
+            {
+                if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss
                 {
 
 #ifdef INSTRUMENTATION
-m_cpt_ins_miss++;
+                    m_cpt_icache_miss++;
 #endif
                     // we request a VCI transaction
-                    r_icache_fsm      = ICACHE_MISS_SELECT;
+                    r_icache_fsm = ICACHE_MISS_SELECT;
 #if DEBUG_ICACHE
-if ( m_debug_activated )
-std::cout << "  <PROC " << name() << " ICACHE_IDLE> READ MISS in icache"
-          << " : PADDR = " << std::hex << paddr << std::endl;
+                    if (m_debug_activated)
+                    {
+                        std::cout << "  <PROC " << name() << " ICACHE_IDLE> READ MISS in icache"
+                            << " : PADDR = " << std::hex << paddr << std::endl;
+                    }
 #endif
                    r_icache_miss_req = true;
                 }
-                else if (cache_state == CACHE_SLOT_STATE_ZOMBI )    // pending cleanup
+                else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
                 {
                     // stalled until cleanup is acknowledged
-                    r_icache_fsm       = ICACHE_IDLE;
-                }
-                else                                       // cache hit
+                    r_icache_fsm = ICACHE_IDLE;
+                }
+                else // cache hit
                 {
 
 #ifdef INSTRUMENTATION
-m_cpt_ins_read++;
+                    m_cpt_ins_read++;
 #endif
                     // return instruction to processor
@@ -1326 +1305 @@
                     r_icache_fsm       = ICACHE_IDLE;
 #if DEBUG_ICACHE
-if ( m_debug_activated )
-std::cout << "  <PROC " << name() << " ICACHE_IDLE> READ HIT in icache"
-          << " : PADDR = " << std::hex << paddr
-          << " / INST  = " << cache_inst << std::dec << std::endl;
-#endif
-                }
-            }
-            else               // non cacheable read
-            {
-                r_icache_unc_req  = true;
-                r_icache_fsm      = ICACHE_UNC_WAIT;
+                    if (m_debug_activated)
+                    {
+                        std::cout << "  <PROC " << name() << " ICACHE_IDLE> READ HIT in icache"
+                            << " : PADDR = " << std::hex << paddr
+                            << " / INST  = " << cache_inst << std::dec << std::endl;
+                    }
+#endif
+                }
+            }
+            else // non cacheable read
+            {
+                r_icache_unc_req = true;
+                r_icache_fsm     = ICACHE_UNC_WAIT;
 
 #if DEBUG_ICACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " ICACHE_IDLE> READ UNCACHEABLE in icache"
-              << " : PADDR = " << std::hex << paddr << std::endl;
-}
+                if (m_debug_activated)
+                {
+                    std::cout << "  <PROC " << name()
+                        << " ICACHE_IDLE> READ UNCACHEABLE in icache"
+                        << " : PADDR = " << std::hex << paddr << std::endl;
+                }
 #endif
             }
@@ -1359 +1340 @@
     {
         // coherence clack interrupt
-        if ( r_icache_clack_req.read() )
+        if (r_icache_clack_req.read())
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1367 +1348 @@
 
         // coherence interrupt
-        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
+        if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1374 +1355 @@
         }
 
-        if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++;
+        if (m_ireq.valid) m_cost_ins_tlb_miss_frz++;
 
         // DCACHE FSM signals response by reseting the request flip-flop
-        if ( not r_icache_tlb_miss_req.read() )
-        {
-            if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated
+        if (not r_icache_tlb_miss_req.read())
+        {
+            if (r_icache_tlb_rsp_error.read()) // error reported : tlb not updated
             {
                 r_icache_tlb_rsp_error = false;
-                m_irsp.error             = true;
-                m_irsp.valid             = true;
-                r_icache_fsm             = ICACHE_IDLE;
-            }
-            else                // tlb updated : return to IDLE state
+                m_irsp.error = true;
+                m_irsp.valid = true;
+                r_icache_fsm = ICACHE_IDLE;
+            }
+            else // tlb updated : return to IDLE state
             {
                 r_icache_fsm  = ICACHE_IDLE;
@@ -1394 +1375 @@
     }
     //////////////////////////
-    case ICACHE_XTN_TLB_FLUSH:      // invalidate in one cycle all non global TLB entries
+    case ICACHE_XTN_TLB_FLUSH:  // invalidate in one cycle all non global TLB entries
     {
         r_itlb.flush();
-        r_dcache_xtn_req     = false;
-        r_icache_fsm         = ICACHE_IDLE;
+        r_dcache_xtn_req = false;
+        r_icache_fsm     = ICACHE_IDLE;
         break;
     }
@@ -1411 +1392 @@
     {
         // coherence clack interrupt
-        if ( r_icache_clack_req.read() )
+        if (r_icache_clack_req.read())
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1419 +1400 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
+        if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1426 +1407 @@
         }
 
-        if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request is sent
-        {
-            int       state;
-            paddr_t   tag;
-            size_t    way = r_icache_flush_count.read()/m_icache_sets;
-            size_t    set = r_icache_flush_count.read()%m_icache_sets;
+        if (not r_icache_cc_send_req.read()) // blocked until previous cc_send request is sent
+        {
+            int state;
+            paddr_t tag;
+            size_t way = r_icache_flush_count.read() / m_icache_sets;
+            size_t set = r_icache_flush_count.read() % m_icache_sets;
 
 #ifdef INSTRUMENTATION
-m_cpt_icache_dir_read++;
-#endif
-            r_icache.read_dir( way,
-                               set,
-                               &tag,
-                               &state );
-
-            if ( state == CACHE_SLOT_STATE_VALID_CC )    // inval required
+            m_cpt_icache_dir_read++;
+#endif
+            r_icache.read_dir(way,
+                              set,
+                              &tag,
+                              &state);
+
+            if (state == CACHE_SLOT_STATE_VALID_CC)    // inval required
             {
                 // request cleanup
@@ -1450 +1431 @@
 
                 // goes to ICACHE_XTN_CACHE_FLUSH_GO to make inval
-                r_icache_miss_way     = way;
-                r_icache_miss_set     = set;
-                r_icache_fsm          = ICACHE_XTN_CACHE_FLUSH_GO;
-            }
-            else if ( r_icache_flush_count.read() ==
-                      (m_icache_sets*m_icache_ways - 1) )  // last slot
+                r_icache_miss_way = way;
+                r_icache_miss_set = set;
+                r_icache_fsm      = ICACHE_XTN_CACHE_FLUSH_GO;
+            }
+            else if (r_icache_flush_count.read() ==
+                      (m_icache_sets*m_icache_ways - 1))  // last slot
             {
                 r_dcache_xtn_req = false;
-                m_drsp.valid     = true;
-                r_icache_fsm     = ICACHE_IDLE;
+                m_drsp.valid = true;
+                r_icache_fsm = ICACHE_IDLE;
             }
 
             // saturation counter, to have the same last slot condition
             // in ICACHE_XTN_CACHE_FLUSH and ICACHE_XTN_CACHE_FLUSH_GO states
-            if ( r_icache_flush_count.read() < (m_icache_sets*m_icache_ways - 1) )
+            if (r_icache_flush_count.read() < (m_icache_sets * m_icache_ways - 1))
             {
                 r_icache_flush_count = r_icache_flush_count.read() + 1;
@@ -1472 +1453 @@
     }
     ///////////////////////////////
-    case ICACHE_XTN_CACHE_FLUSH_GO:     // Switch slot state to ZOMBI for an XTN flush
-    {
-        size_t  way = r_icache_miss_way.read();
-        size_t  set = r_icache_miss_set.read();
+    case ICACHE_XTN_CACHE_FLUSH_GO:   // Switch slot state to ZOMBI for an XTN flush
+    {
+        size_t way = r_icache_miss_way.read();
+        size_t set = r_icache_miss_set.read();
 
 #ifdef INSTRUMENTATION
-m_cpt_icache_dir_write++;
-#endif
-
-        r_icache.write_dir( way,
-                            set,
-                            CACHE_SLOT_STATE_ZOMBI );
-
-        if ( r_icache_flush_count.read() ==
-                      (m_icache_sets*m_icache_ways - 1) )  // last slot
+        m_cpt_icache_dir_write++;
+#endif
+
+        r_icache.write_dir(way,
+                           set,
+                           CACHE_SLOT_STATE_ZOMBI);
+
+        if (r_icache_flush_count.read() ==
+                      (m_icache_sets*m_icache_ways - 1))  // last slot
         {
             r_dcache_xtn_req = false;
-            m_drsp.valid     = true;
-            r_icache_fsm     = ICACHE_IDLE;
+            m_drsp.valid = true;
+            r_icache_fsm = ICACHE_IDLE;
         }
         else
         {
-            r_icache_fsm         = ICACHE_XTN_CACHE_FLUSH;
+            r_icache_fsm = ICACHE_XTN_CACHE_FLUSH;
         }
         break;
@@ -1500 +1481 @@
 
     //////////////////////////
-    case ICACHE_XTN_TLB_INVAL:      // invalidate one TLB entry selected by the virtual address
-                                    // stored in the r_dcache_save_wdata register
+    case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address
+                               // stored in the r_dcache_save_wdata register
     {
         r_itlb.inval(r_dcache_save_wdata.read());
-        r_dcache_xtn_req     = false;
-        r_icache_fsm         = ICACHE_IDLE;
+        r_dcache_xtn_req = false;
+        r_icache_fsm     = ICACHE_IDLE;
         break;
     }
@@ -1518 +1499 @@
 
         // read physical address in TLB when MMU activated
-        if ( r_mmu_mode.read() & INS_TLB_MASK )     // itlb activated
+        if (r_mmu_mode.read() & INS_TLB_MASK) // itlb activated
         {
 
 #ifdef INSTRUMENTATION
-m_cpt_ins_tlb_read++;
-#endif
-            hit = r_itlb.translate(r_dcache_save_wdata.read(),
-                                   &paddr);
-        }
-        else                        // itlb not activated
-        {
-            paddr   = (paddr_t)r_dcache_save_wdata.read();
-            hit     = true;
-        }
-
-        if ( hit )      // continue the selective inval process
-        {
-            r_icache_vci_paddr    = paddr;
-            r_icache_fsm          = ICACHE_XTN_CACHE_INVAL_PA;
-        }
-        else            // miss : send a request to DCACHE FSM
+            m_cpt_itlb_read++;
+#endif
+            hit = r_itlb.translate(r_dcache_save_wdata.read(), &paddr);
+        }
+        else // itlb not activated
+        {
+            paddr = (paddr_t) r_dcache_save_wdata.read();
+            hit   = true;
+        }
+
+        if (hit) // continue the selective inval process
+        {
+            r_icache_vci_paddr = paddr;
+            r_icache_fsm       = ICACHE_XTN_CACHE_INVAL_PA;
+        }
+        else // miss : send a request to DCACHE FSM
         {
 
 #ifdef INSTRUMENTATION
-m_cpt_ins_tlb_miss++;
+            m_cpt_itlb_miss++;
 #endif
             r_icache_tlb_miss_req = true;
@@ -1555 +1535 @@
                                     // with address stored in r_icache_vci_paddr register.
     {
-        int         state;
-        size_t      way;
-        size_t      set;
-        size_t      word;
+        int    state;
+        size_t way;
+        size_t set;
+        size_t word;
 
 #ifdef INSTRUMENTATION
-m_cpt_icache_dir_read++;
+        m_cpt_icache_dir_read++;
 #endif
         r_icache.read_dir(r_icache_vci_paddr.read(),
@@ -1569 +1549 @@
                           &word);
 
-        if ( state == CACHE_SLOT_STATE_VALID_CC )   // inval to be done
+        if (state == CACHE_SLOT_STATE_VALID_CC) // inval to be done
         {
             r_icache_miss_way = way;
@@ -1575 +1555 @@
             r_icache_fsm      = ICACHE_XTN_CACHE_INVAL_GO;
         }
-        else        // miss : acknowlege the XTN request and return
+        else // miss : acknowlege the XTN request and return
         {
             r_dcache_xtn_req = false;
@@ -1585 +1565 @@
     case ICACHE_XTN_CACHE_INVAL_GO:  // Switch slot to ZOMBI state for an XTN inval
     {
-        if ( not r_icache_cc_send_req.read() )  // blocked until previous cc_send request not sent
+        if (not r_icache_cc_send_req.read())  // blocked until previous cc_send request not sent
         {
 
 #ifdef INSTRUMENTATION
-m_cpt_icache_dir_write++;
-#endif
-            r_icache.write_dir( r_icache_miss_way.read(),
-                                r_icache_miss_set.read(),
-                                CACHE_SLOT_STATE_ZOMBI );
+            m_cpt_icache_dir_write++;
+#endif
+            r_icache.write_dir(r_icache_miss_way.read(),
+                               r_icache_miss_set.read(),
+                               CACHE_SLOT_STATE_ZOMBI);
 
             // request cleanup
             r_icache_cc_send_req   = true;
-            r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
+            r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words << 2);
             r_icache_cc_send_way   = r_icache_miss_way.read();
             r_icache_cc_send_type  = CC_TYPE_CLEANUP;
 
             // acknowledge the XTN request and return
-            r_dcache_xtn_req      = false;
-            r_icache_fsm          = ICACHE_IDLE;
+            r_dcache_xtn_req = false;
+            r_icache_fsm     = ICACHE_IDLE;
         }
         break;
@@ -1609 +1589 @@
     ////////////////////////
     case ICACHE_MISS_SELECT:       // Try to select a slot in associative set,
-                                   // if previous cleanup has been sent.
                                    // Waiting in this state if no slot available.
-                                   // Set the r_icache_cleanup_req flip-flop
-                                   // and the r_icache_miss_clack flip-flop,
+                                   // If a victim slot has been choosen and the r_icache_cc_send_req is false,
+                                   // we send the cleanup request in this state.
+                                   // If not, a r_icache_cleanup_victim_req flip-flop is
+                                   // utilized for saving this cleanup request, and it will be sent later
+                                   // in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR.
+                                   // The r_icache_miss_clack flip-flop is set
                                    // when a cleanup is required
     {
@@ -1618 +1601 @@
 
         // coherence clack interrupt
-        if ( r_icache_clack_req.read() )
+        if (r_icache_clack_req.read())
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1626 +1609 @@
 
         // coherence interrupt
-        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
+        if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1634 +1617 @@
 
 
-        bool        found;
-        bool        cleanup;
-        size_t      way;
-        size_t      set;
-        paddr_t     victim;
+        bool found;
+        bool cleanup;
+        size_t way;
+        size_t set;
+        paddr_t victim;
 
 #ifdef INSTRUMENTATION
-m_cpt_icache_dir_read++;
+        m_cpt_icache_dir_read++;
 #endif
         r_icache.read_select(r_icache_vci_paddr.read(),
@@ -1648 +1631 @@
                              &set,
                              &found,
-                             &cleanup );
-        if ( found )
-        {
-            r_icache_miss_way     = way;
-            r_icache_miss_set     = set;
-
-            if ( cleanup )
-            {
-                if ( not r_icache_cc_send_req.read() )
-                {
-                    r_icache_cc_send_req    = true;
-                    r_icache_cc_send_nline  = victim;
-                    r_icache_cc_send_way    = way;
-                    r_icache_cc_send_type   = CC_TYPE_CLEANUP;
+                             &cleanup);
+        if (found)
+        {
+            r_icache_miss_way = way;
+            r_icache_miss_set = set;
+
+            if (cleanup)
+            {
+                if (not r_icache_cc_send_req.read())
+                {
+                    r_icache_cc_send_req   = true;
+                    r_icache_cc_send_nline = victim;
+                    r_icache_cc_send_way   = way;
+                    r_icache_cc_send_type  = CC_TYPE_CLEANUP;
                 }
                 else
@@ -1669 +1652 @@
                 }
 
-                r_icache_miss_clack           = true;
-                r_icache_fsm                  = ICACHE_MISS_CLEAN;
+                r_icache_miss_clack = true;
+                r_icache_fsm        = ICACHE_MISS_CLEAN;
             }
             else
             {
-                r_icache_fsm          = ICACHE_MISS_WAIT;
+                r_icache_fsm = ICACHE_MISS_WAIT;
             }
 
 #if DEBUG_ICACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " ICACHE_MISS_SELECT> Select a slot:" << std::dec
-              << " / WAY = " << way
-              << " / SET = " << set;
-    if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
-    else         std::cout << std::endl;
-}
+            if (m_debug_activated)
+            {
+                std::cout << "  <PROC " << name()
+                    << " ICACHE_MISS_SELECT> Select a slot:" << std::dec
+                    << " / WAY = " << way
+                    << " / SET = " << set;
+                if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl;
+                else         std::cout << std::endl;
+            }
 #endif
         }
@@ -1692 +1675 @@
     }
     ///////////////////////
-    case ICACHE_MISS_CLEAN:          // switch the slot to zombi state
+    case ICACHE_MISS_CLEAN:   // switch the slot to zombi state
     {
         if (m_ireq.valid) m_cost_ins_miss_frz++;
 
 #ifdef INSTRUMENTATION
-m_cpt_icache_dir_write++;
-#endif
-        r_icache.write_dir( r_icache_miss_way.read(),
-                            r_icache_miss_set.read(),
-                            CACHE_SLOT_STATE_ZOMBI);
+        m_cpt_icache_dir_write++;
+#endif
+        r_icache.write_dir(r_icache_miss_way.read(),
+                           r_icache_miss_set.read(),
+                           CACHE_SLOT_STATE_ZOMBI);
 #if DEBUG_ICACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " ICACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
-              << " / WAY = " << r_icache_miss_way.read()
-              << " / SET = " << r_icache_miss_set.read() << std::endl;
-}
+        if (m_debug_activated)
+        {
+            std::cout << "  <PROC " << name()
+                << " ICACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
+                << " / WAY = " << r_icache_miss_way.read()
+                << " / SET = " << r_icache_miss_set.read() << std::endl;
+        }
 #endif
 
@@ -1716 +1699 @@
     }
     //////////////////////
-    case ICACHE_MISS_WAIT:    // waiting response from VCI_RSP FSM
+    case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM
     {
         if (m_ireq.valid) m_cost_ins_miss_frz++;
 
-        if ( r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read() )
+        // send cleanup victim request
+        if (r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read())
         {
             r_icache_cc_send_req        = true;
@@ -1730 +1714 @@
 
         // coherence clack interrupt
-        if ( r_icache_clack_req.read() )
+        if (r_icache_clack_req.read())
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1738 +1722 @@
 
         // coherence interrupt
-        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read() )
+        if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read())
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1745 +1729 @@
         }
 
-        if ( r_vci_rsp_ins_error.read() ) // bus error
+        if (r_vci_rsp_ins_error.read()) // bus error
         {
             r_mmu_ietr          = MMU_READ_DATA_ILLEGAL_ACCESS;
@@ -1754 +1738 @@
             r_icache_fsm        = ICACHE_IDLE;
         }
-        else if ( r_vci_rsp_fifo_icache.rok() ) // response available
+        else if (r_vci_rsp_fifo_icache.rok()) // response available
         {
             r_icache_miss_word = 0;
@@ -1762 +1746 @@
     }
     ///////////////////////////
-    case ICACHE_MISS_DATA_UPDT:   // update the cache (one word per cycle)
-    {
-        if ( m_ireq.valid ) m_cost_ins_miss_frz++;
-
-        if ( r_vci_rsp_fifo_icache.rok() )  // response available
+    case ICACHE_MISS_DATA_UPDT:  // update the cache (one word per cycle)
+    {
+        if (m_ireq.valid) m_cost_ins_miss_frz++;
+
+        if (r_vci_rsp_fifo_icache.rok()) // response available
         {
 
 #ifdef INSTRUMENTATION
-m_cpt_icache_data_write++;
-#endif
-            r_icache.write( r_icache_miss_way.read(),
-                            r_icache_miss_set.read(),
-                            r_icache_miss_word.read(),
-                            r_vci_rsp_fifo_icache.read() );
+            m_cpt_icache_data_write++;
+#endif
+            r_icache.write(r_icache_miss_way.read(),
+                           r_icache_miss_set.read(),
+                           r_icache_miss_word.read(),
+                           r_vci_rsp_fifo_icache.read());
 #if DEBUG_ICACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " ICACHE_MISS_DATA_UPDT> Write one word:"
-              << " WDATA = " << std::hex << r_vci_rsp_fifo_icache.read()
-              << " WAY = " << r_icache_miss_way.read()
-              << " SET = " << r_icache_miss_set.read()
-              << " WORD = " << r_icache_miss_word.read() << std::endl;
-}
+            if (m_debug_activated)
+            {
+                std::cout << "  <PROC " << name()
+                    << " ICACHE_MISS_DATA_UPDT> Write one word:"
+                    << " WDATA = " << std::hex << r_vci_rsp_fifo_icache.read()
+                    << " WAY = " << r_icache_miss_way.read()
+                    << " SET = " << r_icache_miss_set.read()
+                    << " WORD = " << r_icache_miss_word.read() << std::endl;
+            }
 #endif
             vci_rsp_fifo_icache_get = true;
             r_icache_miss_word = r_icache_miss_word.read() + 1;
 
-            if ( r_icache_miss_word.read() == m_icache_words-1 )   // last word
+            if (r_icache_miss_word.read() == m_icache_words - 1) // last word
             {
                 r_icache_fsm = ICACHE_MISS_DIR_UPDT;
@@ -1806 +1790 @@
                                 //   to ZOMBI state, and send a cleanup request.
     {
-        if ( m_ireq.valid ) m_cost_ins_miss_frz++;
+        if (m_ireq.valid) m_cost_ins_miss_frz++;
 
         // send cleanup victim request
-        if ( r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read() )
+        if (r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read())
         {
             r_icache_cc_send_req        = true;
@@ -1819 +1803 @@
 
         // coherence clack interrupt
-        if ( r_icache_clack_req.read() )
+        if (r_icache_clack_req.read())
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1827 +1811 @@
 
         // coherence interrupt
-        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read() )
+        if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read())
         {
             r_icache_fsm = ICACHE_CC_CHECK;
@@ -1834 +1818 @@
         }
 
-        if ( not r_icache_miss_clack.read() ) // waiting cleanup acknowledge for victim line
-        {
-            if ( r_icache_miss_inval )    // Switch slot to ZOMBI state, and new cleanup
-            {
-                if ( not r_icache_cc_send_req.read() )
+        if (not r_icache_miss_clack.read()) // waiting cleanup acknowledge for victim line
+        {
+            if (r_icache_miss_inval) // Switch slot to ZOMBI state, and new cleanup
+            {
+                if (not r_icache_cc_send_req.read())
                 {
                     r_icache_miss_inval    = false;
                     // request cleanup
                     r_icache_cc_send_req   = true;
-                    r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2);
+                    r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words << 2);
                     r_icache_cc_send_way   = r_icache_miss_way.read();
                     r_icache_cc_send_type  = CC_TYPE_CLEANUP;
 
 #ifdef INSTRUMENTATION
-m_cpt_icache_dir_write++;
-#endif
-                    r_icache.write_dir( r_icache_vci_paddr.read(),
-                                        r_icache_miss_way.read(),
-                                        r_icache_miss_set.read(),
-                                        CACHE_SLOT_STATE_ZOMBI );
+                    m_cpt_icache_dir_write++;
+#endif
+                    r_icache.write_dir(r_icache_vci_paddr.read(),
+                                       r_icache_miss_way.read(),
+                                       r_icache_miss_set.read(),
+                                       CACHE_SLOT_STATE_ZOMBI);
 #if DEBUG_ICACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " ICACHE_MISS_DIR_UPDT> Switch cache slot to ZOMBI state"
-              << " PADDR = " << std::hex << r_icache_vci_paddr.read()
-              << " WAY = " << std::dec << r_icache_miss_way.read()
-              << " SET = " << r_icache_miss_set.read() << std::endl;
-}
+                    if (m_debug_activated)
+                    {
+                        std::cout << "  <PROC " << name()
+                            << " ICACHE_MISS_DIR_UPDT> Switch cache slot to ZOMBI state"
+                            << " PADDR = " << std::hex << r_icache_vci_paddr.read()
+                            << " WAY = " << std::dec << r_icache_miss_way.read()
+                            << " SET = " << r_icache_miss_set.read() << std::endl;
+                    }
 #endif
                 }
@@ -1868 +1852 @@
                     break;
             }
-            else                          // Switch slot to VALID state
+            else // Switch slot to VALID state
             {
 
 #ifdef INSTRUMENTATION
-m_cpt_icache_dir_write++;
-#endif
-                r_icache.write_dir( r_icache_vci_paddr.read(),
-                                    r_icache_miss_way.read(),
-                                    r_icache_miss_set.read(),
-                                    CACHE_SLOT_STATE_VALID_CC );
+                m_cpt_icache_dir_write++;
+#endif
+                r_icache.write_dir(r_icache_vci_paddr.read(),
+                                   r_icache_miss_way.read(),
+                                   r_icache_miss_set.read(),
+                                   CACHE_SLOT_STATE_VALID_CC);
 #if DEBUG_ICACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state"
-              << " PADDR = " << std::hex << r_icache_vci_paddr.read()
-              << " WAY = " << std::dec << r_icache_miss_way.read()
-              << " SET = " << r_icache_miss_set.read() << std::endl;
-}
+                if (m_debug_activated)
+                {
+                    std::cout << "  <PROC " << name()
+                        << " ICACHE_MISS_DIR_UPDT> Switch cache slot to VALID state"
+                        << " PADDR = " << std::hex << r_icache_vci_paddr.read()
+                        << " WAY = " << std::dec << r_icache_miss_way.read()
+                        << " SET = " << r_icache_miss_set.read() << std::endl;
+                }
 #endif
             }
@@ -1895 +1879 @@
     }
     ////////////////////
-    case ICACHE_UNC_WAIT:  // waiting a response to an uncacheable read from VCI_RSP FSM
+    case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM
     {
         // coherence clack interrupt
-        if ( r_icache_clack_req.read() )
-        {
-            r_icache_fsm = ICACHE_CC_CHECK;
+        if (r_icache_clack_req.read())
+        {
+            r_icache_fsm      = ICACHE_CC_CHECK;
             r_icache_fsm_save = r_icache_fsm.read();
             break;
@@ -1906 +1890 @@
 
         // coherence interrupt
-        if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
-        {
-            r_icache_fsm = ICACHE_CC_CHECK;
+        if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read())
+        {
+            r_icache_fsm      = ICACHE_CC_CHECK;
             r_icache_fsm_save = r_icache_fsm.read();
             break;
         }
 
-        if ( r_vci_rsp_ins_error.read() ) // bus error
+        if (r_vci_rsp_ins_error.read()) // bus error
         {
             r_mmu_ietr          = MMU_READ_DATA_ILLEGAL_ACCESS;
@@ -1922 +1906 @@
             r_icache_fsm        = ICACHE_IDLE;
         }
-        else if (r_vci_rsp_fifo_icache.rok() ) // instruction available
+        else if (r_vci_rsp_fifo_icache.rok()) // instruction available
         {
             vci_rsp_fifo_icache_get = true;
             r_icache_fsm            = ICACHE_IDLE;
-            if ( m_ireq.valid and
-                (m_ireq.addr == r_icache_vaddr_save.read()) ) // request unmodified
+            if (m_ireq.valid and
+                (m_ireq.addr == r_icache_vaddr_save.read())) // request unmodified
             {
                 m_irsp.valid       = true;
@@ -1936 +1920 @@
     }
     /////////////////////
-    case ICACHE_CC_CHECK:       // This state is the entry point of a sub-fsm
-                                // handling coherence requests.
-                                // if there is a matching pending miss, it is
-                                // signaled in the r_icache_miss_inval flip-flop.
-                                // The return state is defined in r_icache_fsm_save.
-    {
-        paddr_t  paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4;
-        paddr_t  mask  = ~((m_icache_words<<2)-1);
+    case ICACHE_CC_CHECK:   // This state is the entry point of a sub-fsm
+                            // handling coherence requests.
+                            // if there is a matching pending miss, it is
+                            // signaled in the r_icache_miss_inval flip-flop.
+                            // The return state is defined in r_icache_fsm_save.
+    {
+        paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4;
+        paddr_t mask  = ~((m_icache_words << 2) - 1);
 
         // CLACK handler
@@ -1949 +1933 @@
         // and reset r_icache_miss_clack if the cleanup ack
         // is matching a pending miss.
-        if ( r_icache_clack_req.read() )
-        {
-
-            if ( m_ireq.valid ) m_cost_ins_miss_frz++;
+        if (r_icache_clack_req.read())
+        {
+
+            if (m_ireq.valid) m_cost_ins_miss_frz++;
 
 #ifdef INSTRUMENTATION
-m_cpt_icache_dir_write++;
-#endif
-            r_icache.write_dir( 0,
-                                r_icache_clack_way.read(),
-                                r_icache_clack_set.read(),
-                                CACHE_SLOT_STATE_EMPTY);
-
-            if ( (r_icache_miss_set.read() == r_icache_clack_set.read()) and
-                 (r_icache_miss_way.read() == r_icache_clack_way.read()) )
+            m_cpt_icache_dir_write++;
+#endif
+            r_icache.write_dir(0,
+                               r_icache_clack_way.read(),
+                               r_icache_clack_set.read(),
+                               CACHE_SLOT_STATE_EMPTY);
+
+            if ((r_icache_miss_set.read() == r_icache_clack_set.read()) and
+                 (r_icache_miss_way.read() == r_icache_clack_way.read()))
             {
                 r_icache_miss_clack = false;
@@ -1974 +1958 @@
 
 #if DEBUG_ICACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-        << " ICACHE_CC_CHECK>  CC_TYPE_CLACK slot returns to empty state"
-        << " set = " << r_icache_clack_set.read()
-        << " / way = " << r_icache_clack_way.read() << std::endl;
-}
+            if (m_debug_activated)
+            {
+                std::cout << "  <PROC " << name()
+                    << " ICACHE_CC_CHECK>  CC_TYPE_CLACK slot returns to empty state"
+                    << " set = " << r_icache_clack_set.read()
+                    << " / way = " << r_icache_clack_way.read() << std::endl;
+            }
 #endif
 
@@ -1990 +1974 @@
         // because the CLACK access the directory but the MISS match dont.
         if (r_cc_receive_icache_req.read() and
-          ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT  )  or
-           (r_icache_fsm_save.read() == ICACHE_MISS_WAIT    )  or
+          ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT)  or
+           (r_icache_fsm_save.read() == ICACHE_MISS_WAIT)  or
            (r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and
-          ((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching
+          ((r_icache_vci_paddr.read() & mask) == (paddr & mask))) // matching
         {
             // signaling the matching
-            r_icache_miss_inval     = true;
+            r_icache_miss_inval = true;
 
             // in case of update, go to CC_UPDT
@@ -2002 +1986 @@
             if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
             {
-                r_icache_fsm        = ICACHE_CC_UPDT;
-                r_icache_cc_word    = r_cc_receive_word_idx.read();
+                r_icache_fsm = ICACHE_CC_UPDT;
+                r_icache_cc_word = r_cc_receive_word_idx.read();
 
                 // just pop the fifo , don't write in icache
@@ -2012 +1996 @@
             {
                 r_cc_receive_icache_req = false;
-                r_icache_fsm          = r_icache_fsm_save.read();
+                r_icache_fsm = r_icache_fsm_save.read();
             }
 #if DEBUG_ICACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " ICACHE_CC_CHECK> Coherence request matching a pending miss:"
-              << " PADDR = " << std::hex << paddr << std::endl;
-}
-#endif
-        }
-
-        assert ( not r_icache_cc_send_req.read() and "CC_SEND must be available in ICACHE_CC_CHECK");
+            if (m_debug_activated)
+            {
+                std::cout << "  <PROC " << name()
+                    << " ICACHE_CC_CHECK> Coherence request matching a pending miss:"
+                    << " PADDR = " << std::hex << paddr << std::endl;
+            }
+#endif
+        }
+
+        assert(not r_icache_cc_send_req.read() and "CC_SEND must be available in ICACHE_CC_CHECK");
 
         // CC request handler
 
-        int         state = 0;
-        size_t      way = 0;
-        size_t      set = 0;
-        size_t      word = 0;
+        int    state = 0;
+        size_t way = 0;
+        size_t set = 0;
+        size_t word = 0;
 
 #ifdef INSTRUMENTATION
-m_cpt_icache_dir_read++;
+        m_cpt_icache_dir_read++;
 #endif
         r_icache.read_dir(paddr,
@@ -2045 +2029 @@
         r_icache_cc_set = set;
 
-        if ( state == CACHE_SLOT_STATE_VALID_CC)            // hit
+        if (state == CACHE_SLOT_STATE_VALID_CC)            // hit
         {
             // need to update the cache state
@@ -2051 +2035 @@
             {
                 r_icache_cc_need_write = true;
-                r_icache_fsm           = ICACHE_CC_UPDT;
-                r_icache_cc_word       = r_cc_receive_word_idx.read();
-            }
-            else if ( r_cc_receive_icache_type.read() == CC_TYPE_INVAL ) // hit inval
-            {
-                r_icache_fsm           = ICACHE_CC_INVAL;
+                r_icache_fsm = ICACHE_CC_UPDT;
+                r_icache_cc_word = r_cc_receive_word_idx.read();
+            }
+            else if (r_cc_receive_icache_type.read() == CC_TYPE_INVAL) // hit inval
+            {
+                r_icache_fsm = ICACHE_CC_INVAL;
             }
         }
@@ -2062 +2046 @@
         {
             // multicast acknowledgement required in case of update
-            if(r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
-            {
-                r_icache_fsm           = ICACHE_CC_UPDT;
-                r_icache_cc_word       = r_cc_receive_word_idx.read();
+            if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT)
+            {
+                r_icache_fsm = ICACHE_CC_UPDT;
+                r_icache_cc_word = r_cc_receive_word_idx.read();
 
                 // just pop the fifo , don't write in icache
@@ -2073 +2057 @@
             {
                 r_cc_receive_icache_req = false;
-                r_icache_fsm            = r_icache_fsm_save.read();
+                r_icache_fsm = r_icache_fsm_save.read();
             }
         }
 #if DEBUG_ICACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " ICACHE_CC_CHECK> Coherence request received:"
-              << " PADDR = " << std::hex << paddr
-              << " / TYPE = " << std::dec << r_cc_receive_dcache_type.read()
-              << " / HIT = " << ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC)) << std::endl;
-}
-#endif
-
+        if (m_debug_activated)
+        {
+            std::cout << "  <PROC " << name()
+                << " ICACHE_CC_CHECK> Coherence request received:"
+                << " PADDR = " << std::hex << paddr
+                << " / TYPE = " << std::dec << r_cc_receive_dcache_type.read()
+                << " / HIT = " << ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC)) << std::endl;
+        }
+#endif
         break;
     }
     /////////////////////
-    case ICACHE_CC_INVAL:   // hit inval : switch slot to ZOMBI state
-    {
-        assert (not r_icache_cc_send_req.read() &&
-                "ERROR in ICACHE_CC_INVAL: the r_icache_cc_send_req "
-                "must not be set");
+    case ICACHE_CC_INVAL:  // hit inval : switch slot to ZOMBI state
+    {
+        assert(not r_icache_cc_send_req.read() and
+               "ERROR in ICACHE_CC_INVAL: the r_icache_cc_send_req "
+               "must not be set");
 
 #ifdef INSTRUMENTATION
-m_cpt_icache_dir_read++;
+        m_cpt_icache_dir_read++;
 #endif
 
         // Switch slot state to ZOMBI and send CLEANUP command
-        r_icache.write_dir( r_icache_cc_way.read(),
-                            r_icache_cc_set.read(),
-                            CACHE_SLOT_STATE_ZOMBI );
+        r_icache.write_dir(r_icache_cc_way.read(),
+                           r_icache_cc_set.read(),
+                           CACHE_SLOT_STATE_ZOMBI);
 
         // coherence request completed
@@ -2111 +2094 @@
         r_icache_cc_send_type  = CC_TYPE_CLEANUP;
 
-        r_icache_fsm           = r_icache_fsm_save.read();
+        r_icache_fsm = r_icache_fsm_save.read();
 
 #if DEBUG_ICACHE
-if ( m_debug_activated )
-{
-std::cout << "  <PROC " << name()
-          << " ICACHE_CC_INVAL> slot returns to ZOMBI state"
-          << " set = " << r_icache_cc_set.read()
-          << " / way = " << r_icache_cc_way.read() << std::endl;
-}
+        if (m_debug_activated)
+        {
+            std::cout << "  <PROC " << name()
+                << " ICACHE_CC_INVAL> slot returns to ZOMBI state"
+                << " set = " << r_icache_cc_set.read()
+                << " / way = " << r_icache_cc_way.read() << std::endl;
+        }
 #endif
 
@@ -2126 +2109 @@
     }
     ////////////////////
-    case ICACHE_CC_UPDT:    // hit update : write one word per cycle
-    {
-        assert (not r_icache_cc_send_req.read() &&
-                "ERROR in ICACHE_CC_UPDT: the r_icache_cc_send_req "
-                "must not be set");
-
-        if ( not r_cc_receive_updt_fifo_be.rok() ) break;
-
-
-        size_t  word  = r_icache_cc_word.read();
-        size_t  way   = r_icache_cc_way.read();
-        size_t  set   = r_icache_cc_set.read();
+    case ICACHE_CC_UPDT: // hit update : write one word per cycle
+    {
+        assert(not r_icache_cc_send_req.read() and
+               "ERROR in ICACHE_CC_UPDT: the r_icache_cc_send_req "
+               "must not be set");
+
+        if (not r_cc_receive_updt_fifo_be.rok()) break;
+
+
+        size_t word = r_icache_cc_word.read();
+        size_t way  = r_icache_cc_way.read();
+        size_t set  = r_icache_cc_set.read();
 
         if (r_icache_cc_need_write.read())
         {
-            r_icache.write( way,
-                            set,
-                            word,
-                            r_cc_receive_updt_fifo_data.read(),
-                            r_cc_receive_updt_fifo_be.read() );
-
-            r_icache_cc_word = word+1;
+            r_icache.write(way,
+                           set,
+                           word,
+                           r_cc_receive_updt_fifo_data.read(),
+                           r_cc_receive_updt_fifo_be.read());
+
+            r_icache_cc_word = word + 1;
 
 #ifdef INSTRUMENTATION
-m_cpt_icache_data_write++;
+            m_cpt_icache_data_write++;
 #endif
 
 #if DEBUG_ICACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " ICACHE_CC_UPDT> Write one word "
-              << " set = " << r_icache_cc_set.read()
-              << " / way = " << r_icache_cc_way.read()
-              << " / word = " << r_icache_cc_word.read() << std::endl;
-}
-#endif
-        }
-
-        if ( r_cc_receive_updt_fifo_eop.read() )   // last word
+            if (m_debug_activated)
+            {
+                std::cout << "  <PROC " << name()
+                    << " ICACHE_CC_UPDT> Write one word "
+                    << " set = " << r_icache_cc_set.read()
+                    << " / way = " << r_icache_cc_way.read()
+                    << " / word = " << r_icache_cc_word.read() << std::endl;
+            }
+#endif
+        }
+
+        if (r_cc_receive_updt_fifo_eop.read()) // last word
         {
             // no need to write in the cache anymore
-            r_icache_cc_need_write        = false;
+            r_icache_cc_need_write = false;
 
             // coherence request completed
-            r_cc_receive_icache_req       = false;
+            r_cc_receive_icache_req = false;
 
             // request multicast acknowledgement
@@ -2179 +2162 @@
             r_icache_cc_send_type         = CC_TYPE_MULTI_ACK;
 
-            r_icache_fsm                  = r_icache_fsm_save.read();
+            r_icache_fsm = r_icache_fsm_save.read();
         }
         //consume fifo if not eop
-        cc_receive_updt_fifo_get  = true;
+        cc_receive_updt_fifo_get = true;
 
         break;
@@ -2243 +2226 @@
     //    This component implement a strong order between non cacheable access
     //    (read or write) : A new non cacheable VCI transaction starts only when
-    //    the previous non cacheable transaction is completed. Both cacheable and
-    //    non cacheable transactions use the write buffer, but the DCACHE FSM registers
-    //    a non cacheable write transaction posted in the write buffer by setting the
-    //    r_dcache_pending_unc_write flip_flop. All other non cacheable requests
-    //    are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the
-    //    pending non cacheable write transaction completes).
+    //    the previous non cacheable transaction is completed. After send the VCI
+    //    transaction, the DCACHE FSM wait for the respone in the DCACHE_UNC_WAIT state.
+    //    So the processor is blocked until the respone arrives in CACHE L1.
     //
     // 6/ Error handling:
     //    When the MMU is not activated, Read Bus Errors are synchronous events,
-    //    but Write Bus Errors are asynchronous events (processor is not frozen).
-    //    - If a Read Bus Error is detected, the VCI_RSP FSM sets the
+    //    Some Write Bus Errors are synchronous events when the request is a non cacheable access
+    //    but some Write Bus Errors are asynchronous events when the request is cacheable access
+    //    (processor is not frozen).
+    //    - If a Read Bus Error or a Non Cacheable Write Bus Error is detected, the VCI_RSP FSM sets the
     //      r_vci_rsp_data_error flip-flop, without writing any data in the
     //      r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled
     //      by the DCACHE FSM.
-    //    - If a Write Bus Error is detected, the VCI_RSP FSM  signals
-    //      the asynchronous error using the setWriteBerr() method.
+    //    - If a Cacheable Write Bus Error is detected, the VCI_RSP_FSM signals
+    //    the asynchronous error using the setWriteBerr() method.
     //    When the MMU is activated bus error are rare events, as the MMU
     //    checks the physical address before the VCI transaction starts.
@@ -2268 +2250 @@
     m_drsp.rdata = 0;
 
-    switch ( r_dcache_fsm.read() )
+    switch (r_dcache_fsm.read())
     {
     case DCACHE_IDLE: // There are 10 conditions to exit the IDLE state :
@@ -2278 +2260 @@
                       // 6) Dirty bit update (processor)      => DCACHE_DIRTY_GET_PTE
                       // 7) Cacheable read miss (processor)   => DCACHE_MISS_SELECT
-                      // 8) Uncacheable read (processor)      => DCACHE_UNC_WAIT
+                      // 8) Uncacheable read/write (processor)=> DCACHE_UNC_WAIT
                       // 9) LL access (processor)             => DCACHE_LL_WAIT
                       // 10) SC access (processor)            => DCACHE_SC_WAIT
@@ -2305 +2287 @@
                       // updt_request, wbuf_request, wbuf_write_miss.
     {
-        paddr_t     paddr;                          // physical address
-        pte_info_t  tlb_flags;
-        size_t      tlb_way;
-        size_t      tlb_set;
-        paddr_t     tlb_nline = 0;
-        size_t      cache_way;
-        size_t      cache_set;
-        size_t      cache_word;
-        uint32_t    cache_rdata = 0;
-        bool        tlb_hit = false;
-        int         cache_state = CACHE_SLOT_STATE_EMPTY;
-
-        bool        tlb_inval_required = false;     // request TLB inval after cache update
-        bool        wbuf_write_miss    = false;     // miss a WBUF write request
-        bool        updt_request       = false;     // request DCACHE update in P1 stage
-        bool        wbuf_request       = false;     // request WBUF write in P1 stage
-
-        // physical address computation : systematic DTLB access (if activated)
+        paddr_t paddr;
+        pte_info_t tlb_flags;
+        size_t   tlb_way;
+        size_t   tlb_set;
+        paddr_t  tlb_nline = 0;
+        size_t   cache_way;
+        size_t   cache_set;
+        size_t   cache_word;
+        uint32_t cache_rdata = 0;
+        bool     tlb_hit = false;
+        int      cache_state = CACHE_SLOT_STATE_EMPTY;
+
+        bool tlb_inval_required = false; // request TLB inval after cache update
+        bool wbuf_write_miss = false;    // miss a WBUF write request
+        bool updt_request = false;       // request DCACHE update in P1 stage
+        bool wbuf_request = false;       // request WBUF write in P1 stage
+
+        // physical address computation : systematic DTLB access if activated
         paddr = (paddr_t) m_dreq.addr;
-        if ( m_dreq.valid )
-        {
-            if ( r_mmu_mode.read() & DATA_TLB_MASK )  // DTLB activated
-            {
-                tlb_hit = r_dtlb.translate( m_dreq.addr,
-                                            &paddr,
-                                            &tlb_flags,
-                                            &tlb_nline,
-                                            &tlb_way,
-                                            &tlb_set );
+        if (m_dreq.valid)
+        {
+            if (r_mmu_mode.read() & DATA_TLB_MASK)  // DTLB activated
+            {
+                tlb_hit = r_dtlb.translate(m_dreq.addr,
+                                           &paddr,
+                                           &tlb_flags,
+                                           &tlb_nline,
+                                           &tlb_way,
+                                           &tlb_set);
 #ifdef INSTRUMENTATION
-m_cpt_data_tlb_read++;
-#endif
-            }
-            else                                    // identity mapping
+                m_cpt_dtlb_read++;
+#endif
+            }
+            else // identity mapping
             {
                 // we take into account the paddr extension
                 if (vci_param::N > 32)
-                    paddr = paddr | ((paddr_t)(r_dcache_paddr_ext.read()) << 32);
+                    paddr = paddr | ((paddr_t) (r_dcache_paddr_ext.read()) << 32);
             }
         } // end physical address computation
 
         // systematic DCACHE access depending on r_dcache_updt_req (if activated)
-        if ( r_mmu_mode.read() & DATA_CACHE_MASK)
-        {
-
-            if ( m_dreq.valid and r_dcache_updt_req.read() ) // read DIR and write DATA
-            {
-                r_dcache.read_dir( paddr,
-                                   &cache_state,
-                                   &cache_way,
-                                   &cache_set,
-                                   &cache_word );
-
-                r_dcache.write( r_dcache_save_cache_way.read(),
-                                r_dcache_save_cache_set.read(),
-                                r_dcache_save_cache_word.read(),
-                                r_dcache_save_wdata.read(),
-                                r_dcache_save_be.read() );
+        if (r_mmu_mode.read() & DATA_CACHE_MASK)
+        {
+
+            if (m_dreq.valid and r_dcache_updt_req.read()) // read DIR and write DATA
+            {
+                r_dcache.read_dir(paddr,
+                                  &cache_state,
+                                  &cache_way,
+                                  &cache_set,
+                                  &cache_word);
+
+                r_dcache.write(r_dcache_save_cache_way.read(),
+                               r_dcache_save_cache_set.read(),
+                               r_dcache_save_cache_word.read(),
+                               r_dcache_save_wdata.read(),
+                               r_dcache_save_be.read());
 #ifdef INSTRUMENTATION
-m_cpt_dcache_dir_read++;
-m_cpt_dcache_data_write++;
-#endif
-            }
-            else if ( m_dreq.valid and not r_dcache_updt_req.read() ) // read DIR and DATA
-            {
-                r_dcache.read( paddr,
-                               &cache_rdata,
-                               &cache_way,
-                               &cache_set,
-                               &cache_word,
-                               &cache_state );
+                m_cpt_dcache_dir_read++;
+                m_cpt_dcache_data_write++;
+#endif
+            }
+            else if (m_dreq.valid and not r_dcache_updt_req.read()) // read DIR and DATA
+            {
+                r_dcache.read(paddr,
+                              &cache_rdata,
+                              &cache_way,
+                              &cache_set,
+                              &cache_word,
+                              &cache_state);
 
 #ifdef INSTRUMENTATION
-m_cpt_dcache_dir_read++;
-m_cpt_dcache_data_read++;
-#endif
-            }
-            else if ( not m_dreq.valid and r_dcache_updt_req.read() ) // write DATA
-            {
-                r_dcache.write( r_dcache_save_cache_way.read(),
-                                r_dcache_save_cache_set.read(),
-                                r_dcache_save_cache_word.read(),
-                                r_dcache_save_wdata.read(),
-                                r_dcache_save_be.read() );
+                m_cpt_dcache_dir_read++;
+                m_cpt_dcache_data_read++;
+#endif
+            }
+            else if (not m_dreq.valid and r_dcache_updt_req.read()) // write DATA
+            {
+                r_dcache.write(r_dcache_save_cache_way.read(),
+                               r_dcache_save_cache_set.read(),
+                               r_dcache_save_cache_word.read(),
+                               r_dcache_save_wdata.read(),
+                               r_dcache_save_be.read());
 #ifdef INSTRUMENTATION
-m_cpt_dcache_data_write++;
+                m_cpt_dcache_data_write++;
 #endif
             }
@@ -2396 +2378 @@
 
         // DCACHE update in P1 stage can require ITLB / DTLB inval or flush
-        if ( r_dcache_updt_req.read() )
+        if (r_dcache_updt_req.read())
         {
             size_t way = r_dcache_save_cache_way.read();
             size_t set = r_dcache_save_cache_set.read();
 
-            if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB )
-            {
-                tlb_inval_required       = true;
-                r_dcache_tlb_inval_set   = 0;
-                r_dcache_tlb_inval_line  = r_dcache_save_paddr.read()>>
-                                           (uint32_log2(m_dcache_words<<2));
-
-                r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
-            }
-            else if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD )
+            if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_IN_TLB)
+            {
+                tlb_inval_required      = true;
+                r_dcache_tlb_inval_set  = 0;
+                r_dcache_tlb_inval_line = r_dcache_save_paddr.read() >>
+                                           (uint32_log2(m_dcache_words << 2));
+                r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_DIRTY;
+            }
+            else if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_CONTAINS_PTD)
             {
                 r_itlb.reset();
                 r_dtlb.reset();
-
-                r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
+                r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_DIRTY;
             }
 
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
-          << " Cache update in P1 stage" << std::dec
-          << " / WAY = " << r_dcache_save_cache_way.read()
-          << " / SET = " << r_dcache_save_cache_set.read()
-          << " / WORD = " << r_dcache_save_cache_word.read() << std::hex
-          << " / WDATA = " << r_dcache_save_wdata.read()
-          << " / BE = " << r_dcache_save_be.read() << std::endl;
+            if (m_debug_activated)
+            {
+                std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
+                    << " Cache update in P1 stage" << std::dec
+                    << " / WAY = " << r_dcache_save_cache_way.read()
+                    << " / SET = " << r_dcache_save_cache_set.read()
+                    << " / WORD = " << r_dcache_save_cache_word.read() << std::hex
+                    << " / WDATA = " << r_dcache_save_wdata.read()
+                    << " / BE = " << r_dcache_save_be.read() << std::endl;
+            }
 #endif
         } // end test TLB inval
@@ -2433 +2415 @@
         // Miss if the write request is non cacheable, and there is a pending
         // non cacheable write, or if the write buffer is full.
-        if ( r_dcache_wbuf_req.read() )
-        {
-            bool wok = r_wbuf.write( r_dcache_save_paddr.read(),
-                                     r_dcache_save_be.read(),
-                                     r_dcache_save_wdata.read(),
-                                     true );
-/*#ifdef INSTRUMENTATION
-m_cpt_wbuf_write++;
-#endif*/
-
-            if ( not wok ) // miss if write buffer full
+        if (r_dcache_wbuf_req.read())
+        {
+            bool wok = r_wbuf.write(r_dcache_save_paddr.read(),
+                                    r_dcache_save_be.read(),
+                                    r_dcache_save_wdata.read(),
+                                    true);
+#ifdef INSTRUMENTATION
+            m_cpt_wbuf_write++;
+#endif
+            if (not wok) // miss if write buffer full
             {
                 wbuf_write_miss = true;
-             }
+            }
         } // end WBUF update
 
@@ -2453 +2434 @@
 
         // itlb/dtlb invalidation self-request
-        if ( tlb_inval_required )
+        if (tlb_inval_required)
         {
             r_dcache_fsm_scan_save = r_dcache_fsm.read();
@@ -2460 +2441 @@
 
         // coherence clack request (from DSPIN CLACK)
-        else if ( r_dcache_clack_req.read() )
+        else if (r_dcache_clack_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -2466 +2447 @@
         }
         // coherence request (from CC_RECEIVE FSM)
-        else if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
+        else if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -2475 +2456 @@
         // we don't take the processor request, and registers
         // are frozen in case of wbuf_write_miss
-        else if ( m_dreq.valid and not wbuf_write_miss )
+        else if (m_dreq.valid and not wbuf_write_miss)
         {
             // register processor request and DCACHE response
@@ -2491 +2472 @@
             if (m_dreq.type == iss_t::XTN_READ)
             {
-                int xtn_opcode = (int)m_dreq.addr/4;
+                int xtn_opcode = (int)m_dreq.addr / 4;
 
                 // checking processor mode:
@@ -2505 +2486 @@
                 else
                 {
-                    switch( xtn_opcode )
+                    switch (xtn_opcode)
                     {
                     case iss_t::XTN_INS_ERROR_TYPE:
@@ -2580 +2561 @@
 
                     default:
-                        r_mmu_detr = MMU_READ_UNDEFINED_XTN;
+                        r_mmu_detr   = MMU_READ_UNDEFINED_XTN;
                         r_mmu_dbvar  = m_dreq.addr;
                         m_drsp.valid = true;
@@ -2598 +2579 @@
             else if (m_dreq.type == iss_t::XTN_WRITE)
             {
-                int xtn_opcode      = (int)m_dreq.addr/4;
+                int xtn_opcode      = (int) m_dreq.addr / 4;
                 r_dcache_xtn_opcode = xtn_opcode;
 
                 // checking processor mode:
-                if ( (m_dreq.mode  == iss_t::MODE_USER) &&
-                     (xtn_opcode != iss_t::XTN_SYNC) &&
-                     (xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
-                     (xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
-                     (xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
-                     (xtn_opcode != iss_t::XTN_ICACHE_FLUSH) )
+                if ((m_dreq.mode == iss_t::MODE_USER) &&
+                    (xtn_opcode != iss_t::XTN_SYNC) &&
+                    (xtn_opcode != iss_t::XTN_DCACHE_INVAL) &&
+                    (xtn_opcode != iss_t::XTN_DCACHE_FLUSH) &&
+                    (xtn_opcode != iss_t::XTN_ICACHE_INVAL) &&
+                    (xtn_opcode != iss_t::XTN_ICACHE_FLUSH))
                 {
                     r_mmu_detr   = MMU_WRITE_PRIVILEGE_VIOLATION;
@@ -2618 +2599 @@
                 else
                 {
-                    switch( xtn_opcode )
+                    switch (xtn_opcode)
                     {
-                    case iss_t::XTN_PTPR:               // itlb & dtlb must be flushed
+                    case iss_t::XTN_PTPR: // itlb & dtlb must be flushed
                         r_dcache_xtn_req = true;
                         r_dcache_fsm     = DCACHE_XTN_SWITCH;
                         break;
 
-                    case iss_t::XTN_TLB_MODE:           // no cache or tlb access
-                        r_mmu_mode       = m_dreq.wdata;
-                        m_drsp.valid     = true;
-                        r_dcache_fsm     = DCACHE_IDLE;
+                    case iss_t::XTN_TLB_MODE: // no cache or tlb access
+                        r_mmu_mode   = m_dreq.wdata;
+                        m_drsp.valid = true;
+                        r_dcache_fsm = DCACHE_IDLE;
                         break;
 
-                    case iss_t::XTN_DTLB_INVAL:             // dtlb access
-                        r_dcache_fsm     = DCACHE_XTN_DT_INVAL;
+                    case iss_t::XTN_DTLB_INVAL: // dtlb access
+                        r_dcache_fsm = DCACHE_XTN_DT_INVAL;
                         break;
 
-                    case iss_t::XTN_ITLB_INVAL:             // itlb access
+                    case iss_t::XTN_ITLB_INVAL: // itlb access
                         r_dcache_xtn_req = true;
                         r_dcache_fsm     = DCACHE_XTN_IT_INVAL;
                         break;
 
-                    case iss_t::XTN_DCACHE_INVAL:           // dcache, dtlb & itlb access
-                        r_dcache_fsm     = DCACHE_XTN_DC_INVAL_VA;
+                    case iss_t::XTN_DCACHE_INVAL:  // dcache, dtlb & itlb access
+                        r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA;
                         break;
 
-                    case iss_t::XTN_MMU_DCACHE_PA_INV:      // dcache, dtlb & itlb access
-                        r_dcache_fsm     = DCACHE_XTN_DC_INVAL_PA;
+                    case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access
+                        r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
                         if (sizeof(paddr_t) <= 32)
                         {
@@ -2659 +2640 @@
                         break;
 
-                    case iss_t::XTN_DCACHE_FLUSH:           // itlb and dtlb must be reset
+                    case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset
                         r_dcache_flush_count = 0;
-                        r_dcache_fsm     = DCACHE_XTN_DC_FLUSH;
+                        r_dcache_fsm         = DCACHE_XTN_DC_FLUSH;
                         break;
 
-                    case iss_t::XTN_ICACHE_INVAL:           // icache and itlb access
+                    case iss_t::XTN_ICACHE_INVAL: // icache and itlb access
                         r_dcache_xtn_req = true;
                         r_dcache_fsm     = DCACHE_XTN_IC_INVAL_VA;
                         break;
 
-                    case iss_t::XTN_MMU_ICACHE_PA_INV:      // icache access
+                    case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access
                         r_dcache_xtn_req = true;
                         r_dcache_fsm     = DCACHE_XTN_IC_INVAL_PA;
                         break;
 
-                    case iss_t::XTN_ICACHE_FLUSH:           // icache access
+                    case iss_t::XTN_ICACHE_FLUSH:   // icache access
                         r_dcache_xtn_req = true;
                         r_dcache_fsm     = DCACHE_XTN_IC_FLUSH;
                         break;
 
-                    case iss_t::XTN_SYNC:                   // wait until write buffer empty
-                        r_dcache_fsm     = DCACHE_XTN_SYNC;
+                    case iss_t::XTN_SYNC:           // wait until write buffer empty
+                        r_dcache_fsm = DCACHE_XTN_SYNC;
                         break;
 
-                    case iss_t::XTN_MMU_WORD_LO:        // no cache or tlb access
-                        r_mmu_word_lo    = m_dreq.wdata;
-                        m_drsp.valid     = true;
-                        r_dcache_fsm     = DCACHE_IDLE;
+                    case iss_t::XTN_MMU_WORD_LO:    // no cache or tlb access
+                        r_mmu_word_lo = m_dreq.wdata;
+                        m_drsp.valid  = true;
+                        r_dcache_fsm  = DCACHE_IDLE;
                         break;
 
-                    case iss_t::XTN_MMU_WORD_HI:        // no cache or tlb access
-                        r_mmu_word_hi    = m_dreq.wdata;
-                        m_drsp.valid     = true;
-                        r_dcache_fsm     = DCACHE_IDLE;
+                    case iss_t::XTN_MMU_WORD_HI:    // no cache or tlb access
+                        r_mmu_word_hi = m_dreq.wdata;
+                        m_drsp.valid  = true;
+                        r_dcache_fsm  = DCACHE_IDLE;
                         break;
 
-                    case iss_t::XTN_MMU_LL_RESET:      // no cache or tlb access
+                    case iss_t::XTN_MMU_LL_RESET:   // no cache or tlb access
                         r_dcache_llsc_valid = false;
-                        m_drsp.valid     = true;
-                        r_dcache_fsm     = DCACHE_IDLE;
+                        m_drsp.valid        = true;
+                        r_dcache_fsm        = DCACHE_IDLE;
                     break;
 
-                    case iss_t::XTN_DATA_PADDR_EXT:     // no cache or tlb access
+                    case iss_t::XTN_DATA_PADDR_EXT:  // no cache or tlb access
                         r_dcache_paddr_ext = m_dreq.wdata;
                         m_drsp.valid       = true;
@@ -2707 +2688 @@
                     break;
 
-                    case iss_t::XTN_INST_PADDR_EXT:     // no cache or tlb access
+                    case iss_t::XTN_INST_PADDR_EXT:  // no cache or tlb access
                         r_dcache_xtn_req = true;
                         r_dcache_fsm     = DCACHE_XTN_IC_PADDR_EXT;
                     break;
 
-                    case iss_t::XTN_ICACHE_PREFETCH:        // not implemented : no action
-                    case iss_t::XTN_DCACHE_PREFETCH:        // not implemented : no action
-                        m_drsp.valid     = true;
-                        r_dcache_fsm     = DCACHE_IDLE;
+                    case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action
+                    case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action
+                        m_drsp.valid = true;
+                        r_dcache_fsm = DCACHE_IDLE;
                     break;
 
@@ -2739 +2720 @@
             else
             {
-                bool        valid_req;
-                bool        cacheable;
-
-                if ( not (r_mmu_mode.read() & DATA_TLB_MASK) )     // dtlb not activated
-                {
-                    valid_req     = true;
-
-                    if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
+                bool valid_req;
+                bool cacheable;
+
+                if (not (r_mmu_mode.read() & DATA_TLB_MASK)) // dtlb not activated
+                {
+                    valid_req = true;
+
+                    if (not (r_mmu_mode.read() & DATA_CACHE_MASK)) cacheable = false;
                     else cacheable = m_cacheability_table[(uint64_t)m_dreq.addr];
                 }
-                else                                               // dtlb activated
-                {
-                    if ( tlb_hit )                  // tlb hit
+                else // dtlb activated
+                {
+                    if (tlb_hit) // tlb hit
                     {
                         // cacheability
-                        if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false;
+                        if (not (r_mmu_mode.read() & DATA_CACHE_MASK)) cacheable = false;
                         else cacheable = tlb_flags.c;
+
                         // access rights checking
-                        if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
+                        if (not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER))
                         {
-                            if ( (m_dreq.type == iss_t::DATA_READ) or
-                                 (m_dreq.type == iss_t::DATA_LL) )
+                            if ((m_dreq.type == iss_t::DATA_READ) or
+                                (m_dreq.type == iss_t::DATA_LL))
                             {
                                 r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION;
@@ -2774 +2756 @@
                             m_drsp.rdata = 0;
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
-          << " HIT in dtlb, but privilege violation" << std::endl;
+                            if (m_debug_activated)
+                            {
+                                std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
+                                    << " HIT in dtlb, but privilege violation" << std::endl;
+                            }
 #endif
                         }
-                        else if ( not tlb_flags.w and
+                        else if (not tlb_flags.w and
                                   ((m_dreq.type == iss_t::DATA_WRITE) or
-                                   (m_dreq.type == iss_t::DATA_SC)) )
+                                   (m_dreq.type == iss_t::DATA_SC)))
                         {
                             r_mmu_detr   = MMU_WRITE_ACCES_VIOLATION;
@@ -2790 +2774 @@
                             m_drsp.rdata = 0;
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
-          << " HIT in dtlb, but writable violation" << std::endl;
+                            if (m_debug_activated)
+                            {
+                                std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
+                                    << " HIT in dtlb, but writable violation" << std::endl;
+                            }
 #endif
                         }
                         else
                         {
-                            valid_req    = true;
+                            valid_req = true;
                         }
                     }
-                    else                     // tlb miss
+                    else // tlb miss
                     {
-                        valid_req            = false;
-                        r_dcache_tlb_vaddr   = m_dreq.addr;
-                        r_dcache_tlb_ins     = false;
-                        r_dcache_fsm         = DCACHE_TLB_MISS;
+                        valid_req          = false;
+                        r_dcache_tlb_vaddr = m_dreq.addr;
+                        r_dcache_tlb_ins   = false;
+                        r_dcache_fsm       = DCACHE_TLB_MISS;
                     }
                 }    // end DTLB activated
 
-                if ( valid_req )    // processor request is valid (after MMU check)
+                if (valid_req) // processor request is valid (after MMU check)
                 {
                     // READ request
@@ -2815 +2801 @@
                     // We request a VCI transaction to CMD FSM if miss or uncachable
 
-                    if ( ((m_dreq.type == iss_t::DATA_READ))
-                          and not r_dcache_updt_req.read() )
+                    if (((m_dreq.type == iss_t::DATA_READ))
+                          and not r_dcache_updt_req.read())
                     {
-                        if ( cacheable )            // cacheable read
+                        if (cacheable) // cacheable read
                         {
-                            if ( cache_state == CACHE_SLOT_STATE_EMPTY )   // cache miss
+                            if (cache_state == CACHE_SLOT_STATE_EMPTY)   // cache miss
                             {
 #ifdef INSTRUMENTATION
-m_cpt_data_miss++;
+                                m_cpt_dcache_miss++;
 #endif
                                 // request a VCI DMISS transaction
@@ -2831 +2817 @@
                                 r_dcache_fsm          = DCACHE_MISS_SELECT;
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
-          << " READ MISS in dcache"
-          << " / PADDR = " << std::hex << paddr << std::endl;
+                                if (m_debug_activated)
+                                {
+                                    std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
+                                        << " READ MISS in dcache"
+                                        << " / PADDR = " << std::hex << paddr << std::endl;
+                                }
 #endif
                             }
-                            else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
+                            else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup
                             {
                                 // stalled until cleanup is acknowledged
                                 r_dcache_fsm   = DCACHE_IDLE;
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
-          << " Pending cleanup, stalled until cleanup acknowledge"
-          << " / PADDR = " << std::hex << paddr << std::endl;
+                                if (m_debug_activated)
+                                {
+                                    std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
+                                        << " Pending cleanup, stalled until cleanup acknowledge"
+                                        << " / PADDR = " << std::hex << paddr << std::endl;
+                                }
 #endif
                             }
@@ -2851 +2841 @@
                             {
 #ifdef INSTRUMENTATION
-m_cpt_data_read++;
+                                m_cpt_data_read++;
 #endif
                                 // returns data to processor
-                                m_drsp.valid   = true;
-                                m_drsp.error   = false;
-                                m_drsp.rdata   = cache_rdata;
+                                m_drsp.valid = true;
+                                m_drsp.error = false;
+                                m_drsp.rdata = cache_rdata;
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
-          << " READ HIT in dcache"
-          << " : PADDR = " << std::hex << paddr
-          << " / DATA  = " << std::hex << cache_rdata << std::dec << std::endl;
+                                if (m_debug_activated)
+                                {
+                                    std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
+                                        << " READ HIT in dcache"
+                                        << " : PADDR = " << std::hex << paddr
+                                        << " / DATA  = " << std::hex << cache_rdata << std::dec << std::endl;
+                                }
 #endif
                             }
                         }
-                        else                    // uncacheable read
+                        else // uncacheable read
                         {
-                            r_dcache_vci_paddr      = paddr;
-                            r_dcache_vci_unc_be     = m_dreq.be;
-                            r_dcache_vci_unc_write  = false;
-                            r_dcache_vci_unc_req    = true;
-                            r_dcache_fsm            = DCACHE_UNC_WAIT;
+                            r_dcache_vci_paddr     = paddr;
+                            r_dcache_vci_unc_be    = m_dreq.be;
+                            r_dcache_vci_unc_write = false;
+                            r_dcache_vci_unc_req   = true;
+                            r_dcache_fsm           = DCACHE_UNC_WAIT;
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
-          << " READ UNCACHEABLE in dcache"
-          << " / PADDR = " << std::hex << paddr << std::endl;
+                            if (m_debug_activated)
+                            {
+                                std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
+                                    << " READ UNCACHEABLE in dcache"
+                                    << " / PADDR = " << std::hex << paddr << std::endl;
+                            }
 #endif
                         }
@@ -2908 +2902 @@
                     // physical address) are registered in r_dcache_save registers,
                     // and the write will be done in the P1 pipeline stage.
-                    else if ( m_dreq.type == iss_t::DATA_WRITE )
+                    else if (m_dreq.type == iss_t::DATA_WRITE)
                     {
-                        if ( (r_mmu_mode.read() & DATA_TLB_MASK )
-                              and not tlb_flags.d )     // Dirty bit must be set
+                        if ((r_mmu_mode.read() & DATA_TLB_MASK)
+                              and not tlb_flags.d) // Dirty bit must be set
                         {
                             // The PTE physical address is obtained from the nline value (dtlb),
                             // and from the virtual address (word index)
-                            if ( tlb_flags.b )  // PTE1
+                            if (tlb_flags.b) // PTE1
                             {
-                                r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) |
-                                                       (paddr_t)((m_dreq.addr>>19) & 0x3c);
+                                r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) |
+                                                       (paddr_t) ((m_dreq.addr >> 19) & 0x3c);
                             }
-                            else        // PTE2
+                            else // PTE2
                             {
-                                r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) |
-                                                       (paddr_t)((m_dreq.addr>>9) & 0x38);
+                                r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) |
+                                                       (paddr_t) ((m_dreq.addr >> 9) & 0x38);
                             }
-                            r_dcache_fsm      = DCACHE_DIRTY_GET_PTE;
+                            r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
                         }
-                        else                    // Write request accepted
+                        else // Write request accepted
                         {
 #ifdef INSTRUMENTATION
-m_cpt_data_write++;
+                            m_cpt_data_write++;
 #endif
                             // cleaning llsc buffer if address matching
-                            if ( paddr == r_dcache_llsc_paddr.read() )
+                            if (paddr == r_dcache_llsc_paddr.read())
                                 r_dcache_llsc_valid = false;
 
-                            if (not cacheable)
+                            if (not cacheable) // uncacheable write
                             {
-                                r_dcache_vci_paddr      = paddr;
-                                r_dcache_vci_wdata      = m_dreq.wdata;
-                                r_dcache_vci_unc_write  = true;
-                                r_dcache_vci_unc_be     = m_dreq.be;
-                                r_dcache_vci_unc_req    = true;
-                                r_dcache_fsm            = DCACHE_UNC_WAIT;
+                                r_dcache_vci_paddr     = paddr;
+                                r_dcache_vci_wdata     = m_dreq.wdata;
+                                r_dcache_vci_unc_write = true;
+                                r_dcache_vci_unc_be    = m_dreq.be;
+                                r_dcache_vci_unc_req   = true;
+                                r_dcache_fsm           = DCACHE_UNC_WAIT;
                             }
                             // activating P1 stage
-                            else if( (cache_state != CACHE_SLOT_STATE_ZOMBI) && (cache_state != CACHE_SLOT_STATE_EMPTY) )
+                            else if ((cache_state != CACHE_SLOT_STATE_ZOMBI) and
+                                     (cache_state != CACHE_SLOT_STATE_EMPTY))
                             {
-                                wbuf_request = (cache_state == CACHE_SLOT_STATE_VALID_CC); //write to L2 only if CC
+                                wbuf_request = (cache_state == CACHE_SLOT_STATE_VALID_CC);
                                 updt_request = true;
                                 m_drsp.valid = true;
-                                if ( cache_state == CACHE_SLOT_STATE_VALID_NCC )
+                                if (cache_state == CACHE_SLOT_STATE_VALID_NCC)
                                 {
-                                    if ( r_dcache_content_state[cache_way*m_dcache_sets+cache_set] == LINE_CACHE_DATA_NOT_DIRTY )
+                                    if (r_dcache_content_state[cache_way * m_dcache_sets + cache_set] == LINE_CACHE_DATA_NOT_DIRTY)
                                     {
-                                        r_dcache_content_state[cache_way*m_dcache_sets+cache_set] = LINE_CACHE_DATA_DIRTY;
+                                        r_dcache_content_state[cache_way * m_dcache_sets + cache_set] = LINE_CACHE_DATA_DIRTY;
                                     }
-                                    //dirty bit with word granularity (only for stats)
-                                    r_dcache_dirty_word[(cache_way*m_dcache_sets +cache_set)*m_dcache_words+cache_word] = 1;
+                                    // dirty bit with word granularity (only for stats)
+                                    r_dcache_dirty_word[(cache_way * m_dcache_sets + cache_set) * m_dcache_words + cache_word] = 1;
                                     m_cpt_data_write_back ++;
                                 }
@@ -2971 +2966 @@
                             // cleanup and therefore overwrite the new value of
                             // writing that is more current than the data
-                            // contained in the cleanup .
+                            // contained in the cleanup.
                             // TODO : MAYBE NEED TO OPTIMIZE
-                            else if ( cache_state == CACHE_SLOT_STATE_ZOMBI )
+                            else if (cache_state == CACHE_SLOT_STATE_ZOMBI)
                             {
                                 m_drsp.valid = false;
                                 r_dcache_fsm = DCACHE_IDLE;
                                 // STAT : WRITE ON ZOMBI NCC LINE
-                                if (r_dcache_zombi_ncc[cache_way*m_dcache_sets+cache_set] == true)
+                                if (r_dcache_zombi_ncc[cache_way * m_dcache_sets + cache_set] == true)
                                 {
                                     m_cpt_data_write_on_zombi_ncc++;
                                 }
-
                                 m_cpt_data_write_on_zombi++;
                             }
@@ -2994 +2988 @@
                         }
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
-          << " WRITE REQ "
-          << " / wbuf_request = " << wbuf_request
-          << " / updt_request = " << updt_request
-          << " / cache_state = " << cache_state
-          << " / PADDR = " << std::hex << paddr << std::endl;
-#endif
-
+                        if (m_debug_activated)
+                        {
+                            std::cout << "  <PROC " << name() << " DCACHE_IDLE>"
+                                << " WRITE REQ "
+                                << " / wbuf_request = " << wbuf_request
+                                << " / updt_request = " << updt_request
+                                << " / cache_state = " << cache_state
+                                << " / PADDR = " << std::hex << paddr << std::dec << std::endl;
+                        }
+#endif
                     } // end WRITE
 
@@ -3015 +3010 @@
                     // We don't check a possible write hit in dcache, as the cache update
                     // is done by the coherence transaction induced by the SC...
-                    else if ( m_dreq.type == iss_t::DATA_SC )
+                    else if (m_dreq.type == iss_t::DATA_SC)
                     {
-                        if ( (r_mmu_mode.read() & DATA_TLB_MASK )
-                              and not tlb_flags.d )         // Dirty bit must be set
+                        if ((r_mmu_mode.read() & DATA_TLB_MASK)
+                              and not tlb_flags.d) // Dirty bit must be set
                         {
                             // The PTE physical address is obtained from the nline value (dtlb),
                             // and the word index (virtual address)
-                            if ( tlb_flags.b )  // PTE1
+                            if (tlb_flags.b) // PTE1
                             {
-                                r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) |
-                                                       (paddr_t)((m_dreq.addr>>19) & 0x3c);
+                                r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) |
+                                                       (paddr_t) ((m_dreq.addr >> 19) & 0x3c);
                             }
-                            else            // PTE2
+                            else // PTE2
                             {
-                                r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) |
-                                                       (paddr_t)((m_dreq.addr>>9) & 0x38);
+                                r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) |
+                                                       (paddr_t) ((m_dreq.addr >> 9) & 0x38);
                             }
-                            r_dcache_fsm           = DCACHE_DIRTY_GET_PTE;
+                            r_dcache_fsm = DCACHE_DIRTY_GET_PTE;
                             m_drsp.valid = false;
                             m_drsp.error = false;
                             m_drsp.rdata = 0;
                         }
-                        else                    // SC request accepted
+                        else // SC request accepted
                         {
 #ifdef INSTRUMENTATION
-m_cpt_data_sc++;
+                            m_cpt_data_sc++;
 #endif
                             // checking local success
-                            if( r_dcache_llsc_valid.read() and
-                                (r_dcache_llsc_paddr.read() == paddr) )  // local success
+                            if (r_dcache_llsc_valid.read() and
+                               (r_dcache_llsc_paddr.read() == paddr)) // local success
                             {
                                 // request an SC CMD and go to DCACHE_SC_WAIT state
@@ -3052 +3047 @@
                                 r_dcache_fsm         = DCACHE_SC_WAIT;
                             }
-                            else                                          // local fail
+                            else // local fail
                             {
                                 m_drsp.valid = true;
@@ -3065 +3060 @@
 
         // itlb miss request
-        else if ( r_icache_tlb_miss_req.read() and not wbuf_write_miss )
+        else if (r_icache_tlb_miss_req.read() and not wbuf_write_miss)
         {
             r_dcache_tlb_ins    = true;
@@ -3091 +3086 @@
                           // r_mmu_ins_* or r_mmu_data* error reporting registers.
     {
-        uint32_t    ptba = 0;
-        bool        bypass;
-        paddr_t     pte_paddr;
+        uint32_t ptba = 0;
+        bool     bypass;
+        paddr_t  pte_paddr;
 
         // evaluate bypass in order to skip first level page table access
-        if ( r_dcache_tlb_ins.read() )  // itlb miss
+        if (r_dcache_tlb_ins.read()) // itlb miss
         {
             bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
         }
-        else                            // dtlb miss
+        else // dtlb miss
         {
             bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba);
         }
 
-        if ( not bypass )     // Try to read PTE1/PTD1 in dcache
-        {
-            pte_paddr = (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2)) |
-                        ((((paddr_t)r_dcache_tlb_vaddr.read()) >> PAGE_M_NBITS) << 2);
+        if (not bypass) // Try to read PTE1/PTD1 in dcache
+        {
+            pte_paddr = (((paddr_t) r_mmu_ptpr.read()) << (INDEX1_NBITS + 2)) |
+                       ((((paddr_t) r_dcache_tlb_vaddr.read()) >> PAGE_M_NBITS) << 2);
             r_dcache_tlb_paddr = pte_paddr;
             r_dcache_fsm       = DCACHE_TLB_PTE1_GET;
         }
-        else                  // Try to read PTE2 in dcache
-        {
-            pte_paddr = (paddr_t)ptba << PAGE_K_NBITS |
-                        (paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3);
+        else // Try to read PTE2 in dcache
+        {
+            pte_paddr = (paddr_t) ptba << PAGE_K_NBITS |
+                        (paddr_t) (r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> (PAGE_K_NBITS - 3);
             r_dcache_tlb_paddr = pte_paddr;
             r_dcache_fsm       = DCACHE_TLB_PTE2_GET;
@@ -3121 +3116 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    if ( r_dcache_tlb_ins.read() )
-        std::cout << "  <PROC " << name() << " DCACHE_TLB_MISS> ITLB miss";
-    else
-        std::cout << "  <PROC " << name() << " DCACHE_TLB_MISS> DTLB miss";
-    std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
-              << " / ptpr  = " << (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2))
-              << " / BYPASS = " << bypass
-              << " / PTE_ADR = " << pte_paddr << std::endl;
-}
+        if (m_debug_activated)
+        {
+            if (r_dcache_tlb_ins.read())
+                std::cout << "  <PROC " << name() << " DCACHE_TLB_MISS> ITLB miss";
+            else
+                std::cout << "  <PROC " << name() << " DCACHE_TLB_MISS> DTLB miss";
+            std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read()
+                << " / ptpr  = " << (((paddr_t) r_mmu_ptpr.read()) << (INDEX1_NBITS + 2))
+                << " / BYPASS = " << bypass
+                << " / PTE_ADR = " << pte_paddr << std::endl;
+        }
 #endif
 
@@ -3137 +3132 @@
     }
     /////////////////////////
-    case DCACHE_TLB_PTE1_GET:   // try to read a PT1 entry in dcache
+    case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache
     {
         // coherence clack request (from DSPIN CLACK)
-        if ( r_dcache_clack_req.read() )
+        if (r_dcache_clack_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3148 +3143 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
+        if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3155 +3150 @@
         }
 
-        uint32_t    entry;
-        size_t      way;
-        size_t      set;
-        size_t      word;
-        int         cache_state;
-        r_dcache.read( r_dcache_tlb_paddr.read(),
-                       &entry,
-                       &way,
-                       &set,
-                       &word,
-                       &cache_state );
-
+        uint32_t entry;
+        size_t way;
+        size_t set;
+        size_t word;
+        int    cache_state;
+        r_dcache.read(r_dcache_tlb_paddr.read(),
+                      &entry,
+                      &way,
+                      &set,
+                      &word,
+                      &cache_state);
 #ifdef INSTRUMENTATION
-m_cpt_dcache_data_read++;
-m_cpt_dcache_dir_read++;
-#endif
-
-        if (( cache_state == CACHE_SLOT_STATE_VALID_NCC ) or ( cache_state == CACHE_SLOT_STATE_VALID_CC ))
-        {
-            if ( not (entry & PTE_V_MASK) ) // unmapped
-            {
-                if ( r_dcache_tlb_ins.read() )
+        m_cpt_dcache_data_read++;
+        m_cpt_dcache_dir_read++;
+#endif
+        if ((cache_state == CACHE_SLOT_STATE_VALID_NCC) or
+            (cache_state == CACHE_SLOT_STATE_VALID_CC))
+        {
+            if (not (entry & PTE_V_MASK)) // unmapped
+            {
+                if (r_dcache_tlb_ins.read())
                 {
                     r_mmu_ietr             = MMU_READ_PT1_UNMAPPED;
@@ -3185 +3179 @@
                 else
                 {
-                    r_mmu_detr             = MMU_READ_PT1_UNMAPPED;
-                    r_mmu_dbvar            = r_dcache_tlb_vaddr.read();
-                    m_drsp.valid             = true;
-                    m_drsp.error             = true;
-                }
-                r_dcache_fsm          = DCACHE_IDLE;
+                    r_mmu_detr   = MMU_READ_PT1_UNMAPPED;
+                    r_mmu_dbvar  = r_dcache_tlb_vaddr.read();
+                    m_drsp.valid = true;
+                    m_drsp.error = true;
+                }
+                r_dcache_fsm = DCACHE_IDLE;
 
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
-              << std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
-              << std::dec << " / way = " << way
-              << std::dec << " / set = " << set
-              << std::dec << " / word = " << word
-              << std::hex << " / PTE1 = " << entry << std::endl;
-}
-#endif
-
-            }
-            else if( entry & PTE_T_MASK )   //  PTD : me must access PT2
+                if (m_debug_activated)
+                {
+                    std::cout << "  <PROC " << name()
+                        << " DCACHE_TLB_PTE1_GET> HIT in dcache, but unmapped"
+                        << std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
+                        << std::dec << " / way = " << way
+                        << std::dec << " / set = " << set
+                        << std::dec << " / word = " << word
+                        << std::hex << " / PTE1 = " << entry << std::endl;
+                }
+#endif
+
+            }
+            else if (entry & PTE_T_MASK) //  PTD : me must access PT2
             {
                 // mark the cache line ac containing a PTD
-                r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_CONTAINS_PTD;
+                r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_CONTAINS_PTD;
 
                 // register bypass
-                if ( r_dcache_tlb_ins.read() )      // itlb
+                if (r_dcache_tlb_ins.read()) // itlb
                 {
                     r_itlb.set_bypass(r_dcache_tlb_vaddr.read(),
-                                      entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
-                                      r_dcache_tlb_paddr.read() / (m_icache_words<<2) );
-                }
-                else                    // dtlb
+                                      entry & ((1 << (m_paddr_nbits - PAGE_K_NBITS)) - 1),
+                                      r_dcache_tlb_paddr.read() / (m_icache_words << 2));
+                }
+                else // dtlb
                 {
                     r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(),
-                                      entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1),
-                                      r_dcache_tlb_paddr.read() / (m_dcache_words<<2) );
+                                      entry & ((1 << (m_paddr_nbits - PAGE_K_NBITS)) - 1),
+                                      r_dcache_tlb_paddr.read() / (m_dcache_words << 2));
                 }
                 r_dcache_tlb_paddr =
-                    (paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS |
-                    (paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
-                r_dcache_fsm       = DCACHE_TLB_PTE2_GET;
+                    (paddr_t) (entry & ((1 << (m_paddr_nbits - PAGE_K_NBITS)) - 1)) << PAGE_K_NBITS |
+                    (paddr_t) (((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3);
+                r_dcache_fsm = DCACHE_TLB_PTE2_GET;
 
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_TLB_PTE1_GET> HIT in dcache"
-              << std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
-              << std::dec << " / way = " << way
-              << std::dec << " / set = " << set
-              << std::dec << " / word = " << word
-              << std::hex << " / PTD = " << entry << std::endl;
-}
-#endif
-            }
-            else            //  PTE1 :  we must update the TLB
-            {
-                r_dcache_content_state[m_icache_sets*way+set] = LINE_CACHE_IN_TLB;
+                if (m_debug_activated)
+                {
+                    std::cout << "  <PROC " << name()
+                        << " DCACHE_TLB_PTE1_GET> HIT in dcache"
+                        << std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
+                        << std::dec << " / way = " << way
+                        << std::dec << " / set = " << set
+                        << std::dec << " / word = " << word
+                        << std::hex << " / PTD = " << entry << std::endl;
+                }
+#endif
+            }
+            else //  PTE1 :  we must update the TLB
+            {
+                r_dcache_content_state[m_dcache_sets * way + set] = LINE_CACHE_IN_TLB;
                 r_dcache_tlb_pte_flags  = entry;
                 r_dcache_fsm            = DCACHE_TLB_PTE1_SELECT;
 
-                r_cas_islocal    = (cache_state == CACHE_SLOT_STATE_VALID_NCC);//do not check L2 if NCC: the CAS is necessarily a success
+                r_cas_islocal    = (cache_state == CACHE_SLOT_STATE_VALID_NCC); // do not check L2 if NCC: the CAS is necessarily a success
                 r_cas_local_way  = way;
                 r_cas_local_set  = set;
@@ -3254 +3248 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_TLB_PTE1_GET> HIT in dcache"
-              << std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
-              << std::dec << " / way = " << way
-              << std::dec << " / set = " << set
-              << std::dec << " / word = " << word
-              << std::hex << " / PTE1 = " << entry << std::endl;
-}
-#endif
-            }
-        }
-        else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
+                if (m_debug_activated)
+                {
+                    std::cout << "  <PROC " << name()
+                        << " DCACHE_TLB_PTE1_GET> HIT in dcache"
+                        << std::hex << " / paddr = " << r_dcache_tlb_paddr.read()
+                        << std::dec << " / way = " << way
+                        << std::dec << " / set = " << set
+                        << std::dec << " / word = " << word
+                        << std::hex << " / PTE1 = " << entry << std::endl;
+                }
+#endif
+            }
+        }
+        else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup
         {
             // stalled until cleanup is acknowledged
-            r_dcache_fsm   = DCACHE_TLB_PTE1_GET;
-        }
-        else        // we must load the missing cache line in dcache
-        {
-            r_dcache_vci_miss_req  = true;
-            r_dcache_vci_paddr     = r_dcache_tlb_paddr.read();
-            r_dcache_save_paddr    = r_dcache_tlb_paddr.read();
-            r_dcache_miss_type     = PTE1_MISS;
-            r_dcache_fsm           = DCACHE_MISS_SELECT;
+            r_dcache_fsm = DCACHE_TLB_PTE1_GET;
+        }
+        else // we must load the missing cache line in dcache
+        {
+            r_dcache_vci_miss_req = true;
+            r_dcache_vci_paddr    = r_dcache_tlb_paddr.read();
+            r_dcache_save_paddr   = r_dcache_tlb_paddr.read();
+            r_dcache_miss_type    = PTE1_MISS;
+            r_dcache_fsm          = DCACHE_MISS_SELECT;
 
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_TLB_PTE1_GET> MISS in dcache:"
-              << " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
-}
+            if (m_debug_activated)
+            {
+                std::cout << "  <PROC " << name()
+                    << " DCACHE_TLB_PTE1_GET> MISS in dcache:"
+                    << " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
+            }
 #endif
         }
@@ -3292 +3286 @@
     }
     ////////////////////////////
-    case DCACHE_TLB_PTE1_SELECT:   // select a slot for PTE1
+    case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1
     {
         size_t way;
         size_t set;
 
-        if ( r_dcache_tlb_ins.read() )
-        {
-            r_itlb.select( r_dcache_tlb_vaddr.read(),
-                           true,  // PTE1
-                           &way,
-                           &set );
+        if (r_dcache_tlb_ins.read())
+        {
+            r_itlb.select(r_dcache_tlb_vaddr.read(),
+                          true,  // PTE1
+                          &way,
+                          &set);
 #ifdef INSTRUMENTATION
-m_cpt_ins_tlb_read++;
+            m_cpt_itlb_read++;
 #endif
         }
         else
         {
-            r_dtlb.select( r_dcache_tlb_vaddr.read(),
-                           true,  // PTE1
-                           &way,
-                           &set );
+            r_dtlb.select(r_dcache_tlb_vaddr.read(),
+                          true,  // PTE1
+                          &way,
+                          &set);
 #ifdef INSTRUMENTATION
-m_cpt_data_tlb_read++;
+            m_cpt_dtlb_read++;
 #endif
         }
@@ -3322 +3316 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    if ( r_dcache_tlb_ins.read() )
-        std::cout << "  <PROC " << name()
-                  << " DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
-    else
-        std::cout << "  <PROC " << name()
-                  << ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
-        std::cout << " way = " << std::dec << way
-                  << " / set = " << set << std::endl;
-}
+        if (m_debug_activated)
+        {
+            if (r_dcache_tlb_ins.read())
+                std::cout << "  <PROC " << name()
+                    << " DCACHE_TLB_PTE1_SELECT> Select a slot in ITLB:";
+            else
+                std::cout << "  <PROC " << name()
+                    << ".DCACHE_TLB_PTE1_SELECT> Select a slot in DTLB:";
+            std::cout << " way = " << std::dec << way
+                << " / set = " << set << std::endl;
+        }
 #endif
         break;
@@ -3343 +3337 @@
                                 //   the coherence mechanism.
     {
-        paddr_t   nline    = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
-        uint32_t  pte      = r_dcache_tlb_pte_flags.read();
-        bool      pt_updt  = false;
-        bool      local    = true;
+        paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);
+        uint32_t pte  = r_dcache_tlb_pte_flags.read();
+        bool pt_updt  = false;
+        bool local    = true;
 
         // We should compute the access locality:
@@ -3355 +3349 @@
         // As long as this computation is not done, all access are local.
 
-        if ( local )                        // local access
-        {
-            if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
+        if (local) // local access
+        {
+            if (not ((pte & PTE_L_MASK) == PTE_L_MASK)) // we must set the L bit
             {
                 pt_updt                = true;
-                r_dcache_vci_cas_old    = pte;
-                r_dcache_vci_cas_new    = pte | PTE_L_MASK;
+                r_dcache_vci_cas_old   = pte;
+                r_dcache_vci_cas_new   = pte | PTE_L_MASK;
                 pte                    = pte | PTE_L_MASK;
                 r_dcache_tlb_pte_flags = pte;
             }
         }
-        else                                // remote access
-        {
-            if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
+        else // remote access
+        {
+            if (not ((pte & PTE_R_MASK) == PTE_R_MASK)) // we must set the R bit
             {
                 pt_updt                = true;
-                r_dcache_vci_cas_old    = pte;
-                r_dcache_vci_cas_new    = pte | PTE_R_MASK;
+                r_dcache_vci_cas_old   = pte;
+                r_dcache_vci_cas_new   = pte | PTE_R_MASK;
                 pte                    = pte | PTE_R_MASK;
                 r_dcache_tlb_pte_flags = pte;
@@ -3378 +3372 @@
         }
 
-        if ( not pt_updt )                  // update TLB and return
-        {
-            if ( r_dcache_tlb_ins.read() )
-            {
-                r_itlb.write( true,     // 2M page
-                              pte,
-                              0,        // argument unused for a PTE1
-                              r_dcache_tlb_vaddr.read(),
-                              r_dcache_tlb_way.read(),
-                              r_dcache_tlb_set.read(),
-                              nline );
+        if (not pt_updt) // update TLB and return
+        {
+            if (r_dcache_tlb_ins.read())
+            {
+                r_itlb.write(true, // 2M page
+                             pte,
+                             0, // argument unused for a PTE1
+                             r_dcache_tlb_vaddr.read(),
+                             r_dcache_tlb_way.read(),
+                             r_dcache_tlb_set.read(),
+                             nline);
 #ifdef INSTRUMENTATION
-m_cpt_ins_tlb_update_acc++;
+                m_cpt_itlb_write++;
 #endif
 
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB"
-              << " / set = " << std::dec << r_dcache_tlb_set.read()
-              << " / way = " << r_dcache_tlb_way.read() << std::endl;
-    r_itlb.printTrace();
-}
+                if (m_debug_activated)
+                {
+                    std::cout << "  <PROC " << name()
+                        << " DCACHE_TLB_PTE1_UPDT> write PTE1 in ITLB"
+                        << " / set = " << std::dec << r_dcache_tlb_set.read()
+                        << " / way = " << r_dcache_tlb_way.read() << std::endl;
+                    r_itlb.printTrace();
+                }
 #endif
             }
             else
             {
-                r_dtlb.write( true,     // 2M page
-                              pte,
-                              0,        // argument unused for a PTE1
-                              r_dcache_tlb_vaddr.read(),
-                              r_dcache_tlb_way.read(),
-                              r_dcache_tlb_set.read(),
-                              nline );
+                r_dtlb.write(true, // 2M page
+                             pte,
+                             0, // argument unused for a PTE1
+                             r_dcache_tlb_vaddr.read(),
+                             r_dcache_tlb_way.read(),
+                             r_dcache_tlb_set.read(),
+                             nline);
 #ifdef INSTRUMENTATION
-m_cpt_data_tlb_update_acc++;
+                m_cpt_dtlb_write++;
 #endif
 
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB"
-              << " / set = " << std::dec << r_dcache_tlb_set.read()
-              << " / way = " << r_dcache_tlb_way.read() << std::endl;
-    r_dtlb.printTrace();
-}
+                if (m_debug_activated)
+                {
+                    std::cout << "  <PROC " << name()
+                        << " DCACHE_TLB_PTE1_UPDT> write PTE1 in DTLB"
+                        << " / set = " << std::dec << r_dcache_tlb_set.read()
+                        << " / way = " << r_dcache_tlb_way.read() << std::endl;
+                    r_dtlb.printTrace();
+                }
 #endif
             }
@@ -3435 +3429 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_TLB_PTE1_UPDT> L/R bit update required"
-              << std::endl;
-}
+            if (m_debug_activated)
+            {
+                std::cout << "  <PROC " << name()
+                    << " DCACHE_TLB_PTE1_UPDT> L/R bit update required"
+                    << std::endl;
+            }
 #endif
         }
@@ -3446 +3440 @@
     }
     /////////////////////////
-    case DCACHE_TLB_PTE2_GET:   // Try to get a PTE2 (64 bits) in the dcache
+    case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache
     {
         // coherence clack request (from DSPIN CLACK)
-        if ( r_dcache_clack_req.read() )
+        if (r_dcache_clack_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3457 +3451 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
+        if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3464 +3458 @@
         }
 
-        uint32_t    pte_flags     = 0;
-        uint32_t    pte_ppn       = 0;
-        size_t      way           = 0;
-        size_t      set           = 0;
-        size_t      word          = 0;
-        int         cache_state   = 0;
-
-        r_dcache.read( r_dcache_tlb_paddr.read(),
-                       &pte_flags,
-                       &pte_ppn,
-                       &way,
-                       &set,
-                       &word,
-                       &cache_state );
+        uint32_t pte_flags   = 0;
+        uint32_t pte_ppn     = 0;
+        size_t   way         = 0;
+        size_t   set         = 0;
+        size_t   word        = 0;
+        int      cache_state = 0;
+
+        r_dcache.read(r_dcache_tlb_paddr.read(),
+                      &pte_flags,
+                      &pte_ppn,
+                      &way,
+                      &set,
+                      &word,
+                      &cache_state);
 #ifdef INSTRUMENTATION
-m_cpt_dcache_data_read++;
-m_cpt_dcache_dir_read++;
-#endif
-        if ((cache_state == CACHE_SLOT_STATE_VALID_CC) or (cache_state == CACHE_SLOT_STATE_VALID_NCC))
-        {
-            if ( not (pte_flags & PTE_V_MASK) ) // unmapped
-            {
-                if ( r_dcache_tlb_ins.read() )
+        m_cpt_dcache_data_read++;
+        m_cpt_dcache_dir_read++;
+#endif
+        if ((cache_state == CACHE_SLOT_STATE_VALID_CC) or
+            (cache_state == CACHE_SLOT_STATE_VALID_NCC))
+        {
+            if (not (pte_flags & PTE_V_MASK)) // unmapped
+            {
+                if (r_dcache_tlb_ins.read())
                 {
                     r_mmu_ietr             = MMU_READ_PT2_UNMAPPED;
@@ -3495 +3490 @@
                 else
                 {
-                    r_mmu_detr             = MMU_READ_PT2_UNMAPPED;
-                    r_mmu_dbvar            = r_dcache_tlb_vaddr.read();
-                    m_drsp.valid           = true;
-                    m_drsp.error           = true;
-                }
-                r_dcache_fsm               = DCACHE_IDLE;
+                    r_mmu_detr   = MMU_READ_PT2_UNMAPPED;
+                    r_mmu_dbvar  = r_dcache_tlb_vaddr.read();
+                    m_drsp.valid = true;
+                    m_drsp.error = true;
+                }
+                r_dcache_fsm = DCACHE_IDLE;
 
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE unmapped"
-              << " PTE_FLAGS = " << std::hex << pte_flags
-              << " PTE_PPN = " << std::hex << pte_ppn << std::endl;
-}
-#endif
-            }
-            else                // mapped : we must update the TLB
-            {
-                r_dcache_content_state[m_dcache_sets*way+set] = LINE_CACHE_IN_TLB;
+                if (m_debug_activated)
+                {
+                    std::cout << "  <PROC " << name()
+                        << " DCACHE_TLB_PTE2_GET> HIT in dcache, but PTE unmapped"
+                        << " PTE_FLAGS = " << std::hex << pte_flags
+                        << " PTE_PPN = " << std::hex << pte_ppn << std::endl;
+                }
+#endif
+            }
+            else // mapped : we must update the TLB
+            {
+                r_dcache_content_state[m_dcache_sets * way + set] = LINE_CACHE_IN_TLB;
                 r_dcache_tlb_pte_flags  = pte_flags;
                 r_dcache_tlb_pte_ppn    = pte_ppn;
                 r_dcache_fsm            = DCACHE_TLB_PTE2_SELECT;
 
-                r_cas_islocal    = (cache_state == CACHE_SLOT_STATE_VALID_NCC);//do not check L2 if NCC: the CAS is necessarily a success
+                r_cas_islocal    = (cache_state == CACHE_SLOT_STATE_VALID_NCC); // do not check L2 if NCC: the CAS is necessarily a success
                 r_cas_local_way  = way;
                 r_cas_local_set  = set;
@@ -3525 +3520 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_TLB_PTE2_GET> HIT in dcache:"
-              << " PTE_FLAGS = " << std::hex << pte_flags
-              << " PTE_PPN = " << std::hex << pte_ppn << std::endl;
-}
+                if (m_debug_activated)
+                {
+                    std::cout << "  <PROC " << name()
+                        << " DCACHE_TLB_PTE2_GET> HIT in dcache:"
+                        << " PTE_FLAGS = " << std::hex << pte_flags
+                        << " PTE_PPN = " << std::hex << pte_ppn << std::endl;
+                }
 #endif
              }
         }
-        else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup
+        else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup
         {
             // stalled until cleanup is acknowledged
@@ -3541 +3536 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_TLB_PTE2_GET> ZOMBI in dcache: waiting cleanup ack"
-              << std::endl;
-}
+            if (m_debug_activated)
+            {
+                std::cout << "  <PROC " << name()
+                    << " DCACHE_TLB_PTE2_GET> ZOMBI in dcache: waiting cleanup ack"
+                    << std::endl;
+            }
 #endif
         }
@@ -3558 +3553 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_TLB_PTE2_GET> MISS in dcache:"
-              << " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
-}
+            if (m_debug_activated)
+            {
+                std::cout << "  <PROC " << name()
+                    << " DCACHE_TLB_PTE2_GET> MISS in dcache:"
+                    << " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl;
+            }
 #endif
         }
@@ -3574 +3569 @@
         size_t set;
 
-        if ( r_dcache_tlb_ins.read() )
-        {
-            r_itlb.select( r_dcache_tlb_vaddr.read(),
-                           false,   // PTE2
-                           &way,
-                           &set );
+        if (r_dcache_tlb_ins.read())
+        {
+            r_itlb.select(r_dcache_tlb_vaddr.read(),
+                          false, // PTE2
+                          &way,
+                          &set);
 #ifdef INSTRUMENTATION
-m_cpt_ins_tlb_read++;
+            m_cpt_itlb_read++;
 #endif
         }
         else
         {
-            r_dtlb.select( r_dcache_tlb_vaddr.read(),
-                           false,   // PTE2
-                           &way,
-                           &set );
+            r_dtlb.select(r_dcache_tlb_vaddr.read(),
+                          false, // PTE2
+                          &way,
+                          &set);
 #ifdef INSTRUMENTATION
-m_cpt_data_tlb_read++;
+            m_cpt_dtlb_read++;
 #endif
         }
 
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    if ( r_dcache_tlb_ins.read() )
-        std::cout << "  <PROC " << name()
-                  << " DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
-    else
-        std::cout << "  <PROC " << name()
-                  << " DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
-        std::cout << " way = " << std::dec << way
-                  << " / set = " << set << std::endl;
-}
+        if (m_debug_activated)
+        {
+            if (r_dcache_tlb_ins.read())
+                std::cout << "  <PROC " << name()
+                    << " DCACHE_TLB_PTE2_SELECT> Select a slot in ITLB:";
+            else
+                std::cout << "  <PROC " << name()
+                    << " DCACHE_TLB_PTE2_SELECT> Select a slot in DTLB:";
+            std::cout << " way = " << std::dec << way
+                << " / set = " << set << std::endl;
+        }
 #endif
         r_dcache_tlb_way = way;
@@ -3620 +3615 @@
                                 //   the coherence mechanism.
     {
-        paddr_t         nline     = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
-        uint32_t        pte_flags = r_dcache_tlb_pte_flags.read();
-        uint32_t        pte_ppn   = r_dcache_tlb_pte_ppn.read();
-        bool            pt_updt   = false;
-        bool            local     = true;
+        paddr_t  nline     = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);
+        uint32_t pte_flags = r_dcache_tlb_pte_flags.read();
+        uint32_t pte_ppn   = r_dcache_tlb_pte_ppn.read();
+        bool     pt_updt   = false;
+        bool     local     = true;
 
         // We should compute the access locality:
@@ -3633 +3628 @@
         // As long as this computation is not done, all access are local.
 
-        if ( local )                        // local access
-        {
-            if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit
+        if (local) // local access
+        {
+            if (not ((pte_flags & PTE_L_MASK) == PTE_L_MASK)) // we must set the L bit
             {
                 pt_updt                = true;
@@ -3646 +3641 @@
         else                                                    // remote access
         {
-            if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit
+            if (not ((pte_flags & PTE_R_MASK) == PTE_R_MASK)) // we must set the R bit
             {
                 pt_updt                = true;
@@ -3656 +3651 @@
         }
 
-        if ( not pt_updt )                       // update TLB
-        {
-            if ( r_dcache_tlb_ins.read() )
-            {
-                r_itlb.write( false,    // 4K page
-                              pte_flags,
-                              pte_ppn,
-                              r_dcache_tlb_vaddr.read(),
-                              r_dcache_tlb_way.read(),
-                              r_dcache_tlb_set.read(),
-                              nline );
+        if (not pt_updt) // update TLB
+        {
+            if (r_dcache_tlb_ins.read())
+            {
+                r_itlb.write(false, // 4K page
+                             pte_flags,
+                             pte_ppn,
+                             r_dcache_tlb_vaddr.read(),
+                             r_dcache_tlb_way.read(),
+                             r_dcache_tlb_set.read(),
+                             nline);
 #ifdef INSTRUMENTATION
-m_cpt_ins_tlb_update_acc++;
+                m_cpt_itlb_write++;
 #endif
 
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB"
-              << " / set = " << std::dec << r_dcache_tlb_set.read()
-              << " / way = " << r_dcache_tlb_way.read() << std::endl;
-    r_itlb.printTrace();
-}
+                if (m_debug_activated)
+                {
+                    std::cout << "  <PROC " << name()
+                        << " DCACHE_TLB_PTE2_UPDT> write PTE2 in ITLB"
+                        << " / set = " << std::dec << r_dcache_tlb_set.read()
+                        << " / way = " << r_dcache_tlb_way.read() << std::endl;
+                    r_itlb.printTrace();
+                }
 #endif
             }
             else
             {
-                r_dtlb.write( false,    // 4K page
-                              pte_flags,
-                              pte_ppn,
-                              r_dcache_tlb_vaddr.read(),
-                              r_dcache_tlb_way.read(),
-                              r_dcache_tlb_set.read(),
-                              nline );
+                r_dtlb.write(false, // 4K page
+                             pte_flags,
+                             pte_ppn,
+                             r_dcache_tlb_vaddr.read(),
+                             r_dcache_tlb_way.read(),
+                             r_dcache_tlb_set.read(),
+                             nline);
 #ifdef INSTRUMENTATION
-m_cpt_data_tlb_update_acc++;
+                m_cpt_dtlb_write++;
 #endif
 
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB"
-              << " / set = " << std::dec << r_dcache_tlb_set.read()
-              << " / way = " << r_dcache_tlb_way.read() << std::endl;
-    r_dtlb.printTrace();
-}
+                if (m_debug_activated)
+                {
+                    std::cout << "  <PROC " << name()
+                        << " DCACHE_TLB_PTE2_UPDT> write PTE2 in DTLB"
+                        << " / set = " << std::dec << r_dcache_tlb_set.read()
+                        << " / way = " << r_dcache_tlb_way.read() << std::endl;
+                    r_dtlb.printTrace();
+                }
 #endif
 
@@ -3714 +3709 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_TLB_PTE2_UPDT> L/R bit update required" << std::endl;
-}
+            if (m_debug_activated)
+            {
+                std::cout << "  <PROC " << name()
+                    << " DCACHE_TLB_PTE2_UPDT> L/R bit update required" << std::endl;
+            }
 #endif
         }
@@ -3729 +3724 @@
         uint32_t set  = r_cas_local_set.read();
         uint32_t word = r_cas_local_word.read();
-        paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2);
+        paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2);
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
-}
+        if (m_debug_activated)
+        {
+            std::cout << "  <PROC " << name()
+                << " DCACHE_TLB_LR_UPDT> Update dcache: (L/R) bit" << std::endl;
+        }
 #endif
 
@@ -3744 +3739 @@
                            word,
                            r_dcache_vci_cas_new.read());
-            //compteur dirty
-            r_dcache_dirty_word[(way*m_dcache_sets +set)*m_dcache_words+word] = 1;
-
-            if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB )
-            {
-                r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
-                r_dcache_tlb_inval_line  = nline;
-                r_dcache_tlb_inval_set   = 0;
-                r_dcache_fsm_scan_save   = DCACHE_TLB_RETURN;
-                r_dcache_fsm             = DCACHE_INVAL_TLB_SCAN;
+
+            // stats dirty words
+            r_dcache_dirty_word[(way * m_dcache_sets + set) * m_dcache_words + word] = 1;
+
+            if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_IN_TLB)
+            {
+                r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_DIRTY;
+                r_dcache_tlb_inval_line = nline;
+                r_dcache_tlb_inval_set  = 0;
+                r_dcache_fsm_scan_save  = DCACHE_TLB_RETURN;
+                r_dcache_fsm            = DCACHE_INVAL_TLB_SCAN;
                 break;
             }
 
-            if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD )
+            if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_CONTAINS_PTD)
             {
                 r_itlb.reset();
@@ -3764 +3760 @@
 
 #if DEBUG_DCACHE
-                if ( m_debug_activated )
+                if (m_debug_activated)
                 {
                     std::cout << "  <PROC " << name()
@@ -3777 +3773 @@
         {
             // r_dcache_vci_cas_old & r_dcache_vci_cas_new registers are already set
-          r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
+            r_dcache_vci_paddr = r_dcache_tlb_paddr.read();
 
             // checking llsc reservation buffer
-            if ( r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read() )
+            if (r_dcache_llsc_paddr.read() == r_dcache_tlb_paddr.read())
                 r_dcache_llsc_valid = false;
 
@@ -3800 +3796 @@
     {
         // coherence clack request (from DSPIN CLACK)
-        if ( r_dcache_clack_req.read() )
+        if (r_dcache_clack_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3808 +3804 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
+        if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3815 +3811 @@
         }
 
-        if ( r_vci_rsp_data_error.read() )  // bus error
+        if (r_vci_rsp_data_error.read()) // bus error
         {
             std::cout << "BUS ERROR in DCACHE_TLB_LR_WAIT state" << std::endl;
@@ -3821 +3817 @@
             exit(0);
         }
-       else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
+       else if (r_vci_rsp_fifo_dcache.rok()) // response available
        {
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
-}
+           if (m_debug_activated)
+           {
+               std::cout << "  <PROC " << name()
+                   << " DCACHE_TLB_LR_WAIT> SC response received" << std::endl;
+           }
 #endif
             vci_rsp_fifo_dcache_get = true;
-            r_dcache_fsm            = DCACHE_TLB_RETURN;
+            r_dcache_fsm = DCACHE_TLB_RETURN;
         }
         break;
     }
     ///////////////////////
-    case DCACHE_TLB_RETURN:    // return to caller depending on tlb miss type
+    case DCACHE_TLB_RETURN:  // return to caller depending on tlb miss type
     {
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
-}
-#endif
-        if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false;
+        if (m_debug_activated)
+        {
+            std::cout << "  <PROC " << name()
+                << " DCACHE_TLB_RETURN> TLB MISS completed" << std::endl;
+        }
+#endif
+        if (r_dcache_tlb_ins.read()) r_icache_tlb_miss_req = false;
         r_dcache_fsm = DCACHE_IDLE;
         break;
@@ -3854 +3850 @@
                                 // Caution : the itlb miss requests must be taken
                                 // to avoid dead-lock in case of simultaneous ITLB miss
+                                // Caution : the clack and cc requests must be taken
+                                // to avoid dead-lock
     {
         // coherence clack request (from DSPIN CLACK)
-        if ( r_dcache_clack_req.read() )
+        if (r_dcache_clack_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3864 +3862 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
+        if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3872 +3870 @@
 
         // itlb miss request
-        if ( r_icache_tlb_miss_req.read() )
-        {
-            r_dcache_tlb_ins    = true;
-            r_dcache_tlb_vaddr  = r_icache_vaddr_save.read();
-            r_dcache_fsm        = DCACHE_TLB_MISS;
-            break;
-        }
-
-        if ( not r_dcache_xtn_req.read() )
+        if (r_icache_tlb_miss_req.read())
+        {
+            r_dcache_tlb_ins   = true;
+            r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
+            r_dcache_fsm       = DCACHE_TLB_MISS;
+            break;
+        }
+
+        if (not r_dcache_xtn_req.read())
         {
             r_dtlb.flush();
@@ -3890 +3888 @@
     }
     /////////////////////
-    case DCACHE_XTN_SYNC:       // waiting until write buffer empty
-                                // The coherence request must be taken
-                                // as there is a risk of dead-lock
+    case DCACHE_XTN_SYNC:  // waiting until write buffer empty
+                           // The coherence request must be taken
+                           // as there is a risk of dead-lock
     {
         // coherence clack request (from DSPIN CLACK)
-        if ( r_dcache_clack_req.read() )
+        if (r_dcache_clack_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3903 +3901 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
+        if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3910 +3908 @@
         }
 
-        if ( r_wbuf.empty() )
-        {
-            m_drsp.valid   = true;
+        if (r_wbuf.empty())
+        {
+            m_drsp.valid = true;
             r_dcache_fsm = DCACHE_IDLE;
         }
@@ -3926 +3924 @@
     {
         // coherence clack request (from DSPIN CLACK)
-        if ( r_dcache_clack_req.read() )
+        if (r_dcache_clack_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3934 +3932 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
+        if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3942 +3940 @@
 
         // itlb miss request
-        if ( r_icache_tlb_miss_req.read() )
-        {
-            r_dcache_tlb_ins    = true;
-            r_dcache_tlb_vaddr  = r_icache_vaddr_save.read();
-            r_dcache_fsm        = DCACHE_TLB_MISS;
+        if (r_icache_tlb_miss_req.read())
+        {
+            r_dcache_tlb_ins   = true;
+            r_dcache_tlb_vaddr = r_icache_vaddr_save.read();
+            r_dcache_fsm       = DCACHE_TLB_MISS;
             break;
         }
 
         // test if XTN request to icache completed
-        if ( not r_dcache_xtn_req.read() )
+        if (not r_dcache_xtn_req.read())
         {
             r_dcache_fsm = DCACHE_IDLE;
@@ -3969 +3967 @@
     {
         // coherence clack request (from DSPIN CLACK)
-        if ( r_dcache_clack_req.read() )
+        if (r_dcache_clack_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3977 +3975 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
+        if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -3984 +3982 @@
         }
 
-        if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
-        {
-            int       state;
-            paddr_t   tag;
-            size_t    way = r_dcache_flush_count.read()/m_dcache_sets;
-            size_t    set = r_dcache_flush_count.read()%m_dcache_sets;
+        if (not r_dcache_cc_send_req.read()) // blocked until previous cc_send request is sent
+        {
+            int     state;
+            paddr_t tag;
+            size_t  way = r_dcache_flush_count.read()/m_dcache_sets;
+            size_t  set = r_dcache_flush_count.read()%m_dcache_sets;
 
 #ifdef INSTRUMENTATION
-m_cpt_dcache_dir_read++;
-#endif
-            r_dcache.read_dir( way,
-                               set,
-                               &tag,
-                               &state );
-
-            if ( state == CACHE_SLOT_STATE_VALID_CC )         // inval required
+            m_cpt_dcache_dir_read++;
+#endif
+            r_dcache.read_dir(way,
+                              set,
+                              &tag,
+                              &state);
+
+            if (state == CACHE_SLOT_STATE_VALID_CC) // inval required
             {
                 // request cleanup
@@ -4008 +4006 @@
 
                 // goes to DCACHE_XTN_DC_FLUSH_GO to inval directory
-                r_dcache_miss_way     = way;
-                r_dcache_miss_set     = set;
+                r_dcache_miss_way = way;
+                r_dcache_miss_set = set;
+                r_dcache_fsm      = DCACHE_XTN_DC_FLUSH_GO;
                 r_dcache_cc_cleanup_line_ncc = false;
                 r_dcache_cc_cleanup_updt_data = false;
-                r_dcache_fsm          = DCACHE_XTN_DC_FLUSH_GO;
-            }
-            else if ( state == CACHE_SLOT_STATE_VALID_NCC)
+            }
+            else if (state == CACHE_SLOT_STATE_VALID_NCC)
             {
                 // request cleanup
@@ -4023 +4021 @@
 
                 // goes to DCACHE_XTN_DC_FLUSH_GO to inval directory
-                r_dcache_miss_way     = way;
-                r_dcache_miss_set     = set;
+                r_dcache_miss_way = way;
+                r_dcache_miss_set = set;
                 r_dcache_cc_cleanup_line_ncc = true;
 
-                if (r_dcache_content_state[m_dcache_sets*way+set] != LINE_CACHE_DATA_NOT_DIRTY)//Must send data in the cleanup
+                if (r_dcache_content_state[m_dcache_sets * way + set] != LINE_CACHE_DATA_NOT_DIRTY) // Must send data in the cleanup
                 {
                     r_dcache_xtn_flush_addr_data = (tag * m_dcache_sets + set) * m_dcache_words * 4;
                     r_dcache_xtn_flush_data_cpt = 0;
                     r_dcache_cc_cleanup_updt_data = true;
-                    for (size_t w = 0; w< m_dcache_words; w++)
+                    for (size_t w = 0; w < m_dcache_words; w++)
                     {
-                        m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets*way+set)*m_dcache_words + w];
+                        m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets * way + set) * m_dcache_words + w];
                     }
-                    r_dcache_fsm          = DCACHE_XTN_DC_FLUSH_DATA;
+                    r_dcache_fsm = DCACHE_XTN_DC_FLUSH_DATA;
                 }
                 else
                 {
                     r_dcache_cc_cleanup_updt_data = false;
-                    r_dcache_fsm          = DCACHE_XTN_DC_FLUSH_GO;
-                }
-            }
-            else if ( r_dcache_flush_count.read() ==
-                      (m_dcache_sets*m_dcache_ways - 1) )  // last slot
+                    r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO;
+                }
+            }
+            else if (r_dcache_flush_count.read() ==
+                      (m_dcache_sets * m_dcache_ways - 1))  // last slot
             {
                 r_dtlb.reset();
@@ -4054 +4052 @@
 
             // saturation counter
-            if ( r_dcache_flush_count.read() < (m_dcache_sets*m_dcache_ways - 1) )
+            if (r_dcache_flush_count.read() < (m_dcache_sets * m_dcache_ways - 1))
                 r_dcache_flush_count = r_dcache_flush_count.read() + 1;
         }
         break;
     }
-
     ////////////////////////////
     case DCACHE_XTN_DC_FLUSH_DATA:
     {
         uint32_t rdata;
-        size_t   way;
-        size_t   set;
-        size_t   word;
+        size_t way;
+        size_t set;
+        size_t word;
 
         r_dcache.read_neutral(r_dcache_xtn_flush_addr_data.read(),
@@ -4073 +4070 @@
                               &set,
                               &word);
-        if(r_cc_send_data_fifo.wok())
+
+        if (r_cc_send_data_fifo.wok())
         {
             r_dcache_xtn_flush_addr_data = r_dcache_xtn_flush_addr_data.read() + 4;
 
-            cleanup_data_updt_fifo_dcache_put   = true;
-            cleanup_data_updt_fifo_dcache_data  = rdata;
+            cleanup_data_updt_fifo_dcache_put = true;
+            cleanup_data_updt_fifo_dcache_data = rdata;
 
             r_dcache_xtn_flush_data_cpt = r_dcache_xtn_flush_data_cpt + 1;
-            if(r_dcache_xtn_flush_data_cpt.read() == (m_dcache_words - 1))
+            if (r_dcache_xtn_flush_data_cpt.read() == (m_dcache_words - 1))
             {
                 r_dcache_xtn_flush_data_cpt = 0;
@@ -4089 +4087 @@
         break;
     }
-
     ////////////////////////////
     case DCACHE_XTN_DC_FLUSH_GO:    // Switch the cache slot to ZOMBI state
@@ -4098 +4095 @@
         size_t set = r_dcache_miss_set.read();
 
-        r_dcache_content_state[m_dcache_sets*way+set]  = LINE_CACHE_DATA_DIRTY;
+        r_dcache_content_state[m_dcache_sets * way + set]  = LINE_CACHE_DATA_DIRTY;
 
 #ifdef INSTRUMENTATION
-m_cpt_dcache_dir_write++;
-#endif
-
-
-
-        r_dcache.write_dir( way,
-                            set,
-                            CACHE_SLOT_STATE_ZOMBI );
-
-        if ( r_dcache_flush_count.read() ==
-             (m_dcache_sets*m_dcache_ways - 1) )  // last slot
+        m_cpt_dcache_dir_write++;
+#endif
+        r_dcache.write_dir(way,
+                           set,
+                           CACHE_SLOT_STATE_ZOMBI);
+
+        if (r_dcache_flush_count.read() ==
+             (m_dcache_sets * m_dcache_ways - 1))  // last slot
         {
             r_dtlb.reset();
@@ -4125 +4119 @@
     }
     /////////////////////////
-    case DCACHE_XTN_DT_INVAL:   // handling processor XTN_DTLB_INVAL request
+    case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request
     {
         r_dtlb.inval(r_dcache_save_wdata.read());
-        r_dcache_fsm        = DCACHE_IDLE;
-        m_drsp.valid          = true;
+        r_dcache_fsm = DCACHE_IDLE;
+        m_drsp.valid = true;
         break;
     }
@@ -4138 +4132 @@
     {
         paddr_t paddr;
-        bool    hit;
-
-        if ( r_mmu_mode.read() & DATA_TLB_MASK )    // dtlb activated
+        bool hit;
+
+        if (r_mmu_mode.read() & DATA_TLB_MASK) // dtlb activated
         {
 
 #ifdef INSTRUMENTATION
-m_cpt_data_tlb_read++;
-#endif
-            hit = r_dtlb.translate( r_dcache_save_wdata.read(),
-                                    &paddr );
-        }
-        else                        // dtlb not activated
+            m_cpt_dtlb_read++;
+#endif
+            hit = r_dtlb.translate(r_dcache_save_wdata.read(),
+                                   &paddr);
+        }
+        else // dtlb not activated
         {
             paddr = (paddr_t)r_dcache_save_wdata.read();
             if (vci_param::N > 32)
                 paddr = paddr | ((paddr_t)(r_dcache_paddr_ext.read()) << 32);
-            hit   = true;
-        }
-
-        if ( hit )      // tlb hit
+            hit = true;
+        }
+
+        if (hit) // tlb hit
         {
             r_dcache_save_paddr = paddr;
-            r_dcache_fsm      = DCACHE_XTN_DC_INVAL_PA;
-        }
-        else            // tlb miss
+            r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA;
+        }
+        else // tlb miss
         {
 
 #ifdef INSTRUMENTATION
-m_cpt_data_tlb_miss++;
-#endif
-            r_dcache_tlb_ins    = false;        // dtlb
-            r_dcache_tlb_vaddr  = r_dcache_save_wdata.read();
-            r_dcache_fsm        = DCACHE_TLB_MISS;
+            m_cpt_dtlb_miss++;
+#endif
+            r_dcache_tlb_ins   = false; // dtlb
+            r_dcache_tlb_vaddr = r_dcache_save_wdata.read();
+            r_dcache_fsm       = DCACHE_TLB_MISS;
         }
 
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
-              << " / VADDR = " << r_dcache_save_wdata.read()
-              << " / PADDR = " << paddr << std::endl;
-}
+        if (m_debug_activated)
+        {
+            std::cout << "  <PROC " << name()
+                << " DCACHE_XTN_DC_INVAL_VA> Compute physical address" << std::hex
+                << " / VADDR = " << r_dcache_save_wdata.read()
+                << " / PADDR = " << paddr << std::endl;
+        }
 #endif
 
@@ -4190 +4184 @@
                                   // In this state we read dcache.
     {
-        size_t      way;
-        size_t      set;
-        size_t      word;
-        int         state;
+        size_t way;
+        size_t set;
+        size_t word;
+        int    state;
 
 #ifdef INSTRUMENTATION
-m_cpt_dcache_dir_read++;
-#endif
-        r_dcache.read_dir( r_dcache_save_paddr.read(),
-                           &state,
-                           &way,
-                           &set,
-                           &word );
-
-        if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC))  // inval to be done
+        m_cpt_dcache_dir_read++;
+#endif
+        r_dcache.read_dir(r_dcache_save_paddr.read(),
+                          &state,
+                          &way,
+                          &set,
+                          &word);
+
+        if ((state == CACHE_SLOT_STATE_VALID_CC) or
+            (state == CACHE_SLOT_STATE_VALID_NCC))  // inval to be done
         {
             r_dcache_xtn_way       = way;
             r_dcache_xtn_set       = set;
             r_dcache_xtn_state     = state;
-            r_dcache_xtn_data_addr = r_dcache_save_paddr.read()&~0x3F;
-
-            if( (state == CACHE_SLOT_STATE_VALID_NCC) and (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_NOT_DIRTY) )
+            r_dcache_xtn_data_addr = r_dcache_save_paddr.read() & ~0x3F;
+
+            if ((state == CACHE_SLOT_STATE_VALID_NCC) and
+                (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_DATA_NOT_DIRTY))
             {
                 m_cpt_cleanup_data_not_dirty ++;
             }
             r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
-
-        }
-        else        // miss : nothing to do
-        {
-            r_dcache_fsm      = DCACHE_IDLE;
-            m_drsp.valid      = true;
+        }
+        else // miss : nothing to do
+        {
+            r_dcache_fsm = DCACHE_IDLE;
+            m_drsp.valid = true;
         }
 
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
-              << " / PADDR = " << r_dcache_save_paddr.read() << std::dec
-              << " / HIT = " << ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC))
-              << " / SET = " << set
-              << " / WAY = " << way << std::endl;
-    //r_dcache.printTrace();
-}
+        if (m_debug_activated)
+        {
+            std::cout << "  <PROC " << name()
+                << " DCACHE_XTN_DC_INVAL_PA> Test hit in dcache" << std::hex
+                << " / PADDR = " << r_dcache_save_paddr.read() << std::dec
+                << " / HIT = " << ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC))
+                << " / SET = " << set
+                << " / WAY = " << way << std::endl;
+        }
 #endif
         break;
@@ -4243 +4237 @@
                                   // Test if itlb or dtlb inval is required
     {
-        if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent
-        {
-            int     state      = r_dcache_xtn_state.read();
-            size_t  way        = r_dcache_xtn_way.read();
-            size_t  set        = r_dcache_xtn_set.read();
-            paddr_t nline      = r_dcache_save_paddr.read() / (m_dcache_words<<2);
+        if (not r_dcache_cc_send_req.read()) // blocked until previous cc_send request is sent
+        {
+            int state     = r_dcache_xtn_state.read();
+            size_t way    = r_dcache_xtn_way.read();
+            size_t set    = r_dcache_xtn_set.read();
+            paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words << 2);
 
 #ifdef INSTRUMENTATION
-m_cpt_dcache_dir_write++;
-#endif
-
-            if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC))// request cleanup
+            m_cpt_dcache_dir_write++;
+#endif
+            if ((state == CACHE_SLOT_STATE_VALID_CC) or
+                (state == CACHE_SLOT_STATE_VALID_NCC)) // request cleanup
             {
                 r_dcache_cc_send_req   = true;
@@ -4263 +4257 @@
                 {
                     r_dcache_cc_cleanup_line_ncc = false;
-                    r_dcache.write_dir( way,
-                            set,
-                            CACHE_SLOT_STATE_ZOMBI );
+                    r_dcache.write_dir(way,
+                                       set,
+                                       CACHE_SLOT_STATE_ZOMBI);
                 }
                 else
                 {
                     r_dcache_cc_cleanup_line_ncc = true;
-                    if ((r_dcache_content_state[way*m_dcache_sets+set] != LINE_CACHE_DATA_NOT_DIRTY)) //must send data
+                    if ((r_dcache_content_state[way * m_dcache_sets + set] != LINE_CACHE_DATA_NOT_DIRTY)) //must send data
                     {
                         r_dcache_cc_cleanup_updt_data = true;
-                        for (size_t w = 0; w< m_dcache_words; w++)
+                        for (size_t w = 0; w < m_dcache_words; w++)
                         {
-                            m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets*way+set)*m_dcache_words + w];
+                            m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets * way + set) * m_dcache_words + w];
                         }
                         r_dcache_fsm = DCACHE_XTN_DC_INVAL_DATA;
@@ -4283 +4277 @@
                     {
                         r_dcache_cc_cleanup_updt_data = false;
-                        r_dcache.write_dir( way,
-                                            set,
-                                            CACHE_SLOT_STATE_ZOMBI );
+                        r_dcache.write_dir(way,
+                                           set,
+                                           CACHE_SLOT_STATE_ZOMBI);
                     }
-                    if( (state == CACHE_SLOT_STATE_VALID_NCC) and (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_NOT_DIRTY) )
+                    if ((state == CACHE_SLOT_STATE_VALID_NCC) and
+                        (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_DATA_NOT_DIRTY))
+                    {
                         m_cpt_cleanup_data_not_dirty ++;
+                    }
                 }
             }
 
             // possible itlb & dtlb invalidate
-            if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB )
+            if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_IN_TLB)
             {
                 r_dcache_tlb_inval_line = nline;
@@ -4299 +4296 @@
                 r_dcache_fsm_scan_save  = DCACHE_XTN_DC_INVAL_END;
                 r_dcache_fsm            = DCACHE_INVAL_TLB_SCAN;
-                r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
-            }
-            else if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD)
+                r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_DIRTY;
+            }
+            else if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_CONTAINS_PTD)
             {
                 r_itlb.reset();
                 r_dtlb.reset();
-                r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
+                r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_DIRTY;
                 r_dcache_fsm = DCACHE_IDLE;
                 m_drsp.valid = true;
@@ -4316 +4313 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
-              << " / PADDR = " << r_dcache_save_paddr.read() << std::endl;
-}
+            if (m_debug_activated)
+            {
+                std::cout << "  <PROC " << name()
+                    << " DCACHE_XTN_DC_INVAL_GO> Actual dcache inval" << std::hex
+                    << " / PADDR = " << r_dcache_save_paddr.read() << std::endl;
+            }
 #endif
         }
         break;
     }
-
-    /*RWT*/
     //////////////////////////////
     case DCACHE_XTN_DC_INVAL_DATA:
     {
-
         uint32_t rdata;
-        size_t   way = 0; // To avoid gcc warning
-        size_t   set = 0; // To avoid gcc warning
-        size_t   word;
+        size_t way = 0; // To avoid gcc warning
+        size_t set = 0; // To avoid gcc warning
+        size_t word;
         r_dcache.read_neutral(r_dcache_xtn_data_addr.read(),
                               &rdata,
@@ -4341 +4335 @@
                               &set,
                               &word);
-        if(r_cc_send_data_fifo.wok())
+        if (r_cc_send_data_fifo.wok())
         {
             r_dcache_xtn_data_addr = r_dcache_xtn_data_addr.read() + 4;
 
-            cleanup_data_updt_fifo_dcache_put   = true;
-            cleanup_data_updt_fifo_dcache_data  = rdata;
+            cleanup_data_updt_fifo_dcache_put = true;
+            cleanup_data_updt_fifo_dcache_data = rdata;
 
             r_dcache_xtn_data_cpt = r_dcache_xtn_data_cpt.read() + 1;
-            if(r_dcache_xtn_data_cpt.read() == (m_dcache_words - 1))
+            if (r_dcache_xtn_data_cpt.read() == (m_dcache_words - 1))
             {
                 r_dcache_xtn_state = CACHE_SLOT_STATE_ZOMBI;
                 r_dcache_xtn_data_cpt = 0;
                 r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO;
-                r_dcache.write_dir( way,
-                                    set,
-                                    CACHE_SLOT_STATE_ZOMBI );
+                r_dcache.write_dir(way,
+                                   set,
+                                   CACHE_SLOT_STATE_ZOMBI);
             }
         }
         break;
     }
-
     //////////////////////////////
-    case DCACHE_XTN_DC_INVAL_END:   // send response to processor XTN request
+    case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request
     {
         r_dcache_fsm = DCACHE_IDLE;
@@ -4377 +4370 @@
                                // when a cleanup is required
     {
-        if ( m_dreq.valid) m_cost_data_miss_frz++;
+        if (m_dreq.valid) m_cost_data_miss_frz++;
 
         // coherence clack request (from DSPIN CLACK)
-        if ( r_dcache_clack_req.read() )
+        if (r_dcache_clack_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4388 +4381 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
+        if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4395 +4388 @@
         }
 
-            bool    found = false;
-            bool    cleanup = false;
-            size_t  way = 0;
-            size_t  set = 0;
-            paddr_t victim = 0;
-            int     state;
-            bool    s_cleanup_updt_data = false;
-            bool    s_cleanup_line_ncc = false;
+        bool    found = false;
+        bool    cleanup = false;
+        size_t  way = 0;
+        size_t  set = 0;
+        paddr_t victim = 0;
+        int     state;
+        bool    s_cleanup_updt_data = false;
+        bool    s_cleanup_line_ncc = false;
 
 #ifdef INSTRUMENTATION
-m_cpt_dcache_dir_read++;
-#endif
-            r_dcache.read_select( r_dcache_save_paddr.read(),
-                                  &victim,
-                                  &way,
-                                  &set,
-                                  &found,
-                                  &cleanup );
-            state = r_dcache.get_cache_state(way,set);
-
-            if ( found )
-            {
-                r_dcache_miss_way = way;
-                r_dcache_miss_set = set;
-
-                if ( cleanup )
-                {
-                    r_dcache_miss_clack   = true;
-                    r_dcache_fsm          = DCACHE_MISS_CLEAN;
-                    if( (state == CACHE_SLOT_STATE_VALID_NCC) )
+        m_cpt_dcache_dir_read++;
+#endif
+        r_dcache.read_select(r_dcache_save_paddr.read(),
+                             &victim,
+                             &way,
+                             &set,
+                             &found,
+                             &cleanup);
+        state = r_dcache.get_cache_state(way, set);
+
+        if (found)
+        {
+            r_dcache_miss_way = way;
+            r_dcache_miss_set = set;
+
+            if (cleanup)
+            {
+                r_dcache_miss_clack = true;
+                r_dcache_fsm = DCACHE_MISS_CLEAN;
+
+                if ((state == CACHE_SLOT_STATE_VALID_NCC))
+                {
+                    s_cleanup_line_ncc = true;
+                    r_dcache_miss_data_addr = (victim * m_dcache_words) * 4;
+                    if ((r_dcache_content_state[way * m_dcache_sets + set] != LINE_CACHE_DATA_NOT_DIRTY)) // must send data
                     {
-                        s_cleanup_line_ncc = true;
-                        r_dcache_miss_data_addr = (victim*m_dcache_words)*4;
-                        if ((r_dcache_content_state[way*m_dcache_sets+set] != LINE_CACHE_DATA_NOT_DIRTY))//must send data
+                        s_cleanup_updt_data = true;
+                        for (size_t w = 0; w < m_dcache_words; w++)
                         {
-                            s_cleanup_updt_data = true;
-                            for (size_t w = 0; w< m_dcache_words; w++)
-                            {
-                                m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets*way+set)*m_dcache_words + w];
-                            }
-                            r_dcache_fsm = DCACHE_MISS_DATA;
+                            m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets * way + set) * m_dcache_words + w];
                         }
-                        else
-                        {
-                            s_cleanup_updt_data = false;
-                        }
-
-                        if (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_NOT_DIRTY)
-                            m_cpt_cleanup_data_not_dirty ++;
+                        r_dcache_fsm = DCACHE_MISS_DATA;
                     }
                     else
                     {
-                        s_cleanup_line_ncc  = false;
                         s_cleanup_updt_data = false;
                     }
 
-                    if( not r_dcache_cc_send_req.read() )
-                    {
-                        // request cleanup
-                        r_dcache_cc_send_req   = true;
-                        r_dcache_cc_send_nline = victim;
-                        r_dcache_cc_send_way   = way;
-                        r_dcache_cc_send_type  = CC_TYPE_CLEANUP;
-                        r_dcache_cc_cleanup_updt_data = s_cleanup_updt_data;
-                        r_dcache_cc_cleanup_line_ncc  = s_cleanup_line_ncc;
-                    }
-                    else
-                    {
-                        r_dcache_cleanup_victim_nline = victim;
-                        r_dcache_cleanup_victim_req = true;
-                        r_dcache_cleanup_victim_updt_data = s_cleanup_updt_data;
-                        r_dcache_cleanup_victim_line_ncc = s_cleanup_line_ncc;
-                    }
+                    if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_DATA_NOT_DIRTY)
+                        m_cpt_cleanup_data_not_dirty ++;
                 }
                 else
                 {
-                    r_dcache_fsm          = DCACHE_MISS_WAIT;
-                }
+                    s_cleanup_line_ncc  = false;
+                    s_cleanup_updt_data = false;
+                }
+
+                if (not r_dcache_cc_send_req.read())
+                {
+                    // request cleanup
+                    r_dcache_cc_send_req   = true;
+                    r_dcache_cc_send_nline = victim;
+                    r_dcache_cc_send_way   = way;
+                    r_dcache_cc_send_type  = CC_TYPE_CLEANUP;
+                    r_dcache_cc_cleanup_updt_data = s_cleanup_updt_data;
+                    r_dcache_cc_cleanup_line_ncc  = s_cleanup_line_ncc;
+                }
+                else
+                {
+                    r_dcache_cleanup_victim_nline = victim;
+                    r_dcache_cleanup_victim_req = true;
+                    r_dcache_cleanup_victim_updt_data = s_cleanup_updt_data;
+                    r_dcache_cleanup_victim_line_ncc = s_cleanup_line_ncc;
+                }
+            }
+            else
+            {
+                r_dcache_fsm = DCACHE_MISS_WAIT;
+            }
 
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_MISS_SELECT> Select a slot:" << std::dec
-              << " / WAY = "   << way
-              << " / SET = "   << set
-              << " / PADDR = " << std::hex << r_dcache_save_paddr.read();
-    if(cleanup) std::cout << " / VICTIM = " << (victim*m_dcache_words*4) << std::endl;
-    else        std::cout << std::endl;
-}
-#endif
-            } // end found
+            if (m_debug_activated)
+            {
+                std::cout << "  <PROC " << name()
+                    << " DCACHE_MISS_SELECT> Select a slot:" << std::dec
+                    << " / WAY = "   << way
+                    << " / SET = "   << set
+                    << " / PADDR = " << std::hex << r_dcache_save_paddr.read();
+                if (cleanup) std::cout << " / VICTIM = " << (victim * m_dcache_words * 4) << std::dec << std::endl;
+                else         std::cout << std::dec << std::endl;
+            }
+#endif
+        } // end found
         break;
     }
@@ -4497 +4491 @@
         size_t word;
 
-        if( r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read() )
+        if (r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_cc_send_req = true;
@@ -4513 +4507 @@
                               &set,
                               &word);
-        if(r_cc_send_data_fifo.wok())
+        if (r_cc_send_data_fifo.wok())
         {
             r_dcache_miss_data_addr = r_dcache_miss_data_addr.read() + 4;
 
-            cleanup_data_updt_fifo_dcache_put   = true;
-            cleanup_data_updt_fifo_dcache_data  = rdata;
+            cleanup_data_updt_fifo_dcache_put = true;
+            cleanup_data_updt_fifo_dcache_data = rdata;
 
             r_dcache_miss_data_cpt = r_dcache_miss_data_cpt.read() + 1;
-            if (r_dcache_miss_data_cpt.read() == m_dcache_words-1 )
+            if (r_dcache_miss_data_cpt.read() == (m_dcache_words - 1))
             {
                 r_dcache_miss_data_cpt = 0;
@@ -4534 +4528 @@
                                 // and possibly request itlb or dtlb invalidate
     {
-        if ( m_dreq.valid) m_cost_data_miss_frz++;
-
-        size_t  way   = r_dcache_miss_way.read();
-        size_t  set   = r_dcache_miss_set.read();
+        if (m_dreq.valid) m_cost_data_miss_frz++;
+
+        size_t way = r_dcache_miss_way.read();
+        size_t set = r_dcache_miss_set.read();
 
 #ifdef INSTRUMENTATION
-m_cpt_dcache_dir_read++;
-#endif
-        r_dcache.write_dir( way,
-                            set,
-                            CACHE_SLOT_STATE_ZOMBI );
+        m_cpt_dcache_dir_read++;
+#endif
+        r_dcache.write_dir(way,
+                           set,
+                           CACHE_SLOT_STATE_ZOMBI);
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
-              << " / way = "   << way
-              << " / set = "   << set << std::endl;
-}
+        if (m_debug_activated)
+        {
+            std::cout << "  <PROC " << name()
+                << " DCACHE_MISS_CLEAN> Switch to ZOMBI state" << std::dec
+                << " / way = "   << way
+                << " / set = "   << set << std::endl;
+        }
 #endif
         // if selective itlb & dtlb invalidate are required
         // the miss response is not handled before invalidate completed
-        if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB )
-        {
-            r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
-            if( not r_dcache_cleanup_victim_req.read() )
-            {
+        if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_IN_TLB)
+        {
+            r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_DIRTY;
+
+            if (not r_dcache_cleanup_victim_req.read())
                 r_dcache_tlb_inval_line = r_dcache_cc_send_nline.read();
-            }
             else
-            {
                 r_dcache_tlb_inval_line = r_dcache_cleanup_victim_nline.read();
-            }
-            r_dcache_tlb_inval_set   = 0;
-            r_dcache_fsm_scan_save   = DCACHE_MISS_WAIT;
-            r_dcache_fsm             = DCACHE_INVAL_TLB_SCAN;
-        }
-        else if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD )
+
+            r_dcache_tlb_inval_set = 0;
+            r_dcache_fsm_scan_save = DCACHE_MISS_WAIT;
+            r_dcache_fsm           = DCACHE_INVAL_TLB_SCAN;
+        }
+        else if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_CONTAINS_PTD)
         {
             r_itlb.reset();
             r_dtlb.reset();
-            r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
+            r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_DIRTY;
             r_dcache_fsm = DCACHE_MISS_WAIT;
         }
@@ -4589 +4581 @@
                             // There is 5 types of error depending on the requester
     {
-        if ( m_dreq.valid) m_cost_data_miss_frz++;
-
-        if( r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read() )
-        {
-            r_dcache_cc_send_req = true;
-            r_dcache_cc_send_type = CC_TYPE_CLEANUP;
-            r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline.read();
+        if (m_dreq.valid) m_cost_data_miss_frz++;
+
+        // send cleanup victim request
+        if (r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read())
+        {
+            r_dcache_cc_send_req        = true;
+            r_dcache_cc_send_nline      = r_dcache_cleanup_victim_nline.read();
+            r_dcache_cc_send_way        = r_dcache_miss_way.read();
+            r_dcache_cc_send_type       = CC_TYPE_CLEANUP;
             r_dcache_cleanup_victim_req = false;
             r_dcache_cc_cleanup_updt_data = r_dcache_cleanup_victim_updt_data.read();
-            r_dcache_cc_cleanup_line_ncc = r_dcache_cleanup_victim_line_ncc.read();
-            r_dcache_cc_send_way = r_dcache_miss_way;
+            r_dcache_cc_cleanup_line_ncc  = r_dcache_cleanup_victim_line_ncc.read();
         }
 
         // coherence clack request (from DSPIN CLACK)
-        if ( r_dcache_clack_req.read() )
+        if (r_dcache_clack_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4611 +4604 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_cleanup_victim_req.read() )
+        if (r_cc_receive_dcache_req.read() and
+            not r_dcache_cc_send_req.read() and
+            not r_dcache_cleanup_victim_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4618 +4613 @@
         }
 
-        if ( r_vci_rsp_data_error.read() )  // bus error
-        {
-            switch ( r_dcache_miss_type.read() )
+        if (r_vci_rsp_data_error.read()) // bus error
+        {
+            switch (r_dcache_miss_type.read())
             {
                 case PROC_MISS:
                 {
-                    r_mmu_detr            = MMU_READ_DATA_ILLEGAL_ACCESS;
-                    r_mmu_dbvar           = r_dcache_save_vaddr.read();
-                    m_drsp.valid            = true;
-                    m_drsp.error            = true;
-                    r_dcache_fsm          = DCACHE_IDLE;
+                    r_mmu_detr   = MMU_READ_DATA_ILLEGAL_ACCESS;
+                    r_mmu_dbvar  = r_dcache_save_vaddr.read();
+                    m_drsp.valid = true;
+                    m_drsp.error = true;
+                    r_dcache_fsm = DCACHE_IDLE;
                     break;
                 }
                 case PTE1_MISS:
                 {
-                    if ( r_dcache_tlb_ins.read() )
+                    if (r_dcache_tlb_ins.read())
                     {
-                        r_mmu_ietr              = MMU_READ_PT1_ILLEGAL_ACCESS;
-                        r_mmu_ibvar             = r_dcache_tlb_vaddr.read();
-                        r_icache_tlb_miss_req   = false;
-                        r_icache_tlb_rsp_error  = true;
+                        r_mmu_ietr             = MMU_READ_PT1_ILLEGAL_ACCESS;
+                        r_mmu_ibvar            = r_dcache_tlb_vaddr.read();
+                        r_icache_tlb_miss_req  = false;
+                        r_icache_tlb_rsp_error = true;
                     }
                     else
                     {
-                        r_mmu_detr              = MMU_READ_PT1_ILLEGAL_ACCESS;
-                        r_mmu_dbvar             = r_dcache_tlb_vaddr.read();
-                        m_drsp.valid              = true;
-                        m_drsp.error              = true;
+                        r_mmu_detr   = MMU_READ_PT1_ILLEGAL_ACCESS;
+                        r_mmu_dbvar  = r_dcache_tlb_vaddr.read();
+                        m_drsp.valid = true;
+                        m_drsp.error = true;
                     }
-                    r_dcache_fsm                = DCACHE_IDLE;
+                    r_dcache_fsm = DCACHE_IDLE;
                     break;
                 }
                 case PTE2_MISS:
                 {
-                    if ( r_dcache_tlb_ins.read() )
+                    if (r_dcache_tlb_ins.read())
                     {
-                        r_mmu_ietr              = MMU_READ_PT2_ILLEGAL_ACCESS;
-                        r_mmu_ibvar             = r_dcache_tlb_vaddr.read();
-                        r_icache_tlb_miss_req   = false;
-                        r_icache_tlb_rsp_error  = true;
+                        r_mmu_ietr             = MMU_READ_PT2_ILLEGAL_ACCESS;
+                        r_mmu_ibvar            = r_dcache_tlb_vaddr.read();
+                        r_icache_tlb_miss_req  = false;
+                        r_icache_tlb_rsp_error = true;
                     }
                     else
                     {
-                        r_mmu_detr              = MMU_READ_PT2_ILLEGAL_ACCESS;
-                        r_mmu_dbvar             = r_dcache_tlb_vaddr.read();
-                        m_drsp.valid              = true;
-                        m_drsp.error              = true;
+                        r_mmu_detr   = MMU_READ_PT2_ILLEGAL_ACCESS;
+                        r_mmu_dbvar  = r_dcache_tlb_vaddr.read();
+                        m_drsp.valid = true;
+                        m_drsp.error = true;
                     }
-                    r_dcache_fsm                = DCACHE_IDLE;
+                    r_dcache_fsm = DCACHE_IDLE;
                     break;
                 }
@@ -4672 +4667 @@
             r_vci_rsp_data_error = false;
         }
-        else if ( r_vci_rsp_fifo_dcache.rok() )    // valid response available
+        else if (r_vci_rsp_fifo_dcache.rok()) // valid response available
         {
             r_dcache_miss_word = 0;
@@ -4680 +4675 @@
     }
     //////////////////////////
-    case DCACHE_MISS_DATA_UPDT:   // update the dcache (one word per cycle)
-    {
-        if ( m_dreq.valid) m_cost_data_miss_frz++;
-
-        if ( r_vci_rsp_fifo_dcache.rok() && r_vci_rsp_fifo_rpktid.rok())   // one word available
+    case DCACHE_MISS_DATA_UPDT:  // update the dcache (one word per cycle)
+    {
+        if (m_dreq.valid) m_cost_data_miss_frz++;
+
+        if (r_vci_rsp_fifo_dcache.rok() and r_vci_rsp_fifo_rpktid.rok()) // one word available
         {
 #ifdef INSTRUMENTATION
-m_cpt_dcache_data_write++;
-#endif
-                r_dcache.write( r_dcache_miss_way.read(),
-                                r_dcache_miss_set.read(),
-                                r_dcache_miss_word.read(),
-                                r_vci_rsp_fifo_dcache.read() );
+            m_cpt_dcache_data_write++;
+#endif
+            r_dcache.write(r_dcache_miss_way.read(),
+                           r_dcache_miss_set.read(),
+                           r_dcache_miss_word.read(),
+                           r_vci_rsp_fifo_dcache.read());
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_MISS_DATA_UPDT> Write one word:"
-              << " / DATA = "  << std::hex << r_vci_rsp_fifo_dcache.read()
-              << " / WAY = "   << std::dec << r_dcache_miss_way.read()
-              << " / SET = "   << r_dcache_miss_set.read()
-              << " / WORD = "  << r_dcache_miss_word.read() << std::endl;
-}
+            if (m_debug_activated)
+            {
+                std::cout << "  <PROC " << name()
+                    << " DCACHE_MISS_DATA_UPDT> Write one word:"
+                    << " / DATA = "  << std::hex << r_vci_rsp_fifo_dcache.read()
+                    << " / WAY = "   << std::dec << r_dcache_miss_way.read()
+                    << " / SET = "   << r_dcache_miss_set.read()
+                    << " / WORD = "  << r_dcache_miss_word.read() << std::endl;
+            }
 #endif
             vci_rsp_fifo_dcache_get = true;
 
-            r_dcache_read_state = !r_vci_rsp_fifo_rpktid.read();//deduce the state (CC or NCC) from msb of pktid
+            r_dcache_read_state = not r_vci_rsp_fifo_rpktid.read(); //deduce the state (CC or NCC) from msb of pktid
             vci_rsp_fifo_rpktid_get = true;
 
-
             r_dcache_miss_word = r_dcache_miss_word.read() + 1;
 
-            if ( r_dcache_miss_word.read() == (m_dcache_words-1) ) // last word
+            if (r_dcache_miss_word.read() == (m_dcache_words - 1)) // last word
             {
                 r_dcache_fsm = DCACHE_MISS_DIR_UPDT;
@@ -4728 +4722 @@
                                 //   to ZOMBI state, and send a cleanup request.
     {
-        if ( m_dreq.valid) m_cost_data_miss_frz++;
-
-        if( r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read() )
-        {
-            r_dcache_cc_send_req = true;
-            r_dcache_cc_send_type = CC_TYPE_CLEANUP;
-            r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline.read();
+        if (m_dreq.valid) m_cost_data_miss_frz++;
+
+        // send cleanup victim request
+        if (r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read())
+        {
+            r_dcache_cc_send_req        = true;
+            r_dcache_cc_send_nline      = r_dcache_cleanup_victim_nline.read();
+            r_dcache_cc_send_way        = r_dcache_miss_way.read();
+            r_dcache_cc_send_type       = CC_TYPE_CLEANUP;
             r_dcache_cleanup_victim_req = false;
             r_dcache_cc_cleanup_updt_data = r_dcache_cleanup_victim_updt_data.read();
-            r_dcache_cc_cleanup_line_ncc = r_dcache_cleanup_victim_line_ncc.read();
-            r_dcache_cc_send_way = r_dcache_miss_way;
+            r_dcache_cc_cleanup_line_ncc  = r_dcache_cleanup_victim_line_ncc.read();
         }
 
         // coherence clack request (from DSPIN CLACK)
-        if ( r_dcache_clack_req.read() )
+        if (r_dcache_clack_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4750 +4745 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_cleanup_victim_req.read() )
+        if (r_cc_receive_dcache_req.read() and
+            not r_dcache_cc_send_req.read() and
+            not r_dcache_cleanup_victim_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4757 +4754 @@
         }
 
-        if ( not r_dcache_miss_clack.read() )  // waiting cleanup acknowledge
-        {
-            if ( r_dcache_miss_inval.read() ) // switch slot to ZOMBI state, and new cleanup
-            {
-                if ( not r_dcache_cc_send_req.read() ) // blocked until previous request sent
-                {
-                    r_dcache_miss_inval     = false;
+        if (not r_dcache_miss_clack.read())  // waiting cleanup acknowledge
+        {
+            if (r_dcache_miss_inval.read()) // switch slot to ZOMBI state, and new cleanup
+            {
+                if (not r_dcache_cc_send_req.read()) // blocked until previous request sent
+                {
+                    r_dcache_miss_inval    = false;
                     // request cleanup
                     r_dcache_cc_send_req   = true;
-                    r_dcache_cc_send_nline = r_dcache_save_paddr.read()/(m_dcache_words<<2);
+                    r_dcache_cc_send_nline = r_dcache_save_paddr.read() / (m_dcache_words << 2);
                     r_dcache_cc_send_way   = r_dcache_miss_way.read();
                     r_dcache_cc_send_type  = CC_TYPE_CLEANUP;
-                    r_dcache_cc_cleanup_updt_data = false; //the line is evicted at the very moment it arives, so it is not dirty
-                    r_dcache_cc_cleanup_line_ncc = !r_dcache_read_state.read();
+                    r_dcache_cc_cleanup_updt_data = false; // the line is evicted at the very moment it arives, so it is not dirty
+                    r_dcache_cc_cleanup_line_ncc  = !r_dcache_read_state.read();
 
 #ifdef INSTRUMENTATION
-m_cpt_dcache_dir_write++;
+                    m_cpt_dcache_dir_write++;
 #endif
                     r_dcache.write_dir( r_dcache_save_paddr.read(),
@@ -4780 +4777 @@
                                         CACHE_SLOT_STATE_ZOMBI );
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-std::cout << "  <PROC " << name()
-          << " DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state"
-          << " PADDR = " << std::hex << r_dcache_save_paddr.read()
-          << " / WAY = "   << std::dec << r_dcache_miss_way.read()
-          << " / SET = "   << r_dcache_miss_set.read() << std::endl;
+                    if (m_debug_activated)
+                        std::cout << "  <PROC " << name()
+                            << " DCACHE_MISS_DIR_UPDT> Switch slot to ZOMBI state"
+                            << " PADDR = " << std::hex << r_dcache_save_paddr.read()
+                            << " / WAY = "   << std::dec << r_dcache_miss_way.read()
+                            << " / SET = "   << r_dcache_miss_set.read() << std::endl;
 #endif
                 }
@@ -4795 +4792 @@
 
 #ifdef INSTRUMENTATION
-m_cpt_dcache_dir_write++;
-#endif
-
+                m_cpt_dcache_dir_write++;
+#endif
                 size_t way = r_dcache_miss_way.read();
                 size_t set = r_dcache_miss_set.read();
                 if (r_dcache_read_state.read())
                 {
-                    r_dcache.write_dir( r_dcache_save_paddr.read(),
-                                        r_dcache_miss_way.read(),
-                                        r_dcache_miss_set.read(),
-                                        CACHE_SLOT_STATE_VALID_CC );
-
-                    r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY;
-
+                    r_dcache.write_dir(r_dcache_save_paddr.read(),
+                                       r_dcache_miss_way.read(),
+                                       r_dcache_miss_set.read(),
+                                       CACHE_SLOT_STATE_VALID_CC);
+
+                    r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_NOT_DIRTY;
                 }
                 else
                 {
-                    r_dcache.write_dir( r_dcache_save_paddr.read(),
-                                        r_dcache_miss_way.read(),
-                                        r_dcache_miss_set.read(),
-                                        CACHE_SLOT_STATE_VALID_NCC );
-                    r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY;
-                    for (size_t word =0; word < m_dcache_words ; word++)
+                    r_dcache.write_dir(r_dcache_save_paddr.read(),
+                                       r_dcache_miss_way.read(),
+                                       r_dcache_miss_set.read(),
+                                       CACHE_SLOT_STATE_VALID_NCC);
+                    r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_NOT_DIRTY;
+                    for (size_t word = 0; word < m_dcache_words; word++)
                     {
-                        r_dcache_dirty_word[(way*m_dcache_sets +set)*m_dcache_words+word] = 0;
+                        r_dcache_dirty_word[(way * m_dcache_sets + set) * m_dcache_words + word] = 0;
                     }
 
                     // STAT : WRITE ON ZOMBI NCC LINE
-                    r_dcache_zombi_ncc[r_dcache_miss_way.read()*m_dcache_sets+r_dcache_miss_set.read()] = true;
+                    r_dcache_zombi_ncc[r_dcache_miss_way.read() * m_dcache_sets + r_dcache_miss_set.read()] = true;
                 }
 
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-std::cout << "  <PROC " << name()
-          << " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
-          << " PADDR = " << std::hex << r_dcache_save_paddr.read()
-          << " / WAY = "   << std::dec << r_dcache_miss_way.read()
-          << " / SET = "   << r_dcache_miss_set.read() << std::endl;
+                if (m_debug_activated)
+                    std::cout << "  <PROC " << name()
+                        << " DCACHE_MISS_DIR_UPDT> Switch slot to VALID state"
+                        << " PADDR = " << std::hex << r_dcache_save_paddr.read()
+                        << " / WAY = "   << std::dec << r_dcache_miss_way.read()
+                        << " / SET = "   << r_dcache_miss_set.read() << std::endl;
 #endif
             }
@@ -4842 +4837 @@
     }
     /////////////////////
-    case DCACHE_UNC_WAIT:  // waiting a response to an uncacheable read
+    case DCACHE_UNC_WAIT:  // waiting a response to an uncacheable read/write
     {
         // coherence clack request (from DSPIN CLACK)
-        if ( r_dcache_clack_req.read() )
+        if (r_dcache_clack_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4853 +4848 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
+        if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4860 +4855 @@
         }
 
-        if ( r_vci_rsp_data_error.read() )  // bus error
-        {
-            if(r_dcache_vci_unc_write.read())
-                r_mmu_detr           = MMU_WRITE_DATA_ILLEGAL_ACCESS;
+        if (r_vci_rsp_data_error.read()) // bus error
+        {
+            if (r_dcache_vci_unc_write.read())
+                r_mmu_detr = MMU_WRITE_DATA_ILLEGAL_ACCESS;
             else
-                r_mmu_detr           = MMU_READ_DATA_ILLEGAL_ACCESS;
+                r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS;
+
             r_mmu_dbvar          = m_dreq.addr;
             r_vci_rsp_data_error = false;
@@ -4873 +4869 @@
             break;
         }
-        else if ( r_vci_rsp_fifo_dcache.rok() )     // data available
+        else if (r_vci_rsp_fifo_dcache.rok())     // data available
         {
             // consume data
@@ -4880 +4876 @@
 
             // acknowledge the processor request if it has not been modified
-            if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
-            {
-                m_drsp.valid        = true;
-                m_drsp.error        = false;
-                m_drsp.rdata        = r_vci_rsp_fifo_dcache.read();
+            if (m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()))
+            {
+                m_drsp.valid = true;
+                m_drsp.error = false;
+                m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
             }
         }
@@ -4893 +4889 @@
     {
         // coherence clack request (from DSPIN CLACK)
-        if ( r_dcache_clack_req.read() )
+        if (r_dcache_clack_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4901 +4897 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
+        if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4908 +4904 @@
         }
 
-        if ( r_vci_rsp_data_error.read() )  // bus error
+        if (r_vci_rsp_data_error.read()) // bus error
         {
             r_mmu_detr           = MMU_READ_DATA_ILLEGAL_ACCESS;
@@ -4918 +4914 @@
             break;
         }
-        else if ( r_vci_rsp_fifo_dcache.rok() )     // data available
+        else if (r_vci_rsp_fifo_dcache.rok())     // data available
         {
             // consume data
             vci_rsp_fifo_dcache_get = true;
 
-            if(r_dcache_ll_rsp_count.read() == 0) // first flit
+            if (r_dcache_ll_rsp_count.read() == 0) // first flit
             {
                 // set key value in llsc reservation buffer
                 r_dcache_llsc_key     = r_vci_rsp_fifo_dcache.read();
-                r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1 ;
+                r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1;
             }
             else                                  // last flit
             {
                 // acknowledge the processor request if it has not been modified
-                if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) )
-                {
-                    m_drsp.valid        = true;
-                    m_drsp.error        = false;
-                    m_drsp.rdata        = r_vci_rsp_fifo_dcache.read();
+                if (m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()))
+                {
+                    m_drsp.valid = true;
+                    m_drsp.error = false;
+                    m_drsp.rdata = r_vci_rsp_fifo_dcache.read();
                 }
                 r_dcache_fsm = DCACHE_IDLE;
@@ -4944 +4940 @@
     }
     ////////////////////
-    case DCACHE_SC_WAIT:   // waiting VCI response to a SC transaction
+    case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction
     {
         // coherence clack request (from DSPIN CLACK)
-        if ( r_dcache_clack_req.read() )
+        if (r_dcache_clack_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4955 +4951 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
+        if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -4962 +4958 @@
         }
 
-        if ( r_vci_rsp_data_error.read() )     // bus error
+        if (r_vci_rsp_data_error.read()) // bus error
         {
             r_mmu_detr           = MMU_READ_DATA_ILLEGAL_ACCESS;
@@ -4972 +4968 @@
             break;
         }
-        else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
+        else if (r_vci_rsp_fifo_dcache.rok()) // response available
         {
             // consume response
@@ -4983 +4979 @@
     }
     //////////////////////////
-    case DCACHE_DIRTY_GET_PTE:      // This sub_fsm set the PTE Dirty bit in memory
-                                    // before handling a processor WRITE or SC request
-                                    // Input argument is r_dcache_dirty_paddr
-                                    // In this first state, we get PTE value in dcache
-                                    // and post a CAS request to CMD FSM
+    case DCACHE_DIRTY_GET_PTE:  // This sub_fsm set the PTE Dirty bit in memory
+                                // before handling a processor WRITE or SC request
+                                // Input argument is r_dcache_dirty_paddr
+                                // In this first state, we get PTE value in dcache
+                                // and post a CAS request to CMD FSM
     {
         // get PTE in dcache
@@ -4997 +4993 @@
 
 #ifdef INSTRUMENTATION
-m_cpt_dcache_data_read++;
-m_cpt_dcache_dir_read++;
-#endif
-        r_dcache.read( r_dcache_dirty_paddr.read(),
-                       &pte,
-                       &way,
-                       &set,
-                       &word,
-                       &state );
-
-        assert( (state == CACHE_SLOT_STATE_VALID_CC or state == CACHE_SLOT_STATE_VALID_NCC) and
+        m_cpt_dcache_data_read++;
+        m_cpt_dcache_dir_read++;
+#endif
+        r_dcache.read(r_dcache_dirty_paddr.read(),
+                      &pte,
+                      &way,
+                      &set,
+                      &word,
+                      &state);
+
+        assert((state == CACHE_SLOT_STATE_VALID_CC or state == CACHE_SLOT_STATE_VALID_NCC) and
         "error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" );
 
         // request CAS transaction to CMD_FSM
-        r_dcache_dirty_way  = way;
-        r_dcache_dirty_set  = set;
+        r_dcache_dirty_way = way;
+        r_dcache_dirty_set = set;
 
         // check llsc reservation buffer
-        if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read() )
+        if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read())
             r_dcache_llsc_valid = false;
 
@@ -5029 +5025 @@
         else
         {
-            r_cas_islocal = true;
-            r_cas_local_way = way;
-            r_cas_local_set = set;
-            r_cas_local_word = word;
+            r_cas_local_way      = way;
+            r_cas_local_set      = set;
+            r_cas_local_word     = word;
             r_dcache_vci_cas_new = pte | PTE_D_MASK;
-        }
-
-
-            r_dcache_fsm         = DCACHE_DIRTY_WAIT;
+            r_cas_islocal        = true;
+        }
+
+        r_dcache_fsm = DCACHE_DIRTY_WAIT;
 
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_DIRTY_GET_PTE> CAS request" << std::hex
-              << " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
-              << " / PTE_VALUE = " << pte << std::dec
-              << " / SET = " << set
-              << " / WAY = " << way << std::endl;
-}
+        if (m_debug_activated)
+        {
+            std::cout << "  <PROC " << name()
+                << " DCACHE_DIRTY_GET_PTE> CAS request" << std::hex
+                << " / PTE_PADDR = " << r_dcache_dirty_paddr.read()
+                << " / PTE_VALUE = " << pte << std::dec
+                << " / SET = " << set
+                << " / WAY = " << way << std::endl;
+        }
 #endif
         break;
     }
     ///////////////////////
-    case DCACHE_DIRTY_WAIT:         // wait completion of CAS for PTE Dirty bit,
-                                    // and return to IDLE state when response is received.
-                                    // we don't care if the CAS is a failure:
-                                    // - if the CAS is a success, the coherence mechanism
-                                    //   updates the local copy.
-                                    // - if the CAS is a failure, we just retry the write.
+    case DCACHE_DIRTY_WAIT:    // wait completion of CAS for PTE Dirty bit,
+                               // and return to IDLE state when response is received.
+                               // we don't care if the CAS is a failure:
+                               // - if the CAS is a success, the coherence mechanism
+                               //   updates the local copy.
+                               // - if the CAS is a failure, we just retry the write.
     {
         uint32_t way  = r_cas_local_way.read();
@@ -5066 +5061 @@
 
         // coherence clack request (from DSPIN CLACK)
-        if ( r_dcache_clack_req.read() )
+        if (r_dcache_clack_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -5074 +5069 @@
 
         // coherence request (from CC_RECEIVE FSM)
-        if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
+        if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read())
         {
             r_dcache_fsm = DCACHE_CC_CHECK;
@@ -5081 +5076 @@
         }
 
-        if (!r_cas_islocal.read())
-        {
-            if ( r_vci_rsp_data_error.read() )  // bus error
+        if (not r_cas_islocal.read())
+        {
+            if (r_vci_rsp_data_error.read())  // bus error
             {
                 std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl;
@@ -5089 +5084 @@
                 exit(0);
             }
-            else if ( r_vci_rsp_fifo_dcache.rok() ) // response available
+            else if (r_vci_rsp_fifo_dcache.rok()) // response available
             {
                 vci_rsp_fifo_dcache_get = true;
-                r_dcache_fsm            = DCACHE_IDLE;
+                r_dcache_fsm = DCACHE_IDLE;
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_DIRTY_WAIT> CAS completed" << std::endl;
-}
+                if (m_debug_activated)
+                {
+                    std::cout << "  <PROC " << name()
+                        << " DCACHE_DIRTY_WAIT> CAS completed" << std::endl;
+                }
 #endif
             }
@@ -5109 +5104 @@
                            r_dcache_vci_cas_new.read());
 
-            if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB )
-            {
-                r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
+            if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_IN_TLB)
+            {
+                r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_DIRTY;
                 r_dcache_tlb_inval_line  = nline;
                 r_dcache_tlb_inval_set   = 0;
@@ -5119 +5114 @@
             }
 
-            if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD )
+            if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_CONTAINS_PTD)
             {
                 r_itlb.reset();
                 r_dtlb.reset();
-                r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY;
+                r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_DIRTY;
 
 #if DEBUG_DCACHE
-                if ( m_debug_activated )
+                if (m_debug_activated)
                 {
                     std::cout << "  <PROC " << name()
@@ -5133 +5128 @@
 #endif
             }
-            r_dcache_fsm            = DCACHE_IDLE;
+            r_dcache_fsm = DCACHE_IDLE;
         }
         break;
@@ -5146 +5141 @@
                             // The return state is defined in r_dcache_fsm_cc_save
     {
-        paddr_t  paddr = r_cc_receive_dcache_nline.read() * m_dcache_words * 4;
-        paddr_t  mask = ~((m_dcache_words<<2)-1);
-
-//#if DEBUG_DCACHE
-//if ( m_debug_activated )
-//{
-//    std::cout << "  <PROC " << name() << std::hex
-//              << " DCACHE_CC_CHECK> paddr = " << paddr
-//              << " r_dcache_vci_paddr = " << r_dcache_vci_paddr.read()
-//              << " mask = " << mask
-//              << " (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = "
-//              << (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT)
-//              << " (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = "
-//              << (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)
-//              << " ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = "
-//              << ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))
-//              << std::dec <<std::endl;
-//}
-//#endif
+        paddr_t paddr = r_cc_receive_dcache_nline.read() * m_dcache_words * 4;
+        paddr_t mask = ~((m_dcache_words << 2) - 1);
+
         // CLACK handler
         // We switch the directory slot to EMPTY state and reset
         // r_dcache_miss_clack if the cleanup ack is matching a pending miss.
-        if ( r_dcache_clack_req.read() )
-        {
-            if ( m_dreq.valid ) m_cost_data_miss_frz++;
+        if (r_dcache_clack_req.read())
+        {
+            if (m_dreq.valid) m_cost_data_miss_frz++;
 
 #ifdef INSTRUMENTATION
-m_cpt_dcache_dir_write++;
-#endif
-            r_dcache.write_dir( 0,
-                                r_dcache_clack_way.read(),
-                                r_dcache_clack_set.read(),
-                                CACHE_SLOT_STATE_EMPTY);
+            m_cpt_dcache_dir_write++;
+#endif
+            r_dcache.write_dir(0,
+                               r_dcache_clack_way.read(),
+                               r_dcache_clack_set.read(),
+                               CACHE_SLOT_STATE_EMPTY);
 
             // STAT : WRITE ON ZOMBI NCC LINE
-            r_dcache_zombi_ncc[r_dcache_clack_way.read()*m_dcache_sets+r_dcache_clack_set.read()] = false;
-
-            if ( (r_dcache_miss_set.read() == r_dcache_clack_set.read()) and
-                 (r_dcache_miss_way.read() == r_dcache_clack_way.read()) )
+            r_dcache_zombi_ncc[r_dcache_clack_way.read() * m_dcache_sets + r_dcache_clack_set.read()] = false;
+
+            if ((r_dcache_miss_set.read() == r_dcache_clack_set.read()) and
+                (r_dcache_miss_way.read() == r_dcache_clack_way.read()))
             {
                   r_dcache_miss_clack = false;
@@ -5195 +5174 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_CC_CHECK> CC_TYPE_CLACK Switch slot to EMPTY state"
-              << " set = " << r_dcache_clack_set.read()
-              << " / way = " << r_dcache_clack_way.read() << std::endl;
-}
-#endif
-            break;
-        }
-
+            if (m_debug_activated)
+            {
+                std::cout << "  <PROC " << name()
+                    << " DCACHE_CC_CHECK> CLACK for PADDR " << std::hex << paddr
+                    << " Switch slot to EMPTY state : "
+                    << " set = " << std::dec << r_dcache_clack_set.read()
+                    << " / way = " << r_dcache_clack_way.read() << std::endl;
+            }
+#endif
+            break;
+        }
+
+        assert(not r_dcache_cc_send_req.read() and
+        "CC_SEND must be available in DCACHE_CC_CHECK");
 
         // Match between MISS address and CC address
@@ -5211 +5193 @@
         // because the CLACK access the directory but the MISS match dont.
         if (r_cc_receive_dcache_req.read() and
-          ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT  )  or
-           (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT    )  or
+          ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT)  or
+           (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT)  or
            (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and
           ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))) // matching
@@ -5223 +5205 @@
             if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
             {
-                r_dcache_fsm        = DCACHE_CC_UPDT;
-                r_dcache_cc_word    = r_cc_receive_word_idx.read();
+                r_dcache_fsm     = DCACHE_CC_UPDT;
+                r_dcache_cc_word = r_cc_receive_word_idx.read();
 
                 // just pop the fifo , don't write in icache
@@ -5237 +5219 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_CC_CHECK> Coherence request matching a pending miss:"
-              << " PADDR = " << std::hex << paddr << std::endl;
-}
-#endif
-        }
-
-
-        assert ( not r_dcache_cc_send_req.read() and "CC_SEND must be available in DCACHE_CC_CHECK" );
+            if (m_debug_activated)
+            {
+                std::cout << "  <PROC " << name()
+                    << " DCACHE_CC_CHECK> Coherence request matching a pending miss:"
+                    << " PADDR = " << std::hex << paddr << std::endl;
+            }
+#endif
+        }
 
         // CC request handler
@@ -5257 +5236 @@
 
 #ifdef INSTRUMENTATION
-m_cpt_dcache_dir_read++;
-#endif
-        r_dcache.read_dir( paddr,
-                           &state,
-                           &way,
-                           &set,
-                           &word ); // unused
+        m_cpt_dcache_dir_read++;
+#endif
+        r_dcache.read_dir(paddr,
+                          &state,
+                          &way,
+                          &set,
+                          &word); // unused
 
         r_dcache_cc_state = state;
@@ -5269 +5248 @@
         r_dcache_cc_set = set;
 
-        if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC))  // hit
+        if ((state == CACHE_SLOT_STATE_VALID_CC) or
+            (state == CACHE_SLOT_STATE_VALID_NCC))  // hit
         {
             // need to update the cache state
@@ -5276 +5256 @@
             if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)  // hit update
             {
-                r_dcache_fsm          = DCACHE_CC_UPDT;
-                r_dcache_cc_word      = r_cc_receive_word_idx.read();
+                r_dcache_fsm     = DCACHE_CC_UPDT;
+                r_dcache_cc_word = r_cc_receive_word_idx.read();
             }
             else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL)   // hit inval
@@ -5283 +5263 @@
                 if (state == CACHE_SLOT_STATE_VALID_NCC)
                 {
-                    r_dcache_cc_inval_addr = (paddr &~0x3F);
+                    r_dcache_cc_inval_addr = (paddr & ~0x3F);
                     r_dcache_cc_inval_data_cpt = 0;
                 }
-                r_dcache_fsm          = DCACHE_CC_INVAL;
-                r_dcache_dirty_save   = false;
+                r_dcache_fsm        = DCACHE_CC_INVAL;
+                r_dcache_dirty_save = false;
             }
         }
@@ -5293 +5273 @@
         {
             // multicast acknowledgement required in case of update
-            if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
-            {
-                r_dcache_fsm           = DCACHE_CC_UPDT;
-                r_dcache_cc_word       = r_cc_receive_word_idx.read();
+            if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT)
+            {
+                r_dcache_fsm     = DCACHE_CC_UPDT;
+                r_dcache_cc_word = r_cc_receive_word_idx.read();
 
                 // just pop the fifo , don't write in icache
@@ -5309 +5289 @@
 
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_CC_CHECK> Coherence request received:"
-              << " PADDR = " << std::hex << paddr
-              << " / TYPE = " << std::dec << r_cc_receive_dcache_type.read()
-              << " / HIT = " << ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC)) << std::endl;
-}
+        if (m_debug_activated)
+        {
+            std::cout << "  <PROC " << name()
+                << " DCACHE_CC_CHECK> Coherence request received:"
+                << " PADDR = " << std::hex << paddr
+                << " / TYPE = " << std::dec << r_cc_receive_dcache_type.read()
+                << " / HIT = " << ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC)) << std::endl;
+        }
 #endif
 
         break;
     }
-
     /////////////////////
     case DCACHE_CC_INVAL: // hit inval: switch slot to ZOMBI state and send a
@@ -5327 +5306 @@
                           // TLBs
     {
-        size_t way    = r_dcache_cc_way.read();
-        size_t set    = r_dcache_cc_set.read();
-        int      cache_state = r_dcache_cc_state.read();
-        bool     dirty_save = false;
+        size_t way = r_dcache_cc_way.read();
+        size_t set = r_dcache_cc_set.read();
+        int  cache_state = r_dcache_cc_state.read();
+        bool dirty_save = false;
 
         if (r_dcache_cc_need_write.read())
         {
-            if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB )
-            {
-                r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY;//need to remember it was dirty for cleanup
+            if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_IN_TLB)
+            {
+                r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_NOT_DIRTY; //need to remember it was dirty for cleanup
                 dirty_save = true;
                 r_dcache_dirty_save = true;
-                r_dcache_tlb_inval_line  = r_cc_receive_dcache_nline.read();
-                r_dcache_tlb_inval_set   = 0;
-                r_dcache_fsm_scan_save   = r_dcache_fsm.read();
-                r_dcache_fsm             = DCACHE_INVAL_TLB_SCAN;
+                r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
+                r_dcache_tlb_inval_set  = 0;
+                r_dcache_fsm_scan_save  = r_dcache_fsm.read();
+                r_dcache_fsm = DCACHE_INVAL_TLB_SCAN;
                 break;
             }
             else
             {
-                if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD )
+                if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_CONTAINS_PTD)
                 {
                     r_itlb.reset();
                     r_dtlb.reset();
-                    r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY;
+                    r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_NOT_DIRTY;
                     dirty_save = true;
                     r_dcache_dirty_save = true;
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl;
-}
+                    if (m_debug_activated)
+                    {
+                        std::cout << "  <PROC " << name()
+                            << " DCACHE_CC_INVAL> Flush DTLB & ITLB" << std::endl;
+                    }
 #endif
                 }
@@ -5365 +5344 @@
                 // If the type of inval request from Memcache is configuration
                 // (software), we send a classic CLEANUP
-                if (cache_state == CACHE_SLOT_STATE_VALID_CC or r_cc_receive_dcache_inval_is_config.read())
-                {
-                    r_dcache.write_dir( way,
-                                        set,
-                                        CACHE_SLOT_STATE_ZOMBI );
-                }
-
+                if (cache_state == CACHE_SLOT_STATE_VALID_CC or
+                    r_cc_receive_dcache_inval_is_config.read())
+                {
+                    r_dcache.write_dir(way,
+                                       set,
+                                       CACHE_SLOT_STATE_ZOMBI);
+                }
                 r_dcache_cc_need_write = false;
             }
         }
-        assert (not r_dcache_cc_send_req.read() &&
-                    "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "
-                    "must not be set");
+        assert(not r_dcache_cc_send_req.read() and
+               "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "
+               "must not be set");
         // coherence request completed
         r_cc_receive_dcache_req = false;
@@ -5386 +5365 @@
         r_dcache_cc_send_type = CC_TYPE_CLEANUP;
 
-        if (cache_state == CACHE_SLOT_STATE_VALID_NCC and not r_cc_receive_dcache_inval_is_config.read())
+        if (cache_state == CACHE_SLOT_STATE_VALID_NCC and
+            not r_cc_receive_dcache_inval_is_config.read())
         {
             r_dcache_cc_cleanup_line_ncc = true;
-            if ((r_dcache_content_state[way*m_dcache_sets+set] != LINE_CACHE_DATA_NOT_DIRTY) or r_dcache_dirty_save.read() or dirty_save) //must send data
+            if ((r_dcache_content_state[way * m_dcache_sets + set] != LINE_CACHE_DATA_NOT_DIRTY) or
+                 r_dcache_dirty_save.read() or
+                 dirty_save) //must send data
             {
                 r_dcache_cc_cleanup_updt_data = true;
-                for (size_t w = 0; w< m_dcache_words; w++)
-                {
-                    m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets*way+set)*m_dcache_words + w];
-                }
-
-                r_dcache_fsm          = DCACHE_CC_INVAL_DATA;
+                for (size_t w = 0; w < m_dcache_words; w++)
+                {
+                    m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets * way + set) * m_dcache_words + w];
+                }
+
+                r_dcache_fsm = DCACHE_CC_INVAL_DATA;
             }
             else
             {
-                r_dcache.write_dir( way,
-                                    set,
-                                    CACHE_SLOT_STATE_ZOMBI );
+                r_dcache.write_dir(way,
+                                   set,
+                                   CACHE_SLOT_STATE_ZOMBI);
 
                 r_dcache_cc_cleanup_updt_data = false;
@@ -5417 +5399 @@
         break;
     }
-
     /////////////////////
     case DCACHE_CC_INVAL_DATA:
@@ -5423 +5404 @@
 
         uint32_t rdata;
-        size_t   way = 0; // to avoid gcc warning
-        size_t   set = 0; // to avoid gcc warning
-        size_t   word;
+        size_t way = 0; // to avoid gcc warning
+        size_t set = 0; // to avoid gcc warning
+        size_t word;
         r_dcache.read_neutral(r_dcache_cc_inval_addr.read(),
                               &rdata,
@@ -5431 +5412 @@
                               &set,
                               &word);
-        if(r_cc_send_data_fifo.wok())
+        if (r_cc_send_data_fifo.wok())
         {
             r_dcache_cc_inval_addr = r_dcache_cc_inval_addr.read() + 4;
 
-            cleanup_data_updt_fifo_dcache_put   = true;
-            cleanup_data_updt_fifo_dcache_data  = rdata;
+            cleanup_data_updt_fifo_dcache_put = true;
+            cleanup_data_updt_fifo_dcache_data = rdata;
 
             r_dcache_cc_inval_data_cpt = r_dcache_cc_inval_data_cpt.read() + 1;
-            if(r_dcache_cc_inval_data_cpt.read() == (m_dcache_words - 1))
+            if (r_dcache_cc_inval_data_cpt.read() == (m_dcache_words - 1))
             {
                 r_dcache_cc_inval_data_cpt = 0;
-                r_dcache_fsm          = r_dcache_fsm_cc_save.read();
+                r_dcache_fsm = r_dcache_fsm_cc_save.read();
                 r_dcache.write_dir(way,
                                    set,
-                                   CACHE_SLOT_STATE_ZOMBI );
+                                   CACHE_SLOT_STATE_ZOMBI);
             }
         }
@@ -5451 +5432 @@
     }
     ///////////////////
-    case DCACHE_CC_UPDT:        // hit update: write one word per cycle,
-                                // after possible invalidation of copies in TLBs
-    {
-        size_t word       = r_dcache_cc_word.read();
-        size_t way        = r_dcache_cc_way.read();
-        size_t set        = r_dcache_cc_set.read();
-
-            if (r_dcache_cc_need_write.read())
-            {
-                if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB )
-                {
-                    r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY;
-                    r_dcache_tlb_inval_line  = r_cc_receive_dcache_nline.read();
-                    r_dcache_tlb_inval_set   = 0;
-                    r_dcache_fsm_scan_save   = r_dcache_fsm.read();
-                    r_dcache_fsm             = DCACHE_INVAL_TLB_SCAN;
-                    break;
-                }
-                if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD )
-                {
-                    r_itlb.reset();
-                    r_dtlb.reset();
-                    r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY;
+    case DCACHE_CC_UPDT: // hit update: write one word per cycle,
+                         // after possible invalidation of copies in TLBs
+    {
+        size_t word = r_dcache_cc_word.read();
+        size_t way  = r_dcache_cc_way.read();
+        size_t set  = r_dcache_cc_set.read();
+
+        if (r_dcache_cc_need_write.read())
+        {
+            if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_IN_TLB)
+            {
+                r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_NOT_DIRTY;
+                r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read();
+                r_dcache_tlb_inval_set  = 0;
+                r_dcache_fsm_scan_save  = r_dcache_fsm.read();
+                r_dcache_fsm            = DCACHE_INVAL_TLB_SCAN;
+                break;
+            }
+            if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_CONTAINS_PTD)
+            {
+                r_itlb.reset();
+                r_dtlb.reset();
+                r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_NOT_DIRTY;
 
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_CC_UPDT> Flush DTLB & ITLB" << std::endl;
-}
-#endif
-                }
-
-                assert (not r_dcache_cc_send_req.read() &&
-                        "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "
-                        "must not be set");
-
-                if ( not r_cc_receive_updt_fifo_be.rok() ) break;
+                if (m_debug_activated)
+                {
+                    std::cout << "  <PROC " << name()
+                        << " DCACHE_CC_UPDT> Flush DTLB & ITLB" << std::endl;
+                }
+#endif
+            }
+
+            assert(not r_dcache_cc_send_req.read() &&
+                   "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req "
+                   "must not be set");
+
+            if (not r_cc_receive_updt_fifo_be.rok()) break;
 
 #ifdef INSTRUMENTATION
-m_cpt_dcache_data_write++;
-#endif
-            r_dcache.write( way,
-                            set,
-                            word,
-                            r_cc_receive_updt_fifo_data.read(),
-                            r_cc_receive_updt_fifo_be.read() );
+            m_cpt_dcache_data_write++;
+#endif
+            r_dcache.write(way,
+                           set,
+                           word,
+                           r_cc_receive_updt_fifo_data.read(),
+                           r_cc_receive_updt_fifo_be.read());
 
             r_dcache_cc_word = word + 1;
 
 #if DEBUG_DCACHE
-if ( m_debug_activated )
-{
-    std::cout << "  <PROC " << name()
-              << " DCACHE_CC_UPDT> Write one word" << std::dec
-              << " / WAY = " << way
-              << " / SET = " << set
-              << " / WORD = " << word
-              << " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl;
-}
-#endif
-        }
-
-        if ( not r_cc_receive_updt_fifo_be.rok() ) break;
-
-        if ( r_cc_receive_updt_fifo_eop.read() )  // last word
+            if (m_debug_activated)
+            {
+                std::cout << "  <PROC " << name()
+                    << " DCACHE_CC_UPDT> Write one word" << std::dec
+                    << " / WAY = " << way
+                    << " / SET = " << set
+                    << " / WORD = " << word
+                    << " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl;
+            }
+#endif
+        }
+
+        if (not r_cc_receive_updt_fifo_be.rok()) break;
+
+        if (r_cc_receive_updt_fifo_eop.read())  // last word
         {
             // no need to write in the cache anymore
@@ -5528 +5509 @@
             r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read();
             r_dcache_cc_send_type         = CC_TYPE_MULTI_ACK;
-
             r_dcache_fsm                  = r_dcache_fsm_cc_save.read();
         }
@@ -5538 +5518 @@
     }
     ///////////////////////////
-    case DCACHE_INVAL_TLB_SCAN:         // Scan sequencially all sets for both ITLB & DTLB
-                                        // It makes assumption: m_itlb_sets == m_dtlb_sets
-                                        // All ways are handled in parallel.
-                                        // We enter this state when a DCACHE line is modified,
-                                        // and there is a copy in itlb or dtlb.
-                                        // It can be caused by:
-                                        // - a coherence inval or updt transaction,
-                                        // - a line inval caused by a cache miss
-                                        // - a processor XTN inval request,
-                                        // - a WRITE hit,
-                                        // - a Dirty bit update
-                                        // Input arguments are:
-                                        // - r_dcache_tlb_inval_line
-                                        // - r_dcache_tlb_inval_set
-                                        // - r_dcache_fsm_scan_save
+    case DCACHE_INVAL_TLB_SCAN:  // Scan sequencially all sets for both ITLB & DTLB
+                                 // It makes assumption: m_itlb_sets == m_dtlb_sets
+                                 // All ways are handled in parallel.
+                                 // We enter this state when a DCACHE line is modified,
+                                 // and there is a copy in itlb or dtlb.
+                                 // It can be caused by:
+                                 // - a coherence inval or updt transaction,
+                                 // - a line inval caused by a cache miss
+                                 // - a processor XTN inval request,
+                                 // - a WRITE hit,
+                                 // - a Dirty bit update
+                                 // Input arguments are:
+                                 // - r_dcache_tlb_inval_line
+                                 // - r_dcache_tlb_inval_set
+                                 // - r_dcache_fsm_scan_save
     {
         paddr_t line = r_dcache_tlb_inval_line.read();
-        size_t  set  = r_dcache_tlb_inval_set.read();
-        size_t  way;
-        bool    ok;
-
-        for ( way = 0 ; way < m_itlb_ways ; way++ )
-        {
-            ok = r_itlb.inval( line, way, set );
+        size_t set = r_dcache_tlb_inval_set.read();
+        size_t way;
+        bool ok;
+
+        for (way = 0; way < m_itlb_ways; way++)
+        {
+            ok = r_itlb.inval(line, way, set);
 
 #if DEBUG_DCACHE
-if ( m_debug_activated and ok )
-{
-    std::cout << "  <PROC " << name()
-              << ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
-              << " line = " << line << std::dec
-              << " / set = " << set
-              << " / way = " << way << std::endl;
-}
-#endif
-        }
-
-        for ( way = 0 ; way < m_dtlb_ways ; way++ )
-        {
-            ok = r_dtlb.inval( line, way, set );
+            if (m_debug_activated and ok)
+            {
+                std::cout << "  <PROC " << name()
+                    << ".DCACHE_INVAL_TLB_SCAN> Invalidate ITLB entry:" << std::hex
+                    << " line = " << line << std::dec
+                    << " / set = " << set
+                    << " / way = " << way << std::endl;
+            }
+#endif
+        }
+
+        for (way = 0; way < m_dtlb_ways; way++)
+        {
+            ok = r_dtlb.inval(line, way, set);
 
 #if DEBUG_DCACHE
-if ( m_debug_activated and ok )
-std::cout << "  <PROC " << name() << " DCACHE_INVAL_TLB_SCAN>"
-          << " Invalidate DTLB entry" << std::hex
-          << " / line = " << line << std::dec
-          << " / set = " << set
-          << " / way = " << way << std::endl;
+            if (m_debug_activated and ok)
+            {
+                std::cout << "  <PROC " << name() << " DCACHE_INVAL_TLB_SCAN>"
+                    << " Invalidate DTLB entry" << std::hex
+                    << " / line = " << line << std::dec
+                    << " / set = " << set
+                    << " / way = " << way << std::endl;
+            }
 #endif
         }
 
         // return to the calling state when TLB inval completed
-        if ( r_dcache_tlb_inval_set.read() == (m_dtlb_sets-1) )
+        if (r_dcache_tlb_inval_set.read() == (m_dtlb_sets - 1))
         {
             r_dcache_fsm = r_dcache_fsm_scan_save.read();
@@ -5609 +5591 @@
     // The simulation exit if the number of consecutive frozen cycles
     // is larger than the m_max_frozen_cycles (constructor parameter)
-    if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) )
-    {
-        m_cpt_frz_cycles++;         // used for instrumentation
-        m_cpt_stop_simulation++;    // used for debug
-        if ( m_cpt_stop_simulation > m_max_frozen_cycles )
+    if ((m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid))
+    {
+        m_cpt_frz_cycles++;      // used for instrumentation
+        m_cpt_stop_simulation++; // used for debug
+        if (m_cpt_stop_simulation > m_max_frozen_cycles)
         {
             std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl
@@ -5630 +5612 @@
     /////////// execute one iss cycle /////////////////////////////////
     {
-    uint32_t it = 0;
-    for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it |= (1<<i);
-    r_iss.executeNCycles(1, m_irsp, m_drsp, it);
+        uint32_t it = 0;
+        for (size_t i = 0; i < (size_t) iss_t::n_irq; i++) if (p_irq[i].read()) it |= (1 << i);
+        r_iss.executeNCycles(1, m_irsp, m_drsp, it);
     }
 
@@ -5676 +5658 @@
 
 
-    switch ( r_vci_cmd_fsm.read() )
+    switch (r_vci_cmd_fsm.read())
     {
         //////////////
@@ -5688 +5670 @@
             // using the r_vci_cmd_imiss_prio flip-flop.
 
-            size_t      wbuf_min;
-            size_t      wbuf_max;
+            size_t wbuf_min;
+            size_t wbuf_max;
 
             bool dcache_miss_req = r_dcache_vci_miss_req.read() and
-                 ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
-
-            bool dcache_ll_req   = r_dcache_vci_ll_req.read() and
-                 ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
-
-            bool dcache_sc_req   = r_dcache_vci_sc_req.read() and
-                 ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
-
-            bool dcache_cas_req   = r_dcache_vci_cas_req.read() and
-                 ( not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read() );
+                 (not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
+
+            bool dcache_ll_req = r_dcache_vci_ll_req.read() and
+                 (not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
+
+            bool dcache_sc_req = r_dcache_vci_sc_req.read() and
+                 (not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
+
+            bool dcache_cas_req = r_dcache_vci_cas_req.read() and
+                 (not r_icache_miss_req.read() or not r_vci_cmd_imiss_prio.read());
 
             bool icache_miss_req = r_icache_miss_req.read() and
-                 ( not (r_dcache_vci_miss_req.read() or
-                        r_dcache_vci_ll_req.read()   or
-                        r_dcache_vci_cas_req.read()  or
-                        r_dcache_vci_sc_req.read())
-                     or r_vci_cmd_imiss_prio.read() );
+                 (not (r_dcache_vci_miss_req.read() or
+                       r_dcache_vci_ll_req.read()   or
+                       r_dcache_vci_cas_req.read()  or
+                       r_dcache_vci_sc_req.read())  or
+                       r_vci_cmd_imiss_prio.read());
 
             // 1 - Data unc write
-            if ( r_dcache_vci_unc_req.read() and r_dcache_vci_unc_write.read())
+            if (r_dcache_vci_unc_req.read() and r_dcache_vci_unc_write.read())
             {
                 r_vci_cmd_fsm        = CMD_DATA_UNC_WRITE;
                 r_dcache_vci_unc_req = false;
-//                m_cpt_dunc_transaction++;
             }
             // 2 data read miss
-            else if ( dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
+            else if (dcache_miss_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
             {
                 r_vci_cmd_fsm         = CMD_DATA_MISS;
                 r_dcache_vci_miss_req = false;
                 r_vci_cmd_imiss_prio  = true;
-                m_cpt_dmiss_transaction++;
             }
             // 3 - Data Read Uncachable
-            else if ( r_dcache_vci_unc_req.read() and not r_dcache_vci_unc_write.read() )
+            else if (r_dcache_vci_unc_req.read() and not r_dcache_vci_unc_write.read())
             {
                 r_vci_cmd_fsm        = CMD_DATA_UNC_READ;
                 r_dcache_vci_unc_req = false;
-                m_cpt_dunc_transaction++;
             }
             // 4 - Data Linked Load
-            else if ( dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
+            else if (dcache_ll_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
             {
                 r_vci_cmd_fsm         = CMD_DATA_LL;
                 r_dcache_vci_ll_req   = false;
                 r_vci_cmd_imiss_prio  = true;
-                m_cpt_ll_transaction++;
             }
             // 5 - Instruction Miss
-            else if ( icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()) )
+            else if (icache_miss_req and r_wbuf.miss(r_icache_vci_paddr.read()))
             {
                 r_vci_cmd_fsm        = CMD_INS_MISS;
                 r_icache_miss_req    = false;
                 r_vci_cmd_imiss_prio = false;
-                m_cpt_imiss_transaction++;
             }
             // 6 - Instruction Uncachable
-            else if ( r_icache_unc_req.read() )
-            {
-                r_vci_cmd_fsm       = CMD_INS_UNC;
-                r_icache_unc_req    = false;
-                //m_cpt_iunc_transaction++;
+            else if (r_icache_unc_req.read())
+            {
+                r_vci_cmd_fsm    = CMD_INS_UNC;
+                r_icache_unc_req = false;
             }
             // 7 - Data Write
-            else if ( r_wbuf.rok(&wbuf_min, &wbuf_max) )
-            {
-                r_vci_cmd_fsm       = CMD_DATA_WRITE;
-                r_vci_cmd_cpt       = wbuf_min;
-                r_vci_cmd_min       = wbuf_min;
-                r_vci_cmd_max       = wbuf_max;
+            else if (r_wbuf.rok(&wbuf_min, &wbuf_max))
+            {
+                r_vci_cmd_fsm = CMD_DATA_WRITE;
+                r_vci_cmd_cpt = wbuf_min;
+                r_vci_cmd_min = wbuf_min;
+                r_vci_cmd_max = wbuf_max;
                 m_cpt_write_transaction++;
-                m_length_write_transaction += (wbuf_max-wbuf_min+1);
+                m_length_write_transaction += (wbuf_max - wbuf_min + 1);
             }
             // 8 - Data Store Conditionnal
-            else if ( dcache_sc_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
-            {
-                r_vci_cmd_fsm           = CMD_DATA_SC;
-                r_dcache_vci_sc_req     = false;
-                r_vci_cmd_imiss_prio    = true;
-                r_vci_cmd_cpt           = 0;
-                //m_cpt_sc_transaction++;
+            else if (dcache_sc_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
+            {
+                r_vci_cmd_fsm        = CMD_DATA_SC;
+                r_dcache_vci_sc_req  = false;
+                r_vci_cmd_imiss_prio = true;
+                r_vci_cmd_cpt        = 0;
             }
             // 9 - Compare And Swap
-            else if ( dcache_cas_req and r_wbuf.miss(r_dcache_vci_paddr.read()) )
-            {
-                r_vci_cmd_fsm           = CMD_DATA_CAS;
-                r_dcache_vci_cas_req    = false;
-                r_vci_cmd_imiss_prio    = true;
-                r_vci_cmd_cpt           = 0;
-                //m_cpt_cas_transaction++;
+            else if (dcache_cas_req and r_wbuf.miss(r_dcache_vci_paddr.read()))
+            {
+                r_vci_cmd_fsm        = CMD_DATA_CAS;
+                r_dcache_vci_cas_req = false;
+                r_vci_cmd_imiss_prio = true;
+                r_vci_cmd_cpt        = 0;
             }
 
 #if DEBUG_CMD
-if ( m_debug_activated )
-{
-std::cout << "  <PROC " << name() << " CMD_IDLE>"
-          << " / dmiss_req = " << dcache_miss_req
-          << " / imiss_req = " << icache_miss_req
-          << std::endl;
-}
+            if (m_debug_activated)
+            {
+                std::cout << "  <PROC " << name() << " CMD_IDLE>"
+                    << " / dmiss_req = " << dcache_miss_req
+                    << " / imiss_req = " << icache_miss_req
+                    << std::endl;
+            }
 #endif
             break;
@@ -5798 +5772 @@
         case CMD_DATA_WRITE:
         {
-            if ( p_vci.cmdack.read() )
+            if (p_vci.cmdack.read())
             {
                 r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
                 if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent
                 {
-                    r_vci_cmd_fsm = CMD_IDLE ;
-                    r_wbuf.sent() ;
+                    r_vci_cmd_fsm = CMD_IDLE;
+                    r_wbuf.sent();
                 }
             }
@@ -5814 +5788 @@
         {
             // The CAS and SC VCI commands contain two flits
-            if ( p_vci.cmdack.read() )
+            if (p_vci.cmdack.read())
             {
                r_vci_cmd_cpt = r_vci_cmd_cpt + 1;
@@ -5830 +5804 @@
         {
             // all read VCI commands contain one single flit
-            if ( p_vci.cmdack.read() ) {
+            if (p_vci.cmdack.read()) {
                 r_vci_cmd_fsm = CMD_IDLE;
             }
@@ -5865 +5839 @@
     //////////////////////////////////////////////////////////////////////////
 
-    switch ( r_vci_rsp_fsm.read() )
+    switch (r_vci_rsp_fsm.read())
     {
     //////////////
     case RSP_IDLE:
     {
-        if ( p_vci.rspval.read() )
+        if (p_vci.rspval.read())
         {
             r_vci_rsp_cpt = 0;
-            if (r_dcache_vci_paddr.read() == 0x1f624) std::cout << "Tansaction on barrier, pktid = " <<  p_vci.rpktid.read() << std::endl;
-            if      ( (p_vci.rpktid.read() & 0x7) ==  TYPE_DATA_UNC  )
+
+            if ((p_vci.rpktid.read() & 0x7) ==  TYPE_DATA_UNC)
             {
                 r_vci_rsp_fsm = RSP_DATA_UNC;
             }
-            else if ( (p_vci.rpktid.read() & 0x7) ==  TYPE_READ_DATA_MISS )
+            else if ((p_vci.rpktid.read() & 0x7) ==  TYPE_READ_DATA_MISS)
             {
                 r_vci_rsp_fsm = RSP_DATA_MISS;
             }
-            else if ( (p_vci.rpktid.read() & 0x7) ==  TYPE_READ_INS_UNC   )
+            else if ((p_vci.rpktid.read() & 0x7) ==  TYPE_READ_INS_UNC)
             {
                 r_vci_rsp_fsm = RSP_INS_UNC;
             }
-            else if ( (p_vci.rpktid.read() & 0x7) ==  TYPE_READ_INS_MISS  )
+            else if ((p_vci.rpktid.read() & 0x7) ==  TYPE_READ_INS_MISS)
             {
                 r_vci_rsp_fsm = RSP_INS_MISS;
             }
-            else if ( (p_vci.rpktid.read() & 0x7) ==  TYPE_WRITE          )
+            else if ((p_vci.rpktid.read() & 0x7) ==  TYPE_WRITE)
             {
                 r_vci_rsp_fsm = RSP_DATA_WRITE;
             }
-            else if ( (p_vci.rpktid.read() & 0x7) ==  TYPE_CAS            )
+            else if ((p_vci.rpktid.read() & 0x7) ==  TYPE_CAS)
             {
                 r_vci_rsp_fsm = RSP_DATA_UNC;
             }
-            else if ( (p_vci.rpktid.read() & 0x7) ==  TYPE_LL             )
+            else if ((p_vci.rpktid.read() & 0x7) ==  TYPE_LL)
             {
                 r_vci_rsp_fsm = RSP_DATA_LL;
             }
-            else if ( (p_vci.rpktid.read() & 0x7) == TYPE_SC             )
+            else if ((p_vci.rpktid.read() & 0x7) == TYPE_SC)
             {
                 r_vci_rsp_fsm = RSP_DATA_UNC;
@@ -5916 +5890 @@
         case RSP_INS_MISS:
         {
-            if ( p_vci.rspval.read() )
-            {
-                if ( (p_vci.rerror.read()&0x1) != 0 )  // error reported
+            if (p_vci.rspval.read())
+            {
+                if ((p_vci.rerror.read() & 0x1) != 0)  // error reported
                 {
                     r_vci_rsp_ins_error = true;
-                    if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
+                    if (p_vci.reop.read()) r_vci_rsp_fsm = RSP_IDLE;
                 }
                 else                                        // no error reported
                 {
-                    if ( r_vci_rsp_fifo_icache.wok() )
+                    if (r_vci_rsp_fifo_icache.wok())
                     {
-                        if ( r_vci_rsp_cpt.read() >= m_icache_words )
+                        if (r_vci_rsp_cpt.read() >= m_icache_words)
                         {
                             std::cout << "ERROR in VCI_CC_VCACHE " << name()
@@ -5934 +5908 @@
                             exit(0);
                         }
-                        r_vci_rsp_cpt                 = r_vci_rsp_cpt.read() + 1;
-                        vci_rsp_fifo_icache_put       = true,
-                        vci_rsp_fifo_icache_data      = p_vci.rdata.read();
-                        if ( p_vci.reop.read() )
+                        r_vci_rsp_cpt            = r_vci_rsp_cpt.read() + 1;
+                        vci_rsp_fifo_icache_put  = true,
+                        vci_rsp_fifo_icache_data = p_vci.rdata.read();
+                        if (p_vci.reop.read())
                         {
-                            if ( r_vci_rsp_cpt.read() != (m_icache_words - 1) )
+                            if (r_vci_rsp_cpt.read() != (m_icache_words - 1))
                             {
                                 std::cout << "ERROR in VCI_CC_VCACHE " << name()
@@ -5946 +5920 @@
                                 exit(0);
                             }
-                            r_vci_rsp_fsm    = RSP_IDLE;
+                            r_vci_rsp_fsm = RSP_IDLE;
                         }
                     }
@@ -5956 +5930 @@
         case RSP_INS_UNC:
         {
-            if (p_vci.rspval.read() )
-            {
-                assert( p_vci.reop.read() and
+            if (p_vci.rspval.read())
+            {
+                assert(p_vci.reop.read() and
                 "illegal VCI response packet for uncachable instruction");
 
-                if ( (p_vci.rerror.read()&0x1) != 0 )  // error reported
+                if ((p_vci.rerror.read() & 0x1) != 0)  // error reported
                 {
                     r_vci_rsp_ins_error = true;
@@ -5968 +5942 @@
                 else                                         // no error reported
                 {
-                    if ( r_vci_rsp_fifo_icache.wok())
+                    if (r_vci_rsp_fifo_icache.wok())
                     {
-                        vci_rsp_fifo_icache_put       = true;
-                        vci_rsp_fifo_icache_data      = p_vci.rdata.read();
+                        vci_rsp_fifo_icache_put  = true;
+                        vci_rsp_fifo_icache_data = p_vci.rdata.read();
                         r_vci_rsp_fsm = RSP_IDLE;
                     }
@@ -5981 +5955 @@
         case RSP_DATA_MISS:
         {
-            if ( p_vci.rspval.read() )
-            {
-                if ( (p_vci.rerror.read()&0x1) != 0 )  // error reported
+            if (p_vci.rspval.read())
+            {
+                if ((p_vci.rerror.read() & 0x1) != 0)  // error reported
                 {
                     r_vci_rsp_data_error = true;
-                    if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE;
+                    if (p_vci.reop.read()) r_vci_rsp_fsm = RSP_IDLE;
                 }
                 else                                        // no error reported
                 {
-
-
-                    if ( r_vci_rsp_fifo_dcache.wok() && r_vci_rsp_fifo_rpktid.wok())
+                    if (r_vci_rsp_fifo_dcache.wok() and r_vci_rsp_fifo_rpktid.wok())
                     {
-                        assert( (r_vci_rsp_cpt.read() < m_dcache_words) and
+                        assert((r_vci_rsp_cpt.read() < m_dcache_words) and
                         "The VCI response packet for data miss is too long");
 
-                        r_vci_rsp_cpt                 = r_vci_rsp_cpt.read() + 1;
-                        vci_rsp_fifo_dcache_put       = true,
-                        vci_rsp_fifo_dcache_data      = p_vci.rdata.read();
-                        vci_rsp_fifo_rpktid          = (p_vci.rpktid.read() == 0x9);//RWT: interpretation of pktid for state (NCC or CC)
-                        vci_rsp_fifo_rpktid_put      = true;//RWT
-
-                        if ( p_vci.reop.read() )
+                        r_vci_rsp_cpt             = r_vci_rsp_cpt.read() + 1;
+                        vci_rsp_fifo_dcache_put   = true,
+                        vci_rsp_fifo_dcache_data  = p_vci.rdata.read();
+                        vci_rsp_fifo_rpktid       = (p_vci.rpktid.read() == 0x9); //RWT: interpretation of pktid for state (NCC or CC)
+                        vci_rsp_fifo_rpktid_put   = true; //RWT
+
+                        if (p_vci.reop.read())
                         {
-                            if (r_vci_rsp_cpt.read() != m_dcache_words - 1) std::cout << "assert on proc " << name() << std::endl;
-                            assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and
+                            assert((r_vci_rsp_cpt.read() == m_dcache_words - 1) and
                             "The VCI response packet for data miss is too short");
 
-                            r_vci_rsp_fsm     = RSP_IDLE;
+                            r_vci_rsp_fsm = RSP_IDLE;
                         }
                     }
@@ -6019 +5990 @@
         case RSP_DATA_UNC:
         {
-            if (p_vci.rspval.read() )
-            {
-                assert( p_vci.reop.read() and
+            if (p_vci.rspval.read())
+            {
+                assert(p_vci.reop.read() and
                 "illegal VCI response packet for uncachable read data");
 
-                if ( (p_vci.rerror.read()&0x1) != 0 )  // error reported
+                if ((p_vci.rerror.read() & 0x1) != 0)  // error reported
                 {
                     r_vci_rsp_data_error = true;
                     r_vci_rsp_fsm = RSP_IDLE;
                 }
-                else                                         // no error reported
-                {
-                    if ( r_vci_rsp_fifo_dcache.wok())
+                else // no error reported
+                {
+                    if (r_vci_rsp_fifo_dcache.wok())
                     {
-                        vci_rsp_fifo_dcache_put       = true;
-                        vci_rsp_fifo_dcache_data      = p_vci.rdata.read();
+                        vci_rsp_fifo_dcache_put  = true;
+                        vci_rsp_fifo_dcache_data = p_vci.rdata.read();
                         r_vci_rsp_fsm = RSP_IDLE;
                     }
@@ -6044 +6015 @@
         case RSP_DATA_LL:
         {
-            if ( p_vci.rspval.read() )
-            {
-                if ( (p_vci.rerror.read()&0x1) != 0 )  // error reported
+            if (p_vci.rspval.read())
+            {
+                if ((p_vci.rerror.read() & 0x1) != 0)  // error reported
                 {
                     r_vci_rsp_data_error = true;
@@ -6054 +6025 @@
                 if (r_vci_rsp_cpt.read() == 0) //first flit
                 {
-                    if(r_vci_rsp_fifo_dcache.wok())
+                    if (r_vci_rsp_fifo_dcache.wok())
                     {
                         assert(!p_vci.reop.read() &&
@@ -6066 +6037 @@
                 else // last flit
                 {
-                    if(r_vci_rsp_fifo_dcache.wok())
+                    if (r_vci_rsp_fifo_dcache.wok())
                     {
                         assert(p_vci.reop.read() &&
@@ -6084 +6055 @@
             if (p_vci.rspval.read())
             {
-                assert( p_vci.reop.read() and
+                assert(p_vci.reop.read() and
                 "a VCI response packet must contain one flit for a write transaction");
 
                 r_vci_rsp_fsm = RSP_IDLE;
-                uint32_t   wbuf_index = p_vci.rtrdid.read();
+                uint32_t wbuf_index = p_vci.rtrdid.read();
                 r_wbuf.completed(wbuf_index);
-                if ( (p_vci.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr();
+                if ((p_vci.rerror.read() & 0x1) != 0) r_iss.setWriteBerr();
             }
             break;
@@ -6103 +6074 @@
     // soon as the request has been sent.
     /////////////////////////////////////////////////////////////////////////////////////
-    switch ( r_cc_send_fsm.read() )
+    switch (r_cc_send_fsm.read())
     {
         ///////////////////////////
@@ -6115 +6086 @@
             ///////////////////////////////////////////////////////
             bool update_last_client = r_cc_send_last_client.read();
-            if ( r_cc_send_last_client.read() == 0 ) // last client was dcache
+            if (r_cc_send_last_client.read() == 0) // last client was dcache
             {
                 if (r_icache_cc_send_req.read()) // request from icache
@@ -6131 +6102 @@
             {
                 // the new client is dcache and has a cleanup request
-                if      ( (update_last_client == 0) and
-                          (r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
+                if ((update_last_client == 0) and
+                        (r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP))
                     r_cc_send_fsm = CC_SEND_CLEANUP_1;
                 // the new client is dcache and has a multi acknowledgement request
-                else if ( (update_last_client == 0) and
-                          (r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
+                else if ((update_last_client == 0) and
+                        (r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
                     r_cc_send_fsm = CC_SEND_MULTI_ACK;
                 // the new client is icache and has a cleanup request
-                else if ( (update_last_client == 1) and
-                          (r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
+                else if ((update_last_client == 1) and
+                        (r_icache_cc_send_type.read() == CC_TYPE_CLEANUP))
                     r_cc_send_fsm = CC_SEND_CLEANUP_1;
                 // the new client is icache and has a multi acknowledgement request
-                else if ( (update_last_client == 1) and
+                else if ((update_last_client == 1) and
                         (r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK))
                     r_cc_send_fsm = CC_SEND_MULTI_ACK;
@@ -6165 +6136 @@
             {
 
-                if(r_dcache_cc_cleanup_updt_data.read() and (r_cc_send_last_client.read() == 0))//dcache request with data
+                if (r_dcache_cc_cleanup_updt_data.read() and
+                        (r_cc_send_last_client.read() == 0)) //dcache request with data
                 {
                     r_cc_send_fsm = CC_SEND_CLEANUP_DATA_UPDT;
@@ -6190 +6162 @@
             if (p_dspin_p2m.read.read())
             {
-                if(r_cc_send_data_fifo.rok())
+                if (r_cc_send_data_fifo.rok())
                 {
                     m_cpt_data_cleanup++;
                     cleanup_data_updt_fifo_dcache_get = true;
                     r_cc_send_cpt_word = r_cc_send_cpt_word.read() + 1;
-                    if (r_cc_send_cpt_word.read() == m_dcache_words-1)
+                    if (r_cc_send_cpt_word.read() == m_dcache_words - 1)
                     {
                         r_dcache_cc_send_req = false;
@@ -6210 +6182 @@
         {
             // wait for the flit to be consumed
-            if(p_dspin_p2m.read.read())
-            {
-                if(r_cc_send_last_client.read() == 0) // dcache active request
+            if (p_dspin_p2m.read.read())
+            {
+                if (r_cc_send_last_client.read() == 0) // dcache active request
                     r_dcache_cc_send_req = false; // reset dcache request
                 else // icache active request
@@ -6233 +6205 @@
     // - CC_BROADCAST  : Broadcast invalidate request (both DCACHE & ICACHE)
     //////////////////////////////////////////////////////////////////////////////
-    switch( r_cc_receive_fsm.read() )
+    switch (r_cc_receive_fsm.read())
     {
         /////////////////////
@@ -6247 +6219 @@
                                             DspinRwtParam::M2P_TYPE);
                 // test for a broadcast
-                if (DspinRwtParam::dspin_get(receive_data,DspinRwtParam::M2P_BC))
+                if (DspinRwtParam::dspin_get(receive_data, DspinRwtParam::M2P_BC))
                 {
                     r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER;
@@ -6294 +6266 @@
                 // request dcache to handle the BROADCAST
                 r_cc_receive_dcache_req = true;
-                r_cc_receive_dcache_nline  = DspinRwtParam::dspin_get(receive_data,
+                r_cc_receive_dcache_nline = DspinRwtParam::dspin_get(receive_data,
                                              DspinRwtParam::BROADCAST_NLINE);
                 r_cc_receive_dcache_type = CC_TYPE_INVAL;
                 // request icache to handle the BROADCAST
                 r_cc_receive_icache_req = true;
-                r_cc_receive_icache_nline  = DspinRwtParam::dspin_get(receive_data,
+                r_cc_receive_icache_nline = DspinRwtParam::dspin_get(receive_data,
                                              DspinRwtParam::BROADCAST_NLINE);
                 r_cc_receive_icache_type = CC_TYPE_INVAL;
@@ -6333 +6305 @@
             uint64_t receive_data = p_dspin_m2p.data.read();
             // for data INVAL, wait for dcache to take the request
-            if (p_dspin_m2p.write.read()           and
-                not r_cc_receive_dcache_req.read() )
+            if (p_dspin_m2p.write.read() and
+                not r_cc_receive_dcache_req.read())
             {
                 // request dcache to handle the INVAL
                 r_cc_receive_dcache_req = true;
-                r_cc_receive_dcache_nline = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_INVAL_NLINE);
+                r_cc_receive_dcache_nline = DspinRwtParam::dspin_get(receive_data, DspinRwtParam::MULTI_INVAL_NLINE);
                 r_cc_receive_dcache_type = CC_TYPE_INVAL;
                 // get back to idle state
@@ -6352 +6324 @@
             uint64_t receive_data = p_dspin_m2p.data.read();
             // for ins INVAL, wait for icache to take the request
-            if (p_dspin_m2p.write.read()           and
-                not r_cc_receive_icache_req.read() )
+            if (p_dspin_m2p.write.read() and
+                not r_cc_receive_icache_req.read())
             {
                 // request icache to handle the INVAL
                 r_cc_receive_icache_req = true;
-                r_cc_receive_icache_nline = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_INVAL_NLINE);
+                r_cc_receive_icache_nline = DspinRwtParam::dspin_get(receive_data, DspinRwtParam::MULTI_INVAL_NLINE);
                 r_cc_receive_icache_type = CC_TYPE_INVAL;
                 // get back to idle state
@@ -6374 +6346 @@
             if (not r_cc_receive_dcache_req.read())
             {
-                r_cc_receive_dcache_updt_tab_idx  = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_UPDT_INDEX);
+                r_cc_receive_dcache_updt_tab_idx = DspinRwtParam::dspin_get(receive_data, DspinRwtParam::MULTI_UPDT_UPDT_INDEX);
                 r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_NLINE;
                 break;
@@ -6389 +6361 @@
             if (not r_cc_receive_icache_req.read())
             {
-                r_cc_receive_icache_updt_tab_idx  = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_UPDT_INDEX);
+                r_cc_receive_icache_updt_tab_idx = DspinRwtParam::dspin_get(receive_data, DspinRwtParam::MULTI_UPDT_UPDT_INDEX);
                 r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_NLINE;
                 break;
@@ -6403 +6375 @@
             // for data INVAL, wait for dcache to take the request and fifo to
             // be empty
-            if ( r_cc_receive_updt_fifo_be.empty() and
-                 p_dspin_m2p.write.read() )
-            {
-                r_cc_receive_dcache_req = true;
-                r_cc_receive_dcache_nline  = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_NLINE);
-                r_cc_receive_word_idx  = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_WORD_INDEX);
-                r_cc_receive_dcache_type = CC_TYPE_UPDT;
+            if (r_cc_receive_updt_fifo_be.empty() and
+                 p_dspin_m2p.write.read())
+            {
+                r_cc_receive_dcache_req   = true;
+                r_cc_receive_dcache_nline = DspinRwtParam::dspin_get(receive_data, DspinRwtParam::MULTI_UPDT_NLINE);
+                r_cc_receive_word_idx     = DspinRwtParam::dspin_get(receive_data, DspinRwtParam::MULTI_UPDT_WORD_INDEX);
+                r_cc_receive_dcache_type  = CC_TYPE_UPDT;
                 // get back to idle state
                 r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_DATA;
@@ -6423 +6395 @@
             // for ins INVAL, wait for icache to take the request and fifo to be
             // empty
-            if ( r_cc_receive_updt_fifo_be.empty() and
-                 p_dspin_m2p.write.read() )
-            {
-                r_cc_receive_icache_req = true;
-                r_cc_receive_icache_nline  = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_NLINE);
-                r_cc_receive_word_idx  = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_WORD_INDEX);
-                r_cc_receive_icache_type = CC_TYPE_UPDT;
+            if (r_cc_receive_updt_fifo_be.empty() and
+                 p_dspin_m2p.write.read())
+            {
+                r_cc_receive_icache_req   = true;
+                r_cc_receive_icache_nline = DspinRwtParam::dspin_get(receive_data, DspinRwtParam::MULTI_UPDT_NLINE);
+                r_cc_receive_word_idx     = DspinRwtParam::dspin_get(receive_data, DspinRwtParam::MULTI_UPDT_WORD_INDEX);
+                r_cc_receive_icache_type  = CC_TYPE_UPDT;
                 // get back to idle state
                 r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_DATA;
@@ -6444 +6416 @@
                 uint64_t receive_data = p_dspin_m2p.data.read();
                 bool     receive_eop  = p_dspin_m2p.eop.read();
-                cc_receive_updt_fifo_be   = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_BE);
-                cc_receive_updt_fifo_data = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_DATA);
+                cc_receive_updt_fifo_be   = DspinRwtParam::dspin_get(receive_data, DspinRwtParam::MULTI_UPDT_BE);
+                cc_receive_updt_fifo_data = DspinRwtParam::dspin_get(receive_data, DspinRwtParam::MULTI_UPDT_DATA);
                 cc_receive_updt_fifo_eop  = receive_eop;
                 cc_receive_updt_fifo_put  = true;
-                if ( receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE;
+                if (receive_eop) r_cc_receive_fsm = CC_RECEIVE_IDLE;
             }
             break;
@@ -6460 +6432 @@
                 uint64_t receive_data = p_dspin_m2p.data.read();
                 bool     receive_eop  = p_dspin_m2p.eop.read();
-                cc_receive_updt_fifo_be   = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_BE);
-                cc_receive_updt_fifo_data = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_DATA);
+                cc_receive_updt_fifo_be   = DspinRwtParam::dspin_get(receive_data, DspinRwtParam::MULTI_UPDT_BE);
+                cc_receive_updt_fifo_data = DspinRwtParam::dspin_get(receive_data, DspinRwtParam::MULTI_UPDT_DATA);
                 cc_receive_updt_fifo_eop  = receive_eop;
                 cc_receive_updt_fifo_put  = true;
-                if ( receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE;
+                if (receive_eop) r_cc_receive_fsm = CC_RECEIVE_IDLE;
             }
             break;
@@ -6474 +6446 @@
 
     uint64_t clack_type = DspinRwtParam::dspin_get(r_dspin_clack_flit.read(),
-                                                     DspinRwtParam::CLACK_TYPE);
-
-    size_t clack_way  = DspinRwtParam::dspin_get(r_dspin_clack_flit.read(),
-                                                   DspinRwtParam::CLACK_WAY);
-
-    size_t clack_set  = DspinRwtParam::dspin_get(r_dspin_clack_flit.read(),
-                                                   DspinRwtParam::CLACK_SET);
-
-    bool dspin_clack_get      = false;
+                                                   DspinRwtParam::CLACK_TYPE);
+
+    size_t clack_way = DspinRwtParam::dspin_get(r_dspin_clack_flit.read(),
+                                                DspinRwtParam::CLACK_WAY);
+
+    size_t clack_set = DspinRwtParam::dspin_get(r_dspin_clack_flit.read(),
+                                                DspinRwtParam::CLACK_SET);
+
+    bool dspin_clack_get = false;
     bool dcache_clack_request = (clack_type == DspinRwtParam::TYPE_CLACK_DATA);
     bool icache_clack_request = (clack_type == DspinRwtParam::TYPE_CLACK_INST);
@@ -6489 +6461 @@
     {
         // CLACK DATA: Send request to DCACHE FSM
-        if (dcache_clack_request and not r_dcache_clack_req.read()){
+        if (dcache_clack_request and not r_dcache_clack_req.read())
+        {
             r_dcache_clack_req = true;
-            r_dcache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
-            r_dcache_clack_set = clack_set & ((1ULL<<(uint32_log2(m_dcache_sets)))-1);
+            r_dcache_clack_way = clack_way & ((1ULL << (uint32_log2(m_dcache_ways))) - 1);
+            r_dcache_clack_set = clack_set & ((1ULL << (uint32_log2(m_dcache_sets))) - 1);
             dspin_clack_get    = true;
         }
 
         // CLACK INST: Send request to ICACHE FSM
-        else if (icache_clack_request and not r_icache_clack_req.read()){
+        else if (icache_clack_request and not r_icache_clack_req.read())
+        {
             r_icache_clack_req = true;
             r_icache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1);
@@ -6555 +6529 @@
 
     bool is_sc_or_cas  = (r_vci_cmd_fsm.read() == CMD_DATA_CAS) or
-                         (r_vci_cmd_fsm.read() == CMD_DATA_SC );
+                         (r_vci_cmd_fsm.read() == CMD_DATA_SC);
 
     p_vci.pktid  = 0;
@@ -6565 +6539 @@
     p_vci.cfixed = false;
 
-    if ( m_monitor_ok ) {
-        if ( p_vci.cmdack.read() == true and p_vci.cmdval == true) {
+    if (m_monitor_ok) {
+        if (p_vci.cmdack.read() == true and p_vci.cmdval == true) {
             if (((p_vci.address.read()) >= m_monitor_base) and
-                ((p_vci.address.read()) < m_monitor_base + m_monitor_length) ) {
+                ((p_vci.address.read()) < m_monitor_base + m_monitor_length)) {
                 std::cout << "CC_VCACHE Monitor " << name() << std::hex
                           << " Access type = " << vci_cmd_type_str[p_vci.cmd.read()]
@@ -6574 +6548 @@
                           << " : address = " << p_vci.address.read()
                           << " / be = " << p_vci.be.read();
-                if ( p_vci.cmd.read() == vci_param::CMD_WRITE ) {
+                if (p_vci.cmd.read() == vci_param::CMD_WRITE) {
                     std::cout << " / data = " << p_vci.wdata.read();
                 }
@@ -6582 +6556 @@
     }
 
-    switch ( r_vci_cmd_fsm.read() ) {
+    switch (r_vci_cmd_fsm.read()) {
 
     case CMD_IDLE:
@@ -6683 +6657 @@
         p_vci.cmdval  = true;
         p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
-        if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_llsc_key.read();
-        else                             p_vci.wdata = r_dcache_vci_sc_data.read();
+        if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_dcache_llsc_key.read();
+        else                           p_vci.wdata = r_dcache_vci_sc_data.read();
         p_vci.be      = 0xF;
         p_vci.trdid   = 0;
@@ -6696 +6670 @@
         p_vci.cmdval  = true;
         p_vci.address = r_dcache_vci_paddr.read() & ~0x3;
-        if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_vci_cas_old.read();
-        else                             p_vci.wdata = r_dcache_vci_cas_new.read();
+        if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_dcache_vci_cas_old.read();
+        else                           p_vci.wdata = r_dcache_vci_cas_new.read();
         p_vci.be      = 0xF;
         p_vci.trdid   = 0;
@@ -6710 +6684 @@
     // it depends on the VCI_RSP FSM
 
-    switch (r_vci_rsp_fsm.read() )
+    switch (r_vci_rsp_fsm.read())
     {
         case RSP_DATA_WRITE : p_vci.rspack = true; break;
@@ -6726 +6700 @@
 
     uint64_t dspin_send_data = 0;
-    switch ( r_cc_send_fsm.read() )
+    switch (r_cc_send_fsm.read())
     {
         //////////////////
@@ -6739 +6713 @@
             // initialize dspin send data
             DspinRwtParam::dspin_set(dspin_send_data,
-                                       m_cc_global_id,
-                                       DspinRwtParam::CLEANUP_SRCID);
+                                     m_cc_global_id,
+                                     DspinRwtParam::CLEANUP_SRCID);
             DspinRwtParam::dspin_set(dspin_send_data,
-                                       0,
-                                       DspinRwtParam::P2M_BC);
-
-            if(r_cc_send_last_client.read() == 0) // dcache active request
+                                     0,
+                                     DspinRwtParam::P2M_BC);
+
+            if (r_cc_send_last_client.read() == 0) // dcache active request
             {
                 uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
                                 >> (m_nline_width - m_x_width - m_y_width)
                                 << (DspinRwtParam::GLOBALID_WIDTH - m_x_width - m_y_width);
+
                 DspinRwtParam::dspin_set(dspin_send_data,
-                                           dest,
-                                           DspinRwtParam::CLEANUP_DEST);
+                                         dest,
+                                         DspinRwtParam::CLEANUP_DEST);
 
                 DspinRwtParam::dspin_set(dspin_send_data,
-                                           (r_dcache_cc_send_nline.read() & 0x300000000ULL)>>32,
-                                           DspinRwtParam::CLEANUP_NLINE_MSB);
+                                         (r_dcache_cc_send_nline.read() & 0x300000000ULL) >> 32,
+                                         DspinRwtParam::CLEANUP_NLINE_MSB);
 
                 DspinRwtParam::dspin_set(dspin_send_data,
-                                           r_dcache_cc_send_way.read(),
-                                           DspinRwtParam::CLEANUP_WAY_INDEX);
+                                         r_dcache_cc_send_way.read(),
+                                         DspinRwtParam::CLEANUP_WAY_INDEX);
 
                 DspinRwtParam::dspin_set(dspin_send_data,
-                                           DspinRwtParam::TYPE_CLEANUP_DATA,
-                                           DspinRwtParam::P2M_TYPE);
+                                         DspinRwtParam::TYPE_CLEANUP_DATA,
+                                         DspinRwtParam::P2M_TYPE);
 
                 DspinRwtParam::dspin_set(dspin_send_data,
-                                           (r_dcache_cc_cleanup_line_ncc.read() and (r_cc_send_last_client.read() == 0)),
-                                           DspinRwtParam::CLEANUP_NCC);
+                                         (r_dcache_cc_cleanup_line_ncc.read() and (r_cc_send_last_client.read() == 0)),
+                                         DspinRwtParam::CLEANUP_NCC);
             }
             else                                // icache active request
@@ -6777 +6752 @@
 
                 DspinRwtParam::dspin_set(dspin_send_data,
-                                           dest,
-                                           DspinRwtParam::CLEANUP_DEST);
+                                         dest,
+                                         DspinRwtParam::CLEANUP_DEST);
 
                 DspinRwtParam::dspin_set(dspin_send_data,
-                                           (r_icache_cc_send_nline.read() & 0x300000000ULL)>>32,
-                                           DspinRwtParam::CLEANUP_NLINE_MSB);
+                                         (r_icache_cc_send_nline.read() & 0x300000000ULL) >> 32,
+                                         DspinRwtParam::CLEANUP_NLINE_MSB);
 
                 DspinRwtParam::dspin_set(dspin_send_data,
-                                           r_icache_cc_send_way.read(),
-                                           DspinRwtParam::CLEANUP_WAY_INDEX);
+                                         r_icache_cc_send_way.read(),
+                                         DspinRwtParam::CLEANUP_WAY_INDEX);
 
                 DspinRwtParam::dspin_set(dspin_send_data,
-                                           DspinRwtParam::TYPE_CLEANUP_INST,
-                                           DspinRwtParam::P2M_TYPE);
+                                         DspinRwtParam::TYPE_CLEANUP_INST,
+                                         DspinRwtParam::P2M_TYPE);
 
                 DspinRwtParam::dspin_set(dspin_send_data,
-                                           0,
-                                           DspinRwtParam::CLEANUP_NCC);
+                                         0,
+                                         DspinRwtParam::CLEANUP_NCC);
 
 
@@ -6808 +6783 @@
         {
             // initialize dspin send data
-            if(r_cc_send_last_client.read() == 0) // dcache active request
+            if (r_cc_send_last_client.read() == 0) // dcache active request
             {
                 DspinRwtParam::dspin_set(dspin_send_data,
-                                           r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL,
-                                           DspinRwtParam::CLEANUP_NLINE_LSB);
+                                         r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL,
+                                         DspinRwtParam::CLEANUP_NLINE_LSB);
             }
             else                                  // icache active request
             {
                 DspinRwtParam::dspin_set(dspin_send_data,
-                                           r_icache_cc_send_nline.read() & 0xFFFFFFFFULL,
-                                           DspinRwtParam::CLEANUP_NLINE_LSB);
+                                         r_icache_cc_send_nline.read() & 0xFFFFFFFFULL,
+                                         DspinRwtParam::CLEANUP_NLINE_LSB);
             }
             // send flit
             p_dspin_p2m.data  = dspin_send_data;
             p_dspin_p2m.write = true;
-            p_dspin_p2m.eop   = ! (r_dcache_cc_cleanup_updt_data.read() and (r_cc_send_last_client.read() == 0));
+            p_dspin_p2m.eop   = !(r_dcache_cc_cleanup_updt_data.read() and (r_cc_send_last_client.read() == 0));
             break;
         }
@@ -6831 +6806 @@
 
             DspinRwtParam::dspin_set(dspin_send_data,
-                                       r_cc_send_data_fifo.read(),
-                                       DspinRwtParam::CLEANUP_DATA_UPDT);
-
-            p_dspin_p2m.data = dspin_send_data;
+                                     r_cc_send_data_fifo.read(),
+                                     DspinRwtParam::CLEANUP_DATA_UPDT);
+
+            p_dspin_p2m.data  = dspin_send_data;
             p_dspin_p2m.write = true;
-            p_dspin_p2m.eop = (r_cc_send_cpt_word.read() == m_dcache_words-1);
+            p_dspin_p2m.eop   = (r_cc_send_cpt_word.read() == m_dcache_words - 1);
             break;
         }
@@ -6844 +6819 @@
             // initialize dspin send data
             DspinRwtParam::dspin_set(dspin_send_data,
-                                       0,
-                                       DspinRwtParam::P2M_BC);
+                                     0,
+                                     DspinRwtParam::P2M_BC);
             DspinRwtParam::dspin_set(dspin_send_data,
-                                       DspinRwtParam::TYPE_MULTI_ACK,
-                                       DspinRwtParam::P2M_TYPE);
-
-            if(r_cc_send_last_client.read() == 0) // dcache active request
+                                     DspinRwtParam::TYPE_MULTI_ACK,
+                                     DspinRwtParam::P2M_TYPE);
+
+            if (r_cc_send_last_client.read() == 0) // dcache active request
             {
                 uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read()
@@ -6857 +6832 @@
 
                 DspinRwtParam::dspin_set(dspin_send_data,
-                                           dest,
-                                           DspinRwtParam::MULTI_ACK_DEST);
+                                         dest,
+                                         DspinRwtParam::MULTI_ACK_DEST);
 
                 DspinRwtParam::dspin_set(dspin_send_data,
-                                           r_dcache_cc_send_updt_tab_idx.read(),
-                                           DspinRwtParam::MULTI_ACK_UPDT_INDEX);
+                                         r_dcache_cc_send_updt_tab_idx.read(),
+                                         DspinRwtParam::MULTI_ACK_UPDT_INDEX);
             }
             else                                    // icache active request
@@ -6872 +6847 @@
 
                 DspinRwtParam::dspin_set(dspin_send_data,
-                                           dest,
-                                           DspinRwtParam::MULTI_ACK_DEST);
+                                         dest,
+                                         DspinRwtParam::MULTI_ACK_DEST);
 
                 DspinRwtParam::dspin_set(dspin_send_data,
-                                           r_icache_cc_send_updt_tab_idx.read(),
-                                           DspinRwtParam::MULTI_ACK_UPDT_INDEX);
+                                         r_icache_cc_send_updt_tab_idx.read(),
+                                         DspinRwtParam::MULTI_ACK_UPDT_INDEX);
             }
             // send flit
@@ -6890 +6865 @@
     // Receive coherence packets
     // It depends on the CC_RECEIVE FSM
-    switch( r_cc_receive_fsm.read() )
+    switch (r_cc_receive_fsm.read())
     {
         /////////////////////
@@ -6946 +6921 @@
         case CC_RECEIVE_INS_UPDT_HEADER:
         {
-            if ( not r_cc_receive_icache_req.read())
+            if (not r_cc_receive_icache_req.read())
                 p_dspin_m2p.read = true;
             else
@@ -6956 +6931 @@
         case CC_RECEIVE_INS_UPDT_NLINE:
         {
-            if(r_cc_receive_updt_fifo_be.empty())
+            if (r_cc_receive_updt_fifo_be.empty())
                 p_dspin_m2p.read = true;
             else
@@ -6976 +6951 @@
 
     int clack_type = DspinRwtParam::dspin_get(r_dspin_clack_flit.read(),
-                                                DspinRwtParam::CLACK_TYPE);
+                                              DspinRwtParam::CLACK_TYPE);
 
     bool dspin_clack_get      = false;
@@ -7007 +6982 @@
 // This version of monitor print both Read and Write request
 {
-    m_monitor_ok        = true;
-    m_monitor_base      = base;
-    m_monitor_length    = length;
+    m_monitor_ok     = true;
+    m_monitor_base   = base;
+    m_monitor_length = length;
 }
 
 tmpl(void)::stop_monitor()
 {
-    m_monitor_ok        = false;
+    m_monitor_ok = false;
 }