Index: /branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h =================================================================== --- /branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (revision 826) +++ /branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h (revision 827) @@ -35,5 +35,4 @@ #include #include - #include "caba_base_module.h" #include "multi_write_buffer.h" @@ -307,29 +306,29 @@ soclib::common::AddressDecodingTable m_cacheability_table; - const size_t m_srcid; - const size_t m_cc_global_id; - const size_t m_nline_width; - const size_t m_itlb_ways; - const size_t m_itlb_sets; - const size_t m_dtlb_ways; - const size_t m_dtlb_sets; - const size_t m_icache_ways; - const size_t m_icache_sets; - const paddr_t m_icache_yzmask; - const size_t m_icache_words; - const size_t m_dcache_ways; - const size_t m_dcache_sets; - const paddr_t m_dcache_yzmask; - const size_t m_dcache_words; - const size_t m_x_width; - const size_t m_y_width; - const size_t m_proc_id; - const uint32_t m_max_frozen_cycles; - const size_t m_paddr_nbits; - uint32_t m_debug_start_cycle; - bool m_debug_ok; - - uint32_t m_dcache_paddr_ext_reset; - uint32_t m_icache_paddr_ext_reset; + const size_t m_srcid; + const size_t m_cc_global_id; + const size_t m_nline_width; + const size_t m_itlb_ways; + const size_t m_itlb_sets; + const size_t m_dtlb_ways; + const size_t m_dtlb_sets; + const size_t m_icache_ways; + const size_t m_icache_sets; + const paddr_t m_icache_yzmask; + const size_t m_icache_words; + const size_t m_dcache_ways; + const size_t m_dcache_sets; + const paddr_t m_dcache_yzmask; + const size_t m_dcache_words; + const size_t m_x_width; + const size_t m_y_width; + const size_t m_proc_id; + const uint32_t m_max_frozen_cycles; + const size_t m_paddr_nbits; + uint32_t m_debug_start_cycle; + bool m_debug_ok; + + uint32_t m_dcache_paddr_ext_reset; + uint32_t m_icache_paddr_ext_reset; //////////////////////////////////////// @@ -344,21 +343,21 @@ // debug variables ///////////////////////////////////////////// - bool m_debug_previous_i_hit; - bool m_debug_previous_d_hit; - bool m_debug_activated; + bool m_debug_previous_i_hit; + bool m_debug_previous_d_hit; + bool m_debug_activated; /////////////////////////////// // Software visible REGISTERS /////////////////////////////// - sc_signal r_mmu_ptpr; // page table pointer register - sc_signal r_mmu_mode; // mmu mode register - sc_signal r_mmu_word_lo; // mmu misc data low - sc_signal r_mmu_word_hi; // mmu misc data hight - sc_signal r_mmu_ibvar; // mmu bad instruction address - sc_signal r_mmu_dbvar; // mmu bad data address - sc_signal r_mmu_ietr; // mmu instruction error type - sc_signal r_mmu_detr; // mmu data error type - uint32_t r_mmu_params; // read-only - uint32_t r_mmu_release; // read_only + sc_signal r_mmu_ptpr; // page table pointer register + sc_signal r_mmu_mode; // mmu mode register + sc_signal r_mmu_word_lo; // mmu misc data low + sc_signal r_mmu_word_hi; // mmu misc data hight + sc_signal r_mmu_ibvar; // mmu bad instruction address + sc_signal r_mmu_dbvar; // mmu bad data address + sc_signal r_mmu_ietr; // mmu instruction error type + sc_signal r_mmu_detr; // mmu data error type + uint32_t r_mmu_params; // read-only + uint32_t r_mmu_release; // read_only @@ -366,249 +365,247 @@ // ICACHE FSM REGISTERS ////////////////////////////// - sc_signal r_icache_fsm; // state register - sc_signal r_icache_fsm_save; // return state for coherence op - sc_signal r_icache_vci_paddr; // physical address - sc_signal r_icache_vaddr_save; // virtual address from processor + sc_signal r_icache_fsm; // state register + sc_signal r_icache_fsm_save; // return state for coherence op + sc_signal r_icache_vci_paddr; // physical address + sc_signal r_icache_vaddr_save; // virtual address from processor // icache miss handling - sc_signal r_icache_miss_way; // selected way for cache update - sc_signal r_icache_miss_set; // selected set for cache update - sc_signal r_icache_miss_word; // word index ( cache update) - sc_signal r_icache_miss_inval; // coherence request matching a miss - sc_signal r_icache_miss_clack; // waiting for a cleanup acknowledge + sc_signal r_icache_miss_way; // selected way for cache update + sc_signal r_icache_miss_set; // selected set for cache update + sc_signal r_icache_miss_word; // word index ( cache update) + sc_signal r_icache_miss_inval; // coherence request matching a miss + sc_signal r_icache_miss_clack; // waiting for a cleanup acknowledge // coherence request handling - sc_signal r_icache_cc_way; // selected way for cc update/inval - sc_signal r_icache_cc_set; // selected set for cc update/inval - sc_signal r_icache_cc_word; // word counter for cc update - sc_signal r_icache_cc_need_write; // activate the cache for writing + sc_signal r_icache_cc_way; // selected way for cc update/inval + sc_signal r_icache_cc_set; // selected set for cc update/inval + sc_signal r_icache_cc_word; // word counter for cc update + sc_signal r_icache_cc_need_write; // activate the cache for writing // coherence clack handling - sc_signal r_icache_clack_req; // clack request - sc_signal r_icache_clack_way; // clack way - sc_signal r_icache_clack_set; // clack set + sc_signal r_icache_clack_req; // clack request + sc_signal r_icache_clack_way; // clack way + sc_signal r_icache_clack_set; // clack set // icache flush handling - sc_signal r_icache_flush_count; // slot counter used for cache flush + sc_signal r_icache_flush_count; // slot counter used for cache flush // communication between ICACHE FSM and VCI_CMD FSM - sc_signal r_icache_miss_req; // cached read miss - sc_signal r_icache_unc_req; // uncached read miss + sc_signal r_icache_miss_req; // cached read miss + sc_signal r_icache_unc_req; // uncached read miss // communication between ICACHE FSM and DCACHE FSM - sc_signal r_icache_tlb_miss_req; // (set icache/reset dcache) - sc_signal r_icache_tlb_rsp_error; // tlb miss response error + sc_signal r_icache_tlb_miss_req; // (set icache/reset dcache) + sc_signal r_icache_tlb_rsp_error; // tlb miss response error // Flip-Flop in ICACHE FSM for saving the cleanup victim request - sc_signal r_icache_cleanup_victim_req; - sc_signal r_icache_cleanup_victim_nline; + sc_signal r_icache_cleanup_victim_req; + sc_signal r_icache_cleanup_victim_nline; // communication between ICACHE FSM and CC_SEND FSM - sc_signal r_icache_cc_send_req; // ICACHE cc_send request - sc_signal r_icache_cc_send_type; // ICACHE cc_send request type - sc_signal r_icache_cc_send_nline; // ICACHE cc_send nline - sc_signal r_icache_cc_send_way; // ICACHE cc_send way - sc_signal r_icache_cc_send_updt_tab_idx; // ICACHE cc_send update table index + sc_signal r_icache_cc_send_req; // ICACHE cc_send request + sc_signal r_icache_cc_send_type; // ICACHE cc_send request type + sc_signal r_icache_cc_send_nline; // ICACHE cc_send nline + sc_signal r_icache_cc_send_way; // ICACHE cc_send way + sc_signal r_icache_cc_send_updt_tab_idx; // ICACHE cc_send update table index // Physical address extension for data access - sc_signal r_icache_paddr_ext; // CP2 register (if vci_address > 32) + sc_signal r_icache_paddr_ext; // CP2 register (if vci_address > 32) /////////////////////////////// // DCACHE FSM REGISTERS /////////////////////////////// - sc_signal r_dcache_fsm; // state register - sc_signal r_dcache_fsm_cc_save; // return state for coherence op - sc_signal r_dcache_fsm_scan_save; // return state for tlb scan op + sc_signal r_dcache_fsm; // state register + sc_signal r_dcache_fsm_cc_save; // return state for coherence op + sc_signal r_dcache_fsm_scan_save; // return state for tlb scan op // registers written in P0 stage (used in P1 stage) - sc_signal r_dcache_wbuf_req; // WBUF must be written in P1 stage - sc_signal r_dcache_updt_req; // DCACHE must be updated in P1 stage - sc_signal r_dcache_save_vaddr; // virtual address (from proc) - sc_signal r_dcache_save_wdata; // write data (from proc) - sc_signal r_dcache_save_be; // byte enable (from proc) - sc_signal r_dcache_save_paddr; // physical address - sc_signal r_dcache_save_cache_way; // selected way (from dcache) - sc_signal r_dcache_save_cache_set; // selected set (from dcache) - sc_signal r_dcache_save_cache_word; // selected word (from dcache) + sc_signal r_dcache_wbuf_req; // WBUF must be written in P1 stage + sc_signal r_dcache_updt_req; // DCACHE must be updated in P1 stage + sc_signal r_dcache_save_vaddr; // virtual address (from proc) + sc_signal r_dcache_save_wdata; // write data (from proc) + sc_signal r_dcache_save_be; // byte enable (from proc) + sc_signal r_dcache_save_paddr; // physical address + sc_signal r_dcache_save_cache_way; // selected way (from dcache) + sc_signal r_dcache_save_cache_set; // selected set (from dcache) + sc_signal r_dcache_save_cache_word; // selected word (from dcache) // registers used by the Dirty bit sub-fsm - sc_signal r_dcache_dirty_paddr; // PTE physical address - sc_signal r_dcache_dirty_way; // way to invalidate in dcache - sc_signal r_dcache_dirty_set; // set to invalidate in dcache + sc_signal r_dcache_dirty_paddr; // PTE physical address + sc_signal r_dcache_dirty_way; // way to invalidate in dcache + sc_signal r_dcache_dirty_set; // set to invalidate in dcache // communication between DCACHE FSM and VCI_CMD FSM - sc_signal r_dcache_vci_paddr; // physical address for VCI command - sc_signal r_dcache_vci_wdata; // write unc data for VCI command - sc_signal r_dcache_vci_miss_req; // read miss request - sc_signal r_dcache_vci_unc_req; // uncacheable request (read/write) - sc_signal r_dcache_vci_unc_be; // uncacheable byte enable - sc_signal r_dcache_vci_unc_write; // uncacheable data write request - sc_signal r_dcache_vci_cas_req; // atomic write request CAS - sc_signal r_dcache_vci_cas_old; // previous data value for a CAS - sc_signal r_dcache_vci_cas_new; // new data value for a CAS - sc_signal r_dcache_vci_ll_req; // atomic read request LL - sc_signal r_dcache_vci_sc_req; // atomic write request SC - sc_signal r_dcache_vci_sc_data; // SC data (command) + sc_signal r_dcache_vci_paddr; // physical address for VCI command + sc_signal r_dcache_vci_wdata; // write unc data for VCI command + sc_signal r_dcache_vci_miss_req; // read miss request + sc_signal r_dcache_vci_unc_req; // uncacheable request (read/write) + sc_signal r_dcache_vci_unc_be; // uncacheable byte enable + sc_signal r_dcache_vci_unc_write; // uncacheable data write request + sc_signal r_dcache_vci_cas_req; // atomic write request CAS + sc_signal r_dcache_vci_cas_old; // previous data value for a CAS + sc_signal r_dcache_vci_cas_new; // new data value for a CAS + sc_signal r_dcache_vci_ll_req; // atomic read request LL + sc_signal r_dcache_vci_sc_req; // atomic write request SC + sc_signal r_dcache_vci_sc_data; // SC data (command) //RWT: local cas - sc_signal r_cas_islocal; - sc_signal r_cas_local_way; - sc_signal r_cas_local_set; - sc_signal r_cas_local_word; + sc_signal r_cas_islocal; + sc_signal r_cas_local_way; + sc_signal r_cas_local_set; + sc_signal r_cas_local_word; // register used for XTN inval - sc_signal r_dcache_xtn_way; // selected way (from dcache) - sc_signal r_dcache_xtn_set; // selected set (from dcache) + sc_signal r_dcache_xtn_way; // selected way (from dcache) + sc_signal r_dcache_xtn_set; // selected set (from dcache) // handling dcache miss - sc_signal r_dcache_miss_type; // depending on the requester - sc_signal r_dcache_miss_word; // word index for cache update - sc_signal r_dcache_miss_way; // selected way for cache update - sc_signal r_dcache_miss_set; // selected set for cache update - sc_signal r_dcache_miss_inval; // coherence request matching a miss - sc_signal r_dcache_miss_clack; // waiting for a cleanup acknowledge + sc_signal r_dcache_miss_type; // depending on the requester + sc_signal r_dcache_miss_word; // word index for cache update + sc_signal r_dcache_miss_way; // selected way for cache update + sc_signal r_dcache_miss_set; // selected set for cache update + sc_signal r_dcache_miss_inval; // coherence request matching a miss + sc_signal r_dcache_miss_clack; // waiting for a cleanup acknowledge // handling coherence requests - sc_signal r_dcache_cc_way; // selected way for cc update/inval - sc_signal r_dcache_cc_set; // selected set for cc update/inval - sc_signal r_dcache_cc_state; // state of selected cache slot - sc_signal r_dcache_cc_word; // word counter for cc update - sc_signal r_dcache_cc_need_write; // activate the cache for writing - sc_signal r_dcache_cc_inval_addr; // address for a cleanup transaction - sc_signal r_dcache_cc_inval_data_cpt; + sc_signal r_dcache_cc_way; // selected way for cc update/inval + sc_signal r_dcache_cc_set; // selected set for cc update/inval + sc_signal r_dcache_cc_state; // state of selected cache slot + sc_signal r_dcache_cc_word; // word counter for cc update + sc_signal r_dcache_cc_need_write; // activate the cache for writing + sc_signal r_dcache_cc_inval_addr; // address for a cleanup transaction + sc_signal r_dcache_cc_inval_data_cpt; // coherence clack handling - sc_signal r_dcache_clack_req; // clack request - sc_signal r_dcache_clack_way; // clack way - sc_signal r_dcache_clack_set; // clack set + sc_signal r_dcache_clack_req; // clack request + sc_signal r_dcache_clack_way; // clack way + sc_signal r_dcache_clack_set; // clack set // dcache flush handling - sc_signal r_dcache_flush_count; // slot counter used for cache flush + sc_signal r_dcache_flush_count; // slot counter used for cache flush // ll response handling - sc_signal r_dcache_ll_rsp_count; // flit counter used for ll rsp + sc_signal r_dcache_ll_rsp_count; // flit counter used for ll rsp // used by the TLB miss sub-fsm - sc_signal r_dcache_tlb_vaddr; // virtual address for a tlb miss - sc_signal r_dcache_tlb_ins; // target tlb (itlb if true) - sc_signal r_dcache_tlb_paddr; // physical address of pte - sc_signal r_dcache_tlb_pte_flags; // pte1 or first word of pte2 - sc_signal r_dcache_tlb_pte_ppn; // second word of pte2 - sc_signal r_dcache_tlb_cache_way; // selected way in dcache - sc_signal r_dcache_tlb_cache_set; // selected set in dcache - sc_signal r_dcache_tlb_cache_word; // selected word in dcache - sc_signal r_dcache_tlb_way; // selected way in tlb - sc_signal r_dcache_tlb_set; // selected set in tlb + sc_signal r_dcache_tlb_vaddr; // virtual address for a tlb miss + sc_signal r_dcache_tlb_ins; // target tlb (itlb if true) + sc_signal r_dcache_tlb_paddr; // physical address of pte + sc_signal r_dcache_tlb_pte_flags; // pte1 or first word of pte2 + sc_signal r_dcache_tlb_pte_ppn; // second word of pte2 + sc_signal r_dcache_tlb_cache_way; // selected way in dcache + sc_signal r_dcache_tlb_cache_set; // selected set in dcache + sc_signal r_dcache_tlb_cache_word; // selected word in dcache + sc_signal r_dcache_tlb_way; // selected way in tlb + sc_signal r_dcache_tlb_set; // selected set in tlb // ITLB and DTLB invalidation - sc_signal r_dcache_tlb_inval_line; // line index - sc_signal r_dcache_tlb_inval_set; // tlb set counter + sc_signal r_dcache_tlb_inval_line; // line index + sc_signal r_dcache_tlb_inval_set; // tlb set counter // communication between DCACHE FSM and ICACHE FSM - sc_signal r_dcache_xtn_req; // xtn request (caused by processor) - sc_signal r_dcache_xtn_opcode; // xtn request type + sc_signal r_dcache_xtn_req; // xtn request (caused by processor) + sc_signal r_dcache_xtn_opcode; // xtn request type // Filp-Flop in DCACHE FSM for saving the cleanup victim request - sc_signal r_dcache_cleanup_victim_req; - sc_signal r_dcache_cleanup_victim_line_ncc; - sc_signal r_dcache_cleanup_victim_updt_data; - sc_signal r_dcache_cleanup_victim_nline; + sc_signal r_dcache_cleanup_victim_req; + sc_signal r_dcache_cleanup_victim_line_ncc; + sc_signal r_dcache_cleanup_victim_updt_data; + sc_signal r_dcache_cleanup_victim_nline; // communication between DCACHE FSM and CC_SEND FSM - sc_signal r_dcache_cc_send_req; // DCACHE cc_send request - sc_signal r_dcache_cc_send_type; // DCACHE cc_send request type - sc_signal r_dcache_cc_send_nline; // DCACHE cc_send nline - sc_signal r_dcache_cc_send_way; // DCACHE cc_send way - sc_signal r_dcache_cc_send_updt_tab_idx; // DCACHE cc_send update table index + sc_signal r_dcache_cc_send_req; // DCACHE cc_send request + sc_signal r_dcache_cc_send_type; // DCACHE cc_send request type + sc_signal r_dcache_cc_send_nline; // DCACHE cc_send nline + sc_signal r_dcache_cc_send_way; // DCACHE cc_send way + sc_signal r_dcache_cc_send_updt_tab_idx; // DCACHE cc_send update table index // special registers for RWT - sc_signal r_dcache_cc_cleanup_updt_data; // Register for cleanup with data (wb updt) - sc_signal r_dcache_cc_cleanup_line_ncc; // Register for cleanup with data (wb updt) - sc_signal r_dcache_miss_victim_no_coherence; // Register for victim in no coherence mode - sc_signal r_dcache_line_no_coherence; // Register for line current in no coherence mode - sc_signal r_dcache_dirty_save; - sc_signal r_cc_send_cpt_word; - sc_signal r_dcache_miss_data_cpt; - sc_signal r_dcache_miss_data_addr; - sc_signal r_dcache_xtn_flush_data_cpt; - sc_signal r_dcache_xtn_flush_addr_data; - sc_signal r_dcache_xtn_state; - sc_signal r_dcache_xtn_data_addr; - sc_signal r_dcache_xtn_data_cpt; - sc_signal r_dcache_read_state; + sc_signal r_dcache_cc_cleanup_updt_data; // Register for cleanup with data (wb updt) + sc_signal r_dcache_cc_cleanup_line_ncc; // Register for cleanup with data (wb updt) + sc_signal r_dcache_dirty_save; + sc_signal r_cc_send_cpt_word; + sc_signal r_dcache_miss_data_cpt; + sc_signal r_dcache_miss_data_addr; + sc_signal r_dcache_xtn_flush_data_cpt; + sc_signal r_dcache_xtn_flush_addr_data; + sc_signal r_dcache_xtn_state; + sc_signal r_dcache_xtn_data_addr; + sc_signal r_dcache_xtn_data_cpt; + sc_signal r_dcache_read_state; // dcache directory extension - int *r_dcache_content_state; // content state of one cache line + int *r_dcache_content_state; // content state of one cache line // Stats - int *r_dcache_dirty_word; // use for compute number of words dirty per cleanup_data - bool *r_dcache_zombi_ncc; // use for compute number of blocked write on ncc zombi line + int *r_dcache_dirty_word; // use for compute number of words dirty per cleanup_data + bool *r_dcache_zombi_ncc; // use for compute number of blocked write on ncc zombi line ////////////////////////////////////////////////////////////////////////////////////// /////////////////////////////////// // Physical address extension for data access - sc_signal r_dcache_paddr_ext; // CP2 register (if vci_address > 32) + sc_signal r_dcache_paddr_ext; // CP2 register (if vci_address > 32) /////////////////////////////////// // VCI_CMD FSM REGISTERS /////////////////////////////////// - sc_signal r_vci_cmd_fsm; - sc_signal r_vci_cmd_min; // used for write bursts - sc_signal r_vci_cmd_max; // used for write bursts - sc_signal r_vci_cmd_cpt; // used for write bursts - sc_signal r_vci_cmd_imiss_prio; // round-robin between imiss & dmiss + sc_signal r_vci_cmd_fsm; + sc_signal r_vci_cmd_min; // used for write bursts + sc_signal r_vci_cmd_max; // used for write bursts + sc_signal r_vci_cmd_cpt; // used for write bursts + sc_signal r_vci_cmd_imiss_prio; // round-robin between imiss & dmiss /////////////////////////////////// // VCI_RSP FSM REGISTERS /////////////////////////////////// - sc_signal r_vci_rsp_fsm; - sc_signal r_vci_rsp_cpt; - sc_signal r_vci_rsp_ins_error; - sc_signal r_vci_rsp_data_error; - GenericFifo r_vci_rsp_fifo_icache; // response FIFO to ICACHE FSM - GenericFifo r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM + sc_signal r_vci_rsp_fsm; + sc_signal r_vci_rsp_cpt; + sc_signal r_vci_rsp_ins_error; + sc_signal r_vci_rsp_data_error; + GenericFifo r_vci_rsp_fifo_icache; // response FIFO to ICACHE FSM + GenericFifo r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM //RWT - GenericFifo r_vci_rsp_fifo_rpktid; - GenericFifo r_cc_send_data_fifo; + GenericFifo r_vci_rsp_fifo_rpktid; + GenericFifo r_cc_send_data_fifo; /////////////////////////////////// // CC_SEND FSM REGISTER /////////////////////////////////// - sc_signal r_cc_send_fsm; // state register - sc_signal r_cc_send_last_client; // 0 dcache / 1 icache + sc_signal r_cc_send_fsm; // state register + sc_signal r_cc_send_last_client; // 0 dcache / 1 icache /////////////////////////////////// // CC_RECEIVE FSM REGISTER /////////////////////////////////// - sc_signal r_cc_receive_fsm; // state register - sc_signal r_cc_receive_data_ins; // request to : 0 dcache / 1 icache + sc_signal r_cc_receive_fsm; // state register + sc_signal r_cc_receive_data_ins; // request to : 0 dcache / 1 icache // communication between CC_RECEIVE FSM and ICACHE/DCACHE FSM - sc_signal r_cc_receive_word_idx; // word index - GenericFifo r_cc_receive_updt_fifo_be; - GenericFifo r_cc_receive_updt_fifo_data; - GenericFifo r_cc_receive_updt_fifo_eop; + sc_signal r_cc_receive_word_idx; // word index + GenericFifo r_cc_receive_updt_fifo_be; + GenericFifo r_cc_receive_updt_fifo_data; + GenericFifo r_cc_receive_updt_fifo_eop; // communication between CC_RECEIVE FSM and ICACHE FSM - sc_signal r_cc_receive_icache_req; // cc_receive to icache request - sc_signal r_cc_receive_icache_type; // cc_receive type of request - sc_signal r_cc_receive_icache_way; // cc_receive to icache way - sc_signal r_cc_receive_icache_set; // cc_receive to icache set - sc_signal r_cc_receive_icache_updt_tab_idx; // cc_receive update table index - sc_signal r_cc_receive_icache_nline; // cache line physical address + sc_signal r_cc_receive_icache_req; // cc_receive to icache request + sc_signal r_cc_receive_icache_type; // cc_receive type of request + sc_signal r_cc_receive_icache_way; // cc_receive to icache way + sc_signal r_cc_receive_icache_set; // cc_receive to icache set + sc_signal r_cc_receive_icache_updt_tab_idx; // cc_receive update table index + sc_signal r_cc_receive_icache_nline; // cache line physical address // communication between CC_RECEIVE FSM and DCACHE FSM - sc_signal r_cc_receive_dcache_req; // cc_receive to dcache request - sc_signal r_cc_receive_dcache_type; // cc_receive type of request - sc_signal r_cc_receive_dcache_way; // cc_receive to dcache way - sc_signal r_cc_receive_dcache_set; // cc_receive to dcache set - sc_signal r_cc_receive_dcache_updt_tab_idx; // cc_receive update table index - sc_signal r_cc_receive_dcache_nline; // cache line physical address - sc_signal r_cc_receive_dcache_inval_is_config; // inval from memcache is config + sc_signal r_cc_receive_dcache_req; // cc_receive to dcache request + sc_signal r_cc_receive_dcache_type; // cc_receive type of request + sc_signal r_cc_receive_dcache_way; // cc_receive to dcache way + sc_signal r_cc_receive_dcache_set; // cc_receive to dcache set + sc_signal r_cc_receive_dcache_updt_tab_idx; // cc_receive update table index + sc_signal r_cc_receive_dcache_nline; // cache line physical address + sc_signal r_cc_receive_dcache_inval_is_config; // inval from memcache is config /////////////////////////////////// // DSPIN CLACK INTERFACE REGISTER /////////////////////////////////// - sc_signal r_dspin_clack_req; - sc_signal r_dspin_clack_flit; + sc_signal r_dspin_clack_req; + sc_signal r_dspin_clack_flit; ////////////////////////////////////////////////////////////////// @@ -616,10 +613,10 @@ ////////////////////////////////////////////////////////////////// - iss_t r_iss; - MultiWriteBuffer r_wbuf; - GenericCache r_icache; - GenericCache r_dcache; - GenericTlb r_itlb; - GenericTlb r_dtlb; + iss_t r_iss; + MultiWriteBuffer r_wbuf; + GenericCache r_icache; + GenericCache r_dcache; + GenericTlb r_itlb; + GenericTlb r_dtlb; ////////////////////////////////////////////////////////////////// @@ -627,132 +624,98 @@ ////////////////////////////////////////////////////////////////// - sc_signal r_dcache_llsc_paddr; - sc_signal r_dcache_llsc_key; - sc_signal r_dcache_llsc_count; - sc_signal r_dcache_llsc_valid; - - - sc_signal r_cache_frozen; + sc_signal r_dcache_llsc_paddr; + sc_signal r_dcache_llsc_key; + sc_signal r_dcache_llsc_count; + sc_signal r_dcache_llsc_valid; //////////////////////////////// // Activity counters //////////////////////////////// - uint32_t m_cpt_dcache_data_read; // DCACHE DATA READ - uint32_t m_cpt_dcache_data_write; // DCACHE DATA WRITE - uint32_t m_cpt_dcache_dir_read; // DCACHE DIR READ - uint32_t m_cpt_dcache_dir_write; // DCACHE DIR WRITE - - uint32_t m_cpt_icache_data_read; // ICACHE DATA READ - uint32_t m_cpt_icache_data_write; // ICACHE DATA WRITE - uint32_t m_cpt_icache_dir_read; // ICACHE DIR READ - uint32_t m_cpt_icache_dir_write; // ICACHE DIR WRITE - - uint32_t m_cpt_frz_cycles; // number of cycles where the cpu is frozen - uint32_t m_cpt_total_cycles; // total number of cycles + uint32_t m_cpt_dcache_data_read; // DCACHE DATA READ + uint32_t m_cpt_dcache_data_write; // DCACHE DATA WRITE + uint32_t m_cpt_dcache_dir_read; // DCACHE DIR READ + uint32_t m_cpt_dcache_dir_write; // DCACHE DIR WRITE + + uint32_t m_cpt_icache_data_read; // ICACHE DATA READ + uint32_t m_cpt_icache_data_write; // ICACHE DATA WRITE + uint32_t m_cpt_icache_dir_read; // ICACHE DIR READ + uint32_t m_cpt_icache_dir_write; // ICACHE DIR WRITE + + uint32_t m_cpt_frz_cycles; // number of cycles where the cpu is frozen + uint32_t m_cpt_total_cycles; // total number of cycles // Cache activity counters - uint32_t m_cpt_data_read; // total number of read data - uint32_t m_cpt_data_write; // total number of write data + uint32_t m_cpt_data_read; // total number of read data + uint32_t m_cpt_data_write; // total number of write data uint32_t m_cpt_data_write_back; + uint32_t m_cpt_data_write_miss; // number of total write miss + uint32_t m_cpt_data_write_on_zombi; // number of frozen cycles related to blocked write on ZOMBI line + uint32_t m_cpt_data_write_on_zombi_ncc; // number of frozen cycles related to blocked write on NCC ZOMBI line uint32_t m_cpt_data_cleanup; uint32_t m_cpt_data_sc; - uint32_t m_cpt_data_miss; // number of read miss - uint32_t m_cpt_ins_miss; // number of instruction miss - uint32_t m_cpt_unc_read; // number of read uncached - uint32_t m_cpt_write_cached; // number of cached write - uint32_t m_cpt_ins_read; // number of instruction read - uint32_t m_cpt_ins_spc_miss; // number of speculative instruction miss - - uint32_t m_cost_write_frz; // number of frozen cycles related to write buffer - uint32_t m_cost_data_miss_frz; // number of frozen cycles related to data miss - uint32_t m_cost_unc_read_frz; // number of frozen cycles related to uncached read - uint32_t m_cost_ins_miss_frz; // number of frozen cycles related to ins miss - - uint32_t m_cpt_imiss_transaction; // number of VCI instruction miss transactions - uint32_t m_cpt_dmiss_transaction; // number of VCI data miss transactions - uint32_t m_cpt_unc_transaction; // number of VCI uncached read transactions - uint32_t m_cpt_dunc_transaction; // number of VCI uncached read transactions - uint32_t m_cpt_ll_transaction; // number of VCI uncached read transactions - uint32_t m_cpt_write_transaction; // number of VCI write transactions - uint32_t m_cpt_icache_unc_transaction; - - uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions - uint32_t m_cost_dmiss_transaction; // cumulated duration for VCI DMISS transactions - uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions - uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions - uint32_t m_cost_icache_unc_transaction; // cumulated duration for VCI IUNC transactions - uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions + uint32_t m_cpt_dcache_miss; // number of read miss + uint32_t m_cpt_icache_miss; // number of instruction miss + uint32_t m_cpt_ins_read; // number of instruction read + + uint32_t m_cost_data_miss_frz; // number of frozen cycles related to data miss + uint32_t m_cost_ins_miss_frz; // number of frozen cycles related to ins miss + + uint32_t m_cpt_write_transaction; // number of VCI write transactions + uint32_t m_length_write_transaction; // cumulated length for VCI WRITE transactions // TLB activity counters - uint32_t m_cpt_ins_tlb_read; // number of instruction tlb read - uint32_t m_cpt_ins_tlb_miss; // number of instruction tlb miss - uint32_t m_cpt_ins_tlb_update_acc; // number of instruction tlb update - uint32_t m_cpt_ins_tlb_occup_cache; // number of instruction tlb occupy data cache line - uint32_t m_cpt_ins_tlb_hit_dcache; // number of instruction tlb hit in data cache - - uint32_t m_cpt_data_tlb_read; // number of data tlb read - uint32_t m_cpt_data_tlb_miss; // number of data tlb miss - uint32_t m_cpt_data_tlb_update_acc; // number of data tlb update - uint32_t m_cpt_data_tlb_update_dirty; // number of data tlb update dirty - uint32_t m_cpt_data_tlb_hit_dcache; // number of data tlb hit in data cache - uint32_t m_cpt_data_tlb_occup_cache; // number of data tlb occupy data cache line + uint32_t m_cpt_itlb_read; // number of instruction tlb read + uint32_t m_cpt_itlb_miss; // number of instruction tlb miss + uint32_t m_cpt_itlb_write; // number of instruction tlb update + + uint32_t m_cpt_dtlb_read; // number of data tlb read + uint32_t m_cpt_dtlb_miss; // number of data tlb miss + uint32_t m_cpt_dtlb_write; // number of data tlb update + + uint32_t m_cost_ins_tlb_miss_frz; // number of frozen cycles related to instruction tlb miss + + // coherence activity counters + uint32_t m_cpt_cleanup_data_not_dirty; // number of total cleanup data without extra data flits + uint32_t m_cpt_cleanup_data_dirty_word; // number of total words dirty in cleanup data + + + + // counters NOT implemented + uint32_t m_cost_write_frz; // number of frozen cycles related to write buffer + uint32_t m_cost_unc_read_frz; // number of frozen cycles related to uncached read + uint32_t m_cpt_imiss_transaction; // number of VCI instruction miss transactions + uint32_t m_cpt_dmiss_transaction; // number of VCI data miss transactions + uint32_t m_cpt_unc_transaction; // number of VCI uncached read transactions + uint32_t m_cost_imiss_transaction; // cumulated duration for VCI IMISS transactions + uint32_t m_cost_dmiss_transaction; // cumulated duration for VCI DMISS transactions + uint32_t m_cost_unc_transaction; // cumulated duration for VCI UNC transactions + uint32_t m_cost_write_transaction; // cumulated duration for VCI WRITE transactions + uint32_t m_cpt_data_tlb_update_dirty; // number of data tlb update dirty + uint32_t m_cpt_ins_tlb_hit_dcache; // number of instruction tlb hit in data cache + uint32_t m_cpt_data_tlb_hit_dcache; // number of data tlb hit in data cache + uint32_t m_cost_data_tlb_miss_frz; // number of frozen cycles related to data tlb miss + uint32_t m_cost_ins_tlb_update_acc_frz; // number of frozen cycles related to instruction tlb update acc + uint32_t m_cost_data_tlb_update_acc_frz; // number of frozen cycles related to data tlb update acc + uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty + uint32_t m_cpt_itlbmiss_transaction; // number of itlb miss transactions + uint32_t m_cpt_dtlbmiss_transaction; // number of dtlb miss transactions + uint32_t m_cost_itlbmiss_transaction; // cumulated duration for VCI instruction TLB miss transactions + uint32_t m_cost_dtlbmiss_transaction; // cumulated duration for VCI data TLB miss transactions + uint32_t m_cpt_cc_broadcast; // number of coherence broadcast commands + uint32_t m_cost_updt_data_frz; // number of frozen cycles related to coherence update data packets + uint32_t m_cost_inval_ins_frz; // number of frozen cycles related to coherence inval instruction packets + uint32_t m_cost_inval_data_frz; // number of frozen cycles related to coherence inval data packets + uint32_t m_cost_broadcast_frz; // number of frozen cycles related to coherence broadcast packets + uint32_t m_cpt_cc_cleanup_data; // number of coherence cleanup packets + uint32_t m_cpt_cc_cleanup_ins; // number of coherence cleanup packets + uint32_t m_cpt_dunc_transaction; // number of VCI uncached read transactions + uint32_t m_cpt_ll_transaction; // number of VCI uncached read transactions + uint32_t m_cpt_cc_update_dcache; // number of coherence update data commands + uint32_t m_cpt_cc_inval_icache; // number of coherence inval instruction commands + uint32_t m_cpt_cc_inval_dcache; // number of coherence inval data commands + uint32_t m_cpt_unc_read; // number of read uncached + uint32_t m_cpt_write_cached; // number of cached write uint32_t m_cpt_tlb_occup_dcache; - uint32_t m_cost_ins_tlb_miss_frz; // number of frozen cycles related to instruction tlb miss - uint32_t m_cost_data_tlb_miss_frz; // number of frozen cycles related to data tlb miss - uint32_t m_cost_ins_tlb_update_acc_frz; // number of frozen cycles related to instruction tlb update acc - uint32_t m_cost_data_tlb_update_acc_frz; // number of frozen cycles related to data tlb update acc - uint32_t m_cost_data_tlb_update_dirty_frz; // number of frozen cycles related to data tlb update dirty - uint32_t m_cost_ins_tlb_occup_cache_frz; // number of frozen cycles related to instruction tlb miss operate in dcache - uint32_t m_cost_data_tlb_occup_cache_frz; // number of frozen cycles related to data tlb miss operate in dcache - - uint32_t m_cpt_itlbmiss_transaction; // number of itlb miss transactions - uint32_t m_cpt_itlb_ll_transaction; // number of itlb ll acc transactions - uint32_t m_cpt_itlb_sc_transaction; // number of itlb sc acc transactions - uint32_t m_cpt_dtlbmiss_transaction; // number of dtlb miss transactions - uint32_t m_cpt_dtlb_ll_transaction; // number of dtlb ll acc transactions - uint32_t m_cpt_dtlb_sc_transaction; // number of dtlb sc acc transactions - uint32_t m_cpt_dtlb_ll_dirty_transaction; // number of dtlb ll dirty transactions - uint32_t m_cpt_dtlb_sc_dirty_transaction; // number of dtlb sc dirty transactions - - uint32_t m_cost_itlbmiss_transaction; // cumulated duration for VCI instruction TLB miss transactions - uint32_t m_cost_itlb_ll_transaction; // cumulated duration for VCI instruction TLB ll acc transactions - uint32_t m_cost_itlb_sc_transaction; // cumulated duration for VCI instruction TLB sc acc transactions - uint32_t m_cost_dtlbmiss_transaction; // cumulated duration for VCI data TLB miss transactions - uint32_t m_cost_dtlb_ll_transaction; // cumulated duration for VCI data TLB ll acc transactions - uint32_t m_cost_dtlb_sc_transaction; // cumulated duration for VCI data TLB sc acc transactions - uint32_t m_cost_dtlb_ll_dirty_transaction; // cumulated duration for VCI data TLB ll dirty transactions - uint32_t m_cost_dtlb_sc_dirty_transaction; // cumulated duration for VCI data TLB sc dirty transactions - - // coherence activity counters - uint32_t m_cpt_cc_update_icache; // number of coherence update instruction commands - uint32_t m_cpt_cc_update_dcache; // number of coherence update data commands - uint32_t m_cpt_cc_inval_icache; // number of coherence inval instruction commands - uint32_t m_cpt_cc_inval_dcache; // number of coherence inval data commands - uint32_t m_cpt_cc_broadcast; // number of coherence broadcast commands - - uint32_t m_cost_updt_data_frz; // number of frozen cycles related to coherence update data packets - uint32_t m_cost_inval_ins_frz; // number of frozen cycles related to coherence inval instruction packets - uint32_t m_cost_inval_data_frz; // number of frozen cycles related to coherence inval data packets - uint32_t m_cost_broadcast_frz; // number of frozen cycles related to coherence broadcast packets - - uint32_t m_cpt_cc_cleanup_ins; // number of coherence cleanup packets - uint32_t m_cpt_cc_cleanup_data; // number of coherence cleanup packets - uint32_t m_cpt_cleanup_data_not_dirty; // number of total cleanup data without extra data flits - uint32_t m_cpt_cleanup_data_dirty_word; // number of total words dirty in cleanup data - uint32_t m_cpt_data_write_miss; // number of total write miss - uint32_t m_cpt_data_write_on_zombi; // number of frozen cycles related to blocked write on line NCC/CC ZOMBI - uint32_t m_cpt_data_write_on_zombi_ncc; // number of frozen cycles related to blocked write on line NCC ZOMBI - - uint32_t m_cpt_icleanup_transaction; // number of instruction cleanup transactions - uint32_t m_cpt_dcleanup_transaction; // number of instructinumber of data cleanup transactions - uint32_t m_cost_icleanup_transaction; // cumulated duration for VCI instruction cleanup transactions - uint32_t m_cost_dcleanup_transaction; // cumulated duration for VCI data cleanup transactions - - uint32_t m_cost_ins_tlb_inval_frz; // number of frozen cycles related to checking ins tlb invalidate - uint32_t m_cpt_ins_tlb_inval; // number of ins tlb invalidate - - uint32_t m_cost_data_tlb_inval_frz; // number of frozen cycles related to checking data tlb invalidate - uint32_t m_cpt_data_tlb_inval; // number of data tlb invalidate // FSM activity counters @@ -764,6 +727,6 @@ uint32_t m_cpt_fsm_cc_send [64]; - uint32_t m_cpt_stop_simulation; // used to stop simulation if frozen - bool m_monitor_ok; // used to debug cache output + uint32_t m_cpt_stop_simulation; // used to stop simulation if frozen + bool m_monitor_ok; // used to debug cache output uint32_t m_monitor_base; uint32_t m_monitor_length; @@ -774,26 +737,26 @@ public: VciCcVCacheWrapper( - sc_module_name name, - const int proc_id, - const soclib::common::MappingTable &mtd, - const soclib::common::IntTab &srcid, - const size_t cc_global_id, - const size_t itlb_ways, - const size_t itlb_sets, - const size_t dtlb_ways, - const size_t dtlb_sets, - const size_t icache_ways, - const size_t icache_sets, - const size_t icache_words, - const size_t dcache_ways, - const size_t dcache_sets, - const size_t dcache_words, - const size_t wbuf_nlines, - const size_t wbuf_nwords, - const size_t x_width, - const size_t y_width, - const uint32_t max_frozen_cycles, - const uint32_t debug_start_cycle, - const bool debug_ok ); + sc_module_name name, + const int proc_id, + const soclib::common::MappingTable &mtd, + const soclib::common::IntTab &srcid, + const size_t cc_global_id, + const size_t itlb_ways, + const size_t itlb_sets, + const size_t dtlb_ways, + const size_t dtlb_sets, + const size_t icache_ways, + const size_t icache_sets, + const size_t icache_words, + const size_t dcache_ways, + const size_t dcache_sets, + const size_t dcache_words, + const size_t wbuf_nlines, + const size_t wbuf_nwords, + const size_t x_width, + const size_t y_width, + const uint32_t max_frozen_cycles, + const uint32_t debug_start_cycle, + const bool debug_ok ); ~VciCcVCacheWrapper(); Index: /branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp =================================================================== --- /branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 826) +++ /branches/RWT/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 827) @@ -37,5 +37,4 @@ #define DEBUG_ICACHE 1 #define DEBUG_CMD 0 -#define INSTRUMENTATION 1 namespace soclib { @@ -43,5 +42,5 @@ namespace { -const char *icache_fsm_state_str[] = { +const char * icache_fsm_state_str[] = { "ICACHE_IDLE", @@ -69,5 +68,5 @@ }; -const char *dcache_fsm_state_str[] = { +const char * dcache_fsm_state_str[] = { "DCACHE_IDLE", @@ -122,5 +121,5 @@ }; -const char *cmd_fsm_state_str[] = { +const char * cmd_fsm_state_str[] = { "CMD_IDLE", "CMD_INS_MISS", @@ -135,5 +134,5 @@ }; -const char *vci_pktid_type_str[] = { +const char * vci_pktid_type_str[] = { "TYPE_DATA_UNC", "TYPE_READ_DATA_MISS", @@ -146,5 +145,5 @@ }; -const char *vci_cmd_type_str[] = { +const char * vci_cmd_type_str[] = { "NOP or STORE_COND", "READ", @@ -153,5 +152,5 @@ }; -const char *rsp_fsm_state_str[] = { +const char * rsp_fsm_state_str[] = { "RSP_IDLE", "RSP_INS_MISS", @@ -163,5 +162,5 @@ }; -const char *cc_receive_fsm_state_str[] = { +const char * cc_receive_fsm_state_str[] = { "CC_RECEIVE_IDLE", "CC_RECEIVE_BRDCAST_HEADER", @@ -179,5 +178,5 @@ }; -const char *cc_send_fsm_state_str[] = { +const char * cc_send_fsm_state_str[] = { "CC_SEND_IDLE", "CC_SEND_CLEANUP_1", @@ -199,26 +198,26 @@ ///////////////////////////////// tmpl(/**/)::VciCcVCacheWrapper( - sc_module_name name, - const int proc_id, - const MappingTable &mtd, - const IntTab &srcid, - const size_t cc_global_id, - const size_t itlb_ways, - const size_t itlb_sets, - const size_t dtlb_ways, - const size_t dtlb_sets, - const size_t icache_ways, - const size_t icache_sets, - const size_t icache_words, - const size_t dcache_ways, - const size_t dcache_sets, - const size_t dcache_words, - const size_t wbuf_nlines, - const size_t wbuf_nwords, - const size_t x_width, - const size_t y_width, - const uint32_t max_frozen_cycles, - const uint32_t debug_start_cycle, - const bool debug_ok ) + sc_module_name name, + const int proc_id, + const MappingTable &mtd, + const IntTab &srcid, + const size_t cc_global_id, + const size_t itlb_ways, + const size_t itlb_sets, + const size_t dtlb_ways, + const size_t dtlb_sets, + const size_t icache_ways, + const size_t icache_sets, + const size_t icache_words, + const size_t dcache_ways, + const size_t dcache_sets, + const size_t dcache_words, + const size_t wbuf_nlines, + const size_t wbuf_nwords, + const size_t x_width, + const size_t y_width, + const uint32_t max_frozen_cycles, + const uint32_t debug_start_cycle, + const bool debug_ok) : soclib::caba::BaseModule(name), @@ -230,27 +229,27 @@ p_dspin_clack("p_dspin_clack"), - m_cacheability_table( mtd.getCacheabilityTable() ), - m_srcid( mtd.indexForId(srcid) ), - m_cc_global_id( cc_global_id ), - m_nline_width( vci_param::N - (uint32_log2(dcache_words)) - 2 ), - m_itlb_ways( itlb_ways ), - m_itlb_sets( itlb_sets ), - m_dtlb_ways( dtlb_ways ), - m_dtlb_sets( dtlb_sets ), - m_icache_ways( icache_ways ), - m_icache_sets( icache_sets ), - m_icache_yzmask( (~0)<<(uint32_log2(icache_words) + 2) ), - m_icache_words( icache_words ), - m_dcache_ways( dcache_ways ), - m_dcache_sets( dcache_sets ), - m_dcache_yzmask( (~0)<<(uint32_log2(dcache_words) + 2) ), - m_dcache_words( dcache_words ), - m_x_width( x_width ), - m_y_width( y_width ), - m_proc_id( proc_id ), - m_max_frozen_cycles( max_frozen_cycles ), - m_paddr_nbits( vci_param::N ), - m_debug_start_cycle( debug_start_cycle ), - m_debug_ok( debug_ok ), + m_cacheability_table(mtd.getCacheabilityTable()), + m_srcid(mtd.indexForId(srcid)), + m_cc_global_id(cc_global_id), + m_nline_width(vci_param::N - (uint32_log2(dcache_words)) - 2), + m_itlb_ways(itlb_ways), + m_itlb_sets(itlb_sets), + m_dtlb_ways(dtlb_ways), + m_dtlb_sets(dtlb_sets), + m_icache_ways(icache_ways), + m_icache_sets(icache_sets), + m_icache_yzmask((~0) << (uint32_log2(icache_words) + 2)), + m_icache_words(icache_words), + m_dcache_ways(dcache_ways), + m_dcache_sets(dcache_sets), + m_dcache_yzmask((~0) << (uint32_log2(dcache_words) + 2)), + m_dcache_words(dcache_words), + m_x_width(x_width), + m_y_width(y_width), + m_proc_id(proc_id), + m_max_frozen_cycles(max_frozen_cycles), + m_paddr_nbits(vci_param::N), + m_debug_start_cycle(debug_start_cycle), + m_debug_ok(debug_ok), m_dcache_paddr_ext_reset(0), m_icache_paddr_ext_reset(0), @@ -281,4 +280,8 @@ r_icache_cc_need_write("r_icache_cc_need_write"), + r_icache_clack_req("r_icache_clack_req"), + r_icache_clack_way("r_icache_clack_way"), + r_icache_clack_set("r_icache_clack_set"), + r_icache_flush_count("r_icache_flush_count"), @@ -286,5 +289,5 @@ r_icache_unc_req("r_icache_unc_req"), - r_icache_tlb_miss_req("r_icache_tlb_read_req"), + r_icache_tlb_miss_req("r_icache_tlb_miss_req"), r_icache_tlb_rsp_error("r_icache_tlb_rsp_error"), @@ -297,4 +300,6 @@ r_icache_cc_send_way("r_icache_cc_send_way"), r_icache_cc_send_updt_tab_idx("r_icache_cc_send_updt_tab_idx"), + + r_icache_paddr_ext("r_icache_paddr_ext"), r_dcache_fsm("r_dcache_fsm"), @@ -329,4 +334,9 @@ r_dcache_vci_sc_data("r_dcache_vci_sc_data"), + r_cas_islocal("r_cas_islocal"), + r_cas_local_way("r_cas_local_way"), + r_cas_local_set("r_cas_local_set"), + r_cas_local_word("r_cas_local_word"), + r_dcache_xtn_way("r_dcache_xtn_way"), r_dcache_xtn_set("r_dcache_xtn_set"), @@ -337,9 +347,17 @@ r_dcache_miss_set("r_dcache_miss_set"), r_dcache_miss_inval("r_dcache_miss_inval"), + r_dcache_miss_clack("r_dcache_miss_clack"), r_dcache_cc_way("r_dcache_cc_way"), r_dcache_cc_set("r_dcache_cc_set"), + r_dcache_cc_state("r_dcache_cc_state"), r_dcache_cc_word("r_dcache_cc_word"), r_dcache_cc_need_write("r_dcache_cc_need_write"), + r_dcache_cc_inval_addr("r_dcache_cc_inval_addr"), + r_dcache_cc_inval_data_cpt("r_dcache_cc_inval_data_cpt"), + + r_dcache_clack_req("r_dcache_clack_req"), + r_dcache_clack_way("r_dcache_clack_way"), + r_dcache_clack_set("r_dcache_clack_set"), r_dcache_flush_count("r_dcache_flush_count"), @@ -349,6 +367,10 @@ r_dcache_tlb_vaddr("r_dcache_tlb_vaddr"), r_dcache_tlb_ins("r_dcache_tlb_ins"), + r_dcache_tlb_paddr("r_dcache_tlb_paddr"), r_dcache_tlb_pte_flags("r_dcache_tlb_pte_flags"), r_dcache_tlb_pte_ppn("r_dcache_tlb_pte_ppn"), + r_dcache_tlb_cache_way("r_dcache_tlb_cache_way"), + r_dcache_tlb_cache_set("r_dcache_tlb_cache_set"), + r_dcache_tlb_cache_word("r_dcache_tlb_cache_word"), r_dcache_tlb_way("r_dcache_tlb_way"), r_dcache_tlb_set("r_dcache_tlb_set"), @@ -361,4 +383,6 @@ r_dcache_cleanup_victim_req("r_dcache_cleanup_victim_req"), + r_dcache_cleanup_victim_line_ncc("r_dcache_cleanup_victim_line_ncc"), + r_dcache_cleanup_victim_updt_data("r_dcache_cleanup_victim_updt_data"), r_dcache_cleanup_victim_nline("r_dcache_cleanup_victim_nline"), @@ -369,4 +393,19 @@ r_dcache_cc_send_updt_tab_idx("r_dcache_cc_send_updt_tab_idx"), + r_dcache_cc_cleanup_updt_data("r_dcache_cc_cleanup_updt_data"), + r_dcache_cc_cleanup_line_ncc("r_dcache_cc_cleanup_line_ncc"), + r_dcache_dirty_save("r_dcache_dirty_save"), + r_cc_send_cpt_word("r_cc_send_cpt_word"), + r_dcache_miss_data_cpt("r_dcache_miss_data_cpt"), + r_dcache_miss_data_addr("r_dcache_miss_data_addr"), + r_dcache_xtn_flush_data_cpt("r_dcache_xtn_flush_data_cpt"), + r_dcache_xtn_flush_addr_data("r_dcache_xtn_flush_addr_data"), + r_dcache_xtn_state("r_dcache_xtn_state"), + r_dcache_xtn_data_addr("r_dcache_xtn_data_addr"), + r_dcache_xtn_data_cpt("r_dcache_xtn_data_cpt"), + r_dcache_read_state("r_dcache_read_state"), + + r_dcache_paddr_ext("r_dcache_paddr_ext"), + r_vci_cmd_fsm("r_vci_cmd_fsm"), r_vci_cmd_min("r_vci_cmd_min"), @@ -379,7 +418,7 @@ r_vci_rsp_ins_error("r_vci_rsp_ins_error"), r_vci_rsp_data_error("r_vci_rsp_data_error"), - r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth - r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth - r_vci_rsp_fifo_rpktid("r_vci_rsp_fifo_rpktid", 2), // 2 words depth + r_vci_rsp_fifo_icache("r_vci_rsp_fifo_icache", 2), // 2 words depth + r_vci_rsp_fifo_dcache("r_vci_rsp_fifo_dcache", 2), // 2 words depth + r_vci_rsp_fifo_rpktid("r_vci_rsp_fifo_rpktid", 2), // 2 words depth r_cc_send_data_fifo("r_cc_send_data_fifo", 16), @@ -407,4 +446,8 @@ r_cc_receive_dcache_updt_tab_idx("r_cc_receive_dcache_updt_tab_idx"), r_cc_receive_dcache_nline("r_cc_receive_dcache_nline"), + r_cc_receive_dcache_inval_is_config("r_cc_receive_dcache_inval_is_config"), + + r_dspin_clack_req("r_dspin_clack_req"), + r_dspin_clack_flit("r_dspin_clack_flit"), r_iss(this->name(), proc_id), @@ -412,22 +455,27 @@ r_icache("icache", icache_ways, icache_sets, icache_words), r_dcache("dcache", dcache_ways, dcache_sets, dcache_words), - r_itlb("itlb", proc_id, itlb_ways,itlb_sets,vci_param::N), - r_dtlb("dtlb", proc_id, dtlb_ways,dtlb_sets,vci_param::N) + r_itlb("itlb", proc_id, itlb_ways, itlb_sets, vci_param::N), + r_dtlb("dtlb", proc_id, dtlb_ways, dtlb_sets, vci_param::N), + + r_dcache_llsc_paddr("r_dcache_llsc_paddr"), + r_dcache_llsc_key("r_dcache_llsc_key"), + r_dcache_llsc_count("r_dcache_llsc_count"), + r_dcache_llsc_valid("r_dcache_llsc_valid") { std::cout << " - Building VciCcVcacheWrapper : " << name << std::endl; - assert( ((icache_words*vci_param::B) < (1< 2) and ((1<<(vci_param::T-1)) >= (wbuf_nlines)) and + assert((vci_param::T > 2) and ((1 << (vci_param::T - 1)) >= (wbuf_nlines)) and "Need more TRDID bits."); - assert( (icache_words == dcache_words) and + assert((icache_words == dcache_words) and "icache_words and dcache_words parameters must be equal"); - assert( (itlb_sets == dtlb_sets) and + assert((itlb_sets == dtlb_sets) and "itlb_sets and dtlb_sets parameters must be equal"); - assert( (itlb_ways == dtlb_ways) and + assert((itlb_ways == dtlb_ways) and "itlb_ways and dtlb_ways parameters must be equal"); @@ -436,15 +484,11 @@ (uint32_log2(m_itlb_ways) << 15) | (uint32_log2(m_itlb_sets) << 11) | (uint32_log2(m_icache_ways) << 8) | (uint32_log2(m_icache_sets) << 4) | - (uint32_log2(m_icache_words<<2)); - - r_mmu_release = (uint32_t)(1 << 16) | 0x1; - - ////////////////////MODIFIED/////////////////////////////// - //r_dcache_in_tlb = new bool[dcache_ways*dcache_sets]; - //r_dcache_contains_ptd = new bool[dcache_ways*dcache_sets]; - r_dcache_content_state = new int [dcache_ways*dcache_sets]; - r_dcache_dirty_word = new int [dcache_ways*dcache_sets*dcache_words]; - r_dcache_zombi_ncc = new bool [dcache_ways*dcache_sets]; - /////////////////////////////////////////////////////////// + (uint32_log2(m_icache_words << 2)); + + r_mmu_release = (uint32_t) (1 << 16) | 0x1; + + r_dcache_content_state = new int[dcache_ways * dcache_sets]; + r_dcache_dirty_word = new int[dcache_ways * dcache_sets * dcache_words]; + r_dcache_zombi_ncc = new bool[dcache_ways * dcache_sets]; @@ -459,8 +503,8 @@ typename iss_t::CacheInfo cache_info; cache_info.has_mmu = true; - cache_info.icache_line_size = icache_words*sizeof(uint32_t); + cache_info.icache_line_size = icache_words * sizeof(uint32_t); cache_info.icache_assoc = icache_ways; cache_info.icache_n_lines = icache_sets; - cache_info.dcache_line_size = dcache_words*sizeof(uint32_t); + cache_info.dcache_line_size = dcache_words * sizeof(uint32_t); cache_info.dcache_assoc = dcache_ways; cache_info.dcache_n_lines = dcache_sets; @@ -475,6 +519,4 @@ delete [] r_dcache_dirty_word; delete [] r_dcache_zombi_ncc; - ///////////////////////////////// - //print_stats(); } @@ -515,37 +557,37 @@ << " | MMU = " << r_mmu_mode.read(); - if (r_dcache_updt_req.read() ) std::cout << " | P1_UPDT"; - if (r_dcache_wbuf_req.read() ) std::cout << " | P1_WBUF"; + if (r_dcache_updt_req.read()) std::cout << " | P1_UPDT"; + if (r_dcache_wbuf_req.read()) std::cout << " | P1_WBUF"; std::cout << std::endl; - if(mode & 0x01) - { - if ( r_icache_miss_req.read() ) std::cout << " IMISS_REQ" << std::endl; - if ( r_icache_unc_req.read() ) std::cout << " IUNC_REQ" << std::endl; - if ( r_dcache_vci_miss_req.read() ) std::cout << " DMISS_REQ" << std::endl; - if ( r_dcache_vci_unc_req.read() ) std::cout << " DUNC_REQ" << std::endl; - - r_wbuf.printTrace((mode>>1)&1); - } - if(mode & 0x02) + if (mode & 0x01) + { + if (r_icache_miss_req.read()) std::cout << " IMISS_REQ" << std::endl; + if (r_icache_unc_req.read()) std::cout << " IUNC_REQ" << std::endl; + if (r_dcache_vci_miss_req.read()) std::cout << " DMISS_REQ" << std::endl; + if (r_dcache_vci_unc_req.read()) std::cout << " DUNC_REQ" << std::endl; + + r_wbuf.printTrace((mode >> 1) & 1); + } + if (mode & 0x02) { r_iss.dump(); } - if(mode & 0x04) + if (mode & 0x04) { std::cout << " Data Cache" << std::endl; r_dcache.printTrace(); } - if(mode & 0x08) + if (mode & 0x08) { std::cout << " Instruction Cache" << std::endl; r_icache.printTrace(); } - if(mode & 0x10) + if (mode & 0x10) { std::cout << " Data TLB" << std::endl; r_dtlb.printTrace(); } - if(mode & 0x20) + if (mode & 0x20) { std::cout << " Instruction TLB" << std::endl; @@ -555,20 +597,20 @@ ////////////////////////////////////////// -tmpl(void)::cache_monitor( paddr_t addr ) +tmpl(void)::cache_monitor(paddr_t addr) ////////////////////////////////////////// { - bool cache_hit; - size_t cache_way = 0; - size_t cache_set = 0; - size_t cache_word = 0; - uint32_t cache_rdata = 0; - - cache_hit = r_dcache.read_neutral( addr, - &cache_rdata, - &cache_way, - &cache_set, - &cache_word ); - - if ( cache_hit != m_debug_previous_d_hit ) + bool cache_hit; + size_t cache_way = 0; + size_t cache_set = 0; + size_t cache_word = 0; + uint32_t cache_rdata = 0; + + cache_hit = r_dcache.read_neutral(addr, + &cache_rdata, + &cache_way, + &cache_set, + &cache_word); + + if (cache_hit != m_debug_previous_d_hit) { std::cout << "Monitor PROC " << name() @@ -581,11 +623,11 @@ } - cache_hit = r_icache.read_neutral( addr, - &cache_rdata, - &cache_way, - &cache_set, - &cache_word ); - - if ( cache_hit != m_debug_previous_i_hit ) + cache_hit = r_icache.read_neutral(addr, + &cache_rdata, + &cache_way, + &cache_set, + &cache_word); + + if (cache_hit != m_debug_previous_i_hit) { std::cout << "Monitor PROC " << name() @@ -609,22 +651,21 @@ << "- READ RATE = " << (float)m_cpt_data_read/run_cycles << std::endl << "- WRITE RATE = " << (float)m_cpt_data_write/run_cycles << std::endl - << "- IMISS_RATE = " << (float)m_cpt_ins_miss/m_cpt_ins_read << std::endl - << "- DMISS RATE = " << (float)m_cpt_data_miss/(m_cpt_data_read-m_cpt_unc_read) << std::endl - << "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_ins_miss << std::endl - << "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_data_miss << std::endl + << "- IMISS_RATE = " << (float)m_cpt_icache_miss/m_cpt_ins_read << std::endl + << "- DMISS RATE = " << (float)m_cpt_dcache_miss/(m_cpt_data_read-m_cpt_unc_read) << std::endl + << "- INS MISS COST = " << (float)m_cost_ins_miss_frz/m_cpt_icache_miss << std::endl + << "- DATA MISS COST = " << (float)m_cost_data_miss_frz/m_cpt_dcache_miss << std::endl << "- WRITE COST = " << (float)m_cost_write_frz/m_cpt_data_write << std::endl << "- UNC COST = " << (float)m_cost_unc_read_frz/m_cpt_unc_read << std::endl << "- UNCACHED READ RATE = " << (float)m_cpt_unc_read/m_cpt_data_read << std::endl << "- CACHED WRITE RATE = " << (float)m_cpt_write_cached/m_cpt_data_write << std::endl - << "- INS TLB MISS RATE = " << (float)m_cpt_ins_tlb_miss/m_cpt_ins_tlb_read << std::endl - << "- DATA TLB MISS RATE = " << (float)m_cpt_data_tlb_miss/m_cpt_data_tlb_read << std::endl - << "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_ins_tlb_miss << std::endl - << "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_data_tlb_miss << std::endl - << "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_ins_tlb_update_acc << std::endl - << "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_data_tlb_update_acc << std::endl + << "- INS TLB MISS RATE = " << (float)m_cpt_itlb_miss/m_cpt_itlb_read << std::endl + << "- DATA TLB MISS RATE = " << (float)m_cpt_dtlb_miss/m_cpt_dtlb_read << std::endl + << "- ITLB MISS COST = " << (float)m_cost_ins_tlb_miss_frz/m_cpt_itlb_miss << std::endl + << "- DTLB MISS COST = " << (float)m_cost_data_tlb_miss_frz/m_cpt_dtlb_miss << std::endl + << "- ITLB UPDATE ACC COST = " << (float)m_cost_ins_tlb_update_acc_frz/m_cpt_itlb_write << std::endl + << "- DTLB UPDATE ACC COST = " << (float)m_cost_data_tlb_update_acc_frz/m_cpt_dtlb_write << std::endl << "- DTLB UPDATE DIRTY COST = " << (float)m_cost_data_tlb_update_dirty_frz/m_cpt_data_tlb_update_dirty << std::endl - << "- ITLB HIT IN DCACHE RATE = " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_ins_tlb_miss << std::endl - << "- DTLB HIT IN DCACHE RATE = " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_data_tlb_miss << std::endl - //<< "- DCACHE FROZEN BY ITLB = " << (float)m_cost_ins_tlb_occup_cache_frz/m_cpt_dcache_frz_cycles << std::endl + << "- ITLB HIT IN DCACHE RATE = " << (float)m_cpt_ins_tlb_hit_dcache/m_cpt_itlb_miss << std::endl + << "- DTLB HIT IN DCACHE RATE = " << (float)m_cpt_data_tlb_hit_dcache/m_cpt_dtlb_miss << std::endl << "- DCACHE FOR TLB % = " << (float)m_cpt_tlb_occup_dcache/(m_dcache_ways*m_dcache_sets) << std::endl << "- NB CC BROADCAST = " << m_cpt_cc_broadcast << std::endl @@ -666,104 +707,47 @@ //////////////////////// { - m_cpt_dcache_data_read = 0; + m_cpt_dcache_data_read = 0; m_cpt_dcache_data_write = 0; - m_cpt_dcache_dir_read = 0; - m_cpt_dcache_dir_write = 0; - m_cpt_icache_data_read = 0; + m_cpt_dcache_dir_read = 0; + m_cpt_dcache_dir_write = 0; + m_cpt_icache_data_read = 0; m_cpt_icache_data_write = 0; - m_cpt_icache_dir_read = 0; - m_cpt_icache_dir_write = 0; - - m_cpt_frz_cycles = 0; -// m_cpt_dcache_frz_cycles = 0; - m_cpt_total_cycles = 0; - -// m_cpt_read = 0; -// m_cpt_write = 0; - m_cpt_data_miss = 0; - m_cpt_ins_miss = 0; - m_cpt_unc_read = 0; - m_cpt_write_cached = 0; - m_cpt_ins_read = 0; - - m_cost_write_frz = 0; + m_cpt_icache_dir_read = 0; + m_cpt_icache_dir_write = 0; + + m_cpt_frz_cycles = 0; + m_cpt_total_cycles = 0; + + m_cpt_data_read = 0; + m_cpt_data_write = 0; + m_cpt_data_write_back = 0; + m_cpt_data_cleanup = 0; + m_cpt_data_sc = 0; + + m_cpt_dcache_miss = 0; + m_cpt_icache_miss = 0; + m_cpt_ins_read = 0; + m_cost_data_miss_frz = 0; - m_cost_unc_read_frz = 0; - m_cost_ins_miss_frz = 0; - - m_cpt_imiss_transaction = 0; - m_cpt_dmiss_transaction = 0; - m_cpt_unc_transaction = 0; - m_cpt_write_transaction = 0; - m_cpt_icache_unc_transaction = 0; - - m_cost_imiss_transaction = 0; - m_cost_dmiss_transaction = 0; - m_cost_unc_transaction = 0; - m_cost_write_transaction = 0; - m_cost_icache_unc_transaction = 0; - m_length_write_transaction = 0; - - m_cpt_ins_tlb_read = 0; - m_cpt_ins_tlb_miss = 0; - m_cpt_ins_tlb_update_acc = 0; - - m_cpt_data_tlb_read = 0; - m_cpt_data_tlb_miss = 0; - m_cpt_data_tlb_update_acc = 0; - m_cpt_data_tlb_update_dirty = 0; - m_cpt_ins_tlb_hit_dcache = 0; - m_cpt_data_tlb_hit_dcache = 0; - m_cpt_ins_tlb_occup_cache = 0; - m_cpt_data_tlb_occup_cache = 0; - - m_cost_ins_tlb_miss_frz = 0; - m_cost_data_tlb_miss_frz = 0; - m_cost_ins_tlb_update_acc_frz = 0; - m_cost_data_tlb_update_acc_frz = 0; - m_cost_data_tlb_update_dirty_frz = 0; - m_cost_ins_tlb_occup_cache_frz = 0; - m_cost_data_tlb_occup_cache_frz = 0; - - m_cpt_itlbmiss_transaction = 0; - m_cpt_itlb_ll_transaction = 0; - m_cpt_itlb_sc_transaction = 0; - m_cpt_dtlbmiss_transaction = 0; - m_cpt_dtlb_ll_transaction = 0; - m_cpt_dtlb_sc_transaction = 0; - m_cpt_dtlb_ll_dirty_transaction = 0; - m_cpt_dtlb_sc_dirty_transaction = 0; - - m_cost_itlbmiss_transaction = 0; - m_cost_itlb_ll_transaction = 0; - m_cost_itlb_sc_transaction = 0; - m_cost_dtlbmiss_transaction = 0; - m_cost_dtlb_ll_transaction = 0; - m_cost_dtlb_sc_transaction = 0; - m_cost_dtlb_ll_dirty_transaction = 0; - m_cost_dtlb_sc_dirty_transaction = 0; - -// m_cpt_cc_update_data = 0; -// m_cpt_cc_inval_ins = 0; -// m_cpt_cc_inval_data = 0; - m_cpt_cc_broadcast = 0; - - m_cost_updt_data_frz = 0; - m_cost_inval_ins_frz = 0; - m_cost_inval_data_frz = 0; - m_cost_broadcast_frz = 0; - - m_cpt_cc_cleanup_data = 0; - m_cpt_cc_cleanup_ins = 0; - - m_cpt_cleanup_data_not_dirty = 0; + m_cost_ins_miss_frz = 0; + + m_cpt_write_transaction = 0; + m_length_write_transaction = 0; + + m_cpt_itlb_read = 0; + m_cpt_itlb_miss = 0; + m_cpt_itlb_write = 0; + m_cost_ins_tlb_miss_frz = 0; + + m_cpt_dtlb_read = 0; + m_cpt_dtlb_miss = 0; + m_cpt_dtlb_write = 0; + + m_cpt_cleanup_data_not_dirty = 0; m_cpt_cleanup_data_dirty_word = 0; m_cpt_data_write_miss = 0; m_cpt_data_write_on_zombi = 0; m_cpt_data_write_on_zombi_ncc = 0; - } - - ///////////////////////// @@ -771,5 +755,5 @@ ///////////////////////// { - if ( not p_resetn.read() ) + if (not p_resetn.read()) { r_iss.reset(); @@ -780,10 +764,10 @@ r_dtlb.reset(); - r_dcache_fsm = DCACHE_IDLE; - r_icache_fsm = ICACHE_IDLE; - r_vci_cmd_fsm = CMD_IDLE; - r_vci_rsp_fsm = RSP_IDLE; - r_cc_receive_fsm = CC_RECEIVE_IDLE; - r_cc_send_fsm = CC_SEND_IDLE; + r_dcache_fsm = DCACHE_IDLE; + r_icache_fsm = ICACHE_IDLE; + r_vci_cmd_fsm = CMD_IDLE; + r_vci_rsp_fsm = RSP_IDLE; + r_cc_receive_fsm = CC_RECEIVE_IDLE; + r_cc_send_fsm = CC_SEND_IDLE; // reset data physical address extension @@ -794,9 +778,9 @@ // reset dcache directory extension - for (size_t i=0 ; i< m_dcache_ways*m_dcache_sets ; i++) + for (size_t i = 0; i < m_dcache_ways * m_dcache_sets; i++) { r_dcache_content_state[i] = LINE_CACHE_DATA_NOT_DIRTY; - r_dcache_dirty_word[i] = 0; - r_dcache_zombi_ncc[i] = false; + r_dcache_dirty_word[i] = 0; + r_dcache_zombi_ncc[i] = false; } @@ -838,5 +822,7 @@ // No request from DCACHE FSM to CC_SEND FSM - r_dcache_cc_send_req = false; + r_dcache_cc_send_req = false; + r_dcache_cleanup_victim_req = false; + r_dcache_clack_req = false; @@ -867,14 +853,11 @@ m_debug_activated = false; - // SPECIAL REGISTERS ODCCP + // RWT r_dcache_cc_cleanup_updt_data = false; r_dcache_cc_cleanup_line_ncc = false; - r_dcache_miss_victim_no_coherence = false; - r_dcache_line_no_coherence = false; r_cc_send_cpt_word = 0; r_dcache_miss_data_cpt = 0; r_dcache_miss_data_addr = 0; - r_dcache_cleanup_victim_req = false; r_dcache_cleanup_victim_line_ncc = false; r_dcache_cleanup_victim_updt_data = false; @@ -894,5 +877,7 @@ m_cpt_stop_simulation = 0; - m_cpt_data_miss = 0; + m_cpt_data_read = 0; + + m_cpt_dcache_miss = 0; m_cpt_data_write = 0; m_cpt_data_sc = 0; @@ -900,5 +885,5 @@ m_cpt_data_cleanup = 0; m_cpt_cleanup_data_not_dirty = 0; - m_cpt_ins_miss = 0; + m_cpt_icache_miss = 0; m_cpt_unc_read = 0; m_cpt_write_cached = 0; @@ -910,9 +895,11 @@ m_cost_ins_miss_frz = 0; + m_cpt_dunc_transaction = 0; + m_cpt_ll_transaction = 0; + m_cpt_imiss_transaction = 0; m_cpt_dmiss_transaction = 0; m_cpt_unc_transaction = 0; m_cpt_write_transaction = 0; - m_cpt_icache_unc_transaction = 0; m_cost_imiss_transaction = 0; @@ -920,19 +907,18 @@ m_cost_unc_transaction = 0; m_cost_write_transaction = 0; - m_cost_icache_unc_transaction = 0; m_length_write_transaction = 0; - m_cpt_ins_tlb_read = 0; - m_cpt_ins_tlb_miss = 0; - m_cpt_ins_tlb_update_acc = 0; - - m_cpt_data_tlb_read = 0; - m_cpt_data_tlb_miss = 0; - m_cpt_data_tlb_update_acc = 0; + m_cpt_itlb_read = 0; + m_cpt_itlb_miss = 0; + m_cpt_itlb_write = 0; + + m_cpt_dtlb_read = 0; + m_cpt_dtlb_miss = 0; + m_cpt_dtlb_write = 0; + + m_cpt_tlb_occup_dcache = 0; m_cpt_data_tlb_update_dirty = 0; m_cpt_ins_tlb_hit_dcache = 0; m_cpt_data_tlb_hit_dcache = 0; - m_cpt_ins_tlb_occup_cache = 0; - m_cpt_data_tlb_occup_cache = 0; m_cost_ins_tlb_miss_frz = 0; @@ -941,11 +927,8 @@ m_cost_data_tlb_update_acc_frz = 0; m_cost_data_tlb_update_dirty_frz = 0; - m_cost_ins_tlb_occup_cache_frz = 0; - m_cost_data_tlb_occup_cache_frz = 0; - - m_cpt_ins_tlb_inval = 0; - m_cpt_data_tlb_inval = 0; - m_cost_ins_tlb_inval_frz = 0; - m_cost_data_tlb_inval_frz = 0; + + m_cpt_cc_update_dcache = 0; + m_cpt_cc_inval_icache = 0; + m_cpt_cc_inval_dcache = 0; m_cpt_cc_broadcast = 0; @@ -966,33 +949,13 @@ m_cpt_itlbmiss_transaction = 0; - m_cpt_itlb_ll_transaction = 0; - m_cpt_itlb_sc_transaction = 0; m_cpt_dtlbmiss_transaction = 0; - m_cpt_dtlb_ll_transaction = 0; - m_cpt_dtlb_sc_transaction = 0; - m_cpt_dtlb_ll_dirty_transaction = 0; - m_cpt_dtlb_sc_dirty_transaction = 0; m_cost_itlbmiss_transaction = 0; - m_cost_itlb_ll_transaction = 0; - m_cost_itlb_sc_transaction = 0; m_cost_dtlbmiss_transaction = 0; - m_cost_dtlb_ll_transaction = 0; - m_cost_dtlb_sc_transaction = 0; - m_cost_dtlb_ll_dirty_transaction = 0; - m_cost_dtlb_sc_dirty_transaction = 0; -/* - m_cpt_dcache_frz_cycles = 0; - m_cpt_read = 0; - m_cpt_write = 0; - m_cpt_cc_update_data = 0; - m_cpt_cc_inval_ins = 0; - m_cpt_cc_inval_data = 0; -*/ - - for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_icache [i] = 0; - for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_dcache [i] = 0; - for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_cmd [i] = 0; - for (uint32_t i=0; i<32 ; ++i) m_cpt_fsm_rsp [i] = 0; + + for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_icache[i] = 0; + for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_dcache[i] = 0; + for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_cmd[i] = 0; + for (uint32_t i = 0; i < 32; ++i) m_cpt_fsm_rsp[i] = 0; // init the llsc reservation buffer @@ -1004,26 +967,27 @@ // Response FIFOs default values - bool vci_rsp_fifo_icache_get = false; - bool vci_rsp_fifo_icache_put = false; - uint32_t vci_rsp_fifo_icache_data = 0; - - bool vci_rsp_fifo_dcache_get = false; - bool vci_rsp_fifo_dcache_put = false; - uint32_t vci_rsp_fifo_dcache_data = 0; - bool vci_rsp_fifo_rpktid_get = false; - bool vci_rsp_fifo_rpktid_put = false; - bool vci_rsp_fifo_rpktid = false; + bool vci_rsp_fifo_icache_get = false; + bool vci_rsp_fifo_icache_put = false; + uint32_t vci_rsp_fifo_icache_data = 0; + + bool vci_rsp_fifo_dcache_get = false; + bool vci_rsp_fifo_dcache_put = false; + uint32_t vci_rsp_fifo_dcache_data = 0; + + bool vci_rsp_fifo_rpktid_get = false; + bool vci_rsp_fifo_rpktid_put = false; + bool vci_rsp_fifo_rpktid = false; // FIFO for cleanup data updt - bool cleanup_data_updt_fifo_dcache_get = false; - bool cleanup_data_updt_fifo_dcache_put = false; - uint32_t cleanup_data_updt_fifo_dcache_data = 0; + bool cleanup_data_updt_fifo_dcache_get = false; + bool cleanup_data_updt_fifo_dcache_put = false; + uint32_t cleanup_data_updt_fifo_dcache_data = 0; // updt fifo - bool cc_receive_updt_fifo_get = false; - bool cc_receive_updt_fifo_put = false; - uint32_t cc_receive_updt_fifo_be = 0; - uint32_t cc_receive_updt_fifo_data = 0; - bool cc_receive_updt_fifo_eop = false; + bool cc_receive_updt_fifo_get = false; + bool cc_receive_updt_fifo_put = false; + uint32_t cc_receive_updt_fifo_be = 0; + uint32_t cc_receive_updt_fifo_data = 0; + bool cc_receive_updt_fifo_eop = false; #ifdef INSTRUMENTATION @@ -1099,9 +1063,9 @@ // default value for m_irsp - m_irsp.valid = false; - m_irsp.error = false; + m_irsp.valid = false; + m_irsp.error = false; m_irsp.instruction = 0; - switch( r_icache_fsm.read() ) + switch (r_icache_fsm.read()) { ///////////////// @@ -1115,5 +1079,5 @@ { // coherence clack interrupt - if ( r_icache_clack_req.read() ) + if (r_icache_clack_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1123,5 +1087,5 @@ // coherence interrupt - if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) + if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1133,24 +1097,24 @@ // These request are not executed in this IDLE state (except XTN_INST_PADDR_EXT), // because they require access to icache or itlb, that are already accessed - if ( r_dcache_xtn_req.read() ) - { - if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_PTPR ) - { - r_icache_fsm = ICACHE_XTN_TLB_FLUSH; - } - else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_FLUSH) + if (r_dcache_xtn_req.read()) + { + if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_PTPR) + { + r_icache_fsm = ICACHE_XTN_TLB_FLUSH; + } + else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ICACHE_FLUSH) { r_icache_flush_count = 0; - r_icache_fsm = ICACHE_XTN_CACHE_FLUSH; - } - else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ITLB_INVAL) - { - r_icache_fsm = ICACHE_XTN_TLB_INVAL; - } - else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_ICACHE_INVAL) - { - r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA; - } - else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_MMU_ICACHE_PA_INV) + r_icache_fsm = ICACHE_XTN_CACHE_FLUSH; + } + else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ITLB_INVAL) + { + r_icache_fsm = ICACHE_XTN_TLB_INVAL; + } + else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_ICACHE_INVAL) + { + r_icache_fsm = ICACHE_XTN_CACHE_INVAL_VA; + } + else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_MMU_ICACHE_PA_INV) { if (sizeof(paddr_t) <= 32) @@ -1158,14 +1122,14 @@ assert(r_mmu_word_hi.read() == 0 && "illegal XTN request in ICACHE: high bits should be 0 for 32bit paddr"); - r_icache_vci_paddr = (paddr_t)r_mmu_word_lo.read(); + r_icache_vci_paddr = (paddr_t) r_mmu_word_lo.read(); } else { - r_icache_vci_paddr = (paddr_t)r_mmu_word_hi.read() << 32 | - (paddr_t)r_mmu_word_lo.read(); + r_icache_vci_paddr = (paddr_t) r_mmu_word_hi.read() << 32 | + (paddr_t) r_mmu_word_lo.read(); } r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA; } - else if ( (int)r_dcache_xtn_opcode.read() == (int)iss_t::XTN_INST_PADDR_EXT) + else if ((int) r_dcache_xtn_opcode.read() == (int) iss_t::XTN_INST_PADDR_EXT) { r_icache_paddr_ext = r_dcache_save_wdata.read(); @@ -1174,5 +1138,5 @@ else { - assert( false and + assert(false and "undefined XTN request received by ICACHE FSM"); } @@ -1181,18 +1145,18 @@ // processor request - if ( m_ireq.valid ) - { - bool cacheable; - paddr_t paddr; - bool tlb_hit = false; - pte_info_t tlb_flags; - size_t tlb_way; - size_t tlb_set; - paddr_t tlb_nline; - uint32_t cache_inst = 0; - size_t cache_way; - size_t cache_set; - size_t cache_word; - int cache_state = CACHE_SLOT_STATE_EMPTY; + if (m_ireq.valid) + { + bool cacheable; + paddr_t paddr; + bool tlb_hit = false; + pte_info_t tlb_flags; + size_t tlb_way; + size_t tlb_set; + paddr_t tlb_nline; + uint32_t cache_inst = 0; + size_t cache_way; + size_t cache_set; + size_t cache_word; + int cache_state = CACHE_SLOT_STATE_EMPTY; // We register processor request @@ -1201,16 +1165,16 @@ // sytematic itlb access (if activated) - if ( r_mmu_mode.read() & INS_TLB_MASK ) + if (r_mmu_mode.read() & INS_TLB_MASK) { #ifdef INSTRUMENTATION -m_cpt_ins_tlb_read++; -#endif - tlb_hit = r_itlb.translate( m_ireq.addr, - &paddr, - &tlb_flags, - &tlb_nline, // unused - &tlb_way, // unused - &tlb_set ); // unused + m_cpt_itlb_read++; +#endif + tlb_hit = r_itlb.translate(m_ireq.addr, + &paddr, + &tlb_flags, + &tlb_nline, // unused + &tlb_way, // unused + &tlb_set); // unused } else if (vci_param::N > 32) @@ -1220,18 +1184,18 @@ // systematic icache access (if activated) - if ( r_mmu_mode.read() & INS_CACHE_MASK ) + if (r_mmu_mode.read() & INS_CACHE_MASK) { #ifdef INSTRUMENTATION -m_cpt_icache_data_read++; -m_cpt_icache_dir_read++; -#endif - r_icache.read( paddr, - &cache_inst, - &cache_way, - &cache_set, - &cache_word, - &cache_state ); + m_cpt_icache_data_read++; + m_cpt_icache_dir_read++; +#endif + r_icache.read(paddr, + &cache_inst, + &cache_way, + &cache_set, + &cache_word, + &cache_state); } @@ -1242,43 +1206,57 @@ // and there is no access rights checking - if ( not (r_mmu_mode.read() & INS_TLB_MASK) ) // tlb not activated: + if (not (r_mmu_mode.read() & INS_TLB_MASK)) // tlb not activated: { // cacheability - if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false; - else cacheable = m_cacheability_table[(uint64_t)m_ireq.addr]; - } - else // itlb activated - { - if ( tlb_hit ) // ITLB hit + if (not (r_mmu_mode.read() & INS_CACHE_MASK)) cacheable = false; + else cacheable = m_cacheability_table[(uint64_t) m_ireq.addr]; + } + else // itlb activated + { + if (tlb_hit) // ITLB hit { // cacheability - if ( not (r_mmu_mode.read() & INS_CACHE_MASK) ) cacheable = false; - else cacheable = tlb_flags.c; + if (not (r_mmu_mode.read() & INS_CACHE_MASK)) cacheable = false; + else cacheable = tlb_flags.c; // access rights checking - if ( not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER) ) + if (not tlb_flags.u && (m_ireq.mode == iss_t::MODE_USER)) { - r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION; - r_mmu_ibvar = m_ireq.addr; - m_irsp.valid = true; - m_irsp.error = true; - m_irsp.instruction = 0; + +#if DEBUG_ICACHE + if (m_debug_activated) + std::cout << " MMU Privilege Violation" + << " : PADDR = " << std::hex << paddr << std::endl; +#endif + r_mmu_ietr = MMU_READ_PRIVILEGE_VIOLATION; + r_mmu_ibvar = m_ireq.addr; + m_irsp.valid = true; + m_irsp.error = true; + m_irsp.instruction = 0; break; } - else if ( not tlb_flags.x ) + else if (not tlb_flags.x) { - r_mmu_ietr = MMU_READ_EXEC_VIOLATION; - r_mmu_ibvar = m_ireq.addr; - m_irsp.valid = true; - m_irsp.error = true; - m_irsp.instruction = 0; + +#if DEBUG_ICACHE + if (m_debug_activated) + { + std::cout << " MMU Executable Violation" + << " : PADDR = " << std::hex << paddr << std::endl; + } +#endif + r_mmu_ietr = MMU_READ_EXEC_VIOLATION; + r_mmu_ibvar = m_ireq.addr; + m_irsp.valid = true; + m_irsp.error = true; + m_irsp.instruction = 0; break; } } - else // ITLB miss + else // ITLB miss { #ifdef INSTRUMENTATION -m_cpt_ins_tlb_miss++; + m_cpt_itlb_miss++; #endif r_icache_fsm = ICACHE_TLB_WAIT; @@ -1289,35 +1267,36 @@ // physical address registration - r_icache_vci_paddr = paddr; + r_icache_vci_paddr = paddr; // Finally, we send the response to processor, and compute next state - if ( cacheable ) - { - - if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss + if (cacheable) + { + if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss { #ifdef INSTRUMENTATION -m_cpt_ins_miss++; + m_cpt_icache_miss++; #endif // we request a VCI transaction - r_icache_fsm = ICACHE_MISS_SELECT; + r_icache_fsm = ICACHE_MISS_SELECT; #if DEBUG_ICACHE -if ( m_debug_activated ) -std::cout << " READ MISS in icache" - << " : PADDR = " << std::hex << paddr << std::endl; + if (m_debug_activated) + { + std::cout << " READ MISS in icache" + << " : PADDR = " << std::hex << paddr << std::endl; + } #endif r_icache_miss_req = true; } - else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup + else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup { // stalled until cleanup is acknowledged - r_icache_fsm = ICACHE_IDLE; - } - else // cache hit + r_icache_fsm = ICACHE_IDLE; + } + else // cache hit { #ifdef INSTRUMENTATION -m_cpt_ins_read++; + m_cpt_ins_read++; #endif // return instruction to processor @@ -1326,23 +1305,25 @@ r_icache_fsm = ICACHE_IDLE; #if DEBUG_ICACHE -if ( m_debug_activated ) -std::cout << " READ HIT in icache" - << " : PADDR = " << std::hex << paddr - << " / INST = " << cache_inst << std::dec << std::endl; -#endif - } - } - else // non cacheable read - { - r_icache_unc_req = true; - r_icache_fsm = ICACHE_UNC_WAIT; + if (m_debug_activated) + { + std::cout << " READ HIT in icache" + << " : PADDR = " << std::hex << paddr + << " / INST = " << cache_inst << std::dec << std::endl; + } +#endif + } + } + else // non cacheable read + { + r_icache_unc_req = true; + r_icache_fsm = ICACHE_UNC_WAIT; #if DEBUG_ICACHE -if ( m_debug_activated ) -{ - std::cout << " READ UNCACHEABLE in icache" - << " : PADDR = " << std::hex << paddr << std::endl; -} + if (m_debug_activated) + { + std::cout << " READ UNCACHEABLE in icache" + << " : PADDR = " << std::hex << paddr << std::endl; + } #endif } @@ -1359,5 +1340,5 @@ { // coherence clack interrupt - if ( r_icache_clack_req.read() ) + if (r_icache_clack_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1367,5 +1348,5 @@ // coherence interrupt - if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) + if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1374,17 +1355,17 @@ } - if ( m_ireq.valid ) m_cost_ins_tlb_miss_frz++; + if (m_ireq.valid) m_cost_ins_tlb_miss_frz++; // DCACHE FSM signals response by reseting the request flip-flop - if ( not r_icache_tlb_miss_req.read() ) - { - if ( r_icache_tlb_rsp_error.read() ) // error reported : tlb not updated + if (not r_icache_tlb_miss_req.read()) + { + if (r_icache_tlb_rsp_error.read()) // error reported : tlb not updated { r_icache_tlb_rsp_error = false; - m_irsp.error = true; - m_irsp.valid = true; - r_icache_fsm = ICACHE_IDLE; - } - else // tlb updated : return to IDLE state + m_irsp.error = true; + m_irsp.valid = true; + r_icache_fsm = ICACHE_IDLE; + } + else // tlb updated : return to IDLE state { r_icache_fsm = ICACHE_IDLE; @@ -1394,9 +1375,9 @@ } ////////////////////////// - case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries + case ICACHE_XTN_TLB_FLUSH: // invalidate in one cycle all non global TLB entries { r_itlb.flush(); - r_dcache_xtn_req = false; - r_icache_fsm = ICACHE_IDLE; + r_dcache_xtn_req = false; + r_icache_fsm = ICACHE_IDLE; break; } @@ -1411,5 +1392,5 @@ { // coherence clack interrupt - if ( r_icache_clack_req.read() ) + if (r_icache_clack_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1419,5 +1400,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) + if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1426,20 +1407,20 @@ } - if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request is sent - { - int state; - paddr_t tag; - size_t way = r_icache_flush_count.read()/m_icache_sets; - size_t set = r_icache_flush_count.read()%m_icache_sets; + if (not r_icache_cc_send_req.read()) // blocked until previous cc_send request is sent + { + int state; + paddr_t tag; + size_t way = r_icache_flush_count.read() / m_icache_sets; + size_t set = r_icache_flush_count.read() % m_icache_sets; #ifdef INSTRUMENTATION -m_cpt_icache_dir_read++; -#endif - r_icache.read_dir( way, - set, - &tag, - &state ); - - if ( state == CACHE_SLOT_STATE_VALID_CC ) // inval required + m_cpt_icache_dir_read++; +#endif + r_icache.read_dir(way, + set, + &tag, + &state); + + if (state == CACHE_SLOT_STATE_VALID_CC) // inval required { // request cleanup @@ -1450,19 +1431,19 @@ // goes to ICACHE_XTN_CACHE_FLUSH_GO to make inval - r_icache_miss_way = way; - r_icache_miss_set = set; - r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO; - } - else if ( r_icache_flush_count.read() == - (m_icache_sets*m_icache_ways - 1) ) // last slot + r_icache_miss_way = way; + r_icache_miss_set = set; + r_icache_fsm = ICACHE_XTN_CACHE_FLUSH_GO; + } + else if (r_icache_flush_count.read() == + (m_icache_sets*m_icache_ways - 1)) // last slot { r_dcache_xtn_req = false; - m_drsp.valid = true; - r_icache_fsm = ICACHE_IDLE; + m_drsp.valid = true; + r_icache_fsm = ICACHE_IDLE; } // saturation counter, to have the same last slot condition // in ICACHE_XTN_CACHE_FLUSH and ICACHE_XTN_CACHE_FLUSH_GO states - if ( r_icache_flush_count.read() < (m_icache_sets*m_icache_ways - 1) ) + if (r_icache_flush_count.read() < (m_icache_sets * m_icache_ways - 1)) { r_icache_flush_count = r_icache_flush_count.read() + 1; @@ -1472,27 +1453,27 @@ } /////////////////////////////// - case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush - { - size_t way = r_icache_miss_way.read(); - size_t set = r_icache_miss_set.read(); + case ICACHE_XTN_CACHE_FLUSH_GO: // Switch slot state to ZOMBI for an XTN flush + { + size_t way = r_icache_miss_way.read(); + size_t set = r_icache_miss_set.read(); #ifdef INSTRUMENTATION -m_cpt_icache_dir_write++; -#endif - - r_icache.write_dir( way, - set, - CACHE_SLOT_STATE_ZOMBI ); - - if ( r_icache_flush_count.read() == - (m_icache_sets*m_icache_ways - 1) ) // last slot + m_cpt_icache_dir_write++; +#endif + + r_icache.write_dir(way, + set, + CACHE_SLOT_STATE_ZOMBI); + + if (r_icache_flush_count.read() == + (m_icache_sets*m_icache_ways - 1)) // last slot { r_dcache_xtn_req = false; - m_drsp.valid = true; - r_icache_fsm = ICACHE_IDLE; + m_drsp.valid = true; + r_icache_fsm = ICACHE_IDLE; } else { - r_icache_fsm = ICACHE_XTN_CACHE_FLUSH; + r_icache_fsm = ICACHE_XTN_CACHE_FLUSH; } break; @@ -1500,10 +1481,10 @@ ////////////////////////// - case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address - // stored in the r_dcache_save_wdata register + case ICACHE_XTN_TLB_INVAL: // invalidate one TLB entry selected by the virtual address + // stored in the r_dcache_save_wdata register { r_itlb.inval(r_dcache_save_wdata.read()); - r_dcache_xtn_req = false; - r_icache_fsm = ICACHE_IDLE; + r_dcache_xtn_req = false; + r_icache_fsm = ICACHE_IDLE; break; } @@ -1518,29 +1499,28 @@ // read physical address in TLB when MMU activated - if ( r_mmu_mode.read() & INS_TLB_MASK ) // itlb activated + if (r_mmu_mode.read() & INS_TLB_MASK) // itlb activated { #ifdef INSTRUMENTATION -m_cpt_ins_tlb_read++; -#endif - hit = r_itlb.translate(r_dcache_save_wdata.read(), - &paddr); - } - else // itlb not activated - { - paddr = (paddr_t)r_dcache_save_wdata.read(); - hit = true; - } - - if ( hit ) // continue the selective inval process - { - r_icache_vci_paddr = paddr; - r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA; - } - else // miss : send a request to DCACHE FSM + m_cpt_itlb_read++; +#endif + hit = r_itlb.translate(r_dcache_save_wdata.read(), &paddr); + } + else // itlb not activated + { + paddr = (paddr_t) r_dcache_save_wdata.read(); + hit = true; + } + + if (hit) // continue the selective inval process + { + r_icache_vci_paddr = paddr; + r_icache_fsm = ICACHE_XTN_CACHE_INVAL_PA; + } + else // miss : send a request to DCACHE FSM { #ifdef INSTRUMENTATION -m_cpt_ins_tlb_miss++; + m_cpt_itlb_miss++; #endif r_icache_tlb_miss_req = true; @@ -1555,11 +1535,11 @@ // with address stored in r_icache_vci_paddr register. { - int state; - size_t way; - size_t set; - size_t word; + int state; + size_t way; + size_t set; + size_t word; #ifdef INSTRUMENTATION -m_cpt_icache_dir_read++; + m_cpt_icache_dir_read++; #endif r_icache.read_dir(r_icache_vci_paddr.read(), @@ -1569,5 +1549,5 @@ &word); - if ( state == CACHE_SLOT_STATE_VALID_CC ) // inval to be done + if (state == CACHE_SLOT_STATE_VALID_CC) // inval to be done { r_icache_miss_way = way; @@ -1575,5 +1555,5 @@ r_icache_fsm = ICACHE_XTN_CACHE_INVAL_GO; } - else // miss : acknowlege the XTN request and return + else // miss : acknowlege the XTN request and return { r_dcache_xtn_req = false; @@ -1585,23 +1565,23 @@ case ICACHE_XTN_CACHE_INVAL_GO: // Switch slot to ZOMBI state for an XTN inval { - if ( not r_icache_cc_send_req.read() ) // blocked until previous cc_send request not sent + if (not r_icache_cc_send_req.read()) // blocked until previous cc_send request not sent { #ifdef INSTRUMENTATION -m_cpt_icache_dir_write++; -#endif - r_icache.write_dir( r_icache_miss_way.read(), - r_icache_miss_set.read(), - CACHE_SLOT_STATE_ZOMBI ); + m_cpt_icache_dir_write++; +#endif + r_icache.write_dir(r_icache_miss_way.read(), + r_icache_miss_set.read(), + CACHE_SLOT_STATE_ZOMBI); // request cleanup r_icache_cc_send_req = true; - r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2); + r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words << 2); r_icache_cc_send_way = r_icache_miss_way.read(); r_icache_cc_send_type = CC_TYPE_CLEANUP; // acknowledge the XTN request and return - r_dcache_xtn_req = false; - r_icache_fsm = ICACHE_IDLE; + r_dcache_xtn_req = false; + r_icache_fsm = ICACHE_IDLE; } break; @@ -1609,8 +1589,11 @@ //////////////////////// case ICACHE_MISS_SELECT: // Try to select a slot in associative set, - // if previous cleanup has been sent. // Waiting in this state if no slot available. - // Set the r_icache_cleanup_req flip-flop - // and the r_icache_miss_clack flip-flop, + // If a victim slot has been choosen and the r_icache_cc_send_req is false, + // we send the cleanup request in this state. + // If not, a r_icache_cleanup_victim_req flip-flop is + // utilized for saving this cleanup request, and it will be sent later + // in state ICACHE_MISS_WAIT or ICACHE_MISS_UPDT_DIR. + // The r_icache_miss_clack flip-flop is set // when a cleanup is required { @@ -1618,5 +1601,5 @@ // coherence clack interrupt - if ( r_icache_clack_req.read() ) + if (r_icache_clack_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1626,5 +1609,5 @@ // coherence interrupt - if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) + if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1634,12 +1617,12 @@ - bool found; - bool cleanup; - size_t way; - size_t set; - paddr_t victim; + bool found; + bool cleanup; + size_t way; + size_t set; + paddr_t victim; #ifdef INSTRUMENTATION -m_cpt_icache_dir_read++; + m_cpt_icache_dir_read++; #endif r_icache.read_select(r_icache_vci_paddr.read(), @@ -1648,18 +1631,18 @@ &set, &found, - &cleanup ); - if ( found ) - { - r_icache_miss_way = way; - r_icache_miss_set = set; - - if ( cleanup ) - { - if ( not r_icache_cc_send_req.read() ) - { - r_icache_cc_send_req = true; - r_icache_cc_send_nline = victim; - r_icache_cc_send_way = way; - r_icache_cc_send_type = CC_TYPE_CLEANUP; + &cleanup); + if (found) + { + r_icache_miss_way = way; + r_icache_miss_set = set; + + if (cleanup) + { + if (not r_icache_cc_send_req.read()) + { + r_icache_cc_send_req = true; + r_icache_cc_send_nline = victim; + r_icache_cc_send_way = way; + r_icache_cc_send_type = CC_TYPE_CLEANUP; } else @@ -1669,22 +1652,22 @@ } - r_icache_miss_clack = true; - r_icache_fsm = ICACHE_MISS_CLEAN; + r_icache_miss_clack = true; + r_icache_fsm = ICACHE_MISS_CLEAN; } else { - r_icache_fsm = ICACHE_MISS_WAIT; + r_icache_fsm = ICACHE_MISS_WAIT; } #if DEBUG_ICACHE -if ( m_debug_activated ) -{ - std::cout << " Select a slot:" << std::dec - << " / WAY = " << way - << " / SET = " << set; - if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl; - else std::cout << std::endl; -} + if (m_debug_activated) + { + std::cout << " Select a slot:" << std::dec + << " / WAY = " << way + << " / SET = " << set; + if (cleanup) std::cout << " / VICTIM = " << std::hex << victim << std::endl; + else std::cout << std::endl; + } #endif } @@ -1692,22 +1675,22 @@ } /////////////////////// - case ICACHE_MISS_CLEAN: // switch the slot to zombi state + case ICACHE_MISS_CLEAN: // switch the slot to zombi state { if (m_ireq.valid) m_cost_ins_miss_frz++; #ifdef INSTRUMENTATION -m_cpt_icache_dir_write++; -#endif - r_icache.write_dir( r_icache_miss_way.read(), - r_icache_miss_set.read(), - CACHE_SLOT_STATE_ZOMBI); + m_cpt_icache_dir_write++; +#endif + r_icache.write_dir(r_icache_miss_way.read(), + r_icache_miss_set.read(), + CACHE_SLOT_STATE_ZOMBI); #if DEBUG_ICACHE -if ( m_debug_activated ) -{ - std::cout << " Switch to ZOMBI state" << std::dec - << " / WAY = " << r_icache_miss_way.read() - << " / SET = " << r_icache_miss_set.read() << std::endl; -} + if (m_debug_activated) + { + std::cout << " Switch to ZOMBI state" << std::dec + << " / WAY = " << r_icache_miss_way.read() + << " / SET = " << r_icache_miss_set.read() << std::endl; + } #endif @@ -1716,9 +1699,10 @@ } ////////////////////// - case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM + case ICACHE_MISS_WAIT: // waiting response from VCI_RSP FSM { if (m_ireq.valid) m_cost_ins_miss_frz++; - if ( r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read() ) + // send cleanup victim request + if (r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read()) { r_icache_cc_send_req = true; @@ -1730,5 +1714,5 @@ // coherence clack interrupt - if ( r_icache_clack_req.read() ) + if (r_icache_clack_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1738,5 +1722,5 @@ // coherence interrupt - if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read() ) + if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1745,5 +1729,5 @@ } - if ( r_vci_rsp_ins_error.read() ) // bus error + if (r_vci_rsp_ins_error.read()) // bus error { r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS; @@ -1754,5 +1738,5 @@ r_icache_fsm = ICACHE_IDLE; } - else if ( r_vci_rsp_fifo_icache.rok() ) // response available + else if (r_vci_rsp_fifo_icache.rok()) // response available { r_icache_miss_word = 0; @@ -1762,33 +1746,33 @@ } /////////////////////////// - case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle) - { - if ( m_ireq.valid ) m_cost_ins_miss_frz++; - - if ( r_vci_rsp_fifo_icache.rok() ) // response available + case ICACHE_MISS_DATA_UPDT: // update the cache (one word per cycle) + { + if (m_ireq.valid) m_cost_ins_miss_frz++; + + if (r_vci_rsp_fifo_icache.rok()) // response available { #ifdef INSTRUMENTATION -m_cpt_icache_data_write++; -#endif - r_icache.write( r_icache_miss_way.read(), - r_icache_miss_set.read(), - r_icache_miss_word.read(), - r_vci_rsp_fifo_icache.read() ); + m_cpt_icache_data_write++; +#endif + r_icache.write(r_icache_miss_way.read(), + r_icache_miss_set.read(), + r_icache_miss_word.read(), + r_vci_rsp_fifo_icache.read()); #if DEBUG_ICACHE -if ( m_debug_activated ) -{ - std::cout << " Write one word:" - << " WDATA = " << std::hex << r_vci_rsp_fifo_icache.read() - << " WAY = " << r_icache_miss_way.read() - << " SET = " << r_icache_miss_set.read() - << " WORD = " << r_icache_miss_word.read() << std::endl; -} + if (m_debug_activated) + { + std::cout << " Write one word:" + << " WDATA = " << std::hex << r_vci_rsp_fifo_icache.read() + << " WAY = " << r_icache_miss_way.read() + << " SET = " << r_icache_miss_set.read() + << " WORD = " << r_icache_miss_word.read() << std::endl; + } #endif vci_rsp_fifo_icache_get = true; r_icache_miss_word = r_icache_miss_word.read() + 1; - if ( r_icache_miss_word.read() == m_icache_words-1 ) // last word + if (r_icache_miss_word.read() == m_icache_words - 1) // last word { r_icache_fsm = ICACHE_MISS_DIR_UPDT; @@ -1806,8 +1790,8 @@ // to ZOMBI state, and send a cleanup request. { - if ( m_ireq.valid ) m_cost_ins_miss_frz++; + if (m_ireq.valid) m_cost_ins_miss_frz++; // send cleanup victim request - if ( r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read() ) + if (r_icache_cleanup_victim_req.read() and not r_icache_cc_send_req.read()) { r_icache_cc_send_req = true; @@ -1819,5 +1803,5 @@ // coherence clack interrupt - if ( r_icache_clack_req.read() ) + if (r_icache_clack_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1827,5 +1811,5 @@ // coherence interrupt - if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read() ) + if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read() and not r_icache_cleanup_victim_req.read()) { r_icache_fsm = ICACHE_CC_CHECK; @@ -1834,33 +1818,33 @@ } - if ( not r_icache_miss_clack.read() ) // waiting cleanup acknowledge for victim line - { - if ( r_icache_miss_inval ) // Switch slot to ZOMBI state, and new cleanup - { - if ( not r_icache_cc_send_req.read() ) + if (not r_icache_miss_clack.read()) // waiting cleanup acknowledge for victim line + { + if (r_icache_miss_inval) // Switch slot to ZOMBI state, and new cleanup + { + if (not r_icache_cc_send_req.read()) { r_icache_miss_inval = false; // request cleanup r_icache_cc_send_req = true; - r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words<<2); + r_icache_cc_send_nline = r_icache_vci_paddr.read() / (m_icache_words << 2); r_icache_cc_send_way = r_icache_miss_way.read(); r_icache_cc_send_type = CC_TYPE_CLEANUP; #ifdef INSTRUMENTATION -m_cpt_icache_dir_write++; -#endif - r_icache.write_dir( r_icache_vci_paddr.read(), - r_icache_miss_way.read(), - r_icache_miss_set.read(), - CACHE_SLOT_STATE_ZOMBI ); + m_cpt_icache_dir_write++; +#endif + r_icache.write_dir(r_icache_vci_paddr.read(), + r_icache_miss_way.read(), + r_icache_miss_set.read(), + CACHE_SLOT_STATE_ZOMBI); #if DEBUG_ICACHE -if ( m_debug_activated ) -{ - std::cout << " Switch cache slot to ZOMBI state" - << " PADDR = " << std::hex << r_icache_vci_paddr.read() - << " WAY = " << std::dec << r_icache_miss_way.read() - << " SET = " << r_icache_miss_set.read() << std::endl; -} + if (m_debug_activated) + { + std::cout << " Switch cache slot to ZOMBI state" + << " PADDR = " << std::hex << r_icache_vci_paddr.read() + << " WAY = " << std::dec << r_icache_miss_way.read() + << " SET = " << r_icache_miss_set.read() << std::endl; + } #endif } @@ -1868,23 +1852,23 @@ break; } - else // Switch slot to VALID state + else // Switch slot to VALID state { #ifdef INSTRUMENTATION -m_cpt_icache_dir_write++; -#endif - r_icache.write_dir( r_icache_vci_paddr.read(), - r_icache_miss_way.read(), - r_icache_miss_set.read(), - CACHE_SLOT_STATE_VALID_CC ); + m_cpt_icache_dir_write++; +#endif + r_icache.write_dir(r_icache_vci_paddr.read(), + r_icache_miss_way.read(), + r_icache_miss_set.read(), + CACHE_SLOT_STATE_VALID_CC); #if DEBUG_ICACHE -if ( m_debug_activated ) -{ - std::cout << " Switch cache slot to VALID state" - << " PADDR = " << std::hex << r_icache_vci_paddr.read() - << " WAY = " << std::dec << r_icache_miss_way.read() - << " SET = " << r_icache_miss_set.read() << std::endl; -} + if (m_debug_activated) + { + std::cout << " Switch cache slot to VALID state" + << " PADDR = " << std::hex << r_icache_vci_paddr.read() + << " WAY = " << std::dec << r_icache_miss_way.read() + << " SET = " << r_icache_miss_set.read() << std::endl; + } #endif } @@ -1895,10 +1879,10 @@ } //////////////////// - case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM + case ICACHE_UNC_WAIT: // waiting a response to an uncacheable read from VCI_RSP FSM { // coherence clack interrupt - if ( r_icache_clack_req.read() ) - { - r_icache_fsm = ICACHE_CC_CHECK; + if (r_icache_clack_req.read()) + { + r_icache_fsm = ICACHE_CC_CHECK; r_icache_fsm_save = r_icache_fsm.read(); break; @@ -1906,12 +1890,12 @@ // coherence interrupt - if ( r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) - { - r_icache_fsm = ICACHE_CC_CHECK; + if (r_cc_receive_icache_req.read() and not r_icache_cc_send_req.read()) + { + r_icache_fsm = ICACHE_CC_CHECK; r_icache_fsm_save = r_icache_fsm.read(); break; } - if ( r_vci_rsp_ins_error.read() ) // bus error + if (r_vci_rsp_ins_error.read()) // bus error { r_mmu_ietr = MMU_READ_DATA_ILLEGAL_ACCESS; @@ -1922,10 +1906,10 @@ r_icache_fsm = ICACHE_IDLE; } - else if (r_vci_rsp_fifo_icache.rok() ) // instruction available + else if (r_vci_rsp_fifo_icache.rok()) // instruction available { vci_rsp_fifo_icache_get = true; r_icache_fsm = ICACHE_IDLE; - if ( m_ireq.valid and - (m_ireq.addr == r_icache_vaddr_save.read()) ) // request unmodified + if (m_ireq.valid and + (m_ireq.addr == r_icache_vaddr_save.read())) // request unmodified { m_irsp.valid = true; @@ -1936,12 +1920,12 @@ } ///////////////////// - case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm - // handling coherence requests. - // if there is a matching pending miss, it is - // signaled in the r_icache_miss_inval flip-flop. - // The return state is defined in r_icache_fsm_save. - { - paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4; - paddr_t mask = ~((m_icache_words<<2)-1); + case ICACHE_CC_CHECK: // This state is the entry point of a sub-fsm + // handling coherence requests. + // if there is a matching pending miss, it is + // signaled in the r_icache_miss_inval flip-flop. + // The return state is defined in r_icache_fsm_save. + { + paddr_t paddr = r_cc_receive_icache_nline.read() * m_icache_words * 4; + paddr_t mask = ~((m_icache_words << 2) - 1); // CLACK handler @@ -1949,19 +1933,19 @@ // and reset r_icache_miss_clack if the cleanup ack // is matching a pending miss. - if ( r_icache_clack_req.read() ) - { - - if ( m_ireq.valid ) m_cost_ins_miss_frz++; + if (r_icache_clack_req.read()) + { + + if (m_ireq.valid) m_cost_ins_miss_frz++; #ifdef INSTRUMENTATION -m_cpt_icache_dir_write++; -#endif - r_icache.write_dir( 0, - r_icache_clack_way.read(), - r_icache_clack_set.read(), - CACHE_SLOT_STATE_EMPTY); - - if ( (r_icache_miss_set.read() == r_icache_clack_set.read()) and - (r_icache_miss_way.read() == r_icache_clack_way.read()) ) + m_cpt_icache_dir_write++; +#endif + r_icache.write_dir(0, + r_icache_clack_way.read(), + r_icache_clack_set.read(), + CACHE_SLOT_STATE_EMPTY); + + if ((r_icache_miss_set.read() == r_icache_clack_set.read()) and + (r_icache_miss_way.read() == r_icache_clack_way.read())) { r_icache_miss_clack = false; @@ -1974,11 +1958,11 @@ #if DEBUG_ICACHE -if ( m_debug_activated ) -{ - std::cout << " CC_TYPE_CLACK slot returns to empty state" - << " set = " << r_icache_clack_set.read() - << " / way = " << r_icache_clack_way.read() << std::endl; -} + if (m_debug_activated) + { + std::cout << " CC_TYPE_CLACK slot returns to empty state" + << " set = " << r_icache_clack_set.read() + << " / way = " << r_icache_clack_way.read() << std::endl; + } #endif @@ -1990,11 +1974,11 @@ // because the CLACK access the directory but the MISS match dont. if (r_cc_receive_icache_req.read() and - ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT ) or - (r_icache_fsm_save.read() == ICACHE_MISS_WAIT ) or + ((r_icache_fsm_save.read() == ICACHE_MISS_SELECT) or + (r_icache_fsm_save.read() == ICACHE_MISS_WAIT) or (r_icache_fsm_save.read() == ICACHE_MISS_DIR_UPDT)) and - ((r_icache_vci_paddr.read() & mask) == (paddr & mask)) ) // matching + ((r_icache_vci_paddr.read() & mask) == (paddr & mask))) // matching { // signaling the matching - r_icache_miss_inval = true; + r_icache_miss_inval = true; // in case of update, go to CC_UPDT @@ -2002,6 +1986,6 @@ if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) { - r_icache_fsm = ICACHE_CC_UPDT; - r_icache_cc_word = r_cc_receive_word_idx.read(); + r_icache_fsm = ICACHE_CC_UPDT; + r_icache_cc_word = r_cc_receive_word_idx.read(); // just pop the fifo , don't write in icache @@ -2012,27 +1996,27 @@ { r_cc_receive_icache_req = false; - r_icache_fsm = r_icache_fsm_save.read(); + r_icache_fsm = r_icache_fsm_save.read(); } #if DEBUG_ICACHE -if ( m_debug_activated ) -{ - std::cout << " Coherence request matching a pending miss:" - << " PADDR = " << std::hex << paddr << std::endl; -} -#endif - } - - assert ( not r_icache_cc_send_req.read() and "CC_SEND must be available in ICACHE_CC_CHECK"); + if (m_debug_activated) + { + std::cout << " Coherence request matching a pending miss:" + << " PADDR = " << std::hex << paddr << std::endl; + } +#endif + } + + assert(not r_icache_cc_send_req.read() and "CC_SEND must be available in ICACHE_CC_CHECK"); // CC request handler - int state = 0; - size_t way = 0; - size_t set = 0; - size_t word = 0; + int state = 0; + size_t way = 0; + size_t set = 0; + size_t word = 0; #ifdef INSTRUMENTATION -m_cpt_icache_dir_read++; + m_cpt_icache_dir_read++; #endif r_icache.read_dir(paddr, @@ -2045,5 +2029,5 @@ r_icache_cc_set = set; - if ( state == CACHE_SLOT_STATE_VALID_CC) // hit + if (state == CACHE_SLOT_STATE_VALID_CC) // hit { // need to update the cache state @@ -2051,10 +2035,10 @@ { r_icache_cc_need_write = true; - r_icache_fsm = ICACHE_CC_UPDT; - r_icache_cc_word = r_cc_receive_word_idx.read(); - } - else if ( r_cc_receive_icache_type.read() == CC_TYPE_INVAL ) // hit inval - { - r_icache_fsm = ICACHE_CC_INVAL; + r_icache_fsm = ICACHE_CC_UPDT; + r_icache_cc_word = r_cc_receive_word_idx.read(); + } + else if (r_cc_receive_icache_type.read() == CC_TYPE_INVAL) // hit inval + { + r_icache_fsm = ICACHE_CC_INVAL; } } @@ -2062,8 +2046,8 @@ { // multicast acknowledgement required in case of update - if(r_cc_receive_icache_type.read() == CC_TYPE_UPDT) - { - r_icache_fsm = ICACHE_CC_UPDT; - r_icache_cc_word = r_cc_receive_word_idx.read(); + if (r_cc_receive_icache_type.read() == CC_TYPE_UPDT) + { + r_icache_fsm = ICACHE_CC_UPDT; + r_icache_cc_word = r_cc_receive_word_idx.read(); // just pop the fifo , don't write in icache @@ -2073,35 +2057,34 @@ { r_cc_receive_icache_req = false; - r_icache_fsm = r_icache_fsm_save.read(); + r_icache_fsm = r_icache_fsm_save.read(); } } #if DEBUG_ICACHE -if ( m_debug_activated ) -{ - std::cout << " Coherence request received:" - << " PADDR = " << std::hex << paddr - << " / TYPE = " << std::dec << r_cc_receive_dcache_type.read() - << " / HIT = " << ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC)) << std::endl; -} -#endif - + if (m_debug_activated) + { + std::cout << " Coherence request received:" + << " PADDR = " << std::hex << paddr + << " / TYPE = " << std::dec << r_cc_receive_dcache_type.read() + << " / HIT = " << ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC)) << std::endl; + } +#endif break; } ///////////////////// - case ICACHE_CC_INVAL: // hit inval : switch slot to ZOMBI state - { - assert (not r_icache_cc_send_req.read() && - "ERROR in ICACHE_CC_INVAL: the r_icache_cc_send_req " - "must not be set"); + case ICACHE_CC_INVAL: // hit inval : switch slot to ZOMBI state + { + assert(not r_icache_cc_send_req.read() and + "ERROR in ICACHE_CC_INVAL: the r_icache_cc_send_req " + "must not be set"); #ifdef INSTRUMENTATION -m_cpt_icache_dir_read++; + m_cpt_icache_dir_read++; #endif // Switch slot state to ZOMBI and send CLEANUP command - r_icache.write_dir( r_icache_cc_way.read(), - r_icache_cc_set.read(), - CACHE_SLOT_STATE_ZOMBI ); + r_icache.write_dir(r_icache_cc_way.read(), + r_icache_cc_set.read(), + CACHE_SLOT_STATE_ZOMBI); // coherence request completed @@ -2111,14 +2094,14 @@ r_icache_cc_send_type = CC_TYPE_CLEANUP; - r_icache_fsm = r_icache_fsm_save.read(); + r_icache_fsm = r_icache_fsm_save.read(); #if DEBUG_ICACHE -if ( m_debug_activated ) -{ -std::cout << " slot returns to ZOMBI state" - << " set = " << r_icache_cc_set.read() - << " / way = " << r_icache_cc_way.read() << std::endl; -} + if (m_debug_activated) + { + std::cout << " slot returns to ZOMBI state" + << " set = " << r_icache_cc_set.read() + << " / way = " << r_icache_cc_way.read() << std::endl; + } #endif @@ -2126,50 +2109,50 @@ } //////////////////// - case ICACHE_CC_UPDT: // hit update : write one word per cycle - { - assert (not r_icache_cc_send_req.read() && - "ERROR in ICACHE_CC_UPDT: the r_icache_cc_send_req " - "must not be set"); - - if ( not r_cc_receive_updt_fifo_be.rok() ) break; - - - size_t word = r_icache_cc_word.read(); - size_t way = r_icache_cc_way.read(); - size_t set = r_icache_cc_set.read(); + case ICACHE_CC_UPDT: // hit update : write one word per cycle + { + assert(not r_icache_cc_send_req.read() and + "ERROR in ICACHE_CC_UPDT: the r_icache_cc_send_req " + "must not be set"); + + if (not r_cc_receive_updt_fifo_be.rok()) break; + + + size_t word = r_icache_cc_word.read(); + size_t way = r_icache_cc_way.read(); + size_t set = r_icache_cc_set.read(); if (r_icache_cc_need_write.read()) { - r_icache.write( way, - set, - word, - r_cc_receive_updt_fifo_data.read(), - r_cc_receive_updt_fifo_be.read() ); - - r_icache_cc_word = word+1; + r_icache.write(way, + set, + word, + r_cc_receive_updt_fifo_data.read(), + r_cc_receive_updt_fifo_be.read()); + + r_icache_cc_word = word + 1; #ifdef INSTRUMENTATION -m_cpt_icache_data_write++; + m_cpt_icache_data_write++; #endif #if DEBUG_ICACHE -if ( m_debug_activated ) -{ - std::cout << " Write one word " - << " set = " << r_icache_cc_set.read() - << " / way = " << r_icache_cc_way.read() - << " / word = " << r_icache_cc_word.read() << std::endl; -} -#endif - } - - if ( r_cc_receive_updt_fifo_eop.read() ) // last word + if (m_debug_activated) + { + std::cout << " Write one word " + << " set = " << r_icache_cc_set.read() + << " / way = " << r_icache_cc_way.read() + << " / word = " << r_icache_cc_word.read() << std::endl; + } +#endif + } + + if (r_cc_receive_updt_fifo_eop.read()) // last word { // no need to write in the cache anymore - r_icache_cc_need_write = false; + r_icache_cc_need_write = false; // coherence request completed - r_cc_receive_icache_req = false; + r_cc_receive_icache_req = false; // request multicast acknowledgement @@ -2179,8 +2162,8 @@ r_icache_cc_send_type = CC_TYPE_MULTI_ACK; - r_icache_fsm = r_icache_fsm_save.read(); + r_icache_fsm = r_icache_fsm_save.read(); } //consume fifo if not eop - cc_receive_updt_fifo_get = true; + cc_receive_updt_fifo_get = true; break; @@ -2243,20 +2226,19 @@ // This component implement a strong order between non cacheable access // (read or write) : A new non cacheable VCI transaction starts only when - // the previous non cacheable transaction is completed. Both cacheable and - // non cacheable transactions use the write buffer, but the DCACHE FSM registers - // a non cacheable write transaction posted in the write buffer by setting the - // r_dcache_pending_unc_write flip_flop. All other non cacheable requests - // are stalled until this flip-flop is reset by the VCI_RSP_FSM (when the - // pending non cacheable write transaction completes). + // the previous non cacheable transaction is completed. After send the VCI + // transaction, the DCACHE FSM wait for the respone in the DCACHE_UNC_WAIT state. + // So the processor is blocked until the respone arrives in CACHE L1. // // 6/ Error handling: // When the MMU is not activated, Read Bus Errors are synchronous events, - // but Write Bus Errors are asynchronous events (processor is not frozen). - // - If a Read Bus Error is detected, the VCI_RSP FSM sets the + // Some Write Bus Errors are synchronous events when the request is a non cacheable access + // but some Write Bus Errors are asynchronous events when the request is cacheable access + // (processor is not frozen). + // - If a Read Bus Error or a Non Cacheable Write Bus Error is detected, the VCI_RSP FSM sets the // r_vci_rsp_data_error flip-flop, without writing any data in the // r_vci_rsp_fifo_dcache FIFO, and the synchronous error is signaled // by the DCACHE FSM. - // - If a Write Bus Error is detected, the VCI_RSP FSM signals - // the asynchronous error using the setWriteBerr() method. + // - If a Cacheable Write Bus Error is detected, the VCI_RSP_FSM signals + // the asynchronous error using the setWriteBerr() method. // When the MMU is activated bus error are rare events, as the MMU // checks the physical address before the VCI transaction starts. @@ -2268,5 +2250,5 @@ m_drsp.rdata = 0; - switch ( r_dcache_fsm.read() ) + switch (r_dcache_fsm.read()) { case DCACHE_IDLE: // There are 10 conditions to exit the IDLE state : @@ -2278,5 +2260,5 @@ // 6) Dirty bit update (processor) => DCACHE_DIRTY_GET_PTE // 7) Cacheable read miss (processor) => DCACHE_MISS_SELECT - // 8) Uncacheable read (processor) => DCACHE_UNC_WAIT + // 8) Uncacheable read/write (processor)=> DCACHE_UNC_WAIT // 9) LL access (processor) => DCACHE_LL_WAIT // 10) SC access (processor) => DCACHE_SC_WAIT @@ -2305,90 +2287,90 @@ // updt_request, wbuf_request, wbuf_write_miss. { - paddr_t paddr; // physical address - pte_info_t tlb_flags; - size_t tlb_way; - size_t tlb_set; - paddr_t tlb_nline = 0; - size_t cache_way; - size_t cache_set; - size_t cache_word; - uint32_t cache_rdata = 0; - bool tlb_hit = false; - int cache_state = CACHE_SLOT_STATE_EMPTY; - - bool tlb_inval_required = false; // request TLB inval after cache update - bool wbuf_write_miss = false; // miss a WBUF write request - bool updt_request = false; // request DCACHE update in P1 stage - bool wbuf_request = false; // request WBUF write in P1 stage - - // physical address computation : systematic DTLB access (if activated) + paddr_t paddr; + pte_info_t tlb_flags; + size_t tlb_way; + size_t tlb_set; + paddr_t tlb_nline = 0; + size_t cache_way; + size_t cache_set; + size_t cache_word; + uint32_t cache_rdata = 0; + bool tlb_hit = false; + int cache_state = CACHE_SLOT_STATE_EMPTY; + + bool tlb_inval_required = false; // request TLB inval after cache update + bool wbuf_write_miss = false; // miss a WBUF write request + bool updt_request = false; // request DCACHE update in P1 stage + bool wbuf_request = false; // request WBUF write in P1 stage + + // physical address computation : systematic DTLB access if activated paddr = (paddr_t) m_dreq.addr; - if ( m_dreq.valid ) - { - if ( r_mmu_mode.read() & DATA_TLB_MASK ) // DTLB activated - { - tlb_hit = r_dtlb.translate( m_dreq.addr, - &paddr, - &tlb_flags, - &tlb_nline, - &tlb_way, - &tlb_set ); + if (m_dreq.valid) + { + if (r_mmu_mode.read() & DATA_TLB_MASK) // DTLB activated + { + tlb_hit = r_dtlb.translate(m_dreq.addr, + &paddr, + &tlb_flags, + &tlb_nline, + &tlb_way, + &tlb_set); #ifdef INSTRUMENTATION -m_cpt_data_tlb_read++; -#endif - } - else // identity mapping + m_cpt_dtlb_read++; +#endif + } + else // identity mapping { // we take into account the paddr extension if (vci_param::N > 32) - paddr = paddr | ((paddr_t)(r_dcache_paddr_ext.read()) << 32); + paddr = paddr | ((paddr_t) (r_dcache_paddr_ext.read()) << 32); } } // end physical address computation // systematic DCACHE access depending on r_dcache_updt_req (if activated) - if ( r_mmu_mode.read() & DATA_CACHE_MASK) - { - - if ( m_dreq.valid and r_dcache_updt_req.read() ) // read DIR and write DATA - { - r_dcache.read_dir( paddr, - &cache_state, - &cache_way, - &cache_set, - &cache_word ); - - r_dcache.write( r_dcache_save_cache_way.read(), - r_dcache_save_cache_set.read(), - r_dcache_save_cache_word.read(), - r_dcache_save_wdata.read(), - r_dcache_save_be.read() ); + if (r_mmu_mode.read() & DATA_CACHE_MASK) + { + + if (m_dreq.valid and r_dcache_updt_req.read()) // read DIR and write DATA + { + r_dcache.read_dir(paddr, + &cache_state, + &cache_way, + &cache_set, + &cache_word); + + r_dcache.write(r_dcache_save_cache_way.read(), + r_dcache_save_cache_set.read(), + r_dcache_save_cache_word.read(), + r_dcache_save_wdata.read(), + r_dcache_save_be.read()); #ifdef INSTRUMENTATION -m_cpt_dcache_dir_read++; -m_cpt_dcache_data_write++; -#endif - } - else if ( m_dreq.valid and not r_dcache_updt_req.read() ) // read DIR and DATA - { - r_dcache.read( paddr, - &cache_rdata, - &cache_way, - &cache_set, - &cache_word, - &cache_state ); + m_cpt_dcache_dir_read++; + m_cpt_dcache_data_write++; +#endif + } + else if (m_dreq.valid and not r_dcache_updt_req.read()) // read DIR and DATA + { + r_dcache.read(paddr, + &cache_rdata, + &cache_way, + &cache_set, + &cache_word, + &cache_state); #ifdef INSTRUMENTATION -m_cpt_dcache_dir_read++; -m_cpt_dcache_data_read++; -#endif - } - else if ( not m_dreq.valid and r_dcache_updt_req.read() ) // write DATA - { - r_dcache.write( r_dcache_save_cache_way.read(), - r_dcache_save_cache_set.read(), - r_dcache_save_cache_word.read(), - r_dcache_save_wdata.read(), - r_dcache_save_be.read() ); + m_cpt_dcache_dir_read++; + m_cpt_dcache_data_read++; +#endif + } + else if (not m_dreq.valid and r_dcache_updt_req.read()) // write DATA + { + r_dcache.write(r_dcache_save_cache_way.read(), + r_dcache_save_cache_set.read(), + r_dcache_save_cache_word.read(), + r_dcache_save_wdata.read(), + r_dcache_save_be.read()); #ifdef INSTRUMENTATION -m_cpt_dcache_data_write++; + m_cpt_dcache_data_write++; #endif } @@ -2396,35 +2378,35 @@ // DCACHE update in P1 stage can require ITLB / DTLB inval or flush - if ( r_dcache_updt_req.read() ) + if (r_dcache_updt_req.read()) { size_t way = r_dcache_save_cache_way.read(); size_t set = r_dcache_save_cache_set.read(); - if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) - { - tlb_inval_required = true; - r_dcache_tlb_inval_set = 0; - r_dcache_tlb_inval_line = r_dcache_save_paddr.read()>> - (uint32_log2(m_dcache_words<<2)); - - r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY; - } - else if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD ) + if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_IN_TLB) + { + tlb_inval_required = true; + r_dcache_tlb_inval_set = 0; + r_dcache_tlb_inval_line = r_dcache_save_paddr.read() >> + (uint32_log2(m_dcache_words << 2)); + r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_DIRTY; + } + else if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_CONTAINS_PTD) { r_itlb.reset(); r_dtlb.reset(); - - r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY; + r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_DIRTY; } #if DEBUG_DCACHE -if ( m_debug_activated ) -std::cout << " " - << " Cache update in P1 stage" << std::dec - << " / WAY = " << r_dcache_save_cache_way.read() - << " / SET = " << r_dcache_save_cache_set.read() - << " / WORD = " << r_dcache_save_cache_word.read() << std::hex - << " / WDATA = " << r_dcache_save_wdata.read() - << " / BE = " << r_dcache_save_be.read() << std::endl; + if (m_debug_activated) + { + std::cout << " " + << " Cache update in P1 stage" << std::dec + << " / WAY = " << r_dcache_save_cache_way.read() + << " / SET = " << r_dcache_save_cache_set.read() + << " / WORD = " << r_dcache_save_cache_word.read() << std::hex + << " / WDATA = " << r_dcache_save_wdata.read() + << " / BE = " << r_dcache_save_be.read() << std::endl; + } #endif } // end test TLB inval @@ -2433,18 +2415,17 @@ // Miss if the write request is non cacheable, and there is a pending // non cacheable write, or if the write buffer is full. - if ( r_dcache_wbuf_req.read() ) - { - bool wok = r_wbuf.write( r_dcache_save_paddr.read(), - r_dcache_save_be.read(), - r_dcache_save_wdata.read(), - true ); -/*#ifdef INSTRUMENTATION -m_cpt_wbuf_write++; -#endif*/ - - if ( not wok ) // miss if write buffer full + if (r_dcache_wbuf_req.read()) + { + bool wok = r_wbuf.write(r_dcache_save_paddr.read(), + r_dcache_save_be.read(), + r_dcache_save_wdata.read(), + true); +#ifdef INSTRUMENTATION + m_cpt_wbuf_write++; +#endif + if (not wok) // miss if write buffer full { wbuf_write_miss = true; - } + } } // end WBUF update @@ -2453,5 +2434,5 @@ // itlb/dtlb invalidation self-request - if ( tlb_inval_required ) + if (tlb_inval_required) { r_dcache_fsm_scan_save = r_dcache_fsm.read(); @@ -2460,5 +2441,5 @@ // coherence clack request (from DSPIN CLACK) - else if ( r_dcache_clack_req.read() ) + else if (r_dcache_clack_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -2466,5 +2447,5 @@ } // coherence request (from CC_RECEIVE FSM) - else if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + else if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -2475,5 +2456,5 @@ // we don't take the processor request, and registers // are frozen in case of wbuf_write_miss - else if ( m_dreq.valid and not wbuf_write_miss ) + else if (m_dreq.valid and not wbuf_write_miss) { // register processor request and DCACHE response @@ -2491,5 +2472,5 @@ if (m_dreq.type == iss_t::XTN_READ) { - int xtn_opcode = (int)m_dreq.addr/4; + int xtn_opcode = (int)m_dreq.addr / 4; // checking processor mode: @@ -2505,5 +2486,5 @@ else { - switch( xtn_opcode ) + switch (xtn_opcode) { case iss_t::XTN_INS_ERROR_TYPE: @@ -2580,5 +2561,5 @@ default: - r_mmu_detr = MMU_READ_UNDEFINED_XTN; + r_mmu_detr = MMU_READ_UNDEFINED_XTN; r_mmu_dbvar = m_dreq.addr; m_drsp.valid = true; @@ -2598,14 +2579,14 @@ else if (m_dreq.type == iss_t::XTN_WRITE) { - int xtn_opcode = (int)m_dreq.addr/4; + int xtn_opcode = (int) m_dreq.addr / 4; r_dcache_xtn_opcode = xtn_opcode; // checking processor mode: - if ( (m_dreq.mode == iss_t::MODE_USER) && - (xtn_opcode != iss_t::XTN_SYNC) && - (xtn_opcode != iss_t::XTN_DCACHE_INVAL) && - (xtn_opcode != iss_t::XTN_DCACHE_FLUSH) && - (xtn_opcode != iss_t::XTN_ICACHE_INVAL) && - (xtn_opcode != iss_t::XTN_ICACHE_FLUSH) ) + if ((m_dreq.mode == iss_t::MODE_USER) && + (xtn_opcode != iss_t::XTN_SYNC) && + (xtn_opcode != iss_t::XTN_DCACHE_INVAL) && + (xtn_opcode != iss_t::XTN_DCACHE_FLUSH) && + (xtn_opcode != iss_t::XTN_ICACHE_INVAL) && + (xtn_opcode != iss_t::XTN_ICACHE_FLUSH)) { r_mmu_detr = MMU_WRITE_PRIVILEGE_VIOLATION; @@ -2618,32 +2599,32 @@ else { - switch( xtn_opcode ) + switch (xtn_opcode) { - case iss_t::XTN_PTPR: // itlb & dtlb must be flushed + case iss_t::XTN_PTPR: // itlb & dtlb must be flushed r_dcache_xtn_req = true; r_dcache_fsm = DCACHE_XTN_SWITCH; break; - case iss_t::XTN_TLB_MODE: // no cache or tlb access - r_mmu_mode = m_dreq.wdata; - m_drsp.valid = true; - r_dcache_fsm = DCACHE_IDLE; + case iss_t::XTN_TLB_MODE: // no cache or tlb access + r_mmu_mode = m_dreq.wdata; + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; break; - case iss_t::XTN_DTLB_INVAL: // dtlb access - r_dcache_fsm = DCACHE_XTN_DT_INVAL; + case iss_t::XTN_DTLB_INVAL: // dtlb access + r_dcache_fsm = DCACHE_XTN_DT_INVAL; break; - case iss_t::XTN_ITLB_INVAL: // itlb access + case iss_t::XTN_ITLB_INVAL: // itlb access r_dcache_xtn_req = true; r_dcache_fsm = DCACHE_XTN_IT_INVAL; break; - case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access - r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA; + case iss_t::XTN_DCACHE_INVAL: // dcache, dtlb & itlb access + r_dcache_fsm = DCACHE_XTN_DC_INVAL_VA; break; - case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access - r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA; + case iss_t::XTN_MMU_DCACHE_PA_INV: // dcache, dtlb & itlb access + r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA; if (sizeof(paddr_t) <= 32) { @@ -2659,47 +2640,47 @@ break; - case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset + case iss_t::XTN_DCACHE_FLUSH: // itlb and dtlb must be reset r_dcache_flush_count = 0; - r_dcache_fsm = DCACHE_XTN_DC_FLUSH; + r_dcache_fsm = DCACHE_XTN_DC_FLUSH; break; - case iss_t::XTN_ICACHE_INVAL: // icache and itlb access + case iss_t::XTN_ICACHE_INVAL: // icache and itlb access r_dcache_xtn_req = true; r_dcache_fsm = DCACHE_XTN_IC_INVAL_VA; break; - case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access + case iss_t::XTN_MMU_ICACHE_PA_INV: // icache access r_dcache_xtn_req = true; r_dcache_fsm = DCACHE_XTN_IC_INVAL_PA; break; - case iss_t::XTN_ICACHE_FLUSH: // icache access + case iss_t::XTN_ICACHE_FLUSH: // icache access r_dcache_xtn_req = true; r_dcache_fsm = DCACHE_XTN_IC_FLUSH; break; - case iss_t::XTN_SYNC: // wait until write buffer empty - r_dcache_fsm = DCACHE_XTN_SYNC; + case iss_t::XTN_SYNC: // wait until write buffer empty + r_dcache_fsm = DCACHE_XTN_SYNC; break; - case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access - r_mmu_word_lo = m_dreq.wdata; - m_drsp.valid = true; - r_dcache_fsm = DCACHE_IDLE; + case iss_t::XTN_MMU_WORD_LO: // no cache or tlb access + r_mmu_word_lo = m_dreq.wdata; + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; break; - case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access - r_mmu_word_hi = m_dreq.wdata; - m_drsp.valid = true; - r_dcache_fsm = DCACHE_IDLE; + case iss_t::XTN_MMU_WORD_HI: // no cache or tlb access + r_mmu_word_hi = m_dreq.wdata; + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; break; - case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access + case iss_t::XTN_MMU_LL_RESET: // no cache or tlb access r_dcache_llsc_valid = false; - m_drsp.valid = true; - r_dcache_fsm = DCACHE_IDLE; + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; break; - case iss_t::XTN_DATA_PADDR_EXT: // no cache or tlb access + case iss_t::XTN_DATA_PADDR_EXT: // no cache or tlb access r_dcache_paddr_ext = m_dreq.wdata; m_drsp.valid = true; @@ -2707,13 +2688,13 @@ break; - case iss_t::XTN_INST_PADDR_EXT: // no cache or tlb access + case iss_t::XTN_INST_PADDR_EXT: // no cache or tlb access r_dcache_xtn_req = true; r_dcache_fsm = DCACHE_XTN_IC_PADDR_EXT; break; - case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action - case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action - m_drsp.valid = true; - r_dcache_fsm = DCACHE_IDLE; + case iss_t::XTN_ICACHE_PREFETCH: // not implemented : no action + case iss_t::XTN_DCACHE_PREFETCH: // not implemented : no action + m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; break; @@ -2739,26 +2720,27 @@ else { - bool valid_req; - bool cacheable; - - if ( not (r_mmu_mode.read() & DATA_TLB_MASK) ) // dtlb not activated - { - valid_req = true; - - if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false; + bool valid_req; + bool cacheable; + + if (not (r_mmu_mode.read() & DATA_TLB_MASK)) // dtlb not activated + { + valid_req = true; + + if (not (r_mmu_mode.read() & DATA_CACHE_MASK)) cacheable = false; else cacheable = m_cacheability_table[(uint64_t)m_dreq.addr]; } - else // dtlb activated - { - if ( tlb_hit ) // tlb hit + else // dtlb activated + { + if (tlb_hit) // tlb hit { // cacheability - if ( not (r_mmu_mode.read() & DATA_CACHE_MASK) ) cacheable = false; + if (not (r_mmu_mode.read() & DATA_CACHE_MASK)) cacheable = false; else cacheable = tlb_flags.c; + // access rights checking - if ( not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER)) + if (not tlb_flags.u and (m_dreq.mode == iss_t::MODE_USER)) { - if ( (m_dreq.type == iss_t::DATA_READ) or - (m_dreq.type == iss_t::DATA_LL) ) + if ((m_dreq.type == iss_t::DATA_READ) or + (m_dreq.type == iss_t::DATA_LL)) { r_mmu_detr = MMU_READ_PRIVILEGE_VIOLATION; @@ -2774,12 +2756,14 @@ m_drsp.rdata = 0; #if DEBUG_DCACHE -if ( m_debug_activated ) -std::cout << " " - << " HIT in dtlb, but privilege violation" << std::endl; + if (m_debug_activated) + { + std::cout << " " + << " HIT in dtlb, but privilege violation" << std::endl; + } #endif } - else if ( not tlb_flags.w and + else if (not tlb_flags.w and ((m_dreq.type == iss_t::DATA_WRITE) or - (m_dreq.type == iss_t::DATA_SC)) ) + (m_dreq.type == iss_t::DATA_SC))) { r_mmu_detr = MMU_WRITE_ACCES_VIOLATION; @@ -2790,24 +2774,26 @@ m_drsp.rdata = 0; #if DEBUG_DCACHE -if ( m_debug_activated ) -std::cout << " " - << " HIT in dtlb, but writable violation" << std::endl; + if (m_debug_activated) + { + std::cout << " " + << " HIT in dtlb, but writable violation" << std::endl; + } #endif } else { - valid_req = true; + valid_req = true; } } - else // tlb miss + else // tlb miss { - valid_req = false; - r_dcache_tlb_vaddr = m_dreq.addr; - r_dcache_tlb_ins = false; - r_dcache_fsm = DCACHE_TLB_MISS; + valid_req = false; + r_dcache_tlb_vaddr = m_dreq.addr; + r_dcache_tlb_ins = false; + r_dcache_fsm = DCACHE_TLB_MISS; } } // end DTLB activated - if ( valid_req ) // processor request is valid (after MMU check) + if (valid_req) // processor request is valid (after MMU check) { // READ request @@ -2815,13 +2801,13 @@ // We request a VCI transaction to CMD FSM if miss or uncachable - if ( ((m_dreq.type == iss_t::DATA_READ)) - and not r_dcache_updt_req.read() ) + if (((m_dreq.type == iss_t::DATA_READ)) + and not r_dcache_updt_req.read()) { - if ( cacheable ) // cacheable read + if (cacheable) // cacheable read { - if ( cache_state == CACHE_SLOT_STATE_EMPTY ) // cache miss + if (cache_state == CACHE_SLOT_STATE_EMPTY) // cache miss { #ifdef INSTRUMENTATION -m_cpt_data_miss++; + m_cpt_dcache_miss++; #endif // request a VCI DMISS transaction @@ -2831,19 +2817,23 @@ r_dcache_fsm = DCACHE_MISS_SELECT; #if DEBUG_DCACHE -if ( m_debug_activated ) -std::cout << " " - << " READ MISS in dcache" - << " / PADDR = " << std::hex << paddr << std::endl; + if (m_debug_activated) + { + std::cout << " " + << " READ MISS in dcache" + << " / PADDR = " << std::hex << paddr << std::endl; + } #endif } - else if (cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup + else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup { // stalled until cleanup is acknowledged r_dcache_fsm = DCACHE_IDLE; #if DEBUG_DCACHE -if ( m_debug_activated ) -std::cout << " " - << " Pending cleanup, stalled until cleanup acknowledge" - << " / PADDR = " << std::hex << paddr << std::endl; + if (m_debug_activated) + { + std::cout << " " + << " Pending cleanup, stalled until cleanup acknowledge" + << " / PADDR = " << std::hex << paddr << std::endl; + } #endif } @@ -2851,31 +2841,35 @@ { #ifdef INSTRUMENTATION -m_cpt_data_read++; + m_cpt_data_read++; #endif // returns data to processor - m_drsp.valid = true; - m_drsp.error = false; - m_drsp.rdata = cache_rdata; + m_drsp.valid = true; + m_drsp.error = false; + m_drsp.rdata = cache_rdata; #if DEBUG_DCACHE -if ( m_debug_activated ) -std::cout << " " - << " READ HIT in dcache" - << " : PADDR = " << std::hex << paddr - << " / DATA = " << std::hex << cache_rdata << std::dec << std::endl; + if (m_debug_activated) + { + std::cout << " " + << " READ HIT in dcache" + << " : PADDR = " << std::hex << paddr + << " / DATA = " << std::hex << cache_rdata << std::dec << std::endl; + } #endif } } - else // uncacheable read + else // uncacheable read { - r_dcache_vci_paddr = paddr; - r_dcache_vci_unc_be = m_dreq.be; - r_dcache_vci_unc_write = false; - r_dcache_vci_unc_req = true; - r_dcache_fsm = DCACHE_UNC_WAIT; + r_dcache_vci_paddr = paddr; + r_dcache_vci_unc_be = m_dreq.be; + r_dcache_vci_unc_write = false; + r_dcache_vci_unc_req = true; + r_dcache_fsm = DCACHE_UNC_WAIT; #if DEBUG_DCACHE -if ( m_debug_activated ) -std::cout << " " - << " READ UNCACHEABLE in dcache" - << " / PADDR = " << std::hex << paddr << std::endl; + if (m_debug_activated) + { + std::cout << " " + << " READ UNCACHEABLE in dcache" + << " / PADDR = " << std::hex << paddr << std::endl; + } #endif } @@ -2908,55 +2902,56 @@ // physical address) are registered in r_dcache_save registers, // and the write will be done in the P1 pipeline stage. - else if ( m_dreq.type == iss_t::DATA_WRITE ) + else if (m_dreq.type == iss_t::DATA_WRITE) { - if ( (r_mmu_mode.read() & DATA_TLB_MASK ) - and not tlb_flags.d ) // Dirty bit must be set + if ((r_mmu_mode.read() & DATA_TLB_MASK) + and not tlb_flags.d) // Dirty bit must be set { // The PTE physical address is obtained from the nline value (dtlb), // and from the virtual address (word index) - if ( tlb_flags.b ) // PTE1 + if (tlb_flags.b) // PTE1 { - r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) | - (paddr_t)((m_dreq.addr>>19) & 0x3c); + r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) | + (paddr_t) ((m_dreq.addr >> 19) & 0x3c); } - else // PTE2 + else // PTE2 { - r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) | - (paddr_t)((m_dreq.addr>>9) & 0x38); + r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) | + (paddr_t) ((m_dreq.addr >> 9) & 0x38); } - r_dcache_fsm = DCACHE_DIRTY_GET_PTE; + r_dcache_fsm = DCACHE_DIRTY_GET_PTE; } - else // Write request accepted + else // Write request accepted { #ifdef INSTRUMENTATION -m_cpt_data_write++; + m_cpt_data_write++; #endif // cleaning llsc buffer if address matching - if ( paddr == r_dcache_llsc_paddr.read() ) + if (paddr == r_dcache_llsc_paddr.read()) r_dcache_llsc_valid = false; - if (not cacheable) + if (not cacheable) // uncacheable write { - r_dcache_vci_paddr = paddr; - r_dcache_vci_wdata = m_dreq.wdata; - r_dcache_vci_unc_write = true; - r_dcache_vci_unc_be = m_dreq.be; - r_dcache_vci_unc_req = true; - r_dcache_fsm = DCACHE_UNC_WAIT; + r_dcache_vci_paddr = paddr; + r_dcache_vci_wdata = m_dreq.wdata; + r_dcache_vci_unc_write = true; + r_dcache_vci_unc_be = m_dreq.be; + r_dcache_vci_unc_req = true; + r_dcache_fsm = DCACHE_UNC_WAIT; } // activating P1 stage - else if( (cache_state != CACHE_SLOT_STATE_ZOMBI) && (cache_state != CACHE_SLOT_STATE_EMPTY) ) + else if ((cache_state != CACHE_SLOT_STATE_ZOMBI) and + (cache_state != CACHE_SLOT_STATE_EMPTY)) { - wbuf_request = (cache_state == CACHE_SLOT_STATE_VALID_CC); //write to L2 only if CC + wbuf_request = (cache_state == CACHE_SLOT_STATE_VALID_CC); updt_request = true; m_drsp.valid = true; - if ( cache_state == CACHE_SLOT_STATE_VALID_NCC ) + if (cache_state == CACHE_SLOT_STATE_VALID_NCC) { - if ( r_dcache_content_state[cache_way*m_dcache_sets+cache_set] == LINE_CACHE_DATA_NOT_DIRTY ) + if (r_dcache_content_state[cache_way * m_dcache_sets + cache_set] == LINE_CACHE_DATA_NOT_DIRTY) { - r_dcache_content_state[cache_way*m_dcache_sets+cache_set] = LINE_CACHE_DATA_DIRTY; + r_dcache_content_state[cache_way * m_dcache_sets + cache_set] = LINE_CACHE_DATA_DIRTY; } - //dirty bit with word granularity (only for stats) - r_dcache_dirty_word[(cache_way*m_dcache_sets +cache_set)*m_dcache_words+cache_word] = 1; + // dirty bit with word granularity (only for stats) + r_dcache_dirty_word[(cache_way * m_dcache_sets + cache_set) * m_dcache_words + cache_word] = 1; m_cpt_data_write_back ++; } @@ -2971,16 +2966,15 @@ // cleanup and therefore overwrite the new value of // writing that is more current than the data - // contained in the cleanup . + // contained in the cleanup. // TODO : MAYBE NEED TO OPTIMIZE - else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) + else if (cache_state == CACHE_SLOT_STATE_ZOMBI) { m_drsp.valid = false; r_dcache_fsm = DCACHE_IDLE; // STAT : WRITE ON ZOMBI NCC LINE - if (r_dcache_zombi_ncc[cache_way*m_dcache_sets+cache_set] == true) + if (r_dcache_zombi_ncc[cache_way * m_dcache_sets + cache_set] == true) { m_cpt_data_write_on_zombi_ncc++; } - m_cpt_data_write_on_zombi++; } @@ -2994,13 +2988,14 @@ } #if DEBUG_DCACHE -if ( m_debug_activated ) -std::cout << " " - << " WRITE REQ " - << " / wbuf_request = " << wbuf_request - << " / updt_request = " << updt_request - << " / cache_state = " << cache_state - << " / PADDR = " << std::hex << paddr << std::endl; -#endif - + if (m_debug_activated) + { + std::cout << " " + << " WRITE REQ " + << " / wbuf_request = " << wbuf_request + << " / updt_request = " << updt_request + << " / cache_state = " << cache_state + << " / PADDR = " << std::hex << paddr << std::dec << std::endl; + } +#endif } // end WRITE @@ -3015,34 +3010,34 @@ // We don't check a possible write hit in dcache, as the cache update // is done by the coherence transaction induced by the SC... - else if ( m_dreq.type == iss_t::DATA_SC ) + else if (m_dreq.type == iss_t::DATA_SC) { - if ( (r_mmu_mode.read() & DATA_TLB_MASK ) - and not tlb_flags.d ) // Dirty bit must be set + if ((r_mmu_mode.read() & DATA_TLB_MASK) + and not tlb_flags.d) // Dirty bit must be set { // The PTE physical address is obtained from the nline value (dtlb), // and the word index (virtual address) - if ( tlb_flags.b ) // PTE1 + if (tlb_flags.b) // PTE1 { - r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) | - (paddr_t)((m_dreq.addr>>19) & 0x3c); + r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) | + (paddr_t) ((m_dreq.addr >> 19) & 0x3c); } - else // PTE2 + else // PTE2 { - r_dcache_dirty_paddr = (paddr_t)(tlb_nline*(m_dcache_words<<2)) | - (paddr_t)((m_dreq.addr>>9) & 0x38); + r_dcache_dirty_paddr = (paddr_t) (tlb_nline * (m_dcache_words << 2)) | + (paddr_t) ((m_dreq.addr >> 9) & 0x38); } - r_dcache_fsm = DCACHE_DIRTY_GET_PTE; + r_dcache_fsm = DCACHE_DIRTY_GET_PTE; m_drsp.valid = false; m_drsp.error = false; m_drsp.rdata = 0; } - else // SC request accepted + else // SC request accepted { #ifdef INSTRUMENTATION -m_cpt_data_sc++; + m_cpt_data_sc++; #endif // checking local success - if( r_dcache_llsc_valid.read() and - (r_dcache_llsc_paddr.read() == paddr) ) // local success + if (r_dcache_llsc_valid.read() and + (r_dcache_llsc_paddr.read() == paddr)) // local success { // request an SC CMD and go to DCACHE_SC_WAIT state @@ -3052,5 +3047,5 @@ r_dcache_fsm = DCACHE_SC_WAIT; } - else // local fail + else // local fail { m_drsp.valid = true; @@ -3065,5 +3060,5 @@ // itlb miss request - else if ( r_icache_tlb_miss_req.read() and not wbuf_write_miss ) + else if (r_icache_tlb_miss_req.read() and not wbuf_write_miss) { r_dcache_tlb_ins = true; @@ -3091,29 +3086,29 @@ // r_mmu_ins_* or r_mmu_data* error reporting registers. { - uint32_t ptba = 0; - bool bypass; - paddr_t pte_paddr; + uint32_t ptba = 0; + bool bypass; + paddr_t pte_paddr; // evaluate bypass in order to skip first level page table access - if ( r_dcache_tlb_ins.read() ) // itlb miss + if (r_dcache_tlb_ins.read()) // itlb miss { bypass = r_itlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba); } - else // dtlb miss + else // dtlb miss { bypass = r_dtlb.get_bypass(r_dcache_tlb_vaddr.read(), &ptba); } - if ( not bypass ) // Try to read PTE1/PTD1 in dcache - { - pte_paddr = (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2)) | - ((((paddr_t)r_dcache_tlb_vaddr.read()) >> PAGE_M_NBITS) << 2); + if (not bypass) // Try to read PTE1/PTD1 in dcache + { + pte_paddr = (((paddr_t) r_mmu_ptpr.read()) << (INDEX1_NBITS + 2)) | + ((((paddr_t) r_dcache_tlb_vaddr.read()) >> PAGE_M_NBITS) << 2); r_dcache_tlb_paddr = pte_paddr; r_dcache_fsm = DCACHE_TLB_PTE1_GET; } - else // Try to read PTE2 in dcache - { - pte_paddr = (paddr_t)ptba << PAGE_K_NBITS | - (paddr_t)(r_dcache_tlb_vaddr.read()&PTD_ID2_MASK)>>(PAGE_K_NBITS-3); + else // Try to read PTE2 in dcache + { + pte_paddr = (paddr_t) ptba << PAGE_K_NBITS | + (paddr_t) (r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> (PAGE_K_NBITS - 3); r_dcache_tlb_paddr = pte_paddr; r_dcache_fsm = DCACHE_TLB_PTE2_GET; @@ -3121,15 +3116,15 @@ #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - if ( r_dcache_tlb_ins.read() ) - std::cout << " ITLB miss"; - else - std::cout << " DTLB miss"; - std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read() - << " / ptpr = " << (((paddr_t)r_mmu_ptpr.read()) << (INDEX1_NBITS+2)) - << " / BYPASS = " << bypass - << " / PTE_ADR = " << pte_paddr << std::endl; -} + if (m_debug_activated) + { + if (r_dcache_tlb_ins.read()) + std::cout << " ITLB miss"; + else + std::cout << " DTLB miss"; + std::cout << " / VADDR = " << std::hex << r_dcache_tlb_vaddr.read() + << " / ptpr = " << (((paddr_t) r_mmu_ptpr.read()) << (INDEX1_NBITS + 2)) + << " / BYPASS = " << bypass + << " / PTE_ADR = " << pte_paddr << std::endl; + } #endif @@ -3137,8 +3132,8 @@ } ///////////////////////// - case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache + case DCACHE_TLB_PTE1_GET: // try to read a PT1 entry in dcache { // coherence clack request (from DSPIN CLACK) - if ( r_dcache_clack_req.read() ) + if (r_dcache_clack_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3148,5 +3143,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3155,26 +3150,25 @@ } - uint32_t entry; - size_t way; - size_t set; - size_t word; - int cache_state; - r_dcache.read( r_dcache_tlb_paddr.read(), - &entry, - &way, - &set, - &word, - &cache_state ); - + uint32_t entry; + size_t way; + size_t set; + size_t word; + int cache_state; + r_dcache.read(r_dcache_tlb_paddr.read(), + &entry, + &way, + &set, + &word, + &cache_state); #ifdef INSTRUMENTATION -m_cpt_dcache_data_read++; -m_cpt_dcache_dir_read++; -#endif - - if (( cache_state == CACHE_SLOT_STATE_VALID_NCC ) or ( cache_state == CACHE_SLOT_STATE_VALID_CC )) - { - if ( not (entry & PTE_V_MASK) ) // unmapped - { - if ( r_dcache_tlb_ins.read() ) + m_cpt_dcache_data_read++; + m_cpt_dcache_dir_read++; +#endif + if ((cache_state == CACHE_SLOT_STATE_VALID_NCC) or + (cache_state == CACHE_SLOT_STATE_VALID_CC)) + { + if (not (entry & PTE_V_MASK)) // unmapped + { + if (r_dcache_tlb_ins.read()) { r_mmu_ietr = MMU_READ_PT1_UNMAPPED; @@ -3185,68 +3179,68 @@ else { - r_mmu_detr = MMU_READ_PT1_UNMAPPED; - r_mmu_dbvar = r_dcache_tlb_vaddr.read(); - m_drsp.valid = true; - m_drsp.error = true; - } - r_dcache_fsm = DCACHE_IDLE; + r_mmu_detr = MMU_READ_PT1_UNMAPPED; + r_mmu_dbvar = r_dcache_tlb_vaddr.read(); + m_drsp.valid = true; + m_drsp.error = true; + } + r_dcache_fsm = DCACHE_IDLE; #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " HIT in dcache, but unmapped" - << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() - << std::dec << " / way = " << way - << std::dec << " / set = " << set - << std::dec << " / word = " << word - << std::hex << " / PTE1 = " << entry << std::endl; -} -#endif - - } - else if( entry & PTE_T_MASK ) // PTD : me must access PT2 + if (m_debug_activated) + { + std::cout << " HIT in dcache, but unmapped" + << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() + << std::dec << " / way = " << way + << std::dec << " / set = " << set + << std::dec << " / word = " << word + << std::hex << " / PTE1 = " << entry << std::endl; + } +#endif + + } + else if (entry & PTE_T_MASK) // PTD : me must access PT2 { // mark the cache line ac containing a PTD - r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_CONTAINS_PTD; + r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_CONTAINS_PTD; // register bypass - if ( r_dcache_tlb_ins.read() ) // itlb + if (r_dcache_tlb_ins.read()) // itlb { r_itlb.set_bypass(r_dcache_tlb_vaddr.read(), - entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1), - r_dcache_tlb_paddr.read() / (m_icache_words<<2) ); - } - else // dtlb + entry & ((1 << (m_paddr_nbits - PAGE_K_NBITS)) - 1), + r_dcache_tlb_paddr.read() / (m_icache_words << 2)); + } + else // dtlb { r_dtlb.set_bypass(r_dcache_tlb_vaddr.read(), - entry & ((1 << (m_paddr_nbits-PAGE_K_NBITS)) - 1), - r_dcache_tlb_paddr.read() / (m_dcache_words<<2) ); + entry & ((1 << (m_paddr_nbits - PAGE_K_NBITS)) - 1), + r_dcache_tlb_paddr.read() / (m_dcache_words << 2)); } r_dcache_tlb_paddr = - (paddr_t)(entry & ((1<<(m_paddr_nbits-PAGE_K_NBITS))-1)) << PAGE_K_NBITS | - (paddr_t)(((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); - r_dcache_fsm = DCACHE_TLB_PTE2_GET; + (paddr_t) (entry & ((1 << (m_paddr_nbits - PAGE_K_NBITS)) - 1)) << PAGE_K_NBITS | + (paddr_t) (((r_dcache_tlb_vaddr.read() & PTD_ID2_MASK) >> PAGE_K_NBITS) << 3); + r_dcache_fsm = DCACHE_TLB_PTE2_GET; #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " HIT in dcache" - << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() - << std::dec << " / way = " << way - << std::dec << " / set = " << set - << std::dec << " / word = " << word - << std::hex << " / PTD = " << entry << std::endl; -} -#endif - } - else // PTE1 : we must update the TLB - { - r_dcache_content_state[m_icache_sets*way+set] = LINE_CACHE_IN_TLB; + if (m_debug_activated) + { + std::cout << " HIT in dcache" + << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() + << std::dec << " / way = " << way + << std::dec << " / set = " << set + << std::dec << " / word = " << word + << std::hex << " / PTD = " << entry << std::endl; + } +#endif + } + else // PTE1 : we must update the TLB + { + r_dcache_content_state[m_dcache_sets * way + set] = LINE_CACHE_IN_TLB; r_dcache_tlb_pte_flags = entry; r_dcache_fsm = DCACHE_TLB_PTE1_SELECT; - r_cas_islocal = (cache_state == CACHE_SLOT_STATE_VALID_NCC);//do not check L2 if NCC: the CAS is necessarily a success + r_cas_islocal = (cache_state == CACHE_SLOT_STATE_VALID_NCC); // do not check L2 if NCC: the CAS is necessarily a success r_cas_local_way = way; r_cas_local_set = set; @@ -3254,37 +3248,37 @@ #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " HIT in dcache" - << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() - << std::dec << " / way = " << way - << std::dec << " / set = " << set - << std::dec << " / word = " << word - << std::hex << " / PTE1 = " << entry << std::endl; -} -#endif - } - } - else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup + if (m_debug_activated) + { + std::cout << " HIT in dcache" + << std::hex << " / paddr = " << r_dcache_tlb_paddr.read() + << std::dec << " / way = " << way + << std::dec << " / set = " << set + << std::dec << " / word = " << word + << std::hex << " / PTE1 = " << entry << std::endl; + } +#endif + } + } + else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup { // stalled until cleanup is acknowledged - r_dcache_fsm = DCACHE_TLB_PTE1_GET; - } - else // we must load the missing cache line in dcache - { - r_dcache_vci_miss_req = true; - r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); - r_dcache_save_paddr = r_dcache_tlb_paddr.read(); - r_dcache_miss_type = PTE1_MISS; - r_dcache_fsm = DCACHE_MISS_SELECT; + r_dcache_fsm = DCACHE_TLB_PTE1_GET; + } + else // we must load the missing cache line in dcache + { + r_dcache_vci_miss_req = true; + r_dcache_vci_paddr = r_dcache_tlb_paddr.read(); + r_dcache_save_paddr = r_dcache_tlb_paddr.read(); + r_dcache_miss_type = PTE1_MISS; + r_dcache_fsm = DCACHE_MISS_SELECT; #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " MISS in dcache:" - << " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl; -} + if (m_debug_activated) + { + std::cout << " MISS in dcache:" + << " PTE1 address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl; + } #endif } @@ -3292,27 +3286,27 @@ } //////////////////////////// - case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1 + case DCACHE_TLB_PTE1_SELECT: // select a slot for PTE1 { size_t way; size_t set; - if ( r_dcache_tlb_ins.read() ) - { - r_itlb.select( r_dcache_tlb_vaddr.read(), - true, // PTE1 - &way, - &set ); + if (r_dcache_tlb_ins.read()) + { + r_itlb.select(r_dcache_tlb_vaddr.read(), + true, // PTE1 + &way, + &set); #ifdef INSTRUMENTATION -m_cpt_ins_tlb_read++; + m_cpt_itlb_read++; #endif } else { - r_dtlb.select( r_dcache_tlb_vaddr.read(), - true, // PTE1 - &way, - &set ); + r_dtlb.select(r_dcache_tlb_vaddr.read(), + true, // PTE1 + &way, + &set); #ifdef INSTRUMENTATION -m_cpt_data_tlb_read++; + m_cpt_dtlb_read++; #endif } @@ -3322,15 +3316,15 @@ #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - if ( r_dcache_tlb_ins.read() ) - std::cout << " Select a slot in ITLB:"; - else - std::cout << " Select a slot in DTLB:"; - std::cout << " way = " << std::dec << way - << " / set = " << set << std::endl; -} + if (m_debug_activated) + { + if (r_dcache_tlb_ins.read()) + std::cout << " Select a slot in ITLB:"; + else + std::cout << " Select a slot in DTLB:"; + std::cout << " way = " << std::dec << way + << " / set = " << set << std::endl; + } #endif break; @@ -3343,8 +3337,8 @@ // the coherence mechanism. { - paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2); - uint32_t pte = r_dcache_tlb_pte_flags.read(); - bool pt_updt = false; - bool local = true; + paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2); + uint32_t pte = r_dcache_tlb_pte_flags.read(); + bool pt_updt = false; + bool local = true; // We should compute the access locality: @@ -3355,22 +3349,22 @@ // As long as this computation is not done, all access are local. - if ( local ) // local access - { - if ( not ((pte & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit + if (local) // local access + { + if (not ((pte & PTE_L_MASK) == PTE_L_MASK)) // we must set the L bit { pt_updt = true; - r_dcache_vci_cas_old = pte; - r_dcache_vci_cas_new = pte | PTE_L_MASK; + r_dcache_vci_cas_old = pte; + r_dcache_vci_cas_new = pte | PTE_L_MASK; pte = pte | PTE_L_MASK; r_dcache_tlb_pte_flags = pte; } } - else // remote access - { - if ( not ((pte & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit + else // remote access + { + if (not ((pte & PTE_R_MASK) == PTE_R_MASK)) // we must set the R bit { pt_updt = true; - r_dcache_vci_cas_old = pte; - r_dcache_vci_cas_new = pte | PTE_R_MASK; + r_dcache_vci_cas_old = pte; + r_dcache_vci_cas_new = pte | PTE_R_MASK; pte = pte | PTE_R_MASK; r_dcache_tlb_pte_flags = pte; @@ -3378,52 +3372,52 @@ } - if ( not pt_updt ) // update TLB and return - { - if ( r_dcache_tlb_ins.read() ) - { - r_itlb.write( true, // 2M page - pte, - 0, // argument unused for a PTE1 - r_dcache_tlb_vaddr.read(), - r_dcache_tlb_way.read(), - r_dcache_tlb_set.read(), - nline ); + if (not pt_updt) // update TLB and return + { + if (r_dcache_tlb_ins.read()) + { + r_itlb.write(true, // 2M page + pte, + 0, // argument unused for a PTE1 + r_dcache_tlb_vaddr.read(), + r_dcache_tlb_way.read(), + r_dcache_tlb_set.read(), + nline); #ifdef INSTRUMENTATION -m_cpt_ins_tlb_update_acc++; + m_cpt_itlb_write++; #endif #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " write PTE1 in ITLB" - << " / set = " << std::dec << r_dcache_tlb_set.read() - << " / way = " << r_dcache_tlb_way.read() << std::endl; - r_itlb.printTrace(); -} + if (m_debug_activated) + { + std::cout << " write PTE1 in ITLB" + << " / set = " << std::dec << r_dcache_tlb_set.read() + << " / way = " << r_dcache_tlb_way.read() << std::endl; + r_itlb.printTrace(); + } #endif } else { - r_dtlb.write( true, // 2M page - pte, - 0, // argument unused for a PTE1 - r_dcache_tlb_vaddr.read(), - r_dcache_tlb_way.read(), - r_dcache_tlb_set.read(), - nline ); + r_dtlb.write(true, // 2M page + pte, + 0, // argument unused for a PTE1 + r_dcache_tlb_vaddr.read(), + r_dcache_tlb_way.read(), + r_dcache_tlb_set.read(), + nline); #ifdef INSTRUMENTATION -m_cpt_data_tlb_update_acc++; + m_cpt_dtlb_write++; #endif #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " write PTE1 in DTLB" - << " / set = " << std::dec << r_dcache_tlb_set.read() - << " / way = " << r_dcache_tlb_way.read() << std::endl; - r_dtlb.printTrace(); -} + if (m_debug_activated) + { + std::cout << " write PTE1 in DTLB" + << " / set = " << std::dec << r_dcache_tlb_set.read() + << " / way = " << r_dcache_tlb_way.read() << std::endl; + r_dtlb.printTrace(); + } #endif } @@ -3435,10 +3429,10 @@ #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " L/R bit update required" - << std::endl; -} + if (m_debug_activated) + { + std::cout << " L/R bit update required" + << std::endl; + } #endif } @@ -3446,8 +3440,8 @@ } ///////////////////////// - case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache + case DCACHE_TLB_PTE2_GET: // Try to get a PTE2 (64 bits) in the dcache { // coherence clack request (from DSPIN CLACK) - if ( r_dcache_clack_req.read() ) + if (r_dcache_clack_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3457,5 +3451,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3464,27 +3458,28 @@ } - uint32_t pte_flags = 0; - uint32_t pte_ppn = 0; - size_t way = 0; - size_t set = 0; - size_t word = 0; - int cache_state = 0; - - r_dcache.read( r_dcache_tlb_paddr.read(), - &pte_flags, - &pte_ppn, - &way, - &set, - &word, - &cache_state ); + uint32_t pte_flags = 0; + uint32_t pte_ppn = 0; + size_t way = 0; + size_t set = 0; + size_t word = 0; + int cache_state = 0; + + r_dcache.read(r_dcache_tlb_paddr.read(), + &pte_flags, + &pte_ppn, + &way, + &set, + &word, + &cache_state); #ifdef INSTRUMENTATION -m_cpt_dcache_data_read++; -m_cpt_dcache_dir_read++; -#endif - if ((cache_state == CACHE_SLOT_STATE_VALID_CC) or (cache_state == CACHE_SLOT_STATE_VALID_NCC)) - { - if ( not (pte_flags & PTE_V_MASK) ) // unmapped - { - if ( r_dcache_tlb_ins.read() ) + m_cpt_dcache_data_read++; + m_cpt_dcache_dir_read++; +#endif + if ((cache_state == CACHE_SLOT_STATE_VALID_CC) or + (cache_state == CACHE_SLOT_STATE_VALID_NCC)) + { + if (not (pte_flags & PTE_V_MASK)) // unmapped + { + if (r_dcache_tlb_ins.read()) { r_mmu_ietr = MMU_READ_PT2_UNMAPPED; @@ -3495,29 +3490,29 @@ else { - r_mmu_detr = MMU_READ_PT2_UNMAPPED; - r_mmu_dbvar = r_dcache_tlb_vaddr.read(); - m_drsp.valid = true; - m_drsp.error = true; - } - r_dcache_fsm = DCACHE_IDLE; + r_mmu_detr = MMU_READ_PT2_UNMAPPED; + r_mmu_dbvar = r_dcache_tlb_vaddr.read(); + m_drsp.valid = true; + m_drsp.error = true; + } + r_dcache_fsm = DCACHE_IDLE; #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " HIT in dcache, but PTE unmapped" - << " PTE_FLAGS = " << std::hex << pte_flags - << " PTE_PPN = " << std::hex << pte_ppn << std::endl; -} -#endif - } - else // mapped : we must update the TLB - { - r_dcache_content_state[m_dcache_sets*way+set] = LINE_CACHE_IN_TLB; + if (m_debug_activated) + { + std::cout << " HIT in dcache, but PTE unmapped" + << " PTE_FLAGS = " << std::hex << pte_flags + << " PTE_PPN = " << std::hex << pte_ppn << std::endl; + } +#endif + } + else // mapped : we must update the TLB + { + r_dcache_content_state[m_dcache_sets * way + set] = LINE_CACHE_IN_TLB; r_dcache_tlb_pte_flags = pte_flags; r_dcache_tlb_pte_ppn = pte_ppn; r_dcache_fsm = DCACHE_TLB_PTE2_SELECT; - r_cas_islocal = (cache_state == CACHE_SLOT_STATE_VALID_NCC);//do not check L2 if NCC: the CAS is necessarily a success + r_cas_islocal = (cache_state == CACHE_SLOT_STATE_VALID_NCC); // do not check L2 if NCC: the CAS is necessarily a success r_cas_local_way = way; r_cas_local_set = set; @@ -3525,15 +3520,15 @@ #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " HIT in dcache:" - << " PTE_FLAGS = " << std::hex << pte_flags - << " PTE_PPN = " << std::hex << pte_ppn << std::endl; -} + if (m_debug_activated) + { + std::cout << " HIT in dcache:" + << " PTE_FLAGS = " << std::hex << pte_flags + << " PTE_PPN = " << std::hex << pte_ppn << std::endl; + } #endif } } - else if ( cache_state == CACHE_SLOT_STATE_ZOMBI ) // pending cleanup + else if (cache_state == CACHE_SLOT_STATE_ZOMBI) // pending cleanup { // stalled until cleanup is acknowledged @@ -3541,10 +3536,10 @@ #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " ZOMBI in dcache: waiting cleanup ack" - << std::endl; -} + if (m_debug_activated) + { + std::cout << " ZOMBI in dcache: waiting cleanup ack" + << std::endl; + } #endif } @@ -3558,10 +3553,10 @@ #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " MISS in dcache:" - << " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl; -} + if (m_debug_activated) + { + std::cout << " MISS in dcache:" + << " PTE address = " << std::hex << r_dcache_tlb_paddr.read() << std::endl; + } #endif } @@ -3574,37 +3569,37 @@ size_t set; - if ( r_dcache_tlb_ins.read() ) - { - r_itlb.select( r_dcache_tlb_vaddr.read(), - false, // PTE2 - &way, - &set ); + if (r_dcache_tlb_ins.read()) + { + r_itlb.select(r_dcache_tlb_vaddr.read(), + false, // PTE2 + &way, + &set); #ifdef INSTRUMENTATION -m_cpt_ins_tlb_read++; + m_cpt_itlb_read++; #endif } else { - r_dtlb.select( r_dcache_tlb_vaddr.read(), - false, // PTE2 - &way, - &set ); + r_dtlb.select(r_dcache_tlb_vaddr.read(), + false, // PTE2 + &way, + &set); #ifdef INSTRUMENTATION -m_cpt_data_tlb_read++; + m_cpt_dtlb_read++; #endif } #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - if ( r_dcache_tlb_ins.read() ) - std::cout << " Select a slot in ITLB:"; - else - std::cout << " Select a slot in DTLB:"; - std::cout << " way = " << std::dec << way - << " / set = " << set << std::endl; -} + if (m_debug_activated) + { + if (r_dcache_tlb_ins.read()) + std::cout << " Select a slot in ITLB:"; + else + std::cout << " Select a slot in DTLB:"; + std::cout << " way = " << std::dec << way + << " / set = " << set << std::endl; + } #endif r_dcache_tlb_way = way; @@ -3620,9 +3615,9 @@ // the coherence mechanism. { - paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2); - uint32_t pte_flags = r_dcache_tlb_pte_flags.read(); - uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read(); - bool pt_updt = false; - bool local = true; + paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2); + uint32_t pte_flags = r_dcache_tlb_pte_flags.read(); + uint32_t pte_ppn = r_dcache_tlb_pte_ppn.read(); + bool pt_updt = false; + bool local = true; // We should compute the access locality: @@ -3633,7 +3628,7 @@ // As long as this computation is not done, all access are local. - if ( local ) // local access - { - if ( not ((pte_flags & PTE_L_MASK) == PTE_L_MASK) ) // we must set the L bit + if (local) // local access + { + if (not ((pte_flags & PTE_L_MASK) == PTE_L_MASK)) // we must set the L bit { pt_updt = true; @@ -3646,5 +3641,5 @@ else // remote access { - if ( not ((pte_flags & PTE_R_MASK) == PTE_R_MASK) ) // we must set the R bit + if (not ((pte_flags & PTE_R_MASK) == PTE_R_MASK)) // we must set the R bit { pt_updt = true; @@ -3656,52 +3651,52 @@ } - if ( not pt_updt ) // update TLB - { - if ( r_dcache_tlb_ins.read() ) - { - r_itlb.write( false, // 4K page - pte_flags, - pte_ppn, - r_dcache_tlb_vaddr.read(), - r_dcache_tlb_way.read(), - r_dcache_tlb_set.read(), - nline ); + if (not pt_updt) // update TLB + { + if (r_dcache_tlb_ins.read()) + { + r_itlb.write(false, // 4K page + pte_flags, + pte_ppn, + r_dcache_tlb_vaddr.read(), + r_dcache_tlb_way.read(), + r_dcache_tlb_set.read(), + nline); #ifdef INSTRUMENTATION -m_cpt_ins_tlb_update_acc++; + m_cpt_itlb_write++; #endif #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " write PTE2 in ITLB" - << " / set = " << std::dec << r_dcache_tlb_set.read() - << " / way = " << r_dcache_tlb_way.read() << std::endl; - r_itlb.printTrace(); -} + if (m_debug_activated) + { + std::cout << " write PTE2 in ITLB" + << " / set = " << std::dec << r_dcache_tlb_set.read() + << " / way = " << r_dcache_tlb_way.read() << std::endl; + r_itlb.printTrace(); + } #endif } else { - r_dtlb.write( false, // 4K page - pte_flags, - pte_ppn, - r_dcache_tlb_vaddr.read(), - r_dcache_tlb_way.read(), - r_dcache_tlb_set.read(), - nline ); + r_dtlb.write(false, // 4K page + pte_flags, + pte_ppn, + r_dcache_tlb_vaddr.read(), + r_dcache_tlb_way.read(), + r_dcache_tlb_set.read(), + nline); #ifdef INSTRUMENTATION -m_cpt_data_tlb_update_acc++; + m_cpt_dtlb_write++; #endif #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " write PTE2 in DTLB" - << " / set = " << std::dec << r_dcache_tlb_set.read() - << " / way = " << r_dcache_tlb_way.read() << std::endl; - r_dtlb.printTrace(); -} + if (m_debug_activated) + { + std::cout << " write PTE2 in DTLB" + << " / set = " << std::dec << r_dcache_tlb_set.read() + << " / way = " << r_dcache_tlb_way.read() << std::endl; + r_dtlb.printTrace(); + } #endif @@ -3714,9 +3709,9 @@ #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " L/R bit update required" << std::endl; -} + if (m_debug_activated) + { + std::cout << " L/R bit update required" << std::endl; + } #endif } @@ -3729,11 +3724,11 @@ uint32_t set = r_cas_local_set.read(); uint32_t word = r_cas_local_word.read(); - paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words)+2); + paddr_t nline = r_dcache_tlb_paddr.read() >> (uint32_log2(m_dcache_words) + 2); #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " Update dcache: (L/R) bit" << std::endl; -} + if (m_debug_activated) + { + std::cout << " Update dcache: (L/R) bit" << std::endl; + } #endif @@ -3744,18 +3739,19 @@ word, r_dcache_vci_cas_new.read()); - //compteur dirty - r_dcache_dirty_word[(way*m_dcache_sets +set)*m_dcache_words+word] = 1; - - if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) - { - r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY; - r_dcache_tlb_inval_line = nline; - r_dcache_tlb_inval_set = 0; - r_dcache_fsm_scan_save = DCACHE_TLB_RETURN; - r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; + + // stats dirty words + r_dcache_dirty_word[(way * m_dcache_sets + set) * m_dcache_words + word] = 1; + + if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_IN_TLB) + { + r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_DIRTY; + r_dcache_tlb_inval_line = nline; + r_dcache_tlb_inval_set = 0; + r_dcache_fsm_scan_save = DCACHE_TLB_RETURN; + r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; break; } - if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD ) + if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_CONTAINS_PTD) { r_itlb.reset(); @@ -3764,5 +3760,5 @@ #if DEBUG_DCACHE - if ( m_debug_activated ) + if (m_debug_activated) { std::cout << " SC response received" << std::endl; -} + if (m_debug_activated) + { + std::cout << " SC response received" << std::endl; + } #endif vci_rsp_fifo_dcache_get = true; - r_dcache_fsm = DCACHE_TLB_RETURN; + r_dcache_fsm = DCACHE_TLB_RETURN; } break; } /////////////////////// - case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type + case DCACHE_TLB_RETURN: // return to caller depending on tlb miss type { #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " TLB MISS completed" << std::endl; -} -#endif - if ( r_dcache_tlb_ins.read() ) r_icache_tlb_miss_req = false; + if (m_debug_activated) + { + std::cout << " TLB MISS completed" << std::endl; + } +#endif + if (r_dcache_tlb_ins.read()) r_icache_tlb_miss_req = false; r_dcache_fsm = DCACHE_IDLE; break; @@ -3854,7 +3850,9 @@ // Caution : the itlb miss requests must be taken // to avoid dead-lock in case of simultaneous ITLB miss + // Caution : the clack and cc requests must be taken + // to avoid dead-lock { // coherence clack request (from DSPIN CLACK) - if ( r_dcache_clack_req.read() ) + if (r_dcache_clack_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3864,5 +3862,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3872,13 +3870,13 @@ // itlb miss request - if ( r_icache_tlb_miss_req.read() ) - { - r_dcache_tlb_ins = true; - r_dcache_tlb_vaddr = r_icache_vaddr_save.read(); - r_dcache_fsm = DCACHE_TLB_MISS; - break; - } - - if ( not r_dcache_xtn_req.read() ) + if (r_icache_tlb_miss_req.read()) + { + r_dcache_tlb_ins = true; + r_dcache_tlb_vaddr = r_icache_vaddr_save.read(); + r_dcache_fsm = DCACHE_TLB_MISS; + break; + } + + if (not r_dcache_xtn_req.read()) { r_dtlb.flush(); @@ -3890,10 +3888,10 @@ } ///////////////////// - case DCACHE_XTN_SYNC: // waiting until write buffer empty - // The coherence request must be taken - // as there is a risk of dead-lock + case DCACHE_XTN_SYNC: // waiting until write buffer empty + // The coherence request must be taken + // as there is a risk of dead-lock { // coherence clack request (from DSPIN CLACK) - if ( r_dcache_clack_req.read() ) + if (r_dcache_clack_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3903,5 +3901,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3910,7 +3908,7 @@ } - if ( r_wbuf.empty() ) - { - m_drsp.valid = true; + if (r_wbuf.empty()) + { + m_drsp.valid = true; r_dcache_fsm = DCACHE_IDLE; } @@ -3926,5 +3924,5 @@ { // coherence clack request (from DSPIN CLACK) - if ( r_dcache_clack_req.read() ) + if (r_dcache_clack_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3934,5 +3932,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3942,14 +3940,14 @@ // itlb miss request - if ( r_icache_tlb_miss_req.read() ) - { - r_dcache_tlb_ins = true; - r_dcache_tlb_vaddr = r_icache_vaddr_save.read(); - r_dcache_fsm = DCACHE_TLB_MISS; + if (r_icache_tlb_miss_req.read()) + { + r_dcache_tlb_ins = true; + r_dcache_tlb_vaddr = r_icache_vaddr_save.read(); + r_dcache_fsm = DCACHE_TLB_MISS; break; } // test if XTN request to icache completed - if ( not r_dcache_xtn_req.read() ) + if (not r_dcache_xtn_req.read()) { r_dcache_fsm = DCACHE_IDLE; @@ -3969,5 +3967,5 @@ { // coherence clack request (from DSPIN CLACK) - if ( r_dcache_clack_req.read() ) + if (r_dcache_clack_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3977,5 +3975,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -3984,20 +3982,20 @@ } - if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent - { - int state; - paddr_t tag; - size_t way = r_dcache_flush_count.read()/m_dcache_sets; - size_t set = r_dcache_flush_count.read()%m_dcache_sets; + if (not r_dcache_cc_send_req.read()) // blocked until previous cc_send request is sent + { + int state; + paddr_t tag; + size_t way = r_dcache_flush_count.read()/m_dcache_sets; + size_t set = r_dcache_flush_count.read()%m_dcache_sets; #ifdef INSTRUMENTATION -m_cpt_dcache_dir_read++; -#endif - r_dcache.read_dir( way, - set, - &tag, - &state ); - - if ( state == CACHE_SLOT_STATE_VALID_CC ) // inval required + m_cpt_dcache_dir_read++; +#endif + r_dcache.read_dir(way, + set, + &tag, + &state); + + if (state == CACHE_SLOT_STATE_VALID_CC) // inval required { // request cleanup @@ -4008,11 +4006,11 @@ // goes to DCACHE_XTN_DC_FLUSH_GO to inval directory - r_dcache_miss_way = way; - r_dcache_miss_set = set; + r_dcache_miss_way = way; + r_dcache_miss_set = set; + r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO; r_dcache_cc_cleanup_line_ncc = false; r_dcache_cc_cleanup_updt_data = false; - r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO; - } - else if ( state == CACHE_SLOT_STATE_VALID_NCC) + } + else if (state == CACHE_SLOT_STATE_VALID_NCC) { // request cleanup @@ -4023,27 +4021,27 @@ // goes to DCACHE_XTN_DC_FLUSH_GO to inval directory - r_dcache_miss_way = way; - r_dcache_miss_set = set; + r_dcache_miss_way = way; + r_dcache_miss_set = set; r_dcache_cc_cleanup_line_ncc = true; - if (r_dcache_content_state[m_dcache_sets*way+set] != LINE_CACHE_DATA_NOT_DIRTY)//Must send data in the cleanup + if (r_dcache_content_state[m_dcache_sets * way + set] != LINE_CACHE_DATA_NOT_DIRTY) // Must send data in the cleanup { r_dcache_xtn_flush_addr_data = (tag * m_dcache_sets + set) * m_dcache_words * 4; r_dcache_xtn_flush_data_cpt = 0; r_dcache_cc_cleanup_updt_data = true; - for (size_t w = 0; w< m_dcache_words; w++) + for (size_t w = 0; w < m_dcache_words; w++) { - m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets*way+set)*m_dcache_words + w]; + m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets * way + set) * m_dcache_words + w]; } - r_dcache_fsm = DCACHE_XTN_DC_FLUSH_DATA; + r_dcache_fsm = DCACHE_XTN_DC_FLUSH_DATA; } else { r_dcache_cc_cleanup_updt_data = false; - r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO; - } - } - else if ( r_dcache_flush_count.read() == - (m_dcache_sets*m_dcache_ways - 1) ) // last slot + r_dcache_fsm = DCACHE_XTN_DC_FLUSH_GO; + } + } + else if (r_dcache_flush_count.read() == + (m_dcache_sets * m_dcache_ways - 1)) // last slot { r_dtlb.reset(); @@ -4054,17 +4052,16 @@ // saturation counter - if ( r_dcache_flush_count.read() < (m_dcache_sets*m_dcache_ways - 1) ) + if (r_dcache_flush_count.read() < (m_dcache_sets * m_dcache_ways - 1)) r_dcache_flush_count = r_dcache_flush_count.read() + 1; } break; } - //////////////////////////// case DCACHE_XTN_DC_FLUSH_DATA: { uint32_t rdata; - size_t way; - size_t set; - size_t word; + size_t way; + size_t set; + size_t word; r_dcache.read_neutral(r_dcache_xtn_flush_addr_data.read(), @@ -4073,13 +4070,14 @@ &set, &word); - if(r_cc_send_data_fifo.wok()) + + if (r_cc_send_data_fifo.wok()) { r_dcache_xtn_flush_addr_data = r_dcache_xtn_flush_addr_data.read() + 4; - cleanup_data_updt_fifo_dcache_put = true; - cleanup_data_updt_fifo_dcache_data = rdata; + cleanup_data_updt_fifo_dcache_put = true; + cleanup_data_updt_fifo_dcache_data = rdata; r_dcache_xtn_flush_data_cpt = r_dcache_xtn_flush_data_cpt + 1; - if(r_dcache_xtn_flush_data_cpt.read() == (m_dcache_words - 1)) + if (r_dcache_xtn_flush_data_cpt.read() == (m_dcache_words - 1)) { r_dcache_xtn_flush_data_cpt = 0; @@ -4089,5 +4087,4 @@ break; } - //////////////////////////// case DCACHE_XTN_DC_FLUSH_GO: // Switch the cache slot to ZOMBI state @@ -4098,18 +4095,15 @@ size_t set = r_dcache_miss_set.read(); - r_dcache_content_state[m_dcache_sets*way+set] = LINE_CACHE_DATA_DIRTY; + r_dcache_content_state[m_dcache_sets * way + set] = LINE_CACHE_DATA_DIRTY; #ifdef INSTRUMENTATION -m_cpt_dcache_dir_write++; -#endif - - - - r_dcache.write_dir( way, - set, - CACHE_SLOT_STATE_ZOMBI ); - - if ( r_dcache_flush_count.read() == - (m_dcache_sets*m_dcache_ways - 1) ) // last slot + m_cpt_dcache_dir_write++; +#endif + r_dcache.write_dir(way, + set, + CACHE_SLOT_STATE_ZOMBI); + + if (r_dcache_flush_count.read() == + (m_dcache_sets * m_dcache_ways - 1)) // last slot { r_dtlb.reset(); @@ -4125,9 +4119,9 @@ } ///////////////////////// - case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request + case DCACHE_XTN_DT_INVAL: // handling processor XTN_DTLB_INVAL request { r_dtlb.inval(r_dcache_save_wdata.read()); - r_dcache_fsm = DCACHE_IDLE; - m_drsp.valid = true; + r_dcache_fsm = DCACHE_IDLE; + m_drsp.valid = true; break; } @@ -4138,47 +4132,47 @@ { paddr_t paddr; - bool hit; - - if ( r_mmu_mode.read() & DATA_TLB_MASK ) // dtlb activated + bool hit; + + if (r_mmu_mode.read() & DATA_TLB_MASK) // dtlb activated { #ifdef INSTRUMENTATION -m_cpt_data_tlb_read++; -#endif - hit = r_dtlb.translate( r_dcache_save_wdata.read(), - &paddr ); - } - else // dtlb not activated + m_cpt_dtlb_read++; +#endif + hit = r_dtlb.translate(r_dcache_save_wdata.read(), + &paddr); + } + else // dtlb not activated { paddr = (paddr_t)r_dcache_save_wdata.read(); if (vci_param::N > 32) paddr = paddr | ((paddr_t)(r_dcache_paddr_ext.read()) << 32); - hit = true; - } - - if ( hit ) // tlb hit + hit = true; + } + + if (hit) // tlb hit { r_dcache_save_paddr = paddr; - r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA; - } - else // tlb miss + r_dcache_fsm = DCACHE_XTN_DC_INVAL_PA; + } + else // tlb miss { #ifdef INSTRUMENTATION -m_cpt_data_tlb_miss++; -#endif - r_dcache_tlb_ins = false; // dtlb - r_dcache_tlb_vaddr = r_dcache_save_wdata.read(); - r_dcache_fsm = DCACHE_TLB_MISS; + m_cpt_dtlb_miss++; +#endif + r_dcache_tlb_ins = false; // dtlb + r_dcache_tlb_vaddr = r_dcache_save_wdata.read(); + r_dcache_fsm = DCACHE_TLB_MISS; } #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " Compute physical address" << std::hex - << " / VADDR = " << r_dcache_save_wdata.read() - << " / PADDR = " << paddr << std::endl; -} + if (m_debug_activated) + { + std::cout << " Compute physical address" << std::hex + << " / VADDR = " << r_dcache_save_wdata.read() + << " / PADDR = " << paddr << std::endl; + } #endif @@ -4190,49 +4184,49 @@ // In this state we read dcache. { - size_t way; - size_t set; - size_t word; - int state; + size_t way; + size_t set; + size_t word; + int state; #ifdef INSTRUMENTATION -m_cpt_dcache_dir_read++; -#endif - r_dcache.read_dir( r_dcache_save_paddr.read(), - &state, - &way, - &set, - &word ); - - if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC)) // inval to be done + m_cpt_dcache_dir_read++; +#endif + r_dcache.read_dir(r_dcache_save_paddr.read(), + &state, + &way, + &set, + &word); + + if ((state == CACHE_SLOT_STATE_VALID_CC) or + (state == CACHE_SLOT_STATE_VALID_NCC)) // inval to be done { r_dcache_xtn_way = way; r_dcache_xtn_set = set; r_dcache_xtn_state = state; - r_dcache_xtn_data_addr = r_dcache_save_paddr.read()&~0x3F; - - if( (state == CACHE_SLOT_STATE_VALID_NCC) and (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_NOT_DIRTY) ) + r_dcache_xtn_data_addr = r_dcache_save_paddr.read() & ~0x3F; + + if ((state == CACHE_SLOT_STATE_VALID_NCC) and + (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_DATA_NOT_DIRTY)) { m_cpt_cleanup_data_not_dirty ++; } r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO; - - } - else // miss : nothing to do - { - r_dcache_fsm = DCACHE_IDLE; - m_drsp.valid = true; + } + else // miss : nothing to do + { + r_dcache_fsm = DCACHE_IDLE; + m_drsp.valid = true; } #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " Test hit in dcache" << std::hex - << " / PADDR = " << r_dcache_save_paddr.read() << std::dec - << " / HIT = " << ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC)) - << " / SET = " << set - << " / WAY = " << way << std::endl; - //r_dcache.printTrace(); -} + if (m_debug_activated) + { + std::cout << " Test hit in dcache" << std::hex + << " / PADDR = " << r_dcache_save_paddr.read() << std::dec + << " / HIT = " << ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC)) + << " / SET = " << set + << " / WAY = " << way << std::endl; + } #endif break; @@ -4243,16 +4237,16 @@ // Test if itlb or dtlb inval is required { - if ( not r_dcache_cc_send_req.read() ) // blocked until previous cc_send request is sent - { - int state = r_dcache_xtn_state.read(); - size_t way = r_dcache_xtn_way.read(); - size_t set = r_dcache_xtn_set.read(); - paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words<<2); + if (not r_dcache_cc_send_req.read()) // blocked until previous cc_send request is sent + { + int state = r_dcache_xtn_state.read(); + size_t way = r_dcache_xtn_way.read(); + size_t set = r_dcache_xtn_set.read(); + paddr_t nline = r_dcache_save_paddr.read() / (m_dcache_words << 2); #ifdef INSTRUMENTATION -m_cpt_dcache_dir_write++; -#endif - - if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC))// request cleanup + m_cpt_dcache_dir_write++; +#endif + if ((state == CACHE_SLOT_STATE_VALID_CC) or + (state == CACHE_SLOT_STATE_VALID_NCC)) // request cleanup { r_dcache_cc_send_req = true; @@ -4263,17 +4257,17 @@ { r_dcache_cc_cleanup_line_ncc = false; - r_dcache.write_dir( way, - set, - CACHE_SLOT_STATE_ZOMBI ); + r_dcache.write_dir(way, + set, + CACHE_SLOT_STATE_ZOMBI); } else { r_dcache_cc_cleanup_line_ncc = true; - if ((r_dcache_content_state[way*m_dcache_sets+set] != LINE_CACHE_DATA_NOT_DIRTY)) //must send data + if ((r_dcache_content_state[way * m_dcache_sets + set] != LINE_CACHE_DATA_NOT_DIRTY)) //must send data { r_dcache_cc_cleanup_updt_data = true; - for (size_t w = 0; w< m_dcache_words; w++) + for (size_t w = 0; w < m_dcache_words; w++) { - m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets*way+set)*m_dcache_words + w]; + m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets * way + set) * m_dcache_words + w]; } r_dcache_fsm = DCACHE_XTN_DC_INVAL_DATA; @@ -4283,15 +4277,18 @@ { r_dcache_cc_cleanup_updt_data = false; - r_dcache.write_dir( way, - set, - CACHE_SLOT_STATE_ZOMBI ); + r_dcache.write_dir(way, + set, + CACHE_SLOT_STATE_ZOMBI); } - if( (state == CACHE_SLOT_STATE_VALID_NCC) and (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_NOT_DIRTY) ) + if ((state == CACHE_SLOT_STATE_VALID_NCC) and + (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_DATA_NOT_DIRTY)) + { m_cpt_cleanup_data_not_dirty ++; + } } } // possible itlb & dtlb invalidate - if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) + if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_IN_TLB) { r_dcache_tlb_inval_line = nline; @@ -4299,11 +4296,11 @@ r_dcache_fsm_scan_save = DCACHE_XTN_DC_INVAL_END; r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; - r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY; - } - else if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD) + r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_DIRTY; + } + else if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_CONTAINS_PTD) { r_itlb.reset(); r_dtlb.reset(); - r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY; + r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_DIRTY; r_dcache_fsm = DCACHE_IDLE; m_drsp.valid = true; @@ -4316,24 +4313,21 @@ #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " Actual dcache inval" << std::hex - << " / PADDR = " << r_dcache_save_paddr.read() << std::endl; -} + if (m_debug_activated) + { + std::cout << " Actual dcache inval" << std::hex + << " / PADDR = " << r_dcache_save_paddr.read() << std::endl; + } #endif } break; } - - /*RWT*/ ////////////////////////////// case DCACHE_XTN_DC_INVAL_DATA: { - uint32_t rdata; - size_t way = 0; // To avoid gcc warning - size_t set = 0; // To avoid gcc warning - size_t word; + size_t way = 0; // To avoid gcc warning + size_t set = 0; // To avoid gcc warning + size_t word; r_dcache.read_neutral(r_dcache_xtn_data_addr.read(), &rdata, @@ -4341,27 +4335,26 @@ &set, &word); - if(r_cc_send_data_fifo.wok()) + if (r_cc_send_data_fifo.wok()) { r_dcache_xtn_data_addr = r_dcache_xtn_data_addr.read() + 4; - cleanup_data_updt_fifo_dcache_put = true; - cleanup_data_updt_fifo_dcache_data = rdata; + cleanup_data_updt_fifo_dcache_put = true; + cleanup_data_updt_fifo_dcache_data = rdata; r_dcache_xtn_data_cpt = r_dcache_xtn_data_cpt.read() + 1; - if(r_dcache_xtn_data_cpt.read() == (m_dcache_words - 1)) + if (r_dcache_xtn_data_cpt.read() == (m_dcache_words - 1)) { r_dcache_xtn_state = CACHE_SLOT_STATE_ZOMBI; r_dcache_xtn_data_cpt = 0; r_dcache_fsm = DCACHE_XTN_DC_INVAL_GO; - r_dcache.write_dir( way, - set, - CACHE_SLOT_STATE_ZOMBI ); + r_dcache.write_dir(way, + set, + CACHE_SLOT_STATE_ZOMBI); } } break; } - ////////////////////////////// - case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request + case DCACHE_XTN_DC_INVAL_END: // send response to processor XTN request { r_dcache_fsm = DCACHE_IDLE; @@ -4377,8 +4370,8 @@ // when a cleanup is required { - if ( m_dreq.valid) m_cost_data_miss_frz++; + if (m_dreq.valid) m_cost_data_miss_frz++; // coherence clack request (from DSPIN CLACK) - if ( r_dcache_clack_req.read() ) + if (r_dcache_clack_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4388,5 +4381,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4395,96 +4388,97 @@ } - bool found = false; - bool cleanup = false; - size_t way = 0; - size_t set = 0; - paddr_t victim = 0; - int state; - bool s_cleanup_updt_data = false; - bool s_cleanup_line_ncc = false; + bool found = false; + bool cleanup = false; + size_t way = 0; + size_t set = 0; + paddr_t victim = 0; + int state; + bool s_cleanup_updt_data = false; + bool s_cleanup_line_ncc = false; #ifdef INSTRUMENTATION -m_cpt_dcache_dir_read++; -#endif - r_dcache.read_select( r_dcache_save_paddr.read(), - &victim, - &way, - &set, - &found, - &cleanup ); - state = r_dcache.get_cache_state(way,set); - - if ( found ) - { - r_dcache_miss_way = way; - r_dcache_miss_set = set; - - if ( cleanup ) - { - r_dcache_miss_clack = true; - r_dcache_fsm = DCACHE_MISS_CLEAN; - if( (state == CACHE_SLOT_STATE_VALID_NCC) ) + m_cpt_dcache_dir_read++; +#endif + r_dcache.read_select(r_dcache_save_paddr.read(), + &victim, + &way, + &set, + &found, + &cleanup); + state = r_dcache.get_cache_state(way, set); + + if (found) + { + r_dcache_miss_way = way; + r_dcache_miss_set = set; + + if (cleanup) + { + r_dcache_miss_clack = true; + r_dcache_fsm = DCACHE_MISS_CLEAN; + + if ((state == CACHE_SLOT_STATE_VALID_NCC)) + { + s_cleanup_line_ncc = true; + r_dcache_miss_data_addr = (victim * m_dcache_words) * 4; + if ((r_dcache_content_state[way * m_dcache_sets + set] != LINE_CACHE_DATA_NOT_DIRTY)) // must send data { - s_cleanup_line_ncc = true; - r_dcache_miss_data_addr = (victim*m_dcache_words)*4; - if ((r_dcache_content_state[way*m_dcache_sets+set] != LINE_CACHE_DATA_NOT_DIRTY))//must send data + s_cleanup_updt_data = true; + for (size_t w = 0; w < m_dcache_words; w++) { - s_cleanup_updt_data = true; - for (size_t w = 0; w< m_dcache_words; w++) - { - m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets*way+set)*m_dcache_words + w]; - } - r_dcache_fsm = DCACHE_MISS_DATA; + m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets * way + set) * m_dcache_words + w]; } - else - { - s_cleanup_updt_data = false; - } - - if (r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_DATA_NOT_DIRTY) - m_cpt_cleanup_data_not_dirty ++; + r_dcache_fsm = DCACHE_MISS_DATA; } else { - s_cleanup_line_ncc = false; s_cleanup_updt_data = false; } - if( not r_dcache_cc_send_req.read() ) - { - // request cleanup - r_dcache_cc_send_req = true; - r_dcache_cc_send_nline = victim; - r_dcache_cc_send_way = way; - r_dcache_cc_send_type = CC_TYPE_CLEANUP; - r_dcache_cc_cleanup_updt_data = s_cleanup_updt_data; - r_dcache_cc_cleanup_line_ncc = s_cleanup_line_ncc; - } - else - { - r_dcache_cleanup_victim_nline = victim; - r_dcache_cleanup_victim_req = true; - r_dcache_cleanup_victim_updt_data = s_cleanup_updt_data; - r_dcache_cleanup_victim_line_ncc = s_cleanup_line_ncc; - } + if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_DATA_NOT_DIRTY) + m_cpt_cleanup_data_not_dirty ++; } else { - r_dcache_fsm = DCACHE_MISS_WAIT; - } + s_cleanup_line_ncc = false; + s_cleanup_updt_data = false; + } + + if (not r_dcache_cc_send_req.read()) + { + // request cleanup + r_dcache_cc_send_req = true; + r_dcache_cc_send_nline = victim; + r_dcache_cc_send_way = way; + r_dcache_cc_send_type = CC_TYPE_CLEANUP; + r_dcache_cc_cleanup_updt_data = s_cleanup_updt_data; + r_dcache_cc_cleanup_line_ncc = s_cleanup_line_ncc; + } + else + { + r_dcache_cleanup_victim_nline = victim; + r_dcache_cleanup_victim_req = true; + r_dcache_cleanup_victim_updt_data = s_cleanup_updt_data; + r_dcache_cleanup_victim_line_ncc = s_cleanup_line_ncc; + } + } + else + { + r_dcache_fsm = DCACHE_MISS_WAIT; + } #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " Select a slot:" << std::dec - << " / WAY = " << way - << " / SET = " << set - << " / PADDR = " << std::hex << r_dcache_save_paddr.read(); - if(cleanup) std::cout << " / VICTIM = " << (victim*m_dcache_words*4) << std::endl; - else std::cout << std::endl; -} -#endif - } // end found + if (m_debug_activated) + { + std::cout << " Select a slot:" << std::dec + << " / WAY = " << way + << " / SET = " << set + << " / PADDR = " << std::hex << r_dcache_save_paddr.read(); + if (cleanup) std::cout << " / VICTIM = " << (victim * m_dcache_words * 4) << std::dec << std::endl; + else std::cout << std::dec << std::endl; + } +#endif + } // end found break; } @@ -4497,5 +4491,5 @@ size_t word; - if( r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read() ) + if (r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_cc_send_req = true; @@ -4513,13 +4507,13 @@ &set, &word); - if(r_cc_send_data_fifo.wok()) + if (r_cc_send_data_fifo.wok()) { r_dcache_miss_data_addr = r_dcache_miss_data_addr.read() + 4; - cleanup_data_updt_fifo_dcache_put = true; - cleanup_data_updt_fifo_dcache_data = rdata; + cleanup_data_updt_fifo_dcache_put = true; + cleanup_data_updt_fifo_dcache_data = rdata; r_dcache_miss_data_cpt = r_dcache_miss_data_cpt.read() + 1; - if (r_dcache_miss_data_cpt.read() == m_dcache_words-1 ) + if (r_dcache_miss_data_cpt.read() == (m_dcache_words - 1)) { r_dcache_miss_data_cpt = 0; @@ -4534,46 +4528,44 @@ // and possibly request itlb or dtlb invalidate { - if ( m_dreq.valid) m_cost_data_miss_frz++; - - size_t way = r_dcache_miss_way.read(); - size_t set = r_dcache_miss_set.read(); + if (m_dreq.valid) m_cost_data_miss_frz++; + + size_t way = r_dcache_miss_way.read(); + size_t set = r_dcache_miss_set.read(); #ifdef INSTRUMENTATION -m_cpt_dcache_dir_read++; -#endif - r_dcache.write_dir( way, - set, - CACHE_SLOT_STATE_ZOMBI ); + m_cpt_dcache_dir_read++; +#endif + r_dcache.write_dir(way, + set, + CACHE_SLOT_STATE_ZOMBI); #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " Switch to ZOMBI state" << std::dec - << " / way = " << way - << " / set = " << set << std::endl; -} + if (m_debug_activated) + { + std::cout << " Switch to ZOMBI state" << std::dec + << " / way = " << way + << " / set = " << set << std::endl; + } #endif // if selective itlb & dtlb invalidate are required // the miss response is not handled before invalidate completed - if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) - { - r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY; - if( not r_dcache_cleanup_victim_req.read() ) - { + if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_IN_TLB) + { + r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_DIRTY; + + if (not r_dcache_cleanup_victim_req.read()) r_dcache_tlb_inval_line = r_dcache_cc_send_nline.read(); - } else - { r_dcache_tlb_inval_line = r_dcache_cleanup_victim_nline.read(); - } - r_dcache_tlb_inval_set = 0; - r_dcache_fsm_scan_save = DCACHE_MISS_WAIT; - r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; - } - else if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD ) + + r_dcache_tlb_inval_set = 0; + r_dcache_fsm_scan_save = DCACHE_MISS_WAIT; + r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; + } + else if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_CONTAINS_PTD) { r_itlb.reset(); r_dtlb.reset(); - r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY; + r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_DIRTY; r_dcache_fsm = DCACHE_MISS_WAIT; } @@ -4589,19 +4581,20 @@ // There is 5 types of error depending on the requester { - if ( m_dreq.valid) m_cost_data_miss_frz++; - - if( r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read() ) - { - r_dcache_cc_send_req = true; - r_dcache_cc_send_type = CC_TYPE_CLEANUP; - r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline.read(); + if (m_dreq.valid) m_cost_data_miss_frz++; + + // send cleanup victim request + if (r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read()) + { + r_dcache_cc_send_req = true; + r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline.read(); + r_dcache_cc_send_way = r_dcache_miss_way.read(); + r_dcache_cc_send_type = CC_TYPE_CLEANUP; r_dcache_cleanup_victim_req = false; r_dcache_cc_cleanup_updt_data = r_dcache_cleanup_victim_updt_data.read(); - r_dcache_cc_cleanup_line_ncc = r_dcache_cleanup_victim_line_ncc.read(); - r_dcache_cc_send_way = r_dcache_miss_way; + r_dcache_cc_cleanup_line_ncc = r_dcache_cleanup_victim_line_ncc.read(); } // coherence clack request (from DSPIN CLACK) - if ( r_dcache_clack_req.read() ) + if (r_dcache_clack_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4611,5 +4604,7 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_cleanup_victim_req.read() ) + if (r_cc_receive_dcache_req.read() and + not r_dcache_cc_send_req.read() and + not r_dcache_cleanup_victim_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4618,53 +4613,53 @@ } - if ( r_vci_rsp_data_error.read() ) // bus error - { - switch ( r_dcache_miss_type.read() ) + if (r_vci_rsp_data_error.read()) // bus error + { + switch (r_dcache_miss_type.read()) { case PROC_MISS: { - r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; - r_mmu_dbvar = r_dcache_save_vaddr.read(); - m_drsp.valid = true; - m_drsp.error = true; - r_dcache_fsm = DCACHE_IDLE; + r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; + r_mmu_dbvar = r_dcache_save_vaddr.read(); + m_drsp.valid = true; + m_drsp.error = true; + r_dcache_fsm = DCACHE_IDLE; break; } case PTE1_MISS: { - if ( r_dcache_tlb_ins.read() ) + if (r_dcache_tlb_ins.read()) { - r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS; - r_mmu_ibvar = r_dcache_tlb_vaddr.read(); - r_icache_tlb_miss_req = false; - r_icache_tlb_rsp_error = true; + r_mmu_ietr = MMU_READ_PT1_ILLEGAL_ACCESS; + r_mmu_ibvar = r_dcache_tlb_vaddr.read(); + r_icache_tlb_miss_req = false; + r_icache_tlb_rsp_error = true; } else { - r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS; - r_mmu_dbvar = r_dcache_tlb_vaddr.read(); - m_drsp.valid = true; - m_drsp.error = true; + r_mmu_detr = MMU_READ_PT1_ILLEGAL_ACCESS; + r_mmu_dbvar = r_dcache_tlb_vaddr.read(); + m_drsp.valid = true; + m_drsp.error = true; } - r_dcache_fsm = DCACHE_IDLE; + r_dcache_fsm = DCACHE_IDLE; break; } case PTE2_MISS: { - if ( r_dcache_tlb_ins.read() ) + if (r_dcache_tlb_ins.read()) { - r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS; - r_mmu_ibvar = r_dcache_tlb_vaddr.read(); - r_icache_tlb_miss_req = false; - r_icache_tlb_rsp_error = true; + r_mmu_ietr = MMU_READ_PT2_ILLEGAL_ACCESS; + r_mmu_ibvar = r_dcache_tlb_vaddr.read(); + r_icache_tlb_miss_req = false; + r_icache_tlb_rsp_error = true; } else { - r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS; - r_mmu_dbvar = r_dcache_tlb_vaddr.read(); - m_drsp.valid = true; - m_drsp.error = true; + r_mmu_detr = MMU_READ_PT2_ILLEGAL_ACCESS; + r_mmu_dbvar = r_dcache_tlb_vaddr.read(); + m_drsp.valid = true; + m_drsp.error = true; } - r_dcache_fsm = DCACHE_IDLE; + r_dcache_fsm = DCACHE_IDLE; break; } @@ -4672,5 +4667,5 @@ r_vci_rsp_data_error = false; } - else if ( r_vci_rsp_fifo_dcache.rok() ) // valid response available + else if (r_vci_rsp_fifo_dcache.rok()) // valid response available { r_dcache_miss_word = 0; @@ -4680,37 +4675,36 @@ } ////////////////////////// - case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle) - { - if ( m_dreq.valid) m_cost_data_miss_frz++; - - if ( r_vci_rsp_fifo_dcache.rok() && r_vci_rsp_fifo_rpktid.rok()) // one word available + case DCACHE_MISS_DATA_UPDT: // update the dcache (one word per cycle) + { + if (m_dreq.valid) m_cost_data_miss_frz++; + + if (r_vci_rsp_fifo_dcache.rok() and r_vci_rsp_fifo_rpktid.rok()) // one word available { #ifdef INSTRUMENTATION -m_cpt_dcache_data_write++; -#endif - r_dcache.write( r_dcache_miss_way.read(), - r_dcache_miss_set.read(), - r_dcache_miss_word.read(), - r_vci_rsp_fifo_dcache.read() ); + m_cpt_dcache_data_write++; +#endif + r_dcache.write(r_dcache_miss_way.read(), + r_dcache_miss_set.read(), + r_dcache_miss_word.read(), + r_vci_rsp_fifo_dcache.read()); #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " Write one word:" - << " / DATA = " << std::hex << r_vci_rsp_fifo_dcache.read() - << " / WAY = " << std::dec << r_dcache_miss_way.read() - << " / SET = " << r_dcache_miss_set.read() - << " / WORD = " << r_dcache_miss_word.read() << std::endl; -} + if (m_debug_activated) + { + std::cout << " Write one word:" + << " / DATA = " << std::hex << r_vci_rsp_fifo_dcache.read() + << " / WAY = " << std::dec << r_dcache_miss_way.read() + << " / SET = " << r_dcache_miss_set.read() + << " / WORD = " << r_dcache_miss_word.read() << std::endl; + } #endif vci_rsp_fifo_dcache_get = true; - r_dcache_read_state = !r_vci_rsp_fifo_rpktid.read();//deduce the state (CC or NCC) from msb of pktid + r_dcache_read_state = not r_vci_rsp_fifo_rpktid.read(); //deduce the state (CC or NCC) from msb of pktid vci_rsp_fifo_rpktid_get = true; - r_dcache_miss_word = r_dcache_miss_word.read() + 1; - if ( r_dcache_miss_word.read() == (m_dcache_words-1) ) // last word + if (r_dcache_miss_word.read() == (m_dcache_words - 1)) // last word { r_dcache_fsm = DCACHE_MISS_DIR_UPDT; @@ -4728,19 +4722,20 @@ // to ZOMBI state, and send a cleanup request. { - if ( m_dreq.valid) m_cost_data_miss_frz++; - - if( r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read() ) - { - r_dcache_cc_send_req = true; - r_dcache_cc_send_type = CC_TYPE_CLEANUP; - r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline.read(); + if (m_dreq.valid) m_cost_data_miss_frz++; + + // send cleanup victim request + if (r_dcache_cleanup_victim_req.read() and not r_dcache_cc_send_req.read()) + { + r_dcache_cc_send_req = true; + r_dcache_cc_send_nline = r_dcache_cleanup_victim_nline.read(); + r_dcache_cc_send_way = r_dcache_miss_way.read(); + r_dcache_cc_send_type = CC_TYPE_CLEANUP; r_dcache_cleanup_victim_req = false; r_dcache_cc_cleanup_updt_data = r_dcache_cleanup_victim_updt_data.read(); - r_dcache_cc_cleanup_line_ncc = r_dcache_cleanup_victim_line_ncc.read(); - r_dcache_cc_send_way = r_dcache_miss_way; + r_dcache_cc_cleanup_line_ncc = r_dcache_cleanup_victim_line_ncc.read(); } // coherence clack request (from DSPIN CLACK) - if ( r_dcache_clack_req.read() ) + if (r_dcache_clack_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4750,5 +4745,7 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read() and not r_dcache_cleanup_victim_req.read() ) + if (r_cc_receive_dcache_req.read() and + not r_dcache_cc_send_req.read() and + not r_dcache_cleanup_victim_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4757,21 +4754,21 @@ } - if ( not r_dcache_miss_clack.read() ) // waiting cleanup acknowledge - { - if ( r_dcache_miss_inval.read() ) // switch slot to ZOMBI state, and new cleanup - { - if ( not r_dcache_cc_send_req.read() ) // blocked until previous request sent - { - r_dcache_miss_inval = false; + if (not r_dcache_miss_clack.read()) // waiting cleanup acknowledge + { + if (r_dcache_miss_inval.read()) // switch slot to ZOMBI state, and new cleanup + { + if (not r_dcache_cc_send_req.read()) // blocked until previous request sent + { + r_dcache_miss_inval = false; // request cleanup r_dcache_cc_send_req = true; - r_dcache_cc_send_nline = r_dcache_save_paddr.read()/(m_dcache_words<<2); + r_dcache_cc_send_nline = r_dcache_save_paddr.read() / (m_dcache_words << 2); r_dcache_cc_send_way = r_dcache_miss_way.read(); r_dcache_cc_send_type = CC_TYPE_CLEANUP; - r_dcache_cc_cleanup_updt_data = false; //the line is evicted at the very moment it arives, so it is not dirty - r_dcache_cc_cleanup_line_ncc = !r_dcache_read_state.read(); + r_dcache_cc_cleanup_updt_data = false; // the line is evicted at the very moment it arives, so it is not dirty + r_dcache_cc_cleanup_line_ncc = !r_dcache_read_state.read(); #ifdef INSTRUMENTATION -m_cpt_dcache_dir_write++; + m_cpt_dcache_dir_write++; #endif r_dcache.write_dir( r_dcache_save_paddr.read(), @@ -4780,10 +4777,10 @@ CACHE_SLOT_STATE_ZOMBI ); #if DEBUG_DCACHE -if ( m_debug_activated ) -std::cout << " Switch slot to ZOMBI state" - << " PADDR = " << std::hex << r_dcache_save_paddr.read() - << " / WAY = " << std::dec << r_dcache_miss_way.read() - << " / SET = " << r_dcache_miss_set.read() << std::endl; + if (m_debug_activated) + std::cout << " Switch slot to ZOMBI state" + << " PADDR = " << std::hex << r_dcache_save_paddr.read() + << " / WAY = " << std::dec << r_dcache_miss_way.read() + << " / SET = " << r_dcache_miss_set.read() << std::endl; #endif } @@ -4795,42 +4792,40 @@ #ifdef INSTRUMENTATION -m_cpt_dcache_dir_write++; -#endif - + m_cpt_dcache_dir_write++; +#endif size_t way = r_dcache_miss_way.read(); size_t set = r_dcache_miss_set.read(); if (r_dcache_read_state.read()) { - r_dcache.write_dir( r_dcache_save_paddr.read(), - r_dcache_miss_way.read(), - r_dcache_miss_set.read(), - CACHE_SLOT_STATE_VALID_CC ); - - r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; - + r_dcache.write_dir(r_dcache_save_paddr.read(), + r_dcache_miss_way.read(), + r_dcache_miss_set.read(), + CACHE_SLOT_STATE_VALID_CC); + + r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_NOT_DIRTY; } else { - r_dcache.write_dir( r_dcache_save_paddr.read(), - r_dcache_miss_way.read(), - r_dcache_miss_set.read(), - CACHE_SLOT_STATE_VALID_NCC ); - r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; - for (size_t word =0; word < m_dcache_words ; word++) + r_dcache.write_dir(r_dcache_save_paddr.read(), + r_dcache_miss_way.read(), + r_dcache_miss_set.read(), + CACHE_SLOT_STATE_VALID_NCC); + r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_NOT_DIRTY; + for (size_t word = 0; word < m_dcache_words; word++) { - r_dcache_dirty_word[(way*m_dcache_sets +set)*m_dcache_words+word] = 0; + r_dcache_dirty_word[(way * m_dcache_sets + set) * m_dcache_words + word] = 0; } // STAT : WRITE ON ZOMBI NCC LINE - r_dcache_zombi_ncc[r_dcache_miss_way.read()*m_dcache_sets+r_dcache_miss_set.read()] = true; + r_dcache_zombi_ncc[r_dcache_miss_way.read() * m_dcache_sets + r_dcache_miss_set.read()] = true; } #if DEBUG_DCACHE -if ( m_debug_activated ) -std::cout << " Switch slot to VALID state" - << " PADDR = " << std::hex << r_dcache_save_paddr.read() - << " / WAY = " << std::dec << r_dcache_miss_way.read() - << " / SET = " << r_dcache_miss_set.read() << std::endl; + if (m_debug_activated) + std::cout << " Switch slot to VALID state" + << " PADDR = " << std::hex << r_dcache_save_paddr.read() + << " / WAY = " << std::dec << r_dcache_miss_way.read() + << " / SET = " << r_dcache_miss_set.read() << std::endl; #endif } @@ -4842,8 +4837,8 @@ } ///////////////////// - case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read + case DCACHE_UNC_WAIT: // waiting a response to an uncacheable read/write { // coherence clack request (from DSPIN CLACK) - if ( r_dcache_clack_req.read() ) + if (r_dcache_clack_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4853,5 +4848,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4860,10 +4855,11 @@ } - if ( r_vci_rsp_data_error.read() ) // bus error - { - if(r_dcache_vci_unc_write.read()) - r_mmu_detr = MMU_WRITE_DATA_ILLEGAL_ACCESS; + if (r_vci_rsp_data_error.read()) // bus error + { + if (r_dcache_vci_unc_write.read()) + r_mmu_detr = MMU_WRITE_DATA_ILLEGAL_ACCESS; else - r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; + r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; + r_mmu_dbvar = m_dreq.addr; r_vci_rsp_data_error = false; @@ -4873,5 +4869,5 @@ break; } - else if ( r_vci_rsp_fifo_dcache.rok() ) // data available + else if (r_vci_rsp_fifo_dcache.rok()) // data available { // consume data @@ -4880,9 +4876,9 @@ // acknowledge the processor request if it has not been modified - if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) ) - { - m_drsp.valid = true; - m_drsp.error = false; - m_drsp.rdata = r_vci_rsp_fifo_dcache.read(); + if (m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read())) + { + m_drsp.valid = true; + m_drsp.error = false; + m_drsp.rdata = r_vci_rsp_fifo_dcache.read(); } } @@ -4893,5 +4889,5 @@ { // coherence clack request (from DSPIN CLACK) - if ( r_dcache_clack_req.read() ) + if (r_dcache_clack_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4901,5 +4897,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4908,5 +4904,5 @@ } - if ( r_vci_rsp_data_error.read() ) // bus error + if (r_vci_rsp_data_error.read()) // bus error { r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; @@ -4918,23 +4914,23 @@ break; } - else if ( r_vci_rsp_fifo_dcache.rok() ) // data available + else if (r_vci_rsp_fifo_dcache.rok()) // data available { // consume data vci_rsp_fifo_dcache_get = true; - if(r_dcache_ll_rsp_count.read() == 0) // first flit + if (r_dcache_ll_rsp_count.read() == 0) // first flit { // set key value in llsc reservation buffer r_dcache_llsc_key = r_vci_rsp_fifo_dcache.read(); - r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1 ; + r_dcache_ll_rsp_count = r_dcache_ll_rsp_count.read() + 1; } else // last flit { // acknowledge the processor request if it has not been modified - if ( m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read()) ) - { - m_drsp.valid = true; - m_drsp.error = false; - m_drsp.rdata = r_vci_rsp_fifo_dcache.read(); + if (m_dreq.valid and (m_dreq.addr == r_dcache_save_vaddr.read())) + { + m_drsp.valid = true; + m_drsp.error = false; + m_drsp.rdata = r_vci_rsp_fifo_dcache.read(); } r_dcache_fsm = DCACHE_IDLE; @@ -4944,8 +4940,8 @@ } //////////////////// - case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction + case DCACHE_SC_WAIT: // waiting VCI response to a SC transaction { // coherence clack request (from DSPIN CLACK) - if ( r_dcache_clack_req.read() ) + if (r_dcache_clack_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4955,5 +4951,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -4962,5 +4958,5 @@ } - if ( r_vci_rsp_data_error.read() ) // bus error + if (r_vci_rsp_data_error.read()) // bus error { r_mmu_detr = MMU_READ_DATA_ILLEGAL_ACCESS; @@ -4972,5 +4968,5 @@ break; } - else if ( r_vci_rsp_fifo_dcache.rok() ) // response available + else if (r_vci_rsp_fifo_dcache.rok()) // response available { // consume response @@ -4983,9 +4979,9 @@ } ////////////////////////// - case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory - // before handling a processor WRITE or SC request - // Input argument is r_dcache_dirty_paddr - // In this first state, we get PTE value in dcache - // and post a CAS request to CMD FSM + case DCACHE_DIRTY_GET_PTE: // This sub_fsm set the PTE Dirty bit in memory + // before handling a processor WRITE or SC request + // Input argument is r_dcache_dirty_paddr + // In this first state, we get PTE value in dcache + // and post a CAS request to CMD FSM { // get PTE in dcache @@ -4997,23 +4993,23 @@ #ifdef INSTRUMENTATION -m_cpt_dcache_data_read++; -m_cpt_dcache_dir_read++; -#endif - r_dcache.read( r_dcache_dirty_paddr.read(), - &pte, - &way, - &set, - &word, - &state ); - - assert( (state == CACHE_SLOT_STATE_VALID_CC or state == CACHE_SLOT_STATE_VALID_NCC) and + m_cpt_dcache_data_read++; + m_cpt_dcache_dir_read++; +#endif + r_dcache.read(r_dcache_dirty_paddr.read(), + &pte, + &way, + &set, + &word, + &state); + + assert((state == CACHE_SLOT_STATE_VALID_CC or state == CACHE_SLOT_STATE_VALID_NCC) and "error in DCACHE_DIRTY_TLB_SET: the PTE should be in dcache" ); // request CAS transaction to CMD_FSM - r_dcache_dirty_way = way; - r_dcache_dirty_set = set; + r_dcache_dirty_way = way; + r_dcache_dirty_set = set; // check llsc reservation buffer - if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read() ) + if (r_dcache_llsc_paddr.read() == r_dcache_dirty_paddr.read()) r_dcache_llsc_valid = false; @@ -5029,34 +5025,33 @@ else { - r_cas_islocal = true; - r_cas_local_way = way; - r_cas_local_set = set; - r_cas_local_word = word; + r_cas_local_way = way; + r_cas_local_set = set; + r_cas_local_word = word; r_dcache_vci_cas_new = pte | PTE_D_MASK; - } - - - r_dcache_fsm = DCACHE_DIRTY_WAIT; + r_cas_islocal = true; + } + + r_dcache_fsm = DCACHE_DIRTY_WAIT; #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " CAS request" << std::hex - << " / PTE_PADDR = " << r_dcache_dirty_paddr.read() - << " / PTE_VALUE = " << pte << std::dec - << " / SET = " << set - << " / WAY = " << way << std::endl; -} + if (m_debug_activated) + { + std::cout << " CAS request" << std::hex + << " / PTE_PADDR = " << r_dcache_dirty_paddr.read() + << " / PTE_VALUE = " << pte << std::dec + << " / SET = " << set + << " / WAY = " << way << std::endl; + } #endif break; } /////////////////////// - case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit, - // and return to IDLE state when response is received. - // we don't care if the CAS is a failure: - // - if the CAS is a success, the coherence mechanism - // updates the local copy. - // - if the CAS is a failure, we just retry the write. + case DCACHE_DIRTY_WAIT: // wait completion of CAS for PTE Dirty bit, + // and return to IDLE state when response is received. + // we don't care if the CAS is a failure: + // - if the CAS is a success, the coherence mechanism + // updates the local copy. + // - if the CAS is a failure, we just retry the write. { uint32_t way = r_cas_local_way.read(); @@ -5066,5 +5061,5 @@ // coherence clack request (from DSPIN CLACK) - if ( r_dcache_clack_req.read() ) + if (r_dcache_clack_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -5074,5 +5069,5 @@ // coherence request (from CC_RECEIVE FSM) - if ( r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) + if (r_cc_receive_dcache_req.read() and not r_dcache_cc_send_req.read()) { r_dcache_fsm = DCACHE_CC_CHECK; @@ -5081,7 +5076,7 @@ } - if (!r_cas_islocal.read()) - { - if ( r_vci_rsp_data_error.read() ) // bus error + if (not r_cas_islocal.read()) + { + if (r_vci_rsp_data_error.read()) // bus error { std::cout << "BUS ERROR in DCACHE_DIRTY_WAIT state" << std::endl; @@ -5089,14 +5084,14 @@ exit(0); } - else if ( r_vci_rsp_fifo_dcache.rok() ) // response available + else if (r_vci_rsp_fifo_dcache.rok()) // response available { vci_rsp_fifo_dcache_get = true; - r_dcache_fsm = DCACHE_IDLE; + r_dcache_fsm = DCACHE_IDLE; #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " CAS completed" << std::endl; -} + if (m_debug_activated) + { + std::cout << " CAS completed" << std::endl; + } #endif } @@ -5109,7 +5104,7 @@ r_dcache_vci_cas_new.read()); - if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) - { - r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY; + if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_IN_TLB) + { + r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_DIRTY; r_dcache_tlb_inval_line = nline; r_dcache_tlb_inval_set = 0; @@ -5119,12 +5114,12 @@ } - if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD ) + if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_CONTAINS_PTD) { r_itlb.reset(); r_dtlb.reset(); - r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_DIRTY; + r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_DIRTY; #if DEBUG_DCACHE - if ( m_debug_activated ) + if (m_debug_activated) { std::cout << " paddr = " << paddr -// << " r_dcache_vci_paddr = " << r_dcache_vci_paddr.read() -// << " mask = " << mask -// << " (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) = " -// << (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) -// << " (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) = " -// << (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT) -// << " ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) = " -// << ((r_dcache_vci_paddr.read() & mask) == (paddr & mask)) -// << std::dec < CC_TYPE_CLACK Switch slot to EMPTY state" - << " set = " << r_dcache_clack_set.read() - << " / way = " << r_dcache_clack_way.read() << std::endl; -} -#endif - break; - } - + if (m_debug_activated) + { + std::cout << " CLACK for PADDR " << std::hex << paddr + << " Switch slot to EMPTY state : " + << " set = " << std::dec << r_dcache_clack_set.read() + << " / way = " << r_dcache_clack_way.read() << std::endl; + } +#endif + break; + } + + assert(not r_dcache_cc_send_req.read() and + "CC_SEND must be available in DCACHE_CC_CHECK"); // Match between MISS address and CC address @@ -5211,6 +5193,6 @@ // because the CLACK access the directory but the MISS match dont. if (r_cc_receive_dcache_req.read() and - ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT ) or - (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT ) or + ((r_dcache_fsm_cc_save == DCACHE_MISS_SELECT) or + (r_dcache_fsm_cc_save == DCACHE_MISS_WAIT) or (r_dcache_fsm_cc_save == DCACHE_MISS_DIR_UPDT)) and ((r_dcache_vci_paddr.read() & mask) == (paddr & mask))) // matching @@ -5223,6 +5205,6 @@ if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) { - r_dcache_fsm = DCACHE_CC_UPDT; - r_dcache_cc_word = r_cc_receive_word_idx.read(); + r_dcache_fsm = DCACHE_CC_UPDT; + r_dcache_cc_word = r_cc_receive_word_idx.read(); // just pop the fifo , don't write in icache @@ -5237,15 +5219,12 @@ #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " Coherence request matching a pending miss:" - << " PADDR = " << std::hex << paddr << std::endl; -} -#endif - } - - - assert ( not r_dcache_cc_send_req.read() and "CC_SEND must be available in DCACHE_CC_CHECK" ); + if (m_debug_activated) + { + std::cout << " Coherence request matching a pending miss:" + << " PADDR = " << std::hex << paddr << std::endl; + } +#endif + } // CC request handler @@ -5257,11 +5236,11 @@ #ifdef INSTRUMENTATION -m_cpt_dcache_dir_read++; -#endif - r_dcache.read_dir( paddr, - &state, - &way, - &set, - &word ); // unused + m_cpt_dcache_dir_read++; +#endif + r_dcache.read_dir(paddr, + &state, + &way, + &set, + &word); // unused r_dcache_cc_state = state; @@ -5269,5 +5248,6 @@ r_dcache_cc_set = set; - if ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC)) // hit + if ((state == CACHE_SLOT_STATE_VALID_CC) or + (state == CACHE_SLOT_STATE_VALID_NCC)) // hit { // need to update the cache state @@ -5276,6 +5256,6 @@ if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) // hit update { - r_dcache_fsm = DCACHE_CC_UPDT; - r_dcache_cc_word = r_cc_receive_word_idx.read(); + r_dcache_fsm = DCACHE_CC_UPDT; + r_dcache_cc_word = r_cc_receive_word_idx.read(); } else if (r_cc_receive_dcache_type.read() == CC_TYPE_INVAL) // hit inval @@ -5283,9 +5263,9 @@ if (state == CACHE_SLOT_STATE_VALID_NCC) { - r_dcache_cc_inval_addr = (paddr &~0x3F); + r_dcache_cc_inval_addr = (paddr & ~0x3F); r_dcache_cc_inval_data_cpt = 0; } - r_dcache_fsm = DCACHE_CC_INVAL; - r_dcache_dirty_save = false; + r_dcache_fsm = DCACHE_CC_INVAL; + r_dcache_dirty_save = false; } } @@ -5293,8 +5273,8 @@ { // multicast acknowledgement required in case of update - if(r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) - { - r_dcache_fsm = DCACHE_CC_UPDT; - r_dcache_cc_word = r_cc_receive_word_idx.read(); + if (r_cc_receive_dcache_type.read() == CC_TYPE_UPDT) + { + r_dcache_fsm = DCACHE_CC_UPDT; + r_dcache_cc_word = r_cc_receive_word_idx.read(); // just pop the fifo , don't write in icache @@ -5309,17 +5289,16 @@ #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " Coherence request received:" - << " PADDR = " << std::hex << paddr - << " / TYPE = " << std::dec << r_cc_receive_dcache_type.read() - << " / HIT = " << ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC)) << std::endl; -} + if (m_debug_activated) + { + std::cout << " Coherence request received:" + << " PADDR = " << std::hex << paddr + << " / TYPE = " << std::dec << r_cc_receive_dcache_type.read() + << " / HIT = " << ((state == CACHE_SLOT_STATE_VALID_CC) or (state == CACHE_SLOT_STATE_VALID_NCC)) << std::endl; + } #endif break; } - ///////////////////// case DCACHE_CC_INVAL: // hit inval: switch slot to ZOMBI state and send a @@ -5327,37 +5306,37 @@ // TLBs { - size_t way = r_dcache_cc_way.read(); - size_t set = r_dcache_cc_set.read(); - int cache_state = r_dcache_cc_state.read(); - bool dirty_save = false; + size_t way = r_dcache_cc_way.read(); + size_t set = r_dcache_cc_set.read(); + int cache_state = r_dcache_cc_state.read(); + bool dirty_save = false; if (r_dcache_cc_need_write.read()) { - if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) - { - r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY;//need to remember it was dirty for cleanup + if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_IN_TLB) + { + r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_NOT_DIRTY; //need to remember it was dirty for cleanup dirty_save = true; r_dcache_dirty_save = true; - r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); - r_dcache_tlb_inval_set = 0; - r_dcache_fsm_scan_save = r_dcache_fsm.read(); - r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; + r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); + r_dcache_tlb_inval_set = 0; + r_dcache_fsm_scan_save = r_dcache_fsm.read(); + r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; break; } else { - if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD ) + if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_CONTAINS_PTD) { r_itlb.reset(); r_dtlb.reset(); - r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; + r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_NOT_DIRTY; dirty_save = true; r_dcache_dirty_save = true; #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " Flush DTLB & ITLB" << std::endl; -} + if (m_debug_activated) + { + std::cout << " Flush DTLB & ITLB" << std::endl; + } #endif } @@ -5365,17 +5344,17 @@ // If the type of inval request from Memcache is configuration // (software), we send a classic CLEANUP - if (cache_state == CACHE_SLOT_STATE_VALID_CC or r_cc_receive_dcache_inval_is_config.read()) - { - r_dcache.write_dir( way, - set, - CACHE_SLOT_STATE_ZOMBI ); - } - + if (cache_state == CACHE_SLOT_STATE_VALID_CC or + r_cc_receive_dcache_inval_is_config.read()) + { + r_dcache.write_dir(way, + set, + CACHE_SLOT_STATE_ZOMBI); + } r_dcache_cc_need_write = false; } } - assert (not r_dcache_cc_send_req.read() && - "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req " - "must not be set"); + assert(not r_dcache_cc_send_req.read() and + "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req " + "must not be set"); // coherence request completed r_cc_receive_dcache_req = false; @@ -5386,22 +5365,25 @@ r_dcache_cc_send_type = CC_TYPE_CLEANUP; - if (cache_state == CACHE_SLOT_STATE_VALID_NCC and not r_cc_receive_dcache_inval_is_config.read()) + if (cache_state == CACHE_SLOT_STATE_VALID_NCC and + not r_cc_receive_dcache_inval_is_config.read()) { r_dcache_cc_cleanup_line_ncc = true; - if ((r_dcache_content_state[way*m_dcache_sets+set] != LINE_CACHE_DATA_NOT_DIRTY) or r_dcache_dirty_save.read() or dirty_save) //must send data + if ((r_dcache_content_state[way * m_dcache_sets + set] != LINE_CACHE_DATA_NOT_DIRTY) or + r_dcache_dirty_save.read() or + dirty_save) //must send data { r_dcache_cc_cleanup_updt_data = true; - for (size_t w = 0; w< m_dcache_words; w++) - { - m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets*way+set)*m_dcache_words + w]; - } - - r_dcache_fsm = DCACHE_CC_INVAL_DATA; + for (size_t w = 0; w < m_dcache_words; w++) + { + m_cpt_cleanup_data_dirty_word += r_dcache_dirty_word[(m_dcache_sets * way + set) * m_dcache_words + w]; + } + + r_dcache_fsm = DCACHE_CC_INVAL_DATA; } else { - r_dcache.write_dir( way, - set, - CACHE_SLOT_STATE_ZOMBI ); + r_dcache.write_dir(way, + set, + CACHE_SLOT_STATE_ZOMBI); r_dcache_cc_cleanup_updt_data = false; @@ -5417,5 +5399,4 @@ break; } - ///////////////////// case DCACHE_CC_INVAL_DATA: @@ -5423,7 +5404,7 @@ uint32_t rdata; - size_t way = 0; // to avoid gcc warning - size_t set = 0; // to avoid gcc warning - size_t word; + size_t way = 0; // to avoid gcc warning + size_t set = 0; // to avoid gcc warning + size_t word; r_dcache.read_neutral(r_dcache_cc_inval_addr.read(), &rdata, @@ -5431,19 +5412,19 @@ &set, &word); - if(r_cc_send_data_fifo.wok()) + if (r_cc_send_data_fifo.wok()) { r_dcache_cc_inval_addr = r_dcache_cc_inval_addr.read() + 4; - cleanup_data_updt_fifo_dcache_put = true; - cleanup_data_updt_fifo_dcache_data = rdata; + cleanup_data_updt_fifo_dcache_put = true; + cleanup_data_updt_fifo_dcache_data = rdata; r_dcache_cc_inval_data_cpt = r_dcache_cc_inval_data_cpt.read() + 1; - if(r_dcache_cc_inval_data_cpt.read() == (m_dcache_words - 1)) + if (r_dcache_cc_inval_data_cpt.read() == (m_dcache_words - 1)) { r_dcache_cc_inval_data_cpt = 0; - r_dcache_fsm = r_dcache_fsm_cc_save.read(); + r_dcache_fsm = r_dcache_fsm_cc_save.read(); r_dcache.write_dir(way, set, - CACHE_SLOT_STATE_ZOMBI ); + CACHE_SLOT_STATE_ZOMBI); } } @@ -5451,70 +5432,70 @@ } /////////////////// - case DCACHE_CC_UPDT: // hit update: write one word per cycle, - // after possible invalidation of copies in TLBs - { - size_t word = r_dcache_cc_word.read(); - size_t way = r_dcache_cc_way.read(); - size_t set = r_dcache_cc_set.read(); - - if (r_dcache_cc_need_write.read()) - { - if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_IN_TLB ) - { - r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; - r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); - r_dcache_tlb_inval_set = 0; - r_dcache_fsm_scan_save = r_dcache_fsm.read(); - r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; - break; - } - if ( r_dcache_content_state[way*m_dcache_sets+set] == LINE_CACHE_CONTAINS_PTD ) - { - r_itlb.reset(); - r_dtlb.reset(); - r_dcache_content_state[way*m_dcache_sets+set] = LINE_CACHE_DATA_NOT_DIRTY; + case DCACHE_CC_UPDT: // hit update: write one word per cycle, + // after possible invalidation of copies in TLBs + { + size_t word = r_dcache_cc_word.read(); + size_t way = r_dcache_cc_way.read(); + size_t set = r_dcache_cc_set.read(); + + if (r_dcache_cc_need_write.read()) + { + if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_IN_TLB) + { + r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_NOT_DIRTY; + r_dcache_tlb_inval_line = r_cc_receive_dcache_nline.read(); + r_dcache_tlb_inval_set = 0; + r_dcache_fsm_scan_save = r_dcache_fsm.read(); + r_dcache_fsm = DCACHE_INVAL_TLB_SCAN; + break; + } + if (r_dcache_content_state[way * m_dcache_sets + set] == LINE_CACHE_CONTAINS_PTD) + { + r_itlb.reset(); + r_dtlb.reset(); + r_dcache_content_state[way * m_dcache_sets + set] = LINE_CACHE_DATA_NOT_DIRTY; #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " Flush DTLB & ITLB" << std::endl; -} -#endif - } - - assert (not r_dcache_cc_send_req.read() && - "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req " - "must not be set"); - - if ( not r_cc_receive_updt_fifo_be.rok() ) break; + if (m_debug_activated) + { + std::cout << " Flush DTLB & ITLB" << std::endl; + } +#endif + } + + assert(not r_dcache_cc_send_req.read() && + "ERROR in DCACHE_CC_INVAL: the r_dcache_cc_send_req " + "must not be set"); + + if (not r_cc_receive_updt_fifo_be.rok()) break; #ifdef INSTRUMENTATION -m_cpt_dcache_data_write++; -#endif - r_dcache.write( way, - set, - word, - r_cc_receive_updt_fifo_data.read(), - r_cc_receive_updt_fifo_be.read() ); + m_cpt_dcache_data_write++; +#endif + r_dcache.write(way, + set, + word, + r_cc_receive_updt_fifo_data.read(), + r_cc_receive_updt_fifo_be.read()); r_dcache_cc_word = word + 1; #if DEBUG_DCACHE -if ( m_debug_activated ) -{ - std::cout << " Write one word" << std::dec - << " / WAY = " << way - << " / SET = " << set - << " / WORD = " << word - << " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl; -} -#endif - } - - if ( not r_cc_receive_updt_fifo_be.rok() ) break; - - if ( r_cc_receive_updt_fifo_eop.read() ) // last word + if (m_debug_activated) + { + std::cout << " Write one word" << std::dec + << " / WAY = " << way + << " / SET = " << set + << " / WORD = " << word + << " / VALUE = " << std::hex << r_cc_receive_updt_fifo_data.read() << std::endl; + } +#endif + } + + if (not r_cc_receive_updt_fifo_be.rok()) break; + + if (r_cc_receive_updt_fifo_eop.read()) // last word { // no need to write in the cache anymore @@ -5528,5 +5509,4 @@ r_dcache_cc_send_updt_tab_idx = r_cc_receive_dcache_updt_tab_idx.read(); r_dcache_cc_send_type = CC_TYPE_MULTI_ACK; - r_dcache_fsm = r_dcache_fsm_cc_save.read(); } @@ -5538,57 +5518,59 @@ } /////////////////////////// - case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB - // It makes assumption: m_itlb_sets == m_dtlb_sets - // All ways are handled in parallel. - // We enter this state when a DCACHE line is modified, - // and there is a copy in itlb or dtlb. - // It can be caused by: - // - a coherence inval or updt transaction, - // - a line inval caused by a cache miss - // - a processor XTN inval request, - // - a WRITE hit, - // - a Dirty bit update - // Input arguments are: - // - r_dcache_tlb_inval_line - // - r_dcache_tlb_inval_set - // - r_dcache_fsm_scan_save + case DCACHE_INVAL_TLB_SCAN: // Scan sequencially all sets for both ITLB & DTLB + // It makes assumption: m_itlb_sets == m_dtlb_sets + // All ways are handled in parallel. + // We enter this state when a DCACHE line is modified, + // and there is a copy in itlb or dtlb. + // It can be caused by: + // - a coherence inval or updt transaction, + // - a line inval caused by a cache miss + // - a processor XTN inval request, + // - a WRITE hit, + // - a Dirty bit update + // Input arguments are: + // - r_dcache_tlb_inval_line + // - r_dcache_tlb_inval_set + // - r_dcache_fsm_scan_save { paddr_t line = r_dcache_tlb_inval_line.read(); - size_t set = r_dcache_tlb_inval_set.read(); - size_t way; - bool ok; - - for ( way = 0 ; way < m_itlb_ways ; way++ ) - { - ok = r_itlb.inval( line, way, set ); + size_t set = r_dcache_tlb_inval_set.read(); + size_t way; + bool ok; + + for (way = 0; way < m_itlb_ways; way++) + { + ok = r_itlb.inval(line, way, set); #if DEBUG_DCACHE -if ( m_debug_activated and ok ) -{ - std::cout << " Invalidate ITLB entry:" << std::hex - << " line = " << line << std::dec - << " / set = " << set - << " / way = " << way << std::endl; -} -#endif - } - - for ( way = 0 ; way < m_dtlb_ways ; way++ ) - { - ok = r_dtlb.inval( line, way, set ); + if (m_debug_activated and ok) + { + std::cout << " Invalidate ITLB entry:" << std::hex + << " line = " << line << std::dec + << " / set = " << set + << " / way = " << way << std::endl; + } +#endif + } + + for (way = 0; way < m_dtlb_ways; way++) + { + ok = r_dtlb.inval(line, way, set); #if DEBUG_DCACHE -if ( m_debug_activated and ok ) -std::cout << " " - << " Invalidate DTLB entry" << std::hex - << " / line = " << line << std::dec - << " / set = " << set - << " / way = " << way << std::endl; + if (m_debug_activated and ok) + { + std::cout << " " + << " Invalidate DTLB entry" << std::hex + << " / line = " << line << std::dec + << " / set = " << set + << " / way = " << way << std::endl; + } #endif } // return to the calling state when TLB inval completed - if ( r_dcache_tlb_inval_set.read() == (m_dtlb_sets-1) ) + if (r_dcache_tlb_inval_set.read() == (m_dtlb_sets - 1)) { r_dcache_fsm = r_dcache_fsm_scan_save.read(); @@ -5609,9 +5591,9 @@ // The simulation exit if the number of consecutive frozen cycles // is larger than the m_max_frozen_cycles (constructor parameter) - if ( (m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid) ) - { - m_cpt_frz_cycles++; // used for instrumentation - m_cpt_stop_simulation++; // used for debug - if ( m_cpt_stop_simulation > m_max_frozen_cycles ) + if ((m_ireq.valid and not m_irsp.valid) or (m_dreq.valid and not m_drsp.valid)) + { + m_cpt_frz_cycles++; // used for instrumentation + m_cpt_stop_simulation++; // used for debug + if (m_cpt_stop_simulation > m_max_frozen_cycles) { std::cout << std::dec << "ERROR in CC_VCACHE_WRAPPER " << name() << std::endl @@ -5630,7 +5612,7 @@ /////////// execute one iss cycle ///////////////////////////////// { - uint32_t it = 0; - for (size_t i=0; i<(size_t)iss_t::n_irq; i++) if(p_irq[i].read()) it |= (1<" - << " / dmiss_req = " << dcache_miss_req - << " / imiss_req = " << icache_miss_req - << std::endl; -} + if (m_debug_activated) + { + std::cout << " " + << " / dmiss_req = " << dcache_miss_req + << " / imiss_req = " << icache_miss_req + << std::endl; + } #endif break; @@ -5798,11 +5772,11 @@ case CMD_DATA_WRITE: { - if ( p_vci.cmdack.read() ) + if (p_vci.cmdack.read()) { r_vci_cmd_cpt = r_vci_cmd_cpt + 1; if (r_vci_cmd_cpt == r_vci_cmd_max) // last flit sent { - r_vci_cmd_fsm = CMD_IDLE ; - r_wbuf.sent() ; + r_vci_cmd_fsm = CMD_IDLE; + r_wbuf.sent(); } } @@ -5814,5 +5788,5 @@ { // The CAS and SC VCI commands contain two flits - if ( p_vci.cmdack.read() ) + if (p_vci.cmdack.read()) { r_vci_cmd_cpt = r_vci_cmd_cpt + 1; @@ -5830,5 +5804,5 @@ { // all read VCI commands contain one single flit - if ( p_vci.cmdack.read() ) { + if (p_vci.cmdack.read()) { r_vci_cmd_fsm = CMD_IDLE; } @@ -5865,42 +5839,42 @@ ////////////////////////////////////////////////////////////////////////// - switch ( r_vci_rsp_fsm.read() ) + switch (r_vci_rsp_fsm.read()) { ////////////// case RSP_IDLE: { - if ( p_vci.rspval.read() ) + if (p_vci.rspval.read()) { r_vci_rsp_cpt = 0; - if (r_dcache_vci_paddr.read() == 0x1f624) std::cout << "Tansaction on barrier, pktid = " << p_vci.rpktid.read() << std::endl; - if ( (p_vci.rpktid.read() & 0x7) == TYPE_DATA_UNC ) + + if ((p_vci.rpktid.read() & 0x7) == TYPE_DATA_UNC) { r_vci_rsp_fsm = RSP_DATA_UNC; } - else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS ) + else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_DATA_MISS) { r_vci_rsp_fsm = RSP_DATA_MISS; } - else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC ) + else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_UNC) { r_vci_rsp_fsm = RSP_INS_UNC; } - else if ( (p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS ) + else if ((p_vci.rpktid.read() & 0x7) == TYPE_READ_INS_MISS) { r_vci_rsp_fsm = RSP_INS_MISS; } - else if ( (p_vci.rpktid.read() & 0x7) == TYPE_WRITE ) + else if ((p_vci.rpktid.read() & 0x7) == TYPE_WRITE) { r_vci_rsp_fsm = RSP_DATA_WRITE; } - else if ( (p_vci.rpktid.read() & 0x7) == TYPE_CAS ) + else if ((p_vci.rpktid.read() & 0x7) == TYPE_CAS) { r_vci_rsp_fsm = RSP_DATA_UNC; } - else if ( (p_vci.rpktid.read() & 0x7) == TYPE_LL ) + else if ((p_vci.rpktid.read() & 0x7) == TYPE_LL) { r_vci_rsp_fsm = RSP_DATA_LL; } - else if ( (p_vci.rpktid.read() & 0x7) == TYPE_SC ) + else if ((p_vci.rpktid.read() & 0x7) == TYPE_SC) { r_vci_rsp_fsm = RSP_DATA_UNC; @@ -5916,16 +5890,16 @@ case RSP_INS_MISS: { - if ( p_vci.rspval.read() ) - { - if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported + if (p_vci.rspval.read()) + { + if ((p_vci.rerror.read() & 0x1) != 0) // error reported { r_vci_rsp_ins_error = true; - if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE; + if (p_vci.reop.read()) r_vci_rsp_fsm = RSP_IDLE; } else // no error reported { - if ( r_vci_rsp_fifo_icache.wok() ) + if (r_vci_rsp_fifo_icache.wok()) { - if ( r_vci_rsp_cpt.read() >= m_icache_words ) + if (r_vci_rsp_cpt.read() >= m_icache_words) { std::cout << "ERROR in VCI_CC_VCACHE " << name() @@ -5934,10 +5908,10 @@ exit(0); } - r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; - vci_rsp_fifo_icache_put = true, - vci_rsp_fifo_icache_data = p_vci.rdata.read(); - if ( p_vci.reop.read() ) + r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; + vci_rsp_fifo_icache_put = true, + vci_rsp_fifo_icache_data = p_vci.rdata.read(); + if (p_vci.reop.read()) { - if ( r_vci_rsp_cpt.read() != (m_icache_words - 1) ) + if (r_vci_rsp_cpt.read() != (m_icache_words - 1)) { std::cout << "ERROR in VCI_CC_VCACHE " << name() @@ -5946,5 +5920,5 @@ exit(0); } - r_vci_rsp_fsm = RSP_IDLE; + r_vci_rsp_fsm = RSP_IDLE; } } @@ -5956,10 +5930,10 @@ case RSP_INS_UNC: { - if (p_vci.rspval.read() ) - { - assert( p_vci.reop.read() and + if (p_vci.rspval.read()) + { + assert(p_vci.reop.read() and "illegal VCI response packet for uncachable instruction"); - if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported + if ((p_vci.rerror.read() & 0x1) != 0) // error reported { r_vci_rsp_ins_error = true; @@ -5968,8 +5942,8 @@ else // no error reported { - if ( r_vci_rsp_fifo_icache.wok()) + if (r_vci_rsp_fifo_icache.wok()) { - vci_rsp_fifo_icache_put = true; - vci_rsp_fifo_icache_data = p_vci.rdata.read(); + vci_rsp_fifo_icache_put = true; + vci_rsp_fifo_icache_data = p_vci.rdata.read(); r_vci_rsp_fsm = RSP_IDLE; } @@ -5981,33 +5955,30 @@ case RSP_DATA_MISS: { - if ( p_vci.rspval.read() ) - { - if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported + if (p_vci.rspval.read()) + { + if ((p_vci.rerror.read() & 0x1) != 0) // error reported { r_vci_rsp_data_error = true; - if ( p_vci.reop.read() ) r_vci_rsp_fsm = RSP_IDLE; + if (p_vci.reop.read()) r_vci_rsp_fsm = RSP_IDLE; } else // no error reported { - - - if ( r_vci_rsp_fifo_dcache.wok() && r_vci_rsp_fifo_rpktid.wok()) + if (r_vci_rsp_fifo_dcache.wok() and r_vci_rsp_fifo_rpktid.wok()) { - assert( (r_vci_rsp_cpt.read() < m_dcache_words) and + assert((r_vci_rsp_cpt.read() < m_dcache_words) and "The VCI response packet for data miss is too long"); - r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; - vci_rsp_fifo_dcache_put = true, - vci_rsp_fifo_dcache_data = p_vci.rdata.read(); - vci_rsp_fifo_rpktid = (p_vci.rpktid.read() == 0x9);//RWT: interpretation of pktid for state (NCC or CC) - vci_rsp_fifo_rpktid_put = true;//RWT - - if ( p_vci.reop.read() ) + r_vci_rsp_cpt = r_vci_rsp_cpt.read() + 1; + vci_rsp_fifo_dcache_put = true, + vci_rsp_fifo_dcache_data = p_vci.rdata.read(); + vci_rsp_fifo_rpktid = (p_vci.rpktid.read() == 0x9); //RWT: interpretation of pktid for state (NCC or CC) + vci_rsp_fifo_rpktid_put = true; //RWT + + if (p_vci.reop.read()) { - if (r_vci_rsp_cpt.read() != m_dcache_words - 1) std::cout << "assert on proc " << name() << std::endl; - assert( (r_vci_rsp_cpt.read() == m_dcache_words - 1) and + assert((r_vci_rsp_cpt.read() == m_dcache_words - 1) and "The VCI response packet for data miss is too short"); - r_vci_rsp_fsm = RSP_IDLE; + r_vci_rsp_fsm = RSP_IDLE; } } @@ -6019,20 +5990,20 @@ case RSP_DATA_UNC: { - if (p_vci.rspval.read() ) - { - assert( p_vci.reop.read() and + if (p_vci.rspval.read()) + { + assert(p_vci.reop.read() and "illegal VCI response packet for uncachable read data"); - if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported + if ((p_vci.rerror.read() & 0x1) != 0) // error reported { r_vci_rsp_data_error = true; r_vci_rsp_fsm = RSP_IDLE; } - else // no error reported - { - if ( r_vci_rsp_fifo_dcache.wok()) + else // no error reported + { + if (r_vci_rsp_fifo_dcache.wok()) { - vci_rsp_fifo_dcache_put = true; - vci_rsp_fifo_dcache_data = p_vci.rdata.read(); + vci_rsp_fifo_dcache_put = true; + vci_rsp_fifo_dcache_data = p_vci.rdata.read(); r_vci_rsp_fsm = RSP_IDLE; } @@ -6044,7 +6015,7 @@ case RSP_DATA_LL: { - if ( p_vci.rspval.read() ) - { - if ( (p_vci.rerror.read()&0x1) != 0 ) // error reported + if (p_vci.rspval.read()) + { + if ((p_vci.rerror.read() & 0x1) != 0) // error reported { r_vci_rsp_data_error = true; @@ -6054,5 +6025,5 @@ if (r_vci_rsp_cpt.read() == 0) //first flit { - if(r_vci_rsp_fifo_dcache.wok()) + if (r_vci_rsp_fifo_dcache.wok()) { assert(!p_vci.reop.read() && @@ -6066,5 +6037,5 @@ else // last flit { - if(r_vci_rsp_fifo_dcache.wok()) + if (r_vci_rsp_fifo_dcache.wok()) { assert(p_vci.reop.read() && @@ -6084,11 +6055,11 @@ if (p_vci.rspval.read()) { - assert( p_vci.reop.read() and + assert(p_vci.reop.read() and "a VCI response packet must contain one flit for a write transaction"); r_vci_rsp_fsm = RSP_IDLE; - uint32_t wbuf_index = p_vci.rtrdid.read(); + uint32_t wbuf_index = p_vci.rtrdid.read(); r_wbuf.completed(wbuf_index); - if ( (p_vci.rerror.read()&0x1) != 0 ) r_iss.setWriteBerr(); + if ((p_vci.rerror.read() & 0x1) != 0) r_iss.setWriteBerr(); } break; @@ -6103,5 +6074,5 @@ // soon as the request has been sent. ///////////////////////////////////////////////////////////////////////////////////// - switch ( r_cc_send_fsm.read() ) + switch (r_cc_send_fsm.read()) { /////////////////////////// @@ -6115,5 +6086,5 @@ /////////////////////////////////////////////////////// bool update_last_client = r_cc_send_last_client.read(); - if ( r_cc_send_last_client.read() == 0 ) // last client was dcache + if (r_cc_send_last_client.read() == 0) // last client was dcache { if (r_icache_cc_send_req.read()) // request from icache @@ -6131,17 +6102,17 @@ { // the new client is dcache and has a cleanup request - if ( (update_last_client == 0) and - (r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP)) + if ((update_last_client == 0) and + (r_dcache_cc_send_type.read() == CC_TYPE_CLEANUP)) r_cc_send_fsm = CC_SEND_CLEANUP_1; // the new client is dcache and has a multi acknowledgement request - else if ( (update_last_client == 0) and - (r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK)) + else if ((update_last_client == 0) and + (r_dcache_cc_send_type.read() == CC_TYPE_MULTI_ACK)) r_cc_send_fsm = CC_SEND_MULTI_ACK; // the new client is icache and has a cleanup request - else if ( (update_last_client == 1) and - (r_icache_cc_send_type.read() == CC_TYPE_CLEANUP)) + else if ((update_last_client == 1) and + (r_icache_cc_send_type.read() == CC_TYPE_CLEANUP)) r_cc_send_fsm = CC_SEND_CLEANUP_1; // the new client is icache and has a multi acknowledgement request - else if ( (update_last_client == 1) and + else if ((update_last_client == 1) and (r_icache_cc_send_type.read() == CC_TYPE_MULTI_ACK)) r_cc_send_fsm = CC_SEND_MULTI_ACK; @@ -6165,5 +6136,6 @@ { - if(r_dcache_cc_cleanup_updt_data.read() and (r_cc_send_last_client.read() == 0))//dcache request with data + if (r_dcache_cc_cleanup_updt_data.read() and + (r_cc_send_last_client.read() == 0)) //dcache request with data { r_cc_send_fsm = CC_SEND_CLEANUP_DATA_UPDT; @@ -6190,10 +6162,10 @@ if (p_dspin_p2m.read.read()) { - if(r_cc_send_data_fifo.rok()) + if (r_cc_send_data_fifo.rok()) { m_cpt_data_cleanup++; cleanup_data_updt_fifo_dcache_get = true; r_cc_send_cpt_word = r_cc_send_cpt_word.read() + 1; - if (r_cc_send_cpt_word.read() == m_dcache_words-1) + if (r_cc_send_cpt_word.read() == m_dcache_words - 1) { r_dcache_cc_send_req = false; @@ -6210,7 +6182,7 @@ { // wait for the flit to be consumed - if(p_dspin_p2m.read.read()) - { - if(r_cc_send_last_client.read() == 0) // dcache active request + if (p_dspin_p2m.read.read()) + { + if (r_cc_send_last_client.read() == 0) // dcache active request r_dcache_cc_send_req = false; // reset dcache request else // icache active request @@ -6233,5 +6205,5 @@ // - CC_BROADCAST : Broadcast invalidate request (both DCACHE & ICACHE) ////////////////////////////////////////////////////////////////////////////// - switch( r_cc_receive_fsm.read() ) + switch (r_cc_receive_fsm.read()) { ///////////////////// @@ -6247,5 +6219,5 @@ DspinRwtParam::M2P_TYPE); // test for a broadcast - if (DspinRwtParam::dspin_get(receive_data,DspinRwtParam::M2P_BC)) + if (DspinRwtParam::dspin_get(receive_data, DspinRwtParam::M2P_BC)) { r_cc_receive_fsm = CC_RECEIVE_BRDCAST_HEADER; @@ -6294,10 +6266,10 @@ // request dcache to handle the BROADCAST r_cc_receive_dcache_req = true; - r_cc_receive_dcache_nline = DspinRwtParam::dspin_get(receive_data, + r_cc_receive_dcache_nline = DspinRwtParam::dspin_get(receive_data, DspinRwtParam::BROADCAST_NLINE); r_cc_receive_dcache_type = CC_TYPE_INVAL; // request icache to handle the BROADCAST r_cc_receive_icache_req = true; - r_cc_receive_icache_nline = DspinRwtParam::dspin_get(receive_data, + r_cc_receive_icache_nline = DspinRwtParam::dspin_get(receive_data, DspinRwtParam::BROADCAST_NLINE); r_cc_receive_icache_type = CC_TYPE_INVAL; @@ -6333,10 +6305,10 @@ uint64_t receive_data = p_dspin_m2p.data.read(); // for data INVAL, wait for dcache to take the request - if (p_dspin_m2p.write.read() and - not r_cc_receive_dcache_req.read() ) + if (p_dspin_m2p.write.read() and + not r_cc_receive_dcache_req.read()) { // request dcache to handle the INVAL r_cc_receive_dcache_req = true; - r_cc_receive_dcache_nline = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_INVAL_NLINE); + r_cc_receive_dcache_nline = DspinRwtParam::dspin_get(receive_data, DspinRwtParam::MULTI_INVAL_NLINE); r_cc_receive_dcache_type = CC_TYPE_INVAL; // get back to idle state @@ -6352,10 +6324,10 @@ uint64_t receive_data = p_dspin_m2p.data.read(); // for ins INVAL, wait for icache to take the request - if (p_dspin_m2p.write.read() and - not r_cc_receive_icache_req.read() ) + if (p_dspin_m2p.write.read() and + not r_cc_receive_icache_req.read()) { // request icache to handle the INVAL r_cc_receive_icache_req = true; - r_cc_receive_icache_nline = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_INVAL_NLINE); + r_cc_receive_icache_nline = DspinRwtParam::dspin_get(receive_data, DspinRwtParam::MULTI_INVAL_NLINE); r_cc_receive_icache_type = CC_TYPE_INVAL; // get back to idle state @@ -6374,5 +6346,5 @@ if (not r_cc_receive_dcache_req.read()) { - r_cc_receive_dcache_updt_tab_idx = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_UPDT_INDEX); + r_cc_receive_dcache_updt_tab_idx = DspinRwtParam::dspin_get(receive_data, DspinRwtParam::MULTI_UPDT_UPDT_INDEX); r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_NLINE; break; @@ -6389,5 +6361,5 @@ if (not r_cc_receive_icache_req.read()) { - r_cc_receive_icache_updt_tab_idx = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_UPDT_INDEX); + r_cc_receive_icache_updt_tab_idx = DspinRwtParam::dspin_get(receive_data, DspinRwtParam::MULTI_UPDT_UPDT_INDEX); r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_NLINE; break; @@ -6403,11 +6375,11 @@ // for data INVAL, wait for dcache to take the request and fifo to // be empty - if ( r_cc_receive_updt_fifo_be.empty() and - p_dspin_m2p.write.read() ) - { - r_cc_receive_dcache_req = true; - r_cc_receive_dcache_nline = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_NLINE); - r_cc_receive_word_idx = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_WORD_INDEX); - r_cc_receive_dcache_type = CC_TYPE_UPDT; + if (r_cc_receive_updt_fifo_be.empty() and + p_dspin_m2p.write.read()) + { + r_cc_receive_dcache_req = true; + r_cc_receive_dcache_nline = DspinRwtParam::dspin_get(receive_data, DspinRwtParam::MULTI_UPDT_NLINE); + r_cc_receive_word_idx = DspinRwtParam::dspin_get(receive_data, DspinRwtParam::MULTI_UPDT_WORD_INDEX); + r_cc_receive_dcache_type = CC_TYPE_UPDT; // get back to idle state r_cc_receive_fsm = CC_RECEIVE_DATA_UPDT_DATA; @@ -6423,11 +6395,11 @@ // for ins INVAL, wait for icache to take the request and fifo to be // empty - if ( r_cc_receive_updt_fifo_be.empty() and - p_dspin_m2p.write.read() ) - { - r_cc_receive_icache_req = true; - r_cc_receive_icache_nline = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_NLINE); - r_cc_receive_word_idx = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_WORD_INDEX); - r_cc_receive_icache_type = CC_TYPE_UPDT; + if (r_cc_receive_updt_fifo_be.empty() and + p_dspin_m2p.write.read()) + { + r_cc_receive_icache_req = true; + r_cc_receive_icache_nline = DspinRwtParam::dspin_get(receive_data, DspinRwtParam::MULTI_UPDT_NLINE); + r_cc_receive_word_idx = DspinRwtParam::dspin_get(receive_data, DspinRwtParam::MULTI_UPDT_WORD_INDEX); + r_cc_receive_icache_type = CC_TYPE_UPDT; // get back to idle state r_cc_receive_fsm = CC_RECEIVE_INS_UPDT_DATA; @@ -6444,9 +6416,9 @@ uint64_t receive_data = p_dspin_m2p.data.read(); bool receive_eop = p_dspin_m2p.eop.read(); - cc_receive_updt_fifo_be = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_BE); - cc_receive_updt_fifo_data = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_DATA); + cc_receive_updt_fifo_be = DspinRwtParam::dspin_get(receive_data, DspinRwtParam::MULTI_UPDT_BE); + cc_receive_updt_fifo_data = DspinRwtParam::dspin_get(receive_data, DspinRwtParam::MULTI_UPDT_DATA); cc_receive_updt_fifo_eop = receive_eop; cc_receive_updt_fifo_put = true; - if ( receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE; + if (receive_eop) r_cc_receive_fsm = CC_RECEIVE_IDLE; } break; @@ -6460,9 +6432,9 @@ uint64_t receive_data = p_dspin_m2p.data.read(); bool receive_eop = p_dspin_m2p.eop.read(); - cc_receive_updt_fifo_be = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_BE); - cc_receive_updt_fifo_data = DspinRwtParam::dspin_get(receive_data,DspinRwtParam::MULTI_UPDT_DATA); + cc_receive_updt_fifo_be = DspinRwtParam::dspin_get(receive_data, DspinRwtParam::MULTI_UPDT_BE); + cc_receive_updt_fifo_data = DspinRwtParam::dspin_get(receive_data, DspinRwtParam::MULTI_UPDT_DATA); cc_receive_updt_fifo_eop = receive_eop; cc_receive_updt_fifo_put = true; - if ( receive_eop ) r_cc_receive_fsm = CC_RECEIVE_IDLE; + if (receive_eop) r_cc_receive_fsm = CC_RECEIVE_IDLE; } break; @@ -6474,13 +6446,13 @@ uint64_t clack_type = DspinRwtParam::dspin_get(r_dspin_clack_flit.read(), - DspinRwtParam::CLACK_TYPE); - - size_t clack_way = DspinRwtParam::dspin_get(r_dspin_clack_flit.read(), - DspinRwtParam::CLACK_WAY); - - size_t clack_set = DspinRwtParam::dspin_get(r_dspin_clack_flit.read(), - DspinRwtParam::CLACK_SET); - - bool dspin_clack_get = false; + DspinRwtParam::CLACK_TYPE); + + size_t clack_way = DspinRwtParam::dspin_get(r_dspin_clack_flit.read(), + DspinRwtParam::CLACK_WAY); + + size_t clack_set = DspinRwtParam::dspin_get(r_dspin_clack_flit.read(), + DspinRwtParam::CLACK_SET); + + bool dspin_clack_get = false; bool dcache_clack_request = (clack_type == DspinRwtParam::TYPE_CLACK_DATA); bool icache_clack_request = (clack_type == DspinRwtParam::TYPE_CLACK_INST); @@ -6489,13 +6461,15 @@ { // CLACK DATA: Send request to DCACHE FSM - if (dcache_clack_request and not r_dcache_clack_req.read()){ + if (dcache_clack_request and not r_dcache_clack_req.read()) + { r_dcache_clack_req = true; - r_dcache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1); - r_dcache_clack_set = clack_set & ((1ULL<<(uint32_log2(m_dcache_sets)))-1); + r_dcache_clack_way = clack_way & ((1ULL << (uint32_log2(m_dcache_ways))) - 1); + r_dcache_clack_set = clack_set & ((1ULL << (uint32_log2(m_dcache_sets))) - 1); dspin_clack_get = true; } // CLACK INST: Send request to ICACHE FSM - else if (icache_clack_request and not r_icache_clack_req.read()){ + else if (icache_clack_request and not r_icache_clack_req.read()) + { r_icache_clack_req = true; r_icache_clack_way = clack_way & ((1ULL<<(uint32_log2(m_dcache_ways)))-1); @@ -6555,5 +6529,5 @@ bool is_sc_or_cas = (r_vci_cmd_fsm.read() == CMD_DATA_CAS) or - (r_vci_cmd_fsm.read() == CMD_DATA_SC ); + (r_vci_cmd_fsm.read() == CMD_DATA_SC); p_vci.pktid = 0; @@ -6565,8 +6539,8 @@ p_vci.cfixed = false; - if ( m_monitor_ok ) { - if ( p_vci.cmdack.read() == true and p_vci.cmdval == true) { + if (m_monitor_ok) { + if (p_vci.cmdack.read() == true and p_vci.cmdval == true) { if (((p_vci.address.read()) >= m_monitor_base) and - ((p_vci.address.read()) < m_monitor_base + m_monitor_length) ) { + ((p_vci.address.read()) < m_monitor_base + m_monitor_length)) { std::cout << "CC_VCACHE Monitor " << name() << std::hex << " Access type = " << vci_cmd_type_str[p_vci.cmd.read()] @@ -6574,5 +6548,5 @@ << " : address = " << p_vci.address.read() << " / be = " << p_vci.be.read(); - if ( p_vci.cmd.read() == vci_param::CMD_WRITE ) { + if (p_vci.cmd.read() == vci_param::CMD_WRITE) { std::cout << " / data = " << p_vci.wdata.read(); } @@ -6582,5 +6556,5 @@ } - switch ( r_vci_cmd_fsm.read() ) { + switch (r_vci_cmd_fsm.read()) { case CMD_IDLE: @@ -6683,6 +6657,6 @@ p_vci.cmdval = true; p_vci.address = r_dcache_vci_paddr.read() & ~0x3; - if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_llsc_key.read(); - else p_vci.wdata = r_dcache_vci_sc_data.read(); + if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_dcache_llsc_key.read(); + else p_vci.wdata = r_dcache_vci_sc_data.read(); p_vci.be = 0xF; p_vci.trdid = 0; @@ -6696,6 +6670,6 @@ p_vci.cmdval = true; p_vci.address = r_dcache_vci_paddr.read() & ~0x3; - if ( r_vci_cmd_cpt.read() == 0 ) p_vci.wdata = r_dcache_vci_cas_old.read(); - else p_vci.wdata = r_dcache_vci_cas_new.read(); + if (r_vci_cmd_cpt.read() == 0) p_vci.wdata = r_dcache_vci_cas_old.read(); + else p_vci.wdata = r_dcache_vci_cas_new.read(); p_vci.be = 0xF; p_vci.trdid = 0; @@ -6710,5 +6684,5 @@ // it depends on the VCI_RSP FSM - switch (r_vci_rsp_fsm.read() ) + switch (r_vci_rsp_fsm.read()) { case RSP_DATA_WRITE : p_vci.rspack = true; break; @@ -6726,5 +6700,5 @@ uint64_t dspin_send_data = 0; - switch ( r_cc_send_fsm.read() ) + switch (r_cc_send_fsm.read()) { ////////////////// @@ -6739,34 +6713,35 @@ // initialize dspin send data DspinRwtParam::dspin_set(dspin_send_data, - m_cc_global_id, - DspinRwtParam::CLEANUP_SRCID); + m_cc_global_id, + DspinRwtParam::CLEANUP_SRCID); DspinRwtParam::dspin_set(dspin_send_data, - 0, - DspinRwtParam::P2M_BC); - - if(r_cc_send_last_client.read() == 0) // dcache active request + 0, + DspinRwtParam::P2M_BC); + + if (r_cc_send_last_client.read() == 0) // dcache active request { uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read() >> (m_nline_width - m_x_width - m_y_width) << (DspinRwtParam::GLOBALID_WIDTH - m_x_width - m_y_width); + DspinRwtParam::dspin_set(dspin_send_data, - dest, - DspinRwtParam::CLEANUP_DEST); + dest, + DspinRwtParam::CLEANUP_DEST); DspinRwtParam::dspin_set(dspin_send_data, - (r_dcache_cc_send_nline.read() & 0x300000000ULL)>>32, - DspinRwtParam::CLEANUP_NLINE_MSB); + (r_dcache_cc_send_nline.read() & 0x300000000ULL) >> 32, + DspinRwtParam::CLEANUP_NLINE_MSB); DspinRwtParam::dspin_set(dspin_send_data, - r_dcache_cc_send_way.read(), - DspinRwtParam::CLEANUP_WAY_INDEX); + r_dcache_cc_send_way.read(), + DspinRwtParam::CLEANUP_WAY_INDEX); DspinRwtParam::dspin_set(dspin_send_data, - DspinRwtParam::TYPE_CLEANUP_DATA, - DspinRwtParam::P2M_TYPE); + DspinRwtParam::TYPE_CLEANUP_DATA, + DspinRwtParam::P2M_TYPE); DspinRwtParam::dspin_set(dspin_send_data, - (r_dcache_cc_cleanup_line_ncc.read() and (r_cc_send_last_client.read() == 0)), - DspinRwtParam::CLEANUP_NCC); + (r_dcache_cc_cleanup_line_ncc.read() and (r_cc_send_last_client.read() == 0)), + DspinRwtParam::CLEANUP_NCC); } else // icache active request @@ -6777,22 +6752,22 @@ DspinRwtParam::dspin_set(dspin_send_data, - dest, - DspinRwtParam::CLEANUP_DEST); + dest, + DspinRwtParam::CLEANUP_DEST); DspinRwtParam::dspin_set(dspin_send_data, - (r_icache_cc_send_nline.read() & 0x300000000ULL)>>32, - DspinRwtParam::CLEANUP_NLINE_MSB); + (r_icache_cc_send_nline.read() & 0x300000000ULL) >> 32, + DspinRwtParam::CLEANUP_NLINE_MSB); DspinRwtParam::dspin_set(dspin_send_data, - r_icache_cc_send_way.read(), - DspinRwtParam::CLEANUP_WAY_INDEX); + r_icache_cc_send_way.read(), + DspinRwtParam::CLEANUP_WAY_INDEX); DspinRwtParam::dspin_set(dspin_send_data, - DspinRwtParam::TYPE_CLEANUP_INST, - DspinRwtParam::P2M_TYPE); + DspinRwtParam::TYPE_CLEANUP_INST, + DspinRwtParam::P2M_TYPE); DspinRwtParam::dspin_set(dspin_send_data, - 0, - DspinRwtParam::CLEANUP_NCC); + 0, + DspinRwtParam::CLEANUP_NCC); @@ -6808,20 +6783,20 @@ { // initialize dspin send data - if(r_cc_send_last_client.read() == 0) // dcache active request + if (r_cc_send_last_client.read() == 0) // dcache active request { DspinRwtParam::dspin_set(dspin_send_data, - r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL, - DspinRwtParam::CLEANUP_NLINE_LSB); + r_dcache_cc_send_nline.read() & 0xFFFFFFFFULL, + DspinRwtParam::CLEANUP_NLINE_LSB); } else // icache active request { DspinRwtParam::dspin_set(dspin_send_data, - r_icache_cc_send_nline.read() & 0xFFFFFFFFULL, - DspinRwtParam::CLEANUP_NLINE_LSB); + r_icache_cc_send_nline.read() & 0xFFFFFFFFULL, + DspinRwtParam::CLEANUP_NLINE_LSB); } // send flit p_dspin_p2m.data = dspin_send_data; p_dspin_p2m.write = true; - p_dspin_p2m.eop = ! (r_dcache_cc_cleanup_updt_data.read() and (r_cc_send_last_client.read() == 0)); + p_dspin_p2m.eop = !(r_dcache_cc_cleanup_updt_data.read() and (r_cc_send_last_client.read() == 0)); break; } @@ -6831,10 +6806,10 @@ DspinRwtParam::dspin_set(dspin_send_data, - r_cc_send_data_fifo.read(), - DspinRwtParam::CLEANUP_DATA_UPDT); - - p_dspin_p2m.data = dspin_send_data; + r_cc_send_data_fifo.read(), + DspinRwtParam::CLEANUP_DATA_UPDT); + + p_dspin_p2m.data = dspin_send_data; p_dspin_p2m.write = true; - p_dspin_p2m.eop = (r_cc_send_cpt_word.read() == m_dcache_words-1); + p_dspin_p2m.eop = (r_cc_send_cpt_word.read() == m_dcache_words - 1); break; } @@ -6844,11 +6819,11 @@ // initialize dspin send data DspinRwtParam::dspin_set(dspin_send_data, - 0, - DspinRwtParam::P2M_BC); + 0, + DspinRwtParam::P2M_BC); DspinRwtParam::dspin_set(dspin_send_data, - DspinRwtParam::TYPE_MULTI_ACK, - DspinRwtParam::P2M_TYPE); - - if(r_cc_send_last_client.read() == 0) // dcache active request + DspinRwtParam::TYPE_MULTI_ACK, + DspinRwtParam::P2M_TYPE); + + if (r_cc_send_last_client.read() == 0) // dcache active request { uint64_t dest = (uint64_t) r_dcache_cc_send_nline.read() @@ -6857,10 +6832,10 @@ DspinRwtParam::dspin_set(dspin_send_data, - dest, - DspinRwtParam::MULTI_ACK_DEST); + dest, + DspinRwtParam::MULTI_ACK_DEST); DspinRwtParam::dspin_set(dspin_send_data, - r_dcache_cc_send_updt_tab_idx.read(), - DspinRwtParam::MULTI_ACK_UPDT_INDEX); + r_dcache_cc_send_updt_tab_idx.read(), + DspinRwtParam::MULTI_ACK_UPDT_INDEX); } else // icache active request @@ -6872,10 +6847,10 @@ DspinRwtParam::dspin_set(dspin_send_data, - dest, - DspinRwtParam::MULTI_ACK_DEST); + dest, + DspinRwtParam::MULTI_ACK_DEST); DspinRwtParam::dspin_set(dspin_send_data, - r_icache_cc_send_updt_tab_idx.read(), - DspinRwtParam::MULTI_ACK_UPDT_INDEX); + r_icache_cc_send_updt_tab_idx.read(), + DspinRwtParam::MULTI_ACK_UPDT_INDEX); } // send flit @@ -6890,5 +6865,5 @@ // Receive coherence packets // It depends on the CC_RECEIVE FSM - switch( r_cc_receive_fsm.read() ) + switch (r_cc_receive_fsm.read()) { ///////////////////// @@ -6946,5 +6921,5 @@ case CC_RECEIVE_INS_UPDT_HEADER: { - if ( not r_cc_receive_icache_req.read()) + if (not r_cc_receive_icache_req.read()) p_dspin_m2p.read = true; else @@ -6956,5 +6931,5 @@ case CC_RECEIVE_INS_UPDT_NLINE: { - if(r_cc_receive_updt_fifo_be.empty()) + if (r_cc_receive_updt_fifo_be.empty()) p_dspin_m2p.read = true; else @@ -6976,5 +6951,5 @@ int clack_type = DspinRwtParam::dspin_get(r_dspin_clack_flit.read(), - DspinRwtParam::CLACK_TYPE); + DspinRwtParam::CLACK_TYPE); bool dspin_clack_get = false; @@ -7007,12 +6982,12 @@ // This version of monitor print both Read and Write request { - m_monitor_ok = true; - m_monitor_base = base; - m_monitor_length = length; + m_monitor_ok = true; + m_monitor_base = base; + m_monitor_length = length; } tmpl(void)::stop_monitor() { - m_monitor_ok = false; + m_monitor_ok = false; }