- Timestamp:
- Oct 3, 2014, 5:16:54 PM (10 years ago)
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branches/reconfiguration/platforms/tsar_generic_iob/scripts/arch.py
r806 r831 1 1 #!/usr/bin/env python 2 """This file contains a mapping generator for the tsar_generic_iob platform""" 3 2 4 from math import log 3 from mapping import *4 5 ################################################################################ #######5 from mapping import Mapping 6 7 ################################################################################ 6 8 # file : arch.py (for the tsar_generic_iob architecture) 7 9 # date : may 2014 8 10 # author : Alain Greiner 9 ####################################################################################### 10 # This file contains a mapping generator for the "tsar_generic_iob" platform. 11 # This includes both the hardware architecture (clusters, processors, peripherals, 12 # physical space segmentation) and the mapping of all kernel objects (global vsegs). 13 # This platform includes 6 external peripherals, accessible through two IO_Bridge 14 # components located in cluster [0,0] and cluster [x_size-1, y_size-1]. 15 # Available peripherals are: TTY, BDV, FBF, ROM, NIC, CMA. 11 # 12 # modified by: 13 # Cesar Fuguet 14 # - Adding distributed ROMs used by the distributed reconfiguration 15 # procedure 16 # 17 ################################################################################ 18 # This platform includes 6 external peripherals, accessible through two 19 # IO_Bridge components located in cluster [0,0] and cluster [x_size-1, 20 # y_size-1]. Available peripherals are: TTY, BDV, FBF, ROM, NIC, CMA. 16 21 # 17 22 # The "constructor" parameters are: … … 19 24 # - y_size : number of clusters in a column 20 25 # - nb_procs : number of processors per cluster 26 # - fbf_width : frame_buffer width = frame_buffer heigth 21 27 # 22 28 # The "hidden" parameters (defined below) are: 23 # - nb_ttys : number of TTY channels 24 # - nb_nics : number of NIC channels 25 # - fbf_width : frame_buffer width = frame_buffer heigth 26 # - x_io : cluster_io x coordinate 27 # - y_io : cluster_io y coordinate 28 # - x_width : number of bits for x coordinate 29 # - y_width : number of bits for y coordinate 29 # - NB_TTYS : number of TTY channels 30 # - NB_NICS : number of NIC channels 31 # - X_IO : cluster_io x coordinate 32 # - Y_IO : cluster_io y coordinate 33 # - X_WIDTH : number of bits for x coordinate 34 # - Y_WIDTH : number of bits for y coordinate 30 35 # - p_width : number of bits for processor local id field 31 # - paddr_width : number of bits for physical address 32 # - irq_per_proc : number of input IRQs per processor 33 # - use_ramdisk : use a ramdisk when True 34 # - peri_increment : address increment for replicated peripherals 35 #################################################################################### 36 37 ######################## 38 def arch( x_size = 2, 39 y_size = 2, 40 nb_procs = 2 ): 41 42 ### define architecture constants 43 44 nb_ttys = 1 45 nb_nics = 2 46 fbf_width = 128 47 x_io = 0 48 y_io = 0 49 x_width = 4 50 y_width = 4 51 p_width = log(nb_procs, 2) 52 paddr_width = 40 53 irq_per_proc = 4 54 use_ramdisk = False 55 peri_increment = 0x10000 56 distributed_ptabs = True 57 58 ### parameters checking 59 60 assert( nb_procs <= 4 ) 61 62 assert( (x_size == 1) or (x_size == 2) or (x_size == 4) 63 or (x_size == 8) or (x_size == 16) ) 64 65 assert( (y_size == 1) or (y_size == 2) or (y_size == 4) 66 or (y_size == 8) or (y_size == 16) ) 67 68 assert( nb_ttys == 1 ) 69 70 assert( ((x_io == 0) and (y_io == 0)) or 71 ((x_io == x_size-1) and (y_io == y_size-1)) ) 72 73 platform_name = 'tsar_iob_%d_%d_%d' % ( x_size, y_size, nb_procs ) 74 75 ### define physical segments 76 77 ram_base = 0x0000000000 78 if 0: ram_size = 0x4000000 # 64 Mbytes 79 else: ram_size = 0x0040000 # 256 Kbytes 80 81 xcu_base = 0x00B0000000 82 xcu_size = 0x1000 # 4 Kbytes 83 84 dma_base = 0x00B1000000 85 dma_size = 0x1000 * nb_procs # 4 Kbytes * nb_procs 86 87 mmc_base = 0x00B2000000 88 mmc_size = 0x1000 # 4 Kbytes 89 90 rom_base = 0x00BFC00000 91 rom_size = 0x8000 # 32 Kbytes 92 93 offset_io = ((x_io << y_width) + y_io) << (paddr_width - x_width - y_width) 94 95 bdv_base = 0x00B3000000 + offset_io 96 bdv_size = 0x1000 # 4kbytes 97 98 tty_base = 0x00B4000000 + offset_io 99 tty_size = 0x4000 # 16 Kbytes 100 101 nic_base = 0x00B5000000 + offset_io 102 nic_size = 0x80000 # 512 kbytes 103 104 cma_base = 0x00B6000000 + offset_io 105 cma_size = 0x1000 * 2 * nb_nics # 4 kbytes * 2 * nb_nics 106 107 fbf_base = 0x00B7000000 + offset_io 108 fbf_size = fbf_width * fbf_width # fbf_width * fbf_width bytes 109 110 pic_base = 0x00B8000000 + offset_io 111 pic_size = 0x1000 # 4 Kbytes 112 113 sim_base = 0x00B9000000 + offset_io 114 sim_size = 0x1000 # 4 kbytes 115 116 iob_base = 0x00BE000000 + offset_io 117 iob_size = 0x1000 # 4 kbytes 118 119 ### GIET_VM specifics virtual segments 120 ### define bootloader vsegs base addresses 121 122 boot_mapping_vbase = 0x00000000 # ident 123 boot_mapping_size = 0x00080000 # 512 Kbytes 124 125 boot_code_vbase = 0x00080000 # ident 126 boot_code_size = 0x00040000 # 256 Kbytes 127 128 boot_data_vbase = 0x000C0000 # ident 129 boot_data_size = 0x00080000 # 512 Kbytes 130 131 boot_stack_vbase = 0x00140000 # ident 132 boot_stack_size = 0x00050000 # 320 Kbytes 133 134 ### define kernel vsegs base addresses and sizes 135 136 kernel_code_vbase = 0x80000000 137 kernel_code_size = 0x00020000 # 128 Kbytes 138 139 kernel_data_vbase = 0x80020000 140 kernel_data_size = 0x00020000 # 128 Kbytes 141 142 kernel_uncdata_vbase = 0x80040000 143 kernel_uncdata_size = 0x00010000 # 64 Kbytes 144 145 kernel_init_vbase = 0x80050000 146 kernel_init_size = 0x00010000 # 64 Kbytes 147 148 kernel_sched_vbase = 0xF0000000 # distributed in all clusters 149 kernel_sched_size = 0x2000 * nb_procs # 8 kbytes per processor 150 151 ### create mapping 152 153 mapping = Mapping( name = platform_name, 154 x_size = x_size, 155 y_size = y_size, 156 procs_max = nb_procs, 157 x_width = x_width, 158 y_width = y_width, 159 paddr_width = paddr_width, 160 coherence = True, 161 irq_per_proc = irq_per_proc, 162 use_ramdisk = use_ramdisk, 163 x_io = x_io, 164 y_io = y_io, 165 peri_increment = peri_increment, 166 ram_base = ram_base, 167 ram_size = ram_size ) 168 169 ### external peripherals (accessible in cluster[0,0] only for this mapping) 170 171 iob = mapping.addPeriph( 'IOB', base = iob_base, size = iob_size, ptype = 'IOB' ) 172 173 bdv = mapping.addPeriph( 'BDV', base = bdv_base, size = bdv_size, ptype = 'IOC', subtype = 'BDV' ) 174 175 tty = mapping.addPeriph( 'TTY', base = tty_base, size = tty_size, ptype = 'TTY', channels = nb_ttys ) 176 177 nic = mapping.addPeriph( 'NIC', base = nic_base, size = nic_size, ptype = 'NIC', channels = nb_nics ) 178 179 cma = mapping.addPeriph( 'CMA', base = cma_base, size = cma_size, ptype = 'CMA', channels = 2*nb_nics ) 180 181 fbf = mapping.addPeriph( 'FBF', base = fbf_base, size = fbf_size, ptype = 'FBF', arg = fbf_width ) 182 183 pic = mapping.addPeriph( 'PIC', base = pic_base, size = pic_size, ptype = 'PIC', channels = 32 ) 184 185 sim = mapping.addPeriph( 'SIM', base = sim_base, size = sim_size, ptype = 'SIM' ) 186 187 mapping.addIrq( pic, index = 0, isrtype = 'ISR_NIC_RX', channel = 0 ) 188 mapping.addIrq( pic, index = 1, isrtype = 'ISR_NIC_RX', channel = 1 ) 189 190 mapping.addIrq( pic, index = 2, isrtype = 'ISR_NIC_TX', channel = 0 ) 191 mapping.addIrq( pic, index = 3, isrtype = 'ISR_NIC_TX', channel = 1 ) 192 193 mapping.addIrq( pic, index = 4, isrtype = 'ISR_CMA' , channel = 0 ) 194 mapping.addIrq( pic, index = 5, isrtype = 'ISR_CMA' , channel = 1 ) 195 mapping.addIrq( pic, index = 6, isrtype = 'ISR_CMA' , channel = 2 ) 196 mapping.addIrq( pic, index = 7, isrtype = 'ISR_CMA' , channel = 3 ) 197 198 mapping.addIrq( pic, index = 8, isrtype = 'ISR_BDV' , channel = 0 ) 199 200 mapping.addIrq( pic, index = 9, isrtype = 'ISR_TTY_RX', channel = 0 ) 201 202 ### hardware components replicated in all clusters 203 204 for x in xrange( x_size ): 205 for y in xrange( y_size ): 206 cluster_xy = (x << y_width) + y; 207 offset = cluster_xy << (paddr_width - x_width - y_width) 208 209 ram = mapping.addRam( 'RAM', base = ram_base + offset, size = ram_size ) 210 211 mmc = mapping.addPeriph( 'MMC', base = mmc_base + offset, size = mmc_size, 212 ptype = 'MMC' ) 213 214 dma = mapping.addPeriph( 'DMA', base = dma_base + offset, size = dma_size, 215 ptype = 'DMA', channels = nb_procs ) 216 217 xcu = mapping.addPeriph( 'XCU', base = xcu_base + offset, size = xcu_size, 218 ptype = 'XCU', channels = nb_procs * irq_per_proc, arg = 16 ) 219 220 rom = mapping.addPeriph( 'ROM', base = rom_base + offset, size = rom_size, 221 ptype = 'ROM' ) 36 # - PADDR_WIDTH : number of bits for physical address 37 # - IRQ_PER_PROC : number of input IRQs per processor 38 # - USE_RAMDISK : use a ramdisk when True 39 # - PERI_INCREMENT : virtual address increment for replicated peripherals 40 # - PTAB_INCREMENT : virtual address increment for replicated page tables 41 # - SCHED_INCREMENT: virtual address increment for replicated schedulers 42 ################################################################################ 43 44 # define architecture constants 45 PADDR_WIDTH = 40 46 NB_TTYS = 1 47 NB_NICS = 2 48 FBF_WIDTH = 128 49 X_WIDTH = 4 50 Y_WIDTH = 4 51 X_IO = 0 52 Y_IO = 0 53 IRQ_PER_PROC = 4 54 USE_RAMDISK = False 55 56 # virtual address increment for distributed memory segments in the GietVM OS 57 PERI_INCREMENT = 0x10000 58 PTAB_INCREMENT = 0x200000 59 SCHED_INCREMENT = 0x10000 60 61 def pmsb(x, y): 62 """This function returns the physical most signicant bits for the 63 cluster(x,y)""" 64 65 return (x << X_WIDTH) | y 66 67 def arch(x_size=2, 68 y_size=2, 69 nb_procs=4, 70 fbf_width=FBF_WIDTH): 71 """This function describes the tsar_generic_iob platform and defines its 72 parameters""" 73 74 p_width = log(nb_procs, 2) 75 76 # parameters checking 77 assert nb_procs <= 4 78 79 assert ((x_size == 1) or (x_size == 2) or (x_size == 4) or (x_size == 8) or 80 (x_size == 16)) 81 82 assert ((y_size == 1) or (y_size == 2) or (y_size == 4) or (y_size == 8) or 83 (y_size == 16)) 84 85 assert NB_TTYS == 1 86 87 assert (((X_IO == 0) and (Y_IO == 0)) or 88 ((X_IO == x_size-1) and (Y_IO == y_size-1))) 89 90 platform_name = 'reconf-tsar_iob_%d_%d_%d' % (x_size, y_size, nb_procs) 91 92 # define physical segments 93 ram_base = 0x0000000000 94 if 1: 95 ram_size = 0x4000000 # 64 Mbytes 96 else: 97 ram_size = 0x0040000 # 256 Kbytes 98 99 xcu_base = 0x00B0000000 100 xcu_size = 0x1000 # 4 Kbytes 101 102 dma_base = 0x00B1000000 103 dma_size = 0x1000 * nb_procs # 4 Kbytes * nb_procs 104 105 mmc_base = 0x00B2000000 106 mmc_size = 0x1000 # 4 Kbytes 107 108 rom_base = 0x00BFC00000 109 rom_size = 0x8000 # 32 Kbytes 110 111 offset_io = pmsb(X_IO, Y_IO) << (PADDR_WIDTH - X_WIDTH - Y_WIDTH) 112 113 bdv_base = 0x00B3000000 + offset_io 114 bdv_size = 0x1000 # 4 kbytes 115 116 tty_base = 0x00B4000000 + offset_io 117 tty_size = 0x1000 # 4 Kbytes 118 119 nic_base = 0x00B5000000 + offset_io 120 nic_size = 0x80000 # 512 kbytes 121 122 cma_base = 0x00B6000000 + offset_io 123 cma_size = 0x1000 * 2 * NB_NICS # 4 kbytes * 2 * NB_NICS 124 125 fbf_base = 0x00B7000000 + offset_io 126 fbf_size = fbf_width * fbf_width # fbf_width * fbf_width bytes 127 128 pic_base = 0x00B8000000 + offset_io 129 pic_size = 0x1000 # 4 Kbytes 130 131 sim_base = 0x00B9000000 + offset_io 132 sim_size = 0x1000 # 4 kbytes 133 134 iob_base = 0x00BE000000 + offset_io 135 iob_size = 0x1000 # 4 kbytes 136 137 # create mapping 138 mapping = Mapping(name=platform_name, 139 x_size=x_size, 140 y_size=y_size, 141 nprocs=nb_procs, 142 x_width=X_WIDTH, 143 y_width=Y_WIDTH, 144 p_width=p_width, 145 paddr_width=PADDR_WIDTH, 146 coherence=True, 147 irq_per_proc=IRQ_PER_PROC, 148 use_ramdisk=USE_RAMDISK, 149 x_io=X_IO, 150 y_io=Y_IO, 151 peri_increment=PERI_INCREMENT, 152 ram_base=ram_base, 153 ram_size=ram_size) 154 155 # external peripherals (accessible in cluster[0,0] only for this mapping) 156 mapping.addPeriph('IOB', base=iob_base, size=iob_size, 157 ptype='IOB') 158 159 mapping.addPeriph('BDV', base=bdv_base, size=bdv_size, 160 ptype='IOC', subtype='BDV') 161 162 mapping.addPeriph('TTY', base=tty_base, size=tty_size, 163 ptype='TTY', channels=NB_TTYS) 164 165 mapping.addPeriph('NIC', base=nic_base, size=nic_size, 166 ptype='NIC', channels=NB_NICS) 167 168 mapping.addPeriph('CMA', base=cma_base, size=cma_size, 169 ptype='CMA', channels=2*NB_NICS) 170 171 mapping.addPeriph('FBF', base=fbf_base, size=fbf_size, 172 ptype='FBF', arg=fbf_width) 173 174 mapping.addPeriph('SIM', base=sim_base, size=sim_size, 175 ptype='SIM') 176 177 pic = mapping.addPeriph('PIC', base=pic_base, size=pic_size, 178 ptype='PIC', channels=32) 179 180 mapping.addIrq(pic, index=0, isrtype='ISR_NIC_RX', channel=0) 181 mapping.addIrq(pic, index=1, isrtype='ISR_NIC_RX', channel=1) 182 mapping.addIrq(pic, index=2, isrtype='ISR_NIC_TX', channel=0) 183 mapping.addIrq(pic, index=3, isrtype='ISR_NIC_TX', channel=1) 184 mapping.addIrq(pic, index=4, isrtype='ISR_CMA', channel=0) 185 mapping.addIrq(pic, index=5, isrtype='ISR_CMA', channel=1) 186 mapping.addIrq(pic, index=6, isrtype='ISR_CMA', channel=2) 187 mapping.addIrq(pic, index=7, isrtype='ISR_CMA', channel=3) 188 mapping.addIrq(pic, index=8, isrtype='ISR_BDV', channel=0) 189 mapping.addIrq(pic, index=9, isrtype='ISR_TTY_RX', channel=0) 190 191 # hardware components replicated in all clusters 192 for x in xrange(x_size): 193 for y in xrange(y_size): 194 offset = pmsb(x, y) << (PADDR_WIDTH - X_WIDTH - Y_WIDTH) 195 196 mapping.addRam('RAM', base=ram_base + offset, size=ram_size) 197 198 mapping.addPeriph('MMC', base=mmc_base + offset, size=mmc_size, 199 ptype='MMC') 200 201 mapping.addPeriph('ROM', base=rom_base + offset, size=rom_size, 202 ptype='ROM') 203 204 dma = mapping.addPeriph('DMA', base=dma_base + offset, 205 size=dma_size, ptype='DMA', 206 channels=nb_procs) 207 208 xcu = mapping.addPeriph('XCU', base=xcu_base + offset, 209 size=xcu_size, ptype='XCU', 210 channels=nb_procs * IRQ_PER_PROC, 211 arg=16) 222 212 223 213 # MMC IRQ replicated in all clusters 224 mapping.addIrq( xcu, index = 0, isrtype = 'ISR_MMC')214 mapping.addIrq(xcu, index=0, isrtype='ISR_MMC') 225 215 226 216 # DMA IRQ replicated in all clusters 227 for i in xrange ( dma.channels):228 mapping.addIrq( xcu, index = 1+i, isrtype ='ISR_DMA',229 channel = i)217 for i in xrange(dma.channels): 218 mapping.addIrq(xcu, index=1+i, isrtype='ISR_DMA', 219 channel=i) 230 220 231 221 # processors 232 for p in xrange ( nb_procs ): 233 mapping.addProc( x, y, p ) 234 235 ### global vsegs for boot_loader / identity mapping 236 237 mapping.addGlobal( 'seg_boot_mapping', boot_mapping_vbase, boot_mapping_size, 238 'C_W_', vtype = 'BLOB' , x = 0, y = 0, pseg = 'RAM', 239 identity = True ) 240 241 mapping.addGlobal( 'seg_boot_code', boot_code_vbase, boot_code_size, 242 'CXW_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', 243 identity = True ) 244 245 mapping.addGlobal( 'seg_boot_data', boot_data_vbase, boot_data_size, 246 'C_W_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', 247 identity = True ) 248 249 mapping.addGlobal( 'seg_boot_stack', boot_stack_vbase, boot_stack_size, 250 'C_W_', vtype = 'BUFFER', x = 0, y = 0, pseg = 'RAM', 251 identity = True ) 252 253 ### the code global vsegs for kernel can be replicated in all clusters 254 ### if the page tables are distributed in all clusters. 255 256 if distributed_ptabs: 257 for x in xrange( x_size ): 258 for y in xrange( y_size ): 259 cluster_xy = (x << y_width) + y; 260 261 mapping.addGlobal( 'seg_kernel_code', kernel_code_vbase, kernel_code_size, 262 'CXW_', vtype = 'ELF', x = x , y = y , pseg = 'RAM', 263 binpath = 'build/kernel/kernel.elf', local = True ) 264 265 mapping.addGlobal( 'seg_kernel_init', kernel_init_vbase, kernel_init_size, 266 'CXW_', vtype = 'ELF', x = x , y = y , pseg = 'RAM', 267 binpath = 'build/kernel/kernel.elf', local = True ) 268 else: 269 mapping.addGlobal( 'seg_kernel_code', kernel_code_vbase, kernel_code_size, 270 'CXW_', vtype = 'ELF', x = 0 , y = 0 , pseg = 'RAM', 271 binpath = 'build/kernel/kernel.elf', local = False ) 272 273 mapping.addGlobal( 'seg_kernel_init', kernel_init_vbase, kernel_init_size, 274 'CXW_', vtype = 'ELF', x = 0 , y = 0 , pseg = 'RAM', 275 binpath = 'build/kernel/kernel.elf', local = False ) 276 277 ### shared global vsegs for kernel 278 279 mapping.addGlobal( 'seg_kernel_data', kernel_data_vbase, kernel_data_size, 280 'C_W_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', 281 binpath = 'build/kernel/kernel.elf', local = False ) 282 283 mapping.addGlobal( 'seg_kernel_uncdata', kernel_uncdata_vbase, kernel_uncdata_size, 284 '__W_', vtype = 'ELF', x = 0, y = 0, pseg = 'RAM', 285 binpath = 'build/kernel/kernel.elf', local = False ) 286 287 ### global vsegs for external peripherals / identity mapping 288 289 mapping.addGlobal( 'seg_iob', iob_base, iob_size, '__W_', 290 vtype = 'PERI', x = 0, y = 0, pseg = 'IOB', 291 identity = True ) 292 293 mapping.addGlobal( 'seg_bdv', bdv_base, bdv_size, '__W_', 294 vtype = 'PERI', x = 0, y = 0, pseg = 'BDV', 295 identity = True ) 296 297 mapping.addGlobal( 'seg_tty', tty_base, tty_size, '__W_', 298 vtype = 'PERI', x = 0, y = 0, pseg = 'TTY', 299 identity = True ) 300 301 mapping.addGlobal( 'seg_nic', nic_base, nic_size, '__W_', 302 vtype = 'PERI', x = 0, y = 0, pseg = 'NIC', 303 identity = True ) 304 305 mapping.addGlobal( 'seg_cma', cma_base, cma_size, '__W_', 306 vtype = 'PERI', x = 0, y = 0, pseg = 'CMA', 307 identity = True ) 308 309 mapping.addGlobal( 'seg_fbf', fbf_base, fbf_size, '__W_', 310 vtype = 'PERI', x = 0, y = 0, pseg = 'FBF', 311 identity = True ) 312 313 mapping.addGlobal( 'seg_pic', pic_base, pic_size, '__W_', 314 vtype = 'PERI', x = 0, y = 0, pseg = 'PIC', 315 identity = True ) 316 317 mapping.addGlobal( 'seg_sim', sim_base, sim_size, '__W_', 318 vtype = 'PERI', x = 0, y = 0, pseg = 'SIM', 319 identity = True ) 320 321 ### global vsegs for internal peripherals, and for schedulers 322 ### name is indexed by (x,y) / vbase address is incremented by (cluster_xy * peri_increment) 323 324 for x in xrange( x_size ): 325 for y in xrange( y_size ): 326 cluster_xy = (x << y_width) + y; 327 offset = cluster_xy * peri_increment 328 329 mapping.addGlobal( 'seg_rom_%d_%d' %(x,y), rom_base + offset, rom_size, 330 'CX__', vtype = 'PERI' , x = x , y = y , pseg = 'ROM' ) 331 332 mapping.addGlobal( 'seg_xcu_%d_%d' %(x,y), xcu_base + offset, xcu_size, 333 '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'XCU' ) 334 335 mapping.addGlobal( 'seg_dma_%d_%d' %(x,y), dma_base + offset, dma_size, 336 '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'DMA' ) 337 338 mapping.addGlobal( 'seg_mmc_%d_%d' %(x,y), mmc_base + offset, mmc_size, 339 '__W_', vtype = 'PERI' , x = x , y = y , pseg = 'MMC' ) 340 341 mapping.addGlobal( 'seg_sched_%d_%d' %(x,y), kernel_sched_vbase + offset, kernel_sched_size, 342 'C_W_', vtype = 'SCHED', x = x , y = y , pseg = 'RAM' ) 343 344 ### return mapping ### 222 for p in xrange(nb_procs): 223 mapping.addProc(x, y, p) 224 225 ############################################################################ 226 # GIET_VM specifics 227 228 # define bootloader vsegs base addresses 229 bmapping_vbase = 0x00001000 # ident 230 bmapping_size = 0x0007F000 # 508 Kbytes 231 232 bcode_vbase = 0x00080000 # ident 233 bcode_size = 0x00040000 # 256 Kbytes 234 235 bdata_vbase = 0x000C0000 # ident 236 bdata_size = 0x00080000 # 512 Kbytes 237 238 bstack_vbase = 0x00140000 # ident 239 bstack_size = 0x00050000 # 320 Kbytes 240 241 # define kernel vsegs base addresses and sizes 242 kcode_vbase = 0x80000000 243 kcode_size = 0x00080000 # 512 Kbytes 244 245 kinit_vbase = 0x80800000 246 kinit_size = 0x00080000 # 512 Kbytes 247 248 kdata_vbase = 0x80100000 249 kdata_size = 0x00080000 # 512 Kbytes 250 251 kuncdata_vbase = 0x80180000 252 kuncdata_size = 0x00001000 # 4 Kbytes 253 254 kptab_vbase = 0xC0000000 255 kptab_size = 0x00200000 # 512 Kbytes 256 257 ksched_vbase = 0xF0000000 # distributed in all clusters 258 ksched_size = 0x2000 * nb_procs # 8 kbytes per processor 259 260 # global vsegs for boot_loader / identity mapping 261 mapping.addGlobal('seg_boot_mapping', bmapping_vbase, bmapping_size, 262 'CXW_', vtype='BLOB', x=0, y=0, pseg='RAM', 263 identity=True, local=False, big=True) 264 265 mapping.addGlobal('seg_boot_code', bcode_vbase, bcode_size, 266 'CXW_', vtype='BUFFER', x=0, y=0, pseg='RAM', 267 identity=True, local=False, big=True) 268 269 mapping.addGlobal('seg_boot_data', bdata_vbase, bdata_size, 270 'CXW_', vtype='BUFFER', x=0, y=0, pseg='RAM', 271 identity=True, local=False, big=True) 272 273 mapping.addGlobal('seg_boot_stack', bstack_vbase, bstack_size, 274 'CXW_', vtype='BUFFER', x=0, y=0, pseg='RAM', 275 identity=True, local=False, big=True) 276 277 # the code global vsegs for kernel can be replicated in all clusters 278 # if the page tables are distributed in all clusters. 279 for x in xrange(x_size): 280 for y in xrange(y_size): 281 mapping.addGlobal('seg_kernel_code', kcode_vbase, kcode_size, 282 'CXW_', vtype='ELF', x=x, y=y, pseg='RAM', 283 binpath='build/kernel/kernel.elf', 284 local=True, big=True) 285 286 mapping.addGlobal('seg_kernel_init', kinit_vbase, kinit_size, 287 'CXW_', vtype='ELF', x=x, y=y, pseg='RAM', 288 binpath='build/kernel/kernel.elf', 289 local=True, big=True) 290 291 offset = pmsb(x, y) * PTAB_INCREMENT 292 mapping.addGlobal('seg_kernel_ptab_%d_%d' % (x, y), 293 kptab_vbase + offset, kptab_size, 'C_W_', 294 vtype='PTAB', x=x, y=y, pseg='RAM', 295 local=False, big=True) 296 297 298 offset = pmsb(x, y) * SCHED_INCREMENT 299 mapping.addGlobal('seg_kernel_sched_%d_%d' % (x, y), 300 ksched_vbase + offset, ksched_size, 'C_W_', 301 vtype='SCHED', x=x, y=y, pseg='RAM', 302 local=False, big=False) 303 304 # shared global vsegs for kernel 305 mapping.addGlobal('seg_kernel_data', kdata_vbase, kdata_size, 306 'CXW_', vtype='ELF', x=0, y=0, pseg='RAM', 307 binpath='build/kernel/kernel.elf', local=False, 308 big=True) 309 310 mapping.addGlobal('seg_kernel_uncdata', kuncdata_vbase, kuncdata_size, 311 'CXW_', vtype='ELF', x=0, y=0, pseg='RAM', 312 binpath='build/kernel/kernel.elf', local=False, 313 big=True) 314 315 # global vsegs for external peripherals / identity mapping 316 mapping.addGlobal('seg_iob', iob_base, iob_size, '__W_', vtype='PERI', 317 x=X_IO, y=Y_IO, pseg='IOB', local=False, big=False) 318 319 mapping.addGlobal('seg_bdv', bdv_base, bdv_size, '__W_', vtype='PERI', 320 x=X_IO, y=Y_IO, pseg='BDV', local=False, big=False) 321 322 mapping.addGlobal('seg_tty', tty_base, tty_size, '__W_', vtype='PERI', 323 x=X_IO, y=Y_IO, pseg='TTY', local=False, big=False) 324 325 mapping.addGlobal('seg_nic', nic_base, nic_size, '__W_', vtype='PERI', 326 x=X_IO, y=Y_IO, pseg='NIC', local=False, big=False) 327 328 mapping.addGlobal('seg_cma', cma_base, cma_size, '__W_', vtype='PERI', 329 x=X_IO, y=Y_IO, pseg='CMA', local=False, big=False) 330 331 mapping.addGlobal('seg_fbf', fbf_base, fbf_size, '__W_', vtype='PERI', 332 x=X_IO, y=Y_IO, pseg='FBF', local=False, big=True) 333 334 mapping.addGlobal('seg_pic', pic_base, pic_size, '__W_', vtype='PERI', 335 x=X_IO, y=Y_IO, pseg='PIC', local=False, big=False) 336 337 mapping.addGlobal('seg_sim', sim_base, sim_size, '__W_', vtype='PERI', 338 x=X_IO, y=Y_IO, pseg='SIM', local=False, big=False) 339 340 # global vsegs for internal peripherals 341 for x in xrange(x_size): 342 for y in xrange(y_size): 343 offset = pmsb(x, y) * PERI_INCREMENT 344 345 mapping.addGlobal('seg_rom_%d_%d' % (x, y), rom_base + offset, 346 rom_size, 'CX__', vtype='PERI', x=x, y=y, 347 pseg='ROM', local=False, big=False) 348 349 mapping.addGlobal('seg_xcu_%d_%d' % (x, y), xcu_base + offset, 350 xcu_size, '__W_', vtype='PERI', x=x, y=y, 351 pseg='XCU', local=False, big=False) 352 353 mapping.addGlobal('seg_dma_%d_%d' % (x, y), dma_base + offset, 354 dma_size, '__W_', vtype='PERI', x=x, y=y, 355 pseg='DMA', local=False, big=False) 356 357 mapping.addGlobal('seg_mmc_%d_%d' % (x, y), mmc_base + offset, 358 mmc_size, '__W_', vtype='PERI', x=x, y=y, 359 pseg='MMC', local=False, big=False) 345 360 346 361 return mapping 347 362 348 363 def main(x, y, p, hard_path, xml_path): 349 mapping = arch( x_size = x, 350 y_size = y, 351 nb_procs = p) 364 """main function: it generates the map.xml and the hard_config.h file based 365 on the Mapping object returned by arch()""" 366 mapping = arch(x_size=x, 367 y_size=y, 368 nb_procs=p) 352 369 353 370 with open(xml_path, "w") as map_xml: … … 356 373 hard_config.write(mapping.hard_config()) 357 374 358 ################################# platform test ################################ #######################375 ################################# platform test ################################ 359 376 import sys 360 377 if __name__ == '__main__': 361 main( x_size = int(sys.argv[1]), 362 y_size = int(sys.argv[2]), 363 nb_procs = int(sys.argv[3])) 378 main(x=int(sys.argv[1]), 379 y=int(sys.argv[2]), 380 p=int(sys.argv[3]), 381 hard_path="hard_config.test.h", 382 xml_path="map.test.xml") 364 383 365 384 # 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