Index: /trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp =================================================================== --- /trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 835) +++ /trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (revision 836) @@ -1387,6 +1387,6 @@ int state; paddr_t tag; - size_t way = r_icache_flush_count.read()/m_icache_sets; - size_t set = r_icache_flush_count.read()%m_icache_sets; + size_t way = r_icache_flush_count.read() / m_icache_sets; + size_t set = r_icache_flush_count.read() % m_icache_sets; #ifdef INSTRUMENTATION @@ -2438,5 +2438,5 @@ if (m_dreq.type == iss_t::XTN_READ) { - int xtn_opcode = (int)m_dreq.addr / 4; + int xtn_opcode = (int) m_dreq.addr / 4; // checking processor mode: @@ -2972,5 +2972,5 @@ // itlb miss request - else if (r_icache_tlb_miss_req.read() and not wbuf_write_miss ) + else if (r_icache_tlb_miss_req.read() and not wbuf_write_miss) { r_dcache_tlb_ins = true; @@ -3111,5 +3111,5 @@ } - else if (entry & PTE_T_MASK ) // PTD : me must access PT2 + else if (entry & PTE_T_MASK) // PTD : me must access PT2 { // mark the cache line ac containing a PTD @@ -3847,6 +3847,6 @@ int state; paddr_t tag; - size_t way = r_dcache_flush_count.read()/m_dcache_sets; - size_t set = r_dcache_flush_count.read()%m_dcache_sets; + size_t way = r_dcache_flush_count.read() / m_dcache_sets; + size_t set = r_dcache_flush_count.read() % m_dcache_sets; #ifdef INSTRUMENTATION @@ -4460,7 +4460,7 @@ r_dcache_contains_ptd[way * m_dcache_sets + set] = false; } - if (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET; - else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET; - else r_dcache_fsm = DCACHE_IDLE; + if (r_dcache_miss_type.read() == PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET; + else if (r_dcache_miss_type.read() == PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET; + else r_dcache_fsm = DCACHE_IDLE; } break; @@ -4760,6 +4760,6 @@ } - assert ( not r_dcache_cc_send_req.read() and - "CC_SEND must be available in DCACHE_CC_CHECK" ); + assert(not r_dcache_cc_send_req.read() and + "CC_SEND must be available in DCACHE_CC_CHECK"); // Match between MISS address and CC address @@ -6021,5 +6021,5 @@ p_vci.trdid = 0; p_vci.pktid = TYPE_READ_INS_MISS; - p_vci.plen = m_icache_words<<2; + p_vci.plen = m_icache_words << 2; p_vci.cmd = vci_param::CMD_READ; p_vci.eop = true; Index: /trunk/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd =================================================================== --- /trunk/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd (revision 835) +++ /trunk/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd (revision 836) @@ -15,6 +15,6 @@ cell_size = parameter.Reference('memc_cell_size_ext') ), - parameter.Int('dspin_in_width'), - parameter.Int('dspin_out_width'), + parameter.Int('memc_dspin_in_width'), + parameter.Int('memc_dspin_out_width'), ], @@ -50,13 +50,13 @@ Port('caba:dspin_input', 'p_dspin_p2m', - dspin_data_size = parameter.Reference('dspin_in_width') + dspin_data_size = parameter.Reference('memc_dspin_in_width') ), Port('caba:dspin_output', 'p_dspin_m2p', - dspin_data_size = parameter.Reference('dspin_out_width') + dspin_data_size = parameter.Reference('memc_dspin_out_width') ), Port('caba:dspin_output', 'p_dspin_clack', - dspin_data_size = parameter.Reference('dspin_out_width') + dspin_data_size = parameter.Reference('memc_dspin_out_width') ), ], Index: /trunk/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h =================================================================== --- /trunk/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h (revision 835) +++ /trunk/modules/vci_mem_cache/caba/source/include/mem_cache_directory.h (revision 836) @@ -12,62 +12,62 @@ namespace soclib { namespace caba { - using namespace sc_core; - - //////////////////////////////////////////////////////////////////////// - // A LRU entry - //////////////////////////////////////////////////////////////////////// - class LruEntry { +using namespace sc_core; + +//////////////////////////////////////////////////////////////////////// +// A LRU entry +//////////////////////////////////////////////////////////////////////// +class LruEntry { public: - bool recent; - - void init() - { - recent=false; - } - - }; // end class LruEntry - - //////////////////////////////////////////////////////////////////////// - // An Owner - //////////////////////////////////////////////////////////////////////// - class Owner{ - + bool recent; + + void init() + { + recent = false; + } + +}; // end class LruEntry + +//////////////////////////////////////////////////////////////////////// +// An Owner +//////////////////////////////////////////////////////////////////////// +class Owner{ + public: - // Fields - bool inst; // Is the owner an ICache ? - size_t srcid; // The SRCID of the owner - - //////////////////////// - // Constructors - //////////////////////// - Owner(bool i_inst, - size_t i_srcid) - { - inst = i_inst; - srcid = i_srcid; - } - - Owner(const Owner &a) - { - inst = a.inst; - srcid = a.srcid; - } - - Owner() - { - inst = false; - srcid = 0; - } - // end constructors - - }; // end class Owner - - - //////////////////////////////////////////////////////////////////////// - // A directory entry - //////////////////////////////////////////////////////////////////////// - class DirectoryEntry { + // Fields + bool inst; // Is the owner an ICache ? + size_t srcid; // The SRCID of the owner + + //////////////////////// + // Constructors + //////////////////////// + Owner(bool i_inst, + size_t i_srcid) + { + inst = i_inst; + srcid = i_srcid; + } + + Owner(const Owner &a) + { + inst = a.inst; + srcid = a.srcid; + } + + Owner() + { + inst = false; + srcid = 0; + } + // end constructors + +}; // end class Owner + + +//////////////////////////////////////////////////////////////////////// +// A directory entry +//////////////////////////////////////////////////////////////////////// +class DirectoryEntry { typedef uint32_t tag_t; @@ -75,36 +75,36 @@ public: - bool valid; // entry valid - bool is_cnt; // directory entry is in counter mode - bool dirty; // entry dirty - bool lock; // entry locked - tag_t tag; // tag of the entry - size_t count; // number of copies - Owner owner; // an owner of the line - size_t ptr; // pointer to the next owner + bool valid; // entry valid + bool is_cnt; // directory entry is in counter mode + bool dirty; // entry dirty + bool lock; // entry locked + tag_t tag; // tag of the entry + size_t count; // number of copies + Owner owner; // an owner of the line + size_t ptr; // pointer to the next owner DirectoryEntry() { - valid = false; - is_cnt = false; - dirty = false; - lock = false; - tag = 0; - count = 0; - owner.inst = 0; - owner.srcid = 0; - ptr = 0; + valid = false; + is_cnt = false; + dirty = false; + lock = false; + tag = 0; + count = 0; + owner.inst = 0; + owner.srcid = 0; + ptr = 0; } DirectoryEntry(const DirectoryEntry &source) { - valid = source.valid; - is_cnt = source.is_cnt; - dirty = source.dirty; - lock = source.lock; - tag = source.tag; - count = source.count; - owner = source.owner; - ptr = source.ptr; + valid = source.valid; + is_cnt = source.is_cnt; + dirty = source.dirty; + lock = source.lock; + tag = source.tag; + count = source.count; + owner = source.owner; + ptr = source.ptr; } @@ -114,9 +114,9 @@ void init() { - valid = false; - is_cnt = false; - dirty = false; - lock = false; - count = 0; + valid = false; + is_cnt = false; + dirty = false; + lock = false; + count = 0; } @@ -126,12 +126,12 @@ void copy(const DirectoryEntry &source) { - valid = source.valid; - is_cnt = source.is_cnt; - dirty = source.dirty; - lock = source.lock; - tag = source.tag; - count = source.count; - owner = source.owner; - ptr = source.ptr; + valid = source.valid; + is_cnt = source.is_cnt; + dirty = source.dirty; + lock = source.lock; + tag = source.tag; + count = source.count; + owner = source.owner; + ptr = source.ptr; } @@ -141,21 +141,21 @@ void print() { - std::cout << "Valid = " << valid - << " ; IS COUNT = " << is_cnt - << " ; Dirty = " << dirty - << " ; Lock = " << lock - << " ; Tag = " << std::hex << tag << std::dec - << " ; Count = " << count - << " ; Owner = " << owner.srcid - << " " << owner.inst - << " ; Pointer = " << ptr << std::endl; + std::cout << "Valid = " << valid + << " ; IS COUNT = " << is_cnt + << " ; Dirty = " << dirty + << " ; Lock = " << lock + << " ; Tag = " << std::hex << tag << std::dec + << " ; Count = " << count + << " ; Owner = " << owner.srcid + << " " << owner.inst + << " ; Pointer = " << ptr << std::endl; } - }; // end class DirectoryEntry - - //////////////////////////////////////////////////////////////////////// - // The directory - //////////////////////////////////////////////////////////////////////// - class CacheDirectory { +}; // end class DirectoryEntry + +//////////////////////////////////////////////////////////////////////// +// The directory +//////////////////////////////////////////////////////////////////////// +class CacheDirectory { typedef sc_dt::sc_uint<40> addr_t; @@ -166,13 +166,13 @@ // Directory constants - size_t m_ways; - size_t m_sets; - size_t m_words; - size_t m_width; - uint32_t lfsr; + size_t m_ways; + size_t m_sets; + size_t m_words; + size_t m_width; + uint32_t lfsr; // the directory & lru tables - DirectoryEntry **m_dir_tab; - LruEntry **m_lru_tab; + DirectoryEntry ** m_dir_tab; + LruEntry ** m_lru_tab; public: @@ -181,22 +181,22 @@ // Constructor //////////////////////// - CacheDirectory( size_t ways, size_t sets, size_t words, size_t address_width) - { - m_ways = ways; - m_sets = sets; - m_words = words; - m_width = address_width; - lfsr = -1; - - m_dir_tab = new DirectoryEntry*[sets]; - for ( size_t i=0; i> (L2(m_words) + 2)) & (m_sets - 1); - tag_t tag = (tag_t)(address >> (L2(m_sets) + L2(m_words) + 2)); + size_t set = (size_t) (address >> (L2(m_words) + 2)) & (m_sets - 1); + tag_t tag = (tag_t) (address >> (L2(m_sets) + L2(m_words) + 2)); #undef L2 - for ( size_t way = 0 ; way < m_ways ; way++ ) - { - bool equal = ( m_dir_tab[set][way].tag == tag ); + for (size_t way = 0; way < m_ways; way++) + { + bool equal = (m_dir_tab[set][way].tag == tag); bool valid = m_dir_tab[set][way].valid; - if ( equal and valid ) + if (equal and valid) { *ret_set = set; @@ -301,30 +301,28 @@ // - entry : the entry value ///////////////////////////////////////////////////////////////////// - void write( const size_t &set, - const size_t &way, - const DirectoryEntry &entry) - { - assert( (set0 && "Memory Cache, HeapDirectory constructor : invalid size"); - ptr_free = 0; - full = false; - m_heap_tab = new HeapEntry[size]; - tab_size = size; - } // end constructor - - ///////////////// - // Destructor - ///////////////// - ~HeapDirectory(){ - delete [] m_heap_tab; - } // end destructor - - ///////////////////////////////////////////////////////////////////// - // Global initialisation function - ///////////////////////////////////////////////////////////////////// - void init(){ - ptr_free=0; - full=false; - for(size_t i=0; i< tab_size-1;i++){ - m_heap_tab[i].next = i+1; - } - m_heap_tab[tab_size-1].next = tab_size-1; - return; - } - - ///////////////////////////////////////////////////////////////////// - // The print() function prints a selected directory entry - // Arguments : - // - ptr : the pointer to the entry to print - ///////////////////////////////////////////////////////////////////// - void print(const size_t &ptr){ - std::cout << "Heap, printing the entry : " << std::dec << ptr << std::endl; - m_heap_tab[ptr].print(); - } // end print() - - ///////////////////////////////////////////////////////////////////// - // The print_list() function prints a list from selected directory entry - // Arguments : - // - ptr : the pointer to the first entry to print - ///////////////////////////////////////////////////////////////////// - void print_list(const size_t &ptr){ - bool end = false; - size_t ptr_temp = ptr; - std::cout << "Heap, printing the list from : " << std::dec << ptr << std::endl; - while(!end){ - m_heap_tab[ptr_temp].print(); - if(ptr_temp == m_heap_tab[ptr_temp].next) end = true; - ptr_temp = m_heap_tab[ptr_temp].next; - } - } // end print_list() - - ///////////////////////////////////////////////////////////////////// - // The is_full() function return true if the heap is full. - ///////////////////////////////////////////////////////////////////// - bool is_full(){ - return full; - } // end is_full() - - ///////////////////////////////////////////////////////////////////// - // The next_free_ptr() function returns the pointer - // to the next free entry. - ///////////////////////////////////////////////////////////////////// - size_t next_free_ptr(){ - return ptr_free; - } // end next_free_ptr() - - ///////////////////////////////////////////////////////////////////// - // The next_free_entry() function returns - // a copy of the next free entry. - ///////////////////////////////////////////////////////////////////// - HeapEntry next_free_entry(){ - return HeapEntry(m_heap_tab[ptr_free]); - } // end next_free_entry() - - ///////////////////////////////////////////////////////////////////// - // The write_free_entry() function modify the next free entry. - // Arguments : - // - entry : the entry to write - ///////////////////////////////////////////////////////////////////// - void write_free_entry(const HeapEntry &entry){ - m_heap_tab[ptr_free].copy(entry); - } // end write_free_entry() - - ///////////////////////////////////////////////////////////////////// - // The write_free_ptr() function writes the pointer - // to the next free entry - ///////////////////////////////////////////////////////////////////// - void write_free_ptr(const size_t &ptr){ - assert( (ptr 0 && "Memory Cache, HeapDirectory constructor : invalid size"); + ptr_free = 0; + full = false; + m_heap_tab = new HeapEntry[size]; + tab_size = size; + } // end constructor + + ///////////////// + // Destructor + ///////////////// + ~HeapDirectory() { + delete [] m_heap_tab; + } // end destructor + + ///////////////////////////////////////////////////////////////////// + // Global initialisation function + ///////////////////////////////////////////////////////////////////// + void init() { + ptr_free = 0; + full = false; + for (size_t i = 0; i< tab_size - 1; i++){ + m_heap_tab[i].next = i + 1; + } + m_heap_tab[tab_size - 1].next = tab_size - 1; + return; + } + + ///////////////////////////////////////////////////////////////////// + // The print() function prints a selected directory entry + // Arguments : + // - ptr : the pointer to the entry to print + ///////////////////////////////////////////////////////////////////// + void print(const size_t &ptr) { + std::cout << "Heap, printing the entry : " << std::dec << ptr << std::endl; + m_heap_tab[ptr].print(); + } // end print() + + ///////////////////////////////////////////////////////////////////// + // The print_list() function prints a list from selected directory entry + // Arguments : + // - ptr : the pointer to the first entry to print + ///////////////////////////////////////////////////////////////////// + void print_list(const size_t &ptr) { + bool end = false; + size_t ptr_temp = ptr; + std::cout << "Heap, printing the list from : " << std::dec << ptr << std::endl; + while (!end){ + m_heap_tab[ptr_temp].print(); + if (ptr_temp == m_heap_tab[ptr_temp].next) { + end = true; + } + ptr_temp = m_heap_tab[ptr_temp].next; + } + } // end print_list() + + ///////////////////////////////////////////////////////////////////// + // The is_full() function return true if the heap is full. + ///////////////////////////////////////////////////////////////////// + bool is_full() { + return full; + } // end is_full() + + ///////////////////////////////////////////////////////////////////// + // The next_free_ptr() function returns the pointer + // to the next free entry. + ///////////////////////////////////////////////////////////////////// + size_t next_free_ptr() { + return ptr_free; + } // end next_free_ptr() + + ///////////////////////////////////////////////////////////////////// + // The next_free_entry() function returns + // a copy of the next free entry. + ///////////////////////////////////////////////////////////////////// + HeapEntry next_free_entry() { + return HeapEntry(m_heap_tab[ptr_free]); + } // end next_free_entry() + + ///////////////////////////////////////////////////////////////////// + // The write_free_entry() function modify the next free entry. + // Arguments : + // - entry : the entry to write + ///////////////////////////////////////////////////////////////////// + void write_free_entry(const HeapEntry &entry){ + m_heap_tab[ptr_free].copy(entry); + } // end write_free_entry() + + ///////////////////////////////////////////////////////////////////// + // The write_free_ptr() function writes the pointer + // to the next free entry + ///////////////////////////////////////////////////////////////////// + void write_free_ptr(const size_t &ptr){ + assert((ptr < tab_size) && "HeapDirectory error : try to write a wrong free pointer"); + ptr_free = ptr; + } // end write_free_ptr() + + ///////////////////////////////////////////////////////////////////// + // The set_full() function sets the full bit (to true). + ///////////////////////////////////////////////////////////////////// + void set_full() { + full = true; + } // end set_full() + + ///////////////////////////////////////////////////////////////////// + // The unset_full() function unsets the full bit (to false). + ///////////////////////////////////////////////////////////////////// + void unset_full() { + full = false; + } // end unset_full() + + ///////////////////////////////////////////////////////////////////// + // The read() function returns a copy of + // the entry pointed by the argument + // Arguments : + // - ptr : the pointer to the entry to read + ///////////////////////////////////////////////////////////////////// + HeapEntry read(const size_t &ptr) { + assert((ptr < tab_size) && "HeapDirectory error : try to write a wrong free pointer"); + return HeapEntry(m_heap_tab[ptr]); + } // end read() + + ///////////////////////////////////////////////////////////////////// + // The write() function writes an entry in the heap + // Arguments : + // - ptr : the pointer to the entry to replace + // - entry : the entry to write + ///////////////////////////////////////////////////////////////////// + void write(const size_t &ptr, const HeapEntry &entry) { + assert((ptr < tab_size) && "HeapDirectory error : try to write a wrong free pointer"); + m_heap_tab[ptr].copy(entry); + } // end write() + +}; // end class HeapDirectory + +//////////////////////////////////////////////////////////////////////// +// Cache Data +//////////////////////////////////////////////////////////////////////// +class CacheData +{ private: - const uint32_t m_sets; - const uint32_t m_ways; - const uint32_t m_words; - - uint32_t *** m_cache_data; + const uint32_t m_sets; + const uint32_t m_ways; + const uint32_t m_words; + + uint32_t *** m_cache_data; public: - /////////////////////////////////////////////////////// - CacheData(uint32_t ways, uint32_t sets, uint32_t words) - : m_sets(sets), m_ways(ways), m_words(words) - { - m_cache_data = new uint32_t ** [ways]; - for ( size_t i=0 ; i < ways ; i++ ) - { - m_cache_data[i] = new uint32_t * [sets]; - } - for ( size_t i=0; i * cache_line) - { - assert((set < m_sets ) && "Cache data error: Trying to read a wrong set" ); - assert((way < m_ways ) && "Cache data error: Trying to read a wrong way" ); - - for (uint32_t word=0; word * cache_line) + { + assert((set < m_sets) && "Cache data error: Trying to read a wrong set" ); + assert((way < m_ways) && "Cache data error: Trying to read a wrong way" ); + + for (uint32_t word = 0; word < m_words; word++) { + cache_line[word].write(m_cache_data[way][set][word]); + } + } + ///////////////////////////////////////// + void write (const uint32_t &way, + const uint32_t &set, + const uint32_t &word, + const uint32_t &data, + const uint32_t &be = 0xF) + { + + assert((set < m_sets) && "Cache data error: Trying to write a wrong set" ); + assert((way < m_ways) && "Cache data error: Trying to write a wrong way" ); + assert((word < m_words) && "Cache data error: Trying to write a wrong word"); + assert((be <= 0xF) && "Cache data error: Trying to write a wrong be"); + + if (be == 0x0) return; + + if (be == 0xF) + { + m_cache_data[way][set][word] = data; + return; + } + + uint32_t mask = 0; + if (be & 0x1) mask = mask | 0x000000FF; + if (be & 0x2) mask = mask | 0x0000FF00; + if (be & 0x4) mask = mask | 0x00FF0000; + if (be & 0x8) mask = mask | 0xFF000000; + + m_cache_data[way][set][word] = + (data & mask) | (m_cache_data[way][set][word] & ~mask); + } +}; // end class CacheData }} // end namespaces Index: /trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h =================================================================== --- /trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h (revision 835) +++ /trunk/modules/vci_mem_cache/caba/source/include/vci_mem_cache.h (revision 836) @@ -64,6 +64,6 @@ template + size_t memc_dspin_in_width, + size_t memc_dspin_out_width> class VciMemCache : public soclib::caba::BaseModule @@ -470,7 +470,7 @@ soclib::caba::VciTarget p_vci_tgt; soclib::caba::VciInitiator p_vci_ixr; - soclib::caba::DspinInput p_dspin_p2m; - soclib::caba::DspinOutput p_dspin_m2p; - soclib::caba::DspinOutput p_dspin_clack; + soclib::caba::DspinInput p_dspin_p2m; + soclib::caba::DspinOutput p_dspin_m2p; + soclib::caba::DspinOutput p_dspin_clack; #if MONITOR_MEMCACHE_FSM == 1 Index: /trunk/modules/vci_mem_cache/caba/source/include/xram_transaction.h =================================================================== --- /trunk/modules/vci_mem_cache/caba/source/include/xram_transaction.h (revision 835) +++ /trunk/modules/vci_mem_cache/caba/source/include/xram_transaction.h (revision 836) @@ -15,24 +15,24 @@ class TransactionTabEntry { - typedef sc_dt::sc_uint<64> wide_data_t; - typedef sc_dt::sc_uint<40> addr_t; - typedef uint32_t data_t; - typedef uint32_t be_t; + typedef sc_dt::sc_uint<64> wide_data_t; + typedef sc_dt::sc_uint<40> addr_t; + typedef uint32_t data_t; + typedef uint32_t be_t; public: - bool valid; // entry valid - bool xram_read; // read request to XRAM - addr_t nline; // index (zy) of the requested line - size_t srcid; // processor requesting the transaction - size_t trdid; // processor requesting the transaction - size_t pktid; // processor requesting the transaction - bool proc_read; // read request from processor - size_t read_length; // length of the read (for the response) - size_t word_index; // index of the first read word (for response) - std::vector wdata; // write buffer (one cache line) - std::vector wdata_be; // be for each data in the write buffer - bool rerror; // error returned by xram - data_t ll_key; // LL key returned by the llsc_global_table - bool config; // transaction required by CONFIG FSM + bool valid; // entry valid + bool xram_read; // read request to XRAM + addr_t nline; // index (zy) of the requested line + size_t srcid; // processor requesting the transaction + size_t trdid; // processor requesting the transaction + size_t pktid; // processor requesting the transaction + bool proc_read; // read request from processor + size_t read_length; // length of the read (for the response) + size_t word_index; // index of the first read word (for response) + std::vector wdata; // write buffer (one cache line) + std::vector wdata_be; // be for each data in the write buffer + bool rerror; // error returned by xram + data_t ll_key; // LL key returned by the llsc_global_table + bool config; // transaction required by CONFIG FSM ///////////////////////////////////////////////////////////////////// @@ -41,7 +41,7 @@ void init() { - valid = false; - rerror = false; - config = false; + valid = false; + rerror = false; + config = false; } @@ -52,7 +52,7 @@ void alloc(size_t n_words) { - wdata_be.reserve( (int)n_words ); - wdata.reserve( (int)n_words ); - for(size_t i=0; i wide_data_t; - typedef sc_dt::sc_uint<40> addr_t; - typedef uint32_t data_t; - typedef uint32_t be_t; + typedef sc_dt::sc_uint<64> wide_data_t; + typedef sc_dt::sc_uint<40> addr_t; + typedef uint32_t data_t; + typedef uint32_t be_t; private: - const std::string tab_name; // the name for logs - size_t size_tab; // the size of the tab + const std::string tab_name; // the name for logs + size_t size_tab; // the size of the tab data_t be_to_mask(be_t be) { data_t ret = 0; - if ( be&0x1 ) { + if (be & 0x1) { ret = ret | 0x000000FF; } - if ( be&0x2 ) { + if (be & 0x2) { ret = ret | 0x0000FF00; } - if ( be&0x4 ) { + if (be & 0x4) { ret = ret | 0x00FF0000; } - if ( be&0x8 ) { + if (be & 0x8) { ret = ret | 0xFF000000; } @@ -177,23 +177,23 @@ public: - TransactionTabEntry *tab; // The transaction tab - - //////////////////////////////////////////////////////////////////// - // Constructors + TransactionTabEntry * tab; // The transaction tab + + //////////////////////////////////////////////////////////////////// + // Constructors //////////////////////////////////////////////////////////////////// TransactionTab() { - size_tab=0; - tab=NULL; + size_tab = 0; + tab = NULL; } TransactionTab(const std::string &name, - size_t n_entries, - size_t n_words ) - : tab_name( name ), - size_tab( n_entries ) + size_t n_entries, + size_t n_words) + : tab_name(name), + size_tab(n_entries) { tab = new TransactionTabEntry[size_tab]; - for ( size_t i=0; i" << std::endl; - for ( size_t id = 0 ; id < size_tab ; id++ ) + for (size_t id = 0; id < size_tab; id++) { tab[id].print( id , detailed ); @@ -241,6 +241,5 @@ TransactionTabEntry read(const size_t index) { - assert( (index < size_tab) and - "MEMC ERROR: Invalid Transaction Tab Entry"); + assert((index < size_tab) and "MEMC ERROR: Invalid Transaction Tab Entry"); return tab[index]; @@ -252,12 +251,12 @@ // The function returns true if the transaction tab is full ///////////////////////////////////////////////////////////////////// - bool full(size_t &index) - { - for(size_t i=0; i &be, - const std::vector &data) + const std::vector & be, + const std::vector & data) { assert( (index < size_tab) and - "MEMC ERROR: The selected entry is out of range in TRT write_data_mask()"); - - assert( (be.size()==tab[index].wdata_be.size()) and - "MEMC ERROR: Bad be size in TRT write_data_mask()"); - - assert( (data.size()==tab[index].wdata.size()) and - "MEMC ERROR: Bad data size in TRT write_data_mask()"); - - for(size_t i=0; i &data_be, - const std::vector &data, + const std::vector & data_be, + const std::vector & data, const data_t ll_key = 0, const bool config = false) { - assert( (index < size_tab) and - "MEMC ERROR: The selected entry is out of range in TRT set()"); - - assert( (data_be.size()==tab[index].wdata_be.size()) and - "MEMC ERROR: Bad data_be argument in TRT set()"); - - assert( (data.size()==tab[index].wdata.size()) and - "MEMC ERROR: Bad data argument in TRT set()"); - - tab[index].valid = true; - tab[index].xram_read = xram_read; - tab[index].nline = nline; - tab[index].srcid = srcid; - tab[index].trdid = trdid; - tab[index].pktid = pktid; - tab[index].proc_read = proc_read; - tab[index].read_length = read_length; - tab[index].word_index = word_index; - tab[index].ll_key = ll_key; - tab[index].config = config; - for(size_t i=0; i>32); - mask = be_to_mask(tab[index].wdata_be[word+1]); - tab[index].wdata[word+1] = (tab[index].wdata[word+1] & mask) | (value & ~mask); + value = (data_t) (data >> 32); + mask = be_to_mask(tab[index].wdata_be[word + 1]); + tab[index].wdata[word + 1] = (tab[index].wdata[word + 1] & mask) | (value & ~mask); } ///////////////////////////////////////////////////////////////////// @@ -443,8 +442,8 @@ { assert( (index < size_tab) and - "MEMC ERROR: The selected entry is out of range in TRT erase()"); - - tab[index].valid = false; - tab[index].rerror = false; + "MEMC ERROR: The selected entry is out of range in TRT erase()"); + + tab[index].valid = false; + tab[index].rerror = false; } ///////////////////////////////////////////////////////////////////// @@ -456,5 +455,5 @@ { assert( (index < size_tab) and - "MEMC ERROR: The selected entry is out of range in TRT is_config()"); + "MEMC ERROR: The selected entry is out of range in TRT is_config()"); return tab[index].config; Index: /trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp =================================================================== --- /trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 835) +++ /trunk/modules/vci_mem_cache/caba/source/src/vci_mem_cache.cpp (revision 836) @@ -319,7 +319,7 @@ template x \ - VciMemCache + size_t memc_dspin_in_width, \ + size_t memc_dspin_out_width> x \ + VciMemCache using namespace soclib::common; Index: /trunk/platforms/almos-tsar-mipsel/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd =================================================================== --- /trunk/platforms/almos-tsar-mipsel/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd (revision 835) +++ /trunk/platforms/almos-tsar-mipsel/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd (revision 836) @@ -34,6 +34,6 @@ memc_cell_size_int = parameter.Reference('vci_data_width_int'), memc_cell_size_ext = parameter.Reference('vci_data_width_ext'), - dspin_in_width = parameter.Reference('dspin_rsp_width'), - dspin_out_width = parameter.Reference('dspin_cmd_width')), + memc_dspin_in_width = parameter.Reference('dspin_rsp_width'), + memc_dspin_out_width = parameter.Reference('dspin_cmd_width')), Uses('caba:vci_simple_rom', Index: /trunk/platforms/linux_monocluster/desc.py =================================================================== --- /trunk/platforms/linux_monocluster/desc.py (revision 835) +++ /trunk/platforms/linux_monocluster/desc.py (revision 836) @@ -23,6 +23,6 @@ memc_cell_size_int = cell_size, memc_cell_size_ext = 8, - dspin_out_width = dspin_cmd_flit_size, - dspin_in_width = dspin_rsp_flit_size, + memc_dspin_out_width = dspin_cmd_flit_size, + memc_dspin_in_width = dspin_rsp_flit_size, ), Uses('caba:dspin_local_crossbar', Index: /trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd =================================================================== --- /trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd (revision 835) +++ /trunk/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd (revision 836) @@ -39,8 +39,8 @@ Uses('caba:vci_mem_cache', - memc_cell_size_int = parameter.Reference('vci_data_width_int'), - memc_cell_size_ext = parameter.Reference('vci_data_width_ext'), - dspin_in_width = parameter.Reference('dspin_int_rsp_width'), - dspin_out_width = parameter.Reference('dspin_int_cmd_width')), + memc_cell_size_int = parameter.Reference('vci_data_width_int'), + memc_cell_size_ext = parameter.Reference('vci_data_width_ext'), + memc_dspin_in_width = parameter.Reference('dspin_int_rsp_width'), + memc_dspin_out_width = parameter.Reference('dspin_int_cmd_width')), Uses('caba:vci_xicu', Index: /trunk/platforms/tsar_generic_leti/tsar_leti_cluster/caba/metadata/tsar_leti_cluster.sd =================================================================== --- /trunk/platforms/tsar_generic_leti/tsar_leti_cluster/caba/metadata/tsar_leti_cluster.sd (revision 835) +++ /trunk/platforms/tsar_generic_leti/tsar_leti_cluster/caba/metadata/tsar_leti_cluster.sd (revision 836) @@ -32,8 +32,8 @@ Uses('caba:vci_mem_cache', - memc_cell_size_int = parameter.Reference('vci_data_width_int'), - memc_cell_size_ext = parameter.Reference('vci_data_width_ext'), - dspin_in_width = parameter.Reference('dspin_rsp_width'), - dspin_out_width = parameter.Reference('dspin_cmd_width')), + memc_cell_size_int = parameter.Reference('vci_data_width_int'), + memc_cell_size_ext = parameter.Reference('vci_data_width_ext'), + memc_dspin_in_width = parameter.Reference('dspin_rsp_width'), + memc_dspin_out_width = parameter.Reference('dspin_cmd_width')), Uses('caba:vci_simple_ram', Index: /trunk/platforms/tsar_generic_xbar/scripts/counter_defs.py =================================================================== --- /trunk/platforms/tsar_generic_xbar/scripts/counter_defs.py (revision 835) +++ /trunk/platforms/tsar_generic_xbar/scripts/counter_defs.py (revision 836) @@ -9,5 +9,5 @@ m_prot_name['dhccp'] = "DHCCP" m_prot_name['rwt'] = "RWT" -m_prot_name['mesi'] = "HMESI" +m_prot_name['hmesi'] = "HMESI" m_app_name = {} Index: /trunk/platforms/tsar_generic_xbar/scripts/create_graphs.py =================================================================== --- /trunk/platforms/tsar_generic_xbar/scripts/create_graphs.py (revision 835) +++ /trunk/platforms/tsar_generic_xbar/scripts/create_graphs.py (revision 836) @@ -7,10 +7,10 @@ -#apps = [ 'histogram', 'mandel', 'filter', 'radix', 'fft_ga' ] -#apps = [ 'histogram', 'mandel', 'filter', 'radix', 'radix_ga', 'fft', 'fft_ga', 'filt_ga', 'kmeans', 'pca', 'lu' ] -apps = [ 'fft', 'fft_ga' ] -nb_procs = [ 1, 4, 8, 16, 32, 64, 128, 256 ] -single_protocols = ['dhccp', 'rwt'] -joint_protocols = ['dhccp', 'rwt'] +apps = [ 'filter', 'lu', 'fft_ga' ] +#apps = [ 'histogram', 'mandel', 'filter', 'fft', 'fft_ga', 'filt_ga', 'pca', 'lu' ] # radix radix_ga kmeans +#apps = [ 'filt_ga' ] +nb_procs = [ 1, 4, 8, 16, 32, 64 ] +single_protocols = ['dhccp', 'rwt' ] +joint_protocols = ['dhccp', 'rwt' ] #joint_protocols = [] @@ -403,5 +403,5 @@ gp_stacked_name = os.path.join(scripts_path, gen_dir, prot + '_stacked.gp') - norm_factor_value = 256 + norm_factor_value = nb_procs[-1] # Creating the gp file @@ -616,7 +616,7 @@ gp_cost_filename = os.path.join(scripts_path, gen_dir, 'joint_relative_cost.gp') -direct_cost_metrics = [ 'read_cost', 'write_cost' ] -coherence_cost_metrics = ['update_cost', 'm_inv_cost', 'broadcast_cost' ] - +direct_cost_metrics = [ 'read_cost', 'write_cost', 'getm_cost' ] +coherence_cost_metrics = ['update_cost', 'm_inv_cost', 'broadcast_cost', 'inval_ro_cost', 'cleanup_cost', 'cleanup_d_cost' ] + # Creating the gp file template_file = open(stacked_tmpl, 'r') @@ -702,4 +702,84 @@ - - +################################################################################# +### Graph 9 : ### +################################################################################# + + +data_metric_filename = os.path.join(scripts_path, gen_dir, 'single_metric.dat') +gp_metric_filename = os.path.join(scripts_path, gen_dir, 'single_metric.gp') + +metric = 'total_write' + +# Creating the gp file +template_file = open(stacked_tmpl, 'r') +template = template_file.read() + +xtics_str = "(" +first = True +xpos = 0 # successive x position of the center of the first bar in a application +app_labels = "" +prot_labels = "" +for num_appli in range(0, len(apps)): + first_proc = True + for i in nb_procs: + x = 0 # local var for computing position of protocol names + #for prot in joint_protocols: + #prot_labels += "set label \"%s\" at first %f, character 2 center font \"Times,10\"\n" % (m_prot_name[prot], float((xpos - 0.5)) + x) # -0.5 instead of +0.5, don't know why... (bug gnuplot?) + #x += 1 + + if not first: + xtics_str += ", " + first = False + if first_proc: + first_proc = False + xpos_first = xpos + xtics_str += "\"%d\" %f -1" % (i, float(xpos - 0.5 + len(joint_protocols))) + xpos_last = xpos + xpos += 1 + len(joint_protocols) + app_name_xpos = float((xpos_first + xpos_last)) / 2 + app_labels += "set label \"%s\" at first %f,character 1 center font \"Times,12\"\n" % (m_app_name[apps[num_appli]], app_name_xpos) + xpos += 1 +xtics_str += ")" + +n = 1 +plot_str = "newhistogram \"\"" +for prot in joint_protocols: + plot_str += ", \\\n " + "'" + data_metric_filename + "'" + " using " + str(n) + " lc rgb " + colors[n] + " title \"" + m_metric_name[metric] + " for " + m_prot_name[prot] + "\"" + n += 1 + +ylabel_str = "%(m)s" % dict(m = m_metric_name[metric]) +content = template % dict(svg_name = os.path.join(graph_dir, 'single_metric'), xtics_str = xtics_str, plot_str = plot_str, ylabel_str = ylabel_str, app_labels = app_labels, prot_labels = prot_labels) + +create_file(gp_metric_filename, content) + +# Creating the data file +content = "#" + metric +content += "\n" +for app in apps: + if app != apps[0]: + for prot in joint_protocols: + for p in joint_protocols: + content += "%-15f " % 0.0 + content += "\n" + for i in nb_procs: + for prot in joint_protocols: + for p in joint_protocols: + if p != prot: + content += "%-15f " % 0 + else: + content += "%-15f " % (float(metrics_val[prot][app][i][metric])) + content += "\n" + if i != nb_procs[-1]: + for p in joint_protocols: + content += "%-15f " % 0.0 + content += "\n" + +create_file(data_metric_filename, content) +# Calling gnuplot +print "gnuplot", gp_metric_filename +subprocess.call([ 'gnuplot', gp_metric_filename ]) + + + + Index: /trunk/platforms/tsar_generic_xbar/scripts/run_simus.py =================================================================== --- /trunk/platforms/tsar_generic_xbar/scripts/run_simus.py (revision 835) +++ /trunk/platforms/tsar_generic_xbar/scripts/run_simus.py (revision 836) @@ -12,8 +12,8 @@ # User parameters nb_procs = [ 4 ] -#nb_procs = [ 16, 32, 64, 128, 256 ] +#nb_procs = [ 1, 4, 8, 16, 32, 64, 128, 256 ] rerun_stats = False use_omp = False -protocol = 'dhccp' +protocol = 'wtidl' #apps = [ 'histogram', 'mandel', 'filter', 'radix_ga', 'fft_ga', 'kmeans' ] @@ -32,5 +32,5 @@ # to come: 'barnes', 'fmm', 'ocean', 'raytrace', 'radiosity', 'waters', 'watern' -all_protocols = [ 'dhccp', 'rwt', 'hmesi' ] +all_protocols = [ 'dhccp', 'rwt', 'hmesi', 'wtidl' ] top_path = os.path.join(os.path.dirname(os.path.realpath(__file__)), "..") @@ -66,5 +66,10 @@ - apps_dir: path to almos-tsar-mipsel/apps directory - almos_src_dir: path to almos source directory (for kernel and bootloader binaries) - - hdd_img_name: path to the hdd image to use + - hdd_img_name: path to the hdd image to use (will be copied but not modified) + - tsar_dir: path to tsar repository +Optional definitions (necessary if you want to use alternative protocols): + - rwt_dir: path to the RWT repository + - hmesi_dir: path to HMESI directory + - wtidl_dir: path to the ideal write-through protocol directory *** Stopping execution ''' @@ -98,4 +103,12 @@ if not os.path.exists(hmesi_dir): print "*** Error: variable hmesi_dir does not define a valid path" + sys.exit() + +if protocol == "wtidl": + if wtidl_dir == "": + print "*** Error: variable wtidl_dir not defined in config file" + sys.exit() + if not os.path.exists(wtidl_dir): + print "*** Error: variable wtidl_dir does not define a valid path" sys.exit() @@ -156,5 +169,5 @@ 'modules/vci_io_bridge', 'modules/vci_iox_network', - 'modules/vci_spi' + 'modules/vci_spi', 'platforms/tsar_generic_xbar/tsar_xbar_cluster' ] @@ -164,5 +177,5 @@ 'lib/generic_cache_tsar', 'modules/vci_cc_vcache_wrapper', - 'modules/vci_mem_cache' + 'modules/vci_mem_cache', ] @@ -179,4 +192,6 @@ elif protocol == "hmesi": arch_dir = hmesi_dir + elif protocol == "wtidl": + arch_dir = wtidl_dir else: assert(False) @@ -213,11 +228,16 @@ #define IOMMU_ACTIVE 0 -#define IRQ_PER_PROCESSOR 1 - -#endif //_HD_CONFIG_H +#define IRQ_PER_PROCESSOR 1 ''' % dict(x = x, y = y, nb_clus = x * y) + + if protocol == 'wtidl': + header += '#define WT_IDL\n' + + header += '#endif //_HD_CONFIG_H\n' + file = open(hard_config, 'w') file.write(header) file.close() + Index: /trunk/platforms/tsar_generic_xbar/soclib.conf =================================================================== --- /trunk/platforms/tsar_generic_xbar/soclib.conf (revision 835) +++ /trunk/platforms/tsar_generic_xbar/soclib.conf (revision 836) @@ -1,4 +1,8 @@ # DescPath modified by a script + + + +config.default = config.mysystemcass config.addDescPath("/users/cao/meunier/src/tsar/lib/generic_llsc_global_table") @@ -9,8 +13,8 @@ config.addDescPath("/users/cao/meunier/src/tsar/modules/vci_io_bridge") config.addDescPath("/users/cao/meunier/src/tsar/modules/vci_iox_network") -config.addDescPath("/users/cao/meunier/src/tsar/modules/vci_spiplatforms/tsar_generic_xbar/tsar_xbar_cluster") -config.addDescPath("/users/cao/meunier/src/rwt/communication") -config.addDescPath("/users/cao/meunier/src/rwt/lib/generic_cache_tsar") -config.addDescPath("/users/cao/meunier/src/rwt/modules/vci_cc_vcache_wrapper") -config.addDescPath("/users/cao/meunier/src/rwt/modules/vci_mem_cache") - +config.addDescPath("/users/cao/meunier/src/tsar/modules/vci_spi") +config.addDescPath("/users/cao/meunier/src/tsar/platforms/tsar_generic_xbar/tsar_xbar_cluster") +config.addDescPath("/users/cao/meunier/src/wt_ideal/communication") +config.addDescPath("/users/cao/meunier/src/wt_ideal/lib/generic_cache_tsar") +config.addDescPath("/users/cao/meunier/src/wt_ideal/modules/vci_cc_vcache_wrapper") +config.addDescPath("/users/cao/meunier/src/wt_ideal/modules/vci_mem_cache") Index: /trunk/platforms/tsar_generic_xbar/top.cpp =================================================================== --- /trunk/platforms/tsar_generic_xbar/top.cpp (revision 835) +++ /trunk/platforms/tsar_generic_xbar/top.cpp (revision 836) @@ -397,5 +397,5 @@ #else size_t x = debug_memc_id >> Y_WIDTH; - size_t y = debug_memc_id & ((1<> Y_WIDTH; - size_t y = cluster_xy & ((1<> Y_WIDTH; + size_t y = cluster_xy & ((1 << Y_WIDTH) - 1); assert( (x <= X_SIZE) and (y <= Y_SIZE) && @@ -635,5 +635,5 @@ sc_uint offset; offset = (sc_uint)cluster(x,y) - << (vci_address_width-x_width-y_width); + << (vci_address_width - x_width - y_width); std::ostringstream sh; @@ -699,5 +699,5 @@ dspin_rsp_width, vci_param_int, - vci_param_ext>* clusters[X_SIZE][Y_SIZE]; + vci_param_ext> * clusters[X_SIZE][Y_SIZE]; #if USE_OPENMP @@ -769,6 +769,6 @@ frozen_cycles, debug_from, - debug_ok and (cluster(x,y) == debug_memc_id), - debug_ok and (cluster(x,y) == debug_proc_id) + debug_ok, + debug_ok ); @@ -880,4 +880,26 @@ +#ifdef WT_IDL + std::list > * > l1_caches; + + for (size_t x = 0; x < X_SIZE; x++) { + for (size_t y = 0; y < Y_SIZE; y++) { + for (int proc = 0; proc < NB_PROCS_MAX; proc++) { + l1_caches.push_back(clusters[x][y]->proc[proc]); + } + } + } + + for (size_t x = 0; x < X_SIZE; x++) { + for (size_t y = 0; y < Y_SIZE; y++) { + clusters[x][y]->memc->set_vcache_list(l1_caches); + } + } +#endif + + //#define SC_TRACE #ifdef SC_TRACE @@ -943,10 +965,10 @@ signal_dspin_false_cmd_out[x][y][a][k].read = true; } - for (size_t k = 0; k < 2; k++){ - signal_dspin_false_rsp_in [x][y][a][k].write = false; - signal_dspin_false_rsp_in [x][y][a][k].read = true; - signal_dspin_false_rsp_out[x][y][a][k].write = false; - signal_dspin_false_rsp_out[x][y][a][k].read = true; - } + for (size_t k = 0; k < 2; k++){ + signal_dspin_false_rsp_in [x][y][a][k].write = false; + signal_dspin_false_rsp_in [x][y][a][k].read = true; + signal_dspin_false_rsp_out[x][y][a][k].write = false; + signal_dspin_false_rsp_out[x][y][a][k].read = true; + } } } @@ -968,8 +990,4 @@ for (int64_t n = 1; n < ncycles && !stop_called; n++) { - // Monitor a specific address for L1 & L2 caches - //clusters[0][0]->proc[0]->cache_monitor(0x800002c000ULL); - //clusters[1][0]->memc->copies_monitor(0x800002C000ULL); - if ((n % max_cycles) == 0) { @@ -1012,62 +1030,41 @@ { std::cout << "****************** cycle " << std::dec << n ; - std::cout << " ************************************************" << std::endl; - - // trace proc[debug_proc_id] - size_t l = debug_proc_id % NB_PROCS_MAX ; - size_t y = (debug_proc_id / NB_PROCS_MAX) % Y_SIZE ; - size_t x = debug_proc_id / (Y_SIZE * NB_PROCS_MAX) ; - - std::ostringstream proc_signame; - proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << l ; - std::ostringstream p2m_signame; - p2m_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " P2M" ; - std::ostringstream m2p_signame; - m2p_signame << "[SIG]PROC_" << x << "_" << y << "_" << l << " M2P" ; - - //clusters[x][y]->signal_vci_ini_proc[l].print_trace(proc_signame.str()); - //clusters[x][y]->signal_dspin_p2m_proc[l].print_trace(p2m_signame.str()); - //clusters[x][y]->signal_dspin_m2p_proc[l].print_trace(m2p_signame.str()); - - //clusters[x][y]->signal_dspin_cmd_l2g_d.print_trace("[SIG]L2G CMD"); - //clusters[x][y]->signal_dspin_cmd_g2l_d.print_trace("[SIG]G2L CMD"); - //clusters[x][y]->signal_dspin_rsp_l2g_d.print_trace("[SIG]L2G RSP"); - //clusters[x][y]->signal_dspin_rsp_g2l_d.print_trace("[SIG]G2L RSP"); - - // trace memc[debug_memc_id] - x = debug_memc_id / Y_SIZE; - y = debug_memc_id % Y_SIZE; - - std::ostringstream smemc; - smemc << "[SIG]MEMC_" << x << "_" << y; - std::ostringstream sxram; - sxram << "[SIG]XRAM_" << x << "_" << y; - std::ostringstream sm2p; - sm2p << "[SIG]MEMC_" << x << "_" << y << " M2P" ; - std::ostringstream sp2m; - sp2m << "[SIG]MEMC_" << x << "_" << y << " P2M" ; - - //clusters[x][y]->memc->print_trace(); - //clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str()); - //clusters[x][y]->signal_vci_xram.print_trace(sxram.str()); - //clusters[x][y]->signal_dspin_p2m_memc.print_trace(sp2m.str()); - //clusters[x][y]->signal_dspin_m2p_memc.print_trace(sm2p.str()); - - // trace replicated peripherals - //clusters[1][1]->mdma->print_trace(); - //clusters[1][1]->signal_vci_tgt_mdma.print_trace("[SIG]MDMA_TGT_1_1"); - //clusters[1][1]->signal_vci_ini_mdma.print_trace("[SIG]MDMA_INI_1_1"); - - - // trace external peripherals - //size_t io_x = cluster_io_id / Y_SIZE; - //size_t io_y = cluster_io_id % Y_SIZE; - - //clusters[io_x][io_y]->brom->print_trace(); - //clusters[io_x][io_y]->signal_vci_tgt_brom.print_trace("[SIG]BROM"); - - //clusters[io_x][io_y]->bdev->print_trace(); - //clusters[io_x][io_y]->signal_vci_tgt_bdev.print_trace("[SIG]BDEV_TGT"); - //clusters[io_x][io_y]->signal_vci_ini_bdev.print_trace("[SIG]BDEV_INI"); + std::cout << "************************************************" << std::endl; + + for (size_t x = 0; x < X_SIZE ; x++){ + for (size_t y = 0; y < Y_SIZE ; y++){ + for (int proc = 0; proc < NB_PROCS_MAX; proc++) { + + clusters[x][y]->proc[proc]->print_trace(); + + std::ostringstream proc_signame; + proc_signame << "[SIG]PROC_" << x << "_" << y << "_" << proc ; + std::ostringstream p2m_signame; + p2m_signame << "[SIG]PROC_" << x << "_" << y << "_" << proc << " P2M"; + std::ostringstream m2p_signame; + m2p_signame << "[SIG]PROC_" << x << "_" << y << "_" << proc << " M2P"; + + clusters[x][y]->signal_vci_ini_proc[proc].print_trace(proc_signame.str()); + clusters[x][y]->signal_dspin_p2m_proc[proc].print_trace(p2m_signame.str()); + clusters[x][y]->signal_dspin_m2p_proc[proc].print_trace(m2p_signame.str()); + } + + clusters[x][y]->memc->print_trace(); + + std::ostringstream smemc; + smemc << "[SIG]MEMC_" << x << "_" << y; + std::ostringstream sxram; + sxram << "[SIG]XRAM_" << x << "_" << y; + std::ostringstream sm2p; + sm2p << "[SIG]MEMC_" << x << "_" << y << " M2P"; + std::ostringstream sp2m; + sp2m << "[SIG]MEMC_" << x << "_" << y << " P2M"; + + clusters[x][y]->signal_vci_tgt_memc.print_trace(smemc.str()); + clusters[x][y]->signal_vci_xram.print_trace(sxram.str()); + clusters[x][y]->signal_dspin_p2m_memc.print_trace(sp2m.str()); + clusters[x][y]->signal_dspin_m2p_memc.print_trace(sm2p.str()); + } + } } Index: /trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd =================================================================== --- /trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd (revision 835) +++ /trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd (revision 836) @@ -32,6 +32,6 @@ memc_cell_size_int = parameter.Reference('vci_data_width_int'), memc_cell_size_ext = parameter.Reference('vci_data_width_ext'), - dspin_in_width = parameter.Reference('dspin_rsp_width'), - dspin_out_width = parameter.Reference('dspin_cmd_width')), + memc_dspin_in_width = parameter.Reference('dspin_rsp_width'), + memc_dspin_out_width = parameter.Reference('dspin_cmd_width')), Uses('caba:vci_simple_rom', Index: /trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp =================================================================== --- /trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp (revision 835) +++ /trunk/platforms/tsar_generic_xbar/tsar_xbar_cluster/caba/source/src/tsar_xbar_cluster.cpp (revision 836) @@ -142,5 +142,4 @@ IntTab(cluster_id), // SRCID external space IntTab(cluster_id, tgtid_memc), // TGTID direct space - //(cluster_id << l_width) + nb_procs, // CC_GLOBAL_ID x_width, // Number of x bits in platform y_width, // Number of y bits in platform @@ -215,5 +214,5 @@ wt_xbar_d = new VciDspinTargetWrapper( swtxbar.str().c_str(), - x_width + y_width + l_width ); + x_width + y_width + l_width); std::ostringstream swixbar; Index: /trunk/platforms/tsar_mono_mmu/top.desc =================================================================== --- /trunk/platforms/tsar_mono_mmu/top.desc (revision 835) +++ /trunk/platforms/tsar_mono_mmu/top.desc (revision 836) @@ -22,6 +22,6 @@ memc_cell_size_int = cell_size, memc_cell_size_ext = 8, - dspin_out_width = dspin_cmd_flit_size, - dspin_in_width = dspin_rsp_flit_size, + memc_dspin_out_width = dspin_cmd_flit_size, + memc_dspin_in_width = dspin_rsp_flit_size, ), Uses('caba:dspin_local_crossbar', Index: /trunk/softs/tests_cc_vcache/common/common.sh =================================================================== --- /trunk/softs/tests_cc_vcache/common/common.sh (revision 835) +++ /trunk/softs/tests_cc_vcache/common/common.sh (revision 836) @@ -1,3 +1,3 @@ -SIMUL=../../../platforms/tsar_mono_mmu/simul.x +SIMUL="../../../platforms/tsar_mono_mmu/simul.x" #SIMUL=../../../../soclib-svn-june-2009/soclib/soclib/platform/topcells/caba_vgsb_almo_mmu/simul.x Index: /trunk/softs/tests_cc_vcache/run_tests =================================================================== --- /trunk/softs/tests_cc_vcache/run_tests (revision 835) +++ /trunk/softs/tests_cc_vcache/run_tests (revision 836) @@ -1,6 +1,4 @@ #!/bin/sh -PATH=${PATH}:/dsk/l1/misc/bouyer/tmp/tsarmips/obj/netbsd-5/tooldir/bin -export PATH SOCLIB_TTY=TERM export SOCLIB_TTY