Changeset 836 for trunk/modules/vci_cc_vcache_wrapper/caba

Timestamp:

Oct 15, 2014, 11:41:49 AM (10 years ago)

Author:

meunier

Message:

Trunk:

• Cosmetic in mem_cache_directory.h and xram_transaction.h
• Renamed mem_cache param dspin_in_width and dspin_out_width to memc_dspin_in_width and memc_dspin_out_width (because of a bug in soclib-cc ?). Should have updated these names in the .sd or .py files of all platforms
• Updated the scripts for tsar_generic_xbar to take into account the ideal write-through + added a graph in create_graphs.py

File:

• trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp (modified) (8 diffs)

trunk/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp

@@ -1387 +1387 @@
             int state;
             paddr_t tag;
-            size_t way = r_icache_flush_count.read()/m_icache_sets;
-            size_t set = r_icache_flush_count.read()%m_icache_sets;
+            size_t way = r_icache_flush_count.read() / m_icache_sets;
+            size_t set = r_icache_flush_count.read() % m_icache_sets;
 
 #ifdef INSTRUMENTATION
@@ -2438 +2438 @@
             if (m_dreq.type == iss_t::XTN_READ)
             {
-                int xtn_opcode = (int)m_dreq.addr / 4;
+                int xtn_opcode = (int) m_dreq.addr / 4;
 
                 // checking processor mode:
@@ -2972 +2972 @@
 
         // itlb miss request
-        else if (r_icache_tlb_miss_req.read() and not wbuf_write_miss )
+        else if (r_icache_tlb_miss_req.read() and not wbuf_write_miss)
         {
             r_dcache_tlb_ins    = true;
@@ -3111 +3111 @@
 
             }
-            else if (entry & PTE_T_MASK ) //  PTD : me must access PT2
+            else if (entry & PTE_T_MASK) //  PTD : me must access PT2
             {
                 // mark the cache line ac containing a PTD
@@ -3847 +3847 @@
             int     state;
             paddr_t tag;
-            size_t  way = r_dcache_flush_count.read()/m_dcache_sets;
-            size_t  set = r_dcache_flush_count.read()%m_dcache_sets;
+            size_t  way = r_dcache_flush_count.read() / m_dcache_sets;
+            size_t  set = r_dcache_flush_count.read() % m_dcache_sets;
 
 #ifdef INSTRUMENTATION
@@ -4460 +4460 @@
                 r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
             }
-            if      (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
-            else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
-            else                                           r_dcache_fsm = DCACHE_IDLE;
+            if      (r_dcache_miss_type.read() == PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
+            else if (r_dcache_miss_type.read() == PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
+            else                                             r_dcache_fsm = DCACHE_IDLE;
         }
         break;
@@ -4760 +4760 @@
         }
 
-        assert ( not r_dcache_cc_send_req.read() and
-        "CC_SEND must be available in DCACHE_CC_CHECK" );
+        assert(not r_dcache_cc_send_req.read() and 
+        "CC_SEND must be available in DCACHE_CC_CHECK");
 
         // Match between MISS address and CC address
@@ -6021 +6021 @@
         p_vci.trdid   = 0;
         p_vci.pktid   = TYPE_READ_INS_MISS;
-        p_vci.plen    = m_icache_words<<2;
+        p_vci.plen    = m_icache_words << 2;
         p_vci.cmd     = vci_param::CMD_READ;
         p_vci.eop     = true;