Ignore:
Timestamp:
Oct 15, 2014, 11:41:49 AM (9 years ago)
Author:
meunier
Message:

Trunk:

  • Cosmetic in mem_cache_directory.h and xram_transaction.h
  • Renamed mem_cache param dspin_in_width and dspin_out_width to memc_dspin_in_width and memc_dspin_out_width (because of a bug in soclib-cc ?). Should have updated these names in the .sd or .py files of all platforms
  • Updated the scripts for tsar_generic_xbar to take into account the ideal write-through + added a graph in create_graphs.py
File:
1 edited

Legend:

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  • trunk/modules/vci_mem_cache/caba/metadata/vci_mem_cache.sd

    r468 r836  
    1515                cell_size = parameter.Reference('memc_cell_size_ext')
    1616            ),
    17             parameter.Int('dspin_in_width'),
    18             parameter.Int('dspin_out_width'),
     17            parameter.Int('memc_dspin_in_width'),
     18            parameter.Int('memc_dspin_out_width'),
    1919        ],
    2020
     
    5050            Port('caba:dspin_input',
    5151                'p_dspin_p2m',
    52                 dspin_data_size = parameter.Reference('dspin_in_width')
     52                dspin_data_size = parameter.Reference('memc_dspin_in_width')
    5353            ),
    5454            Port('caba:dspin_output',
    5555                'p_dspin_m2p',
    56                 dspin_data_size = parameter.Reference('dspin_out_width')
     56                dspin_data_size = parameter.Reference('memc_dspin_out_width')
    5757            ),
    5858            Port('caba:dspin_output',
    5959                'p_dspin_clack',
    60                 dspin_data_size = parameter.Reference('dspin_out_width')
     60                dspin_data_size = parameter.Reference('memc_dspin_out_width')
    6161            ),
    6262        ],
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