Changeset 836 for trunk/platforms/almos-tsar-mipsel/tsar_xbar_cluster

Timestamp:

Oct 15, 2014, 11:41:49 AM (10 years ago)

Author:

meunier

Message:

Trunk:

• Cosmetic in mem_cache_directory.h and xram_transaction.h
• Renamed mem_cache param dspin_in_width and dspin_out_width to memc_dspin_in_width and memc_dspin_out_width (because of a bug in soclib-cc ?). Should have updated these names in the .sd or .py files of all platforms
• Updated the scripts for tsar_generic_xbar to take into account the ideal write-through + added a graph in create_graphs.py

File:

• trunk/platforms/almos-tsar-mipsel/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd (modified) (1 diff)

trunk/platforms/almos-tsar-mipsel/tsar_xbar_cluster/caba/metadata/tsar_xbar_cluster.sd

@@ -34 +34 @@
               memc_cell_size_int = parameter.Reference('vci_data_width_int'),
               memc_cell_size_ext = parameter.Reference('vci_data_width_ext'),
-              dspin_in_width  = parameter.Reference('dspin_rsp_width'),
-              dspin_out_width = parameter.Reference('dspin_cmd_width')),
+              memc_dspin_in_width  = parameter.Reference('dspin_rsp_width'),
+              memc_dspin_out_width = parameter.Reference('dspin_cmd_width')),
 
       Uses('caba:vci_simple_rom',