Ignore:
Timestamp:
Oct 15, 2014, 11:41:49 AM (12 years ago)
Author:
meunier
Message:

Trunk:

  • Cosmetic in mem_cache_directory.h and xram_transaction.h
  • Renamed mem_cache param dspin_in_width and dspin_out_width to memc_dspin_in_width and memc_dspin_out_width (because of a bug in soclib-cc ?). Should have updated these names in the .sd or .py files of all platforms
  • Updated the scripts for tsar_generic_xbar to take into account the ideal write-through + added a graph in create_graphs.py
File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/softs/tests_cc_vcache/common/common.sh

    r520 r836  
    1 SIMUL=../../../platforms/tsar_mono_mmu/simul.x
     1SIMUL="../../../platforms/tsar_mono_mmu/simul.x"
    22
    33#SIMUL=../../../../soclib-svn-june-2009/soclib/soclib/platform/topcells/caba_vgsb_almo_mmu/simul.x
Note: See TracChangeset for help on using the changeset viewer.