Changeset 840 for branches/reconfiguration
- Timestamp:
- Oct 15, 2014, 3:30:33 PM (10 years ago)
- Location:
- branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba
- Files:
-
- 3 edited
-
metadata/vci_cc_vcache_wrapper.sd (modified) (1 diff)
-
source/include/vci_cc_vcache_wrapper.h (modified) (34 diffs)
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source/src/vci_cc_vcache_wrapper.cpp (modified) (8 diffs)
Legend:
- Unmodified
- Added
- Removed
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branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/metadata/vci_cc_vcache_wrapper.sd
r839 r840 2 2 # -*- python -*- 3 3 4 Module('caba: vci_cc_vcache_wrapper',5 4 Module('caba:reconf:vci_cc_vcache_wrapper', 5 classname = 'soclib::caba::VciCcVCacheWrapper', 6 6 7 7 tmpl_parameters = [ 8 8 parameter.Module('vci_param', default = 'caba:vci_param'), 9 9 parameter.Int('dspin_in_width'), 10 10 parameter.Int('dspin_out_width'), 11 11 parameter.Module('iss_t') 12 12 ], 13 13 14 14 header_files = [ '../source/include/vci_cc_vcache_wrapper.h' ], 15 15 16 16 implementation_files = [ '../source/src/vci_cc_vcache_wrapper.cpp' ], 17 17 18 18 uses = [ 19 19 Uses('caba:base_module'), 20 20 Uses('common:mapping_table'), 21 22 23 24 25 addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', 21 Uses('common:iss2'), 22 Uses('caba:multi_write_buffer'), 23 Uses('caba:generic_fifo'), 24 Uses('caba:generic_cache_tsar', 25 addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', 26 26 parameter.Reference('addr_size'))), 27 Uses('caba:generic_tlb', 28 addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', 27 Uses('caba:generic_tlb', 28 addr_t = parameter.StringExt('sc_dt::sc_uint<%d> ', 29 29 parameter.Reference('addr_size'))), 30 Uses('common:address_masking_table', 31 data_t = parameter.StringExt('sc_dt::sc_uint<%d> ', 30 Uses('common:address_masking_table', 31 data_t = parameter.StringExt('sc_dt::sc_uint<%d> ', 32 32 parameter.Reference('addr_size')) 33 33 ), 34 34 Uses('caba:dspin_dhccp_param'), 35 35 ], 36 36 37 37 ports = [ 38 38 Port('caba:vci_initiator', 'p_vci'), 39 Port('caba:dspin_input', 'p_dspin_m2p', 39 Port('caba:dspin_input', 'p_dspin_m2p', 40 40 dspin_data_size = parameter.Reference('dspin_in_width')), 41 Port('caba:dspin_output', 'p_dspin_p2m', 41 Port('caba:dspin_output', 'p_dspin_p2m', 42 42 dspin_data_size = parameter.Reference('dspin_out_width')), 43 Port('caba:dspin_input', 'p_dspin_clack', 43 Port('caba:dspin_input', 'p_dspin_clack', 44 44 dspin_data_size = parameter.Reference('dspin_in_width')), 45 46 47 45 Port('caba:bit_in','p_irq', parameter.Constant('n_irq')), 46 Port('caba:bit_in', 'p_resetn', auto = 'resetn'), 47 Port('caba:clock_in', 'p_clk', auto = 'clock') 48 48 ], 49 49 50 50 instance_parameters = [ 51 51 parameter.Int('proc_id'), 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 52 parameter.Module('mt', 'common:mapping_table'), 53 parameter.Module('mc', 'common:mapping_table'), 54 parameter.IntTab('initiator_rw_index'), 55 parameter.IntTab('initiator_c_index'), 56 parameter.IntTab('target_index'), 57 parameter.Int('itlb_ways'), 58 parameter.Int('itlb_sets'), 59 parameter.Int('dtlb_ways'), 60 parameter.Int('dtlb_sets'), 61 parameter.Int('icache_ways'), 62 parameter.Int('icache_sets'), 63 parameter.Int('icache_words'), 64 parameter.Int('dcache_ways'), 65 parameter.Int('dcache_sets'), 66 parameter.Int('dcache_words'), 67 parameter.Int('wbuf_nlines'), 68 parameter.Int('wbuf_nwords'), 69 parameter.Int('max_frozen_cycles') 70 70 ], 71 71 ) 72 72 73 -
branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
r839 r840 55 55 56 56 //////////////////////////////////////////// 57 template<typename vci_param, 57 template<typename vci_param, 58 58 size_t dspin_in_width, 59 59 size_t dspin_out_width, … … 66 66 typedef typename vci_param::fast_addr_t paddr_t; 67 67 68 enum icache_fsm_state_e 68 enum icache_fsm_state_e 69 69 { 70 70 ICACHE_IDLE, … … 93 93 }; 94 94 95 enum dcache_fsm_state_e 95 enum dcache_fsm_state_e 96 96 { 97 97 DCACHE_IDLE, … … 107 107 DCACHE_TLB_LR_WAIT, 108 108 DCACHE_TLB_RETURN, 109 109 // handling processor XTN requests 110 110 DCACHE_XTN_SWITCH, 111 111 DCACHE_XTN_SYNC, … … 125 125 DCACHE_DIRTY_GET_PTE, 126 126 DCACHE_DIRTY_WAIT, 127 127 // handling processor miss requests 128 128 DCACHE_MISS_SELECT, 129 129 DCACHE_MISS_CLEAN, … … 143 143 }; 144 144 145 enum cmd_fsm_state_e 145 enum cmd_fsm_state_e 146 146 { 147 147 CMD_IDLE, … … 157 157 }; 158 158 159 enum rsp_fsm_state_e 159 enum rsp_fsm_state_e 160 160 { 161 161 RSP_IDLE, … … 168 168 }; 169 169 170 enum cc_receive_fsm_state_e 170 enum cc_receive_fsm_state_e 171 171 { 172 172 CC_RECEIVE_IDLE, … … 185 185 }; 186 186 187 enum cc_send_fsm_state_e 187 enum cc_send_fsm_state_e 188 188 { 189 189 CC_SEND_IDLE, … … 204 204 // b1 accÚs table llsc type SW / other 205 205 // b2 WRITE/CAS/LL/SC 206 TYPE_DATA_UNC 207 TYPE_READ_DATA_MISS 208 TYPE_READ_INS_UNC 209 TYPE_READ_INS_MISS 210 TYPE_WRITE 211 TYPE_CAS 212 TYPE_LL 213 TYPE_SC 206 TYPE_DATA_UNC = 0x0, 207 TYPE_READ_DATA_MISS = 0x1, 208 TYPE_READ_INS_UNC = 0x2, 209 TYPE_READ_INS_MISS = 0x3, 210 TYPE_WRITE = 0x4, 211 TYPE_CAS = 0x5, 212 TYPE_LL = 0x6, 213 TYPE_SC = 0x7 214 214 }; 215 215 … … 217 217 enum sc_status_type_e 218 218 { 219 SC_SUCCESS =0x00000000,220 SC_FAIL =0x00000001219 SC_SUCCESS = 0x00000000, 220 SC_FAIL = 0x00000001 221 221 }; 222 222 223 223 // cc_send_type 224 typedef enum 224 typedef enum 225 225 { 226 226 CC_TYPE_CLEANUP, … … 229 229 230 230 // cc_receive_type 231 typedef enum 231 typedef enum 232 232 { 233 233 CC_TYPE_CLACK, … … 238 238 239 239 // TLB Mode : ITLB / DTLB / ICACHE / DCACHE 240 enum 240 enum 241 241 { 242 242 INS_TLB_MASK = 0x8, … … 250 250 { 251 251 MMU_NONE = 0x0000, // None 252 MMU_WRITE_PT1_UNMAPPED 253 MMU_WRITE_PT2_UNMAPPED 252 MMU_WRITE_PT1_UNMAPPED = 0x0001, // Write & Page fault on PT1 253 MMU_WRITE_PT2_UNMAPPED = 0x0002, // Write & Page fault on PT2 254 254 MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write & Protected access in user mode 255 255 MMU_WRITE_ACCES_VIOLATION = 0x0008, // Write to non writable page … … 258 258 MMU_WRITE_PT2_ILLEGAL_ACCESS = 0x0080, // Write & Bus Error accessing PT2 259 259 MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write & Bus Error in cache access 260 MMU_READ_PT1_UNMAPPED 261 MMU_READ_PT2_UNMAPPED 260 MMU_READ_PT1_UNMAPPED = 0x1001, // Read & Page fault on PT1 261 MMU_READ_PT2_UNMAPPED = 0x1002, // Read & Page fault on PT2 262 262 MMU_READ_PRIVILEGE_VIOLATION = 0x1004, // Read & Protected access in user mode 263 263 MMU_READ_EXEC_VIOLATION = 0x1010, // Read & Exec access to a non exec page 264 MMU_READ_UNDEFINED_XTN 264 MMU_READ_UNDEFINED_XTN = 0x1020, // Read & Undefined external access 265 265 MMU_READ_PT1_ILLEGAL_ACCESS = 0x1040, // Read & Bus Error accessing PT1 266 266 MMU_READ_PT2_ILLEGAL_ACCESS = 0x1080, // Read & Bus Error accessing PT2 … … 300 300 soclib::common::AddressDecodingTable<uint64_t, bool> m_cacheability_table; 301 301 302 const size_t 303 const size_t 304 const size_t 305 const size_t 306 const size_t 307 const size_t 308 const size_t 309 const size_t 310 const size_t 311 const paddr_t 312 const size_t 313 const size_t 314 const size_t 315 const paddr_t 316 const size_t 317 const size_t 318 const size_t 319 const size_t 320 const uint32_t 321 const size_t 322 uint32_t 323 bool 324 325 uint32_t 326 uint32_t 302 const size_t m_srcid; 303 const size_t m_cc_global_id; 304 const size_t m_nline_width; 305 const size_t m_itlb_ways; 306 const size_t m_itlb_sets; 307 const size_t m_dtlb_ways; 308 const size_t m_dtlb_sets; 309 const size_t m_icache_ways; 310 const size_t m_icache_sets; 311 const paddr_t m_icache_yzmask; 312 const size_t m_icache_words; 313 const size_t m_dcache_ways; 314 const size_t m_dcache_sets; 315 const paddr_t m_dcache_yzmask; 316 const size_t m_dcache_words; 317 const size_t m_x_width; 318 const size_t m_y_width; 319 const size_t m_proc_id; 320 const uint32_t m_max_frozen_cycles; 321 const size_t m_paddr_nbits; 322 uint32_t m_debug_start_cycle; 323 bool m_debug_ok; 324 325 uint32_t m_dcache_paddr_ext_reset; 326 uint32_t m_icache_paddr_ext_reset; 327 327 328 328 //////////////////////////////////////// … … 335 335 336 336 ///////////////////////////////////////////// 337 // debug variables 337 // debug variables 338 338 ///////////////////////////////////////////// 339 339 bool m_debug_previous_i_hit; … … 348 348 // Software visible REGISTERS 349 349 /////////////////////////////// 350 sc_signal<uint32_t> r_mmu_ptpr; 351 sc_signal<uint32_t> r_mmu_mode; 352 sc_signal<uint32_t> r_mmu_word_lo; 353 sc_signal<uint32_t> r_mmu_word_hi; 354 sc_signal<uint32_t> r_mmu_ibvar; 355 sc_signal<uint32_t> r_mmu_dbvar; 350 sc_signal<uint32_t> r_mmu_ptpr; // page table pointer register 351 sc_signal<uint32_t> r_mmu_mode; // mmu mode register 352 sc_signal<uint32_t> r_mmu_word_lo; // mmu misc data low 353 sc_signal<uint32_t> r_mmu_word_hi; // mmu misc data hight 354 sc_signal<uint32_t> r_mmu_ibvar; // mmu bad instruction address 355 sc_signal<uint32_t> r_mmu_dbvar; // mmu bad data address 356 356 sc_signal<uint32_t> r_mmu_ietr; // mmu instruction error type 357 357 sc_signal<uint32_t> r_mmu_detr; // mmu data error type 358 uint32_t r_mmu_params;// read-only359 uint32_t r_mmu_release;// read_only358 uint32_t r_mmu_params; // read-only 359 uint32_t r_mmu_release; // read_only 360 360 361 361 … … 365 365 sc_signal<int> r_icache_fsm; // state register 366 366 sc_signal<int> r_icache_fsm_save; // return state for coherence op 367 sc_signal<paddr_t> r_icache_vci_paddr; 367 sc_signal<paddr_t> r_icache_vci_paddr; // physical address 368 368 sc_signal<uint32_t> r_icache_vaddr_save; // virtual address from processor 369 369 370 370 // icache miss handling 371 sc_signal<size_t> r_icache_miss_way; 372 sc_signal<size_t> r_icache_miss_set; 373 sc_signal<size_t> r_icache_miss_word; 371 sc_signal<size_t> r_icache_miss_way; // selected way for cache update 372 sc_signal<size_t> r_icache_miss_set; // selected set for cache update 373 sc_signal<size_t> r_icache_miss_word; // word index ( cache update) 374 374 sc_signal<bool> r_icache_miss_inval; // coherence request matching a miss 375 375 sc_signal<bool> r_icache_miss_clack; // waiting for a cleanup acknowledge 376 376 377 377 // coherence request handling 378 sc_signal<size_t> r_icache_cc_way; 379 sc_signal<size_t> r_icache_cc_set; 380 sc_signal<size_t> r_icache_cc_word; 378 sc_signal<size_t> r_icache_cc_way; // selected way for cc update/inval 379 sc_signal<size_t> r_icache_cc_set; // selected set for cc update/inval 380 sc_signal<size_t> r_icache_cc_word; // word counter for cc update 381 381 sc_signal<bool> r_icache_cc_need_write; // activate the cache for writing 382 382 383 383 // coherence clack handling 384 384 sc_signal<bool> r_icache_clack_req; // clack request 385 sc_signal<size_t> r_icache_clack_way; 386 sc_signal<size_t> r_icache_clack_set; 385 sc_signal<size_t> r_icache_clack_way; // clack way 386 sc_signal<size_t> r_icache_clack_set; // clack set 387 387 388 388 // icache flush handling 389 sc_signal<size_t> r_icache_flush_count; 389 sc_signal<size_t> r_icache_flush_count; // slot counter used for cache flush 390 390 391 391 // communication between ICACHE FSM and VCI_CMD FSM … … 394 394 395 395 // communication between ICACHE FSM and DCACHE FSM 396 sc_signal<bool> 396 sc_signal<bool> r_icache_tlb_miss_req; // (set icache/reset dcache) 397 397 sc_signal<bool> r_icache_tlb_rsp_error; // tlb miss response error 398 398 399 399 // Filp-Flop in ICACHE FSM for saving the cleanup victim request 400 sc_signal<bool> r_icache_cleanup_victim_req; 400 sc_signal<bool> r_icache_cleanup_victim_req; 401 401 sc_signal<paddr_t> r_icache_cleanup_victim_nline; 402 402 … … 424 424 sc_signal<uint32_t> r_dcache_save_be; // byte enable (from proc) 425 425 sc_signal<paddr_t> r_dcache_save_paddr; // physical address 426 sc_signal<size_t> r_dcache_save_cache_way; 427 sc_signal<size_t> r_dcache_save_cache_set; 428 sc_signal<size_t> r_dcache_save_cache_word; 426 sc_signal<size_t> r_dcache_save_cache_way; // selected way (from dcache) 427 sc_signal<size_t> r_dcache_save_cache_set; // selected set (from dcache) 428 sc_signal<size_t> r_dcache_save_cache_word; // selected word (from dcache) 429 429 // registers used by the Dirty bit sub-fsm 430 430 sc_signal<paddr_t> r_dcache_dirty_paddr; // PTE physical address 431 sc_signal<size_t> r_dcache_dirty_way; 432 sc_signal<size_t> r_dcache_dirty_set; 431 sc_signal<size_t> r_dcache_dirty_way; // way to invalidate in dcache 432 sc_signal<size_t> r_dcache_dirty_set; // set to invalidate in dcache 433 433 434 434 // communication between DCACHE FSM and VCI_CMD FSM 435 sc_signal<paddr_t> r_dcache_vci_paddr; 436 sc_signal<uint32_t> r_dcache_vci_wdata; 435 sc_signal<paddr_t> r_dcache_vci_paddr; // physical address for VCI command 436 sc_signal<uint32_t> r_dcache_vci_wdata; // write unc data for VCI command 437 437 sc_signal<bool> r_dcache_vci_miss_req; // read miss request 438 438 sc_signal<bool> r_dcache_vci_unc_req; // uncacheable request (read/write) … … 447 447 448 448 // register used for XTN inval 449 sc_signal<size_t> r_dcache_xtn_way; 450 sc_signal<size_t> r_dcache_xtn_set; 449 sc_signal<size_t> r_dcache_xtn_way; // selected way (from dcache) 450 sc_signal<size_t> r_dcache_xtn_set; // selected set (from dcache) 451 451 452 452 // handling dcache miss 453 sc_signal<int> r_dcache_miss_type;// depending on the requester454 sc_signal<size_t> r_dcache_miss_word; 455 sc_signal<size_t> r_dcache_miss_way; 456 sc_signal<size_t> r_dcache_miss_set; 453 sc_signal<int> r_dcache_miss_type; // depending on the requester 454 sc_signal<size_t> r_dcache_miss_word; // word index for cache update 455 sc_signal<size_t> r_dcache_miss_way; // selected way for cache update 456 sc_signal<size_t> r_dcache_miss_set; // selected set for cache update 457 457 sc_signal<bool> r_dcache_miss_inval; // coherence request matching a miss 458 458 sc_signal<bool> r_dcache_miss_clack; // waiting for a cleanup acknowledge 459 459 460 460 // handling coherence requests 461 sc_signal<size_t> r_dcache_cc_way; 462 sc_signal<size_t> r_dcache_cc_set; 463 sc_signal<size_t> r_dcache_cc_word; 461 sc_signal<size_t> r_dcache_cc_way; // selected way for cc update/inval 462 sc_signal<size_t> r_dcache_cc_set; // selected set for cc update/inval 463 sc_signal<size_t> r_dcache_cc_word; // word counter for cc update 464 464 sc_signal<bool> r_dcache_cc_need_write; // activate the cache for writing 465 465 466 466 // coherence clack handling 467 467 sc_signal<bool> r_dcache_clack_req; // clack request 468 sc_signal<size_t> r_dcache_clack_way; 469 sc_signal<size_t> r_dcache_clack_set; 468 sc_signal<size_t> r_dcache_clack_way; // clack way 469 sc_signal<size_t> r_dcache_clack_set; // clack set 470 470 471 471 // dcache flush handling 472 sc_signal<size_t> r_dcache_flush_count; 472 sc_signal<size_t> r_dcache_flush_count; // slot counter used for cache flush 473 473 474 474 // ll response handling 475 sc_signal<size_t> r_dcache_ll_rsp_count; 475 sc_signal<size_t> r_dcache_ll_rsp_count; // flit counter used for ll rsp 476 476 477 477 // used by the TLB miss sub-fsm 478 sc_signal<uint32_t> r_dcache_tlb_vaddr; 479 sc_signal<bool> r_dcache_tlb_ins; 480 sc_signal<paddr_t> r_dcache_tlb_paddr; 481 sc_signal<uint32_t> r_dcache_tlb_pte_flags; 482 sc_signal<uint32_t> r_dcache_tlb_pte_ppn; 483 sc_signal<size_t> r_dcache_tlb_cache_way; 484 sc_signal<size_t> r_dcache_tlb_cache_set; 485 sc_signal<size_t> r_dcache_tlb_cache_word; 486 sc_signal<size_t> r_dcache_tlb_way; 487 sc_signal<size_t> r_dcache_tlb_set; 478 sc_signal<uint32_t> r_dcache_tlb_vaddr; // virtual address for a tlb miss 479 sc_signal<bool> r_dcache_tlb_ins; // target tlb (itlb if true) 480 sc_signal<paddr_t> r_dcache_tlb_paddr; // physical address of pte 481 sc_signal<uint32_t> r_dcache_tlb_pte_flags; // pte1 or first word of pte2 482 sc_signal<uint32_t> r_dcache_tlb_pte_ppn; // second word of pte2 483 sc_signal<size_t> r_dcache_tlb_cache_way; // selected way in dcache 484 sc_signal<size_t> r_dcache_tlb_cache_set; // selected set in dcache 485 sc_signal<size_t> r_dcache_tlb_cache_word; // selected word in dcache 486 sc_signal<size_t> r_dcache_tlb_way; // selected way in tlb 487 sc_signal<size_t> r_dcache_tlb_set; // selected set in tlb 488 488 489 489 // ITLB and DTLB invalidation 490 sc_signal<paddr_t> r_dcache_tlb_inval_line; 490 sc_signal<paddr_t> r_dcache_tlb_inval_line; // line index 491 491 sc_signal<size_t> r_dcache_tlb_inval_set; // tlb set counter 492 492 … … 496 496 497 497 // Filp-Flop in DCACHE FSM for saving the cleanup victim request 498 sc_signal<bool> r_dcache_cleanup_victim_req; 498 sc_signal<bool> r_dcache_cleanup_victim_req; 499 499 sc_signal<paddr_t> r_dcache_cleanup_victim_nline; 500 500 … … 517 517 /////////////////////////////////// 518 518 sc_signal<int> r_vci_cmd_fsm; 519 sc_signal<size_t> r_vci_cmd_min; 520 sc_signal<size_t> r_vci_cmd_max; 521 sc_signal<size_t> r_vci_cmd_cpt; 522 sc_signal<bool> r_vci_cmd_imiss_prio; 519 sc_signal<size_t> r_vci_cmd_min; // used for write bursts 520 sc_signal<size_t> r_vci_cmd_max; // used for write bursts 521 sc_signal<size_t> r_vci_cmd_cpt; // used for write bursts 522 sc_signal<bool> r_vci_cmd_imiss_prio; // round-robin between imiss & dmiss 523 523 524 524 /////////////////////////////////// … … 529 529 sc_signal<bool> r_vci_rsp_ins_error; 530 530 sc_signal<bool> r_vci_rsp_data_error; 531 GenericFifo<uint32_t> r_vci_rsp_fifo_icache; 532 GenericFifo<uint32_t> r_vci_rsp_fifo_dcache; 531 GenericFifo<uint32_t> r_vci_rsp_fifo_icache; // response FIFO to ICACHE FSM 532 GenericFifo<uint32_t> r_vci_rsp_fifo_dcache; // response FIFO to DCACHE FSM 533 533 534 534 /////////////////////////////////// … … 556 556 sc_signal<size_t> r_cc_receive_icache_set; // cc_receive to icache set 557 557 sc_signal<size_t> r_cc_receive_icache_updt_tab_idx; // cc_receive update table index 558 sc_signal<paddr_t> r_cc_receive_icache_nline; 558 sc_signal<paddr_t> r_cc_receive_icache_nline; // cache line physical address 559 559 560 560 // communication between CC_RECEIVE FSM and DCACHE FSM … … 564 564 sc_signal<size_t> r_cc_receive_dcache_set; // cc_receive to dcache set 565 565 sc_signal<size_t> r_cc_receive_dcache_updt_tab_idx; // cc_receive update table index 566 sc_signal<paddr_t> r_cc_receive_dcache_nline; 566 sc_signal<paddr_t> r_cc_receive_dcache_nline; // cache line physical address 567 567 568 568 /////////////////////////////////// … … 571 571 sc_signal<bool> r_dspin_clack_req; 572 572 sc_signal<uint64_t> r_dspin_clack_flit; 573 573 574 574 ////////////////////////////////////////////////////////////////// 575 575 // processor, write buffer, caches , TLBs 576 576 ////////////////////////////////////////////////////////////////// 577 577 578 iss_t 579 MultiWriteBuffer<paddr_t> 580 GenericCache<paddr_t> 581 GenericCache<paddr_t> 582 GenericTlb<paddr_t> 583 GenericTlb<paddr_t> 578 iss_t r_iss; 579 MultiWriteBuffer<paddr_t> r_wbuf; 580 GenericCache<paddr_t> r_icache; 581 GenericCache<paddr_t> r_dcache; 582 GenericTlb<paddr_t> r_itlb; 583 GenericTlb<paddr_t> r_dtlb; 584 584 585 585 ////////////////////////////////////////////////////////////////// … … 587 587 ////////////////////////////////////////////////////////////////// 588 588 589 sc_signal<paddr_t> 590 sc_signal<uint32_t> 591 sc_signal<uint32_t> 592 sc_signal<bool> 589 sc_signal<paddr_t> r_dcache_llsc_paddr; 590 sc_signal<uint32_t> r_dcache_llsc_key; 591 sc_signal<uint32_t> r_dcache_llsc_count; 592 sc_signal<bool> r_dcache_llsc_valid; 593 593 594 594 //////////////////////////////// … … 605 605 uint32_t m_cpt_icache_dir_write; // ICACHE DIR WRITE 606 606 607 uint32_t m_cpt_frz_cycles; 608 uint32_t m_cpt_total_cycles; 607 uint32_t m_cpt_frz_cycles; // number of cycles where the cpu is frozen 608 uint32_t m_cpt_total_cycles; // total number of cycles 609 609 610 610 // Cache activity counters … … 651 651 uint32_t m_cpt_tlb_occup_dcache; 652 652 653 uint32_t m_cost_ins_tlb_miss_frz; // number of frozen cycles related to instruction tlb miss654 uint32_t m_cost_data_tlb_miss_frz; // number of frozen cycles related to data tlb miss653 uint32_t m_cost_ins_tlb_miss_frz; // number of frozen cycles related to instruction tlb miss 654 uint32_t m_cost_data_tlb_miss_frz; // number of frozen cycles related to data tlb miss 655 655 uint32_t m_cost_ins_tlb_update_acc_frz; // number of frozen cycles related to instruction tlb update acc 656 656 uint32_t m_cost_data_tlb_update_acc_frz; // number of frozen cycles related to data tlb update acc … … 668 668 uint32_t m_cpt_dtlb_sc_dirty_transaction; // number of dtlb sc dirty transactions 669 669 670 uint32_t m_cost_itlbmiss_transaction; 671 uint32_t m_cost_itlb_ll_transaction; 672 uint32_t m_cost_itlb_sc_transaction; 673 uint32_t m_cost_dtlbmiss_transaction; 674 uint32_t m_cost_dtlb_ll_transaction; 675 uint32_t m_cost_dtlb_sc_transaction; 676 uint32_t m_cost_dtlb_ll_dirty_transaction; 677 uint32_t m_cost_dtlb_sc_dirty_transaction; 670 uint32_t m_cost_itlbmiss_transaction; // cumulated duration for VCI instruction TLB miss transactions 671 uint32_t m_cost_itlb_ll_transaction; // cumulated duration for VCI instruction TLB ll acc transactions 672 uint32_t m_cost_itlb_sc_transaction; // cumulated duration for VCI instruction TLB sc acc transactions 673 uint32_t m_cost_dtlbmiss_transaction; // cumulated duration for VCI data TLB miss transactions 674 uint32_t m_cost_dtlb_ll_transaction; // cumulated duration for VCI data TLB ll acc transactions 675 uint32_t m_cost_dtlb_sc_transaction; // cumulated duration for VCI data TLB sc acc transactions 676 uint32_t m_cost_dtlb_ll_dirty_transaction; // cumulated duration for VCI data TLB ll dirty transactions 677 uint32_t m_cost_dtlb_sc_dirty_transaction; // cumulated duration for VCI data TLB sc dirty transactions 678 678 679 679 // coherence activity counters 680 uint32_t m_cpt_cc_update_icache; 681 uint32_t m_cpt_cc_update_dcache; 682 uint32_t m_cpt_cc_inval_icache; 683 uint32_t m_cpt_cc_inval_dcache; 684 uint32_t m_cpt_cc_broadcast; 685 686 uint32_t m_cost_updt_data_frz; 687 uint32_t m_cost_inval_ins_frz; 688 uint32_t m_cost_inval_data_frz; 689 uint32_t m_cost_broadcast_frz; 690 691 uint32_t m_cpt_cc_cleanup_ins; 692 uint32_t m_cpt_cc_cleanup_data; 693 694 uint32_t m_cpt_icleanup_transaction; 695 uint32_t m_cpt_dcleanup_transaction; 696 uint32_t m_cost_icleanup_transaction; 697 uint32_t m_cost_dcleanup_transaction; 680 uint32_t m_cpt_cc_update_icache; // number of coherence update instruction commands 681 uint32_t m_cpt_cc_update_dcache; // number of coherence update data commands 682 uint32_t m_cpt_cc_inval_icache; // number of coherence inval instruction commands 683 uint32_t m_cpt_cc_inval_dcache; // number of coherence inval data commands 684 uint32_t m_cpt_cc_broadcast; // number of coherence broadcast commands 685 686 uint32_t m_cost_updt_data_frz; // number of frozen cycles related to coherence update data packets 687 uint32_t m_cost_inval_ins_frz; // number of frozen cycles related to coherence inval instruction packets 688 uint32_t m_cost_inval_data_frz; // number of frozen cycles related to coherence inval data packets 689 uint32_t m_cost_broadcast_frz; // number of frozen cycles related to coherence broadcast packets 690 691 uint32_t m_cpt_cc_cleanup_ins; // number of coherence cleanup packets 692 uint32_t m_cpt_cc_cleanup_data; // number of coherence cleanup packets 693 694 uint32_t m_cpt_icleanup_transaction; // number of instruction cleanup transactions 695 uint32_t m_cpt_dcleanup_transaction; // number of instructinumber of data cleanup transactions 696 uint32_t m_cost_icleanup_transaction; // cumulated duration for VCI instruction cleanup transactions 697 uint32_t m_cost_dcleanup_transaction; // cumulated duration for VCI data cleanup transactions 698 698 699 699 uint32_t m_cost_ins_tlb_inval_frz; // number of frozen cycles related to checking ins tlb invalidate … … 711 711 uint32_t m_cpt_fsm_cc_send [64]; 712 712 713 uint32_t m_cpt_stop_simulation; 714 bool m_monitor_ok; // used to debug cache output715 uint32_t m_monitor_base; 716 uint32_t m_monitor_length; 713 uint32_t m_cpt_stop_simulation; // used to stop simulation if frozen 714 bool m_monitor_ok; // used to debug cache output 715 uint32_t m_monitor_base; 716 uint32_t m_monitor_length; 717 717 718 718 protected: … … 753 753 void start_monitor(paddr_t,paddr_t); 754 754 void stop_monitor(); 755 inline void iss_set_debug_mask(uint v) 756 { 757 755 inline void iss_set_debug_mask(uint v) 756 { 757 r_iss.set_debug_mask(v); 758 758 } 759 759 -
branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
r839 r840 1387 1387 int state; 1388 1388 paddr_t tag; 1389 size_t way = r_icache_flush_count.read() /m_icache_sets;1390 size_t set = r_icache_flush_count.read() %m_icache_sets;1389 size_t way = r_icache_flush_count.read() / m_icache_sets; 1390 size_t set = r_icache_flush_count.read() % m_icache_sets; 1391 1391 1392 1392 #ifdef INSTRUMENTATION … … 2438 2438 if (m_dreq.type == iss_t::XTN_READ) 2439 2439 { 2440 int xtn_opcode = (int) m_dreq.addr / 4;2440 int xtn_opcode = (int) m_dreq.addr / 4; 2441 2441 2442 2442 // checking processor mode: … … 2972 2972 2973 2973 // itlb miss request 2974 else if (r_icache_tlb_miss_req.read() and not wbuf_write_miss 2974 else if (r_icache_tlb_miss_req.read() and not wbuf_write_miss) 2975 2975 { 2976 2976 r_dcache_tlb_ins = true; … … 3111 3111 3112 3112 } 3113 else if (entry & PTE_T_MASK 3113 else if (entry & PTE_T_MASK) // PTD : me must access PT2 3114 3114 { 3115 3115 // mark the cache line ac containing a PTD … … 3847 3847 int state; 3848 3848 paddr_t tag; 3849 size_t way = r_dcache_flush_count.read() /m_dcache_sets;3850 size_t set = r_dcache_flush_count.read() %m_dcache_sets;3849 size_t way = r_dcache_flush_count.read() / m_dcache_sets; 3850 size_t set = r_dcache_flush_count.read() % m_dcache_sets; 3851 3851 3852 3852 #ifdef INSTRUMENTATION … … 4460 4460 r_dcache_contains_ptd[way * m_dcache_sets + set] = false; 4461 4461 } 4462 if (r_dcache_miss_type.read() ==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;4463 else if (r_dcache_miss_type.read() ==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;4464 else r_dcache_fsm = DCACHE_IDLE;4462 if (r_dcache_miss_type.read() == PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET; 4463 else if (r_dcache_miss_type.read() == PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET; 4464 else r_dcache_fsm = DCACHE_IDLE; 4465 4465 } 4466 4466 break; … … 4760 4760 } 4761 4761 4762 assert (not r_dcache_cc_send_req.read() and4763 "CC_SEND must be available in DCACHE_CC_CHECK" 4762 assert(not r_dcache_cc_send_req.read() and 4763 "CC_SEND must be available in DCACHE_CC_CHECK"); 4764 4764 4765 4765 // Match between MISS address and CC address … … 6021 6021 p_vci.trdid = 0; 6022 6022 p_vci.pktid = TYPE_READ_INS_MISS; 6023 p_vci.plen = m_icache_words <<2;6023 p_vci.plen = m_icache_words << 2; 6024 6024 p_vci.cmd = vci_param::CMD_READ; 6025 6025 p_vci.eop = true;
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