Index: branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h
===================================================================
--- branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 839)
+++ branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/include/vci_cc_vcache_wrapper.h	(revision 840)
@@ -55,5 +55,5 @@
 
 ////////////////////////////////////////////
-template<typename vci_param, 
+template<typename vci_param,
          size_t   dspin_in_width,
          size_t   dspin_out_width,
@@ -66,5 +66,5 @@
     typedef typename vci_param::fast_addr_t  paddr_t;
 
-    enum icache_fsm_state_e 
+    enum icache_fsm_state_e
     {
         ICACHE_IDLE,
@@ -93,5 +93,5 @@
     };
 
-    enum dcache_fsm_state_e 
+    enum dcache_fsm_state_e
     {
         DCACHE_IDLE,
@@ -107,5 +107,5 @@
         DCACHE_TLB_LR_WAIT,
         DCACHE_TLB_RETURN,
-	    // handling processor XTN requests
+        // handling processor XTN requests
         DCACHE_XTN_SWITCH,
         DCACHE_XTN_SYNC,
@@ -125,5 +125,5 @@
         DCACHE_DIRTY_GET_PTE,
         DCACHE_DIRTY_WAIT,
-	    // handling processor miss requests
+        // handling processor miss requests
         DCACHE_MISS_SELECT,
         DCACHE_MISS_CLEAN,
@@ -143,5 +143,5 @@
     };
 
-    enum cmd_fsm_state_e 
+    enum cmd_fsm_state_e
     {
         CMD_IDLE,
@@ -157,5 +157,5 @@
     };
 
-    enum rsp_fsm_state_e 
+    enum rsp_fsm_state_e
     {
         RSP_IDLE,
@@ -168,5 +168,5 @@
     };
 
-    enum cc_receive_fsm_state_e 
+    enum cc_receive_fsm_state_e
     {
         CC_RECEIVE_IDLE,
@@ -185,5 +185,5 @@
     };
 
-    enum cc_send_fsm_state_e 
+    enum cc_send_fsm_state_e
     {
         CC_SEND_IDLE,
@@ -204,12 +204,12 @@
         //  b1 accÃšs table llsc type SW / other
         //  b2 WRITE/CAS/LL/SC
-        TYPE_DATA_UNC               = 0x0,
-        TYPE_READ_DATA_MISS         = 0x1,
-        TYPE_READ_INS_UNC           = 0x2,
-        TYPE_READ_INS_MISS          = 0x3,
-        TYPE_WRITE                  = 0x4,
-        TYPE_CAS                    = 0x5,
-        TYPE_LL                     = 0x6,
-        TYPE_SC                     = 0x7
+        TYPE_DATA_UNC       = 0x0,
+        TYPE_READ_DATA_MISS = 0x1,
+        TYPE_READ_INS_UNC   = 0x2,
+        TYPE_READ_INS_MISS  = 0x3,
+        TYPE_WRITE          = 0x4,
+        TYPE_CAS            = 0x5,
+        TYPE_LL             = 0x6,
+        TYPE_SC             = 0x7
     };
 
@@ -217,10 +217,10 @@
     enum sc_status_type_e
     {
-        SC_SUCCESS  =   0x00000000,
-        SC_FAIL     =   0x00000001
+        SC_SUCCESS = 0x00000000,
+        SC_FAIL    = 0x00000001
     };
 
     // cc_send_type
-    typedef enum 
+    typedef enum
     {
         CC_TYPE_CLEANUP,
@@ -229,5 +229,5 @@
 
     // cc_receive_type
-    typedef enum 
+    typedef enum
     {
         CC_TYPE_CLACK,
@@ -238,5 +238,5 @@
 
     // TLB Mode : ITLB / DTLB / ICACHE / DCACHE
-    enum 
+    enum
     {
         INS_TLB_MASK    = 0x8,
@@ -250,6 +250,6 @@
     {
         MMU_NONE                      = 0x0000, // None
-        MMU_WRITE_PT1_UNMAPPED 	      = 0x0001, // Write & Page fault on PT1
-        MMU_WRITE_PT2_UNMAPPED 	      = 0x0002, // Write & Page fault on PT2
+        MMU_WRITE_PT1_UNMAPPED        = 0x0001, // Write & Page fault on PT1
+        MMU_WRITE_PT2_UNMAPPED        = 0x0002, // Write & Page fault on PT2
         MMU_WRITE_PRIVILEGE_VIOLATION = 0x0004, // Write & Protected access in user mode
         MMU_WRITE_ACCES_VIOLATION     = 0x0008, // Write to non writable page
@@ -258,9 +258,9 @@
         MMU_WRITE_PT2_ILLEGAL_ACCESS  = 0x0080, // Write & Bus Error accessing PT2
         MMU_WRITE_DATA_ILLEGAL_ACCESS = 0x0100, // Write & Bus Error in cache access
-        MMU_READ_PT1_UNMAPPED 	      = 0x1001, // Read & Page fault on PT1
-        MMU_READ_PT2_UNMAPPED 	      = 0x1002, // Read & Page fault on PT2
+        MMU_READ_PT1_UNMAPPED         = 0x1001, // Read & Page fault on PT1
+        MMU_READ_PT2_UNMAPPED         = 0x1002, // Read & Page fault on PT2
         MMU_READ_PRIVILEGE_VIOLATION  = 0x1004, // Read & Protected access in user mode
         MMU_READ_EXEC_VIOLATION       = 0x1010, // Read & Exec access to a non exec page
-        MMU_READ_UNDEFINED_XTN 	      = 0x1020, // Read & Undefined external access
+        MMU_READ_UNDEFINED_XTN        = 0x1020, // Read & Undefined external access
         MMU_READ_PT1_ILLEGAL_ACCESS   = 0x1040, // Read & Bus Error accessing PT1
         MMU_READ_PT2_ILLEGAL_ACCESS   = 0x1080, // Read & Bus Error accessing PT2
@@ -300,29 +300,29 @@
     soclib::common::AddressDecodingTable<uint64_t, bool> m_cacheability_table;
 
-    const size_t                        m_srcid;
-    const size_t                        m_cc_global_id;
-    const size_t                        m_nline_width;
-    const size_t  						m_itlb_ways;
-    const size_t  						m_itlb_sets;
-    const size_t  						m_dtlb_ways;
-    const size_t  						m_dtlb_sets;
-    const size_t  						m_icache_ways;
-    const size_t  						m_icache_sets;
-    const paddr_t 						m_icache_yzmask;
-    const size_t  						m_icache_words;
-    const size_t  						m_dcache_ways;
-    const size_t  						m_dcache_sets;
-    const paddr_t 						m_dcache_yzmask;
-    const size_t  						m_dcache_words;
-    const size_t                        m_x_width;
-    const size_t                        m_y_width;
-    const size_t                        m_proc_id;
-    const uint32_t						m_max_frozen_cycles;
-    const size_t  						m_paddr_nbits;
-    uint32_t                            m_debug_start_cycle;
-    bool                                m_debug_ok;
-
-    uint32_t                            m_dcache_paddr_ext_reset;
-    uint32_t                            m_icache_paddr_ext_reset;
+    const size_t   m_srcid;
+    const size_t   m_cc_global_id;
+    const size_t   m_nline_width;
+    const size_t   m_itlb_ways;
+    const size_t   m_itlb_sets;
+    const size_t   m_dtlb_ways;
+    const size_t   m_dtlb_sets;
+    const size_t   m_icache_ways;
+    const size_t   m_icache_sets;
+    const paddr_t  m_icache_yzmask;
+    const size_t   m_icache_words;
+    const size_t   m_dcache_ways;
+    const size_t   m_dcache_sets;
+    const paddr_t  m_dcache_yzmask;
+    const size_t   m_dcache_words;
+    const size_t   m_x_width;
+    const size_t   m_y_width;
+    const size_t   m_proc_id;
+    const uint32_t m_max_frozen_cycles;
+    const size_t   m_paddr_nbits;
+    uint32_t       m_debug_start_cycle;
+    bool           m_debug_ok;
+
+    uint32_t       m_dcache_paddr_ext_reset;
+    uint32_t       m_icache_paddr_ext_reset;
 
     ////////////////////////////////////////
@@ -335,5 +335,5 @@
 
     /////////////////////////////////////////////
-    // debug variables 
+    // debug variables
     /////////////////////////////////////////////
     bool                                m_debug_previous_i_hit;
@@ -348,14 +348,14 @@
     // Software visible REGISTERS
     ///////////////////////////////
-    sc_signal<uint32_t>     r_mmu_ptpr;             	// page table pointer register
-    sc_signal<uint32_t>     r_mmu_mode;             	// mmu mode register
-    sc_signal<uint32_t>     r_mmu_word_lo;          	// mmu misc data low
-    sc_signal<uint32_t>     r_mmu_word_hi;          	// mmu misc data hight
-    sc_signal<uint32_t>     r_mmu_ibvar;      	    	// mmu bad instruction address
-    sc_signal<uint32_t>     r_mmu_dbvar;              	// mmu bad data address
+    sc_signal<uint32_t>     r_mmu_ptpr;                 // page table pointer register
+    sc_signal<uint32_t>     r_mmu_mode;                 // mmu mode register
+    sc_signal<uint32_t>     r_mmu_word_lo;              // mmu misc data low
+    sc_signal<uint32_t>     r_mmu_word_hi;              // mmu misc data hight
+    sc_signal<uint32_t>     r_mmu_ibvar;                  // mmu bad instruction address
+    sc_signal<uint32_t>     r_mmu_dbvar;                  // mmu bad data address
     sc_signal<uint32_t>     r_mmu_ietr;                 // mmu instruction error type
     sc_signal<uint32_t>     r_mmu_detr;                 // mmu data error type
-    uint32_t	            r_mmu_params;		        // read-only
-    uint32_t	            r_mmu_release;		        // read_only
+    uint32_t                r_mmu_params;                // read-only
+    uint32_t                r_mmu_release;                // read_only
 
 
@@ -365,27 +365,27 @@
     sc_signal<int>          r_icache_fsm;               // state register
     sc_signal<int>          r_icache_fsm_save;          // return state for coherence op
-    sc_signal<paddr_t>      r_icache_vci_paddr;      	// physical address
+    sc_signal<paddr_t>      r_icache_vci_paddr;          // physical address
     sc_signal<uint32_t>     r_icache_vaddr_save;        // virtual address from processor
 
     // icache miss handling
-    sc_signal<size_t>       r_icache_miss_way;		    // selected way for cache update
-    sc_signal<size_t>       r_icache_miss_set;		    // selected set for cache update
-    sc_signal<size_t>       r_icache_miss_word;		    // word index ( cache update)
+    sc_signal<size_t>       r_icache_miss_way;            // selected way for cache update
+    sc_signal<size_t>       r_icache_miss_set;            // selected set for cache update
+    sc_signal<size_t>       r_icache_miss_word;            // word index ( cache update)
     sc_signal<bool>         r_icache_miss_inval;        // coherence request matching a miss
     sc_signal<bool>         r_icache_miss_clack;        // waiting for a cleanup acknowledge
 
     // coherence request handling
-    sc_signal<size_t>       r_icache_cc_way;		    // selected way for cc update/inval
-    sc_signal<size_t>       r_icache_cc_set;		    // selected set for cc update/inval
-    sc_signal<size_t>       r_icache_cc_word;		    // word counter for cc update
+    sc_signal<size_t>       r_icache_cc_way;            // selected way for cc update/inval
+    sc_signal<size_t>       r_icache_cc_set;            // selected set for cc update/inval
+    sc_signal<size_t>       r_icache_cc_word;            // word counter for cc update
     sc_signal<bool>         r_icache_cc_need_write;     // activate the cache for writing
 
     // coherence clack handling
     sc_signal<bool>         r_icache_clack_req;         // clack request
-    sc_signal<size_t>       r_icache_clack_way;		    // clack way
-    sc_signal<size_t>       r_icache_clack_set;		    // clack set
+    sc_signal<size_t>       r_icache_clack_way;            // clack way
+    sc_signal<size_t>       r_icache_clack_set;            // clack set
 
     // icache flush handling
-    sc_signal<size_t>       r_icache_flush_count;	    // slot counter used for cache flush
+    sc_signal<size_t>       r_icache_flush_count;        // slot counter used for cache flush
 
     // communication between ICACHE FSM and VCI_CMD FSM
@@ -394,9 +394,9 @@
 
     // communication between ICACHE FSM and DCACHE FSM
-    sc_signal<bool>	        r_icache_tlb_miss_req;       // (set icache/reset dcache)
+    sc_signal<bool>            r_icache_tlb_miss_req;       // (set icache/reset dcache)
     sc_signal<bool>         r_icache_tlb_rsp_error;      // tlb miss response error
 
     // Filp-Flop in ICACHE FSM for saving the cleanup victim request
-    sc_signal<bool>         r_icache_cleanup_victim_req; 
+    sc_signal<bool>         r_icache_cleanup_victim_req;
     sc_signal<paddr_t>      r_icache_cleanup_victim_nline;
 
@@ -424,15 +424,15 @@
     sc_signal<uint32_t>     r_dcache_save_be;           // byte enable (from proc)
     sc_signal<paddr_t>      r_dcache_save_paddr;        // physical address
-    sc_signal<size_t>       r_dcache_save_cache_way;	// selected way (from dcache)
-    sc_signal<size_t>       r_dcache_save_cache_set;	// selected set (from dcache)
-    sc_signal<size_t>       r_dcache_save_cache_word;	// selected word (from dcache)
+    sc_signal<size_t>       r_dcache_save_cache_way;    // selected way (from dcache)
+    sc_signal<size_t>       r_dcache_save_cache_set;    // selected set (from dcache)
+    sc_signal<size_t>       r_dcache_save_cache_word;    // selected word (from dcache)
     // registers used by the Dirty bit sub-fsm
     sc_signal<paddr_t>      r_dcache_dirty_paddr;       // PTE physical address
-    sc_signal<size_t>       r_dcache_dirty_way;	        // way to invalidate in dcache
-    sc_signal<size_t>       r_dcache_dirty_set;	        // set to invalidate in dcache
+    sc_signal<size_t>       r_dcache_dirty_way;            // way to invalidate in dcache
+    sc_signal<size_t>       r_dcache_dirty_set;            // set to invalidate in dcache
 
     // communication between DCACHE FSM and VCI_CMD FSM
-    sc_signal<paddr_t>      r_dcache_vci_paddr;		    // physical address for VCI command
-    sc_signal<uint32_t>     r_dcache_vci_wdata;		    // write unc data for VCI command
+    sc_signal<paddr_t>      r_dcache_vci_paddr;            // physical address for VCI command
+    sc_signal<uint32_t>     r_dcache_vci_wdata;            // write unc data for VCI command
     sc_signal<bool>         r_dcache_vci_miss_req;      // read miss request
     sc_signal<bool>         r_dcache_vci_unc_req;       // uncacheable request (read/write)
@@ -447,46 +447,46 @@
 
     // register used for XTN inval
-    sc_signal<size_t>       r_dcache_xtn_way;		    // selected way (from dcache)
-    sc_signal<size_t>       r_dcache_xtn_set;		    // selected set (from dcache)
+    sc_signal<size_t>       r_dcache_xtn_way;            // selected way (from dcache)
+    sc_signal<size_t>       r_dcache_xtn_set;            // selected set (from dcache)
 
     // handling dcache miss
-    sc_signal<int>	        r_dcache_miss_type;		    // depending on the requester
-    sc_signal<size_t>       r_dcache_miss_word;		    // word index for cache update
-    sc_signal<size_t>       r_dcache_miss_way;		    // selected way for cache update
-    sc_signal<size_t>       r_dcache_miss_set;		    // selected set for cache update
+    sc_signal<int>            r_dcache_miss_type;            // depending on the requester
+    sc_signal<size_t>       r_dcache_miss_word;            // word index for cache update
+    sc_signal<size_t>       r_dcache_miss_way;            // selected way for cache update
+    sc_signal<size_t>       r_dcache_miss_set;            // selected set for cache update
     sc_signal<bool>         r_dcache_miss_inval;        // coherence request matching a miss
     sc_signal<bool>         r_dcache_miss_clack;        // waiting for a cleanup acknowledge
 
     // handling coherence requests
-    sc_signal<size_t>       r_dcache_cc_way;		    // selected way for cc update/inval
-    sc_signal<size_t>       r_dcache_cc_set;		    // selected set for cc update/inval
-    sc_signal<size_t>       r_dcache_cc_word;		    // word counter for cc update
+    sc_signal<size_t>       r_dcache_cc_way;            // selected way for cc update/inval
+    sc_signal<size_t>       r_dcache_cc_set;            // selected set for cc update/inval
+    sc_signal<size_t>       r_dcache_cc_word;            // word counter for cc update
     sc_signal<bool>         r_dcache_cc_need_write;     // activate the cache for writing
 
     // coherence clack handling
     sc_signal<bool>         r_dcache_clack_req;         // clack request
-    sc_signal<size_t>       r_dcache_clack_way;		    // clack way
-    sc_signal<size_t>       r_dcache_clack_set;		    // clack set
+    sc_signal<size_t>       r_dcache_clack_way;            // clack way
+    sc_signal<size_t>       r_dcache_clack_set;            // clack set
 
     // dcache flush handling
-    sc_signal<size_t>       r_dcache_flush_count;	    // slot counter used for cache flush
+    sc_signal<size_t>       r_dcache_flush_count;        // slot counter used for cache flush
 
     // ll response handling
-    sc_signal<size_t>       r_dcache_ll_rsp_count;	    // flit counter used for ll rsp
+    sc_signal<size_t>       r_dcache_ll_rsp_count;        // flit counter used for ll rsp
 
     // used by the TLB miss sub-fsm
-    sc_signal<uint32_t>     r_dcache_tlb_vaddr;		    // virtual address for a tlb miss
-    sc_signal<bool>         r_dcache_tlb_ins;		    // target tlb (itlb if true)
-    sc_signal<paddr_t>      r_dcache_tlb_paddr;		    // physical address of pte
-    sc_signal<uint32_t>     r_dcache_tlb_pte_flags;	    // pte1 or first word of pte2
-    sc_signal<uint32_t>     r_dcache_tlb_pte_ppn;	    // second word of pte2
-    sc_signal<size_t>       r_dcache_tlb_cache_way;	    // selected way in dcache
-    sc_signal<size_t>       r_dcache_tlb_cache_set;	    // selected set in dcache
-    sc_signal<size_t>       r_dcache_tlb_cache_word;	// selected word in dcache
-    sc_signal<size_t>       r_dcache_tlb_way;		    // selected way in tlb
-    sc_signal<size_t>       r_dcache_tlb_set;		    // selected set in tlb
+    sc_signal<uint32_t>     r_dcache_tlb_vaddr;            // virtual address for a tlb miss
+    sc_signal<bool>         r_dcache_tlb_ins;            // target tlb (itlb if true)
+    sc_signal<paddr_t>      r_dcache_tlb_paddr;            // physical address of pte
+    sc_signal<uint32_t>     r_dcache_tlb_pte_flags;        // pte1 or first word of pte2
+    sc_signal<uint32_t>     r_dcache_tlb_pte_ppn;        // second word of pte2
+    sc_signal<size_t>       r_dcache_tlb_cache_way;        // selected way in dcache
+    sc_signal<size_t>       r_dcache_tlb_cache_set;        // selected set in dcache
+    sc_signal<size_t>       r_dcache_tlb_cache_word;    // selected word in dcache
+    sc_signal<size_t>       r_dcache_tlb_way;            // selected way in tlb
+    sc_signal<size_t>       r_dcache_tlb_set;            // selected set in tlb
 
     // ITLB and DTLB invalidation
-    sc_signal<paddr_t>      r_dcache_tlb_inval_line;	// line index
+    sc_signal<paddr_t>      r_dcache_tlb_inval_line;    // line index
     sc_signal<size_t>       r_dcache_tlb_inval_set;     // tlb set counter
 
@@ -496,5 +496,5 @@
 
     // Filp-Flop in DCACHE FSM for saving the cleanup victim request
-    sc_signal<bool>         r_dcache_cleanup_victim_req; 
+    sc_signal<bool>         r_dcache_cleanup_victim_req;
     sc_signal<paddr_t>      r_dcache_cleanup_victim_nline;
 
@@ -517,8 +517,8 @@
     ///////////////////////////////////
     sc_signal<int>          r_vci_cmd_fsm;
-    sc_signal<size_t>       r_vci_cmd_min;      	        // used for write bursts
-    sc_signal<size_t>       r_vci_cmd_max;      	        // used for write bursts
-    sc_signal<size_t>       r_vci_cmd_cpt;    		        // used for write bursts
-    sc_signal<bool>         r_vci_cmd_imiss_prio;	        // round-robin between imiss & dmiss
+    sc_signal<size_t>       r_vci_cmd_min;                  // used for write bursts
+    sc_signal<size_t>       r_vci_cmd_max;                  // used for write bursts
+    sc_signal<size_t>       r_vci_cmd_cpt;                    // used for write bursts
+    sc_signal<bool>         r_vci_cmd_imiss_prio;            // round-robin between imiss & dmiss
 
     ///////////////////////////////////
@@ -529,6 +529,6 @@
     sc_signal<bool>         r_vci_rsp_ins_error;
     sc_signal<bool>         r_vci_rsp_data_error;
-    GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;	        // response FIFO to ICACHE FSM
-    GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;	        // response FIFO to DCACHE FSM
+    GenericFifo<uint32_t>   r_vci_rsp_fifo_icache;            // response FIFO to ICACHE FSM
+    GenericFifo<uint32_t>   r_vci_rsp_fifo_dcache;            // response FIFO to DCACHE FSM
 
     ///////////////////////////////////
@@ -556,5 +556,5 @@
     sc_signal<size_t>       r_cc_receive_icache_set;        // cc_receive to icache set
     sc_signal<size_t>       r_cc_receive_icache_updt_tab_idx;  // cc_receive update table index
-    sc_signal<paddr_t>      r_cc_receive_icache_nline;	    // cache line physical address
+    sc_signal<paddr_t>      r_cc_receive_icache_nline;        // cache line physical address
 
     // communication between CC_RECEIVE FSM and DCACHE FSM
@@ -564,5 +564,5 @@
     sc_signal<size_t>       r_cc_receive_dcache_set;        // cc_receive to dcache set
     sc_signal<size_t>       r_cc_receive_dcache_updt_tab_idx;  // cc_receive update table index
-    sc_signal<paddr_t>      r_cc_receive_dcache_nline;	    // cache line physical address
+    sc_signal<paddr_t>      r_cc_receive_dcache_nline;        // cache line physical address
 
     ///////////////////////////////////
@@ -571,15 +571,15 @@
     sc_signal<bool>         r_dspin_clack_req;
     sc_signal<uint64_t>     r_dspin_clack_flit;
-    
+
     //////////////////////////////////////////////////////////////////
     // processor, write buffer, caches , TLBs
     //////////////////////////////////////////////////////////////////
 
-    iss_t                       r_iss;
-    MultiWriteBuffer<paddr_t>	r_wbuf;
-    GenericCache<paddr_t>   	r_icache;
-    GenericCache<paddr_t>    	r_dcache;
-    GenericTlb<paddr_t>       	r_itlb;
-    GenericTlb<paddr_t>     	r_dtlb;
+    iss_t                     r_iss;
+    MultiWriteBuffer<paddr_t> r_wbuf;
+    GenericCache<paddr_t>     r_icache;
+    GenericCache<paddr_t>     r_dcache;
+    GenericTlb<paddr_t>       r_itlb;
+    GenericTlb<paddr_t>       r_dtlb;
 
     //////////////////////////////////////////////////////////////////
@@ -587,8 +587,8 @@
     //////////////////////////////////////////////////////////////////
 
-    sc_signal<paddr_t>                     r_dcache_llsc_paddr;
-    sc_signal<uint32_t>                    r_dcache_llsc_key;
-    sc_signal<uint32_t>                    r_dcache_llsc_count;
-    sc_signal<bool>                        r_dcache_llsc_valid;
+    sc_signal<paddr_t>        r_dcache_llsc_paddr;
+    sc_signal<uint32_t>       r_dcache_llsc_key;
+    sc_signal<uint32_t>       r_dcache_llsc_count;
+    sc_signal<bool>           r_dcache_llsc_valid;
 
     ////////////////////////////////
@@ -605,6 +605,6 @@
     uint32_t m_cpt_icache_dir_write;        // ICACHE DIR WRITE
 
-    uint32_t m_cpt_frz_cycles;	            // number of cycles where the cpu is frozen
-    uint32_t m_cpt_total_cycles;	        // total number of cycles
+    uint32_t m_cpt_frz_cycles;              // number of cycles where the cpu is frozen
+    uint32_t m_cpt_total_cycles;            // total number of cycles
 
     // Cache activity counters
@@ -651,6 +651,6 @@
     uint32_t m_cpt_tlb_occup_dcache;
 
-    uint32_t m_cost_ins_tlb_miss_frz;       // number of frozen cycles related to instruction tlb miss
-    uint32_t m_cost_data_tlb_miss_frz;      // number of frozen cycles related to data tlb miss
+    uint32_t m_cost_ins_tlb_miss_frz;          // number of frozen cycles related to instruction tlb miss
+    uint32_t m_cost_data_tlb_miss_frz;         // number of frozen cycles related to data tlb miss
     uint32_t m_cost_ins_tlb_update_acc_frz;    // number of frozen cycles related to instruction tlb update acc
     uint32_t m_cost_data_tlb_update_acc_frz;   // number of frozen cycles related to data tlb update acc
@@ -668,32 +668,32 @@
     uint32_t m_cpt_dtlb_sc_dirty_transaction;  // number of dtlb sc dirty transactions
 
-    uint32_t m_cost_itlbmiss_transaction;       // cumulated duration for VCI instruction TLB miss transactions
-    uint32_t m_cost_itlb_ll_transaction;        // cumulated duration for VCI instruction TLB ll acc transactions
-    uint32_t m_cost_itlb_sc_transaction;        // cumulated duration for VCI instruction TLB sc acc transactions
-    uint32_t m_cost_dtlbmiss_transaction;       // cumulated duration for VCI data TLB miss transactions
-    uint32_t m_cost_dtlb_ll_transaction;        // cumulated duration for VCI data TLB ll acc transactions
-    uint32_t m_cost_dtlb_sc_transaction;        // cumulated duration for VCI data TLB sc acc transactions
-    uint32_t m_cost_dtlb_ll_dirty_transaction;  // cumulated duration for VCI data TLB ll dirty transactions
-    uint32_t m_cost_dtlb_sc_dirty_transaction;  // cumulated duration for VCI data TLB sc dirty transactions
+    uint32_t m_cost_itlbmiss_transaction;      // cumulated duration for VCI instruction TLB miss transactions
+    uint32_t m_cost_itlb_ll_transaction;       // cumulated duration for VCI instruction TLB ll acc transactions
+    uint32_t m_cost_itlb_sc_transaction;       // cumulated duration for VCI instruction TLB sc acc transactions
+    uint32_t m_cost_dtlbmiss_transaction;      // cumulated duration for VCI data TLB miss transactions
+    uint32_t m_cost_dtlb_ll_transaction;       // cumulated duration for VCI data TLB ll acc transactions
+    uint32_t m_cost_dtlb_sc_transaction;       // cumulated duration for VCI data TLB sc acc transactions
+    uint32_t m_cost_dtlb_ll_dirty_transaction; // cumulated duration for VCI data TLB ll dirty transactions
+    uint32_t m_cost_dtlb_sc_dirty_transaction; // cumulated duration for VCI data TLB sc dirty transactions
 
     // coherence activity counters
-    uint32_t m_cpt_cc_update_icache;            // number of coherence update instruction commands
-    uint32_t m_cpt_cc_update_dcache;            // number of coherence update data commands
-    uint32_t m_cpt_cc_inval_icache;             // number of coherence inval instruction commands
-    uint32_t m_cpt_cc_inval_dcache;             // number of coherence inval data commands
-    uint32_t m_cpt_cc_broadcast;                // number of coherence broadcast commands
-
-    uint32_t m_cost_updt_data_frz;              // number of frozen cycles related to coherence update data packets
-    uint32_t m_cost_inval_ins_frz;              // number of frozen cycles related to coherence inval instruction packets
-    uint32_t m_cost_inval_data_frz;             // number of frozen cycles related to coherence inval data packets
-    uint32_t m_cost_broadcast_frz;              // number of frozen cycles related to coherence broadcast packets
-
-    uint32_t m_cpt_cc_cleanup_ins;              // number of coherence cleanup packets
-    uint32_t m_cpt_cc_cleanup_data;             // number of coherence cleanup packets
-
-    uint32_t m_cpt_icleanup_transaction;        // number of instruction cleanup transactions
-    uint32_t m_cpt_dcleanup_transaction;        // number of instructinumber of data cleanup transactions
-    uint32_t m_cost_icleanup_transaction;       // cumulated duration for VCI instruction cleanup transactions
-    uint32_t m_cost_dcleanup_transaction;       // cumulated duration for VCI data cleanup transactions
+    uint32_t m_cpt_cc_update_icache;        // number of coherence update instruction commands
+    uint32_t m_cpt_cc_update_dcache;        // number of coherence update data commands
+    uint32_t m_cpt_cc_inval_icache;         // number of coherence inval instruction commands
+    uint32_t m_cpt_cc_inval_dcache;         // number of coherence inval data commands
+    uint32_t m_cpt_cc_broadcast;            // number of coherence broadcast commands
+
+    uint32_t m_cost_updt_data_frz;          // number of frozen cycles related to coherence update data packets
+    uint32_t m_cost_inval_ins_frz;          // number of frozen cycles related to coherence inval instruction packets
+    uint32_t m_cost_inval_data_frz;         // number of frozen cycles related to coherence inval data packets
+    uint32_t m_cost_broadcast_frz;          // number of frozen cycles related to coherence broadcast packets
+
+    uint32_t m_cpt_cc_cleanup_ins;          // number of coherence cleanup packets
+    uint32_t m_cpt_cc_cleanup_data;         // number of coherence cleanup packets
+
+    uint32_t m_cpt_icleanup_transaction;    // number of instruction cleanup transactions
+    uint32_t m_cpt_dcleanup_transaction;    // number of instructinumber of data cleanup transactions
+    uint32_t m_cost_icleanup_transaction;   // cumulated duration for VCI instruction cleanup transactions
+    uint32_t m_cost_dcleanup_transaction;   // cumulated duration for VCI data cleanup transactions
 
     uint32_t m_cost_ins_tlb_inval_frz;      // number of frozen cycles related to checking ins tlb invalidate
@@ -711,8 +711,8 @@
     uint32_t m_cpt_fsm_cc_send    [64];
 
-    uint32_t m_cpt_stop_simulation;		// used to stop simulation if frozen
-    bool     m_monitor_ok;		        // used to debug cache output  
-    uint32_t m_monitor_base;		    
-    uint32_t m_monitor_length;		    
+    uint32_t m_cpt_stop_simulation;       // used to stop simulation if frozen
+    bool     m_monitor_ok;                // used to debug cache output
+    uint32_t m_monitor_base;
+    uint32_t m_monitor_length;
 
 protected:
@@ -753,7 +753,7 @@
     void start_monitor(paddr_t,paddr_t);
     void stop_monitor();
-    inline void iss_set_debug_mask(uint v) 
-    {
-	    r_iss.set_debug_mask(v);
+    inline void iss_set_debug_mask(uint v)
+    {
+        r_iss.set_debug_mask(v);
     }
 
Index: branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp
===================================================================
--- branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 839)
+++ branches/reconfiguration/modules/vci_cc_vcache_wrapper/caba/source/src/vci_cc_vcache_wrapper.cpp	(revision 840)
@@ -1387,6 +1387,6 @@
             int state;
             paddr_t tag;
-            size_t way = r_icache_flush_count.read()/m_icache_sets;
-            size_t set = r_icache_flush_count.read()%m_icache_sets;
+            size_t way = r_icache_flush_count.read() / m_icache_sets;
+            size_t set = r_icache_flush_count.read() % m_icache_sets;
 
 #ifdef INSTRUMENTATION
@@ -2438,5 +2438,5 @@
             if (m_dreq.type == iss_t::XTN_READ)
             {
-                int xtn_opcode = (int)m_dreq.addr / 4;
+                int xtn_opcode = (int) m_dreq.addr / 4;
 
                 // checking processor mode:
@@ -2972,5 +2972,5 @@
 
         // itlb miss request
-        else if (r_icache_tlb_miss_req.read() and not wbuf_write_miss )
+        else if (r_icache_tlb_miss_req.read() and not wbuf_write_miss)
         {
             r_dcache_tlb_ins    = true;
@@ -3111,5 +3111,5 @@
 
             }
-            else if (entry & PTE_T_MASK ) //  PTD : me must access PT2
+            else if (entry & PTE_T_MASK) //  PTD : me must access PT2
             {
                 // mark the cache line ac containing a PTD
@@ -3847,6 +3847,6 @@
             int     state;
             paddr_t tag;
-            size_t  way = r_dcache_flush_count.read()/m_dcache_sets;
-            size_t  set = r_dcache_flush_count.read()%m_dcache_sets;
+            size_t  way = r_dcache_flush_count.read() / m_dcache_sets;
+            size_t  set = r_dcache_flush_count.read() % m_dcache_sets;
 
 #ifdef INSTRUMENTATION
@@ -4460,7 +4460,7 @@
                 r_dcache_contains_ptd[way * m_dcache_sets + set] = false;
             }
-            if      (r_dcache_miss_type.read()==PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
-            else if (r_dcache_miss_type.read()==PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
-            else                                           r_dcache_fsm = DCACHE_IDLE;
+            if      (r_dcache_miss_type.read() == PTE1_MISS) r_dcache_fsm = DCACHE_TLB_PTE1_GET;
+            else if (r_dcache_miss_type.read() == PTE2_MISS) r_dcache_fsm = DCACHE_TLB_PTE2_GET;
+            else                                             r_dcache_fsm = DCACHE_IDLE;
         }
         break;
@@ -4760,6 +4760,6 @@
         }
 
-        assert ( not r_dcache_cc_send_req.read() and
-        "CC_SEND must be available in DCACHE_CC_CHECK" );
+        assert(not r_dcache_cc_send_req.read() and
+        "CC_SEND must be available in DCACHE_CC_CHECK");
 
         // Match between MISS address and CC address
@@ -6021,5 +6021,5 @@
         p_vci.trdid   = 0;
         p_vci.pktid   = TYPE_READ_INS_MISS;
-        p_vci.plen    = m_icache_words<<2;
+        p_vci.plen    = m_icache_words << 2;
         p_vci.cmd     = vci_param::CMD_READ;
         p_vci.eop     = true;
