Changeset 841 for branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster

Timestamp:

Oct 15, 2014, 3:30:34 PM (10 years ago)

Author:

cfuguet

Message:

reconf/tsar_generic_iob: updating metadata files

• Renaming the mem cache dspin parameters by the new names introduced in revision 836.

• Using the vci_cc_vcache_wrapper of the reconfiguration branch instead of the one in the trunk

File:

• branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd (modified) (8 diffs)

branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd

@@ -6 +6 @@
 
     tmpl_parameters = [
-        parameter.Module('vci_param_int', default = 'caba:vci_param', 
+        parameter.Module('vci_param_int', default = 'caba:vci_param',
                           cell_size = parameter.Reference('vci_data_width_int')),
-        parameter.Module('vci_param_ext', default = 'caba:vci_param', 
+        parameter.Module('vci_param_ext', default = 'caba:vci_param',
                           cell_size = parameter.Reference('vci_data_width_ext')),
         parameter.Int('dspin_int_cmd_width'),
@@ -16 +16 @@
     ],
 
-    header_files = [ 
-        '../source/include/tsar_iob_cluster.h', 
+    header_files = [
+        '../source/include/tsar_iob_cluster.h',
     ],
 
-    implementation_files = [ 
-        '../source/src/tsar_iob_cluster.cpp', 
+    implementation_files = [
+        '../source/src/tsar_iob_cluster.cpp',
     ],
 
@@ -31 +31 @@
 
         # internal network components
-        Uses('caba:vci_cc_vcache_wrapper', 
+        Uses('caba:reconf:vci_cc_vcache_wrapper',
               cell_size          = parameter.Reference('vci_data_width_int'),
               dspin_in_width     = parameter.Reference('dspin_int_cmd_width'),
               dspin_out_width    = parameter.Reference('dspin_int_rsp_width'),
-              iss_t              = 'common:gdb_iss', 
+              iss_t              = 'common:gdb_iss',
               gdb_iss_t          = 'common:mips32el'),
 
         Uses('caba:vci_mem_cache',
-              memc_cell_size_int = parameter.Reference('vci_data_width_int'),
-              memc_cell_size_ext = parameter.Reference('vci_data_width_ext'),
-              dspin_in_width     = parameter.Reference('dspin_int_rsp_width'),
-              dspin_out_width    = parameter.Reference('dspin_int_cmd_width')),
+              memc_cell_size_int   = parameter.Reference('vci_data_width_int'),
+              memc_cell_size_ext   = parameter.Reference('vci_data_width_ext'),
+              memc_dspin_in_width  = parameter.Reference('dspin_int_rsp_width'),
+              memc_dspin_out_width = parameter.Reference('dspin_int_cmd_width')),
 
         Uses('caba:vci_xicu',
@@ -53 +53 @@
               cell_size          = parameter.Reference('vci_data_width_int')),
 
-        Uses('caba:vci_local_crossbar', 
+        Uses('caba:vci_local_crossbar',
               cell_size          = parameter.Reference('vci_data_width_int')),
 
-        Uses('caba:dspin_local_crossbar', 
+        Uses('caba:dspin_local_crossbar',
               flit_width         = parameter.Reference('dspin_int_cmd_width')),
 
-        Uses('caba:dspin_local_crossbar', 
+        Uses('caba:dspin_local_crossbar',
               flit_width         = parameter.Reference('dspin_int_rsp_width')),
 
-        Uses('caba:dspin_local_crossbar', 
+        Uses('caba:dspin_local_crossbar',
               flit_width         = parameter.Reference('dspin_ram_cmd_width')),
 
-        Uses('caba:dspin_local_crossbar', 
+        Uses('caba:dspin_local_crossbar',
               flit_width         = parameter.Reference('dspin_ram_rsp_width')),
 
-        Uses('caba:vci_dspin_initiator_wrapper', 
+        Uses('caba:vci_dspin_initiator_wrapper',
               cell_size          = parameter.Reference('vci_data_width_int'),
               dspin_cmd_width    = parameter.Reference('dspin_int_cmd_width'),
@@ -78 +78 @@
               dspin_rsp_width    = parameter.Reference('dspin_int_rsp_width')),
 
-        Uses('caba:virtual_dspin_router', 
+        Uses('caba:virtual_dspin_router',
               flit_width         = parameter.Reference('dspin_int_cmd_width')),
 
-        Uses('caba:virtual_dspin_router', 
+        Uses('caba:virtual_dspin_router',
               flit_width         = parameter.Reference('dspin_int_rsp_width')),
 
         # RAM network components
-        Uses('caba:vci_dspin_initiator_wrapper', 
+        Uses('caba:vci_dspin_initiator_wrapper',
               cell_size          = parameter.Reference('vci_data_width_ext'),
               dspin_cmd_width    = parameter.Reference('dspin_ram_cmd_width'),
@@ -95 +95 @@
               dspin_rsp_width    = parameter.Reference('dspin_ram_rsp_width')),
 
-        Uses('caba:dspin_router', 
+        Uses('caba:dspin_router',
               flit_width         = parameter.Reference('dspin_ram_cmd_width')),
 
-        Uses('caba:dspin_router', 
+        Uses('caba:dspin_router',
               flit_width         = parameter.Reference('dspin_ram_rsp_width')),
 
@@ -105 +105 @@
 
         # IOX network components
-        Uses('caba:vci_io_bridge', 
+        Uses('caba:vci_io_bridge',
               iob_cell_size_int  = parameter.Reference('vci_data_width_int'),
               iob_cell_size_ext  = parameter.Reference('vci_data_width_ext')),
@@ -114 +114 @@
         Port('caba:clock_in', 'p_clk', auto = 'clock'),
 
-        Port('caba:dspin_output', 'p_int_cmd_out', [4, 3], 
+        Port('caba:dspin_output', 'p_int_cmd_out', [4, 3],
               dspin_data_size = parameter.Reference('dspin_int_cmd_width')),
-        Port('caba:dspin_input', 'p_int_cmd_in', [4, 3], 
+        Port('caba:dspin_input', 'p_int_cmd_in', [4, 3],
               dspin_data_size = parameter.Reference('dspin_int_cmd_width')),
-        Port('caba:dspin_output', 'p_int_rsp_out', [4, 2], 
-              dspin_data_size = parameter.Reference('dspin_int_rsp_width')), 
-        Port('caba:dspin_input', 'p_int_rsp_in', [4, 2], 
+        Port('caba:dspin_output', 'p_int_rsp_out', [4, 2],
+              dspin_data_size = parameter.Reference('dspin_int_rsp_width')),
+        Port('caba:dspin_input', 'p_int_rsp_in', [4, 2],
               dspin_data_size = parameter.Reference('dspin_int_rsp_width')),
 
-        Port('caba:dspin_output', 'p_ram_cmd_out', [4], 
+        Port('caba:dspin_output', 'p_ram_cmd_out', [4],
               dspin_data_size = parameter.Reference('dspin_ram_cmd_width')),
-        Port('caba:dspin_input', 'p_ram_cmd_in', [4], 
+        Port('caba:dspin_input', 'p_ram_cmd_in', [4],
               dspin_data_size = parameter.Reference('dspin_ram_cmd_width')),
-        Port('caba:dspin_output', 'p_ram_rsp_out', [4], 
-              dspin_data_size = parameter.Reference('dspin_ram_rsp_width')), 
-        Port('caba:dspin_input', 'p_ram_rsp_in', [4], 
+        Port('caba:dspin_output', 'p_ram_rsp_out', [4],
+              dspin_data_size = parameter.Reference('dspin_ram_rsp_width')),
+        Port('caba:dspin_input', 'p_ram_rsp_in', [4],
               dspin_data_size = parameter.Reference('dspin_ram_rsp_width')),
         ],