Index: branches/reconfiguration/platforms/tsar_generic_iob/scripts/onerun.py
===================================================================
--- branches/reconfiguration/platforms/tsar_generic_iob/scripts/onerun.py	(revision 840)
+++ branches/reconfiguration/platforms/tsar_generic_iob/scripts/onerun.py	(revision 841)
@@ -88,4 +88,5 @@
 # 5. execute simulator
 os.environ["DISTRIBUTED_BOOT"] = "1"
+os.environ["SOCLIB_FB"] = "HEADLESS"
 if args.quiet: os.environ["SOCLIB_TTY"] = "FILES"
 
Index: branches/reconfiguration/platforms/tsar_generic_iob/soclib.conf
===================================================================
--- branches/reconfiguration/platforms/tsar_generic_iob/soclib.conf	(revision 840)
+++ branches/reconfiguration/platforms/tsar_generic_iob/soclib.conf	(revision 841)
@@ -12,2 +12,3 @@
 config.addDescPath(join(tsarpath, "trunk/communication"))
 config.addDescPath(join(tsarpath, "trunk/modules"))
+config.addDescPath(join(tsarpath, "branches/reconfiguration/modules"))
Index: branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd
===================================================================
--- branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd	(revision 840)
+++ branches/reconfiguration/platforms/tsar_generic_iob/tsar_iob_cluster/caba/metadata/tsar_iob_cluster.sd	(revision 841)
@@ -6,7 +6,7 @@
 
     tmpl_parameters = [
-        parameter.Module('vci_param_int', default = 'caba:vci_param', 
+        parameter.Module('vci_param_int', default = 'caba:vci_param',
                           cell_size = parameter.Reference('vci_data_width_int')),
-        parameter.Module('vci_param_ext', default = 'caba:vci_param', 
+        parameter.Module('vci_param_ext', default = 'caba:vci_param',
                           cell_size = parameter.Reference('vci_data_width_ext')),
         parameter.Int('dspin_int_cmd_width'),
@@ -16,10 +16,10 @@
     ],
 
-    header_files = [ 
-        '../source/include/tsar_iob_cluster.h', 
+    header_files = [
+        '../source/include/tsar_iob_cluster.h',
     ],
 
-    implementation_files = [ 
-        '../source/src/tsar_iob_cluster.cpp', 
+    implementation_files = [
+        '../source/src/tsar_iob_cluster.cpp',
     ],
 
@@ -31,16 +31,16 @@
 
         # internal network components
-        Uses('caba:vci_cc_vcache_wrapper', 
+        Uses('caba:reconf:vci_cc_vcache_wrapper',
               cell_size          = parameter.Reference('vci_data_width_int'),
               dspin_in_width     = parameter.Reference('dspin_int_cmd_width'),
               dspin_out_width    = parameter.Reference('dspin_int_rsp_width'),
-              iss_t              = 'common:gdb_iss', 
+              iss_t              = 'common:gdb_iss',
               gdb_iss_t          = 'common:mips32el'),
 
         Uses('caba:vci_mem_cache',
-              memc_cell_size_int = parameter.Reference('vci_data_width_int'),
-              memc_cell_size_ext = parameter.Reference('vci_data_width_ext'),
-              dspin_in_width     = parameter.Reference('dspin_int_rsp_width'),
-              dspin_out_width    = parameter.Reference('dspin_int_cmd_width')),
+              memc_cell_size_int   = parameter.Reference('vci_data_width_int'),
+              memc_cell_size_ext   = parameter.Reference('vci_data_width_ext'),
+              memc_dspin_in_width  = parameter.Reference('dspin_int_rsp_width'),
+              memc_dspin_out_width = parameter.Reference('dspin_int_cmd_width')),
 
         Uses('caba:vci_xicu',
@@ -53,20 +53,20 @@
               cell_size          = parameter.Reference('vci_data_width_int')),
 
-        Uses('caba:vci_local_crossbar', 
+        Uses('caba:vci_local_crossbar',
               cell_size          = parameter.Reference('vci_data_width_int')),
 
-        Uses('caba:dspin_local_crossbar', 
+        Uses('caba:dspin_local_crossbar',
               flit_width         = parameter.Reference('dspin_int_cmd_width')),
 
-        Uses('caba:dspin_local_crossbar', 
+        Uses('caba:dspin_local_crossbar',
               flit_width         = parameter.Reference('dspin_int_rsp_width')),
 
-        Uses('caba:dspin_local_crossbar', 
+        Uses('caba:dspin_local_crossbar',
               flit_width         = parameter.Reference('dspin_ram_cmd_width')),
 
-        Uses('caba:dspin_local_crossbar', 
+        Uses('caba:dspin_local_crossbar',
               flit_width         = parameter.Reference('dspin_ram_rsp_width')),
 
-        Uses('caba:vci_dspin_initiator_wrapper', 
+        Uses('caba:vci_dspin_initiator_wrapper',
               cell_size          = parameter.Reference('vci_data_width_int'),
               dspin_cmd_width    = parameter.Reference('dspin_int_cmd_width'),
@@ -78,12 +78,12 @@
               dspin_rsp_width    = parameter.Reference('dspin_int_rsp_width')),
 
-        Uses('caba:virtual_dspin_router', 
+        Uses('caba:virtual_dspin_router',
               flit_width         = parameter.Reference('dspin_int_cmd_width')),
 
-        Uses('caba:virtual_dspin_router', 
+        Uses('caba:virtual_dspin_router',
               flit_width         = parameter.Reference('dspin_int_rsp_width')),
 
         # RAM network components
-        Uses('caba:vci_dspin_initiator_wrapper', 
+        Uses('caba:vci_dspin_initiator_wrapper',
               cell_size          = parameter.Reference('vci_data_width_ext'),
               dspin_cmd_width    = parameter.Reference('dspin_ram_cmd_width'),
@@ -95,8 +95,8 @@
               dspin_rsp_width    = parameter.Reference('dspin_ram_rsp_width')),
 
-        Uses('caba:dspin_router', 
+        Uses('caba:dspin_router',
               flit_width         = parameter.Reference('dspin_ram_cmd_width')),
 
-        Uses('caba:dspin_router', 
+        Uses('caba:dspin_router',
               flit_width         = parameter.Reference('dspin_ram_rsp_width')),
 
@@ -105,5 +105,5 @@
 
         # IOX network components
-        Uses('caba:vci_io_bridge', 
+        Uses('caba:vci_io_bridge',
               iob_cell_size_int  = parameter.Reference('vci_data_width_int'),
               iob_cell_size_ext  = parameter.Reference('vci_data_width_ext')),
@@ -114,20 +114,20 @@
         Port('caba:clock_in', 'p_clk', auto = 'clock'),
 
-        Port('caba:dspin_output', 'p_int_cmd_out', [4, 3], 
+        Port('caba:dspin_output', 'p_int_cmd_out', [4, 3],
               dspin_data_size = parameter.Reference('dspin_int_cmd_width')),
-        Port('caba:dspin_input', 'p_int_cmd_in', [4, 3], 
+        Port('caba:dspin_input', 'p_int_cmd_in', [4, 3],
               dspin_data_size = parameter.Reference('dspin_int_cmd_width')),
-        Port('caba:dspin_output', 'p_int_rsp_out', [4, 2], 
-              dspin_data_size = parameter.Reference('dspin_int_rsp_width')), 
-        Port('caba:dspin_input', 'p_int_rsp_in', [4, 2], 
+        Port('caba:dspin_output', 'p_int_rsp_out', [4, 2],
+              dspin_data_size = parameter.Reference('dspin_int_rsp_width')),
+        Port('caba:dspin_input', 'p_int_rsp_in', [4, 2],
               dspin_data_size = parameter.Reference('dspin_int_rsp_width')),
 
-        Port('caba:dspin_output', 'p_ram_cmd_out', [4], 
+        Port('caba:dspin_output', 'p_ram_cmd_out', [4],
               dspin_data_size = parameter.Reference('dspin_ram_cmd_width')),
-        Port('caba:dspin_input', 'p_ram_cmd_in', [4], 
+        Port('caba:dspin_input', 'p_ram_cmd_in', [4],
               dspin_data_size = parameter.Reference('dspin_ram_cmd_width')),
-        Port('caba:dspin_output', 'p_ram_rsp_out', [4], 
-              dspin_data_size = parameter.Reference('dspin_ram_rsp_width')), 
-        Port('caba:dspin_input', 'p_ram_rsp_in', [4], 
+        Port('caba:dspin_output', 'p_ram_rsp_out', [4],
+              dspin_data_size = parameter.Reference('dspin_ram_rsp_width')),
+        Port('caba:dspin_input', 'p_ram_rsp_in', [4],
               dspin_data_size = parameter.Reference('dspin_ram_rsp_width')),
         ],